Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
9b254dd1 DJ |
4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
123dc839 DJ |
43 | #include "target-descriptions.h" |
44 | #include "user-regs.h" | |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 AC |
53 | #include "gdb_assert.h" |
54 | ||
6529d2dd AC |
55 | static int arm_debug; |
56 | ||
082fc60d RE |
57 | /* Macros for setting and testing a bit in a minimal symbol that marks |
58 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 59 | is used for this purpose. |
082fc60d RE |
60 | |
61 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 62 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
63 | |
64 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
65 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
66 | | 0x80000000) | |
67 | ||
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
69 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
70 | ||
afd7eef0 RE |
71 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
72 | static struct cmd_list_element *setarmcmdlist = NULL; | |
73 | static struct cmd_list_element *showarmcmdlist = NULL; | |
74 | ||
fd50bc42 RE |
75 | /* The type of floating-point to use. Keep this in sync with enum |
76 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
77 | static const char *fp_model_strings[] = | |
78 | { | |
79 | "auto", | |
80 | "softfpa", | |
81 | "fpa", | |
82 | "softvfp", | |
28e97307 DJ |
83 | "vfp", |
84 | NULL | |
fd50bc42 RE |
85 | }; |
86 | ||
87 | /* A variable that can be configured by the user. */ | |
88 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
89 | static const char *current_fp_model = "auto"; | |
90 | ||
28e97307 DJ |
91 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
92 | static const char *arm_abi_strings[] = | |
93 | { | |
94 | "auto", | |
95 | "APCS", | |
96 | "AAPCS", | |
97 | NULL | |
98 | }; | |
99 | ||
100 | /* A variable that can be configured by the user. */ | |
101 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
102 | static const char *arm_abi_string = "auto"; | |
103 | ||
94c30b78 | 104 | /* Number of different reg name sets (options). */ |
afd7eef0 | 105 | static int num_disassembly_options; |
bc90b915 | 106 | |
123dc839 DJ |
107 | /* The standard register names, and all the valid aliases for them. */ |
108 | static const struct | |
109 | { | |
110 | const char *name; | |
111 | int regnum; | |
112 | } arm_register_aliases[] = { | |
113 | /* Basic register numbers. */ | |
114 | { "r0", 0 }, | |
115 | { "r1", 1 }, | |
116 | { "r2", 2 }, | |
117 | { "r3", 3 }, | |
118 | { "r4", 4 }, | |
119 | { "r5", 5 }, | |
120 | { "r6", 6 }, | |
121 | { "r7", 7 }, | |
122 | { "r8", 8 }, | |
123 | { "r9", 9 }, | |
124 | { "r10", 10 }, | |
125 | { "r11", 11 }, | |
126 | { "r12", 12 }, | |
127 | { "r13", 13 }, | |
128 | { "r14", 14 }, | |
129 | { "r15", 15 }, | |
130 | /* Synonyms (argument and variable registers). */ | |
131 | { "a1", 0 }, | |
132 | { "a2", 1 }, | |
133 | { "a3", 2 }, | |
134 | { "a4", 3 }, | |
135 | { "v1", 4 }, | |
136 | { "v2", 5 }, | |
137 | { "v3", 6 }, | |
138 | { "v4", 7 }, | |
139 | { "v5", 8 }, | |
140 | { "v6", 9 }, | |
141 | { "v7", 10 }, | |
142 | { "v8", 11 }, | |
143 | /* Other platform-specific names for r9. */ | |
144 | { "sb", 9 }, | |
145 | { "tr", 9 }, | |
146 | /* Special names. */ | |
147 | { "ip", 12 }, | |
148 | { "sp", 13 }, | |
149 | { "lr", 14 }, | |
150 | { "pc", 15 }, | |
151 | /* Names used by GCC (not listed in the ARM EABI). */ | |
152 | { "sl", 10 }, | |
153 | { "fp", 11 }, | |
154 | /* A special name from the older ATPCS. */ | |
155 | { "wr", 7 }, | |
156 | }; | |
bc90b915 | 157 | |
123dc839 | 158 | static const char *const arm_register_names[] = |
da59e081 JM |
159 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
160 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
161 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
162 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
163 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
164 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 165 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 166 | |
afd7eef0 RE |
167 | /* Valid register name styles. */ |
168 | static const char **valid_disassembly_styles; | |
ed9a39eb | 169 | |
afd7eef0 RE |
170 | /* Disassembly style to use. Default to "std" register names. */ |
171 | static const char *disassembly_style; | |
96baa820 | 172 | |
ed9a39eb | 173 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
174 | style. */ |
175 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 176 | struct cmd_list_element *); |
afd7eef0 | 177 | static void set_disassembly_style (void); |
ed9a39eb | 178 | |
b508a996 | 179 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 180 | void *, int); |
b508a996 | 181 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 182 | const void *, int); |
ed9a39eb | 183 | |
9b8d791a | 184 | struct arm_prologue_cache |
c3b4394c | 185 | { |
eb5492fa DJ |
186 | /* The stack pointer at the time this frame was created; i.e. the |
187 | caller's stack pointer when this function was called. It is used | |
188 | to identify this frame. */ | |
189 | CORE_ADDR prev_sp; | |
190 | ||
4be43953 DJ |
191 | /* The frame base for this frame is just prev_sp - frame size. |
192 | FRAMESIZE is the distance from the frame pointer to the | |
193 | initial stack pointer. */ | |
eb5492fa | 194 | |
c3b4394c | 195 | int framesize; |
eb5492fa DJ |
196 | |
197 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 198 | int framereg; |
eb5492fa DJ |
199 | |
200 | /* Saved register offsets. */ | |
201 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 202 | }; |
ed9a39eb | 203 | |
bc90b915 FN |
204 | /* Addresses for calling Thumb functions have the bit 0 set. |
205 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
206 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
207 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
208 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
209 | ||
94c30b78 | 210 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
211 | |
212 | int arm_apcs_32 = 1; | |
213 | ||
ed9a39eb JM |
214 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
215 | function. */ | |
c906108c | 216 | |
ad527d2e | 217 | static int |
2a451106 | 218 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 219 | { |
c5aa993b | 220 | struct minimal_symbol *sym; |
c906108c | 221 | |
ed9a39eb | 222 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
223 | if (IS_THUMB_ADDR (memaddr)) |
224 | return 1; | |
225 | ||
ed9a39eb | 226 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
227 | sym = lookup_minimal_symbol_by_pc (memaddr); |
228 | if (sym) | |
229 | { | |
c5aa993b | 230 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
231 | } |
232 | else | |
ed9a39eb JM |
233 | { |
234 | return 0; | |
235 | } | |
c906108c SS |
236 | } |
237 | ||
181c1381 | 238 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 239 | static CORE_ADDR |
ed9a39eb | 240 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 241 | { |
a3a2ee65 | 242 | if (arm_apcs_32) |
dd6be234 | 243 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 244 | else |
a3a2ee65 | 245 | return (val & 0x03fffffc); |
c906108c SS |
246 | } |
247 | ||
181c1381 RE |
248 | /* When reading symbols, we need to zap the low bit of the address, |
249 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 250 | static CORE_ADDR |
181c1381 RE |
251 | arm_smash_text_address (CORE_ADDR val) |
252 | { | |
253 | return val & ~1; | |
254 | } | |
255 | ||
29d73ae4 DJ |
256 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
257 | and frame pointer. Scan until we encounter a store that could | |
258 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
259 | |
260 | static CORE_ADDR | |
29d73ae4 DJ |
261 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
262 | CORE_ADDR start, CORE_ADDR limit, | |
263 | struct arm_prologue_cache *cache) | |
c906108c | 264 | { |
29d73ae4 DJ |
265 | int i; |
266 | pv_t regs[16]; | |
267 | struct pv_area *stack; | |
268 | struct cleanup *back_to; | |
269 | CORE_ADDR offset; | |
da3c6d4a | 270 | |
29d73ae4 DJ |
271 | for (i = 0; i < 16; i++) |
272 | regs[i] = pv_register (i, 0); | |
273 | stack = make_pv_area (ARM_SP_REGNUM); | |
274 | back_to = make_cleanup_free_pv_area (stack); | |
275 | ||
276 | /* The call instruction saved PC in LR, and the current PC is not | |
277 | interesting. Due to this file's conventions, we want the value | |
278 | of LR at this function's entry, not at the call site, so we do | |
279 | not record the save of the PC - when the ARM prologue analyzer | |
280 | has also been converted to the pv mechanism, we could record the | |
281 | save here and remove the hack in prev_register. */ | |
282 | regs[ARM_PC_REGNUM] = pv_unknown (); | |
283 | ||
284 | while (start < limit) | |
c906108c | 285 | { |
29d73ae4 DJ |
286 | unsigned short insn; |
287 | ||
288 | insn = read_memory_unsigned_integer (start, 2); | |
c906108c | 289 | |
94c30b78 | 290 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 291 | { |
29d73ae4 DJ |
292 | int regno; |
293 | int mask; | |
4be43953 DJ |
294 | |
295 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
296 | break; | |
29d73ae4 DJ |
297 | |
298 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
299 | whether to save LR (R14). */ | |
300 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
301 | ||
302 | /* Calculate offsets of saved R0-R7 and LR. */ | |
303 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
304 | if (mask & (1 << regno)) | |
305 | { | |
29d73ae4 DJ |
306 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
307 | -4); | |
308 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
309 | } | |
da59e081 | 310 | } |
da3c6d4a MS |
311 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
312 | sub sp, #simm */ | |
da59e081 | 313 | { |
29d73ae4 DJ |
314 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
315 | if (insn & 0x80) /* Check for SUB. */ | |
316 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
317 | -offset); | |
da59e081 | 318 | else |
29d73ae4 DJ |
319 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
320 | offset); | |
da59e081 JM |
321 | } |
322 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
323 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
324 | (insn & 0xff) << 2); | |
325 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 326 | { |
29d73ae4 DJ |
327 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
328 | int src_reg = (insn & 0x78) >> 3; | |
329 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 330 | } |
29d73ae4 | 331 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 332 | { |
29d73ae4 DJ |
333 | /* Handle stores to the stack. Normally pushes are used, |
334 | but with GCC -mtpcs-frame, there may be other stores | |
335 | in the prologue to create the frame. */ | |
336 | int regno = (insn >> 8) & 0x7; | |
337 | pv_t addr; | |
338 | ||
339 | offset = (insn & 0xff) << 2; | |
340 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
341 | ||
342 | if (pv_area_store_would_trash (stack, addr)) | |
343 | break; | |
344 | ||
345 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 346 | } |
29d73ae4 | 347 | else |
3d74b771 | 348 | { |
29d73ae4 DJ |
349 | /* We don't know what this instruction is. We're finished |
350 | scanning. NOTE: Recognizing more safe-to-ignore | |
351 | instructions here will improve support for optimized | |
352 | code. */ | |
da3c6d4a | 353 | break; |
3d74b771 | 354 | } |
29d73ae4 DJ |
355 | |
356 | start += 2; | |
c906108c SS |
357 | } |
358 | ||
29d73ae4 DJ |
359 | if (cache == NULL) |
360 | { | |
361 | do_cleanups (back_to); | |
362 | return start; | |
363 | } | |
364 | ||
29d73ae4 DJ |
365 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
366 | { | |
367 | /* Frame pointer is fp. Frame size is constant. */ | |
368 | cache->framereg = ARM_FP_REGNUM; | |
369 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
370 | } | |
371 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
372 | { | |
373 | /* Frame pointer is r7. Frame size is constant. */ | |
374 | cache->framereg = THUMB_FP_REGNUM; | |
375 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
376 | } | |
377 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
378 | { | |
379 | /* Try the stack pointer... this is a bit desperate. */ | |
380 | cache->framereg = ARM_SP_REGNUM; | |
381 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
382 | } | |
383 | else | |
384 | { | |
385 | /* We're just out of luck. We don't know where the frame is. */ | |
386 | cache->framereg = -1; | |
387 | cache->framesize = 0; | |
388 | } | |
389 | ||
390 | for (i = 0; i < 16; i++) | |
391 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
392 | cache->saved_regs[i].addr = offset; | |
393 | ||
394 | do_cleanups (back_to); | |
395 | return start; | |
c906108c SS |
396 | } |
397 | ||
da3c6d4a MS |
398 | /* Advance the PC across any function entry prologue instructions to |
399 | reach some "real" code. | |
34e8f22d RE |
400 | |
401 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 402 | prologue: |
c906108c | 403 | |
c5aa993b JM |
404 | mov ip, sp |
405 | [stmfd sp!, {a1,a2,a3,a4}] | |
406 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
407 | [stfe f7, [sp, #-12]!] |
408 | [stfe f6, [sp, #-12]!] | |
409 | [stfe f5, [sp, #-12]!] | |
410 | [stfe f4, [sp, #-12]!] | |
411 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 412 | |
34e8f22d | 413 | static CORE_ADDR |
6093d2eb | 414 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c SS |
415 | { |
416 | unsigned long inst; | |
417 | CORE_ADDR skip_pc; | |
b8d5e71d | 418 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 419 | char *func_name; |
c906108c SS |
420 | struct symtab_and_line sal; |
421 | ||
848cfffb | 422 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 423 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
424 | return pc; |
425 | ||
96baa820 | 426 | /* See what the symbol table says. */ |
ed9a39eb | 427 | |
50f6fb4b | 428 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 429 | { |
50f6fb4b CV |
430 | struct symbol *sym; |
431 | ||
432 | /* Found a function. */ | |
176620f1 | 433 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
434 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
435 | { | |
94c30b78 | 436 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
437 | sal = find_pc_line (func_addr, 0); |
438 | if ((sal.line != 0) && (sal.end < func_end)) | |
439 | return sal.end; | |
440 | } | |
c906108c SS |
441 | } |
442 | ||
c906108c | 443 | /* Can't find the prologue end in the symbol table, try it the hard way |
94c30b78 | 444 | by disassembling the instructions. */ |
c906108c | 445 | |
b8d5e71d MS |
446 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
447 | if (func_end == 0 || func_end > pc + 64) | |
448 | func_end = pc + 64; | |
c906108c | 449 | |
29d73ae4 DJ |
450 | /* Check if this is Thumb code. */ |
451 | if (arm_pc_is_thumb (pc)) | |
6093d2eb | 452 | return thumb_analyze_prologue (gdbarch, pc, func_end, NULL); |
29d73ae4 | 453 | |
b8d5e71d | 454 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 455 | { |
1c5bada0 | 456 | inst = read_memory_unsigned_integer (skip_pc, 4); |
f43845b3 | 457 | |
b8d5e71d MS |
458 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
459 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
460 | continue; | |
c906108c | 461 | |
28cd8767 JG |
462 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
463 | continue; | |
464 | ||
465 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
466 | continue; | |
467 | ||
b8d5e71d MS |
468 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
469 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
470 | continue; | |
c906108c | 471 | |
b8d5e71d MS |
472 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
473 | continue; | |
c906108c | 474 | |
b8d5e71d MS |
475 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
476 | continue; | |
11d3b27d | 477 | |
b8d5e71d MS |
478 | /* Any insns after this point may float into the code, if it makes |
479 | for better instruction scheduling, so we skip them only if we | |
480 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 481 | |
b8d5e71d MS |
482 | /* We may have either one sfmfd instruction here, or several stfe |
483 | insns, depending on the version of floating point code we | |
484 | support. */ | |
485 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
486 | continue; | |
487 | ||
488 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
489 | continue; | |
490 | ||
491 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
492 | continue; | |
493 | ||
494 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
495 | continue; | |
496 | ||
497 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
498 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
499 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
500 | continue; | |
501 | ||
502 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
503 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
504 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
505 | continue; | |
506 | ||
507 | /* Un-recognized instruction; stop scanning. */ | |
508 | break; | |
f43845b3 | 509 | } |
c906108c | 510 | |
b8d5e71d | 511 | return skip_pc; /* End of prologue */ |
c906108c | 512 | } |
94c30b78 | 513 | |
c5aa993b | 514 | /* *INDENT-OFF* */ |
c906108c SS |
515 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
516 | This function decodes a Thumb function prologue to determine: | |
517 | 1) the size of the stack frame | |
518 | 2) which registers are saved on it | |
519 | 3) the offsets of saved regs | |
520 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 521 | |
da59e081 JM |
522 | A typical Thumb function prologue would create this stack frame |
523 | (offsets relative to FP) | |
c906108c SS |
524 | old SP -> 24 stack parameters |
525 | 20 LR | |
526 | 16 R7 | |
527 | R7 -> 0 local variables (16 bytes) | |
528 | SP -> -12 additional stack space (12 bytes) | |
529 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
530 | 12 bytes. The frame register is R7. |
531 | ||
da3c6d4a MS |
532 | The comments for thumb_skip_prolog() describe the algorithm we use |
533 | to detect the end of the prolog. */ | |
c5aa993b JM |
534 | /* *INDENT-ON* */ |
535 | ||
c906108c | 536 | static void |
be8626e0 MD |
537 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
538 | struct arm_prologue_cache *cache) | |
c906108c SS |
539 | { |
540 | CORE_ADDR prologue_start; | |
541 | CORE_ADDR prologue_end; | |
542 | CORE_ADDR current_pc; | |
94c30b78 | 543 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
544 | int saved_reg[16]; |
545 | /* findmask: | |
546 | bit 0 - push { rlist } | |
547 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
548 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
549 | */ | |
550 | int findmask = 0; | |
c5aa993b | 551 | int i; |
c906108c | 552 | |
eb5492fa | 553 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
554 | { |
555 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
556 | ||
94c30b78 | 557 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 558 | prologue_end = prev_pc; |
c906108c | 559 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 560 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
561 | } |
562 | else | |
f7060f85 DJ |
563 | /* We're in the boondocks: we have no idea where the start of the |
564 | function is. */ | |
565 | return; | |
c906108c | 566 | |
eb5492fa | 567 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 568 | |
be8626e0 | 569 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
570 | } |
571 | ||
ed9a39eb | 572 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
573 | 1) the size of the stack frame |
574 | 2) which registers are saved on it | |
575 | 3) the offsets of saved regs | |
576 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
577 | This information is stored in the "extra" fields of the frame_info. |
578 | ||
96baa820 JM |
579 | There are two basic forms for the ARM prologue. The fixed argument |
580 | function call will look like: | |
ed9a39eb JM |
581 | |
582 | mov ip, sp | |
583 | stmfd sp!, {fp, ip, lr, pc} | |
584 | sub fp, ip, #4 | |
585 | [sub sp, sp, #4] | |
96baa820 | 586 | |
c906108c | 587 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
588 | IP -> 4 (caller's stack) |
589 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
590 | -4 LR (return address in caller) | |
591 | -8 IP (copy of caller's SP) | |
592 | -12 FP (caller's FP) | |
593 | SP -> -28 Local variables | |
594 | ||
c906108c | 595 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
596 | 28 bytes. The stmfd call can also save any of the vN registers it |
597 | plans to use, which increases the frame size accordingly. | |
598 | ||
599 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
600 | because the ARM Store instructions always store PC + 8 when you read | |
601 | the PC register. | |
ed9a39eb | 602 | |
96baa820 JM |
603 | A variable argument function call will look like: |
604 | ||
ed9a39eb JM |
605 | mov ip, sp |
606 | stmfd sp!, {a1, a2, a3, a4} | |
607 | stmfd sp!, {fp, ip, lr, pc} | |
608 | sub fp, ip, #20 | |
609 | ||
96baa820 | 610 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
611 | IP -> 20 (caller's stack) |
612 | 16 A4 | |
613 | 12 A3 | |
614 | 8 A2 | |
615 | 4 A1 | |
616 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
617 | -4 LR (return address in caller) | |
618 | -8 IP (copy of caller's SP) | |
619 | -12 FP (caller's FP) | |
620 | SP -> -28 Local variables | |
96baa820 JM |
621 | |
622 | The frame size would thus be 48 bytes, and the frame offset would be | |
623 | 28 bytes. | |
624 | ||
625 | There is another potential complication, which is that the optimizer | |
626 | will try to separate the store of fp in the "stmfd" instruction from | |
627 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
628 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
629 | ||
630 | Also, note, the original version of the ARM toolchain claimed that there | |
631 | should be an | |
632 | ||
633 | instruction at the end of the prologue. I have never seen GCC produce | |
634 | this, and the ARM docs don't mention it. We still test for it below in | |
635 | case it happens... | |
ed9a39eb JM |
636 | |
637 | */ | |
c906108c SS |
638 | |
639 | static void | |
2af46ca0 UW |
640 | arm_scan_prologue (struct frame_info *next_frame, |
641 | struct arm_prologue_cache *cache) | |
c906108c | 642 | { |
2af46ca0 | 643 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
4be43953 | 644 | int regno; |
c906108c | 645 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 646 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
4be43953 DJ |
647 | pv_t regs[ARM_FPS_REGNUM]; |
648 | struct pv_area *stack; | |
649 | struct cleanup *back_to; | |
650 | CORE_ADDR offset; | |
c906108c | 651 | |
c906108c | 652 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
653 | cache->framereg = ARM_SP_REGNUM; |
654 | cache->framesize = 0; | |
c906108c SS |
655 | |
656 | /* Check for Thumb prologue. */ | |
eb5492fa | 657 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 658 | { |
be8626e0 | 659 | thumb_scan_prologue (gdbarch, prev_pc, cache); |
c906108c SS |
660 | return; |
661 | } | |
662 | ||
663 | /* Find the function prologue. If we can't find the function in | |
664 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 665 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 666 | { |
2a451106 KB |
667 | /* One way to find the end of the prologue (which works well |
668 | for unoptimized code) is to do the following: | |
669 | ||
670 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
671 | ||
672 | if (sal.line == 0) | |
eb5492fa | 673 | prologue_end = prev_pc; |
2a451106 KB |
674 | else if (sal.end < prologue_end) |
675 | prologue_end = sal.end; | |
676 | ||
677 | This mechanism is very accurate so long as the optimizer | |
678 | doesn't move any instructions from the function body into the | |
679 | prologue. If this happens, sal.end will be the last | |
680 | instruction in the first hunk of prologue code just before | |
681 | the first instruction that the scheduler has moved from | |
682 | the body to the prologue. | |
683 | ||
684 | In order to make sure that we scan all of the prologue | |
685 | instructions, we use a slightly less accurate mechanism which | |
686 | may scan more than necessary. To help compensate for this | |
687 | lack of accuracy, the prologue scanning loop below contains | |
688 | several clauses which'll cause the loop to terminate early if | |
689 | an implausible prologue instruction is encountered. | |
690 | ||
691 | The expression | |
692 | ||
693 | prologue_start + 64 | |
694 | ||
695 | is a suitable endpoint since it accounts for the largest | |
696 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 697 | the scheduler. */ |
2a451106 KB |
698 | |
699 | if (prologue_end > prologue_start + 64) | |
700 | { | |
94c30b78 | 701 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 702 | } |
c906108c SS |
703 | } |
704 | else | |
705 | { | |
eb5492fa DJ |
706 | /* We have no symbol information. Our only option is to assume this |
707 | function has a standard stack frame and the normal frame register. | |
708 | Then, we can find the value of our frame pointer on entrance to | |
709 | the callee (or at the present moment if this is the innermost frame). | |
710 | The value stored there should be the address of the stmfd + 8. */ | |
711 | CORE_ADDR frame_loc; | |
712 | LONGEST return_value; | |
713 | ||
714 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
715 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
716 | return; |
717 | else | |
718 | { | |
bf6ae464 | 719 | prologue_start = gdbarch_addr_bits_remove |
2af46ca0 | 720 | (gdbarch, return_value) - 8; |
94c30b78 | 721 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 722 | } |
c906108c SS |
723 | } |
724 | ||
eb5492fa DJ |
725 | if (prev_pc < prologue_end) |
726 | prologue_end = prev_pc; | |
727 | ||
c906108c | 728 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 729 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 730 | |
96baa820 JM |
731 | Be careful, however, and if it doesn't look like a prologue, |
732 | don't try to scan it. If, for instance, a frameless function | |
733 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 734 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
735 | and other operations that rely on a knowledge of the stack |
736 | traceback. | |
737 | ||
738 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 739 | if we don't see this as the first insn, we will stop. |
c906108c | 740 | |
f43845b3 MS |
741 | [Note: This doesn't seem to be true any longer, so it's now an |
742 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 743 | |
f43845b3 MS |
744 | [Note further: The "mov ip,sp" only seems to be missing in |
745 | frameless functions at optimization level "-O2" or above, | |
746 | in which case it is often (but not always) replaced by | |
b8d5e71d | 747 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 748 | |
4be43953 DJ |
749 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
750 | regs[regno] = pv_register (regno, 0); | |
751 | stack = make_pv_area (ARM_SP_REGNUM); | |
752 | back_to = make_cleanup_free_pv_area (stack); | |
753 | ||
754 | regs[ARM_PC_REGNUM] = pv_unknown (); | |
f43845b3 | 755 | |
94c30b78 MS |
756 | for (current_pc = prologue_start; |
757 | current_pc < prologue_end; | |
f43845b3 | 758 | current_pc += 4) |
96baa820 | 759 | { |
d4473757 KB |
760 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
761 | ||
94c30b78 | 762 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 763 | { |
4be43953 | 764 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
765 | continue; |
766 | } | |
767 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
768 | { | |
769 | unsigned imm = insn & 0xff; /* immediate value */ | |
770 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
771 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 772 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
28cd8767 JG |
773 | continue; |
774 | } | |
775 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
776 | { | |
777 | unsigned imm = insn & 0xff; /* immediate value */ | |
778 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
779 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 780 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
f43845b3 MS |
781 | continue; |
782 | } | |
94c30b78 | 783 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 784 | { |
4be43953 DJ |
785 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
786 | break; | |
787 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
788 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); | |
f43845b3 MS |
789 | continue; |
790 | } | |
791 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
792 | /* stmfd sp!, {..., fp, ip, lr, pc} |
793 | or | |
794 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 795 | { |
d4473757 | 796 | int mask = insn & 0xffff; |
ed9a39eb | 797 | |
4be43953 DJ |
798 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
799 | break; | |
800 | ||
94c30b78 | 801 | /* Calculate offsets of saved registers. */ |
34e8f22d | 802 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
803 | if (mask & (1 << regno)) |
804 | { | |
4be43953 DJ |
805 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
806 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
d4473757 KB |
807 | } |
808 | } | |
b8d5e71d MS |
809 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
810 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
811 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
812 | { | |
813 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
814 | continue; | |
815 | } | |
816 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
817 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
818 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
819 | { |
820 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
821 | continue; | |
822 | } | |
d4473757 KB |
823 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
824 | { | |
94c30b78 MS |
825 | unsigned imm = insn & 0xff; /* immediate value */ |
826 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 827 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 828 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
829 | } |
830 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
831 | { | |
94c30b78 MS |
832 | unsigned imm = insn & 0xff; /* immediate value */ |
833 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 834 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 835 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 836 | } |
ff6f572f | 837 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
2af46ca0 | 838 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 839 | { |
4be43953 DJ |
840 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
841 | break; | |
842 | ||
843 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 844 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 845 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 846 | } |
ff6f572f | 847 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
2af46ca0 | 848 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
849 | { |
850 | int n_saved_fp_regs; | |
851 | unsigned int fp_start_reg, fp_bound_reg; | |
852 | ||
4be43953 DJ |
853 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
854 | break; | |
855 | ||
94c30b78 | 856 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 857 | { |
d4473757 KB |
858 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
859 | n_saved_fp_regs = 3; | |
860 | else | |
861 | n_saved_fp_regs = 1; | |
96baa820 | 862 | } |
d4473757 | 863 | else |
96baa820 | 864 | { |
d4473757 KB |
865 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
866 | n_saved_fp_regs = 2; | |
867 | else | |
868 | n_saved_fp_regs = 4; | |
96baa820 | 869 | } |
d4473757 | 870 | |
34e8f22d | 871 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
872 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
873 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 874 | { |
4be43953 DJ |
875 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
876 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
877 | regs[fp_start_reg++]); | |
96baa820 | 878 | } |
c906108c | 879 | } |
d4473757 | 880 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 881 | break; /* Condition not true, exit early */ |
b8d5e71d | 882 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 883 | break; /* Don't scan past a block load */ |
d4473757 KB |
884 | else |
885 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 886 | so we just skip what we don't recognize. */ |
d4473757 | 887 | continue; |
c906108c SS |
888 | } |
889 | ||
4be43953 DJ |
890 | /* The frame size is just the distance from the frame register |
891 | to the original stack pointer. */ | |
892 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
893 | { | |
894 | /* Frame pointer is fp. */ | |
895 | cache->framereg = ARM_FP_REGNUM; | |
896 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
897 | } | |
898 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
899 | { | |
900 | /* Try the stack pointer... this is a bit desperate. */ | |
901 | cache->framereg = ARM_SP_REGNUM; | |
902 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
903 | } | |
d4473757 | 904 | else |
4be43953 DJ |
905 | { |
906 | /* We're just out of luck. We don't know where the frame is. */ | |
907 | cache->framereg = -1; | |
908 | cache->framesize = 0; | |
909 | } | |
910 | ||
911 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
912 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
913 | cache->saved_regs[regno].addr = offset; | |
914 | ||
915 | do_cleanups (back_to); | |
c906108c SS |
916 | } |
917 | ||
eb5492fa DJ |
918 | static struct arm_prologue_cache * |
919 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 920 | { |
eb5492fa DJ |
921 | int reg; |
922 | struct arm_prologue_cache *cache; | |
923 | CORE_ADDR unwound_fp; | |
c5aa993b | 924 | |
35d5d4ee | 925 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
eb5492fa | 926 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
c906108c | 927 | |
eb5492fa | 928 | arm_scan_prologue (next_frame, cache); |
848cfffb | 929 | |
eb5492fa DJ |
930 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
931 | if (unwound_fp == 0) | |
932 | return cache; | |
c906108c | 933 | |
4be43953 | 934 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 935 | |
eb5492fa DJ |
936 | /* Calculate actual addresses of saved registers using offsets |
937 | determined by arm_scan_prologue. */ | |
2af46ca0 | 938 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (next_frame)); reg++) |
e28a332c | 939 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
940 | cache->saved_regs[reg].addr += cache->prev_sp; |
941 | ||
942 | return cache; | |
c906108c SS |
943 | } |
944 | ||
eb5492fa DJ |
945 | /* Our frame ID for a normal frame is the current function's starting PC |
946 | and the caller's SP when we were called. */ | |
c906108c | 947 | |
148754e5 | 948 | static void |
eb5492fa DJ |
949 | arm_prologue_this_id (struct frame_info *next_frame, |
950 | void **this_cache, | |
951 | struct frame_id *this_id) | |
c906108c | 952 | { |
eb5492fa DJ |
953 | struct arm_prologue_cache *cache; |
954 | struct frame_id id; | |
955 | CORE_ADDR func; | |
f079148d | 956 | |
eb5492fa DJ |
957 | if (*this_cache == NULL) |
958 | *this_cache = arm_make_prologue_cache (next_frame); | |
959 | cache = *this_cache; | |
2a451106 | 960 | |
93d42b30 | 961 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
2a451106 | 962 | |
eb5492fa DJ |
963 | /* This is meant to halt the backtrace at "_start". Make sure we |
964 | don't halt it at a generic dummy frame. */ | |
2301df11 | 965 | if (func <= gdbarch_tdep (get_frame_arch (next_frame))->lowest_pc) |
eb5492fa | 966 | return; |
5a203e44 | 967 | |
eb5492fa DJ |
968 | /* If we've hit a wall, stop. */ |
969 | if (cache->prev_sp == 0) | |
970 | return; | |
24de872b | 971 | |
eb5492fa | 972 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 973 | *this_id = id; |
c906108c SS |
974 | } |
975 | ||
eb5492fa DJ |
976 | static void |
977 | arm_prologue_prev_register (struct frame_info *next_frame, | |
978 | void **this_cache, | |
979 | int prev_regnum, | |
980 | int *optimized, | |
981 | enum lval_type *lvalp, | |
982 | CORE_ADDR *addrp, | |
983 | int *realnump, | |
9af75ef6 | 984 | gdb_byte *valuep) |
24de872b DJ |
985 | { |
986 | struct arm_prologue_cache *cache; | |
987 | ||
eb5492fa DJ |
988 | if (*this_cache == NULL) |
989 | *this_cache = arm_make_prologue_cache (next_frame); | |
990 | cache = *this_cache; | |
24de872b | 991 | |
eb5492fa DJ |
992 | /* If we are asked to unwind the PC, then we need to return the LR |
993 | instead. The saved value of PC points into this frame's | |
994 | prologue, not the next frame's resume location. */ | |
995 | if (prev_regnum == ARM_PC_REGNUM) | |
996 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 997 | |
eb5492fa DJ |
998 | /* SP is generally not saved to the stack, but this frame is |
999 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
1000 | The value was already reconstructed into PREV_SP. */ | |
1001 | if (prev_regnum == ARM_SP_REGNUM) | |
1002 | { | |
1003 | *lvalp = not_lval; | |
1004 | if (valuep) | |
1005 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
1006 | return; | |
1007 | } | |
1008 | ||
1f67027d AC |
1009 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
1010 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
1011 | } |
1012 | ||
1013 | struct frame_unwind arm_prologue_unwind = { | |
1014 | NORMAL_FRAME, | |
1015 | arm_prologue_this_id, | |
1016 | arm_prologue_prev_register | |
1017 | }; | |
1018 | ||
1019 | static const struct frame_unwind * | |
1020 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
1021 | { | |
1022 | return &arm_prologue_unwind; | |
24de872b DJ |
1023 | } |
1024 | ||
909cf6ea DJ |
1025 | static struct arm_prologue_cache * |
1026 | arm_make_stub_cache (struct frame_info *next_frame) | |
1027 | { | |
1028 | int reg; | |
1029 | struct arm_prologue_cache *cache; | |
1030 | CORE_ADDR unwound_fp; | |
1031 | ||
35d5d4ee | 1032 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
909cf6ea DJ |
1033 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
1034 | ||
1035 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
1036 | ||
1037 | return cache; | |
1038 | } | |
1039 | ||
1040 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1041 | ||
1042 | static void | |
1043 | arm_stub_this_id (struct frame_info *next_frame, | |
1044 | void **this_cache, | |
1045 | struct frame_id *this_id) | |
1046 | { | |
1047 | struct arm_prologue_cache *cache; | |
1048 | ||
1049 | if (*this_cache == NULL) | |
1050 | *this_cache = arm_make_stub_cache (next_frame); | |
1051 | cache = *this_cache; | |
1052 | ||
1053 | *this_id = frame_id_build (cache->prev_sp, | |
1054 | frame_pc_unwind (next_frame)); | |
1055 | } | |
1056 | ||
1057 | struct frame_unwind arm_stub_unwind = { | |
1058 | NORMAL_FRAME, | |
1059 | arm_stub_this_id, | |
1060 | arm_prologue_prev_register | |
1061 | }; | |
1062 | ||
1063 | static const struct frame_unwind * | |
1064 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1065 | { | |
93d42b30 | 1066 | CORE_ADDR addr_in_block; |
909cf6ea DJ |
1067 | char dummy[4]; |
1068 | ||
93d42b30 DJ |
1069 | addr_in_block = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
1070 | if (in_plt_section (addr_in_block, NULL) | |
909cf6ea DJ |
1071 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) |
1072 | return &arm_stub_unwind; | |
1073 | ||
1074 | return NULL; | |
1075 | } | |
1076 | ||
24de872b | 1077 | static CORE_ADDR |
eb5492fa | 1078 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1079 | { |
1080 | struct arm_prologue_cache *cache; | |
1081 | ||
eb5492fa DJ |
1082 | if (*this_cache == NULL) |
1083 | *this_cache = arm_make_prologue_cache (next_frame); | |
1084 | cache = *this_cache; | |
1085 | ||
4be43953 | 1086 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
1087 | } |
1088 | ||
eb5492fa DJ |
1089 | struct frame_base arm_normal_base = { |
1090 | &arm_prologue_unwind, | |
1091 | arm_normal_frame_base, | |
1092 | arm_normal_frame_base, | |
1093 | arm_normal_frame_base | |
1094 | }; | |
1095 | ||
eb5492fa DJ |
1096 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1097 | dummy frame. The frame ID's base needs to match the TOS value | |
1098 | saved by save_dummy_frame_tos() and returned from | |
1099 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1100 | breakpoint. */ | |
c906108c | 1101 | |
eb5492fa DJ |
1102 | static struct frame_id |
1103 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1104 | { |
eb5492fa DJ |
1105 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1106 | frame_pc_unwind (next_frame)); | |
1107 | } | |
c3b4394c | 1108 | |
eb5492fa DJ |
1109 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1110 | be used to construct the previous frame's ID, after looking up the | |
1111 | containing function). */ | |
c3b4394c | 1112 | |
eb5492fa DJ |
1113 | static CORE_ADDR |
1114 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1115 | { | |
1116 | CORE_ADDR pc; | |
1117 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
59ea4f70 | 1118 | return arm_addr_bits_remove (pc); |
eb5492fa DJ |
1119 | } |
1120 | ||
1121 | static CORE_ADDR | |
1122 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1123 | { | |
1124 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1125 | } |
1126 | ||
2dd604e7 RE |
1127 | /* When arguments must be pushed onto the stack, they go on in reverse |
1128 | order. The code below implements a FILO (stack) to do this. */ | |
1129 | ||
1130 | struct stack_item | |
1131 | { | |
1132 | int len; | |
1133 | struct stack_item *prev; | |
1134 | void *data; | |
1135 | }; | |
1136 | ||
1137 | static struct stack_item * | |
1138 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1139 | { | |
1140 | struct stack_item *si; | |
1141 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1142 | si->data = xmalloc (len); |
2dd604e7 RE |
1143 | si->len = len; |
1144 | si->prev = prev; | |
1145 | memcpy (si->data, contents, len); | |
1146 | return si; | |
1147 | } | |
1148 | ||
1149 | static struct stack_item * | |
1150 | pop_stack_item (struct stack_item *si) | |
1151 | { | |
1152 | struct stack_item *dead = si; | |
1153 | si = si->prev; | |
1154 | xfree (dead->data); | |
1155 | xfree (dead); | |
1156 | return si; | |
1157 | } | |
1158 | ||
2af48f68 PB |
1159 | |
1160 | /* Return the alignment (in bytes) of the given type. */ | |
1161 | ||
1162 | static int | |
1163 | arm_type_align (struct type *t) | |
1164 | { | |
1165 | int n; | |
1166 | int align; | |
1167 | int falign; | |
1168 | ||
1169 | t = check_typedef (t); | |
1170 | switch (TYPE_CODE (t)) | |
1171 | { | |
1172 | default: | |
1173 | /* Should never happen. */ | |
1174 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1175 | return 4; | |
1176 | ||
1177 | case TYPE_CODE_PTR: | |
1178 | case TYPE_CODE_ENUM: | |
1179 | case TYPE_CODE_INT: | |
1180 | case TYPE_CODE_FLT: | |
1181 | case TYPE_CODE_SET: | |
1182 | case TYPE_CODE_RANGE: | |
1183 | case TYPE_CODE_BITSTRING: | |
1184 | case TYPE_CODE_REF: | |
1185 | case TYPE_CODE_CHAR: | |
1186 | case TYPE_CODE_BOOL: | |
1187 | return TYPE_LENGTH (t); | |
1188 | ||
1189 | case TYPE_CODE_ARRAY: | |
1190 | case TYPE_CODE_COMPLEX: | |
1191 | /* TODO: What about vector types? */ | |
1192 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1193 | ||
1194 | case TYPE_CODE_STRUCT: | |
1195 | case TYPE_CODE_UNION: | |
1196 | align = 1; | |
1197 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1198 | { | |
1199 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1200 | if (falign > align) | |
1201 | align = falign; | |
1202 | } | |
1203 | return align; | |
1204 | } | |
1205 | } | |
1206 | ||
2dd604e7 RE |
1207 | /* We currently only support passing parameters in integer registers. This |
1208 | conforms with GCC's default model. Several other variants exist and | |
1209 | we should probably support some of them based on the selected ABI. */ | |
1210 | ||
1211 | static CORE_ADDR | |
7d9b040b | 1212 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1213 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1214 | struct value **args, CORE_ADDR sp, int struct_return, | |
1215 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1216 | { |
1217 | int argnum; | |
1218 | int argreg; | |
1219 | int nstack; | |
1220 | struct stack_item *si = NULL; | |
1221 | ||
6a65450a AC |
1222 | /* Set the return address. For the ARM, the return breakpoint is |
1223 | always at BP_ADDR. */ | |
2dd604e7 | 1224 | /* XXX Fix for Thumb. */ |
6a65450a | 1225 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1226 | |
1227 | /* Walk through the list of args and determine how large a temporary | |
1228 | stack is required. Need to take care here as structs may be | |
1229 | passed on the stack, and we have to to push them. */ | |
1230 | nstack = 0; | |
1231 | ||
1232 | argreg = ARM_A1_REGNUM; | |
1233 | nstack = 0; | |
1234 | ||
2dd604e7 RE |
1235 | /* The struct_return pointer occupies the first parameter |
1236 | passing register. */ | |
1237 | if (struct_return) | |
1238 | { | |
1239 | if (arm_debug) | |
1240 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
2af46ca0 | 1241 | gdbarch_register_name (gdbarch, argreg), |
c9f4d572 | 1242 | paddr (struct_addr)); |
2dd604e7 RE |
1243 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
1244 | argreg++; | |
1245 | } | |
1246 | ||
1247 | for (argnum = 0; argnum < nargs; argnum++) | |
1248 | { | |
1249 | int len; | |
1250 | struct type *arg_type; | |
1251 | struct type *target_type; | |
1252 | enum type_code typecode; | |
0fd88904 | 1253 | bfd_byte *val; |
2af48f68 | 1254 | int align; |
2dd604e7 | 1255 | |
df407dfe | 1256 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1257 | len = TYPE_LENGTH (arg_type); |
1258 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1259 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1260 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1261 | |
2af48f68 PB |
1262 | align = arm_type_align (arg_type); |
1263 | /* Round alignment up to a whole number of words. */ | |
1264 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1265 | /* Different ABIs have different maximum alignments. */ | |
1266 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1267 | { | |
1268 | /* The APCS ABI only requires word alignment. */ | |
1269 | align = INT_REGISTER_SIZE; | |
1270 | } | |
1271 | else | |
1272 | { | |
1273 | /* The AAPCS requires at most doubleword alignment. */ | |
1274 | if (align > INT_REGISTER_SIZE * 2) | |
1275 | align = INT_REGISTER_SIZE * 2; | |
1276 | } | |
1277 | ||
1278 | /* Push stack padding for dowubleword alignment. */ | |
1279 | if (nstack & (align - 1)) | |
1280 | { | |
1281 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1282 | nstack += INT_REGISTER_SIZE; | |
1283 | } | |
1284 | ||
1285 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1286 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1287 | && align > INT_REGISTER_SIZE | |
1288 | && argreg & 1) | |
1289 | argreg++; | |
1290 | ||
2dd604e7 RE |
1291 | /* If the argument is a pointer to a function, and it is a |
1292 | Thumb function, create a LOCAL copy of the value and set | |
1293 | the THUMB bit in it. */ | |
1294 | if (TYPE_CODE_PTR == typecode | |
1295 | && target_type != NULL | |
1296 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1297 | { | |
7c0b4a20 | 1298 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1299 | if (arm_pc_is_thumb (regval)) |
1300 | { | |
1301 | val = alloca (len); | |
fbd9dcd3 | 1302 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1303 | } |
1304 | } | |
1305 | ||
1306 | /* Copy the argument to general registers or the stack in | |
1307 | register-sized pieces. Large arguments are split between | |
1308 | registers and stack. */ | |
1309 | while (len > 0) | |
1310 | { | |
f0c9063c | 1311 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 RE |
1312 | |
1313 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1314 | { | |
1315 | /* The argument is being passed in a general purpose | |
1316 | register. */ | |
7c0b4a20 | 1317 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2af46ca0 | 1318 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
8bf8793c | 1319 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
1320 | if (arm_debug) |
1321 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
1322 | argnum, |
1323 | gdbarch_register_name | |
2af46ca0 | 1324 | (gdbarch, argreg), |
f0c9063c | 1325 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
1326 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1327 | argreg++; | |
1328 | } | |
1329 | else | |
1330 | { | |
1331 | /* Push the arguments onto the stack. */ | |
1332 | if (arm_debug) | |
1333 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1334 | argnum, nstack); | |
f0c9063c UW |
1335 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
1336 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
1337 | } |
1338 | ||
1339 | len -= partial_len; | |
1340 | val += partial_len; | |
1341 | } | |
1342 | } | |
1343 | /* If we have an odd number of words to push, then decrement the stack | |
1344 | by one word now, so first stack argument will be dword aligned. */ | |
1345 | if (nstack & 4) | |
1346 | sp -= 4; | |
1347 | ||
1348 | while (si) | |
1349 | { | |
1350 | sp -= si->len; | |
1351 | write_memory (sp, si->data, si->len); | |
1352 | si = pop_stack_item (si); | |
1353 | } | |
1354 | ||
1355 | /* Finally, update teh SP register. */ | |
1356 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1357 | ||
1358 | return sp; | |
1359 | } | |
1360 | ||
f53f0d0b PB |
1361 | |
1362 | /* Always align the frame to an 8-byte boundary. This is required on | |
1363 | some platforms and harmless on the rest. */ | |
1364 | ||
1365 | static CORE_ADDR | |
1366 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1367 | { | |
1368 | /* Align the stack to eight bytes. */ | |
1369 | return sp & ~ (CORE_ADDR) 7; | |
1370 | } | |
1371 | ||
c906108c | 1372 | static void |
ed9a39eb | 1373 | print_fpu_flags (int flags) |
c906108c | 1374 | { |
c5aa993b JM |
1375 | if (flags & (1 << 0)) |
1376 | fputs ("IVO ", stdout); | |
1377 | if (flags & (1 << 1)) | |
1378 | fputs ("DVZ ", stdout); | |
1379 | if (flags & (1 << 2)) | |
1380 | fputs ("OFL ", stdout); | |
1381 | if (flags & (1 << 3)) | |
1382 | fputs ("UFL ", stdout); | |
1383 | if (flags & (1 << 4)) | |
1384 | fputs ("INX ", stdout); | |
1385 | putchar ('\n'); | |
c906108c SS |
1386 | } |
1387 | ||
5e74b15c RE |
1388 | /* Print interesting information about the floating point processor |
1389 | (if present) or emulator. */ | |
34e8f22d | 1390 | static void |
d855c300 | 1391 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1392 | struct frame_info *frame, const char *args) |
c906108c | 1393 | { |
9c9acae0 | 1394 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
1395 | int type; |
1396 | ||
1397 | type = (status >> 24) & 127; | |
edefbb7c AC |
1398 | if (status & (1 << 31)) |
1399 | printf (_("Hardware FPU type %d\n"), type); | |
1400 | else | |
1401 | printf (_("Software FPU type %d\n"), type); | |
1402 | /* i18n: [floating point unit] mask */ | |
1403 | fputs (_("mask: "), stdout); | |
c5aa993b | 1404 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1405 | /* i18n: [floating point unit] flags */ |
1406 | fputs (_("flags: "), stdout); | |
c5aa993b | 1407 | print_fpu_flags (status); |
c906108c SS |
1408 | } |
1409 | ||
34e8f22d RE |
1410 | /* Return the GDB type object for the "standard" data type of data in |
1411 | register N. */ | |
1412 | ||
1413 | static struct type * | |
7a5ea0d4 | 1414 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1415 | { |
34e8f22d | 1416 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
8da61cc4 | 1417 | return builtin_type_arm_ext; |
e4c16157 DJ |
1418 | else if (regnum == ARM_SP_REGNUM) |
1419 | return builtin_type_void_data_ptr; | |
1420 | else if (regnum == ARM_PC_REGNUM) | |
1421 | return builtin_type_void_func_ptr; | |
ff6f572f DJ |
1422 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
1423 | /* These registers are only supported on targets which supply | |
1424 | an XML description. */ | |
1425 | return builtin_type_int0; | |
032758dc | 1426 | else |
e4c16157 | 1427 | return builtin_type_uint32; |
032758dc AC |
1428 | } |
1429 | ||
ff6f572f DJ |
1430 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
1431 | number. */ | |
1432 | ||
1433 | static int | |
d3f73121 | 1434 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
1435 | { |
1436 | /* Core integer regs. */ | |
1437 | if (reg >= 0 && reg <= 15) | |
1438 | return reg; | |
1439 | ||
1440 | /* Legacy FPA encoding. These were once used in a way which | |
1441 | overlapped with VFP register numbering, so their use is | |
1442 | discouraged, but GDB doesn't support the ARM toolchain | |
1443 | which used them for VFP. */ | |
1444 | if (reg >= 16 && reg <= 23) | |
1445 | return ARM_F0_REGNUM + reg - 16; | |
1446 | ||
1447 | /* New assignments for the FPA registers. */ | |
1448 | if (reg >= 96 && reg <= 103) | |
1449 | return ARM_F0_REGNUM + reg - 96; | |
1450 | ||
1451 | /* WMMX register assignments. */ | |
1452 | if (reg >= 104 && reg <= 111) | |
1453 | return ARM_WCGR0_REGNUM + reg - 104; | |
1454 | ||
1455 | if (reg >= 112 && reg <= 127) | |
1456 | return ARM_WR0_REGNUM + reg - 112; | |
1457 | ||
1458 | if (reg >= 192 && reg <= 199) | |
1459 | return ARM_WC0_REGNUM + reg - 192; | |
1460 | ||
1461 | return -1; | |
1462 | } | |
1463 | ||
26216b98 AC |
1464 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1465 | static int | |
e7faf938 | 1466 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
1467 | { |
1468 | int reg = regnum; | |
e7faf938 | 1469 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 1470 | |
ff6f572f DJ |
1471 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
1472 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
1473 | ||
1474 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
1475 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
1476 | ||
1477 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
1478 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
1479 | ||
26216b98 AC |
1480 | if (reg < NUM_GREGS) |
1481 | return SIM_ARM_R0_REGNUM + reg; | |
1482 | reg -= NUM_GREGS; | |
1483 | ||
1484 | if (reg < NUM_FREGS) | |
1485 | return SIM_ARM_FP0_REGNUM + reg; | |
1486 | reg -= NUM_FREGS; | |
1487 | ||
1488 | if (reg < NUM_SREGS) | |
1489 | return SIM_ARM_FPS_REGNUM + reg; | |
1490 | reg -= NUM_SREGS; | |
1491 | ||
edefbb7c | 1492 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1493 | } |
34e8f22d | 1494 | |
a37b3cc0 AC |
1495 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1496 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1497 | It is thought that this is is the floating-point register format on | |
1498 | little-endian systems. */ | |
c906108c | 1499 | |
ed9a39eb | 1500 | static void |
b508a996 | 1501 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 1502 | void *dbl, int endianess) |
c906108c | 1503 | { |
a37b3cc0 | 1504 | DOUBLEST d; |
be8626e0 MD |
1505 | |
1506 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
1507 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1508 | else | |
1509 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1510 | ptr, &d); | |
b508a996 | 1511 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1512 | } |
1513 | ||
34e8f22d | 1514 | static void |
be8626e0 MD |
1515 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
1516 | int endianess) | |
c906108c | 1517 | { |
a37b3cc0 | 1518 | DOUBLEST d; |
be8626e0 | 1519 | |
b508a996 | 1520 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 1521 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1522 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1523 | else | |
1524 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1525 | &d, dbl); | |
c906108c | 1526 | } |
ed9a39eb | 1527 | |
c906108c | 1528 | static int |
ed9a39eb | 1529 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1530 | { |
1531 | if (cond == INST_AL || cond == INST_NV) | |
1532 | return 1; | |
1533 | ||
1534 | switch (cond) | |
1535 | { | |
1536 | case INST_EQ: | |
1537 | return ((status_reg & FLAG_Z) != 0); | |
1538 | case INST_NE: | |
1539 | return ((status_reg & FLAG_Z) == 0); | |
1540 | case INST_CS: | |
1541 | return ((status_reg & FLAG_C) != 0); | |
1542 | case INST_CC: | |
1543 | return ((status_reg & FLAG_C) == 0); | |
1544 | case INST_MI: | |
1545 | return ((status_reg & FLAG_N) != 0); | |
1546 | case INST_PL: | |
1547 | return ((status_reg & FLAG_N) == 0); | |
1548 | case INST_VS: | |
1549 | return ((status_reg & FLAG_V) != 0); | |
1550 | case INST_VC: | |
1551 | return ((status_reg & FLAG_V) == 0); | |
1552 | case INST_HI: | |
1553 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1554 | case INST_LS: | |
1555 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1556 | case INST_GE: | |
1557 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1558 | case INST_LT: | |
1559 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1560 | case INST_GT: | |
1561 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1562 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1563 | case INST_LE: |
1564 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1565 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1566 | } |
1567 | return 1; | |
1568 | } | |
1569 | ||
9512d7fd | 1570 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1571 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1572 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1573 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1574 | #define sbits(obj,st,fn) \ | |
1575 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1576 | #define BranchDest(addr,instr) \ | |
1577 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1578 | #define ARM_PC_32 1 | |
1579 | ||
1580 | static unsigned long | |
0b1b3e42 UW |
1581 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
1582 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
1583 | { |
1584 | unsigned long res, shift; | |
1585 | int rm = bits (inst, 0, 3); | |
1586 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1587 | |
1588 | if (bit (inst, 4)) | |
c906108c SS |
1589 | { |
1590 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
1591 | shift = (rs == 15 ? pc_val + 8 |
1592 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
1593 | } |
1594 | else | |
1595 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1596 | |
1597 | res = (rm == 15 | |
c906108c | 1598 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1599 | + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 1600 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
1601 | |
1602 | switch (shifttype) | |
1603 | { | |
c5aa993b | 1604 | case 0: /* LSL */ |
c906108c SS |
1605 | res = shift >= 32 ? 0 : res << shift; |
1606 | break; | |
c5aa993b JM |
1607 | |
1608 | case 1: /* LSR */ | |
c906108c SS |
1609 | res = shift >= 32 ? 0 : res >> shift; |
1610 | break; | |
1611 | ||
c5aa993b JM |
1612 | case 2: /* ASR */ |
1613 | if (shift >= 32) | |
1614 | shift = 31; | |
c906108c SS |
1615 | res = ((res & 0x80000000L) |
1616 | ? ~((~res) >> shift) : res >> shift); | |
1617 | break; | |
1618 | ||
c5aa993b | 1619 | case 3: /* ROR/RRX */ |
c906108c SS |
1620 | shift &= 31; |
1621 | if (shift == 0) | |
1622 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1623 | else | |
c5aa993b | 1624 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1625 | break; |
1626 | } | |
1627 | ||
1628 | return res & 0xffffffff; | |
1629 | } | |
1630 | ||
c906108c SS |
1631 | /* Return number of 1-bits in VAL. */ |
1632 | ||
1633 | static int | |
ed9a39eb | 1634 | bitcount (unsigned long val) |
c906108c SS |
1635 | { |
1636 | int nbits; | |
1637 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1638 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1639 | return nbits; |
1640 | } | |
1641 | ||
ad527d2e | 1642 | static CORE_ADDR |
0b1b3e42 | 1643 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1644 | { |
2af46ca0 | 1645 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b | 1646 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
1c5bada0 | 1647 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
94c30b78 | 1648 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1649 | unsigned long offset; |
1650 | ||
1651 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1652 | { | |
1653 | CORE_ADDR sp; | |
1654 | ||
1655 | /* Fetch the saved PC from the stack. It's stored above | |
1656 | all of the other registers. */ | |
f0c9063c | 1657 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 1658 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
1c5bada0 | 1659 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
2af46ca0 | 1660 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 1661 | if (nextpc == pc) |
edefbb7c | 1662 | error (_("Infinite loop detected")); |
c906108c SS |
1663 | } |
1664 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1665 | { | |
0b1b3e42 | 1666 | unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1667 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1668 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1669 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1670 | } | |
1671 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1672 | { | |
1673 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1674 | } | |
aa17d93e | 1675 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1676 | { |
1c5bada0 | 1677 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
c5aa993b | 1678 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1679 | nextpc = pc_val + offset; |
aa17d93e DJ |
1680 | /* For BLX make sure to clear the low bits. */ |
1681 | if (bits (inst2, 11, 12) == 1) | |
1682 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1683 | } |
aa17d93e | 1684 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1685 | { |
1686 | if (bits (inst1, 3, 6) == 0x0f) | |
1687 | nextpc = pc_val; | |
1688 | else | |
0b1b3e42 | 1689 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 1690 | |
2af46ca0 | 1691 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
9498281f | 1692 | if (nextpc == pc) |
edefbb7c | 1693 | error (_("Infinite loop detected")); |
9498281f | 1694 | } |
c906108c SS |
1695 | |
1696 | return nextpc; | |
1697 | } | |
1698 | ||
daddc3c1 | 1699 | CORE_ADDR |
0b1b3e42 | 1700 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1701 | { |
2af46ca0 | 1702 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
1703 | unsigned long pc_val; |
1704 | unsigned long this_instr; | |
1705 | unsigned long status; | |
1706 | CORE_ADDR nextpc; | |
1707 | ||
1708 | if (arm_pc_is_thumb (pc)) | |
0b1b3e42 | 1709 | return thumb_get_next_pc (frame, pc); |
c906108c SS |
1710 | |
1711 | pc_val = (unsigned long) pc; | |
1c5bada0 | 1712 | this_instr = read_memory_unsigned_integer (pc, 4); |
0b1b3e42 | 1713 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1714 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 1715 | |
daddc3c1 DJ |
1716 | if (bits (this_instr, 28, 31) == INST_NV) |
1717 | switch (bits (this_instr, 24, 27)) | |
1718 | { | |
1719 | case 0xa: | |
1720 | case 0xb: | |
1721 | { | |
1722 | /* Branch with Link and change to Thumb. */ | |
1723 | nextpc = BranchDest (pc, this_instr); | |
1724 | nextpc |= bit (this_instr, 24) << 1; | |
1725 | ||
e1e01acd | 1726 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
daddc3c1 DJ |
1727 | if (nextpc == pc) |
1728 | error (_("Infinite loop detected")); | |
1729 | break; | |
1730 | } | |
1731 | case 0xc: | |
1732 | case 0xd: | |
1733 | case 0xe: | |
1734 | /* Coprocessor register transfer. */ | |
1735 | if (bits (this_instr, 12, 15) == 15) | |
1736 | error (_("Invalid update to pc in instruction")); | |
1737 | break; | |
1738 | } | |
1739 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
1740 | { |
1741 | switch (bits (this_instr, 24, 27)) | |
1742 | { | |
c5aa993b | 1743 | case 0x0: |
94c30b78 | 1744 | case 0x1: /* data processing */ |
c5aa993b JM |
1745 | case 0x2: |
1746 | case 0x3: | |
c906108c SS |
1747 | { |
1748 | unsigned long operand1, operand2, result = 0; | |
1749 | unsigned long rn; | |
1750 | int c; | |
c5aa993b | 1751 | |
c906108c SS |
1752 | if (bits (this_instr, 12, 15) != 15) |
1753 | break; | |
1754 | ||
1755 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1756 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1757 | error (_("Invalid update to pc in instruction")); |
c906108c | 1758 | |
9498281f | 1759 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
1760 | if (bits (this_instr, 4, 27) == 0x12fff1 |
1761 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
1762 | { |
1763 | rn = bits (this_instr, 0, 3); | |
0b1b3e42 UW |
1764 | result = (rn == 15) ? pc_val + 8 |
1765 | : get_frame_register_unsigned (frame, rn); | |
bf6ae464 | 1766 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 1767 | (gdbarch, result); |
9498281f DJ |
1768 | |
1769 | if (nextpc == pc) | |
edefbb7c | 1770 | error (_("Infinite loop detected")); |
9498281f DJ |
1771 | |
1772 | return nextpc; | |
1773 | } | |
1774 | ||
c906108c SS |
1775 | /* Multiply into PC */ |
1776 | c = (status & FLAG_C) ? 1 : 0; | |
1777 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
1778 | operand1 = (rn == 15) ? pc_val + 8 |
1779 | : get_frame_register_unsigned (frame, rn); | |
c5aa993b | 1780 | |
c906108c SS |
1781 | if (bit (this_instr, 25)) |
1782 | { | |
1783 | unsigned long immval = bits (this_instr, 0, 7); | |
1784 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1785 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1786 | & 0xffffffff; | |
c906108c | 1787 | } |
c5aa993b | 1788 | else /* operand 2 is a shifted register */ |
0b1b3e42 | 1789 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
c5aa993b | 1790 | |
c906108c SS |
1791 | switch (bits (this_instr, 21, 24)) |
1792 | { | |
c5aa993b | 1793 | case 0x0: /*and */ |
c906108c SS |
1794 | result = operand1 & operand2; |
1795 | break; | |
1796 | ||
c5aa993b | 1797 | case 0x1: /*eor */ |
c906108c SS |
1798 | result = operand1 ^ operand2; |
1799 | break; | |
1800 | ||
c5aa993b | 1801 | case 0x2: /*sub */ |
c906108c SS |
1802 | result = operand1 - operand2; |
1803 | break; | |
1804 | ||
c5aa993b | 1805 | case 0x3: /*rsb */ |
c906108c SS |
1806 | result = operand2 - operand1; |
1807 | break; | |
1808 | ||
c5aa993b | 1809 | case 0x4: /*add */ |
c906108c SS |
1810 | result = operand1 + operand2; |
1811 | break; | |
1812 | ||
c5aa993b | 1813 | case 0x5: /*adc */ |
c906108c SS |
1814 | result = operand1 + operand2 + c; |
1815 | break; | |
1816 | ||
c5aa993b | 1817 | case 0x6: /*sbc */ |
c906108c SS |
1818 | result = operand1 - operand2 + c; |
1819 | break; | |
1820 | ||
c5aa993b | 1821 | case 0x7: /*rsc */ |
c906108c SS |
1822 | result = operand2 - operand1 + c; |
1823 | break; | |
1824 | ||
c5aa993b JM |
1825 | case 0x8: |
1826 | case 0x9: | |
1827 | case 0xa: | |
1828 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1829 | result = (unsigned long) nextpc; |
1830 | break; | |
1831 | ||
c5aa993b | 1832 | case 0xc: /*orr */ |
c906108c SS |
1833 | result = operand1 | operand2; |
1834 | break; | |
1835 | ||
c5aa993b | 1836 | case 0xd: /*mov */ |
c906108c SS |
1837 | /* Always step into a function. */ |
1838 | result = operand2; | |
c5aa993b | 1839 | break; |
c906108c | 1840 | |
c5aa993b | 1841 | case 0xe: /*bic */ |
c906108c SS |
1842 | result = operand1 & ~operand2; |
1843 | break; | |
1844 | ||
c5aa993b | 1845 | case 0xf: /*mvn */ |
c906108c SS |
1846 | result = ~operand2; |
1847 | break; | |
1848 | } | |
bf6ae464 | 1849 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 1850 | (gdbarch, result); |
c906108c SS |
1851 | |
1852 | if (nextpc == pc) | |
edefbb7c | 1853 | error (_("Infinite loop detected")); |
c906108c SS |
1854 | break; |
1855 | } | |
c5aa993b JM |
1856 | |
1857 | case 0x4: | |
1858 | case 0x5: /* data transfer */ | |
1859 | case 0x6: | |
1860 | case 0x7: | |
c906108c SS |
1861 | if (bit (this_instr, 20)) |
1862 | { | |
1863 | /* load */ | |
1864 | if (bits (this_instr, 12, 15) == 15) | |
1865 | { | |
1866 | /* rd == pc */ | |
c5aa993b | 1867 | unsigned long rn; |
c906108c | 1868 | unsigned long base; |
c5aa993b | 1869 | |
c906108c | 1870 | if (bit (this_instr, 22)) |
edefbb7c | 1871 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1872 | |
1873 | /* byte write to PC */ | |
1874 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
1875 | base = (rn == 15) ? pc_val + 8 |
1876 | : get_frame_register_unsigned (frame, rn); | |
c906108c SS |
1877 | if (bit (this_instr, 24)) |
1878 | { | |
1879 | /* pre-indexed */ | |
1880 | int c = (status & FLAG_C) ? 1 : 0; | |
1881 | unsigned long offset = | |
c5aa993b | 1882 | (bit (this_instr, 25) |
0b1b3e42 | 1883 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 1884 | : bits (this_instr, 0, 11)); |
c906108c SS |
1885 | |
1886 | if (bit (this_instr, 23)) | |
1887 | base += offset; | |
1888 | else | |
1889 | base -= offset; | |
1890 | } | |
c5aa993b | 1891 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1892 | 4); |
c5aa993b | 1893 | |
2af46ca0 | 1894 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c SS |
1895 | |
1896 | if (nextpc == pc) | |
edefbb7c | 1897 | error (_("Infinite loop detected")); |
c906108c SS |
1898 | } |
1899 | } | |
1900 | break; | |
c5aa993b JM |
1901 | |
1902 | case 0x8: | |
1903 | case 0x9: /* block transfer */ | |
c906108c SS |
1904 | if (bit (this_instr, 20)) |
1905 | { | |
1906 | /* LDM */ | |
1907 | if (bit (this_instr, 15)) | |
1908 | { | |
1909 | /* loading pc */ | |
1910 | int offset = 0; | |
1911 | ||
1912 | if (bit (this_instr, 23)) | |
1913 | { | |
1914 | /* up */ | |
1915 | unsigned long reglist = bits (this_instr, 0, 14); | |
1916 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1917 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1918 | offset += 4; |
1919 | } | |
1920 | else if (bit (this_instr, 24)) | |
1921 | offset = -4; | |
c5aa993b | 1922 | |
c906108c | 1923 | { |
c5aa993b | 1924 | unsigned long rn_val = |
0b1b3e42 UW |
1925 | get_frame_register_unsigned (frame, |
1926 | bits (this_instr, 16, 19)); | |
c906108c SS |
1927 | nextpc = |
1928 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1929 | + offset), |
c906108c SS |
1930 | 4); |
1931 | } | |
bf6ae464 | 1932 | nextpc = gdbarch_addr_bits_remove |
2af46ca0 | 1933 | (gdbarch, nextpc); |
c906108c | 1934 | if (nextpc == pc) |
edefbb7c | 1935 | error (_("Infinite loop detected")); |
c906108c SS |
1936 | } |
1937 | } | |
1938 | break; | |
c5aa993b JM |
1939 | |
1940 | case 0xb: /* branch & link */ | |
1941 | case 0xa: /* branch */ | |
c906108c SS |
1942 | { |
1943 | nextpc = BranchDest (pc, this_instr); | |
1944 | ||
2af46ca0 | 1945 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 1946 | if (nextpc == pc) |
edefbb7c | 1947 | error (_("Infinite loop detected")); |
c906108c SS |
1948 | break; |
1949 | } | |
c5aa993b JM |
1950 | |
1951 | case 0xc: | |
1952 | case 0xd: | |
1953 | case 0xe: /* coproc ops */ | |
1954 | case 0xf: /* SWI */ | |
c906108c SS |
1955 | break; |
1956 | ||
1957 | default: | |
edefbb7c | 1958 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1959 | return (pc); |
1960 | } | |
1961 | } | |
1962 | ||
1963 | return nextpc; | |
1964 | } | |
1965 | ||
9512d7fd FN |
1966 | /* single_step() is called just before we want to resume the inferior, |
1967 | if we want to single-step it but there is no hardware or kernel | |
1968 | single-step support. We find the target of the coming instruction | |
e0cd558a | 1969 | and breakpoint it. */ |
9512d7fd | 1970 | |
190dce09 | 1971 | int |
0b1b3e42 | 1972 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 1973 | { |
8181d85f DJ |
1974 | /* NOTE: This may insert the wrong breakpoint instruction when |
1975 | single-stepping over a mode-changing instruction, if the | |
1976 | CPSR heuristics are used. */ | |
9512d7fd | 1977 | |
0b1b3e42 | 1978 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
e0cd558a | 1979 | insert_single_step_breakpoint (next_pc); |
e6590a1b UW |
1980 | |
1981 | return 1; | |
9512d7fd | 1982 | } |
9512d7fd | 1983 | |
c906108c SS |
1984 | #include "bfd-in2.h" |
1985 | #include "libcoff.h" | |
1986 | ||
1987 | static int | |
ed9a39eb | 1988 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1989 | { |
1990 | if (arm_pc_is_thumb (memaddr)) | |
1991 | { | |
c5aa993b JM |
1992 | static asymbol *asym; |
1993 | static combined_entry_type ce; | |
1994 | static struct coff_symbol_struct csym; | |
27cddce2 | 1995 | static struct bfd fake_bfd; |
c5aa993b | 1996 | static bfd_target fake_target; |
c906108c SS |
1997 | |
1998 | if (csym.native == NULL) | |
1999 | { | |
da3c6d4a MS |
2000 | /* Create a fake symbol vector containing a Thumb symbol. |
2001 | This is solely so that the code in print_insn_little_arm() | |
2002 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2003 | the presence of a Thumb symbol and switch to decoding | |
2004 | Thumb instructions. */ | |
c5aa993b JM |
2005 | |
2006 | fake_target.flavour = bfd_target_coff_flavour; | |
2007 | fake_bfd.xvec = &fake_target; | |
c906108c | 2008 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2009 | csym.native = &ce; |
2010 | csym.symbol.the_bfd = &fake_bfd; | |
2011 | csym.symbol.name = "fake"; | |
2012 | asym = (asymbol *) & csym; | |
c906108c | 2013 | } |
c5aa993b | 2014 | |
c906108c | 2015 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2016 | info->symbols = &asym; |
c906108c SS |
2017 | } |
2018 | else | |
2019 | info->symbols = NULL; | |
c5aa993b | 2020 | |
40887e1a | 2021 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
2022 | return print_insn_big_arm (memaddr, info); |
2023 | else | |
2024 | return print_insn_little_arm (memaddr, info); | |
2025 | } | |
2026 | ||
66e810cd RE |
2027 | /* The following define instruction sequences that will cause ARM |
2028 | cpu's to take an undefined instruction trap. These are used to | |
2029 | signal a breakpoint to GDB. | |
2030 | ||
2031 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2032 | modes. A different instruction is required for each mode. The ARM | |
2033 | cpu's can also be big or little endian. Thus four different | |
2034 | instructions are needed to support all cases. | |
2035 | ||
2036 | Note: ARMv4 defines several new instructions that will take the | |
2037 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2038 | not in fact add the new instructions. The new undefined | |
2039 | instructions in ARMv4 are all instructions that had no defined | |
2040 | behaviour in earlier chips. There is no guarantee that they will | |
2041 | raise an exception, but may be treated as NOP's. In practice, it | |
2042 | may only safe to rely on instructions matching: | |
2043 | ||
2044 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2045 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2046 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2047 | ||
2048 | Even this may only true if the condition predicate is true. The | |
2049 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2050 | ||
2051 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2052 | and NetBSD all use a software interrupt rather than an undefined | |
2053 | instruction to force a trap. This can be handled by by the | |
2054 | abi-specific code during establishment of the gdbarch vector. */ | |
2055 | ||
66e810cd | 2056 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
66e810cd | 2057 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
190dce09 UW |
2058 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
2059 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
66e810cd RE |
2060 | |
2061 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2062 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2063 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2064 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2065 | ||
34e8f22d RE |
2066 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2067 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2068 | breakpoint should be used. It returns a pointer to a string of |
2069 | bytes that encode a breakpoint instruction, stores the length of | |
2070 | the string to *lenptr, and adjusts the program counter (if | |
2071 | necessary) to point to the actual memory location where the | |
c906108c SS |
2072 | breakpoint should be inserted. */ |
2073 | ||
ab89facf | 2074 | static const unsigned char * |
67d57894 | 2075 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2076 | { |
67d57894 | 2077 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
66e810cd | 2078 | |
4bf7064c | 2079 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 2080 | { |
66e810cd RE |
2081 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2082 | *lenptr = tdep->thumb_breakpoint_size; | |
2083 | return tdep->thumb_breakpoint; | |
c906108c SS |
2084 | } |
2085 | else | |
2086 | { | |
66e810cd RE |
2087 | *lenptr = tdep->arm_breakpoint_size; |
2088 | return tdep->arm_breakpoint; | |
c906108c SS |
2089 | } |
2090 | } | |
ed9a39eb JM |
2091 | |
2092 | /* Extract from an array REGBUF containing the (raw) register state a | |
2093 | function return value of type TYPE, and copy that, in virtual | |
2094 | format, into VALBUF. */ | |
2095 | ||
34e8f22d | 2096 | static void |
5238cf52 MK |
2097 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2098 | gdb_byte *valbuf) | |
ed9a39eb | 2099 | { |
be8626e0 MD |
2100 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
2101 | ||
ed9a39eb | 2102 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2103 | { |
be8626e0 | 2104 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2105 | { |
2106 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2107 | { |
2108 | /* The value is in register F0 in internal format. We need to | |
2109 | extract the raw value and then convert it to the desired | |
2110 | internal type. */ | |
7a5ea0d4 | 2111 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2112 | |
2113 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2114 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
be8626e0 | 2115 | valbuf, gdbarch_byte_order (gdbarch)); |
b508a996 | 2116 | } |
08216dd7 RE |
2117 | break; |
2118 | ||
fd50bc42 | 2119 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2120 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2121 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2122 | if (TYPE_LENGTH (type) > 4) | |
2123 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2124 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2125 | break; |
2126 | ||
2127 | default: | |
2128 | internal_error | |
2129 | (__FILE__, __LINE__, | |
edefbb7c | 2130 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2131 | break; |
2132 | } | |
2133 | } | |
b508a996 RE |
2134 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2135 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2136 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2137 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2138 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2139 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2140 | { | |
2141 | /* If the the type is a plain integer, then the access is | |
2142 | straight-forward. Otherwise we have to play around a bit more. */ | |
2143 | int len = TYPE_LENGTH (type); | |
2144 | int regno = ARM_A1_REGNUM; | |
2145 | ULONGEST tmp; | |
2146 | ||
2147 | while (len > 0) | |
2148 | { | |
2149 | /* By using store_unsigned_integer we avoid having to do | |
2150 | anything special for small big-endian values. */ | |
2151 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2152 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2153 | (len > INT_REGISTER_SIZE |
2154 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2155 | tmp); |
7a5ea0d4 DJ |
2156 | len -= INT_REGISTER_SIZE; |
2157 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2158 | } |
2159 | } | |
ed9a39eb | 2160 | else |
b508a996 RE |
2161 | { |
2162 | /* For a structure or union the behaviour is as if the value had | |
2163 | been stored to word-aligned memory and then loaded into | |
2164 | registers with 32-bit load instruction(s). */ | |
2165 | int len = TYPE_LENGTH (type); | |
2166 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2167 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2168 | |
2169 | while (len > 0) | |
2170 | { | |
2171 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2172 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2173 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2174 | len -= INT_REGISTER_SIZE; | |
2175 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2176 | } |
2177 | } | |
34e8f22d RE |
2178 | } |
2179 | ||
67255d04 RE |
2180 | |
2181 | /* Will a function return an aggregate type in memory or in a | |
2182 | register? Return 0 if an aggregate type can be returned in a | |
2183 | register, 1 if it must be returned in memory. */ | |
2184 | ||
2185 | static int | |
2af48f68 | 2186 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2187 | { |
2188 | int nRc; | |
52f0bd74 | 2189 | enum type_code code; |
67255d04 | 2190 | |
44e1a9eb DJ |
2191 | CHECK_TYPEDEF (type); |
2192 | ||
67255d04 RE |
2193 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2194 | registers. For an aggregate type to be integer like, its size | |
f0c9063c | 2195 | must be less than or equal to INT_REGISTER_SIZE and the |
b1e29e33 AC |
2196 | offset of each addressable subfield must be zero. Note that bit |
2197 | fields are not addressable, and all addressable subfields of | |
2198 | unions always start at offset zero. | |
67255d04 RE |
2199 | |
2200 | This function is based on the behaviour of GCC 2.95.1. | |
2201 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2202 | ||
2203 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2204 | parameters correctly for a function returning the following | |
2205 | structure: struct { float f;}; This should be returned in memory, | |
2206 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2207 | know of any way to detect if a function like the above has been | |
2208 | compiled with the correct calling convention. */ | |
2209 | ||
2210 | /* All aggregate types that won't fit in a register must be returned | |
2211 | in memory. */ | |
f0c9063c | 2212 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
67255d04 RE |
2213 | { |
2214 | return 1; | |
2215 | } | |
2216 | ||
2af48f68 PB |
2217 | /* The AAPCS says all aggregates not larger than a word are returned |
2218 | in a register. */ | |
2219 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2220 | return 0; | |
2221 | ||
67255d04 RE |
2222 | /* The only aggregate types that can be returned in a register are |
2223 | structs and unions. Arrays must be returned in memory. */ | |
2224 | code = TYPE_CODE (type); | |
2225 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2226 | { | |
2227 | return 1; | |
2228 | } | |
2229 | ||
2230 | /* Assume all other aggregate types can be returned in a register. | |
2231 | Run a check for structures, unions and arrays. */ | |
2232 | nRc = 0; | |
2233 | ||
2234 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2235 | { | |
2236 | int i; | |
2237 | /* Need to check if this struct/union is "integer" like. For | |
2238 | this to be true, its size must be less than or equal to | |
f0c9063c | 2239 | INT_REGISTER_SIZE and the offset of each addressable |
b1e29e33 AC |
2240 | subfield must be zero. Note that bit fields are not |
2241 | addressable, and unions always start at offset zero. If any | |
2242 | of the subfields is a floating point type, the struct/union | |
2243 | cannot be an integer type. */ | |
67255d04 RE |
2244 | |
2245 | /* For each field in the object, check: | |
2246 | 1) Is it FP? --> yes, nRc = 1; | |
2247 | 2) Is it addressable (bitpos != 0) and | |
2248 | not packed (bitsize == 0)? | |
2249 | --> yes, nRc = 1 | |
2250 | */ | |
2251 | ||
2252 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2253 | { | |
2254 | enum type_code field_type_code; | |
44e1a9eb | 2255 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2256 | |
2257 | /* Is it a floating point type field? */ | |
2258 | if (field_type_code == TYPE_CODE_FLT) | |
2259 | { | |
2260 | nRc = 1; | |
2261 | break; | |
2262 | } | |
2263 | ||
2264 | /* If bitpos != 0, then we have to care about it. */ | |
2265 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2266 | { | |
2267 | /* Bitfields are not addressable. If the field bitsize is | |
2268 | zero, then the field is not packed. Hence it cannot be | |
2269 | a bitfield or any other packed type. */ | |
2270 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2271 | { | |
2272 | nRc = 1; | |
2273 | break; | |
2274 | } | |
2275 | } | |
2276 | } | |
2277 | } | |
2278 | ||
2279 | return nRc; | |
2280 | } | |
2281 | ||
34e8f22d RE |
2282 | /* Write into appropriate registers a function return value of type |
2283 | TYPE, given in virtual format. */ | |
2284 | ||
2285 | static void | |
b508a996 | 2286 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2287 | const gdb_byte *valbuf) |
34e8f22d | 2288 | { |
be8626e0 MD |
2289 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
2290 | ||
34e8f22d RE |
2291 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2292 | { | |
7a5ea0d4 | 2293 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2294 | |
be8626e0 | 2295 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2296 | { |
2297 | case ARM_FLOAT_FPA: | |
2298 | ||
be8626e0 MD |
2299 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
2300 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 2301 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
2302 | break; |
2303 | ||
fd50bc42 | 2304 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2305 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2306 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2307 | if (TYPE_LENGTH (type) > 4) | |
2308 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2309 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2310 | break; |
2311 | ||
2312 | default: | |
2313 | internal_error | |
2314 | (__FILE__, __LINE__, | |
edefbb7c | 2315 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2316 | break; |
2317 | } | |
34e8f22d | 2318 | } |
b508a996 RE |
2319 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2320 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2321 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2322 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2323 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2324 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2325 | { | |
2326 | if (TYPE_LENGTH (type) <= 4) | |
2327 | { | |
2328 | /* Values of one word or less are zero/sign-extended and | |
2329 | returned in r0. */ | |
7a5ea0d4 | 2330 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2331 | LONGEST val = unpack_long (type, valbuf); |
2332 | ||
7a5ea0d4 | 2333 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2334 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2335 | } | |
2336 | else | |
2337 | { | |
2338 | /* Integral values greater than one word are stored in consecutive | |
2339 | registers starting with r0. This will always be a multiple of | |
2340 | the regiser size. */ | |
2341 | int len = TYPE_LENGTH (type); | |
2342 | int regno = ARM_A1_REGNUM; | |
2343 | ||
2344 | while (len > 0) | |
2345 | { | |
2346 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2347 | len -= INT_REGISTER_SIZE; |
2348 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2349 | } |
2350 | } | |
2351 | } | |
34e8f22d | 2352 | else |
b508a996 RE |
2353 | { |
2354 | /* For a structure or union the behaviour is as if the value had | |
2355 | been stored to word-aligned memory and then loaded into | |
2356 | registers with 32-bit load instruction(s). */ | |
2357 | int len = TYPE_LENGTH (type); | |
2358 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2359 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2360 | |
2361 | while (len > 0) | |
2362 | { | |
2363 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2364 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2365 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2366 | len -= INT_REGISTER_SIZE; |
2367 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2368 | } |
2369 | } | |
34e8f22d RE |
2370 | } |
2371 | ||
2af48f68 PB |
2372 | |
2373 | /* Handle function return values. */ | |
2374 | ||
2375 | static enum return_value_convention | |
2376 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
25224166 MK |
2377 | struct regcache *regcache, gdb_byte *readbuf, |
2378 | const gdb_byte *writebuf) | |
2af48f68 | 2379 | { |
7c00367c MK |
2380 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2381 | ||
2af48f68 PB |
2382 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
2383 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2384 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2385 | { | |
7c00367c MK |
2386 | if (tdep->struct_return == pcc_struct_return |
2387 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
2388 | return RETURN_VALUE_STRUCT_CONVENTION; |
2389 | } | |
2390 | ||
2391 | if (writebuf) | |
2392 | arm_store_return_value (valtype, regcache, writebuf); | |
2393 | ||
2394 | if (readbuf) | |
2395 | arm_extract_return_value (valtype, regcache, readbuf); | |
2396 | ||
2397 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2398 | } | |
2399 | ||
2400 | ||
9df628e0 | 2401 | static int |
60ade65d | 2402 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 RE |
2403 | { |
2404 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2405 | char buf[INT_REGISTER_SIZE]; |
60ade65d | 2406 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
9df628e0 | 2407 | |
60ade65d | 2408 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
2409 | |
2410 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2411 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2412 | return 0; |
2413 | ||
7a5ea0d4 | 2414 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2415 | return 1; |
2416 | } | |
2417 | ||
faa95490 DJ |
2418 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
2419 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
2420 | |
2421 | CORE_ADDR | |
52f729a7 | 2422 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2423 | { |
c5aa993b | 2424 | char *name; |
faa95490 | 2425 | int namelen; |
c906108c SS |
2426 | CORE_ADDR start_addr; |
2427 | ||
2428 | /* Find the starting address and name of the function containing the PC. */ | |
2429 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2430 | return 0; | |
2431 | ||
faa95490 DJ |
2432 | /* If PC is in a Thumb call or return stub, return the address of the |
2433 | target PC, which is in a register. The thunk functions are called | |
2434 | _call_via_xx, where x is the register name. The possible names | |
2435 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2436 | if (strncmp (name, "_call_via_", 10) == 0) |
2437 | { | |
ed9a39eb JM |
2438 | /* Use the name suffix to determine which register contains the |
2439 | target PC. */ | |
c5aa993b JM |
2440 | static char *table[15] = |
2441 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2442 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2443 | }; | |
c906108c | 2444 | int regno; |
faa95490 | 2445 | int offset = strlen (name) - 2; |
c906108c SS |
2446 | |
2447 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 2448 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 2449 | return get_frame_register_unsigned (frame, regno); |
c906108c | 2450 | } |
ed9a39eb | 2451 | |
faa95490 DJ |
2452 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
2453 | non-interworking calls to foo. We could decode the stubs | |
2454 | to find the target but it's easier to use the symbol table. */ | |
2455 | namelen = strlen (name); | |
2456 | if (name[0] == '_' && name[1] == '_' | |
2457 | && ((namelen > 2 + strlen ("_from_thumb") | |
2458 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", | |
2459 | strlen ("_from_thumb")) == 0) | |
2460 | || (namelen > 2 + strlen ("_from_arm") | |
2461 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", | |
2462 | strlen ("_from_arm")) == 0))) | |
2463 | { | |
2464 | char *target_name; | |
2465 | int target_len = namelen - 2; | |
2466 | struct minimal_symbol *minsym; | |
2467 | struct objfile *objfile; | |
2468 | struct obj_section *sec; | |
2469 | ||
2470 | if (name[namelen - 1] == 'b') | |
2471 | target_len -= strlen ("_from_thumb"); | |
2472 | else | |
2473 | target_len -= strlen ("_from_arm"); | |
2474 | ||
2475 | target_name = alloca (target_len + 1); | |
2476 | memcpy (target_name, name + 2, target_len); | |
2477 | target_name[target_len] = '\0'; | |
2478 | ||
2479 | sec = find_pc_section (pc); | |
2480 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
2481 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
2482 | if (minsym != NULL) | |
2483 | return SYMBOL_VALUE_ADDRESS (minsym); | |
2484 | else | |
2485 | return 0; | |
2486 | } | |
2487 | ||
c5aa993b | 2488 | return 0; /* not a stub */ |
c906108c SS |
2489 | } |
2490 | ||
afd7eef0 RE |
2491 | static void |
2492 | set_arm_command (char *args, int from_tty) | |
2493 | { | |
edefbb7c AC |
2494 | printf_unfiltered (_("\ |
2495 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2496 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2497 | } | |
2498 | ||
2499 | static void | |
2500 | show_arm_command (char *args, int from_tty) | |
2501 | { | |
26304000 | 2502 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2503 | } |
2504 | ||
28e97307 DJ |
2505 | static void |
2506 | arm_update_current_architecture (void) | |
fd50bc42 | 2507 | { |
28e97307 | 2508 | struct gdbarch_info info; |
fd50bc42 | 2509 | |
28e97307 DJ |
2510 | /* If the current architecture is not ARM, we have nothing to do. */ |
2511 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2512 | return; | |
fd50bc42 | 2513 | |
28e97307 DJ |
2514 | /* Update the architecture. */ |
2515 | gdbarch_info_init (&info); | |
fd50bc42 | 2516 | |
28e97307 DJ |
2517 | if (!gdbarch_update_p (info)) |
2518 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2519 | } |
2520 | ||
2521 | static void | |
2522 | set_fp_model_sfunc (char *args, int from_tty, | |
2523 | struct cmd_list_element *c) | |
2524 | { | |
2525 | enum arm_float_model fp_model; | |
2526 | ||
2527 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2528 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2529 | { | |
2530 | arm_fp_model = fp_model; | |
2531 | break; | |
2532 | } | |
2533 | ||
2534 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2535 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2536 | current_fp_model); |
2537 | ||
28e97307 | 2538 | arm_update_current_architecture (); |
fd50bc42 RE |
2539 | } |
2540 | ||
2541 | static void | |
08546159 AC |
2542 | show_fp_model (struct ui_file *file, int from_tty, |
2543 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2544 | { |
2545 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2546 | ||
28e97307 | 2547 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2548 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2549 | fprintf_filtered (file, _("\ |
2550 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2551 | fp_model_strings[tdep->fp_model]); | |
2552 | else | |
2553 | fprintf_filtered (file, _("\ | |
2554 | The current ARM floating point model is \"%s\".\n"), | |
2555 | fp_model_strings[arm_fp_model]); | |
2556 | } | |
2557 | ||
2558 | static void | |
2559 | arm_set_abi (char *args, int from_tty, | |
2560 | struct cmd_list_element *c) | |
2561 | { | |
2562 | enum arm_abi_kind arm_abi; | |
2563 | ||
2564 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2565 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2566 | { | |
2567 | arm_abi_global = arm_abi; | |
2568 | break; | |
2569 | } | |
2570 | ||
2571 | if (arm_abi == ARM_ABI_LAST) | |
2572 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2573 | arm_abi_string); | |
2574 | ||
2575 | arm_update_current_architecture (); | |
2576 | } | |
2577 | ||
2578 | static void | |
2579 | arm_show_abi (struct ui_file *file, int from_tty, | |
2580 | struct cmd_list_element *c, const char *value) | |
2581 | { | |
2582 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2583 | ||
2584 | if (arm_abi_global == ARM_ABI_AUTO | |
2585 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2586 | fprintf_filtered (file, _("\ | |
2587 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2588 | arm_abi_strings[tdep->arm_abi]); | |
2589 | else | |
2590 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2591 | arm_abi_string); | |
fd50bc42 RE |
2592 | } |
2593 | ||
afd7eef0 RE |
2594 | /* If the user changes the register disassembly style used for info |
2595 | register and other commands, we have to also switch the style used | |
2596 | in opcodes for disassembly output. This function is run in the "set | |
2597 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2598 | |
2599 | static void | |
afd7eef0 | 2600 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2601 | struct cmd_list_element *c) |
2602 | { | |
afd7eef0 | 2603 | set_disassembly_style (); |
bc90b915 FN |
2604 | } |
2605 | \f | |
966fbf70 | 2606 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2607 | static const char * |
d93859e2 | 2608 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 2609 | { |
ff6f572f DJ |
2610 | if (i >= ARRAY_SIZE (arm_register_names)) |
2611 | /* These registers are only supported on targets which supply | |
2612 | an XML description. */ | |
2613 | return ""; | |
2614 | ||
966fbf70 RE |
2615 | return arm_register_names[i]; |
2616 | } | |
2617 | ||
bc90b915 | 2618 | static void |
afd7eef0 | 2619 | set_disassembly_style (void) |
bc90b915 | 2620 | { |
123dc839 | 2621 | int current; |
bc90b915 | 2622 | |
123dc839 DJ |
2623 | /* Find the style that the user wants. */ |
2624 | for (current = 0; current < num_disassembly_options; current++) | |
2625 | if (disassembly_style == valid_disassembly_styles[current]) | |
2626 | break; | |
2627 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 2628 | |
94c30b78 | 2629 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2630 | set_arm_regname_option (current); |
2631 | } | |
2632 | ||
082fc60d RE |
2633 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2634 | function. */ | |
2635 | ||
2636 | static int | |
2637 | coff_sym_is_thumb (int val) | |
2638 | { | |
2639 | return (val == C_THUMBEXT || | |
2640 | val == C_THUMBSTAT || | |
2641 | val == C_THUMBEXTFUNC || | |
2642 | val == C_THUMBSTATFUNC || | |
2643 | val == C_THUMBLABEL); | |
2644 | } | |
2645 | ||
2646 | /* arm_coff_make_msymbol_special() | |
2647 | arm_elf_make_msymbol_special() | |
2648 | ||
2649 | These functions test whether the COFF or ELF symbol corresponds to | |
2650 | an address in thumb code, and set a "special" bit in a minimal | |
2651 | symbol to indicate that it does. */ | |
2652 | ||
34e8f22d | 2653 | static void |
082fc60d RE |
2654 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2655 | { | |
2656 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2657 | STT_ARM_TFUNC). */ | |
2658 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2659 | == STT_LOPROC) | |
2660 | MSYMBOL_SET_SPECIAL (msym); | |
2661 | } | |
2662 | ||
34e8f22d | 2663 | static void |
082fc60d RE |
2664 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2665 | { | |
2666 | if (coff_sym_is_thumb (val)) | |
2667 | MSYMBOL_SET_SPECIAL (msym); | |
2668 | } | |
2669 | ||
756fe439 | 2670 | static void |
61a1198a | 2671 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 2672 | { |
61a1198a | 2673 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
2674 | |
2675 | /* If necessary, set the T bit. */ | |
2676 | if (arm_apcs_32) | |
2677 | { | |
61a1198a UW |
2678 | ULONGEST val; |
2679 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); | |
756fe439 | 2680 | if (arm_pc_is_thumb (pc)) |
61a1198a | 2681 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | 0x20); |
756fe439 | 2682 | else |
61a1198a UW |
2683 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
2684 | val & ~(ULONGEST) 0x20); | |
756fe439 DJ |
2685 | } |
2686 | } | |
123dc839 DJ |
2687 | |
2688 | static struct value * | |
2689 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
2690 | { | |
2691 | const int *reg_p = baton; | |
2692 | return value_of_register (*reg_p, frame); | |
2693 | } | |
97e03143 | 2694 | \f |
70f80edf JT |
2695 | static enum gdb_osabi |
2696 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2697 | { |
2af48f68 | 2698 | unsigned int elfosabi; |
70f80edf | 2699 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2700 | |
70f80edf | 2701 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2702 | |
28e97307 DJ |
2703 | if (elfosabi == ELFOSABI_ARM) |
2704 | /* GNU tools use this value. Check note sections in this case, | |
2705 | as well. */ | |
2706 | bfd_map_over_sections (abfd, | |
2707 | generic_elf_osabi_sniff_abi_tag_sections, | |
2708 | &osabi); | |
97e03143 | 2709 | |
28e97307 | 2710 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2711 | return osabi; |
97e03143 RE |
2712 | } |
2713 | ||
70f80edf | 2714 | \f |
da3c6d4a MS |
2715 | /* Initialize the current architecture based on INFO. If possible, |
2716 | re-use an architecture from ARCHES, which is a list of | |
2717 | architectures already created during this debugging session. | |
97e03143 | 2718 | |
da3c6d4a MS |
2719 | Called e.g. at program startup, when reading a core file, and when |
2720 | reading a binary file. */ | |
97e03143 | 2721 | |
39bbf761 RE |
2722 | static struct gdbarch * |
2723 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2724 | { | |
97e03143 | 2725 | struct gdbarch_tdep *tdep; |
39bbf761 | 2726 | struct gdbarch *gdbarch; |
28e97307 DJ |
2727 | struct gdbarch_list *best_arch; |
2728 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2729 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
2730 | struct tdesc_arch_data *tdesc_data = NULL; |
2731 | int i; | |
ff6f572f | 2732 | int have_fpa_registers = 1; |
123dc839 DJ |
2733 | |
2734 | /* Check any target description for validity. */ | |
2735 | if (tdesc_has_registers (info.target_desc)) | |
2736 | { | |
2737 | /* For most registers we require GDB's default names; but also allow | |
2738 | the numeric names for sp / lr / pc, as a convenience. */ | |
2739 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
2740 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
2741 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
2742 | ||
2743 | const struct tdesc_feature *feature; | |
2744 | int i, valid_p; | |
2745 | ||
2746 | feature = tdesc_find_feature (info.target_desc, | |
2747 | "org.gnu.gdb.arm.core"); | |
2748 | if (feature == NULL) | |
2749 | return NULL; | |
2750 | ||
2751 | tdesc_data = tdesc_data_alloc (); | |
2752 | ||
2753 | valid_p = 1; | |
2754 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
2755 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2756 | arm_register_names[i]); | |
2757 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2758 | ARM_SP_REGNUM, | |
2759 | arm_sp_names); | |
2760 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2761 | ARM_LR_REGNUM, | |
2762 | arm_lr_names); | |
2763 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2764 | ARM_PC_REGNUM, | |
2765 | arm_pc_names); | |
2766 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
2767 | ARM_PS_REGNUM, "cpsr"); | |
2768 | ||
2769 | if (!valid_p) | |
2770 | { | |
2771 | tdesc_data_cleanup (tdesc_data); | |
2772 | return NULL; | |
2773 | } | |
2774 | ||
2775 | feature = tdesc_find_feature (info.target_desc, | |
2776 | "org.gnu.gdb.arm.fpa"); | |
2777 | if (feature != NULL) | |
2778 | { | |
2779 | valid_p = 1; | |
2780 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
2781 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2782 | arm_register_names[i]); | |
2783 | if (!valid_p) | |
2784 | { | |
2785 | tdesc_data_cleanup (tdesc_data); | |
2786 | return NULL; | |
2787 | } | |
2788 | } | |
ff6f572f DJ |
2789 | else |
2790 | have_fpa_registers = 0; | |
2791 | ||
2792 | feature = tdesc_find_feature (info.target_desc, | |
2793 | "org.gnu.gdb.xscale.iwmmxt"); | |
2794 | if (feature != NULL) | |
2795 | { | |
2796 | static const char *const iwmmxt_names[] = { | |
2797 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
2798 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
2799 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
2800 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
2801 | }; | |
2802 | ||
2803 | valid_p = 1; | |
2804 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
2805 | valid_p | |
2806 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2807 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2808 | ||
2809 | /* Check for the control registers, but do not fail if they | |
2810 | are missing. */ | |
2811 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
2812 | tdesc_numbered_register (feature, tdesc_data, i, | |
2813 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2814 | ||
2815 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
2816 | valid_p | |
2817 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2818 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2819 | ||
2820 | if (!valid_p) | |
2821 | { | |
2822 | tdesc_data_cleanup (tdesc_data); | |
2823 | return NULL; | |
2824 | } | |
2825 | } | |
123dc839 | 2826 | } |
39bbf761 | 2827 | |
28e97307 DJ |
2828 | /* If we have an object to base this architecture on, try to determine |
2829 | its ABI. */ | |
39bbf761 | 2830 | |
28e97307 | 2831 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2832 | { |
6b26d61a | 2833 | int ei_osabi, e_flags; |
28e97307 | 2834 | |
4be87837 | 2835 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2836 | { |
4be87837 DJ |
2837 | case bfd_target_aout_flavour: |
2838 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2839 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2840 | break; |
97e03143 | 2841 | |
4be87837 DJ |
2842 | case bfd_target_coff_flavour: |
2843 | /* Assume it's an old APCS-style ABI. */ | |
2844 | /* XXX WinCE? */ | |
28e97307 DJ |
2845 | arm_abi = ARM_ABI_APCS; |
2846 | break; | |
2847 | ||
2848 | case bfd_target_elf_flavour: | |
2849 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
2850 | e_flags = elf_elfheader (info.abfd)->e_flags; |
2851 | ||
28e97307 DJ |
2852 | if (ei_osabi == ELFOSABI_ARM) |
2853 | { | |
2854 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
2855 | objects. There's nowhere to tag an EABI version |
2856 | anyway, so assume APCS. */ | |
28e97307 DJ |
2857 | arm_abi = ARM_ABI_APCS; |
2858 | } | |
2859 | else if (ei_osabi == ELFOSABI_NONE) | |
2860 | { | |
6b26d61a | 2861 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
2862 | |
2863 | switch (eabi_ver) | |
2864 | { | |
2865 | case EF_ARM_EABI_UNKNOWN: | |
2866 | /* Assume GNU tools. */ | |
2867 | arm_abi = ARM_ABI_APCS; | |
2868 | break; | |
2869 | ||
2870 | case EF_ARM_EABI_VER4: | |
625b5003 | 2871 | case EF_ARM_EABI_VER5: |
28e97307 | 2872 | arm_abi = ARM_ABI_AAPCS; |
2af48f68 PB |
2873 | /* EABI binaries default to VFP float ordering. */ |
2874 | if (fp_model == ARM_FLOAT_AUTO) | |
2875 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2876 | break; |
2877 | ||
2878 | default: | |
6b26d61a | 2879 | /* Leave it as "auto". */ |
28e97307 | 2880 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
2881 | break; |
2882 | } | |
2883 | } | |
2884 | ||
2885 | if (fp_model == ARM_FLOAT_AUTO) | |
2886 | { | |
2887 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2888 | ||
2889 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
2890 | { | |
2891 | case 0: | |
2892 | /* Leave it as "auto". Strictly speaking this case | |
2893 | means FPA, but almost nobody uses that now, and | |
2894 | many toolchains fail to set the appropriate bits | |
2895 | for the floating-point model they use. */ | |
2896 | break; | |
2897 | case EF_ARM_SOFT_FLOAT: | |
2898 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2899 | break; | |
2900 | case EF_ARM_VFP_FLOAT: | |
2901 | fp_model = ARM_FLOAT_VFP; | |
2902 | break; | |
2903 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
2904 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2905 | break; |
2906 | } | |
2907 | } | |
4be87837 | 2908 | break; |
97e03143 | 2909 | |
4be87837 | 2910 | default: |
28e97307 | 2911 | /* Leave it as "auto". */ |
50ceaba5 | 2912 | break; |
97e03143 RE |
2913 | } |
2914 | } | |
2915 | ||
28e97307 DJ |
2916 | /* If there is already a candidate, use it. */ |
2917 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2918 | best_arch != NULL; | |
2919 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2920 | { | |
b8926edc DJ |
2921 | if (arm_abi != ARM_ABI_AUTO |
2922 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
2923 | continue; |
2924 | ||
b8926edc DJ |
2925 | if (fp_model != ARM_FLOAT_AUTO |
2926 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
2927 | continue; |
2928 | ||
2929 | /* Found a match. */ | |
2930 | break; | |
2931 | } | |
97e03143 | 2932 | |
28e97307 | 2933 | if (best_arch != NULL) |
123dc839 DJ |
2934 | { |
2935 | if (tdesc_data != NULL) | |
2936 | tdesc_data_cleanup (tdesc_data); | |
2937 | return best_arch->gdbarch; | |
2938 | } | |
28e97307 DJ |
2939 | |
2940 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2941 | gdbarch = gdbarch_alloc (&info, tdep); |
2942 | ||
28e97307 DJ |
2943 | /* Record additional information about the architecture we are defining. |
2944 | These are gdbarch discriminators, like the OSABI. */ | |
2945 | tdep->arm_abi = arm_abi; | |
2946 | tdep->fp_model = fp_model; | |
ff6f572f | 2947 | tdep->have_fpa_registers = have_fpa_registers; |
08216dd7 RE |
2948 | |
2949 | /* Breakpoints. */ | |
67255d04 RE |
2950 | switch (info.byte_order) |
2951 | { | |
2952 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2953 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2954 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2955 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2956 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2957 | ||
67255d04 RE |
2958 | break; |
2959 | ||
2960 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2961 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2962 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2963 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2964 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2965 | ||
67255d04 RE |
2966 | break; |
2967 | ||
2968 | default: | |
2969 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2970 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2971 | } |
2972 | ||
d7b486e7 RE |
2973 | /* On ARM targets char defaults to unsigned. */ |
2974 | set_gdbarch_char_signed (gdbarch, 0); | |
2975 | ||
9df628e0 | 2976 | /* This should be low enough for everything. */ |
97e03143 | 2977 | tdep->lowest_pc = 0x20; |
94c30b78 | 2978 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2979 | |
7c00367c MK |
2980 | /* The default, for both APCS and AAPCS, is to return small |
2981 | structures in registers. */ | |
2982 | tdep->struct_return = reg_struct_return; | |
2983 | ||
2dd604e7 | 2984 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 2985 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 2986 | |
756fe439 DJ |
2987 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2988 | ||
148754e5 | 2989 | /* Frame handling. */ |
eb5492fa DJ |
2990 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2991 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2992 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2993 | ||
eb5492fa | 2994 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2995 | |
34e8f22d RE |
2996 | /* Address manipulation. */ |
2997 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2998 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2999 | ||
34e8f22d RE |
3000 | /* Advance PC across function entry code. */ |
3001 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
3002 | ||
190dce09 UW |
3003 | /* Skip trampolines. */ |
3004 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
3005 | ||
34e8f22d RE |
3006 | /* The stack grows downward. */ |
3007 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3008 | ||
3009 | /* Breakpoint manipulation. */ | |
3010 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
3011 | |
3012 | /* Information about registers, etc. */ | |
0ba6dca9 | 3013 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
3014 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
3015 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 3016 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 3017 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 3018 | |
ff6f572f DJ |
3019 | /* This "info float" is FPA-specific. Use the generic version if we |
3020 | do not have FPA. */ | |
3021 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
3022 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
3023 | ||
26216b98 | 3024 | /* Internal <-> external register number maps. */ |
ff6f572f DJ |
3025 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
3026 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); | |
26216b98 AC |
3027 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
3028 | ||
34e8f22d RE |
3029 | set_gdbarch_register_name (gdbarch, arm_register_name); |
3030 | ||
3031 | /* Returning results. */ | |
2af48f68 | 3032 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 3033 | |
03d48a7d RE |
3034 | /* Disassembly. */ |
3035 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
3036 | ||
34e8f22d RE |
3037 | /* Minsymbol frobbing. */ |
3038 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
3039 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
3040 | arm_coff_make_msymbol_special); | |
3041 | ||
0d5de010 DJ |
3042 | /* Virtual tables. */ |
3043 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3044 | ||
97e03143 | 3045 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 3046 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 3047 | |
eb5492fa | 3048 | /* Add some default predicates. */ |
909cf6ea | 3049 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
842e1f1e | 3050 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
3051 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
3052 | ||
97e03143 RE |
3053 | /* Now we have tuned the configuration, set a few final things, |
3054 | based on what the OS ABI has told us. */ | |
3055 | ||
b8926edc DJ |
3056 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
3057 | binaries are always marked. */ | |
3058 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
3059 | tdep->arm_abi = ARM_ABI_APCS; | |
3060 | ||
3061 | /* We used to default to FPA for generic ARM, but almost nobody | |
3062 | uses that now, and we now provide a way for the user to force | |
3063 | the model. So default to the most useful variant. */ | |
3064 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
3065 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
3066 | ||
9df628e0 RE |
3067 | if (tdep->jb_pc >= 0) |
3068 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3069 | ||
08216dd7 | 3070 | /* Floating point sizes and format. */ |
8da61cc4 | 3071 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 3072 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 3073 | { |
8da61cc4 DJ |
3074 | set_gdbarch_double_format |
3075 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3076 | set_gdbarch_long_double_format | |
3077 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3078 | } | |
3079 | else | |
3080 | { | |
3081 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
3082 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
3083 | } |
3084 | ||
123dc839 | 3085 | if (tdesc_data) |
7cc46491 | 3086 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
123dc839 DJ |
3087 | |
3088 | /* Add standard register aliases. We add aliases even for those | |
3089 | nanes which are used by the current architecture - it's simpler, | |
3090 | and does no harm, since nothing ever lists user registers. */ | |
3091 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
3092 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
3093 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
3094 | ||
39bbf761 RE |
3095 | return gdbarch; |
3096 | } | |
3097 | ||
97e03143 | 3098 | static void |
2af46ca0 | 3099 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 3100 | { |
2af46ca0 | 3101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
3102 | |
3103 | if (tdep == NULL) | |
3104 | return; | |
3105 | ||
edefbb7c | 3106 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
3107 | (unsigned long) tdep->lowest_pc); |
3108 | } | |
3109 | ||
a78f21af AC |
3110 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
3111 | ||
c906108c | 3112 | void |
ed9a39eb | 3113 | _initialize_arm_tdep (void) |
c906108c | 3114 | { |
bc90b915 FN |
3115 | struct ui_file *stb; |
3116 | long length; | |
26304000 | 3117 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
3118 | const char *setname; |
3119 | const char *setdesc; | |
4bd7b427 | 3120 | const char *const *regnames; |
bc90b915 FN |
3121 | int numregs, i, j; |
3122 | static char *helptext; | |
edefbb7c AC |
3123 | char regdesc[1024], *rdptr = regdesc; |
3124 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 3125 | |
42cf1509 | 3126 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 3127 | |
70f80edf JT |
3128 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3129 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3130 | bfd_target_elf_flavour, | |
3131 | arm_elf_osabi_sniffer); | |
3132 | ||
94c30b78 | 3133 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3134 | num_disassembly_options = get_arm_regname_num_options (); |
3135 | ||
3136 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3137 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 3138 | _("Various ARM-specific commands."), |
afd7eef0 RE |
3139 | &setarmcmdlist, "set arm ", 0, &setlist); |
3140 | ||
3141 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 3142 | _("Various ARM-specific commands."), |
afd7eef0 | 3143 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 3144 | |
94c30b78 | 3145 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3146 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3147 | |
eefe576e AC |
3148 | /* Initialize the array that will be passed to |
3149 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
3150 | valid_disassembly_styles |
3151 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3152 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3153 | { |
3154 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3155 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
3156 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
3157 | rdptr += length; | |
3158 | rest -= length; | |
123dc839 DJ |
3159 | /* When we find the default names, tell the disassembler to use |
3160 | them. */ | |
bc90b915 FN |
3161 | if (!strcmp (setname, "std")) |
3162 | { | |
afd7eef0 | 3163 | disassembly_style = setname; |
bc90b915 FN |
3164 | set_arm_regname_option (i); |
3165 | } | |
3166 | } | |
94c30b78 | 3167 | /* Mark the end of valid options. */ |
afd7eef0 | 3168 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3169 | |
edefbb7c AC |
3170 | /* Create the help text. */ |
3171 | stb = mem_fileopen (); | |
3172 | fprintf_unfiltered (stb, "%s%s%s", | |
3173 | _("The valid values are:\n"), | |
3174 | regdesc, | |
3175 | _("The default is \"std\".")); | |
bc90b915 FN |
3176 | helptext = ui_file_xstrdup (stb, &length); |
3177 | ui_file_delete (stb); | |
ed9a39eb | 3178 | |
edefbb7c AC |
3179 | add_setshow_enum_cmd("disassembler", no_class, |
3180 | valid_disassembly_styles, &disassembly_style, | |
3181 | _("Set the disassembly style."), | |
3182 | _("Show the disassembly style."), | |
3183 | helptext, | |
2c5b56ce | 3184 | set_disassembly_style_sfunc, |
7915a72c | 3185 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 3186 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
3187 | |
3188 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3189 | _("Set usage of ARM 32-bit mode."), | |
3190 | _("Show usage of ARM 32-bit mode."), | |
3191 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 3192 | NULL, |
7915a72c | 3193 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 3194 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 3195 | |
fd50bc42 | 3196 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
3197 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
3198 | _("Set the floating point type."), | |
3199 | _("Show the floating point type."), | |
3200 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
3201 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
3202 | fpa - FPA co-processor (GCC compiled).\n\ | |
3203 | softvfp - Software FP with pure-endian doubles.\n\ | |
3204 | vfp - VFP co-processor."), | |
edefbb7c | 3205 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 3206 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 3207 | |
28e97307 DJ |
3208 | /* Add a command to allow the user to force the ABI. */ |
3209 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
3210 | _("Set the ABI."), | |
3211 | _("Show the ABI."), | |
3212 | NULL, arm_set_abi, arm_show_abi, | |
3213 | &setarmcmdlist, &showarmcmdlist); | |
3214 | ||
6529d2dd | 3215 | /* Debugging flag. */ |
edefbb7c AC |
3216 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3217 | _("Set ARM debugging."), | |
3218 | _("Show ARM debugging."), | |
3219 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 3220 | NULL, |
7915a72c | 3221 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 3222 | &setdebuglist, &showdebuglist); |
c906108c | 3223 | } |