Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 AC |
2 | |
3 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, | |
4 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c | 22 | |
34e8f22d RE |
23 | #include <ctype.h> /* XXX for isupper () */ |
24 | ||
c906108c SS |
25 | #include "defs.h" |
26 | #include "frame.h" | |
27 | #include "inferior.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
c906108c | 30 | #include "gdb_string.h" |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
4be87837 | 36 | #include "osabi.h" |
eb5492fa DJ |
37 | #include "frame-unwind.h" |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
842e1f1e DJ |
40 | #include "objfiles.h" |
41 | #include "dwarf2-frame.h" | |
34e8f22d RE |
42 | |
43 | #include "arm-tdep.h" | |
26216b98 | 44 | #include "gdb/sim-arm.h" |
34e8f22d | 45 | |
082fc60d RE |
46 | #include "elf-bfd.h" |
47 | #include "coff/internal.h" | |
97e03143 | 48 | #include "elf/arm.h" |
c906108c | 49 | |
26216b98 AC |
50 | #include "gdb_assert.h" |
51 | ||
6529d2dd AC |
52 | static int arm_debug; |
53 | ||
2a451106 KB |
54 | /* Each OS has a different mechanism for accessing the various |
55 | registers stored in the sigcontext structure. | |
56 | ||
57 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
58 | function pointer) which may be used to determine the addresses | |
59 | of the various saved registers in the sigcontext structure. | |
60 | ||
61 | For the ARM target, there are three parameters to this function. | |
62 | The first is the pc value of the frame under consideration, the | |
63 | second the stack pointer of this frame, and the last is the | |
64 | register number to fetch. | |
65 | ||
66 | If the tm.h file does not define this macro, then it's assumed that | |
67 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
68 | be 0. | |
69 | ||
70 | When it comes time to multi-arching this code, see the identically | |
71 | named machinery in ia64-tdep.c for an example of how it could be | |
72 | done. It should not be necessary to modify the code below where | |
73 | this macro is used. */ | |
74 | ||
3bb04bdd AC |
75 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
76 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
78 | #endif | |
79 | #else | |
80 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
81 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
82 | #endif |
83 | ||
082fc60d RE |
84 | /* Macros for setting and testing a bit in a minimal symbol that marks |
85 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 86 | is used for this purpose. |
082fc60d RE |
87 | |
88 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 89 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
90 | |
91 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
92 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
93 | | 0x80000000) | |
94 | ||
95 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
96 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
97 | ||
afd7eef0 RE |
98 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
99 | static struct cmd_list_element *setarmcmdlist = NULL; | |
100 | static struct cmd_list_element *showarmcmdlist = NULL; | |
101 | ||
fd50bc42 RE |
102 | /* The type of floating-point to use. Keep this in sync with enum |
103 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
104 | static const char *fp_model_strings[] = | |
105 | { | |
106 | "auto", | |
107 | "softfpa", | |
108 | "fpa", | |
109 | "softvfp", | |
28e97307 DJ |
110 | "vfp", |
111 | NULL | |
fd50bc42 RE |
112 | }; |
113 | ||
114 | /* A variable that can be configured by the user. */ | |
115 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
116 | static const char *current_fp_model = "auto"; | |
117 | ||
28e97307 DJ |
118 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
119 | static const char *arm_abi_strings[] = | |
120 | { | |
121 | "auto", | |
122 | "APCS", | |
123 | "AAPCS", | |
124 | NULL | |
125 | }; | |
126 | ||
127 | /* A variable that can be configured by the user. */ | |
128 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
129 | static const char *arm_abi_string = "auto"; | |
130 | ||
94c30b78 | 131 | /* Number of different reg name sets (options). */ |
afd7eef0 | 132 | static int num_disassembly_options; |
bc90b915 FN |
133 | |
134 | /* We have more registers than the disassembler as gdb can print the value | |
135 | of special registers as well. | |
136 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 137 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 138 | |
94c30b78 | 139 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 140 | static char * arm_register_name_strings[] = |
da59e081 JM |
141 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
142 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
143 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
144 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
145 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
146 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 147 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 148 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 149 | |
afd7eef0 RE |
150 | /* Valid register name styles. */ |
151 | static const char **valid_disassembly_styles; | |
ed9a39eb | 152 | |
afd7eef0 RE |
153 | /* Disassembly style to use. Default to "std" register names. */ |
154 | static const char *disassembly_style; | |
94c30b78 | 155 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 156 | static int current_option; |
96baa820 | 157 | |
ed9a39eb | 158 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
159 | style. */ |
160 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 161 | struct cmd_list_element *); |
afd7eef0 | 162 | static void set_disassembly_style (void); |
ed9a39eb | 163 | |
b508a996 RE |
164 | static void convert_from_extended (const struct floatformat *, const void *, |
165 | void *); | |
166 | static void convert_to_extended (const struct floatformat *, void *, | |
167 | const void *); | |
ed9a39eb | 168 | |
9b8d791a | 169 | struct arm_prologue_cache |
c3b4394c | 170 | { |
eb5492fa DJ |
171 | /* The stack pointer at the time this frame was created; i.e. the |
172 | caller's stack pointer when this function was called. It is used | |
173 | to identify this frame. */ | |
174 | CORE_ADDR prev_sp; | |
175 | ||
176 | /* The frame base for this frame is just prev_sp + frame offset - | |
177 | frame size. FRAMESIZE is the size of this stack frame, and | |
178 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
179 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
180 | ||
c3b4394c RE |
181 | int framesize; |
182 | int frameoffset; | |
eb5492fa DJ |
183 | |
184 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 185 | int framereg; |
eb5492fa DJ |
186 | |
187 | /* Saved register offsets. */ | |
188 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 189 | }; |
ed9a39eb | 190 | |
bc90b915 FN |
191 | /* Addresses for calling Thumb functions have the bit 0 set. |
192 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
193 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
194 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
195 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
196 | ||
94c30b78 | 197 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
198 | |
199 | int arm_apcs_32 = 1; | |
200 | ||
ed9a39eb JM |
201 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
202 | function. */ | |
c906108c | 203 | |
34e8f22d | 204 | int |
2a451106 | 205 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 206 | { |
c5aa993b | 207 | struct minimal_symbol *sym; |
c906108c | 208 | |
ed9a39eb | 209 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
210 | if (IS_THUMB_ADDR (memaddr)) |
211 | return 1; | |
212 | ||
ed9a39eb | 213 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
214 | sym = lookup_minimal_symbol_by_pc (memaddr); |
215 | if (sym) | |
216 | { | |
c5aa993b | 217 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
218 | } |
219 | else | |
ed9a39eb JM |
220 | { |
221 | return 0; | |
222 | } | |
c906108c SS |
223 | } |
224 | ||
181c1381 | 225 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 226 | static CORE_ADDR |
ed9a39eb | 227 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 228 | { |
a3a2ee65 JT |
229 | if (arm_apcs_32) |
230 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 231 | else |
a3a2ee65 | 232 | return (val & 0x03fffffc); |
c906108c SS |
233 | } |
234 | ||
181c1381 RE |
235 | /* When reading symbols, we need to zap the low bit of the address, |
236 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 237 | static CORE_ADDR |
181c1381 RE |
238 | arm_smash_text_address (CORE_ADDR val) |
239 | { | |
240 | return val & ~1; | |
241 | } | |
242 | ||
34e8f22d RE |
243 | /* Immediately after a function call, return the saved pc. Can't |
244 | always go through the frames for this because on some machines the | |
245 | new frame is not set up until the new function executes some | |
246 | instructions. */ | |
247 | ||
248 | static CORE_ADDR | |
ed9a39eb | 249 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 250 | { |
34e8f22d | 251 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
252 | } |
253 | ||
254 | /* A typical Thumb prologue looks like this: | |
c5aa993b JM |
255 | push {r7, lr} |
256 | add sp, sp, #-28 | |
257 | add r7, sp, #12 | |
c906108c | 258 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
259 | mov r7, sp |
260 | ||
261 | or like this: | |
262 | push {r7, lr} | |
263 | mov r7, sp | |
264 | sub sp, #12 | |
265 | ||
266 | or, on tpcs, like this: | |
267 | sub sp,#16 | |
268 | push {r7, lr} | |
269 | (many instructions) | |
270 | mov r7, sp | |
271 | sub sp, #12 | |
272 | ||
273 | There is always one instruction of three classes: | |
274 | 1 - push | |
275 | 2 - setting of r7 | |
276 | 3 - adjusting of sp | |
277 | ||
278 | When we have found at least one of each class we are done with the prolog. | |
279 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 280 | */ |
c906108c SS |
281 | |
282 | static CORE_ADDR | |
c7885828 | 283 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
284 | { |
285 | CORE_ADDR current_pc; | |
da3c6d4a MS |
286 | /* findmask: |
287 | bit 0 - push { rlist } | |
288 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
289 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
290 | */ | |
291 | int findmask = 0; | |
292 | ||
94c30b78 MS |
293 | for (current_pc = pc; |
294 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 295 | current_pc += 2) |
c906108c SS |
296 | { |
297 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
298 | ||
94c30b78 | 299 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 300 | { |
94c30b78 | 301 | findmask |= 1; /* push found */ |
da59e081 | 302 | } |
da3c6d4a MS |
303 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
304 | sub sp, #simm */ | |
da59e081 | 305 | { |
94c30b78 | 306 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
307 | continue; |
308 | else | |
94c30b78 | 309 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
310 | } |
311 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
312 | { | |
94c30b78 | 313 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
314 | } |
315 | else if (insn == 0x466f) /* mov r7, sp */ | |
316 | { | |
94c30b78 | 317 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 318 | } |
3d74b771 FF |
319 | else if (findmask == (4+2+1)) |
320 | { | |
da3c6d4a MS |
321 | /* We have found one of each type of prologue instruction */ |
322 | break; | |
3d74b771 | 323 | } |
da59e081 | 324 | else |
94c30b78 | 325 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 326 | instruction from outside the prolog scheduled here for |
94c30b78 | 327 | optimization. */ |
da3c6d4a | 328 | continue; |
c906108c SS |
329 | } |
330 | ||
331 | return current_pc; | |
332 | } | |
333 | ||
da3c6d4a MS |
334 | /* Advance the PC across any function entry prologue instructions to |
335 | reach some "real" code. | |
34e8f22d RE |
336 | |
337 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 338 | prologue: |
c906108c | 339 | |
c5aa993b JM |
340 | mov ip, sp |
341 | [stmfd sp!, {a1,a2,a3,a4}] | |
342 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
343 | [stfe f7, [sp, #-12]!] |
344 | [stfe f6, [sp, #-12]!] | |
345 | [stfe f5, [sp, #-12]!] | |
346 | [stfe f4, [sp, #-12]!] | |
347 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 348 | |
34e8f22d | 349 | static CORE_ADDR |
ed9a39eb | 350 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
351 | { |
352 | unsigned long inst; | |
353 | CORE_ADDR skip_pc; | |
b8d5e71d | 354 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 355 | char *func_name; |
c906108c SS |
356 | struct symtab_and_line sal; |
357 | ||
848cfffb | 358 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 359 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
360 | return pc; |
361 | ||
96baa820 | 362 | /* See what the symbol table says. */ |
ed9a39eb | 363 | |
50f6fb4b | 364 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 365 | { |
50f6fb4b CV |
366 | struct symbol *sym; |
367 | ||
368 | /* Found a function. */ | |
176620f1 | 369 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
370 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
371 | { | |
94c30b78 | 372 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
373 | sal = find_pc_line (func_addr, 0); |
374 | if ((sal.line != 0) && (sal.end < func_end)) | |
375 | return sal.end; | |
376 | } | |
c906108c SS |
377 | } |
378 | ||
379 | /* Check if this is Thumb code. */ | |
380 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 381 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
382 | |
383 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 384 | by disassembling the instructions. */ |
c906108c | 385 | |
b8d5e71d MS |
386 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
387 | if (func_end == 0 || func_end > pc + 64) | |
388 | func_end = pc + 64; | |
c906108c | 389 | |
b8d5e71d | 390 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 391 | { |
f43845b3 | 392 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 393 | |
b8d5e71d MS |
394 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
395 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
396 | continue; | |
c906108c | 397 | |
28cd8767 JG |
398 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
399 | continue; | |
400 | ||
401 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
402 | continue; | |
403 | ||
b8d5e71d MS |
404 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
405 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
406 | continue; | |
c906108c | 407 | |
b8d5e71d MS |
408 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
409 | continue; | |
c906108c | 410 | |
b8d5e71d MS |
411 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
412 | continue; | |
11d3b27d | 413 | |
b8d5e71d MS |
414 | /* Any insns after this point may float into the code, if it makes |
415 | for better instruction scheduling, so we skip them only if we | |
416 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 417 | |
b8d5e71d MS |
418 | /* We may have either one sfmfd instruction here, or several stfe |
419 | insns, depending on the version of floating point code we | |
420 | support. */ | |
421 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
422 | continue; | |
423 | ||
424 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
425 | continue; | |
426 | ||
427 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
428 | continue; | |
429 | ||
430 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
431 | continue; | |
432 | ||
433 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
434 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
435 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
436 | continue; | |
437 | ||
438 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
439 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
440 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
441 | continue; | |
442 | ||
443 | /* Un-recognized instruction; stop scanning. */ | |
444 | break; | |
f43845b3 | 445 | } |
c906108c | 446 | |
b8d5e71d | 447 | return skip_pc; /* End of prologue */ |
c906108c | 448 | } |
94c30b78 | 449 | |
c5aa993b | 450 | /* *INDENT-OFF* */ |
c906108c SS |
451 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
452 | This function decodes a Thumb function prologue to determine: | |
453 | 1) the size of the stack frame | |
454 | 2) which registers are saved on it | |
455 | 3) the offsets of saved regs | |
456 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 457 | |
da59e081 JM |
458 | A typical Thumb function prologue would create this stack frame |
459 | (offsets relative to FP) | |
c906108c SS |
460 | old SP -> 24 stack parameters |
461 | 20 LR | |
462 | 16 R7 | |
463 | R7 -> 0 local variables (16 bytes) | |
464 | SP -> -12 additional stack space (12 bytes) | |
465 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
466 | 12 bytes. The frame register is R7. |
467 | ||
da3c6d4a MS |
468 | The comments for thumb_skip_prolog() describe the algorithm we use |
469 | to detect the end of the prolog. */ | |
c5aa993b JM |
470 | /* *INDENT-ON* */ |
471 | ||
c906108c | 472 | static void |
eb5492fa | 473 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
474 | { |
475 | CORE_ADDR prologue_start; | |
476 | CORE_ADDR prologue_end; | |
477 | CORE_ADDR current_pc; | |
94c30b78 | 478 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
479 | int saved_reg[16]; |
480 | /* findmask: | |
481 | bit 0 - push { rlist } | |
482 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
483 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
484 | */ | |
485 | int findmask = 0; | |
c5aa993b | 486 | int i; |
c906108c | 487 | |
eb5492fa | 488 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
489 | { |
490 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
491 | ||
94c30b78 | 492 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 493 | prologue_end = prev_pc; |
c906108c | 494 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 495 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
496 | } |
497 | else | |
da3c6d4a MS |
498 | /* We're in the boondocks: allow for |
499 | 16 pushes, an add, and "mv fp,sp". */ | |
500 | prologue_end = prologue_start + 40; | |
c906108c | 501 | |
eb5492fa | 502 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
503 | |
504 | /* Initialize the saved register map. When register H is copied to | |
505 | register L, we will put H in saved_reg[L]. */ | |
506 | for (i = 0; i < 16; i++) | |
507 | saved_reg[i] = i; | |
508 | ||
509 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
510 | frame pointer, adjust the stack pointer, and save registers. |
511 | Do this until all basic prolog instructions are found. */ | |
c906108c | 512 | |
9b8d791a | 513 | cache->framesize = 0; |
da59e081 JM |
514 | for (current_pc = prologue_start; |
515 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
516 | current_pc += 2) | |
c906108c SS |
517 | { |
518 | unsigned short insn; | |
519 | int regno; | |
520 | int offset; | |
521 | ||
522 | insn = read_memory_unsigned_integer (current_pc, 2); | |
523 | ||
c5aa993b | 524 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 525 | { |
da59e081 | 526 | int mask; |
94c30b78 | 527 | findmask |= 1; /* push found */ |
c906108c SS |
528 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
529 | whether to save LR (R14). */ | |
da59e081 | 530 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 531 | |
b8d5e71d | 532 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 533 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 534 | if (mask & (1 << regno)) |
c5aa993b | 535 | { |
9b8d791a | 536 | cache->framesize += 4; |
eb5492fa | 537 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
538 | /* Reset saved register map. */ |
539 | saved_reg[regno] = regno; | |
c906108c SS |
540 | } |
541 | } | |
da3c6d4a MS |
542 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
543 | sub sp, #simm */ | |
c906108c | 544 | { |
b8d5e71d | 545 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
546 | continue; |
547 | else | |
94c30b78 | 548 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 549 | |
94c30b78 MS |
550 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
551 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 552 | { |
9b8d791a | 553 | cache->frameoffset += offset; |
da59e081 JM |
554 | offset = -offset; |
555 | } | |
9b8d791a | 556 | cache->framesize -= offset; |
c906108c SS |
557 | } |
558 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
559 | { | |
94c30b78 | 560 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 561 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 562 | /* get scaled offset */ |
9b8d791a | 563 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 564 | } |
da59e081 | 565 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 566 | { |
94c30b78 | 567 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
568 | cache->framereg = THUMB_FP_REGNUM; |
569 | cache->frameoffset = 0; | |
34e8f22d | 570 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
571 | } |
572 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
573 | { | |
da3c6d4a | 574 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 575 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 576 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
577 | } |
578 | else | |
da3c6d4a MS |
579 | /* Something in the prolog that we don't care about or some |
580 | instruction from outside the prolog scheduled here for | |
581 | optimization. */ | |
582 | continue; | |
c906108c SS |
583 | } |
584 | } | |
585 | ||
ed9a39eb | 586 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
587 | 1) the size of the stack frame |
588 | 2) which registers are saved on it | |
589 | 3) the offsets of saved regs | |
590 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
591 | This information is stored in the "extra" fields of the frame_info. |
592 | ||
96baa820 JM |
593 | There are two basic forms for the ARM prologue. The fixed argument |
594 | function call will look like: | |
ed9a39eb JM |
595 | |
596 | mov ip, sp | |
597 | stmfd sp!, {fp, ip, lr, pc} | |
598 | sub fp, ip, #4 | |
599 | [sub sp, sp, #4] | |
96baa820 | 600 | |
c906108c | 601 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
602 | IP -> 4 (caller's stack) |
603 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
604 | -4 LR (return address in caller) | |
605 | -8 IP (copy of caller's SP) | |
606 | -12 FP (caller's FP) | |
607 | SP -> -28 Local variables | |
608 | ||
c906108c | 609 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
610 | 28 bytes. The stmfd call can also save any of the vN registers it |
611 | plans to use, which increases the frame size accordingly. | |
612 | ||
613 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
614 | because the ARM Store instructions always store PC + 8 when you read | |
615 | the PC register. | |
ed9a39eb | 616 | |
96baa820 JM |
617 | A variable argument function call will look like: |
618 | ||
ed9a39eb JM |
619 | mov ip, sp |
620 | stmfd sp!, {a1, a2, a3, a4} | |
621 | stmfd sp!, {fp, ip, lr, pc} | |
622 | sub fp, ip, #20 | |
623 | ||
96baa820 | 624 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
625 | IP -> 20 (caller's stack) |
626 | 16 A4 | |
627 | 12 A3 | |
628 | 8 A2 | |
629 | 4 A1 | |
630 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
631 | -4 LR (return address in caller) | |
632 | -8 IP (copy of caller's SP) | |
633 | -12 FP (caller's FP) | |
634 | SP -> -28 Local variables | |
96baa820 JM |
635 | |
636 | The frame size would thus be 48 bytes, and the frame offset would be | |
637 | 28 bytes. | |
638 | ||
639 | There is another potential complication, which is that the optimizer | |
640 | will try to separate the store of fp in the "stmfd" instruction from | |
641 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
642 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
643 | ||
644 | Also, note, the original version of the ARM toolchain claimed that there | |
645 | should be an | |
646 | ||
647 | instruction at the end of the prologue. I have never seen GCC produce | |
648 | this, and the ARM docs don't mention it. We still test for it below in | |
649 | case it happens... | |
ed9a39eb JM |
650 | |
651 | */ | |
c906108c SS |
652 | |
653 | static void | |
eb5492fa | 654 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 655 | { |
28cd8767 | 656 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 657 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 658 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 659 | |
c906108c | 660 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
661 | cache->framereg = ARM_SP_REGNUM; |
662 | cache->framesize = 0; | |
663 | cache->frameoffset = 0; | |
c906108c SS |
664 | |
665 | /* Check for Thumb prologue. */ | |
eb5492fa | 666 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 667 | { |
eb5492fa | 668 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
669 | return; |
670 | } | |
671 | ||
672 | /* Find the function prologue. If we can't find the function in | |
673 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 674 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 675 | { |
2a451106 KB |
676 | /* One way to find the end of the prologue (which works well |
677 | for unoptimized code) is to do the following: | |
678 | ||
679 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
680 | ||
681 | if (sal.line == 0) | |
eb5492fa | 682 | prologue_end = prev_pc; |
2a451106 KB |
683 | else if (sal.end < prologue_end) |
684 | prologue_end = sal.end; | |
685 | ||
686 | This mechanism is very accurate so long as the optimizer | |
687 | doesn't move any instructions from the function body into the | |
688 | prologue. If this happens, sal.end will be the last | |
689 | instruction in the first hunk of prologue code just before | |
690 | the first instruction that the scheduler has moved from | |
691 | the body to the prologue. | |
692 | ||
693 | In order to make sure that we scan all of the prologue | |
694 | instructions, we use a slightly less accurate mechanism which | |
695 | may scan more than necessary. To help compensate for this | |
696 | lack of accuracy, the prologue scanning loop below contains | |
697 | several clauses which'll cause the loop to terminate early if | |
698 | an implausible prologue instruction is encountered. | |
699 | ||
700 | The expression | |
701 | ||
702 | prologue_start + 64 | |
703 | ||
704 | is a suitable endpoint since it accounts for the largest | |
705 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 706 | the scheduler. */ |
2a451106 KB |
707 | |
708 | if (prologue_end > prologue_start + 64) | |
709 | { | |
94c30b78 | 710 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 711 | } |
c906108c SS |
712 | } |
713 | else | |
714 | { | |
eb5492fa DJ |
715 | /* We have no symbol information. Our only option is to assume this |
716 | function has a standard stack frame and the normal frame register. | |
717 | Then, we can find the value of our frame pointer on entrance to | |
718 | the callee (or at the present moment if this is the innermost frame). | |
719 | The value stored there should be the address of the stmfd + 8. */ | |
720 | CORE_ADDR frame_loc; | |
721 | LONGEST return_value; | |
722 | ||
723 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
724 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
725 | return; |
726 | else | |
727 | { | |
728 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 729 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 730 | } |
c906108c SS |
731 | } |
732 | ||
eb5492fa DJ |
733 | if (prev_pc < prologue_end) |
734 | prologue_end = prev_pc; | |
735 | ||
c906108c | 736 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 737 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 738 | |
96baa820 JM |
739 | Be careful, however, and if it doesn't look like a prologue, |
740 | don't try to scan it. If, for instance, a frameless function | |
741 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 742 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
743 | and other operations that rely on a knowledge of the stack |
744 | traceback. | |
745 | ||
746 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 747 | if we don't see this as the first insn, we will stop. |
c906108c | 748 | |
f43845b3 MS |
749 | [Note: This doesn't seem to be true any longer, so it's now an |
750 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 751 | |
f43845b3 MS |
752 | [Note further: The "mov ip,sp" only seems to be missing in |
753 | frameless functions at optimization level "-O2" or above, | |
754 | in which case it is often (but not always) replaced by | |
b8d5e71d | 755 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 756 | |
28cd8767 | 757 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 758 | |
94c30b78 MS |
759 | for (current_pc = prologue_start; |
760 | current_pc < prologue_end; | |
f43845b3 | 761 | current_pc += 4) |
96baa820 | 762 | { |
d4473757 KB |
763 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
764 | ||
94c30b78 | 765 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 766 | { |
28cd8767 JG |
767 | ip_offset = 0; |
768 | continue; | |
769 | } | |
770 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
771 | { | |
772 | unsigned imm = insn & 0xff; /* immediate value */ | |
773 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
774 | imm = (imm >> rot) | (imm << (32 - rot)); | |
775 | ip_offset = imm; | |
776 | continue; | |
777 | } | |
778 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
779 | { | |
780 | unsigned imm = insn & 0xff; /* immediate value */ | |
781 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
782 | imm = (imm >> rot) | (imm << (32 - rot)); | |
783 | ip_offset = -imm; | |
f43845b3 MS |
784 | continue; |
785 | } | |
94c30b78 | 786 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 787 | { |
e28a332c JG |
788 | sp_offset -= 4; |
789 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
790 | continue; |
791 | } | |
792 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
793 | /* stmfd sp!, {..., fp, ip, lr, pc} |
794 | or | |
795 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 796 | { |
d4473757 | 797 | int mask = insn & 0xffff; |
ed9a39eb | 798 | |
94c30b78 | 799 | /* Calculate offsets of saved registers. */ |
34e8f22d | 800 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
801 | if (mask & (1 << regno)) |
802 | { | |
803 | sp_offset -= 4; | |
eb5492fa | 804 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
805 | } |
806 | } | |
b8d5e71d MS |
807 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
808 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
809 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
810 | { | |
811 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
812 | continue; | |
813 | } | |
814 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
815 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
816 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
817 | { |
818 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
819 | continue; | |
820 | } | |
d4473757 KB |
821 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
822 | { | |
94c30b78 MS |
823 | unsigned imm = insn & 0xff; /* immediate value */ |
824 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 825 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 826 | fp_offset = -imm + ip_offset; |
9b8d791a | 827 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
828 | } |
829 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
830 | { | |
94c30b78 MS |
831 | unsigned imm = insn & 0xff; /* immediate value */ |
832 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
833 | imm = (imm >> rot) | (imm << (32 - rot)); |
834 | sp_offset -= imm; | |
835 | } | |
836 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
837 | { | |
838 | sp_offset -= 12; | |
34e8f22d | 839 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 840 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
841 | } |
842 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
843 | { | |
844 | int n_saved_fp_regs; | |
845 | unsigned int fp_start_reg, fp_bound_reg; | |
846 | ||
94c30b78 | 847 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 848 | { |
d4473757 KB |
849 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
850 | n_saved_fp_regs = 3; | |
851 | else | |
852 | n_saved_fp_regs = 1; | |
96baa820 | 853 | } |
d4473757 | 854 | else |
96baa820 | 855 | { |
d4473757 KB |
856 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
857 | n_saved_fp_regs = 2; | |
858 | else | |
859 | n_saved_fp_regs = 4; | |
96baa820 | 860 | } |
d4473757 | 861 | |
34e8f22d | 862 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
863 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
864 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
865 | { |
866 | sp_offset -= 12; | |
eb5492fa | 867 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 868 | } |
c906108c | 869 | } |
d4473757 | 870 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 871 | break; /* Condition not true, exit early */ |
b8d5e71d | 872 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 873 | break; /* Don't scan past a block load */ |
d4473757 KB |
874 | else |
875 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 876 | so we just skip what we don't recognize. */ |
d4473757 | 877 | continue; |
c906108c SS |
878 | } |
879 | ||
94c30b78 MS |
880 | /* The frame size is just the negative of the offset (from the |
881 | original SP) of the last thing thing we pushed on the stack. | |
882 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
883 | cache->framesize = -sp_offset; |
884 | if (cache->framereg == ARM_FP_REGNUM) | |
885 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 886 | else |
9b8d791a | 887 | cache->frameoffset = 0; |
c906108c SS |
888 | } |
889 | ||
eb5492fa DJ |
890 | static struct arm_prologue_cache * |
891 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 892 | { |
eb5492fa DJ |
893 | int reg; |
894 | struct arm_prologue_cache *cache; | |
895 | CORE_ADDR unwound_fp; | |
c5aa993b | 896 | |
eb5492fa DJ |
897 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
898 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 899 | |
eb5492fa | 900 | arm_scan_prologue (next_frame, cache); |
848cfffb | 901 | |
eb5492fa DJ |
902 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
903 | if (unwound_fp == 0) | |
904 | return cache; | |
c906108c | 905 | |
eb5492fa | 906 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 907 | |
eb5492fa DJ |
908 | /* Calculate actual addresses of saved registers using offsets |
909 | determined by arm_scan_prologue. */ | |
910 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 911 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
912 | cache->saved_regs[reg].addr += cache->prev_sp; |
913 | ||
914 | return cache; | |
c906108c SS |
915 | } |
916 | ||
eb5492fa DJ |
917 | /* Our frame ID for a normal frame is the current function's starting PC |
918 | and the caller's SP when we were called. */ | |
c906108c | 919 | |
148754e5 | 920 | static void |
eb5492fa DJ |
921 | arm_prologue_this_id (struct frame_info *next_frame, |
922 | void **this_cache, | |
923 | struct frame_id *this_id) | |
c906108c | 924 | { |
eb5492fa DJ |
925 | struct arm_prologue_cache *cache; |
926 | struct frame_id id; | |
927 | CORE_ADDR func; | |
f079148d | 928 | |
eb5492fa DJ |
929 | if (*this_cache == NULL) |
930 | *this_cache = arm_make_prologue_cache (next_frame); | |
931 | cache = *this_cache; | |
2a451106 | 932 | |
eb5492fa | 933 | func = frame_func_unwind (next_frame); |
2a451106 | 934 | |
eb5492fa DJ |
935 | /* This is meant to halt the backtrace at "_start". Make sure we |
936 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 937 | if (func <= LOWEST_PC) |
eb5492fa | 938 | return; |
5a203e44 | 939 | |
eb5492fa DJ |
940 | /* If we've hit a wall, stop. */ |
941 | if (cache->prev_sp == 0) | |
942 | return; | |
24de872b | 943 | |
eb5492fa | 944 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 945 | *this_id = id; |
c906108c SS |
946 | } |
947 | ||
eb5492fa DJ |
948 | static void |
949 | arm_prologue_prev_register (struct frame_info *next_frame, | |
950 | void **this_cache, | |
951 | int prev_regnum, | |
952 | int *optimized, | |
953 | enum lval_type *lvalp, | |
954 | CORE_ADDR *addrp, | |
955 | int *realnump, | |
9af75ef6 | 956 | gdb_byte *valuep) |
24de872b DJ |
957 | { |
958 | struct arm_prologue_cache *cache; | |
959 | ||
eb5492fa DJ |
960 | if (*this_cache == NULL) |
961 | *this_cache = arm_make_prologue_cache (next_frame); | |
962 | cache = *this_cache; | |
24de872b | 963 | |
eb5492fa DJ |
964 | /* If we are asked to unwind the PC, then we need to return the LR |
965 | instead. The saved value of PC points into this frame's | |
966 | prologue, not the next frame's resume location. */ | |
967 | if (prev_regnum == ARM_PC_REGNUM) | |
968 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 969 | |
eb5492fa DJ |
970 | /* SP is generally not saved to the stack, but this frame is |
971 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
972 | The value was already reconstructed into PREV_SP. */ | |
973 | if (prev_regnum == ARM_SP_REGNUM) | |
974 | { | |
975 | *lvalp = not_lval; | |
976 | if (valuep) | |
977 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
978 | return; | |
979 | } | |
980 | ||
1f67027d AC |
981 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
982 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
983 | } |
984 | ||
985 | struct frame_unwind arm_prologue_unwind = { | |
986 | NORMAL_FRAME, | |
987 | arm_prologue_this_id, | |
988 | arm_prologue_prev_register | |
989 | }; | |
990 | ||
991 | static const struct frame_unwind * | |
992 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
993 | { | |
994 | return &arm_prologue_unwind; | |
24de872b DJ |
995 | } |
996 | ||
909cf6ea DJ |
997 | static struct arm_prologue_cache * |
998 | arm_make_stub_cache (struct frame_info *next_frame) | |
999 | { | |
1000 | int reg; | |
1001 | struct arm_prologue_cache *cache; | |
1002 | CORE_ADDR unwound_fp; | |
1003 | ||
1004 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
1005 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1006 | ||
1007 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
1008 | ||
1009 | return cache; | |
1010 | } | |
1011 | ||
1012 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1013 | ||
1014 | static void | |
1015 | arm_stub_this_id (struct frame_info *next_frame, | |
1016 | void **this_cache, | |
1017 | struct frame_id *this_id) | |
1018 | { | |
1019 | struct arm_prologue_cache *cache; | |
1020 | ||
1021 | if (*this_cache == NULL) | |
1022 | *this_cache = arm_make_stub_cache (next_frame); | |
1023 | cache = *this_cache; | |
1024 | ||
1025 | *this_id = frame_id_build (cache->prev_sp, | |
1026 | frame_pc_unwind (next_frame)); | |
1027 | } | |
1028 | ||
1029 | struct frame_unwind arm_stub_unwind = { | |
1030 | NORMAL_FRAME, | |
1031 | arm_stub_this_id, | |
1032 | arm_prologue_prev_register | |
1033 | }; | |
1034 | ||
1035 | static const struct frame_unwind * | |
1036 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1037 | { | |
1038 | char dummy[4]; | |
1039 | ||
1040 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
1041 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
1042 | return &arm_stub_unwind; | |
1043 | ||
1044 | return NULL; | |
1045 | } | |
1046 | ||
24de872b | 1047 | static CORE_ADDR |
eb5492fa | 1048 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1049 | { |
1050 | struct arm_prologue_cache *cache; | |
1051 | ||
eb5492fa DJ |
1052 | if (*this_cache == NULL) |
1053 | *this_cache = arm_make_prologue_cache (next_frame); | |
1054 | cache = *this_cache; | |
1055 | ||
1056 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1057 | } |
1058 | ||
eb5492fa DJ |
1059 | struct frame_base arm_normal_base = { |
1060 | &arm_prologue_unwind, | |
1061 | arm_normal_frame_base, | |
1062 | arm_normal_frame_base, | |
1063 | arm_normal_frame_base | |
1064 | }; | |
1065 | ||
1066 | static struct arm_prologue_cache * | |
1067 | arm_make_sigtramp_cache (struct frame_info *next_frame) | |
24de872b DJ |
1068 | { |
1069 | struct arm_prologue_cache *cache; | |
eb5492fa DJ |
1070 | int reg; |
1071 | ||
1072 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
24de872b | 1073 | |
eb5492fa | 1074 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
24de872b | 1075 | |
eb5492fa | 1076 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
24de872b | 1077 | |
eb5492fa DJ |
1078 | for (reg = 0; reg < NUM_REGS; reg++) |
1079 | cache->saved_regs[reg].addr | |
1080 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, | |
1081 | frame_pc_unwind (next_frame), reg); | |
24de872b | 1082 | |
eb5492fa DJ |
1083 | /* FIXME: What about thumb mode? */ |
1084 | cache->framereg = ARM_SP_REGNUM; | |
1085 | cache->prev_sp | |
1086 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, | |
7a5ea0d4 | 1087 | register_size (current_gdbarch, cache->framereg)); |
eb5492fa DJ |
1088 | |
1089 | return cache; | |
24de872b | 1090 | } |
c906108c | 1091 | |
eb5492fa DJ |
1092 | static void |
1093 | arm_sigtramp_this_id (struct frame_info *next_frame, | |
1094 | void **this_cache, | |
1095 | struct frame_id *this_id) | |
1096 | { | |
1097 | struct arm_prologue_cache *cache; | |
c906108c | 1098 | |
eb5492fa DJ |
1099 | if (*this_cache == NULL) |
1100 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1101 | cache = *this_cache; | |
c906108c | 1102 | |
eb5492fa DJ |
1103 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
1104 | the sigtramp frame; the PC should be the beginning of the trampoline. */ | |
1105 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); | |
1106 | } | |
1107 | ||
1108 | static void | |
1109 | arm_sigtramp_prev_register (struct frame_info *next_frame, | |
1110 | void **this_cache, | |
1111 | int prev_regnum, | |
1112 | int *optimized, | |
1113 | enum lval_type *lvalp, | |
1114 | CORE_ADDR *addrp, | |
1115 | int *realnump, | |
9af75ef6 | 1116 | gdb_byte *valuep) |
c906108c | 1117 | { |
eb5492fa | 1118 | struct arm_prologue_cache *cache; |
848cfffb | 1119 | |
eb5492fa DJ |
1120 | if (*this_cache == NULL) |
1121 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1122 | cache = *this_cache; | |
1123 | ||
1f67027d AC |
1124 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
1125 | optimized, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1126 | } |
1127 | ||
eb5492fa DJ |
1128 | struct frame_unwind arm_sigtramp_unwind = { |
1129 | SIGTRAMP_FRAME, | |
1130 | arm_sigtramp_this_id, | |
1131 | arm_sigtramp_prev_register | |
1132 | }; | |
c906108c | 1133 | |
eb5492fa DJ |
1134 | static const struct frame_unwind * |
1135 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) | |
c906108c | 1136 | { |
eb5492fa | 1137 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
0b281939 | 1138 | && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0)) |
eb5492fa DJ |
1139 | return &arm_sigtramp_unwind; |
1140 | ||
1141 | return NULL; | |
c906108c SS |
1142 | } |
1143 | ||
eb5492fa DJ |
1144 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1145 | dummy frame. The frame ID's base needs to match the TOS value | |
1146 | saved by save_dummy_frame_tos() and returned from | |
1147 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1148 | breakpoint. */ | |
c906108c | 1149 | |
eb5492fa DJ |
1150 | static struct frame_id |
1151 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1152 | { |
eb5492fa DJ |
1153 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1154 | frame_pc_unwind (next_frame)); | |
1155 | } | |
c3b4394c | 1156 | |
eb5492fa DJ |
1157 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1158 | be used to construct the previous frame's ID, after looking up the | |
1159 | containing function). */ | |
c3b4394c | 1160 | |
eb5492fa DJ |
1161 | static CORE_ADDR |
1162 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1163 | { | |
1164 | CORE_ADDR pc; | |
1165 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1166 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1167 | } | |
1168 | ||
1169 | static CORE_ADDR | |
1170 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1171 | { | |
1172 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1173 | } |
1174 | ||
2dd604e7 RE |
1175 | /* When arguments must be pushed onto the stack, they go on in reverse |
1176 | order. The code below implements a FILO (stack) to do this. */ | |
1177 | ||
1178 | struct stack_item | |
1179 | { | |
1180 | int len; | |
1181 | struct stack_item *prev; | |
1182 | void *data; | |
1183 | }; | |
1184 | ||
1185 | static struct stack_item * | |
1186 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1187 | { | |
1188 | struct stack_item *si; | |
1189 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1190 | si->data = xmalloc (len); |
2dd604e7 RE |
1191 | si->len = len; |
1192 | si->prev = prev; | |
1193 | memcpy (si->data, contents, len); | |
1194 | return si; | |
1195 | } | |
1196 | ||
1197 | static struct stack_item * | |
1198 | pop_stack_item (struct stack_item *si) | |
1199 | { | |
1200 | struct stack_item *dead = si; | |
1201 | si = si->prev; | |
1202 | xfree (dead->data); | |
1203 | xfree (dead); | |
1204 | return si; | |
1205 | } | |
1206 | ||
1207 | /* We currently only support passing parameters in integer registers. This | |
1208 | conforms with GCC's default model. Several other variants exist and | |
1209 | we should probably support some of them based on the selected ABI. */ | |
1210 | ||
1211 | static CORE_ADDR | |
7d9b040b | 1212 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1213 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1214 | struct value **args, CORE_ADDR sp, int struct_return, | |
1215 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1216 | { |
1217 | int argnum; | |
1218 | int argreg; | |
1219 | int nstack; | |
1220 | struct stack_item *si = NULL; | |
1221 | ||
6a65450a AC |
1222 | /* Set the return address. For the ARM, the return breakpoint is |
1223 | always at BP_ADDR. */ | |
2dd604e7 | 1224 | /* XXX Fix for Thumb. */ |
6a65450a | 1225 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1226 | |
1227 | /* Walk through the list of args and determine how large a temporary | |
1228 | stack is required. Need to take care here as structs may be | |
1229 | passed on the stack, and we have to to push them. */ | |
1230 | nstack = 0; | |
1231 | ||
1232 | argreg = ARM_A1_REGNUM; | |
1233 | nstack = 0; | |
1234 | ||
1235 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1236 | is correctly aligned before we start. We always do this even if | |
1237 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1238 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1239 | |
1240 | /* The struct_return pointer occupies the first parameter | |
1241 | passing register. */ | |
1242 | if (struct_return) | |
1243 | { | |
1244 | if (arm_debug) | |
1245 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1246 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1247 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1248 | argreg++; | |
1249 | } | |
1250 | ||
1251 | for (argnum = 0; argnum < nargs; argnum++) | |
1252 | { | |
1253 | int len; | |
1254 | struct type *arg_type; | |
1255 | struct type *target_type; | |
1256 | enum type_code typecode; | |
0fd88904 | 1257 | bfd_byte *val; |
2dd604e7 | 1258 | |
df407dfe | 1259 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1260 | len = TYPE_LENGTH (arg_type); |
1261 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1262 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1263 | val = value_contents_writeable (args[argnum]); |
2dd604e7 RE |
1264 | |
1265 | /* If the argument is a pointer to a function, and it is a | |
1266 | Thumb function, create a LOCAL copy of the value and set | |
1267 | the THUMB bit in it. */ | |
1268 | if (TYPE_CODE_PTR == typecode | |
1269 | && target_type != NULL | |
1270 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1271 | { | |
7c0b4a20 | 1272 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1273 | if (arm_pc_is_thumb (regval)) |
1274 | { | |
1275 | val = alloca (len); | |
fbd9dcd3 | 1276 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1277 | } |
1278 | } | |
1279 | ||
1280 | /* Copy the argument to general registers or the stack in | |
1281 | register-sized pieces. Large arguments are split between | |
1282 | registers and stack. */ | |
1283 | while (len > 0) | |
1284 | { | |
b1e29e33 | 1285 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1286 | |
1287 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1288 | { | |
1289 | /* The argument is being passed in a general purpose | |
1290 | register. */ | |
7c0b4a20 | 1291 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1292 | if (arm_debug) |
1293 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1294 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1295 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1296 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1297 | argreg++; | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | /* Push the arguments onto the stack. */ | |
1302 | if (arm_debug) | |
1303 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1304 | argnum, nstack); | |
b1e29e33 AC |
1305 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1306 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1307 | } |
1308 | ||
1309 | len -= partial_len; | |
1310 | val += partial_len; | |
1311 | } | |
1312 | } | |
1313 | /* If we have an odd number of words to push, then decrement the stack | |
1314 | by one word now, so first stack argument will be dword aligned. */ | |
1315 | if (nstack & 4) | |
1316 | sp -= 4; | |
1317 | ||
1318 | while (si) | |
1319 | { | |
1320 | sp -= si->len; | |
1321 | write_memory (sp, si->data, si->len); | |
1322 | si = pop_stack_item (si); | |
1323 | } | |
1324 | ||
1325 | /* Finally, update teh SP register. */ | |
1326 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1327 | ||
1328 | return sp; | |
1329 | } | |
1330 | ||
c906108c | 1331 | static void |
ed9a39eb | 1332 | print_fpu_flags (int flags) |
c906108c | 1333 | { |
c5aa993b JM |
1334 | if (flags & (1 << 0)) |
1335 | fputs ("IVO ", stdout); | |
1336 | if (flags & (1 << 1)) | |
1337 | fputs ("DVZ ", stdout); | |
1338 | if (flags & (1 << 2)) | |
1339 | fputs ("OFL ", stdout); | |
1340 | if (flags & (1 << 3)) | |
1341 | fputs ("UFL ", stdout); | |
1342 | if (flags & (1 << 4)) | |
1343 | fputs ("INX ", stdout); | |
1344 | putchar ('\n'); | |
c906108c SS |
1345 | } |
1346 | ||
5e74b15c RE |
1347 | /* Print interesting information about the floating point processor |
1348 | (if present) or emulator. */ | |
34e8f22d | 1349 | static void |
d855c300 | 1350 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1351 | struct frame_info *frame, const char *args) |
c906108c | 1352 | { |
52f0bd74 | 1353 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1354 | int type; |
1355 | ||
1356 | type = (status >> 24) & 127; | |
edefbb7c AC |
1357 | if (status & (1 << 31)) |
1358 | printf (_("Hardware FPU type %d\n"), type); | |
1359 | else | |
1360 | printf (_("Software FPU type %d\n"), type); | |
1361 | /* i18n: [floating point unit] mask */ | |
1362 | fputs (_("mask: "), stdout); | |
c5aa993b | 1363 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1364 | /* i18n: [floating point unit] flags */ |
1365 | fputs (_("flags: "), stdout); | |
c5aa993b | 1366 | print_fpu_flags (status); |
c906108c SS |
1367 | } |
1368 | ||
34e8f22d RE |
1369 | /* Return the GDB type object for the "standard" data type of data in |
1370 | register N. */ | |
1371 | ||
1372 | static struct type * | |
7a5ea0d4 | 1373 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1374 | { |
34e8f22d | 1375 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1376 | { |
d7449b42 | 1377 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1378 | return builtin_type_arm_ext_big; |
1379 | else | |
1380 | return builtin_type_arm_ext_littlebyte_bigword; | |
1381 | } | |
1382 | else | |
1383 | return builtin_type_int32; | |
1384 | } | |
1385 | ||
34e8f22d RE |
1386 | /* Index within `registers' of the first byte of the space for |
1387 | register N. */ | |
1388 | ||
1389 | static int | |
1390 | arm_register_byte (int regnum) | |
1391 | { | |
1392 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1393 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1394 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1395 | return (NUM_GREGS * INT_REGISTER_SIZE |
1396 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1397 | else |
7a5ea0d4 DJ |
1398 | return (NUM_GREGS * INT_REGISTER_SIZE |
1399 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1400 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1401 | } | |
1402 | ||
26216b98 AC |
1403 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1404 | static int | |
1405 | arm_register_sim_regno (int regnum) | |
1406 | { | |
1407 | int reg = regnum; | |
1408 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1409 | ||
1410 | if (reg < NUM_GREGS) | |
1411 | return SIM_ARM_R0_REGNUM + reg; | |
1412 | reg -= NUM_GREGS; | |
1413 | ||
1414 | if (reg < NUM_FREGS) | |
1415 | return SIM_ARM_FP0_REGNUM + reg; | |
1416 | reg -= NUM_FREGS; | |
1417 | ||
1418 | if (reg < NUM_SREGS) | |
1419 | return SIM_ARM_FPS_REGNUM + reg; | |
1420 | reg -= NUM_SREGS; | |
1421 | ||
edefbb7c | 1422 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1423 | } |
34e8f22d | 1424 | |
a37b3cc0 AC |
1425 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1426 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1427 | It is thought that this is is the floating-point register format on | |
1428 | little-endian systems. */ | |
c906108c | 1429 | |
ed9a39eb | 1430 | static void |
b508a996 RE |
1431 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1432 | void *dbl) | |
c906108c | 1433 | { |
a37b3cc0 | 1434 | DOUBLEST d; |
d7449b42 | 1435 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1436 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1437 | else | |
1438 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1439 | ptr, &d); | |
b508a996 | 1440 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1441 | } |
1442 | ||
34e8f22d | 1443 | static void |
b508a996 | 1444 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1445 | { |
a37b3cc0 | 1446 | DOUBLEST d; |
b508a996 | 1447 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1448 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1449 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1450 | else | |
1451 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1452 | &d, dbl); | |
c906108c | 1453 | } |
ed9a39eb | 1454 | |
c906108c | 1455 | static int |
ed9a39eb | 1456 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1457 | { |
1458 | if (cond == INST_AL || cond == INST_NV) | |
1459 | return 1; | |
1460 | ||
1461 | switch (cond) | |
1462 | { | |
1463 | case INST_EQ: | |
1464 | return ((status_reg & FLAG_Z) != 0); | |
1465 | case INST_NE: | |
1466 | return ((status_reg & FLAG_Z) == 0); | |
1467 | case INST_CS: | |
1468 | return ((status_reg & FLAG_C) != 0); | |
1469 | case INST_CC: | |
1470 | return ((status_reg & FLAG_C) == 0); | |
1471 | case INST_MI: | |
1472 | return ((status_reg & FLAG_N) != 0); | |
1473 | case INST_PL: | |
1474 | return ((status_reg & FLAG_N) == 0); | |
1475 | case INST_VS: | |
1476 | return ((status_reg & FLAG_V) != 0); | |
1477 | case INST_VC: | |
1478 | return ((status_reg & FLAG_V) == 0); | |
1479 | case INST_HI: | |
1480 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1481 | case INST_LS: | |
1482 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1483 | case INST_GE: | |
1484 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1485 | case INST_LT: | |
1486 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1487 | case INST_GT: | |
1488 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1489 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1490 | case INST_LE: |
1491 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1492 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1493 | } |
1494 | return 1; | |
1495 | } | |
1496 | ||
9512d7fd | 1497 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1498 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1499 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1500 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1501 | #define sbits(obj,st,fn) \ | |
1502 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1503 | #define BranchDest(addr,instr) \ | |
1504 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1505 | #define ARM_PC_32 1 | |
1506 | ||
1507 | static unsigned long | |
ed9a39eb JM |
1508 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1509 | unsigned long status_reg) | |
c906108c SS |
1510 | { |
1511 | unsigned long res, shift; | |
1512 | int rm = bits (inst, 0, 3); | |
1513 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1514 | |
1515 | if (bit (inst, 4)) | |
c906108c SS |
1516 | { |
1517 | int rs = bits (inst, 8, 11); | |
1518 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1519 | } | |
1520 | else | |
1521 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1522 | |
1523 | res = (rm == 15 | |
c906108c | 1524 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1525 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1526 | : read_register (rm)); |
1527 | ||
1528 | switch (shifttype) | |
1529 | { | |
c5aa993b | 1530 | case 0: /* LSL */ |
c906108c SS |
1531 | res = shift >= 32 ? 0 : res << shift; |
1532 | break; | |
c5aa993b JM |
1533 | |
1534 | case 1: /* LSR */ | |
c906108c SS |
1535 | res = shift >= 32 ? 0 : res >> shift; |
1536 | break; | |
1537 | ||
c5aa993b JM |
1538 | case 2: /* ASR */ |
1539 | if (shift >= 32) | |
1540 | shift = 31; | |
c906108c SS |
1541 | res = ((res & 0x80000000L) |
1542 | ? ~((~res) >> shift) : res >> shift); | |
1543 | break; | |
1544 | ||
c5aa993b | 1545 | case 3: /* ROR/RRX */ |
c906108c SS |
1546 | shift &= 31; |
1547 | if (shift == 0) | |
1548 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1549 | else | |
c5aa993b | 1550 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1551 | break; |
1552 | } | |
1553 | ||
1554 | return res & 0xffffffff; | |
1555 | } | |
1556 | ||
c906108c SS |
1557 | /* Return number of 1-bits in VAL. */ |
1558 | ||
1559 | static int | |
ed9a39eb | 1560 | bitcount (unsigned long val) |
c906108c SS |
1561 | { |
1562 | int nbits; | |
1563 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1564 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1565 | return nbits; |
1566 | } | |
1567 | ||
34e8f22d | 1568 | CORE_ADDR |
ed9a39eb | 1569 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1570 | { |
c5aa993b | 1571 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1572 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1573 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1574 | unsigned long offset; |
1575 | ||
1576 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1577 | { | |
1578 | CORE_ADDR sp; | |
1579 | ||
1580 | /* Fetch the saved PC from the stack. It's stored above | |
1581 | all of the other registers. */ | |
b1e29e33 | 1582 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1583 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1584 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1585 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1586 | if (nextpc == pc) | |
edefbb7c | 1587 | error (_("Infinite loop detected")); |
c906108c SS |
1588 | } |
1589 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1590 | { | |
34e8f22d | 1591 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1592 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1593 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1594 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1595 | } | |
1596 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1597 | { | |
1598 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1599 | } | |
aa17d93e | 1600 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c SS |
1601 | { |
1602 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1603 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1604 | nextpc = pc_val + offset; |
aa17d93e DJ |
1605 | /* For BLX make sure to clear the low bits. */ |
1606 | if (bits (inst2, 11, 12) == 1) | |
1607 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1608 | } |
aa17d93e | 1609 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1610 | { |
1611 | if (bits (inst1, 3, 6) == 0x0f) | |
1612 | nextpc = pc_val; | |
1613 | else | |
1614 | nextpc = read_register (bits (inst1, 3, 6)); | |
1615 | ||
1616 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1617 | if (nextpc == pc) | |
edefbb7c | 1618 | error (_("Infinite loop detected")); |
9498281f | 1619 | } |
c906108c SS |
1620 | |
1621 | return nextpc; | |
1622 | } | |
1623 | ||
34e8f22d | 1624 | CORE_ADDR |
ed9a39eb | 1625 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1626 | { |
1627 | unsigned long pc_val; | |
1628 | unsigned long this_instr; | |
1629 | unsigned long status; | |
1630 | CORE_ADDR nextpc; | |
1631 | ||
1632 | if (arm_pc_is_thumb (pc)) | |
1633 | return thumb_get_next_pc (pc); | |
1634 | ||
1635 | pc_val = (unsigned long) pc; | |
1636 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1637 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1638 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1639 | |
1640 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1641 | { | |
1642 | switch (bits (this_instr, 24, 27)) | |
1643 | { | |
c5aa993b | 1644 | case 0x0: |
94c30b78 | 1645 | case 0x1: /* data processing */ |
c5aa993b JM |
1646 | case 0x2: |
1647 | case 0x3: | |
c906108c SS |
1648 | { |
1649 | unsigned long operand1, operand2, result = 0; | |
1650 | unsigned long rn; | |
1651 | int c; | |
c5aa993b | 1652 | |
c906108c SS |
1653 | if (bits (this_instr, 12, 15) != 15) |
1654 | break; | |
1655 | ||
1656 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1657 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1658 | error (_("Invalid update to pc in instruction")); |
c906108c | 1659 | |
9498281f DJ |
1660 | /* BX <reg>, BLX <reg> */ |
1661 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1662 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1663 | { | |
1664 | rn = bits (this_instr, 0, 3); | |
1665 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1666 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1667 | ||
1668 | if (nextpc == pc) | |
edefbb7c | 1669 | error (_("Infinite loop detected")); |
9498281f DJ |
1670 | |
1671 | return nextpc; | |
1672 | } | |
1673 | ||
c906108c SS |
1674 | /* Multiply into PC */ |
1675 | c = (status & FLAG_C) ? 1 : 0; | |
1676 | rn = bits (this_instr, 16, 19); | |
1677 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1678 | |
c906108c SS |
1679 | if (bit (this_instr, 25)) |
1680 | { | |
1681 | unsigned long immval = bits (this_instr, 0, 7); | |
1682 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1683 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1684 | & 0xffffffff; | |
c906108c | 1685 | } |
c5aa993b | 1686 | else /* operand 2 is a shifted register */ |
c906108c | 1687 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1688 | |
c906108c SS |
1689 | switch (bits (this_instr, 21, 24)) |
1690 | { | |
c5aa993b | 1691 | case 0x0: /*and */ |
c906108c SS |
1692 | result = operand1 & operand2; |
1693 | break; | |
1694 | ||
c5aa993b | 1695 | case 0x1: /*eor */ |
c906108c SS |
1696 | result = operand1 ^ operand2; |
1697 | break; | |
1698 | ||
c5aa993b | 1699 | case 0x2: /*sub */ |
c906108c SS |
1700 | result = operand1 - operand2; |
1701 | break; | |
1702 | ||
c5aa993b | 1703 | case 0x3: /*rsb */ |
c906108c SS |
1704 | result = operand2 - operand1; |
1705 | break; | |
1706 | ||
c5aa993b | 1707 | case 0x4: /*add */ |
c906108c SS |
1708 | result = operand1 + operand2; |
1709 | break; | |
1710 | ||
c5aa993b | 1711 | case 0x5: /*adc */ |
c906108c SS |
1712 | result = operand1 + operand2 + c; |
1713 | break; | |
1714 | ||
c5aa993b | 1715 | case 0x6: /*sbc */ |
c906108c SS |
1716 | result = operand1 - operand2 + c; |
1717 | break; | |
1718 | ||
c5aa993b | 1719 | case 0x7: /*rsc */ |
c906108c SS |
1720 | result = operand2 - operand1 + c; |
1721 | break; | |
1722 | ||
c5aa993b JM |
1723 | case 0x8: |
1724 | case 0x9: | |
1725 | case 0xa: | |
1726 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1727 | result = (unsigned long) nextpc; |
1728 | break; | |
1729 | ||
c5aa993b | 1730 | case 0xc: /*orr */ |
c906108c SS |
1731 | result = operand1 | operand2; |
1732 | break; | |
1733 | ||
c5aa993b | 1734 | case 0xd: /*mov */ |
c906108c SS |
1735 | /* Always step into a function. */ |
1736 | result = operand2; | |
c5aa993b | 1737 | break; |
c906108c | 1738 | |
c5aa993b | 1739 | case 0xe: /*bic */ |
c906108c SS |
1740 | result = operand1 & ~operand2; |
1741 | break; | |
1742 | ||
c5aa993b | 1743 | case 0xf: /*mvn */ |
c906108c SS |
1744 | result = ~operand2; |
1745 | break; | |
1746 | } | |
1747 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1748 | ||
1749 | if (nextpc == pc) | |
edefbb7c | 1750 | error (_("Infinite loop detected")); |
c906108c SS |
1751 | break; |
1752 | } | |
c5aa993b JM |
1753 | |
1754 | case 0x4: | |
1755 | case 0x5: /* data transfer */ | |
1756 | case 0x6: | |
1757 | case 0x7: | |
c906108c SS |
1758 | if (bit (this_instr, 20)) |
1759 | { | |
1760 | /* load */ | |
1761 | if (bits (this_instr, 12, 15) == 15) | |
1762 | { | |
1763 | /* rd == pc */ | |
c5aa993b | 1764 | unsigned long rn; |
c906108c | 1765 | unsigned long base; |
c5aa993b | 1766 | |
c906108c | 1767 | if (bit (this_instr, 22)) |
edefbb7c | 1768 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1769 | |
1770 | /* byte write to PC */ | |
1771 | rn = bits (this_instr, 16, 19); | |
1772 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1773 | if (bit (this_instr, 24)) | |
1774 | { | |
1775 | /* pre-indexed */ | |
1776 | int c = (status & FLAG_C) ? 1 : 0; | |
1777 | unsigned long offset = | |
c5aa993b | 1778 | (bit (this_instr, 25) |
ed9a39eb | 1779 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1780 | : bits (this_instr, 0, 11)); |
c906108c SS |
1781 | |
1782 | if (bit (this_instr, 23)) | |
1783 | base += offset; | |
1784 | else | |
1785 | base -= offset; | |
1786 | } | |
c5aa993b | 1787 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1788 | 4); |
c5aa993b | 1789 | |
c906108c SS |
1790 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1791 | ||
1792 | if (nextpc == pc) | |
edefbb7c | 1793 | error (_("Infinite loop detected")); |
c906108c SS |
1794 | } |
1795 | } | |
1796 | break; | |
c5aa993b JM |
1797 | |
1798 | case 0x8: | |
1799 | case 0x9: /* block transfer */ | |
c906108c SS |
1800 | if (bit (this_instr, 20)) |
1801 | { | |
1802 | /* LDM */ | |
1803 | if (bit (this_instr, 15)) | |
1804 | { | |
1805 | /* loading pc */ | |
1806 | int offset = 0; | |
1807 | ||
1808 | if (bit (this_instr, 23)) | |
1809 | { | |
1810 | /* up */ | |
1811 | unsigned long reglist = bits (this_instr, 0, 14); | |
1812 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1813 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1814 | offset += 4; |
1815 | } | |
1816 | else if (bit (this_instr, 24)) | |
1817 | offset = -4; | |
c5aa993b | 1818 | |
c906108c | 1819 | { |
c5aa993b JM |
1820 | unsigned long rn_val = |
1821 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1822 | nextpc = |
1823 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1824 | + offset), |
c906108c SS |
1825 | 4); |
1826 | } | |
1827 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1828 | if (nextpc == pc) | |
edefbb7c | 1829 | error (_("Infinite loop detected")); |
c906108c SS |
1830 | } |
1831 | } | |
1832 | break; | |
c5aa993b JM |
1833 | |
1834 | case 0xb: /* branch & link */ | |
1835 | case 0xa: /* branch */ | |
c906108c SS |
1836 | { |
1837 | nextpc = BranchDest (pc, this_instr); | |
1838 | ||
9498281f DJ |
1839 | /* BLX */ |
1840 | if (bits (this_instr, 28, 31) == INST_NV) | |
1841 | nextpc |= bit (this_instr, 24) << 1; | |
1842 | ||
c906108c SS |
1843 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1844 | if (nextpc == pc) | |
edefbb7c | 1845 | error (_("Infinite loop detected")); |
c906108c SS |
1846 | break; |
1847 | } | |
c5aa993b JM |
1848 | |
1849 | case 0xc: | |
1850 | case 0xd: | |
1851 | case 0xe: /* coproc ops */ | |
1852 | case 0xf: /* SWI */ | |
c906108c SS |
1853 | break; |
1854 | ||
1855 | default: | |
edefbb7c | 1856 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1857 | return (pc); |
1858 | } | |
1859 | } | |
1860 | ||
1861 | return nextpc; | |
1862 | } | |
1863 | ||
9512d7fd FN |
1864 | /* single_step() is called just before we want to resume the inferior, |
1865 | if we want to single-step it but there is no hardware or kernel | |
1866 | single-step support. We find the target of the coming instruction | |
1867 | and breakpoint it. | |
1868 | ||
94c30b78 MS |
1869 | single_step() is also called just after the inferior stops. If we |
1870 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1871 | |
34e8f22d RE |
1872 | static void |
1873 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1874 | { |
b8d5e71d | 1875 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
1876 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
1877 | ||
1878 | if (insert_bpt) | |
1879 | { | |
34e8f22d | 1880 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 1881 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1882 | } |
1883 | else | |
80fcf3f0 | 1884 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1885 | } |
9512d7fd | 1886 | |
c906108c SS |
1887 | #include "bfd-in2.h" |
1888 | #include "libcoff.h" | |
1889 | ||
1890 | static int | |
ed9a39eb | 1891 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1892 | { |
1893 | if (arm_pc_is_thumb (memaddr)) | |
1894 | { | |
c5aa993b JM |
1895 | static asymbol *asym; |
1896 | static combined_entry_type ce; | |
1897 | static struct coff_symbol_struct csym; | |
27cddce2 | 1898 | static struct bfd fake_bfd; |
c5aa993b | 1899 | static bfd_target fake_target; |
c906108c SS |
1900 | |
1901 | if (csym.native == NULL) | |
1902 | { | |
da3c6d4a MS |
1903 | /* Create a fake symbol vector containing a Thumb symbol. |
1904 | This is solely so that the code in print_insn_little_arm() | |
1905 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1906 | the presence of a Thumb symbol and switch to decoding | |
1907 | Thumb instructions. */ | |
c5aa993b JM |
1908 | |
1909 | fake_target.flavour = bfd_target_coff_flavour; | |
1910 | fake_bfd.xvec = &fake_target; | |
c906108c | 1911 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1912 | csym.native = &ce; |
1913 | csym.symbol.the_bfd = &fake_bfd; | |
1914 | csym.symbol.name = "fake"; | |
1915 | asym = (asymbol *) & csym; | |
c906108c | 1916 | } |
c5aa993b | 1917 | |
c906108c | 1918 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1919 | info->symbols = &asym; |
c906108c SS |
1920 | } |
1921 | else | |
1922 | info->symbols = NULL; | |
c5aa993b | 1923 | |
d7449b42 | 1924 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1925 | return print_insn_big_arm (memaddr, info); |
1926 | else | |
1927 | return print_insn_little_arm (memaddr, info); | |
1928 | } | |
1929 | ||
66e810cd RE |
1930 | /* The following define instruction sequences that will cause ARM |
1931 | cpu's to take an undefined instruction trap. These are used to | |
1932 | signal a breakpoint to GDB. | |
1933 | ||
1934 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1935 | modes. A different instruction is required for each mode. The ARM | |
1936 | cpu's can also be big or little endian. Thus four different | |
1937 | instructions are needed to support all cases. | |
1938 | ||
1939 | Note: ARMv4 defines several new instructions that will take the | |
1940 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1941 | not in fact add the new instructions. The new undefined | |
1942 | instructions in ARMv4 are all instructions that had no defined | |
1943 | behaviour in earlier chips. There is no guarantee that they will | |
1944 | raise an exception, but may be treated as NOP's. In practice, it | |
1945 | may only safe to rely on instructions matching: | |
1946 | ||
1947 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1948 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1949 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1950 | ||
1951 | Even this may only true if the condition predicate is true. The | |
1952 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1953 | ||
1954 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1955 | and NetBSD all use a software interrupt rather than an undefined | |
1956 | instruction to force a trap. This can be handled by by the | |
1957 | abi-specific code during establishment of the gdbarch vector. */ | |
1958 | ||
1959 | ||
d7b486e7 RE |
1960 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1961 | override these definitions. */ | |
66e810cd RE |
1962 | #ifndef ARM_LE_BREAKPOINT |
1963 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1964 | #endif | |
1965 | #ifndef ARM_BE_BREAKPOINT | |
1966 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1967 | #endif | |
1968 | #ifndef THUMB_LE_BREAKPOINT | |
1969 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1970 | #endif | |
1971 | #ifndef THUMB_BE_BREAKPOINT | |
1972 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1973 | #endif | |
1974 | ||
1975 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1976 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1977 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1978 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1979 | ||
34e8f22d RE |
1980 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1981 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1982 | breakpoint should be used. It returns a pointer to a string of |
1983 | bytes that encode a breakpoint instruction, stores the length of | |
1984 | the string to *lenptr, and adjusts the program counter (if | |
1985 | necessary) to point to the actual memory location where the | |
c906108c SS |
1986 | breakpoint should be inserted. */ |
1987 | ||
34e8f22d RE |
1988 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
1989 | breakpoints and storing their handles instread of what was in | |
1990 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 1991 | otherwise remote-rdp will have to change. */ |
34e8f22d | 1992 | |
ab89facf | 1993 | static const unsigned char * |
ed9a39eb | 1994 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1995 | { |
66e810cd RE |
1996 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1997 | ||
4bf7064c | 1998 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 1999 | { |
66e810cd RE |
2000 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2001 | *lenptr = tdep->thumb_breakpoint_size; | |
2002 | return tdep->thumb_breakpoint; | |
c906108c SS |
2003 | } |
2004 | else | |
2005 | { | |
66e810cd RE |
2006 | *lenptr = tdep->arm_breakpoint_size; |
2007 | return tdep->arm_breakpoint; | |
c906108c SS |
2008 | } |
2009 | } | |
ed9a39eb JM |
2010 | |
2011 | /* Extract from an array REGBUF containing the (raw) register state a | |
2012 | function return value of type TYPE, and copy that, in virtual | |
2013 | format, into VALBUF. */ | |
2014 | ||
34e8f22d | 2015 | static void |
5238cf52 MK |
2016 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2017 | gdb_byte *valbuf) | |
ed9a39eb JM |
2018 | { |
2019 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 | 2020 | { |
28e97307 | 2021 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2022 | { |
2023 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2024 | { |
2025 | /* The value is in register F0 in internal format. We need to | |
2026 | extract the raw value and then convert it to the desired | |
2027 | internal type. */ | |
7a5ea0d4 | 2028 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2029 | |
2030 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2031 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2032 | valbuf); | |
2033 | } | |
08216dd7 RE |
2034 | break; |
2035 | ||
fd50bc42 | 2036 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2037 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2038 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2039 | if (TYPE_LENGTH (type) > 4) | |
2040 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2041 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2042 | break; |
2043 | ||
2044 | default: | |
2045 | internal_error | |
2046 | (__FILE__, __LINE__, | |
edefbb7c | 2047 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2048 | break; |
2049 | } | |
2050 | } | |
b508a996 RE |
2051 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2052 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2053 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2054 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2055 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2056 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2057 | { | |
2058 | /* If the the type is a plain integer, then the access is | |
2059 | straight-forward. Otherwise we have to play around a bit more. */ | |
2060 | int len = TYPE_LENGTH (type); | |
2061 | int regno = ARM_A1_REGNUM; | |
2062 | ULONGEST tmp; | |
2063 | ||
2064 | while (len > 0) | |
2065 | { | |
2066 | /* By using store_unsigned_integer we avoid having to do | |
2067 | anything special for small big-endian values. */ | |
2068 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2069 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2070 | (len > INT_REGISTER_SIZE |
2071 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2072 | tmp); |
7a5ea0d4 DJ |
2073 | len -= INT_REGISTER_SIZE; |
2074 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2075 | } |
2076 | } | |
ed9a39eb | 2077 | else |
b508a996 RE |
2078 | { |
2079 | /* For a structure or union the behaviour is as if the value had | |
2080 | been stored to word-aligned memory and then loaded into | |
2081 | registers with 32-bit load instruction(s). */ | |
2082 | int len = TYPE_LENGTH (type); | |
2083 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2084 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2085 | |
2086 | while (len > 0) | |
2087 | { | |
2088 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2089 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2090 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2091 | len -= INT_REGISTER_SIZE; | |
2092 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2093 | } |
2094 | } | |
34e8f22d RE |
2095 | } |
2096 | ||
67255d04 RE |
2097 | /* Extract from an array REGBUF containing the (raw) register state |
2098 | the address in which a function should return its structure value. */ | |
2099 | ||
2100 | static CORE_ADDR | |
95f95911 | 2101 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2102 | { |
95f95911 MS |
2103 | ULONGEST ret; |
2104 | ||
2105 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2106 | return ret; | |
67255d04 RE |
2107 | } |
2108 | ||
2109 | /* Will a function return an aggregate type in memory or in a | |
2110 | register? Return 0 if an aggregate type can be returned in a | |
2111 | register, 1 if it must be returned in memory. */ | |
2112 | ||
2113 | static int | |
2114 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2115 | { | |
2116 | int nRc; | |
52f0bd74 | 2117 | enum type_code code; |
67255d04 | 2118 | |
44e1a9eb DJ |
2119 | CHECK_TYPEDEF (type); |
2120 | ||
67255d04 RE |
2121 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2122 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2123 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2124 | offset of each addressable subfield must be zero. Note that bit | |
2125 | fields are not addressable, and all addressable subfields of | |
2126 | unions always start at offset zero. | |
67255d04 RE |
2127 | |
2128 | This function is based on the behaviour of GCC 2.95.1. | |
2129 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2130 | ||
2131 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2132 | parameters correctly for a function returning the following | |
2133 | structure: struct { float f;}; This should be returned in memory, | |
2134 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2135 | know of any way to detect if a function like the above has been | |
2136 | compiled with the correct calling convention. */ | |
2137 | ||
2138 | /* All aggregate types that won't fit in a register must be returned | |
2139 | in memory. */ | |
b1e29e33 | 2140 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2141 | { |
2142 | return 1; | |
2143 | } | |
2144 | ||
2145 | /* The only aggregate types that can be returned in a register are | |
2146 | structs and unions. Arrays must be returned in memory. */ | |
2147 | code = TYPE_CODE (type); | |
2148 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2149 | { | |
2150 | return 1; | |
2151 | } | |
2152 | ||
2153 | /* Assume all other aggregate types can be returned in a register. | |
2154 | Run a check for structures, unions and arrays. */ | |
2155 | nRc = 0; | |
2156 | ||
2157 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2158 | { | |
2159 | int i; | |
2160 | /* Need to check if this struct/union is "integer" like. For | |
2161 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2162 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2163 | subfield must be zero. Note that bit fields are not | |
2164 | addressable, and unions always start at offset zero. If any | |
2165 | of the subfields is a floating point type, the struct/union | |
2166 | cannot be an integer type. */ | |
67255d04 RE |
2167 | |
2168 | /* For each field in the object, check: | |
2169 | 1) Is it FP? --> yes, nRc = 1; | |
2170 | 2) Is it addressable (bitpos != 0) and | |
2171 | not packed (bitsize == 0)? | |
2172 | --> yes, nRc = 1 | |
2173 | */ | |
2174 | ||
2175 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2176 | { | |
2177 | enum type_code field_type_code; | |
44e1a9eb | 2178 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2179 | |
2180 | /* Is it a floating point type field? */ | |
2181 | if (field_type_code == TYPE_CODE_FLT) | |
2182 | { | |
2183 | nRc = 1; | |
2184 | break; | |
2185 | } | |
2186 | ||
2187 | /* If bitpos != 0, then we have to care about it. */ | |
2188 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2189 | { | |
2190 | /* Bitfields are not addressable. If the field bitsize is | |
2191 | zero, then the field is not packed. Hence it cannot be | |
2192 | a bitfield or any other packed type. */ | |
2193 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2194 | { | |
2195 | nRc = 1; | |
2196 | break; | |
2197 | } | |
2198 | } | |
2199 | } | |
2200 | } | |
2201 | ||
2202 | return nRc; | |
2203 | } | |
2204 | ||
34e8f22d RE |
2205 | /* Write into appropriate registers a function return value of type |
2206 | TYPE, given in virtual format. */ | |
2207 | ||
2208 | static void | |
b508a996 | 2209 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2210 | const gdb_byte *valbuf) |
34e8f22d RE |
2211 | { |
2212 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2213 | { | |
7a5ea0d4 | 2214 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2215 | |
28e97307 | 2216 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2217 | { |
2218 | case ARM_FLOAT_FPA: | |
2219 | ||
b508a996 RE |
2220 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2221 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2222 | break; |
2223 | ||
fd50bc42 | 2224 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2225 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2226 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2227 | if (TYPE_LENGTH (type) > 4) | |
2228 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2229 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2230 | break; |
2231 | ||
2232 | default: | |
2233 | internal_error | |
2234 | (__FILE__, __LINE__, | |
edefbb7c | 2235 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2236 | break; |
2237 | } | |
34e8f22d | 2238 | } |
b508a996 RE |
2239 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2240 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2241 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2242 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2243 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2244 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2245 | { | |
2246 | if (TYPE_LENGTH (type) <= 4) | |
2247 | { | |
2248 | /* Values of one word or less are zero/sign-extended and | |
2249 | returned in r0. */ | |
7a5ea0d4 | 2250 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2251 | LONGEST val = unpack_long (type, valbuf); |
2252 | ||
7a5ea0d4 | 2253 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2254 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2255 | } | |
2256 | else | |
2257 | { | |
2258 | /* Integral values greater than one word are stored in consecutive | |
2259 | registers starting with r0. This will always be a multiple of | |
2260 | the regiser size. */ | |
2261 | int len = TYPE_LENGTH (type); | |
2262 | int regno = ARM_A1_REGNUM; | |
2263 | ||
2264 | while (len > 0) | |
2265 | { | |
2266 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2267 | len -= INT_REGISTER_SIZE; |
2268 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2269 | } |
2270 | } | |
2271 | } | |
34e8f22d | 2272 | else |
b508a996 RE |
2273 | { |
2274 | /* For a structure or union the behaviour is as if the value had | |
2275 | been stored to word-aligned memory and then loaded into | |
2276 | registers with 32-bit load instruction(s). */ | |
2277 | int len = TYPE_LENGTH (type); | |
2278 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2279 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2280 | |
2281 | while (len > 0) | |
2282 | { | |
2283 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2284 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2285 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2286 | len -= INT_REGISTER_SIZE; |
2287 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2288 | } |
2289 | } | |
34e8f22d RE |
2290 | } |
2291 | ||
9df628e0 RE |
2292 | static int |
2293 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2294 | { | |
2295 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2296 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2297 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2298 | ||
2299 | jb_addr = read_register (ARM_A1_REGNUM); | |
2300 | ||
2301 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2302 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2303 | return 0; |
2304 | ||
7a5ea0d4 | 2305 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2306 | return 1; |
2307 | } | |
2308 | ||
ed9a39eb | 2309 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2310 | |
2311 | int | |
ed9a39eb | 2312 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2313 | { |
2314 | CORE_ADDR start_addr; | |
2315 | ||
ed9a39eb JM |
2316 | /* Find the starting address of the function containing the PC. If |
2317 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2318 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2319 | &start_addr, NULL)) | |
c906108c SS |
2320 | return 0; |
2321 | ||
2322 | return strncmp (name, "_call_via_r", 11) == 0; | |
2323 | } | |
2324 | ||
ed9a39eb JM |
2325 | /* If PC is in a Thumb call or return stub, return the address of the |
2326 | target PC, which is in a register. The thunk functions are called | |
2327 | _called_via_xx, where x is the register name. The possible names | |
2328 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2329 | |
2330 | CORE_ADDR | |
ed9a39eb | 2331 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2332 | { |
c5aa993b | 2333 | char *name; |
c906108c SS |
2334 | CORE_ADDR start_addr; |
2335 | ||
2336 | /* Find the starting address and name of the function containing the PC. */ | |
2337 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2338 | return 0; | |
2339 | ||
2340 | /* Call thunks always start with "_call_via_". */ | |
2341 | if (strncmp (name, "_call_via_", 10) == 0) | |
2342 | { | |
ed9a39eb JM |
2343 | /* Use the name suffix to determine which register contains the |
2344 | target PC. */ | |
c5aa993b JM |
2345 | static char *table[15] = |
2346 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2347 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2348 | }; | |
c906108c SS |
2349 | int regno; |
2350 | ||
2351 | for (regno = 0; regno <= 14; regno++) | |
2352 | if (strcmp (&name[10], table[regno]) == 0) | |
2353 | return read_register (regno); | |
2354 | } | |
ed9a39eb | 2355 | |
c5aa993b | 2356 | return 0; /* not a stub */ |
c906108c SS |
2357 | } |
2358 | ||
afd7eef0 RE |
2359 | static void |
2360 | set_arm_command (char *args, int from_tty) | |
2361 | { | |
edefbb7c AC |
2362 | printf_unfiltered (_("\ |
2363 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2364 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2365 | } | |
2366 | ||
2367 | static void | |
2368 | show_arm_command (char *args, int from_tty) | |
2369 | { | |
26304000 | 2370 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2371 | } |
2372 | ||
28e97307 DJ |
2373 | static void |
2374 | arm_update_current_architecture (void) | |
fd50bc42 | 2375 | { |
28e97307 | 2376 | struct gdbarch_info info; |
fd50bc42 | 2377 | |
28e97307 DJ |
2378 | /* If the current architecture is not ARM, we have nothing to do. */ |
2379 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2380 | return; | |
fd50bc42 | 2381 | |
28e97307 DJ |
2382 | /* Update the architecture. */ |
2383 | gdbarch_info_init (&info); | |
fd50bc42 | 2384 | |
28e97307 DJ |
2385 | if (!gdbarch_update_p (info)) |
2386 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2387 | } |
2388 | ||
2389 | static void | |
2390 | set_fp_model_sfunc (char *args, int from_tty, | |
2391 | struct cmd_list_element *c) | |
2392 | { | |
2393 | enum arm_float_model fp_model; | |
2394 | ||
2395 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2396 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2397 | { | |
2398 | arm_fp_model = fp_model; | |
2399 | break; | |
2400 | } | |
2401 | ||
2402 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2403 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2404 | current_fp_model); |
2405 | ||
28e97307 | 2406 | arm_update_current_architecture (); |
fd50bc42 RE |
2407 | } |
2408 | ||
2409 | static void | |
08546159 AC |
2410 | show_fp_model (struct ui_file *file, int from_tty, |
2411 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2412 | { |
2413 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2414 | ||
28e97307 | 2415 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2416 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2417 | fprintf_filtered (file, _("\ |
2418 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2419 | fp_model_strings[tdep->fp_model]); | |
2420 | else | |
2421 | fprintf_filtered (file, _("\ | |
2422 | The current ARM floating point model is \"%s\".\n"), | |
2423 | fp_model_strings[arm_fp_model]); | |
2424 | } | |
2425 | ||
2426 | static void | |
2427 | arm_set_abi (char *args, int from_tty, | |
2428 | struct cmd_list_element *c) | |
2429 | { | |
2430 | enum arm_abi_kind arm_abi; | |
2431 | ||
2432 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2433 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2434 | { | |
2435 | arm_abi_global = arm_abi; | |
2436 | break; | |
2437 | } | |
2438 | ||
2439 | if (arm_abi == ARM_ABI_LAST) | |
2440 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2441 | arm_abi_string); | |
2442 | ||
2443 | arm_update_current_architecture (); | |
2444 | } | |
2445 | ||
2446 | static void | |
2447 | arm_show_abi (struct ui_file *file, int from_tty, | |
2448 | struct cmd_list_element *c, const char *value) | |
2449 | { | |
2450 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2451 | ||
2452 | if (arm_abi_global == ARM_ABI_AUTO | |
2453 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2454 | fprintf_filtered (file, _("\ | |
2455 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2456 | arm_abi_strings[tdep->arm_abi]); | |
2457 | else | |
2458 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2459 | arm_abi_string); | |
fd50bc42 RE |
2460 | } |
2461 | ||
afd7eef0 RE |
2462 | /* If the user changes the register disassembly style used for info |
2463 | register and other commands, we have to also switch the style used | |
2464 | in opcodes for disassembly output. This function is run in the "set | |
2465 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2466 | |
2467 | static void | |
afd7eef0 | 2468 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2469 | struct cmd_list_element *c) |
2470 | { | |
afd7eef0 | 2471 | set_disassembly_style (); |
bc90b915 FN |
2472 | } |
2473 | \f | |
966fbf70 | 2474 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2475 | static const char * |
34e8f22d | 2476 | arm_register_name (int i) |
966fbf70 RE |
2477 | { |
2478 | return arm_register_names[i]; | |
2479 | } | |
2480 | ||
bc90b915 | 2481 | static void |
afd7eef0 | 2482 | set_disassembly_style (void) |
bc90b915 | 2483 | { |
4bd7b427 | 2484 | const char *setname, *setdesc, *const *regnames; |
bc90b915 FN |
2485 | int numregs, j; |
2486 | ||
afd7eef0 | 2487 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2488 | int current = 0; |
2489 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2490 | while ((disassembly_style != setname) |
2491 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2492 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2493 | current_option = current; | |
2494 | ||
94c30b78 | 2495 | /* Fill our copy. */ |
bc90b915 FN |
2496 | for (j = 0; j < numregs; j++) |
2497 | arm_register_names[j] = (char *) regnames[j]; | |
2498 | ||
94c30b78 | 2499 | /* Adjust case. */ |
34e8f22d | 2500 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2501 | { |
34e8f22d RE |
2502 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2503 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2504 | } |
2505 | else | |
2506 | { | |
34e8f22d RE |
2507 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2508 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2509 | } |
2510 | ||
94c30b78 | 2511 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2512 | set_arm_regname_option (current); |
2513 | } | |
2514 | ||
082fc60d RE |
2515 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2516 | function. */ | |
2517 | ||
2518 | static int | |
2519 | coff_sym_is_thumb (int val) | |
2520 | { | |
2521 | return (val == C_THUMBEXT || | |
2522 | val == C_THUMBSTAT || | |
2523 | val == C_THUMBEXTFUNC || | |
2524 | val == C_THUMBSTATFUNC || | |
2525 | val == C_THUMBLABEL); | |
2526 | } | |
2527 | ||
2528 | /* arm_coff_make_msymbol_special() | |
2529 | arm_elf_make_msymbol_special() | |
2530 | ||
2531 | These functions test whether the COFF or ELF symbol corresponds to | |
2532 | an address in thumb code, and set a "special" bit in a minimal | |
2533 | symbol to indicate that it does. */ | |
2534 | ||
34e8f22d | 2535 | static void |
082fc60d RE |
2536 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2537 | { | |
2538 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2539 | STT_ARM_TFUNC). */ | |
2540 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2541 | == STT_LOPROC) | |
2542 | MSYMBOL_SET_SPECIAL (msym); | |
2543 | } | |
2544 | ||
34e8f22d | 2545 | static void |
082fc60d RE |
2546 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2547 | { | |
2548 | if (coff_sym_is_thumb (val)) | |
2549 | MSYMBOL_SET_SPECIAL (msym); | |
2550 | } | |
2551 | ||
756fe439 DJ |
2552 | static void |
2553 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2554 | { | |
2555 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2556 | ||
2557 | /* If necessary, set the T bit. */ | |
2558 | if (arm_apcs_32) | |
2559 | { | |
2560 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2561 | if (arm_pc_is_thumb (pc)) | |
2562 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2563 | else | |
2564 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2565 | } | |
2566 | } | |
97e03143 | 2567 | \f |
70f80edf JT |
2568 | static enum gdb_osabi |
2569 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2570 | { |
70f80edf JT |
2571 | unsigned int elfosabi, eflags; |
2572 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2573 | |
70f80edf | 2574 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2575 | |
28e97307 DJ |
2576 | if (elfosabi == ELFOSABI_ARM) |
2577 | /* GNU tools use this value. Check note sections in this case, | |
2578 | as well. */ | |
2579 | bfd_map_over_sections (abfd, | |
2580 | generic_elf_osabi_sniff_abi_tag_sections, | |
2581 | &osabi); | |
97e03143 | 2582 | |
28e97307 | 2583 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2584 | return osabi; |
97e03143 RE |
2585 | } |
2586 | ||
70f80edf | 2587 | \f |
da3c6d4a MS |
2588 | /* Initialize the current architecture based on INFO. If possible, |
2589 | re-use an architecture from ARCHES, which is a list of | |
2590 | architectures already created during this debugging session. | |
97e03143 | 2591 | |
da3c6d4a MS |
2592 | Called e.g. at program startup, when reading a core file, and when |
2593 | reading a binary file. */ | |
97e03143 | 2594 | |
39bbf761 RE |
2595 | static struct gdbarch * |
2596 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2597 | { | |
97e03143 | 2598 | struct gdbarch_tdep *tdep; |
39bbf761 | 2599 | struct gdbarch *gdbarch; |
28e97307 DJ |
2600 | struct gdbarch_list *best_arch; |
2601 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2602 | enum arm_float_model fp_model = arm_fp_model; | |
39bbf761 | 2603 | |
28e97307 DJ |
2604 | /* If we have an object to base this architecture on, try to determine |
2605 | its ABI. */ | |
39bbf761 | 2606 | |
28e97307 | 2607 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2608 | { |
28e97307 DJ |
2609 | int ei_osabi; |
2610 | ||
4be87837 | 2611 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2612 | { |
4be87837 DJ |
2613 | case bfd_target_aout_flavour: |
2614 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2615 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2616 | break; |
97e03143 | 2617 | |
4be87837 DJ |
2618 | case bfd_target_coff_flavour: |
2619 | /* Assume it's an old APCS-style ABI. */ | |
2620 | /* XXX WinCE? */ | |
28e97307 DJ |
2621 | arm_abi = ARM_ABI_APCS; |
2622 | break; | |
2623 | ||
2624 | case bfd_target_elf_flavour: | |
2625 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
2626 | if (ei_osabi == ELFOSABI_ARM) | |
2627 | { | |
2628 | /* GNU tools used to use this value, but do not for EABI | |
2629 | objects. There's nowhere to tag an EABI version anyway, | |
2630 | so assume APCS. */ | |
2631 | arm_abi = ARM_ABI_APCS; | |
2632 | } | |
2633 | else if (ei_osabi == ELFOSABI_NONE) | |
2634 | { | |
2635 | int e_flags, eabi_ver; | |
2636 | ||
2637 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
2638 | eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
2639 | ||
2640 | switch (eabi_ver) | |
2641 | { | |
2642 | case EF_ARM_EABI_UNKNOWN: | |
2643 | /* Assume GNU tools. */ | |
2644 | arm_abi = ARM_ABI_APCS; | |
2645 | break; | |
2646 | ||
2647 | case EF_ARM_EABI_VER4: | |
2648 | arm_abi = ARM_ABI_AAPCS; | |
2649 | break; | |
2650 | ||
2651 | default: | |
2652 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
2653 | arm_abi = ARM_ABI_APCS; | |
2654 | break; | |
2655 | } | |
2656 | } | |
4be87837 | 2657 | break; |
97e03143 | 2658 | |
4be87837 | 2659 | default: |
28e97307 | 2660 | /* Leave it as "auto". */ |
50ceaba5 | 2661 | break; |
97e03143 RE |
2662 | } |
2663 | } | |
2664 | ||
28e97307 DJ |
2665 | /* Now that we have inferred any architecture settings that we |
2666 | can, try to inherit from the last ARM ABI. */ | |
4be87837 | 2667 | if (arches != NULL) |
28e97307 DJ |
2668 | { |
2669 | if (arm_abi == ARM_ABI_AUTO) | |
2670 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; | |
2671 | ||
2672 | if (fp_model == ARM_FLOAT_AUTO) | |
2673 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; | |
2674 | } | |
2675 | else | |
2676 | { | |
2677 | /* There was no prior ARM architecture; fill in default values. */ | |
2678 | ||
2679 | if (arm_abi == ARM_ABI_AUTO) | |
2680 | arm_abi = ARM_ABI_APCS; | |
2681 | ||
2682 | /* We used to default to FPA for generic ARM, but almost nobody | |
2683 | uses that now, and we now provide a way for the user to force | |
2684 | the model. So default to the most useful variant. */ | |
2685 | if (fp_model == ARM_FLOAT_AUTO) | |
2686 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2687 | } | |
2688 | ||
2689 | /* If there is already a candidate, use it. */ | |
2690 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2691 | best_arch != NULL; | |
2692 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2693 | { | |
2694 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
2695 | continue; | |
2696 | ||
2697 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
2698 | continue; | |
2699 | ||
2700 | /* Found a match. */ | |
2701 | break; | |
2702 | } | |
97e03143 | 2703 | |
28e97307 DJ |
2704 | if (best_arch != NULL) |
2705 | return best_arch->gdbarch; | |
2706 | ||
2707 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2708 | gdbarch = gdbarch_alloc (&info, tdep); |
2709 | ||
28e97307 DJ |
2710 | /* Record additional information about the architecture we are defining. |
2711 | These are gdbarch discriminators, like the OSABI. */ | |
2712 | tdep->arm_abi = arm_abi; | |
2713 | tdep->fp_model = fp_model; | |
08216dd7 RE |
2714 | |
2715 | /* Breakpoints. */ | |
67255d04 RE |
2716 | switch (info.byte_order) |
2717 | { | |
2718 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2719 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2720 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2721 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2722 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2723 | ||
67255d04 RE |
2724 | break; |
2725 | ||
2726 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2727 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2728 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2729 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2730 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2731 | ||
67255d04 RE |
2732 | break; |
2733 | ||
2734 | default: | |
2735 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2736 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2737 | } |
2738 | ||
d7b486e7 RE |
2739 | /* On ARM targets char defaults to unsigned. */ |
2740 | set_gdbarch_char_signed (gdbarch, 0); | |
2741 | ||
9df628e0 | 2742 | /* This should be low enough for everything. */ |
97e03143 | 2743 | tdep->lowest_pc = 0x20; |
94c30b78 | 2744 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2745 | |
2dd604e7 | 2746 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2747 | |
756fe439 DJ |
2748 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2749 | ||
148754e5 | 2750 | /* Frame handling. */ |
eb5492fa DJ |
2751 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2752 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2753 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2754 | ||
eb5492fa | 2755 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2756 | |
34e8f22d RE |
2757 | /* Address manipulation. */ |
2758 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2759 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2760 | ||
34e8f22d RE |
2761 | /* Advance PC across function entry code. */ |
2762 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2763 | ||
2764 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2765 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2766 | |
2767 | /* The stack grows downward. */ | |
2768 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2769 | ||
2770 | /* Breakpoint manipulation. */ | |
2771 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2772 | |
2773 | /* Information about registers, etc. */ | |
2774 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2775 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2776 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2777 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2778 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2779 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2780 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2781 | |
26216b98 AC |
2782 | /* Internal <-> external register number maps. */ |
2783 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2784 | ||
34e8f22d | 2785 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2786 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2787 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2788 | ||
2789 | /* Returning results. */ | |
b508a996 RE |
2790 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2791 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
b5622e8d | 2792 | set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention); |
74055713 | 2793 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); |
34e8f22d RE |
2794 | |
2795 | /* Single stepping. */ | |
2796 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2797 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2798 | ||
03d48a7d RE |
2799 | /* Disassembly. */ |
2800 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2801 | ||
34e8f22d RE |
2802 | /* Minsymbol frobbing. */ |
2803 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2804 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2805 | arm_coff_make_msymbol_special); | |
2806 | ||
97e03143 | 2807 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2808 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2809 | |
eb5492fa | 2810 | /* Add some default predicates. */ |
909cf6ea | 2811 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
eb5492fa | 2812 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); |
842e1f1e | 2813 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2814 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2815 | ||
97e03143 RE |
2816 | /* Now we have tuned the configuration, set a few final things, |
2817 | based on what the OS ABI has told us. */ | |
2818 | ||
9df628e0 RE |
2819 | if (tdep->jb_pc >= 0) |
2820 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2821 | ||
08216dd7 RE |
2822 | /* Floating point sizes and format. */ |
2823 | switch (info.byte_order) | |
2824 | { | |
2825 | case BFD_ENDIAN_BIG: | |
2826 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2827 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2828 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
08216dd7 RE |
2829 | break; |
2830 | ||
2831 | case BFD_ENDIAN_LITTLE: | |
2832 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
28e97307 DJ |
2833 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
2834 | { | |
2835 | set_gdbarch_double_format | |
2836 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2837 | set_gdbarch_long_double_format | |
2838 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2839 | } | |
2840 | else | |
2841 | { | |
2842 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2843 | set_gdbarch_long_double_format (gdbarch, | |
2844 | &floatformat_ieee_double_little); | |
2845 | } | |
08216dd7 RE |
2846 | break; |
2847 | ||
2848 | default: | |
2849 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2850 | _("arm_gdbarch_init: bad byte order for float format")); |
08216dd7 RE |
2851 | } |
2852 | ||
39bbf761 RE |
2853 | return gdbarch; |
2854 | } | |
2855 | ||
97e03143 RE |
2856 | static void |
2857 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2858 | { | |
2859 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2860 | ||
2861 | if (tdep == NULL) | |
2862 | return; | |
2863 | ||
edefbb7c | 2864 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
2865 | (unsigned long) tdep->lowest_pc); |
2866 | } | |
2867 | ||
a78f21af AC |
2868 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2869 | ||
c906108c | 2870 | void |
ed9a39eb | 2871 | _initialize_arm_tdep (void) |
c906108c | 2872 | { |
bc90b915 FN |
2873 | struct ui_file *stb; |
2874 | long length; | |
26304000 | 2875 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2876 | const char *setname; |
2877 | const char *setdesc; | |
4bd7b427 | 2878 | const char *const *regnames; |
bc90b915 FN |
2879 | int numregs, i, j; |
2880 | static char *helptext; | |
edefbb7c AC |
2881 | char regdesc[1024], *rdptr = regdesc; |
2882 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 2883 | |
42cf1509 | 2884 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2885 | |
70f80edf JT |
2886 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2887 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2888 | bfd_target_elf_flavour, | |
2889 | arm_elf_osabi_sniffer); | |
2890 | ||
94c30b78 | 2891 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2892 | num_disassembly_options = get_arm_regname_num_options (); |
2893 | ||
2894 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2895 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 2896 | _("Various ARM-specific commands."), |
afd7eef0 RE |
2897 | &setarmcmdlist, "set arm ", 0, &setlist); |
2898 | ||
2899 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 2900 | _("Various ARM-specific commands."), |
afd7eef0 | 2901 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 2902 | |
94c30b78 | 2903 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2904 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2905 | |
eefe576e AC |
2906 | /* Initialize the array that will be passed to |
2907 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
2908 | valid_disassembly_styles |
2909 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2910 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2911 | { |
2912 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2913 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
2914 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
2915 | rdptr += length; | |
2916 | rest -= length; | |
94c30b78 | 2917 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2918 | if (!strcmp (setname, "std")) |
2919 | { | |
afd7eef0 | 2920 | disassembly_style = setname; |
bc90b915 FN |
2921 | current_option = i; |
2922 | for (j = 0; j < numregs; j++) | |
2923 | arm_register_names[j] = (char *) regnames[j]; | |
2924 | set_arm_regname_option (i); | |
2925 | } | |
2926 | } | |
94c30b78 | 2927 | /* Mark the end of valid options. */ |
afd7eef0 | 2928 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2929 | |
edefbb7c AC |
2930 | /* Create the help text. */ |
2931 | stb = mem_fileopen (); | |
2932 | fprintf_unfiltered (stb, "%s%s%s", | |
2933 | _("The valid values are:\n"), | |
2934 | regdesc, | |
2935 | _("The default is \"std\".")); | |
bc90b915 FN |
2936 | helptext = ui_file_xstrdup (stb, &length); |
2937 | ui_file_delete (stb); | |
ed9a39eb | 2938 | |
edefbb7c AC |
2939 | add_setshow_enum_cmd("disassembler", no_class, |
2940 | valid_disassembly_styles, &disassembly_style, | |
2941 | _("Set the disassembly style."), | |
2942 | _("Show the disassembly style."), | |
2943 | helptext, | |
2c5b56ce | 2944 | set_disassembly_style_sfunc, |
7915a72c | 2945 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 2946 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
2947 | |
2948 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2949 | _("Set usage of ARM 32-bit mode."), | |
2950 | _("Show usage of ARM 32-bit mode."), | |
2951 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 2952 | NULL, |
7915a72c | 2953 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 2954 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 2955 | |
fd50bc42 | 2956 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
2957 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
2958 | _("Set the floating point type."), | |
2959 | _("Show the floating point type."), | |
2960 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
2961 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
2962 | fpa - FPA co-processor (GCC compiled).\n\ | |
2963 | softvfp - Software FP with pure-endian doubles.\n\ | |
2964 | vfp - VFP co-processor."), | |
edefbb7c | 2965 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 2966 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 2967 | |
28e97307 DJ |
2968 | /* Add a command to allow the user to force the ABI. */ |
2969 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
2970 | _("Set the ABI."), | |
2971 | _("Show the ABI."), | |
2972 | NULL, arm_set_abi, arm_show_abi, | |
2973 | &setarmcmdlist, &showarmcmdlist); | |
2974 | ||
6529d2dd | 2975 | /* Debugging flag. */ |
edefbb7c AC |
2976 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2977 | _("Set ARM debugging."), | |
2978 | _("Show ARM debugging."), | |
2979 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 2980 | NULL, |
7915a72c | 2981 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 2982 | &setdebuglist, &showdebuglist); |
c906108c | 2983 | } |