Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
618f726f | 3 | Copyright (C) 1988-2016 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
0963b4bd | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
45741a9c | 26 | #include "infrun.h" |
c906108c SS |
27 | #include "gdbcmd.h" |
28 | #include "gdbcore.h" | |
0963b4bd | 29 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 30 | #include "regcache.h" |
54483882 | 31 | #include "reggroups.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
25f8c692 | 43 | #include "remote.h" |
123dc839 DJ |
44 | #include "target-descriptions.h" |
45 | #include "user-regs.h" | |
0e9e9abd | 46 | #include "observer.h" |
34e8f22d | 47 | |
8689682c | 48 | #include "arch/arm.h" |
d9311bfa | 49 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 50 | #include "arm-tdep.h" |
26216b98 | 51 | #include "gdb/sim-arm.h" |
34e8f22d | 52 | |
082fc60d RE |
53 | #include "elf-bfd.h" |
54 | #include "coff/internal.h" | |
97e03143 | 55 | #include "elf/arm.h" |
c906108c | 56 | |
60c5725c | 57 | #include "vec.h" |
26216b98 | 58 | |
72508ac0 | 59 | #include "record.h" |
d02ed0bb | 60 | #include "record-full.h" |
72508ac0 | 61 | |
9779414d | 62 | #include "features/arm-with-m.c" |
25f8c692 | 63 | #include "features/arm-with-m-fpa-layout.c" |
3184d3f9 | 64 | #include "features/arm-with-m-vfp-d16.c" |
ef7e8358 UW |
65 | #include "features/arm-with-iwmmxt.c" |
66 | #include "features/arm-with-vfpv2.c" | |
67 | #include "features/arm-with-vfpv3.c" | |
68 | #include "features/arm-with-neon.c" | |
9779414d | 69 | |
6529d2dd AC |
70 | static int arm_debug; |
71 | ||
082fc60d RE |
72 | /* Macros for setting and testing a bit in a minimal symbol that marks |
73 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 74 | is used for this purpose. |
082fc60d RE |
75 | |
76 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 77 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 78 | |
0963b4bd | 79 | #define MSYMBOL_SET_SPECIAL(msym) \ |
b887350f | 80 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
81 | |
82 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 83 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 84 | |
60c5725c DJ |
85 | /* Per-objfile data used for mapping symbols. */ |
86 | static const struct objfile_data *arm_objfile_data_key; | |
87 | ||
88 | struct arm_mapping_symbol | |
89 | { | |
90 | bfd_vma value; | |
91 | char type; | |
92 | }; | |
93 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; | |
94 | DEF_VEC_O(arm_mapping_symbol_s); | |
95 | ||
96 | struct arm_per_objfile | |
97 | { | |
98 | VEC(arm_mapping_symbol_s) **section_maps; | |
99 | }; | |
100 | ||
afd7eef0 RE |
101 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
102 | static struct cmd_list_element *setarmcmdlist = NULL; | |
103 | static struct cmd_list_element *showarmcmdlist = NULL; | |
104 | ||
fd50bc42 RE |
105 | /* The type of floating-point to use. Keep this in sync with enum |
106 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 107 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
108 | { |
109 | "auto", | |
110 | "softfpa", | |
111 | "fpa", | |
112 | "softvfp", | |
28e97307 DJ |
113 | "vfp", |
114 | NULL | |
fd50bc42 RE |
115 | }; |
116 | ||
117 | /* A variable that can be configured by the user. */ | |
118 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
119 | static const char *current_fp_model = "auto"; | |
120 | ||
28e97307 | 121 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 122 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
123 | { |
124 | "auto", | |
125 | "APCS", | |
126 | "AAPCS", | |
127 | NULL | |
128 | }; | |
129 | ||
130 | /* A variable that can be configured by the user. */ | |
131 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
132 | static const char *arm_abi_string = "auto"; | |
133 | ||
0428b8f5 | 134 | /* The execution mode to assume. */ |
40478521 | 135 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
136 | { |
137 | "auto", | |
138 | "arm", | |
68770265 MGD |
139 | "thumb", |
140 | NULL | |
0428b8f5 DJ |
141 | }; |
142 | ||
143 | static const char *arm_fallback_mode_string = "auto"; | |
144 | static const char *arm_force_mode_string = "auto"; | |
145 | ||
18819fa6 UW |
146 | /* Internal override of the execution mode. -1 means no override, |
147 | 0 means override to ARM mode, 1 means override to Thumb mode. | |
148 | The effect is the same as if arm_force_mode has been set by the | |
149 | user (except the internal override has precedence over a user's | |
150 | arm_force_mode override). */ | |
151 | static int arm_override_mode = -1; | |
152 | ||
94c30b78 | 153 | /* Number of different reg name sets (options). */ |
afd7eef0 | 154 | static int num_disassembly_options; |
bc90b915 | 155 | |
f32bf4a4 YQ |
156 | /* The standard register names, and all the valid aliases for them. Note |
157 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
158 | have been added as builtin user registers in | |
159 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
160 | static const struct |
161 | { | |
162 | const char *name; | |
163 | int regnum; | |
164 | } arm_register_aliases[] = { | |
165 | /* Basic register numbers. */ | |
166 | { "r0", 0 }, | |
167 | { "r1", 1 }, | |
168 | { "r2", 2 }, | |
169 | { "r3", 3 }, | |
170 | { "r4", 4 }, | |
171 | { "r5", 5 }, | |
172 | { "r6", 6 }, | |
173 | { "r7", 7 }, | |
174 | { "r8", 8 }, | |
175 | { "r9", 9 }, | |
176 | { "r10", 10 }, | |
177 | { "r11", 11 }, | |
178 | { "r12", 12 }, | |
179 | { "r13", 13 }, | |
180 | { "r14", 14 }, | |
181 | { "r15", 15 }, | |
182 | /* Synonyms (argument and variable registers). */ | |
183 | { "a1", 0 }, | |
184 | { "a2", 1 }, | |
185 | { "a3", 2 }, | |
186 | { "a4", 3 }, | |
187 | { "v1", 4 }, | |
188 | { "v2", 5 }, | |
189 | { "v3", 6 }, | |
190 | { "v4", 7 }, | |
191 | { "v5", 8 }, | |
192 | { "v6", 9 }, | |
193 | { "v7", 10 }, | |
194 | { "v8", 11 }, | |
195 | /* Other platform-specific names for r9. */ | |
196 | { "sb", 9 }, | |
197 | { "tr", 9 }, | |
198 | /* Special names. */ | |
199 | { "ip", 12 }, | |
123dc839 | 200 | { "lr", 14 }, |
123dc839 DJ |
201 | /* Names used by GCC (not listed in the ARM EABI). */ |
202 | { "sl", 10 }, | |
123dc839 DJ |
203 | /* A special name from the older ATPCS. */ |
204 | { "wr", 7 }, | |
205 | }; | |
bc90b915 | 206 | |
123dc839 | 207 | static const char *const arm_register_names[] = |
da59e081 JM |
208 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
209 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
210 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
211 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
212 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
213 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 214 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 215 | |
afd7eef0 RE |
216 | /* Valid register name styles. */ |
217 | static const char **valid_disassembly_styles; | |
ed9a39eb | 218 | |
afd7eef0 RE |
219 | /* Disassembly style to use. Default to "std" register names. */ |
220 | static const char *disassembly_style; | |
96baa820 | 221 | |
ed9a39eb | 222 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
223 | style. */ |
224 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 225 | struct cmd_list_element *); |
afd7eef0 | 226 | static void set_disassembly_style (void); |
ed9a39eb | 227 | |
b508a996 | 228 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 229 | void *, int); |
b508a996 | 230 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 231 | const void *, int); |
ed9a39eb | 232 | |
05d1431c PA |
233 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
234 | struct regcache *regcache, | |
235 | int regnum, gdb_byte *buf); | |
58d6951d DJ |
236 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
237 | struct regcache *regcache, | |
238 | int regnum, const gdb_byte *buf); | |
239 | ||
e7cf25a8 YQ |
240 | static CORE_ADDR |
241 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, | |
242 | CORE_ADDR pc); | |
243 | ||
244 | ||
d9311bfa AT |
245 | /* get_next_pcs operations. */ |
246 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
247 | arm_get_next_pcs_read_memory_unsigned_integer, | |
248 | arm_get_next_pcs_syscall_next_pc, | |
249 | arm_get_next_pcs_addr_bits_remove, | |
250 | arm_get_next_pcs_is_thumb | |
251 | }; | |
252 | ||
9b8d791a | 253 | struct arm_prologue_cache |
c3b4394c | 254 | { |
eb5492fa DJ |
255 | /* The stack pointer at the time this frame was created; i.e. the |
256 | caller's stack pointer when this function was called. It is used | |
257 | to identify this frame. */ | |
258 | CORE_ADDR prev_sp; | |
259 | ||
4be43953 DJ |
260 | /* The frame base for this frame is just prev_sp - frame size. |
261 | FRAMESIZE is the distance from the frame pointer to the | |
262 | initial stack pointer. */ | |
eb5492fa | 263 | |
c3b4394c | 264 | int framesize; |
eb5492fa DJ |
265 | |
266 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 267 | int framereg; |
eb5492fa DJ |
268 | |
269 | /* Saved register offsets. */ | |
270 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 271 | }; |
ed9a39eb | 272 | |
0d39a070 DJ |
273 | static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, |
274 | CORE_ADDR prologue_start, | |
275 | CORE_ADDR prologue_end, | |
276 | struct arm_prologue_cache *cache); | |
277 | ||
cca44b1b JB |
278 | /* Architecture version for displaced stepping. This effects the behaviour of |
279 | certain instructions, and really should not be hard-wired. */ | |
280 | ||
281 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
282 | ||
94c30b78 | 283 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
284 | |
285 | int arm_apcs_32 = 1; | |
286 | ||
9779414d DJ |
287 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
288 | ||
478fd957 | 289 | int |
9779414d DJ |
290 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
291 | { | |
292 | if (gdbarch_tdep (gdbarch)->is_m) | |
293 | return XPSR_T; | |
294 | else | |
295 | return CPSR_T; | |
296 | } | |
297 | ||
d0e59a68 AT |
298 | /* Determine if the processor is currently executing in Thumb mode. */ |
299 | ||
300 | int | |
301 | arm_is_thumb (struct regcache *regcache) | |
302 | { | |
303 | ULONGEST cpsr; | |
304 | ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache)); | |
305 | ||
306 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
307 | ||
308 | return (cpsr & t_bit) != 0; | |
309 | } | |
310 | ||
b39cc962 DJ |
311 | /* Determine if FRAME is executing in Thumb mode. */ |
312 | ||
25b41d01 | 313 | int |
b39cc962 DJ |
314 | arm_frame_is_thumb (struct frame_info *frame) |
315 | { | |
316 | CORE_ADDR cpsr; | |
9779414d | 317 | ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); |
b39cc962 DJ |
318 | |
319 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
320 | directly (from a signal frame or dummy frame) or by interpreting | |
321 | the saved LR (from a prologue or DWARF frame). So consult it and | |
322 | trust the unwinders. */ | |
323 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
324 | ||
9779414d | 325 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
326 | } |
327 | ||
60c5725c DJ |
328 | /* Callback for VEC_lower_bound. */ |
329 | ||
330 | static inline int | |
331 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, | |
332 | const struct arm_mapping_symbol *rhs) | |
333 | { | |
334 | return lhs->value < rhs->value; | |
335 | } | |
336 | ||
f9d67f43 DJ |
337 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
338 | return its type. Otherwise, return 0. If START is non-NULL, | |
339 | set *START to the location of the mapping symbol. */ | |
c906108c | 340 | |
f9d67f43 DJ |
341 | static char |
342 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 343 | { |
60c5725c | 344 | struct obj_section *sec; |
0428b8f5 | 345 | |
60c5725c DJ |
346 | /* If there are mapping symbols, consult them. */ |
347 | sec = find_pc_section (memaddr); | |
348 | if (sec != NULL) | |
349 | { | |
350 | struct arm_per_objfile *data; | |
351 | VEC(arm_mapping_symbol_s) *map; | |
aded6f54 PA |
352 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
353 | 0 }; | |
60c5725c DJ |
354 | unsigned int idx; |
355 | ||
9a3c8263 SM |
356 | data = (struct arm_per_objfile *) objfile_data (sec->objfile, |
357 | arm_objfile_data_key); | |
60c5725c DJ |
358 | if (data != NULL) |
359 | { | |
360 | map = data->section_maps[sec->the_bfd_section->index]; | |
361 | if (!VEC_empty (arm_mapping_symbol_s, map)) | |
362 | { | |
363 | struct arm_mapping_symbol *map_sym; | |
364 | ||
365 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, | |
366 | arm_compare_mapping_symbols); | |
367 | ||
368 | /* VEC_lower_bound finds the earliest ordered insertion | |
369 | point. If the following symbol starts at this exact | |
370 | address, we use that; otherwise, the preceding | |
371 | mapping symbol covers this address. */ | |
372 | if (idx < VEC_length (arm_mapping_symbol_s, map)) | |
373 | { | |
374 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); | |
375 | if (map_sym->value == map_key.value) | |
f9d67f43 DJ |
376 | { |
377 | if (start) | |
378 | *start = map_sym->value + obj_section_addr (sec); | |
379 | return map_sym->type; | |
380 | } | |
60c5725c DJ |
381 | } |
382 | ||
383 | if (idx > 0) | |
384 | { | |
385 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); | |
f9d67f43 DJ |
386 | if (start) |
387 | *start = map_sym->value + obj_section_addr (sec); | |
388 | return map_sym->type; | |
60c5725c DJ |
389 | } |
390 | } | |
391 | } | |
392 | } | |
393 | ||
f9d67f43 DJ |
394 | return 0; |
395 | } | |
396 | ||
397 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
398 | function. This function should be called for addresses unrelated to | |
399 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
400 | ||
e3039479 | 401 | int |
9779414d | 402 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 403 | { |
7cbd4a93 | 404 | struct bound_minimal_symbol sym; |
f9d67f43 | 405 | char type; |
a42244db YQ |
406 | struct displaced_step_closure* dsc |
407 | = get_displaced_step_closure_by_addr(memaddr); | |
408 | ||
409 | /* If checking the mode of displaced instruction in copy area, the mode | |
410 | should be determined by instruction on the original address. */ | |
411 | if (dsc) | |
412 | { | |
413 | if (debug_displaced) | |
414 | fprintf_unfiltered (gdb_stdlog, | |
415 | "displaced: check mode of %.8lx instead of %.8lx\n", | |
416 | (unsigned long) dsc->insn_addr, | |
417 | (unsigned long) memaddr); | |
418 | memaddr = dsc->insn_addr; | |
419 | } | |
f9d67f43 DJ |
420 | |
421 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
422 | if (IS_THUMB_ADDR (memaddr)) | |
423 | return 1; | |
424 | ||
18819fa6 UW |
425 | /* Respect internal mode override if active. */ |
426 | if (arm_override_mode != -1) | |
427 | return arm_override_mode; | |
428 | ||
f9d67f43 DJ |
429 | /* If the user wants to override the symbol table, let him. */ |
430 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
431 | return 0; | |
432 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
433 | return 1; | |
434 | ||
9779414d DJ |
435 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
436 | if (gdbarch_tdep (gdbarch)->is_m) | |
437 | return 1; | |
438 | ||
f9d67f43 DJ |
439 | /* If there are mapping symbols, consult them. */ |
440 | type = arm_find_mapping_symbol (memaddr, NULL); | |
441 | if (type) | |
442 | return type == 't'; | |
443 | ||
ed9a39eb | 444 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 445 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
446 | if (sym.minsym) |
447 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
448 | |
449 | /* If the user wants to override the fallback mode, let them. */ | |
450 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
451 | return 0; | |
452 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
453 | return 1; | |
454 | ||
455 | /* If we couldn't find any symbol, but we're talking to a running | |
456 | target, then trust the current value of $cpsr. This lets | |
457 | "display/i $pc" always show the correct mode (though if there is | |
458 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 459 | displayed in the mode it will be executed). */ |
0428b8f5 | 460 | if (target_has_registers) |
18819fa6 | 461 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
462 | |
463 | /* Otherwise we're out of luck; we assume ARM. */ | |
464 | return 0; | |
c906108c SS |
465 | } |
466 | ||
181c1381 | 467 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 468 | static CORE_ADDR |
24568a2c | 469 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 470 | { |
2ae28aa9 YQ |
471 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
472 | (the magic exception return address). */ | |
473 | if (gdbarch_tdep (gdbarch)->is_m | |
474 | && (val & 0xfffffff0) == 0xfffffff0) | |
475 | return val; | |
476 | ||
a3a2ee65 | 477 | if (arm_apcs_32) |
dd6be234 | 478 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 479 | else |
a3a2ee65 | 480 | return (val & 0x03fffffc); |
c906108c SS |
481 | } |
482 | ||
0d39a070 | 483 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
484 | can be safely ignored during prologue skipping. IS_THUMB is true |
485 | if the function is known to be a Thumb function due to the way it | |
486 | is being called. */ | |
0d39a070 | 487 | static int |
e0634ccf | 488 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 489 | { |
e0634ccf | 490 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 491 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
492 | |
493 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 494 | if (msym.minsym != NULL |
77e371c0 | 495 | && BMSYMBOL_VALUE_ADDRESS (msym) == pc |
efd66ac6 | 496 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL) |
e0634ccf | 497 | { |
efd66ac6 | 498 | const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym); |
0d39a070 | 499 | |
e0634ccf UW |
500 | /* The GNU linker's Thumb call stub to foo is named |
501 | __foo_from_thumb. */ | |
502 | if (strstr (name, "_from_thumb") != NULL) | |
503 | name += 2; | |
0d39a070 | 504 | |
e0634ccf UW |
505 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
506 | arguments to their argument types in non-prototyped | |
507 | functions. */ | |
61012eef | 508 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 509 | return 1; |
61012eef | 510 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 511 | return 1; |
0d39a070 | 512 | |
e0634ccf | 513 | /* Internal functions related to thread-local storage. */ |
61012eef | 514 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 515 | return 1; |
61012eef | 516 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
517 | return 1; |
518 | } | |
519 | else | |
520 | { | |
521 | /* If we run against a stripped glibc, we may be unable to identify | |
522 | special functions by name. Check for one important case, | |
523 | __aeabi_read_tp, by comparing the *code* against the default | |
524 | implementation (this is hand-written ARM assembler in glibc). */ | |
525 | ||
526 | if (!is_thumb | |
527 | && read_memory_unsigned_integer (pc, 4, byte_order_for_code) | |
528 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ | |
529 | && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code) | |
530 | == 0xe240f01f) /* sub pc, r0, #31 */ | |
531 | return 1; | |
532 | } | |
ec3d575a | 533 | |
0d39a070 DJ |
534 | return 0; |
535 | } | |
536 | ||
621c6d5b YQ |
537 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
538 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
539 | instruction. */ | |
540 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
541 | ((bits ((insn1), 0, 3) << 12) \ | |
542 | | (bits ((insn1), 10, 10) << 11) \ | |
543 | | (bits ((insn2), 12, 14) << 8) \ | |
544 | | bits ((insn2), 0, 7)) | |
545 | ||
546 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
547 | the 32-bit instruction. */ | |
548 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
549 | ((bits ((insn), 16, 19) << 12) \ | |
550 | | bits ((insn), 0, 11)) | |
551 | ||
ec3d575a UW |
552 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
553 | ||
554 | static unsigned int | |
555 | thumb_expand_immediate (unsigned int imm) | |
556 | { | |
557 | unsigned int count = imm >> 7; | |
558 | ||
559 | if (count < 8) | |
560 | switch (count / 2) | |
561 | { | |
562 | case 0: | |
563 | return imm & 0xff; | |
564 | case 1: | |
565 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
566 | case 2: | |
567 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
568 | case 3: | |
569 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
570 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
571 | } | |
572 | ||
573 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
574 | } | |
575 | ||
540314bd YQ |
576 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
577 | epilogue, 0 otherwise. */ | |
578 | ||
579 | static int | |
580 | thumb_instruction_restores_sp (unsigned short insn) | |
581 | { | |
582 | return (insn == 0x46bd /* mov sp, r7 */ | |
583 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
584 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
585 | } | |
586 | ||
29d73ae4 DJ |
587 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
588 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
589 | clobber the stack frame unexpectedly, or an unknown instruction. |
590 | Return the last address which is definitely safe to skip for an | |
591 | initial breakpoint. */ | |
c906108c SS |
592 | |
593 | static CORE_ADDR | |
29d73ae4 DJ |
594 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
595 | CORE_ADDR start, CORE_ADDR limit, | |
596 | struct arm_prologue_cache *cache) | |
c906108c | 597 | { |
0d39a070 | 598 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 599 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
600 | int i; |
601 | pv_t regs[16]; | |
602 | struct pv_area *stack; | |
603 | struct cleanup *back_to; | |
604 | CORE_ADDR offset; | |
ec3d575a | 605 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 606 | |
29d73ae4 DJ |
607 | for (i = 0; i < 16; i++) |
608 | regs[i] = pv_register (i, 0); | |
55f960e1 | 609 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 DJ |
610 | back_to = make_cleanup_free_pv_area (stack); |
611 | ||
29d73ae4 | 612 | while (start < limit) |
c906108c | 613 | { |
29d73ae4 DJ |
614 | unsigned short insn; |
615 | ||
e17a4113 | 616 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 617 | |
94c30b78 | 618 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 619 | { |
29d73ae4 DJ |
620 | int regno; |
621 | int mask; | |
4be43953 DJ |
622 | |
623 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
624 | break; | |
29d73ae4 DJ |
625 | |
626 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
627 | whether to save LR (R14). */ | |
628 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
629 | ||
630 | /* Calculate offsets of saved R0-R7 and LR. */ | |
631 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
632 | if (mask & (1 << regno)) | |
633 | { | |
29d73ae4 DJ |
634 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
635 | -4); | |
636 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
637 | } | |
da59e081 | 638 | } |
1db01f22 | 639 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 640 | { |
29d73ae4 | 641 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
642 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
643 | -offset); | |
da59e081 | 644 | } |
808f7ab1 YQ |
645 | else if (thumb_instruction_restores_sp (insn)) |
646 | { | |
647 | /* Don't scan past the epilogue. */ | |
648 | break; | |
649 | } | |
0d39a070 DJ |
650 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
651 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
652 | (insn & 0xff) << 2); | |
653 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
654 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
655 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
656 | bits (insn, 6, 8)); | |
657 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
658 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
659 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
660 | bits (insn, 0, 7)); | |
661 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
662 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
663 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
664 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
665 | regs[bits (insn, 6, 8)]); | |
666 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
667 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
668 | { | |
669 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
670 | int rm = bits (insn, 3, 6); | |
671 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
672 | } | |
29d73ae4 | 673 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 674 | { |
29d73ae4 DJ |
675 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
676 | int src_reg = (insn & 0x78) >> 3; | |
677 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 678 | } |
29d73ae4 | 679 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 680 | { |
29d73ae4 DJ |
681 | /* Handle stores to the stack. Normally pushes are used, |
682 | but with GCC -mtpcs-frame, there may be other stores | |
683 | in the prologue to create the frame. */ | |
684 | int regno = (insn >> 8) & 0x7; | |
685 | pv_t addr; | |
686 | ||
687 | offset = (insn & 0xff) << 2; | |
688 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
689 | ||
690 | if (pv_area_store_would_trash (stack, addr)) | |
691 | break; | |
692 | ||
693 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 694 | } |
0d39a070 DJ |
695 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
696 | { | |
697 | int rd = bits (insn, 0, 2); | |
698 | int rn = bits (insn, 3, 5); | |
699 | pv_t addr; | |
700 | ||
701 | offset = bits (insn, 6, 10) << 2; | |
702 | addr = pv_add_constant (regs[rn], offset); | |
703 | ||
704 | if (pv_area_store_would_trash (stack, addr)) | |
705 | break; | |
706 | ||
707 | pv_area_store (stack, addr, 4, regs[rd]); | |
708 | } | |
709 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
710 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
711 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
712 | /* Ignore stores of argument registers to the stack. */ | |
713 | ; | |
714 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
715 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
716 | /* Ignore block loads from the stack, potentially copying | |
717 | parameters from memory. */ | |
718 | ; | |
719 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
720 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
721 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
722 | /* Similarly ignore single loads from the stack. */ | |
723 | ; | |
724 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
725 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
726 | /* Skip register copies, i.e. saves to another register | |
727 | instead of the stack. */ | |
728 | ; | |
729 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
730 | /* Recognize constant loads; even with small stacks these are necessary | |
731 | on Thumb. */ | |
732 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
733 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
734 | { | |
735 | /* Constant pool loads, for the same reason. */ | |
736 | unsigned int constant; | |
737 | CORE_ADDR loc; | |
738 | ||
739 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
740 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
741 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
742 | } | |
db24da6d | 743 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 744 | { |
0d39a070 DJ |
745 | unsigned short inst2; |
746 | ||
747 | inst2 = read_memory_unsigned_integer (start + 2, 2, | |
748 | byte_order_for_code); | |
749 | ||
750 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
751 | { | |
752 | /* BL, BLX. Allow some special function calls when | |
753 | skipping the prologue; GCC generates these before | |
754 | storing arguments to the stack. */ | |
755 | CORE_ADDR nextpc; | |
756 | int j1, j2, imm1, imm2; | |
757 | ||
758 | imm1 = sbits (insn, 0, 10); | |
759 | imm2 = bits (inst2, 0, 10); | |
760 | j1 = bit (inst2, 13); | |
761 | j2 = bit (inst2, 11); | |
762 | ||
763 | offset = ((imm1 << 12) + (imm2 << 1)); | |
764 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
765 | ||
766 | nextpc = start + 4 + offset; | |
767 | /* For BLX make sure to clear the low bits. */ | |
768 | if (bit (inst2, 12) == 0) | |
769 | nextpc = nextpc & 0xfffffffc; | |
770 | ||
e0634ccf UW |
771 | if (!skip_prologue_function (gdbarch, nextpc, |
772 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
773 | break; |
774 | } | |
ec3d575a | 775 | |
0963b4bd MS |
776 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
777 | { registers } */ | |
ec3d575a UW |
778 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
779 | { | |
780 | pv_t addr = regs[bits (insn, 0, 3)]; | |
781 | int regno; | |
782 | ||
783 | if (pv_area_store_would_trash (stack, addr)) | |
784 | break; | |
785 | ||
786 | /* Calculate offsets of saved registers. */ | |
787 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
788 | if (inst2 & (1 << regno)) | |
789 | { | |
790 | addr = pv_add_constant (addr, -4); | |
791 | pv_area_store (stack, addr, 4, regs[regno]); | |
792 | } | |
793 | ||
794 | if (insn & 0x0020) | |
795 | regs[bits (insn, 0, 3)] = addr; | |
796 | } | |
797 | ||
0963b4bd MS |
798 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
799 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
800 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
801 | { | |
802 | int regno1 = bits (inst2, 12, 15); | |
803 | int regno2 = bits (inst2, 8, 11); | |
804 | pv_t addr = regs[bits (insn, 0, 3)]; | |
805 | ||
806 | offset = inst2 & 0xff; | |
807 | if (insn & 0x0080) | |
808 | addr = pv_add_constant (addr, offset); | |
809 | else | |
810 | addr = pv_add_constant (addr, -offset); | |
811 | ||
812 | if (pv_area_store_would_trash (stack, addr)) | |
813 | break; | |
814 | ||
815 | pv_area_store (stack, addr, 4, regs[regno1]); | |
816 | pv_area_store (stack, pv_add_constant (addr, 4), | |
817 | 4, regs[regno2]); | |
818 | ||
819 | if (insn & 0x0020) | |
820 | regs[bits (insn, 0, 3)] = addr; | |
821 | } | |
822 | ||
823 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
824 | && (inst2 & 0x0c00) == 0x0c00 | |
825 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
826 | { | |
827 | int regno = bits (inst2, 12, 15); | |
828 | pv_t addr = regs[bits (insn, 0, 3)]; | |
829 | ||
830 | offset = inst2 & 0xff; | |
831 | if (inst2 & 0x0200) | |
832 | addr = pv_add_constant (addr, offset); | |
833 | else | |
834 | addr = pv_add_constant (addr, -offset); | |
835 | ||
836 | if (pv_area_store_would_trash (stack, addr)) | |
837 | break; | |
838 | ||
839 | pv_area_store (stack, addr, 4, regs[regno]); | |
840 | ||
841 | if (inst2 & 0x0100) | |
842 | regs[bits (insn, 0, 3)] = addr; | |
843 | } | |
844 | ||
845 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
846 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
847 | { | |
848 | int regno = bits (inst2, 12, 15); | |
849 | pv_t addr; | |
850 | ||
851 | offset = inst2 & 0xfff; | |
852 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
853 | ||
854 | if (pv_area_store_would_trash (stack, addr)) | |
855 | break; | |
856 | ||
857 | pv_area_store (stack, addr, 4, regs[regno]); | |
858 | } | |
859 | ||
860 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 861 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 862 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 863 | ; |
ec3d575a UW |
864 | |
865 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
866 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 867 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 868 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 869 | ; |
ec3d575a | 870 | |
0963b4bd MS |
871 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
872 | { registers } */ | |
ec3d575a UW |
873 | && (inst2 & 0x8000) == 0x0000 |
874 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
875 | /* Ignore block loads from the stack, potentially copying | |
876 | parameters from memory. */ | |
0d39a070 | 877 | ; |
ec3d575a | 878 | |
0963b4bd MS |
879 | else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, |
880 | [Rn, #+/-imm] */ | |
0d39a070 | 881 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 882 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 883 | ; |
ec3d575a UW |
884 | |
885 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
886 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 887 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 888 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 889 | ; |
ec3d575a UW |
890 | |
891 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 892 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 893 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 894 | ; |
ec3d575a UW |
895 | |
896 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
897 | && (inst2 & 0x8000) == 0x0000) | |
898 | { | |
899 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
900 | | (bits (inst2, 12, 14) << 8) | |
901 | | bits (inst2, 0, 7)); | |
902 | ||
903 | regs[bits (inst2, 8, 11)] | |
904 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
905 | thumb_expand_immediate (imm)); | |
906 | } | |
907 | ||
908 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
909 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 910 | { |
ec3d575a UW |
911 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
912 | | (bits (inst2, 12, 14) << 8) | |
913 | | bits (inst2, 0, 7)); | |
914 | ||
915 | regs[bits (inst2, 8, 11)] | |
916 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
917 | } | |
918 | ||
919 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
920 | && (inst2 & 0x8000) == 0x0000) | |
921 | { | |
922 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
923 | | (bits (inst2, 12, 14) << 8) | |
924 | | bits (inst2, 0, 7)); | |
925 | ||
926 | regs[bits (inst2, 8, 11)] | |
927 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
928 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
929 | } | |
930 | ||
931 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
932 | && (inst2 & 0x8000) == 0x0000) | |
933 | { | |
934 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
935 | | (bits (inst2, 12, 14) << 8) | |
936 | | bits (inst2, 0, 7)); | |
937 | ||
938 | regs[bits (inst2, 8, 11)] | |
939 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
940 | } | |
941 | ||
942 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
943 | { | |
944 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
945 | | (bits (inst2, 12, 14) << 8) | |
946 | | bits (inst2, 0, 7)); | |
947 | ||
948 | regs[bits (inst2, 8, 11)] | |
949 | = pv_constant (thumb_expand_immediate (imm)); | |
950 | } | |
951 | ||
952 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
953 | { | |
621c6d5b YQ |
954 | unsigned int imm |
955 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
956 | |
957 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
958 | } | |
959 | ||
960 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
961 | && (inst2 & 0xf0f0) == 0) | |
962 | { | |
963 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
964 | int src_reg = inst2 & 0xf; | |
965 | regs[dst_reg] = regs[src_reg]; | |
966 | } | |
967 | ||
968 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
969 | { | |
970 | /* Constant pool loads. */ | |
971 | unsigned int constant; | |
972 | CORE_ADDR loc; | |
973 | ||
cac395ea | 974 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
975 | if (insn & 0x0080) |
976 | loc = start + 4 + offset; | |
977 | else | |
978 | loc = start + 4 - offset; | |
979 | ||
980 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
981 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
982 | } | |
983 | ||
984 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
985 | { | |
986 | /* Constant pool loads. */ | |
987 | unsigned int constant; | |
988 | CORE_ADDR loc; | |
989 | ||
cac395ea | 990 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
991 | if (insn & 0x0080) |
992 | loc = start + 4 + offset; | |
993 | else | |
994 | loc = start + 4 - offset; | |
995 | ||
996 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
997 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
998 | ||
999 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1000 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1001 | } | |
1002 | ||
1003 | else if (thumb2_instruction_changes_pc (insn, inst2)) | |
1004 | { | |
1005 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1006 | break; |
1007 | } | |
ec3d575a UW |
1008 | else |
1009 | { | |
1010 | /* The optimizer might shove anything into the prologue, | |
1011 | so we just skip what we don't recognize. */ | |
1012 | unrecognized_pc = start; | |
1013 | } | |
0d39a070 DJ |
1014 | |
1015 | start += 2; | |
1016 | } | |
ec3d575a | 1017 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1018 | { |
ec3d575a | 1019 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1020 | break; |
3d74b771 | 1021 | } |
ec3d575a UW |
1022 | else |
1023 | { | |
1024 | /* The optimizer might shove anything into the prologue, | |
1025 | so we just skip what we don't recognize. */ | |
1026 | unrecognized_pc = start; | |
1027 | } | |
29d73ae4 DJ |
1028 | |
1029 | start += 2; | |
c906108c SS |
1030 | } |
1031 | ||
0d39a070 DJ |
1032 | if (arm_debug) |
1033 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1034 | paddress (gdbarch, start)); | |
1035 | ||
ec3d575a UW |
1036 | if (unrecognized_pc == 0) |
1037 | unrecognized_pc = start; | |
1038 | ||
29d73ae4 DJ |
1039 | if (cache == NULL) |
1040 | { | |
1041 | do_cleanups (back_to); | |
ec3d575a | 1042 | return unrecognized_pc; |
29d73ae4 DJ |
1043 | } |
1044 | ||
29d73ae4 DJ |
1045 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1046 | { | |
1047 | /* Frame pointer is fp. Frame size is constant. */ | |
1048 | cache->framereg = ARM_FP_REGNUM; | |
1049 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1050 | } | |
1051 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1052 | { | |
1053 | /* Frame pointer is r7. Frame size is constant. */ | |
1054 | cache->framereg = THUMB_FP_REGNUM; | |
1055 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1056 | } | |
72a2e3dc | 1057 | else |
29d73ae4 DJ |
1058 | { |
1059 | /* Try the stack pointer... this is a bit desperate. */ | |
1060 | cache->framereg = ARM_SP_REGNUM; | |
1061 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1062 | } | |
29d73ae4 DJ |
1063 | |
1064 | for (i = 0; i < 16; i++) | |
1065 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
1066 | cache->saved_regs[i].addr = offset; | |
1067 | ||
1068 | do_cleanups (back_to); | |
ec3d575a | 1069 | return unrecognized_pc; |
c906108c SS |
1070 | } |
1071 | ||
621c6d5b YQ |
1072 | |
1073 | /* Try to analyze the instructions starting from PC, which load symbol | |
1074 | __stack_chk_guard. Return the address of instruction after loading this | |
1075 | symbol, set the dest register number to *BASEREG, and set the size of | |
1076 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1077 | not recognized. */ | |
1078 | ||
1079 | static CORE_ADDR | |
1080 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1081 | unsigned int *destreg, int *offset) | |
1082 | { | |
1083 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1084 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1085 | unsigned int low, high, address; | |
1086 | ||
1087 | address = 0; | |
1088 | if (is_thumb) | |
1089 | { | |
1090 | unsigned short insn1 | |
1091 | = read_memory_unsigned_integer (pc, 2, byte_order_for_code); | |
1092 | ||
1093 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1094 | { | |
1095 | *destreg = bits (insn1, 8, 10); | |
1096 | *offset = 2; | |
6ae274b7 YQ |
1097 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1098 | address = read_memory_unsigned_integer (address, 4, | |
1099 | byte_order_for_code); | |
621c6d5b YQ |
1100 | } |
1101 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1102 | { | |
1103 | unsigned short insn2 | |
1104 | = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
1105 | ||
1106 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1107 | ||
1108 | insn1 | |
1109 | = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code); | |
1110 | insn2 | |
1111 | = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code); | |
1112 | ||
1113 | /* movt Rd, #const */ | |
1114 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1115 | { | |
1116 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1117 | *destreg = bits (insn2, 8, 11); | |
1118 | *offset = 8; | |
1119 | address = (high << 16 | low); | |
1120 | } | |
1121 | } | |
1122 | } | |
1123 | else | |
1124 | { | |
2e9e421f UW |
1125 | unsigned int insn |
1126 | = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
1127 | ||
6ae274b7 | 1128 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1129 | { |
6ae274b7 YQ |
1130 | address = bits (insn, 0, 11) + pc + 8; |
1131 | address = read_memory_unsigned_integer (address, 4, | |
1132 | byte_order_for_code); | |
1133 | ||
2e9e421f UW |
1134 | *destreg = bits (insn, 12, 15); |
1135 | *offset = 4; | |
1136 | } | |
1137 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1138 | { | |
1139 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1140 | ||
1141 | insn | |
1142 | = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code); | |
1143 | ||
1144 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1145 | { | |
1146 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1147 | *destreg = bits (insn, 12, 15); | |
1148 | *offset = 8; | |
1149 | address = (high << 16 | low); | |
1150 | } | |
1151 | } | |
621c6d5b YQ |
1152 | } |
1153 | ||
1154 | return address; | |
1155 | } | |
1156 | ||
1157 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1158 | points to the first instruction of this sequence, return the address of |
1159 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1160 | |
1161 | On arm, this sequence of instructions is composed of mainly three steps, | |
1162 | Step 1: load symbol __stack_chk_guard, | |
1163 | Step 2: load from address of __stack_chk_guard, | |
1164 | Step 3: store it to somewhere else. | |
1165 | ||
1166 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1167 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1168 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1169 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1170 | they are, | |
1171 | ||
1172 | movw Rn, #:lower16:__stack_chk_guard | |
1173 | movt Rn, #:upper16:__stack_chk_guard | |
1174 | ||
1175 | On ARMv5t, it is, | |
1176 | ||
1177 | ldr Rn, .Label | |
1178 | .... | |
1179 | .Lable: | |
1180 | .word __stack_chk_guard | |
1181 | ||
1182 | Since ldr/str is a very popular instruction, we can't use them as | |
1183 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1184 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1185 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1186 | ||
1187 | static CORE_ADDR | |
1188 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1189 | { | |
1190 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1191 | unsigned int basereg; |
7cbd4a93 | 1192 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1193 | int offset; |
1194 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1195 | CORE_ADDR addr; | |
1196 | ||
1197 | /* Try to parse the instructions in Step 1. */ | |
1198 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1199 | &basereg, &offset); | |
1200 | if (!addr) | |
1201 | return pc; | |
1202 | ||
1203 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1204 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1205 | Otherwise, this sequence cannot be for stack protector. */ | |
1206 | if (stack_chk_guard.minsym == NULL | |
61012eef | 1207 | || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard")) |
621c6d5b YQ |
1208 | return pc; |
1209 | ||
1210 | if (is_thumb) | |
1211 | { | |
1212 | unsigned int destreg; | |
1213 | unsigned short insn | |
1214 | = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code); | |
1215 | ||
1216 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1217 | if ((insn & 0xf800) != 0x6800) | |
1218 | return pc; | |
1219 | if (bits (insn, 3, 5) != basereg) | |
1220 | return pc; | |
1221 | destreg = bits (insn, 0, 2); | |
1222 | ||
1223 | insn = read_memory_unsigned_integer (pc + offset + 2, 2, | |
1224 | byte_order_for_code); | |
1225 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ | |
1226 | if ((insn & 0xf800) != 0x6000) | |
1227 | return pc; | |
1228 | if (destreg != bits (insn, 0, 2)) | |
1229 | return pc; | |
1230 | } | |
1231 | else | |
1232 | { | |
1233 | unsigned int destreg; | |
1234 | unsigned int insn | |
1235 | = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code); | |
1236 | ||
1237 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1238 | if ((insn & 0x0e500000) != 0x04100000) | |
1239 | return pc; | |
1240 | if (bits (insn, 16, 19) != basereg) | |
1241 | return pc; | |
1242 | destreg = bits (insn, 12, 15); | |
1243 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
1244 | insn = read_memory_unsigned_integer (pc + offset + 4, | |
1245 | 4, byte_order_for_code); | |
1246 | if ((insn & 0x0e500000) != 0x04000000) | |
1247 | return pc; | |
1248 | if (bits (insn, 12, 15) != destreg) | |
1249 | return pc; | |
1250 | } | |
1251 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1252 | on arm. */ | |
1253 | if (is_thumb) | |
1254 | return pc + offset + 4; | |
1255 | else | |
1256 | return pc + offset + 8; | |
1257 | } | |
1258 | ||
da3c6d4a MS |
1259 | /* Advance the PC across any function entry prologue instructions to |
1260 | reach some "real" code. | |
34e8f22d RE |
1261 | |
1262 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1263 | prologue: |
c906108c | 1264 | |
c5aa993b JM |
1265 | mov ip, sp |
1266 | [stmfd sp!, {a1,a2,a3,a4}] | |
1267 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1268 | [stfe f7, [sp, #-12]!] |
1269 | [stfe f6, [sp, #-12]!] | |
1270 | [stfe f5, [sp, #-12]!] | |
1271 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1272 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1273 | |
34e8f22d | 1274 | static CORE_ADDR |
6093d2eb | 1275 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1276 | { |
e17a4113 | 1277 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
c906108c | 1278 | unsigned long inst; |
a89fea3c | 1279 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1280 | |
a89fea3c JL |
1281 | /* See if we can determine the end of the prologue via the symbol table. |
1282 | If so, then return either PC, or the PC after the prologue, whichever | |
1283 | is greater. */ | |
1284 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1285 | { |
d80b854b UW |
1286 | CORE_ADDR post_prologue_pc |
1287 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1288 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1289 | |
621c6d5b YQ |
1290 | if (post_prologue_pc) |
1291 | post_prologue_pc | |
1292 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1293 | ||
1294 | ||
0d39a070 DJ |
1295 | /* GCC always emits a line note before the prologue and another |
1296 | one after, even if the two are at the same address or on the | |
1297 | same line. Take advantage of this so that we do not need to | |
1298 | know every instruction that might appear in the prologue. We | |
1299 | will have producer information for most binaries; if it is | |
1300 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1301 | if (post_prologue_pc | |
43f3e411 DE |
1302 | && (cust == NULL |
1303 | || COMPUNIT_PRODUCER (cust) == NULL | |
61012eef GB |
1304 | || startswith (COMPUNIT_PRODUCER (cust), "GNU ") |
1305 | || startswith (COMPUNIT_PRODUCER (cust), "clang "))) | |
0d39a070 DJ |
1306 | return post_prologue_pc; |
1307 | ||
a89fea3c | 1308 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1309 | { |
1310 | CORE_ADDR analyzed_limit; | |
1311 | ||
1312 | /* For non-GCC compilers, make sure the entire line is an | |
1313 | acceptable prologue; GDB will round this function's | |
1314 | return value up to the end of the following line so we | |
1315 | can not skip just part of a line (and we do not want to). | |
1316 | ||
1317 | RealView does not treat the prologue specially, but does | |
1318 | associate prologue code with the opening brace; so this | |
1319 | lets us skip the first line if we think it is the opening | |
1320 | brace. */ | |
9779414d | 1321 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1322 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1323 | post_prologue_pc, NULL); | |
1324 | else | |
1325 | analyzed_limit = arm_analyze_prologue (gdbarch, func_addr, | |
1326 | post_prologue_pc, NULL); | |
1327 | ||
1328 | if (analyzed_limit != post_prologue_pc) | |
1329 | return func_addr; | |
1330 | ||
1331 | return post_prologue_pc; | |
1332 | } | |
c906108c SS |
1333 | } |
1334 | ||
a89fea3c JL |
1335 | /* Can't determine prologue from the symbol table, need to examine |
1336 | instructions. */ | |
c906108c | 1337 | |
a89fea3c JL |
1338 | /* Find an upper limit on the function prologue using the debug |
1339 | information. If the debug information could not be used to provide | |
1340 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1341 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1342 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1343 | if (limit_pc == 0) |
1344 | limit_pc = pc + 64; /* Magic. */ | |
1345 | ||
c906108c | 1346 | |
29d73ae4 | 1347 | /* Check if this is Thumb code. */ |
9779414d | 1348 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1349 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf YQ |
1350 | else |
1351 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
c906108c | 1352 | } |
94c30b78 | 1353 | |
c5aa993b | 1354 | /* *INDENT-OFF* */ |
c906108c SS |
1355 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1356 | This function decodes a Thumb function prologue to determine: | |
1357 | 1) the size of the stack frame | |
1358 | 2) which registers are saved on it | |
1359 | 3) the offsets of saved regs | |
1360 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1361 | |
da59e081 JM |
1362 | A typical Thumb function prologue would create this stack frame |
1363 | (offsets relative to FP) | |
c906108c SS |
1364 | old SP -> 24 stack parameters |
1365 | 20 LR | |
1366 | 16 R7 | |
1367 | R7 -> 0 local variables (16 bytes) | |
1368 | SP -> -12 additional stack space (12 bytes) | |
1369 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1370 | 12 bytes. The frame register is R7. |
da59e081 | 1371 | |
da3c6d4a MS |
1372 | The comments for thumb_skip_prolog() describe the algorithm we use |
1373 | to detect the end of the prolog. */ | |
c5aa993b JM |
1374 | /* *INDENT-ON* */ |
1375 | ||
c906108c | 1376 | static void |
be8626e0 | 1377 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1378 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1379 | { |
1380 | CORE_ADDR prologue_start; | |
1381 | CORE_ADDR prologue_end; | |
c906108c | 1382 | |
b39cc962 DJ |
1383 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1384 | &prologue_end)) | |
c906108c | 1385 | { |
ec3d575a UW |
1386 | /* See comment in arm_scan_prologue for an explanation of |
1387 | this heuristics. */ | |
1388 | if (prologue_end > prologue_start + 64) | |
1389 | { | |
1390 | prologue_end = prologue_start + 64; | |
1391 | } | |
c906108c SS |
1392 | } |
1393 | else | |
f7060f85 DJ |
1394 | /* We're in the boondocks: we have no idea where the start of the |
1395 | function is. */ | |
1396 | return; | |
c906108c | 1397 | |
eb5492fa | 1398 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 1399 | |
be8626e0 | 1400 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1401 | } |
1402 | ||
f303bc3e YQ |
1403 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1404 | otherwise. */ | |
1405 | ||
1406 | static int | |
1407 | arm_instruction_restores_sp (unsigned int insn) | |
1408 | { | |
1409 | if (bits (insn, 28, 31) != INST_NV) | |
1410 | { | |
1411 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1412 | /* ADD SP (register or immediate). */ | |
1413 | || (insn & 0x0df0f000) == 0x0040d000 | |
1414 | /* SUB SP (register or immediate). */ | |
1415 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1416 | /* MOV SP. */ | |
1417 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1418 | /* POP (LDMIA). */ | |
1419 | || (insn & 0x0fff0000) == 0x049d0000) | |
1420 | /* POP of a single register. */ | |
1421 | return 1; | |
1422 | } | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
0d39a070 DJ |
1427 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1428 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1429 | fill it in. Return the first address not recognized as a prologue | |
1430 | instruction. | |
eb5492fa | 1431 | |
0d39a070 DJ |
1432 | We recognize all the instructions typically found in ARM prologues, |
1433 | plus harmless instructions which can be skipped (either for analysis | |
1434 | purposes, or a more restrictive set that can be skipped when finding | |
1435 | the end of the prologue). */ | |
1436 | ||
1437 | static CORE_ADDR | |
1438 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1439 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
1440 | struct arm_prologue_cache *cache) | |
1441 | { | |
1442 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1443 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1444 | int regno; | |
1445 | CORE_ADDR offset, current_pc; | |
1446 | pv_t regs[ARM_FPS_REGNUM]; | |
1447 | struct pv_area *stack; | |
1448 | struct cleanup *back_to; | |
0d39a070 DJ |
1449 | CORE_ADDR unrecognized_pc = 0; |
1450 | ||
1451 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1452 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1453 | |
96baa820 JM |
1454 | Be careful, however, and if it doesn't look like a prologue, |
1455 | don't try to scan it. If, for instance, a frameless function | |
1456 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1457 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1458 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1459 | traceback. */ |
d4473757 | 1460 | |
4be43953 DJ |
1461 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1462 | regs[regno] = pv_register (regno, 0); | |
55f960e1 | 1463 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 DJ |
1464 | back_to = make_cleanup_free_pv_area (stack); |
1465 | ||
94c30b78 MS |
1466 | for (current_pc = prologue_start; |
1467 | current_pc < prologue_end; | |
f43845b3 | 1468 | current_pc += 4) |
96baa820 | 1469 | { |
e17a4113 UW |
1470 | unsigned int insn |
1471 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); | |
9d4fde75 | 1472 | |
94c30b78 | 1473 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1474 | { |
4be43953 | 1475 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1476 | continue; |
1477 | } | |
0d39a070 DJ |
1478 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1479 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 JG |
1480 | { |
1481 | unsigned imm = insn & 0xff; /* immediate value */ | |
1482 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
0d39a070 | 1483 | int rd = bits (insn, 12, 15); |
28cd8767 | 1484 | imm = (imm >> rot) | (imm << (32 - rot)); |
0d39a070 | 1485 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1486 | continue; |
1487 | } | |
0d39a070 DJ |
1488 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1489 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 JG |
1490 | { |
1491 | unsigned imm = insn & 0xff; /* immediate value */ | |
1492 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
0d39a070 | 1493 | int rd = bits (insn, 12, 15); |
28cd8767 | 1494 | imm = (imm >> rot) | (imm << (32 - rot)); |
0d39a070 | 1495 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1496 | continue; |
1497 | } | |
0963b4bd MS |
1498 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1499 | [sp, #-4]! */ | |
f43845b3 | 1500 | { |
4be43953 DJ |
1501 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1502 | break; | |
1503 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
0d39a070 DJ |
1504 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, |
1505 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1506 | continue; |
1507 | } | |
1508 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1509 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1510 | or | |
1511 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1512 | { |
d4473757 | 1513 | int mask = insn & 0xffff; |
ed9a39eb | 1514 | |
4be43953 DJ |
1515 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1516 | break; | |
1517 | ||
94c30b78 | 1518 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1519 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1520 | if (mask & (1 << regno)) |
1521 | { | |
0963b4bd MS |
1522 | regs[ARM_SP_REGNUM] |
1523 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
4be43953 | 1524 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1525 | } |
1526 | } | |
0d39a070 DJ |
1527 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1528 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1529 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1530 | { |
1531 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1532 | continue; | |
1533 | } | |
0d39a070 DJ |
1534 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1535 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1536 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1537 | { |
1538 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1539 | continue; | |
1540 | } | |
0963b4bd MS |
1541 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1542 | { registers } */ | |
0d39a070 DJ |
1543 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1544 | { | |
1545 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1546 | continue; | |
1547 | } | |
d4473757 KB |
1548 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1549 | { | |
94c30b78 MS |
1550 | unsigned imm = insn & 0xff; /* immediate value */ |
1551 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 1552 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 1553 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1554 | } |
1555 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1556 | { | |
94c30b78 MS |
1557 | unsigned imm = insn & 0xff; /* immediate value */ |
1558 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 1559 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 1560 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1561 | } |
0963b4bd MS |
1562 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1563 | [sp, -#c]! */ | |
2af46ca0 | 1564 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 1565 | { |
4be43953 DJ |
1566 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1567 | break; | |
1568 | ||
1569 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1570 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 1571 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1572 | } |
0963b4bd MS |
1573 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1574 | [sp!] */ | |
2af46ca0 | 1575 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
1576 | { |
1577 | int n_saved_fp_regs; | |
1578 | unsigned int fp_start_reg, fp_bound_reg; | |
1579 | ||
4be43953 DJ |
1580 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1581 | break; | |
1582 | ||
94c30b78 | 1583 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1584 | { |
d4473757 KB |
1585 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1586 | n_saved_fp_regs = 3; | |
1587 | else | |
1588 | n_saved_fp_regs = 1; | |
96baa820 | 1589 | } |
d4473757 | 1590 | else |
96baa820 | 1591 | { |
d4473757 KB |
1592 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1593 | n_saved_fp_regs = 2; | |
1594 | else | |
1595 | n_saved_fp_regs = 4; | |
96baa820 | 1596 | } |
d4473757 | 1597 | |
34e8f22d | 1598 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1599 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1600 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1601 | { |
4be43953 DJ |
1602 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
1603 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
1604 | regs[fp_start_reg++]); | |
96baa820 | 1605 | } |
c906108c | 1606 | } |
0d39a070 DJ |
1607 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
1608 | { | |
1609 | /* Allow some special function calls when skipping the | |
1610 | prologue; GCC generates these before storing arguments to | |
1611 | the stack. */ | |
1612 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
1613 | ||
e0634ccf | 1614 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
1615 | continue; |
1616 | else | |
1617 | break; | |
1618 | } | |
d4473757 | 1619 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 1620 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
1621 | else if (arm_instruction_changes_pc (insn)) |
1622 | /* Don't scan past anything that might change control flow. */ | |
1623 | break; | |
f303bc3e YQ |
1624 | else if (arm_instruction_restores_sp (insn)) |
1625 | { | |
1626 | /* Don't scan past the epilogue. */ | |
1627 | break; | |
1628 | } | |
d19f7eee UW |
1629 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
1630 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1631 | /* Ignore block loads from the stack, potentially copying | |
1632 | parameters from memory. */ | |
1633 | continue; | |
1634 | else if ((insn & 0xfc500000) == 0xe4100000 | |
1635 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1636 | /* Similarly ignore single loads from the stack. */ | |
1637 | continue; | |
0d39a070 DJ |
1638 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
1639 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
1640 | register instead of the stack. */ | |
d4473757 | 1641 | continue; |
0d39a070 DJ |
1642 | else |
1643 | { | |
21daaaaf YQ |
1644 | /* The optimizer might shove anything into the prologue, if |
1645 | we build up cache (cache != NULL) from scanning prologue, | |
1646 | we just skip what we don't recognize and scan further to | |
1647 | make cache as complete as possible. However, if we skip | |
1648 | prologue, we'll stop immediately on unrecognized | |
1649 | instruction. */ | |
0d39a070 | 1650 | unrecognized_pc = current_pc; |
21daaaaf YQ |
1651 | if (cache != NULL) |
1652 | continue; | |
1653 | else | |
1654 | break; | |
0d39a070 | 1655 | } |
c906108c SS |
1656 | } |
1657 | ||
0d39a070 DJ |
1658 | if (unrecognized_pc == 0) |
1659 | unrecognized_pc = current_pc; | |
1660 | ||
0d39a070 DJ |
1661 | if (cache) |
1662 | { | |
4072f920 YQ |
1663 | int framereg, framesize; |
1664 | ||
1665 | /* The frame size is just the distance from the frame register | |
1666 | to the original stack pointer. */ | |
1667 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1668 | { | |
1669 | /* Frame pointer is fp. */ | |
1670 | framereg = ARM_FP_REGNUM; | |
1671 | framesize = -regs[ARM_FP_REGNUM].k; | |
1672 | } | |
1673 | else | |
1674 | { | |
1675 | /* Try the stack pointer... this is a bit desperate. */ | |
1676 | framereg = ARM_SP_REGNUM; | |
1677 | framesize = -regs[ARM_SP_REGNUM].k; | |
1678 | } | |
1679 | ||
0d39a070 DJ |
1680 | cache->framereg = framereg; |
1681 | cache->framesize = framesize; | |
1682 | ||
1683 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
1684 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
1685 | cache->saved_regs[regno].addr = offset; | |
1686 | } | |
1687 | ||
1688 | if (arm_debug) | |
1689 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1690 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 DJ |
1691 | |
1692 | do_cleanups (back_to); | |
0d39a070 DJ |
1693 | return unrecognized_pc; |
1694 | } | |
1695 | ||
1696 | static void | |
1697 | arm_scan_prologue (struct frame_info *this_frame, | |
1698 | struct arm_prologue_cache *cache) | |
1699 | { | |
1700 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1701 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1702 | int regno; | |
1703 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
1704 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
1705 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
1706 | pv_t regs[ARM_FPS_REGNUM]; | |
1707 | struct pv_area *stack; | |
1708 | struct cleanup *back_to; | |
1709 | CORE_ADDR offset; | |
1710 | ||
1711 | /* Assume there is no frame until proven otherwise. */ | |
1712 | cache->framereg = ARM_SP_REGNUM; | |
1713 | cache->framesize = 0; | |
1714 | ||
1715 | /* Check for Thumb prologue. */ | |
1716 | if (arm_frame_is_thumb (this_frame)) | |
1717 | { | |
1718 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
1719 | return; | |
1720 | } | |
1721 | ||
1722 | /* Find the function prologue. If we can't find the function in | |
1723 | the symbol table, peek in the stack frame to find the PC. */ | |
1724 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
1725 | &prologue_end)) | |
1726 | { | |
1727 | /* One way to find the end of the prologue (which works well | |
1728 | for unoptimized code) is to do the following: | |
1729 | ||
1730 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
1731 | ||
1732 | if (sal.line == 0) | |
1733 | prologue_end = prev_pc; | |
1734 | else if (sal.end < prologue_end) | |
1735 | prologue_end = sal.end; | |
1736 | ||
1737 | This mechanism is very accurate so long as the optimizer | |
1738 | doesn't move any instructions from the function body into the | |
1739 | prologue. If this happens, sal.end will be the last | |
1740 | instruction in the first hunk of prologue code just before | |
1741 | the first instruction that the scheduler has moved from | |
1742 | the body to the prologue. | |
1743 | ||
1744 | In order to make sure that we scan all of the prologue | |
1745 | instructions, we use a slightly less accurate mechanism which | |
1746 | may scan more than necessary. To help compensate for this | |
1747 | lack of accuracy, the prologue scanning loop below contains | |
1748 | several clauses which'll cause the loop to terminate early if | |
1749 | an implausible prologue instruction is encountered. | |
1750 | ||
1751 | The expression | |
1752 | ||
1753 | prologue_start + 64 | |
1754 | ||
1755 | is a suitable endpoint since it accounts for the largest | |
1756 | possible prologue plus up to five instructions inserted by | |
1757 | the scheduler. */ | |
1758 | ||
1759 | if (prologue_end > prologue_start + 64) | |
1760 | { | |
1761 | prologue_end = prologue_start + 64; /* See above. */ | |
1762 | } | |
1763 | } | |
1764 | else | |
1765 | { | |
1766 | /* We have no symbol information. Our only option is to assume this | |
1767 | function has a standard stack frame and the normal frame register. | |
1768 | Then, we can find the value of our frame pointer on entrance to | |
1769 | the callee (or at the present moment if this is the innermost frame). | |
1770 | The value stored there should be the address of the stmfd + 8. */ | |
1771 | CORE_ADDR frame_loc; | |
1772 | LONGEST return_value; | |
1773 | ||
1774 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); | |
1775 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) | |
1776 | return; | |
1777 | else | |
1778 | { | |
1779 | prologue_start = gdbarch_addr_bits_remove | |
1780 | (gdbarch, return_value) - 8; | |
1781 | prologue_end = prologue_start + 64; /* See above. */ | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | if (prev_pc < prologue_end) | |
1786 | prologue_end = prev_pc; | |
1787 | ||
1788 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); | |
c906108c SS |
1789 | } |
1790 | ||
eb5492fa | 1791 | static struct arm_prologue_cache * |
a262aec2 | 1792 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1793 | { |
eb5492fa DJ |
1794 | int reg; |
1795 | struct arm_prologue_cache *cache; | |
1796 | CORE_ADDR unwound_fp; | |
c5aa993b | 1797 | |
35d5d4ee | 1798 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1799 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1800 | |
a262aec2 | 1801 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1802 | |
a262aec2 | 1803 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1804 | if (unwound_fp == 0) |
1805 | return cache; | |
c906108c | 1806 | |
4be43953 | 1807 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1808 | |
eb5492fa DJ |
1809 | /* Calculate actual addresses of saved registers using offsets |
1810 | determined by arm_scan_prologue. */ | |
a262aec2 | 1811 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 1812 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
1813 | cache->saved_regs[reg].addr += cache->prev_sp; |
1814 | ||
1815 | return cache; | |
c906108c SS |
1816 | } |
1817 | ||
c1ee9414 LM |
1818 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
1819 | ||
1820 | static enum unwind_stop_reason | |
1821 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
1822 | void **this_cache) | |
1823 | { | |
1824 | struct arm_prologue_cache *cache; | |
1825 | CORE_ADDR pc; | |
1826 | ||
1827 | if (*this_cache == NULL) | |
1828 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 1829 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
1830 | |
1831 | /* This is meant to halt the backtrace at "_start". */ | |
1832 | pc = get_frame_pc (this_frame); | |
1833 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
1834 | return UNWIND_OUTERMOST; | |
1835 | ||
1836 | /* If we've hit a wall, stop. */ | |
1837 | if (cache->prev_sp == 0) | |
1838 | return UNWIND_OUTERMOST; | |
1839 | ||
1840 | return UNWIND_NO_REASON; | |
1841 | } | |
1842 | ||
eb5492fa DJ |
1843 | /* Our frame ID for a normal frame is the current function's starting PC |
1844 | and the caller's SP when we were called. */ | |
c906108c | 1845 | |
148754e5 | 1846 | static void |
a262aec2 | 1847 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1848 | void **this_cache, |
1849 | struct frame_id *this_id) | |
c906108c | 1850 | { |
eb5492fa DJ |
1851 | struct arm_prologue_cache *cache; |
1852 | struct frame_id id; | |
2c404490 | 1853 | CORE_ADDR pc, func; |
f079148d | 1854 | |
eb5492fa | 1855 | if (*this_cache == NULL) |
a262aec2 | 1856 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1857 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 1858 | |
0e9e9abd UW |
1859 | /* Use function start address as part of the frame ID. If we cannot |
1860 | identify the start address (due to missing symbol information), | |
1861 | fall back to just using the current PC. */ | |
c1ee9414 | 1862 | pc = get_frame_pc (this_frame); |
2c404490 | 1863 | func = get_frame_func (this_frame); |
0e9e9abd UW |
1864 | if (!func) |
1865 | func = pc; | |
1866 | ||
eb5492fa | 1867 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1868 | *this_id = id; |
c906108c SS |
1869 | } |
1870 | ||
a262aec2 DJ |
1871 | static struct value * |
1872 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1873 | void **this_cache, |
a262aec2 | 1874 | int prev_regnum) |
24de872b | 1875 | { |
24568a2c | 1876 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1877 | struct arm_prologue_cache *cache; |
1878 | ||
eb5492fa | 1879 | if (*this_cache == NULL) |
a262aec2 | 1880 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1881 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 1882 | |
eb5492fa | 1883 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1884 | instead. The prologue may save PC, but it will point into this |
1885 | frame's prologue, not the next frame's resume location. Also | |
1886 | strip the saved T bit. A valid LR may have the low bit set, but | |
1887 | a valid PC never does. */ | |
eb5492fa | 1888 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1889 | { |
1890 | CORE_ADDR lr; | |
1891 | ||
1892 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1893 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1894 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1895 | } |
24de872b | 1896 | |
eb5492fa | 1897 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1898 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1899 | The value was already reconstructed into PREV_SP. */ |
1900 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1901 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1902 | |
b39cc962 DJ |
1903 | /* The CPSR may have been changed by the call instruction and by the |
1904 | called function. The only bit we can reconstruct is the T bit, | |
1905 | by checking the low bit of LR as of the call. This is a reliable | |
1906 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
1907 | Thumb code, which could get away with a clear low bit as long as | |
1908 | the called function did not use bx. Guess that all other | |
1909 | bits are unchanged; the condition flags are presumably lost, | |
1910 | but the processor status is likely valid. */ | |
1911 | if (prev_regnum == ARM_PS_REGNUM) | |
1912 | { | |
1913 | CORE_ADDR lr, cpsr; | |
9779414d | 1914 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
1915 | |
1916 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
1917 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1918 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 1919 | cpsr |= t_bit; |
b39cc962 | 1920 | else |
9779414d | 1921 | cpsr &= ~t_bit; |
b39cc962 DJ |
1922 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
1923 | } | |
1924 | ||
a262aec2 DJ |
1925 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
1926 | prev_regnum); | |
eb5492fa DJ |
1927 | } |
1928 | ||
1929 | struct frame_unwind arm_prologue_unwind = { | |
1930 | NORMAL_FRAME, | |
c1ee9414 | 1931 | arm_prologue_unwind_stop_reason, |
eb5492fa | 1932 | arm_prologue_this_id, |
a262aec2 DJ |
1933 | arm_prologue_prev_register, |
1934 | NULL, | |
1935 | default_frame_sniffer | |
eb5492fa DJ |
1936 | }; |
1937 | ||
0e9e9abd UW |
1938 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
1939 | list of mapping symbols. We only cache entries for standard ARM-defined | |
1940 | personality routines; the cache will contain only the frame unwinding | |
1941 | instructions associated with the entry (not the descriptors). */ | |
1942 | ||
1943 | static const struct objfile_data *arm_exidx_data_key; | |
1944 | ||
1945 | struct arm_exidx_entry | |
1946 | { | |
1947 | bfd_vma addr; | |
1948 | gdb_byte *entry; | |
1949 | }; | |
1950 | typedef struct arm_exidx_entry arm_exidx_entry_s; | |
1951 | DEF_VEC_O(arm_exidx_entry_s); | |
1952 | ||
1953 | struct arm_exidx_data | |
1954 | { | |
1955 | VEC(arm_exidx_entry_s) **section_maps; | |
1956 | }; | |
1957 | ||
1958 | static void | |
1959 | arm_exidx_data_free (struct objfile *objfile, void *arg) | |
1960 | { | |
9a3c8263 | 1961 | struct arm_exidx_data *data = (struct arm_exidx_data *) arg; |
0e9e9abd UW |
1962 | unsigned int i; |
1963 | ||
1964 | for (i = 0; i < objfile->obfd->section_count; i++) | |
1965 | VEC_free (arm_exidx_entry_s, data->section_maps[i]); | |
1966 | } | |
1967 | ||
1968 | static inline int | |
1969 | arm_compare_exidx_entries (const struct arm_exidx_entry *lhs, | |
1970 | const struct arm_exidx_entry *rhs) | |
1971 | { | |
1972 | return lhs->addr < rhs->addr; | |
1973 | } | |
1974 | ||
1975 | static struct obj_section * | |
1976 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
1977 | { | |
1978 | struct obj_section *osect; | |
1979 | ||
1980 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
1981 | if (bfd_get_section_flags (objfile->obfd, | |
1982 | osect->the_bfd_section) & SEC_ALLOC) | |
1983 | { | |
1984 | bfd_vma start, size; | |
1985 | start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section); | |
1986 | size = bfd_get_section_size (osect->the_bfd_section); | |
1987 | ||
1988 | if (start <= vma && vma < start + size) | |
1989 | return osect; | |
1990 | } | |
1991 | ||
1992 | return NULL; | |
1993 | } | |
1994 | ||
1995 | /* Parse contents of exception table and exception index sections | |
1996 | of OBJFILE, and fill in the exception table entry cache. | |
1997 | ||
1998 | For each entry that refers to a standard ARM-defined personality | |
1999 | routine, extract the frame unwinding instructions (from either | |
2000 | the index or the table section). The unwinding instructions | |
2001 | are normalized by: | |
2002 | - extracting them from the rest of the table data | |
2003 | - converting to host endianness | |
2004 | - appending the implicit 0xb0 ("Finish") code | |
2005 | ||
2006 | The extracted and normalized instructions are stored for later | |
2007 | retrieval by the arm_find_exidx_entry routine. */ | |
2008 | ||
2009 | static void | |
2010 | arm_exidx_new_objfile (struct objfile *objfile) | |
2011 | { | |
3bb47e8b | 2012 | struct cleanup *cleanups; |
0e9e9abd UW |
2013 | struct arm_exidx_data *data; |
2014 | asection *exidx, *extab; | |
2015 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
2016 | bfd_size_type exidx_size = 0, extab_size = 0; | |
2017 | gdb_byte *exidx_data = NULL, *extab_data = NULL; | |
2018 | LONGEST i; | |
2019 | ||
2020 | /* If we've already touched this file, do nothing. */ | |
2021 | if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL) | |
2022 | return; | |
3bb47e8b | 2023 | cleanups = make_cleanup (null_cleanup, NULL); |
0e9e9abd UW |
2024 | |
2025 | /* Read contents of exception table and index. */ | |
a5eda10c | 2026 | exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); |
0e9e9abd UW |
2027 | if (exidx) |
2028 | { | |
2029 | exidx_vma = bfd_section_vma (objfile->obfd, exidx); | |
2030 | exidx_size = bfd_get_section_size (exidx); | |
224c3ddb | 2031 | exidx_data = (gdb_byte *) xmalloc (exidx_size); |
0e9e9abd UW |
2032 | make_cleanup (xfree, exidx_data); |
2033 | ||
2034 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
2035 | exidx_data, 0, exidx_size)) | |
2036 | { | |
2037 | do_cleanups (cleanups); | |
2038 | return; | |
2039 | } | |
2040 | } | |
2041 | ||
2042 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
2043 | if (extab) | |
2044 | { | |
2045 | extab_vma = bfd_section_vma (objfile->obfd, extab); | |
2046 | extab_size = bfd_get_section_size (extab); | |
224c3ddb | 2047 | extab_data = (gdb_byte *) xmalloc (extab_size); |
0e9e9abd UW |
2048 | make_cleanup (xfree, extab_data); |
2049 | ||
2050 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
2051 | extab_data, 0, extab_size)) | |
2052 | { | |
2053 | do_cleanups (cleanups); | |
2054 | return; | |
2055 | } | |
2056 | } | |
2057 | ||
2058 | /* Allocate exception table data structure. */ | |
2059 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data); | |
2060 | set_objfile_data (objfile, arm_exidx_data_key, data); | |
2061 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
2062 | objfile->obfd->section_count, | |
2063 | VEC(arm_exidx_entry_s) *); | |
2064 | ||
2065 | /* Fill in exception table. */ | |
2066 | for (i = 0; i < exidx_size / 8; i++) | |
2067 | { | |
2068 | struct arm_exidx_entry new_exidx_entry; | |
2069 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8); | |
2070 | bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4); | |
2071 | bfd_vma addr = 0, word = 0; | |
2072 | int n_bytes = 0, n_words = 0; | |
2073 | struct obj_section *sec; | |
2074 | gdb_byte *entry = NULL; | |
2075 | ||
2076 | /* Extract address of start of function. */ | |
2077 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2078 | idx += exidx_vma + i * 8; | |
2079 | ||
2080 | /* Find section containing function and compute section offset. */ | |
2081 | sec = arm_obj_section_from_vma (objfile, idx); | |
2082 | if (sec == NULL) | |
2083 | continue; | |
2084 | idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section); | |
2085 | ||
2086 | /* Determine address of exception table entry. */ | |
2087 | if (val == 1) | |
2088 | { | |
2089 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2090 | } | |
2091 | else if ((val & 0xff000000) == 0x80000000) | |
2092 | { | |
2093 | /* Exception table entry embedded in .ARM.exidx | |
2094 | -- must be short form. */ | |
2095 | word = val; | |
2096 | n_bytes = 3; | |
2097 | } | |
2098 | else if (!(val & 0x80000000)) | |
2099 | { | |
2100 | /* Exception table entry in .ARM.extab. */ | |
2101 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2102 | addr += exidx_vma + i * 8 + 4; | |
2103 | ||
2104 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size) | |
2105 | { | |
2106 | word = bfd_h_get_32 (objfile->obfd, | |
2107 | extab_data + addr - extab_vma); | |
2108 | addr += 4; | |
2109 | ||
2110 | if ((word & 0xff000000) == 0x80000000) | |
2111 | { | |
2112 | /* Short form. */ | |
2113 | n_bytes = 3; | |
2114 | } | |
2115 | else if ((word & 0xff000000) == 0x81000000 | |
2116 | || (word & 0xff000000) == 0x82000000) | |
2117 | { | |
2118 | /* Long form. */ | |
2119 | n_bytes = 2; | |
2120 | n_words = ((word >> 16) & 0xff); | |
2121 | } | |
2122 | else if (!(word & 0x80000000)) | |
2123 | { | |
2124 | bfd_vma pers; | |
2125 | struct obj_section *pers_sec; | |
2126 | int gnu_personality = 0; | |
2127 | ||
2128 | /* Custom personality routine. */ | |
2129 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2130 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2131 | ||
2132 | /* Check whether we've got one of the variants of the | |
2133 | GNU personality routines. */ | |
2134 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2135 | if (pers_sec) | |
2136 | { | |
2137 | static const char *personality[] = | |
2138 | { | |
2139 | "__gcc_personality_v0", | |
2140 | "__gxx_personality_v0", | |
2141 | "__gcj_personality_v0", | |
2142 | "__gnu_objc_personality_v0", | |
2143 | NULL | |
2144 | }; | |
2145 | ||
2146 | CORE_ADDR pc = pers + obj_section_offset (pers_sec); | |
2147 | int k; | |
2148 | ||
2149 | for (k = 0; personality[k]; k++) | |
2150 | if (lookup_minimal_symbol_by_pc_name | |
2151 | (pc, personality[k], objfile)) | |
2152 | { | |
2153 | gnu_personality = 1; | |
2154 | break; | |
2155 | } | |
2156 | } | |
2157 | ||
2158 | /* If so, the next word contains a word count in the high | |
2159 | byte, followed by the same unwind instructions as the | |
2160 | pre-defined forms. */ | |
2161 | if (gnu_personality | |
2162 | && addr + 4 <= extab_vma + extab_size) | |
2163 | { | |
2164 | word = bfd_h_get_32 (objfile->obfd, | |
2165 | extab_data + addr - extab_vma); | |
2166 | addr += 4; | |
2167 | n_bytes = 3; | |
2168 | n_words = ((word >> 24) & 0xff); | |
2169 | } | |
2170 | } | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | /* Sanity check address. */ | |
2175 | if (n_words) | |
2176 | if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size) | |
2177 | n_words = n_bytes = 0; | |
2178 | ||
2179 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2180 | significant bytes are valid), followed by N_WORDS words in the | |
2181 | extab section starting at ADDR. */ | |
2182 | if (n_bytes || n_words) | |
2183 | { | |
224c3ddb SM |
2184 | gdb_byte *p = entry |
2185 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2186 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2187 | |
2188 | while (n_bytes--) | |
2189 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2190 | ||
2191 | while (n_words--) | |
2192 | { | |
2193 | word = bfd_h_get_32 (objfile->obfd, | |
2194 | extab_data + addr - extab_vma); | |
2195 | addr += 4; | |
2196 | ||
2197 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2198 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2199 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2200 | *p++ = (gdb_byte) (word & 0xff); | |
2201 | } | |
2202 | ||
2203 | /* Implied "Finish" to terminate the list. */ | |
2204 | *p++ = 0xb0; | |
2205 | } | |
2206 | ||
2207 | /* Push entry onto vector. They are guaranteed to always | |
2208 | appear in order of increasing addresses. */ | |
2209 | new_exidx_entry.addr = idx; | |
2210 | new_exidx_entry.entry = entry; | |
2211 | VEC_safe_push (arm_exidx_entry_s, | |
2212 | data->section_maps[sec->the_bfd_section->index], | |
2213 | &new_exidx_entry); | |
2214 | } | |
2215 | ||
2216 | do_cleanups (cleanups); | |
2217 | } | |
2218 | ||
2219 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2220 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2221 | set *START to the start of the region covered by this entry. */ | |
2222 | ||
2223 | static gdb_byte * | |
2224 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2225 | { | |
2226 | struct obj_section *sec; | |
2227 | ||
2228 | sec = find_pc_section (memaddr); | |
2229 | if (sec != NULL) | |
2230 | { | |
2231 | struct arm_exidx_data *data; | |
2232 | VEC(arm_exidx_entry_s) *map; | |
2233 | struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 }; | |
2234 | unsigned int idx; | |
2235 | ||
9a3c8263 SM |
2236 | data = ((struct arm_exidx_data *) |
2237 | objfile_data (sec->objfile, arm_exidx_data_key)); | |
0e9e9abd UW |
2238 | if (data != NULL) |
2239 | { | |
2240 | map = data->section_maps[sec->the_bfd_section->index]; | |
2241 | if (!VEC_empty (arm_exidx_entry_s, map)) | |
2242 | { | |
2243 | struct arm_exidx_entry *map_sym; | |
2244 | ||
2245 | idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key, | |
2246 | arm_compare_exidx_entries); | |
2247 | ||
2248 | /* VEC_lower_bound finds the earliest ordered insertion | |
2249 | point. If the following symbol starts at this exact | |
2250 | address, we use that; otherwise, the preceding | |
2251 | exception table entry covers this address. */ | |
2252 | if (idx < VEC_length (arm_exidx_entry_s, map)) | |
2253 | { | |
2254 | map_sym = VEC_index (arm_exidx_entry_s, map, idx); | |
2255 | if (map_sym->addr == map_key.addr) | |
2256 | { | |
2257 | if (start) | |
2258 | *start = map_sym->addr + obj_section_addr (sec); | |
2259 | return map_sym->entry; | |
2260 | } | |
2261 | } | |
2262 | ||
2263 | if (idx > 0) | |
2264 | { | |
2265 | map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1); | |
2266 | if (start) | |
2267 | *start = map_sym->addr + obj_section_addr (sec); | |
2268 | return map_sym->entry; | |
2269 | } | |
2270 | } | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | return NULL; | |
2275 | } | |
2276 | ||
2277 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2278 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2279 | return a prologue cache structure describing how to unwind this frame. | |
2280 | ||
2281 | Return NULL if the unwinding instruction list contains a "spare", | |
2282 | "reserved" or "refuse to unwind" instruction as defined in section | |
2283 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2284 | for the ARM Architecture" document. */ | |
2285 | ||
2286 | static struct arm_prologue_cache * | |
2287 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2288 | { | |
2289 | CORE_ADDR vsp = 0; | |
2290 | int vsp_valid = 0; | |
2291 | ||
2292 | struct arm_prologue_cache *cache; | |
2293 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2294 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2295 | ||
2296 | for (;;) | |
2297 | { | |
2298 | gdb_byte insn; | |
2299 | ||
2300 | /* Whenever we reload SP, we actually have to retrieve its | |
2301 | actual value in the current frame. */ | |
2302 | if (!vsp_valid) | |
2303 | { | |
2304 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2305 | { | |
2306 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2307 | vsp = get_frame_register_unsigned (this_frame, reg); | |
2308 | } | |
2309 | else | |
2310 | { | |
2311 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr; | |
2312 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); | |
2313 | } | |
2314 | ||
2315 | vsp_valid = 1; | |
2316 | } | |
2317 | ||
2318 | /* Decode next unwind instruction. */ | |
2319 | insn = *entry++; | |
2320 | ||
2321 | if ((insn & 0xc0) == 0) | |
2322 | { | |
2323 | int offset = insn & 0x3f; | |
2324 | vsp += (offset << 2) + 4; | |
2325 | } | |
2326 | else if ((insn & 0xc0) == 0x40) | |
2327 | { | |
2328 | int offset = insn & 0x3f; | |
2329 | vsp -= (offset << 2) + 4; | |
2330 | } | |
2331 | else if ((insn & 0xf0) == 0x80) | |
2332 | { | |
2333 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2334 | int i; | |
2335 | ||
2336 | /* The special case of an all-zero mask identifies | |
2337 | "Refuse to unwind". We return NULL to fall back | |
2338 | to the prologue analyzer. */ | |
2339 | if (mask == 0) | |
2340 | return NULL; | |
2341 | ||
2342 | /* Pop registers r4..r15 under mask. */ | |
2343 | for (i = 0; i < 12; i++) | |
2344 | if (mask & (1 << i)) | |
2345 | { | |
2346 | cache->saved_regs[4 + i].addr = vsp; | |
2347 | vsp += 4; | |
2348 | } | |
2349 | ||
2350 | /* Special-case popping SP -- we need to reload vsp. */ | |
2351 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2352 | vsp_valid = 0; | |
2353 | } | |
2354 | else if ((insn & 0xf0) == 0x90) | |
2355 | { | |
2356 | int reg = insn & 0xf; | |
2357 | ||
2358 | /* Reserved cases. */ | |
2359 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2360 | return NULL; | |
2361 | ||
2362 | /* Set SP from another register and mark VSP for reload. */ | |
2363 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2364 | vsp_valid = 0; | |
2365 | } | |
2366 | else if ((insn & 0xf0) == 0xa0) | |
2367 | { | |
2368 | int count = insn & 0x7; | |
2369 | int pop_lr = (insn & 0x8) != 0; | |
2370 | int i; | |
2371 | ||
2372 | /* Pop r4..r[4+count]. */ | |
2373 | for (i = 0; i <= count; i++) | |
2374 | { | |
2375 | cache->saved_regs[4 + i].addr = vsp; | |
2376 | vsp += 4; | |
2377 | } | |
2378 | ||
2379 | /* If indicated by flag, pop LR as well. */ | |
2380 | if (pop_lr) | |
2381 | { | |
2382 | cache->saved_regs[ARM_LR_REGNUM].addr = vsp; | |
2383 | vsp += 4; | |
2384 | } | |
2385 | } | |
2386 | else if (insn == 0xb0) | |
2387 | { | |
2388 | /* We could only have updated PC by popping into it; if so, it | |
2389 | will show up as address. Otherwise, copy LR into PC. */ | |
2390 | if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM)) | |
2391 | cache->saved_regs[ARM_PC_REGNUM] | |
2392 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2393 | ||
2394 | /* We're done. */ | |
2395 | break; | |
2396 | } | |
2397 | else if (insn == 0xb1) | |
2398 | { | |
2399 | int mask = *entry++; | |
2400 | int i; | |
2401 | ||
2402 | /* All-zero mask and mask >= 16 is "spare". */ | |
2403 | if (mask == 0 || mask >= 16) | |
2404 | return NULL; | |
2405 | ||
2406 | /* Pop r0..r3 under mask. */ | |
2407 | for (i = 0; i < 4; i++) | |
2408 | if (mask & (1 << i)) | |
2409 | { | |
2410 | cache->saved_regs[i].addr = vsp; | |
2411 | vsp += 4; | |
2412 | } | |
2413 | } | |
2414 | else if (insn == 0xb2) | |
2415 | { | |
2416 | ULONGEST offset = 0; | |
2417 | unsigned shift = 0; | |
2418 | ||
2419 | do | |
2420 | { | |
2421 | offset |= (*entry & 0x7f) << shift; | |
2422 | shift += 7; | |
2423 | } | |
2424 | while (*entry++ & 0x80); | |
2425 | ||
2426 | vsp += 0x204 + (offset << 2); | |
2427 | } | |
2428 | else if (insn == 0xb3) | |
2429 | { | |
2430 | int start = *entry >> 4; | |
2431 | int count = (*entry++) & 0xf; | |
2432 | int i; | |
2433 | ||
2434 | /* Only registers D0..D15 are valid here. */ | |
2435 | if (start + count >= 16) | |
2436 | return NULL; | |
2437 | ||
2438 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2439 | for (i = 0; i <= count; i++) | |
2440 | { | |
2441 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2442 | vsp += 8; | |
2443 | } | |
2444 | ||
2445 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2446 | vsp += 4; | |
2447 | } | |
2448 | else if ((insn & 0xf8) == 0xb8) | |
2449 | { | |
2450 | int count = insn & 0x7; | |
2451 | int i; | |
2452 | ||
2453 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2454 | for (i = 0; i <= count; i++) | |
2455 | { | |
2456 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2457 | vsp += 8; | |
2458 | } | |
2459 | ||
2460 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2461 | vsp += 4; | |
2462 | } | |
2463 | else if (insn == 0xc6) | |
2464 | { | |
2465 | int start = *entry >> 4; | |
2466 | int count = (*entry++) & 0xf; | |
2467 | int i; | |
2468 | ||
2469 | /* Only registers WR0..WR15 are valid. */ | |
2470 | if (start + count >= 16) | |
2471 | return NULL; | |
2472 | ||
2473 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2474 | for (i = 0; i <= count; i++) | |
2475 | { | |
2476 | cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp; | |
2477 | vsp += 8; | |
2478 | } | |
2479 | } | |
2480 | else if (insn == 0xc7) | |
2481 | { | |
2482 | int mask = *entry++; | |
2483 | int i; | |
2484 | ||
2485 | /* All-zero mask and mask >= 16 is "spare". */ | |
2486 | if (mask == 0 || mask >= 16) | |
2487 | return NULL; | |
2488 | ||
2489 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2490 | for (i = 0; i < 4; i++) | |
2491 | if (mask & (1 << i)) | |
2492 | { | |
2493 | cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp; | |
2494 | vsp += 4; | |
2495 | } | |
2496 | } | |
2497 | else if ((insn & 0xf8) == 0xc0) | |
2498 | { | |
2499 | int count = insn & 0x7; | |
2500 | int i; | |
2501 | ||
2502 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2503 | for (i = 0; i <= count; i++) | |
2504 | { | |
2505 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp; | |
2506 | vsp += 8; | |
2507 | } | |
2508 | } | |
2509 | else if (insn == 0xc8) | |
2510 | { | |
2511 | int start = *entry >> 4; | |
2512 | int count = (*entry++) & 0xf; | |
2513 | int i; | |
2514 | ||
2515 | /* Only registers D0..D31 are valid. */ | |
2516 | if (start + count >= 16) | |
2517 | return NULL; | |
2518 | ||
2519 | /* Pop VFP double-precision registers | |
2520 | D[16+start]..D[16+start+count]. */ | |
2521 | for (i = 0; i <= count; i++) | |
2522 | { | |
2523 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp; | |
2524 | vsp += 8; | |
2525 | } | |
2526 | } | |
2527 | else if (insn == 0xc9) | |
2528 | { | |
2529 | int start = *entry >> 4; | |
2530 | int count = (*entry++) & 0xf; | |
2531 | int i; | |
2532 | ||
2533 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2534 | for (i = 0; i <= count; i++) | |
2535 | { | |
2536 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2537 | vsp += 8; | |
2538 | } | |
2539 | } | |
2540 | else if ((insn & 0xf8) == 0xd0) | |
2541 | { | |
2542 | int count = insn & 0x7; | |
2543 | int i; | |
2544 | ||
2545 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2546 | for (i = 0; i <= count; i++) | |
2547 | { | |
2548 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2549 | vsp += 8; | |
2550 | } | |
2551 | } | |
2552 | else | |
2553 | { | |
2554 | /* Everything else is "spare". */ | |
2555 | return NULL; | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | /* If we restore SP from a register, assume this was the frame register. | |
2560 | Otherwise just fall back to SP as frame register. */ | |
2561 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2562 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2563 | else | |
2564 | cache->framereg = ARM_SP_REGNUM; | |
2565 | ||
2566 | /* Determine offset to previous frame. */ | |
2567 | cache->framesize | |
2568 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2569 | ||
2570 | /* We already got the previous SP. */ | |
2571 | cache->prev_sp = vsp; | |
2572 | ||
2573 | return cache; | |
2574 | } | |
2575 | ||
2576 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2577 | already computes a filled-in prologue cache, which is then used | |
2578 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2579 | routines also used for prologue-parsing based unwinding. */ | |
2580 | ||
2581 | static int | |
2582 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
2583 | struct frame_info *this_frame, | |
2584 | void **this_prologue_cache) | |
2585 | { | |
2586 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2587 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2588 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
2589 | struct arm_prologue_cache *cache; | |
2590 | gdb_byte *entry; | |
2591 | ||
2592 | /* See if we have an ARM exception table entry covering this address. */ | |
2593 | addr_in_block = get_frame_address_in_block (this_frame); | |
2594 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
2595 | if (!entry) | |
2596 | return 0; | |
2597 | ||
2598 | /* The ARM exception table does not describe unwind information | |
2599 | for arbitrary PC values, but is guaranteed to be correct only | |
2600 | at call sites. We have to decide here whether we want to use | |
2601 | ARM exception table information for this frame, or fall back | |
2602 | to using prologue parsing. (Note that if we have DWARF CFI, | |
2603 | this sniffer isn't even called -- CFI is always preferred.) | |
2604 | ||
2605 | Before we make this decision, however, we check whether we | |
2606 | actually have *symbol* information for the current frame. | |
2607 | If not, prologue parsing would not work anyway, so we might | |
2608 | as well use the exception table and hope for the best. */ | |
2609 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
2610 | { | |
2611 | int exc_valid = 0; | |
2612 | ||
2613 | /* If the next frame is "normal", we are at a call site in this | |
2614 | frame, so exception information is guaranteed to be valid. */ | |
2615 | if (get_next_frame (this_frame) | |
2616 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
2617 | exc_valid = 1; | |
2618 | ||
2619 | /* We also assume exception information is valid if we're currently | |
2620 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
2621 | ensure this, so that e.g. pthread cancellation works. */ |
2622 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 2623 | { |
d9311bfa | 2624 | LONGEST insn; |
416dc9c6 | 2625 | |
d9311bfa AT |
2626 | if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2, |
2627 | byte_order_for_code, &insn) | |
2628 | && (insn & 0xff00) == 0xdf00 /* svc */) | |
2629 | exc_valid = 1; | |
0e9e9abd | 2630 | } |
d9311bfa AT |
2631 | else |
2632 | { | |
2633 | LONGEST insn; | |
416dc9c6 | 2634 | |
d9311bfa AT |
2635 | if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4, |
2636 | byte_order_for_code, &insn) | |
2637 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) | |
2638 | exc_valid = 1; | |
2639 | } | |
2640 | ||
0e9e9abd UW |
2641 | /* Bail out if we don't know that exception information is valid. */ |
2642 | if (!exc_valid) | |
2643 | return 0; | |
2644 | ||
2645 | /* The ARM exception index does not mark the *end* of the region | |
2646 | covered by the entry, and some functions will not have any entry. | |
2647 | To correctly recognize the end of the covered region, the linker | |
2648 | should have inserted dummy records with a CANTUNWIND marker. | |
2649 | ||
2650 | Unfortunately, current versions of GNU ld do not reliably do | |
2651 | this, and thus we may have found an incorrect entry above. | |
2652 | As a (temporary) sanity check, we only use the entry if it | |
2653 | lies *within* the bounds of the function. Note that this check | |
2654 | might reject perfectly valid entries that just happen to cover | |
2655 | multiple functions; therefore this check ought to be removed | |
2656 | once the linker is fixed. */ | |
2657 | if (func_start > exidx_region) | |
2658 | return 0; | |
2659 | } | |
2660 | ||
2661 | /* Decode the list of unwinding instructions into a prologue cache. | |
2662 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
2663 | cache = arm_exidx_fill_cache (this_frame, entry); | |
2664 | if (!cache) | |
2665 | return 0; | |
2666 | ||
2667 | *this_prologue_cache = cache; | |
2668 | return 1; | |
2669 | } | |
2670 | ||
2671 | struct frame_unwind arm_exidx_unwind = { | |
2672 | NORMAL_FRAME, | |
8fbca658 | 2673 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
2674 | arm_prologue_this_id, |
2675 | arm_prologue_prev_register, | |
2676 | NULL, | |
2677 | arm_exidx_unwind_sniffer | |
2678 | }; | |
2679 | ||
80d8d390 YQ |
2680 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
2681 | trampoline, return the target PC. Otherwise return 0. | |
2682 | ||
2683 | void call0a (char c, short s, int i, long l) {} | |
2684 | ||
2685 | int main (void) | |
2686 | { | |
2687 | (*pointer_to_call0a) (c, s, i, l); | |
2688 | } | |
2689 | ||
2690 | Instead of calling a stub library function _call_via_xx (xx is | |
2691 | the register name), GCC may inline the trampoline in the object | |
2692 | file as below (register r2 has the address of call0a). | |
2693 | ||
2694 | .global main | |
2695 | .type main, %function | |
2696 | ... | |
2697 | bl .L1 | |
2698 | ... | |
2699 | .size main, .-main | |
2700 | ||
2701 | .L1: | |
2702 | bx r2 | |
2703 | ||
2704 | The trampoline 'bx r2' doesn't belong to main. */ | |
2705 | ||
2706 | static CORE_ADDR | |
2707 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
2708 | { | |
2709 | /* The heuristics of recognizing such trampoline is that FRAME is | |
2710 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
2711 | if (arm_frame_is_thumb (frame)) | |
2712 | { | |
2713 | gdb_byte buf[2]; | |
2714 | ||
2715 | if (target_read_memory (pc, buf, 2) == 0) | |
2716 | { | |
2717 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2718 | enum bfd_endian byte_order_for_code | |
2719 | = gdbarch_byte_order_for_code (gdbarch); | |
2720 | uint16_t insn | |
2721 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
2722 | ||
2723 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
2724 | { | |
2725 | CORE_ADDR dest | |
2726 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
2727 | ||
2728 | /* Clear the LSB so that gdb core sets step-resume | |
2729 | breakpoint at the right address. */ | |
2730 | return UNMAKE_THUMB_ADDR (dest); | |
2731 | } | |
2732 | } | |
2733 | } | |
2734 | ||
2735 | return 0; | |
2736 | } | |
2737 | ||
909cf6ea | 2738 | static struct arm_prologue_cache * |
a262aec2 | 2739 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 2740 | { |
909cf6ea | 2741 | struct arm_prologue_cache *cache; |
909cf6ea | 2742 | |
35d5d4ee | 2743 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 2744 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 2745 | |
a262aec2 | 2746 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
2747 | |
2748 | return cache; | |
2749 | } | |
2750 | ||
2751 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
2752 | ||
2753 | static void | |
a262aec2 | 2754 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
2755 | void **this_cache, |
2756 | struct frame_id *this_id) | |
2757 | { | |
2758 | struct arm_prologue_cache *cache; | |
2759 | ||
2760 | if (*this_cache == NULL) | |
a262aec2 | 2761 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 2762 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 2763 | |
a262aec2 | 2764 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
2765 | } |
2766 | ||
a262aec2 DJ |
2767 | static int |
2768 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
2769 | struct frame_info *this_frame, | |
2770 | void **this_prologue_cache) | |
909cf6ea | 2771 | { |
93d42b30 | 2772 | CORE_ADDR addr_in_block; |
948f8e3d | 2773 | gdb_byte dummy[4]; |
18d18ac8 YQ |
2774 | CORE_ADDR pc, start_addr; |
2775 | const char *name; | |
909cf6ea | 2776 | |
a262aec2 | 2777 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 2778 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 2779 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
2780 | /* We also use the stub winder if the target memory is unreadable |
2781 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
2782 | || target_read_memory (pc, dummy, 4) != 0) |
2783 | return 1; | |
2784 | ||
2785 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
2786 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 2787 | return 1; |
909cf6ea | 2788 | |
a262aec2 | 2789 | return 0; |
909cf6ea DJ |
2790 | } |
2791 | ||
a262aec2 DJ |
2792 | struct frame_unwind arm_stub_unwind = { |
2793 | NORMAL_FRAME, | |
8fbca658 | 2794 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
2795 | arm_stub_this_id, |
2796 | arm_prologue_prev_register, | |
2797 | NULL, | |
2798 | arm_stub_unwind_sniffer | |
2799 | }; | |
2800 | ||
2ae28aa9 YQ |
2801 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
2802 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
2803 | returned. */ | |
2804 | ||
2805 | static struct arm_prologue_cache * | |
2806 | arm_m_exception_cache (struct frame_info *this_frame) | |
2807 | { | |
2808 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2809 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2810 | struct arm_prologue_cache *cache; | |
2811 | CORE_ADDR unwound_sp; | |
2812 | LONGEST xpsr; | |
2813 | ||
2814 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2815 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2816 | ||
2817 | unwound_sp = get_frame_register_unsigned (this_frame, | |
2818 | ARM_SP_REGNUM); | |
2819 | ||
2820 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
2821 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
2822 | "B1.5.6 Exception entry behavior" in | |
2823 | "ARMv7-M Architecture Reference Manual". */ | |
2824 | cache->saved_regs[0].addr = unwound_sp; | |
2825 | cache->saved_regs[1].addr = unwound_sp + 4; | |
2826 | cache->saved_regs[2].addr = unwound_sp + 8; | |
2827 | cache->saved_regs[3].addr = unwound_sp + 12; | |
2828 | cache->saved_regs[12].addr = unwound_sp + 16; | |
2829 | cache->saved_regs[14].addr = unwound_sp + 20; | |
2830 | cache->saved_regs[15].addr = unwound_sp + 24; | |
2831 | cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28; | |
2832 | ||
2833 | /* If bit 9 of the saved xPSR is set, then there is a four-byte | |
2834 | aligner between the top of the 32-byte stack frame and the | |
2835 | previous context's stack pointer. */ | |
2836 | cache->prev_sp = unwound_sp + 32; | |
2837 | if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) | |
2838 | && (xpsr & (1 << 9)) != 0) | |
2839 | cache->prev_sp += 4; | |
2840 | ||
2841 | return cache; | |
2842 | } | |
2843 | ||
2844 | /* Implementation of function hook 'this_id' in | |
2845 | 'struct frame_uwnind'. */ | |
2846 | ||
2847 | static void | |
2848 | arm_m_exception_this_id (struct frame_info *this_frame, | |
2849 | void **this_cache, | |
2850 | struct frame_id *this_id) | |
2851 | { | |
2852 | struct arm_prologue_cache *cache; | |
2853 | ||
2854 | if (*this_cache == NULL) | |
2855 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 2856 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
2857 | |
2858 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
2859 | *this_id = frame_id_build (cache->prev_sp, | |
2860 | get_frame_pc (this_frame)); | |
2861 | } | |
2862 | ||
2863 | /* Implementation of function hook 'prev_register' in | |
2864 | 'struct frame_uwnind'. */ | |
2865 | ||
2866 | static struct value * | |
2867 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
2868 | void **this_cache, | |
2869 | int prev_regnum) | |
2870 | { | |
2871 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2872 | struct arm_prologue_cache *cache; | |
2873 | ||
2874 | if (*this_cache == NULL) | |
2875 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 2876 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
2877 | |
2878 | /* The value was already reconstructed into PREV_SP. */ | |
2879 | if (prev_regnum == ARM_SP_REGNUM) | |
2880 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
2881 | cache->prev_sp); | |
2882 | ||
2883 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
2884 | prev_regnum); | |
2885 | } | |
2886 | ||
2887 | /* Implementation of function hook 'sniffer' in | |
2888 | 'struct frame_uwnind'. */ | |
2889 | ||
2890 | static int | |
2891 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
2892 | struct frame_info *this_frame, | |
2893 | void **this_prologue_cache) | |
2894 | { | |
2895 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
2896 | ||
2897 | /* No need to check is_m; this sniffer is only registered for | |
2898 | M-profile architectures. */ | |
2899 | ||
2900 | /* Exception frames return to one of these magic PCs. Other values | |
2901 | are not defined as of v7-M. See details in "B1.5.8 Exception | |
2902 | return behavior" in "ARMv7-M Architecture Reference Manual". */ | |
2903 | if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9 | |
2904 | || this_pc == 0xfffffffd) | |
2905 | return 1; | |
2906 | ||
2907 | return 0; | |
2908 | } | |
2909 | ||
2910 | /* Frame unwinder for M-profile exceptions. */ | |
2911 | ||
2912 | struct frame_unwind arm_m_exception_unwind = | |
2913 | { | |
2914 | SIGTRAMP_FRAME, | |
2915 | default_frame_unwind_stop_reason, | |
2916 | arm_m_exception_this_id, | |
2917 | arm_m_exception_prev_register, | |
2918 | NULL, | |
2919 | arm_m_exception_unwind_sniffer | |
2920 | }; | |
2921 | ||
24de872b | 2922 | static CORE_ADDR |
a262aec2 | 2923 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
2924 | { |
2925 | struct arm_prologue_cache *cache; | |
2926 | ||
eb5492fa | 2927 | if (*this_cache == NULL) |
a262aec2 | 2928 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2929 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 2930 | |
4be43953 | 2931 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
2932 | } |
2933 | ||
eb5492fa DJ |
2934 | struct frame_base arm_normal_base = { |
2935 | &arm_prologue_unwind, | |
2936 | arm_normal_frame_base, | |
2937 | arm_normal_frame_base, | |
2938 | arm_normal_frame_base | |
2939 | }; | |
2940 | ||
a262aec2 | 2941 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
2942 | dummy frame. The frame ID's base needs to match the TOS value |
2943 | saved by save_dummy_frame_tos() and returned from | |
2944 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
2945 | breakpoint. */ | |
c906108c | 2946 | |
eb5492fa | 2947 | static struct frame_id |
a262aec2 | 2948 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 2949 | { |
0963b4bd MS |
2950 | return frame_id_build (get_frame_register_unsigned (this_frame, |
2951 | ARM_SP_REGNUM), | |
a262aec2 | 2952 | get_frame_pc (this_frame)); |
eb5492fa | 2953 | } |
c3b4394c | 2954 | |
eb5492fa DJ |
2955 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
2956 | be used to construct the previous frame's ID, after looking up the | |
2957 | containing function). */ | |
c3b4394c | 2958 | |
eb5492fa DJ |
2959 | static CORE_ADDR |
2960 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2961 | { | |
2962 | CORE_ADDR pc; | |
2963 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
24568a2c | 2964 | return arm_addr_bits_remove (gdbarch, pc); |
eb5492fa DJ |
2965 | } |
2966 | ||
2967 | static CORE_ADDR | |
2968 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2969 | { | |
2970 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
2971 | } |
2972 | ||
b39cc962 DJ |
2973 | static struct value * |
2974 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
2975 | int regnum) | |
2976 | { | |
24568a2c | 2977 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 | 2978 | CORE_ADDR lr, cpsr; |
9779414d | 2979 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
2980 | |
2981 | switch (regnum) | |
2982 | { | |
2983 | case ARM_PC_REGNUM: | |
2984 | /* The PC is normally copied from the return column, which | |
2985 | describes saves of LR. However, that version may have an | |
2986 | extra bit set to indicate Thumb state. The bit is not | |
2987 | part of the PC. */ | |
2988 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2989 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 2990 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
2991 | |
2992 | case ARM_PS_REGNUM: | |
2993 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 2994 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
2995 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
2996 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 2997 | cpsr |= t_bit; |
b39cc962 | 2998 | else |
9779414d | 2999 | cpsr &= ~t_bit; |
ca38c58e | 3000 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3001 | |
3002 | default: | |
3003 | internal_error (__FILE__, __LINE__, | |
3004 | _("Unexpected register %d"), regnum); | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | static void | |
3009 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3010 | struct dwarf2_frame_state_reg *reg, | |
3011 | struct frame_info *this_frame) | |
3012 | { | |
3013 | switch (regnum) | |
3014 | { | |
3015 | case ARM_PC_REGNUM: | |
3016 | case ARM_PS_REGNUM: | |
3017 | reg->how = DWARF2_FRAME_REG_FN; | |
3018 | reg->loc.fn = arm_dwarf2_prev_register; | |
3019 | break; | |
3020 | case ARM_SP_REGNUM: | |
3021 | reg->how = DWARF2_FRAME_REG_CFA; | |
3022 | break; | |
3023 | } | |
3024 | } | |
3025 | ||
c9cf6e20 | 3026 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3027 | |
3028 | static int | |
c9cf6e20 | 3029 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3030 | { |
3031 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3032 | unsigned int insn, insn2; | |
3033 | int found_return = 0, found_stack_adjust = 0; | |
3034 | CORE_ADDR func_start, func_end; | |
3035 | CORE_ADDR scan_pc; | |
3036 | gdb_byte buf[4]; | |
3037 | ||
3038 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3039 | return 0; | |
3040 | ||
3041 | /* The epilogue is a sequence of instructions along the following lines: | |
3042 | ||
3043 | - add stack frame size to SP or FP | |
3044 | - [if frame pointer used] restore SP from FP | |
3045 | - restore registers from SP [may include PC] | |
3046 | - a return-type instruction [if PC wasn't already restored] | |
3047 | ||
3048 | In a first pass, we scan forward from the current PC and verify the | |
3049 | instructions we find as compatible with this sequence, ending in a | |
3050 | return instruction. | |
3051 | ||
3052 | However, this is not sufficient to distinguish indirect function calls | |
3053 | within a function from indirect tail calls in the epilogue in some cases. | |
3054 | Therefore, if we didn't already find any SP-changing instruction during | |
3055 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3056 | are in the epilogue. */ | |
3057 | ||
3058 | scan_pc = pc; | |
3059 | while (scan_pc < func_end && !found_return) | |
3060 | { | |
3061 | if (target_read_memory (scan_pc, buf, 2)) | |
3062 | break; | |
3063 | ||
3064 | scan_pc += 2; | |
3065 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3066 | ||
3067 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3068 | found_return = 1; | |
3069 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3070 | found_return = 1; | |
540314bd | 3071 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3072 | { |
b7576e5c | 3073 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3074 | found_return = 1; |
3075 | } | |
db24da6d | 3076 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3077 | { |
3078 | if (target_read_memory (scan_pc, buf, 2)) | |
3079 | break; | |
3080 | ||
3081 | scan_pc += 2; | |
3082 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3083 | ||
3084 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3085 | { | |
4024ca99 UW |
3086 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3087 | found_return = 1; | |
3088 | } | |
3089 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3090 | && (insn2 & 0x0fff) == 0x0b04) | |
3091 | { | |
4024ca99 UW |
3092 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3093 | found_return = 1; | |
3094 | } | |
3095 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3096 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3097 | ; |
4024ca99 UW |
3098 | else |
3099 | break; | |
3100 | } | |
3101 | else | |
3102 | break; | |
3103 | } | |
3104 | ||
3105 | if (!found_return) | |
3106 | return 0; | |
3107 | ||
3108 | /* Since any instruction in the epilogue sequence, with the possible | |
3109 | exception of return itself, updates the stack pointer, we need to | |
3110 | scan backwards for at most one instruction. Try either a 16-bit or | |
3111 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3112 | too much about false positives. */ |
4024ca99 | 3113 | |
6b65d1b6 YQ |
3114 | if (pc - 4 < func_start) |
3115 | return 0; | |
3116 | if (target_read_memory (pc - 4, buf, 4)) | |
3117 | return 0; | |
4024ca99 | 3118 | |
6b65d1b6 YQ |
3119 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3120 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3121 | ||
3122 | if (thumb_instruction_restores_sp (insn2)) | |
3123 | found_stack_adjust = 1; | |
3124 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3125 | found_stack_adjust = 1; | |
3126 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3127 | && (insn2 & 0x0fff) == 0x0b04) | |
3128 | found_stack_adjust = 1; | |
3129 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3130 | && (insn2 & 0x0e00) == 0x0a00) | |
3131 | found_stack_adjust = 1; | |
4024ca99 UW |
3132 | |
3133 | return found_stack_adjust; | |
3134 | } | |
3135 | ||
c9cf6e20 | 3136 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3137 | |
3138 | static int | |
c9cf6e20 | 3139 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3140 | { |
3141 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3142 | unsigned int insn; | |
f303bc3e | 3143 | int found_return; |
4024ca99 UW |
3144 | CORE_ADDR func_start, func_end; |
3145 | ||
3146 | if (arm_pc_is_thumb (gdbarch, pc)) | |
c9cf6e20 | 3147 | return thumb_stack_frame_destroyed_p (gdbarch, pc); |
4024ca99 UW |
3148 | |
3149 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3150 | return 0; | |
3151 | ||
3152 | /* We are in the epilogue if the previous instruction was a stack | |
3153 | adjustment and the next instruction is a possible return (bx, mov | |
3154 | pc, or pop). We could have to scan backwards to find the stack | |
3155 | adjustment, or forwards to find the return, but this is a decent | |
3156 | approximation. First scan forwards. */ | |
3157 | ||
3158 | found_return = 0; | |
3159 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3160 | if (bits (insn, 28, 31) != INST_NV) | |
3161 | { | |
3162 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3163 | /* BX. */ | |
3164 | found_return = 1; | |
3165 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3166 | /* MOV PC. */ | |
3167 | found_return = 1; | |
3168 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3169 | && (insn & 0x0000c000) != 0) | |
3170 | /* POP (LDMIA), including PC or LR. */ | |
3171 | found_return = 1; | |
3172 | } | |
3173 | ||
3174 | if (!found_return) | |
3175 | return 0; | |
3176 | ||
3177 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3178 | false positives from mode changes. */ | |
3179 | ||
3180 | if (pc < func_start + 4) | |
3181 | return 0; | |
3182 | ||
3183 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3184 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3185 | return 1; |
3186 | ||
3187 | return 0; | |
3188 | } | |
3189 | ||
3190 | ||
2dd604e7 RE |
3191 | /* When arguments must be pushed onto the stack, they go on in reverse |
3192 | order. The code below implements a FILO (stack) to do this. */ | |
3193 | ||
3194 | struct stack_item | |
3195 | { | |
3196 | int len; | |
3197 | struct stack_item *prev; | |
7c543f7b | 3198 | gdb_byte *data; |
2dd604e7 RE |
3199 | }; |
3200 | ||
3201 | static struct stack_item * | |
df3b6708 | 3202 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2dd604e7 RE |
3203 | { |
3204 | struct stack_item *si; | |
8d749320 | 3205 | si = XNEW (struct stack_item); |
7c543f7b | 3206 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
3207 | si->len = len; |
3208 | si->prev = prev; | |
3209 | memcpy (si->data, contents, len); | |
3210 | return si; | |
3211 | } | |
3212 | ||
3213 | static struct stack_item * | |
3214 | pop_stack_item (struct stack_item *si) | |
3215 | { | |
3216 | struct stack_item *dead = si; | |
3217 | si = si->prev; | |
3218 | xfree (dead->data); | |
3219 | xfree (dead); | |
3220 | return si; | |
3221 | } | |
3222 | ||
2af48f68 PB |
3223 | |
3224 | /* Return the alignment (in bytes) of the given type. */ | |
3225 | ||
3226 | static int | |
3227 | arm_type_align (struct type *t) | |
3228 | { | |
3229 | int n; | |
3230 | int align; | |
3231 | int falign; | |
3232 | ||
3233 | t = check_typedef (t); | |
3234 | switch (TYPE_CODE (t)) | |
3235 | { | |
3236 | default: | |
3237 | /* Should never happen. */ | |
3238 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
3239 | return 4; | |
3240 | ||
3241 | case TYPE_CODE_PTR: | |
3242 | case TYPE_CODE_ENUM: | |
3243 | case TYPE_CODE_INT: | |
3244 | case TYPE_CODE_FLT: | |
3245 | case TYPE_CODE_SET: | |
3246 | case TYPE_CODE_RANGE: | |
2af48f68 PB |
3247 | case TYPE_CODE_REF: |
3248 | case TYPE_CODE_CHAR: | |
3249 | case TYPE_CODE_BOOL: | |
3250 | return TYPE_LENGTH (t); | |
3251 | ||
3252 | case TYPE_CODE_ARRAY: | |
c4312b19 YQ |
3253 | if (TYPE_VECTOR (t)) |
3254 | { | |
3255 | /* Use the natural alignment for vector types (the same for | |
3256 | scalar type), but the maximum alignment is 64-bit. */ | |
3257 | if (TYPE_LENGTH (t) > 8) | |
3258 | return 8; | |
3259 | else | |
3260 | return TYPE_LENGTH (t); | |
3261 | } | |
3262 | else | |
3263 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
2af48f68 | 3264 | case TYPE_CODE_COMPLEX: |
2af48f68 PB |
3265 | return arm_type_align (TYPE_TARGET_TYPE (t)); |
3266 | ||
3267 | case TYPE_CODE_STRUCT: | |
3268 | case TYPE_CODE_UNION: | |
3269 | align = 1; | |
3270 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
3271 | { | |
3272 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
3273 | if (falign > align) | |
3274 | align = falign; | |
3275 | } | |
3276 | return align; | |
3277 | } | |
3278 | } | |
3279 | ||
90445bd3 DJ |
3280 | /* Possible base types for a candidate for passing and returning in |
3281 | VFP registers. */ | |
3282 | ||
3283 | enum arm_vfp_cprc_base_type | |
3284 | { | |
3285 | VFP_CPRC_UNKNOWN, | |
3286 | VFP_CPRC_SINGLE, | |
3287 | VFP_CPRC_DOUBLE, | |
3288 | VFP_CPRC_VEC64, | |
3289 | VFP_CPRC_VEC128 | |
3290 | }; | |
3291 | ||
3292 | /* The length of one element of base type B. */ | |
3293 | ||
3294 | static unsigned | |
3295 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
3296 | { | |
3297 | switch (b) | |
3298 | { | |
3299 | case VFP_CPRC_SINGLE: | |
3300 | return 4; | |
3301 | case VFP_CPRC_DOUBLE: | |
3302 | return 8; | |
3303 | case VFP_CPRC_VEC64: | |
3304 | return 8; | |
3305 | case VFP_CPRC_VEC128: | |
3306 | return 16; | |
3307 | default: | |
3308 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3309 | (int) b); | |
3310 | } | |
3311 | } | |
3312 | ||
3313 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
3314 | for passing base type B. */ | |
3315 | ||
3316 | static int | |
3317 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
3318 | { | |
3319 | switch (b) | |
3320 | { | |
3321 | case VFP_CPRC_SINGLE: | |
3322 | return 's'; | |
3323 | case VFP_CPRC_DOUBLE: | |
3324 | return 'd'; | |
3325 | case VFP_CPRC_VEC64: | |
3326 | return 'd'; | |
3327 | case VFP_CPRC_VEC128: | |
3328 | return 'q'; | |
3329 | default: | |
3330 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3331 | (int) b); | |
3332 | } | |
3333 | } | |
3334 | ||
3335 | /* Determine whether T may be part of a candidate for passing and | |
3336 | returning in VFP registers, ignoring the limit on the total number | |
3337 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
3338 | classification of the first valid component found; if it is not | |
3339 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
3340 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
3341 | for passing and returning in VFP registers, a type differently | |
3342 | classified from *BASE_TYPE, or two types differently classified | |
3343 | from each other, return -1, otherwise return the total number of | |
3344 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
3345 | array). Vector types are not currently supported, matching the |
3346 | generic AAPCS support. */ | |
90445bd3 DJ |
3347 | |
3348 | static int | |
3349 | arm_vfp_cprc_sub_candidate (struct type *t, | |
3350 | enum arm_vfp_cprc_base_type *base_type) | |
3351 | { | |
3352 | t = check_typedef (t); | |
3353 | switch (TYPE_CODE (t)) | |
3354 | { | |
3355 | case TYPE_CODE_FLT: | |
3356 | switch (TYPE_LENGTH (t)) | |
3357 | { | |
3358 | case 4: | |
3359 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3360 | *base_type = VFP_CPRC_SINGLE; | |
3361 | else if (*base_type != VFP_CPRC_SINGLE) | |
3362 | return -1; | |
3363 | return 1; | |
3364 | ||
3365 | case 8: | |
3366 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3367 | *base_type = VFP_CPRC_DOUBLE; | |
3368 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3369 | return -1; | |
3370 | return 1; | |
3371 | ||
3372 | default: | |
3373 | return -1; | |
3374 | } | |
3375 | break; | |
3376 | ||
817e0957 YQ |
3377 | case TYPE_CODE_COMPLEX: |
3378 | /* Arguments of complex T where T is one of the types float or | |
3379 | double get treated as if they are implemented as: | |
3380 | ||
3381 | struct complexT | |
3382 | { | |
3383 | T real; | |
3384 | T imag; | |
5f52445b YQ |
3385 | }; |
3386 | ||
3387 | */ | |
817e0957 YQ |
3388 | switch (TYPE_LENGTH (t)) |
3389 | { | |
3390 | case 8: | |
3391 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3392 | *base_type = VFP_CPRC_SINGLE; | |
3393 | else if (*base_type != VFP_CPRC_SINGLE) | |
3394 | return -1; | |
3395 | return 2; | |
3396 | ||
3397 | case 16: | |
3398 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3399 | *base_type = VFP_CPRC_DOUBLE; | |
3400 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3401 | return -1; | |
3402 | return 2; | |
3403 | ||
3404 | default: | |
3405 | return -1; | |
3406 | } | |
3407 | break; | |
3408 | ||
90445bd3 DJ |
3409 | case TYPE_CODE_ARRAY: |
3410 | { | |
c4312b19 | 3411 | if (TYPE_VECTOR (t)) |
90445bd3 | 3412 | { |
c4312b19 YQ |
3413 | /* A 64-bit or 128-bit containerized vector type are VFP |
3414 | CPRCs. */ | |
3415 | switch (TYPE_LENGTH (t)) | |
3416 | { | |
3417 | case 8: | |
3418 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3419 | *base_type = VFP_CPRC_VEC64; | |
3420 | return 1; | |
3421 | case 16: | |
3422 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3423 | *base_type = VFP_CPRC_VEC128; | |
3424 | return 1; | |
3425 | default: | |
3426 | return -1; | |
3427 | } | |
3428 | } | |
3429 | else | |
3430 | { | |
3431 | int count; | |
3432 | unsigned unitlen; | |
3433 | ||
3434 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), | |
3435 | base_type); | |
3436 | if (count == -1) | |
3437 | return -1; | |
3438 | if (TYPE_LENGTH (t) == 0) | |
3439 | { | |
3440 | gdb_assert (count == 0); | |
3441 | return 0; | |
3442 | } | |
3443 | else if (count == 0) | |
3444 | return -1; | |
3445 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3446 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
3447 | return TYPE_LENGTH (t) / unitlen; | |
90445bd3 | 3448 | } |
90445bd3 DJ |
3449 | } |
3450 | break; | |
3451 | ||
3452 | case TYPE_CODE_STRUCT: | |
3453 | { | |
3454 | int count = 0; | |
3455 | unsigned unitlen; | |
3456 | int i; | |
3457 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
3458 | { | |
3459 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
3460 | base_type); | |
3461 | if (sub_count == -1) | |
3462 | return -1; | |
3463 | count += sub_count; | |
3464 | } | |
3465 | if (TYPE_LENGTH (t) == 0) | |
3466 | { | |
3467 | gdb_assert (count == 0); | |
3468 | return 0; | |
3469 | } | |
3470 | else if (count == 0) | |
3471 | return -1; | |
3472 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3473 | if (TYPE_LENGTH (t) != unitlen * count) | |
3474 | return -1; | |
3475 | return count; | |
3476 | } | |
3477 | ||
3478 | case TYPE_CODE_UNION: | |
3479 | { | |
3480 | int count = 0; | |
3481 | unsigned unitlen; | |
3482 | int i; | |
3483 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
3484 | { | |
3485 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
3486 | base_type); | |
3487 | if (sub_count == -1) | |
3488 | return -1; | |
3489 | count = (count > sub_count ? count : sub_count); | |
3490 | } | |
3491 | if (TYPE_LENGTH (t) == 0) | |
3492 | { | |
3493 | gdb_assert (count == 0); | |
3494 | return 0; | |
3495 | } | |
3496 | else if (count == 0) | |
3497 | return -1; | |
3498 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3499 | if (TYPE_LENGTH (t) != unitlen * count) | |
3500 | return -1; | |
3501 | return count; | |
3502 | } | |
3503 | ||
3504 | default: | |
3505 | break; | |
3506 | } | |
3507 | ||
3508 | return -1; | |
3509 | } | |
3510 | ||
3511 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
3512 | if passed to or returned from a non-variadic function with the VFP | |
3513 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
3514 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
3515 | elements of that base type before returning. */ | |
3516 | ||
3517 | static int | |
3518 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
3519 | int *count) | |
3520 | { | |
3521 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
3522 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
3523 | if (c <= 0 || c > 4) | |
3524 | return 0; | |
3525 | *base_type = b; | |
3526 | *count = c; | |
3527 | return 1; | |
3528 | } | |
3529 | ||
3530 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
3531 | returning values from a function of type FUNC_TYPE, 0 | |
3532 | otherwise. */ | |
3533 | ||
3534 | static int | |
3535 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
3536 | { | |
3537 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3538 | /* Variadic functions always use the base ABI. Assume that functions | |
3539 | without debug info are not variadic. */ | |
3540 | if (func_type && TYPE_VARARGS (check_typedef (func_type))) | |
3541 | return 0; | |
3542 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
3543 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
3544 | return 0; | |
3545 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
3546 | } | |
3547 | ||
3548 | /* We currently only support passing parameters in integer registers, which | |
3549 | conforms with GCC's default model, and VFP argument passing following | |
3550 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
3551 | we should probably support some of them based on the selected ABI. */ |
3552 | ||
3553 | static CORE_ADDR | |
7d9b040b | 3554 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
3555 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
3556 | struct value **args, CORE_ADDR sp, int struct_return, | |
3557 | CORE_ADDR struct_addr) | |
2dd604e7 | 3558 | { |
e17a4113 | 3559 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
3560 | int argnum; |
3561 | int argreg; | |
3562 | int nstack; | |
3563 | struct stack_item *si = NULL; | |
90445bd3 DJ |
3564 | int use_vfp_abi; |
3565 | struct type *ftype; | |
3566 | unsigned vfp_regs_free = (1 << 16) - 1; | |
3567 | ||
3568 | /* Determine the type of this function and whether the VFP ABI | |
3569 | applies. */ | |
3570 | ftype = check_typedef (value_type (function)); | |
3571 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) | |
3572 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); | |
3573 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 3574 | |
6a65450a AC |
3575 | /* Set the return address. For the ARM, the return breakpoint is |
3576 | always at BP_ADDR. */ | |
9779414d | 3577 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 3578 | bp_addr |= 1; |
6a65450a | 3579 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
3580 | |
3581 | /* Walk through the list of args and determine how large a temporary | |
3582 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 3583 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
3584 | nstack = 0; |
3585 | ||
3586 | argreg = ARM_A1_REGNUM; | |
3587 | nstack = 0; | |
3588 | ||
2dd604e7 RE |
3589 | /* The struct_return pointer occupies the first parameter |
3590 | passing register. */ | |
3591 | if (struct_return) | |
3592 | { | |
3593 | if (arm_debug) | |
5af949e3 | 3594 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 3595 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 3596 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
3597 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
3598 | argreg++; | |
3599 | } | |
3600 | ||
3601 | for (argnum = 0; argnum < nargs; argnum++) | |
3602 | { | |
3603 | int len; | |
3604 | struct type *arg_type; | |
3605 | struct type *target_type; | |
3606 | enum type_code typecode; | |
8c6363cf | 3607 | const bfd_byte *val; |
2af48f68 | 3608 | int align; |
90445bd3 DJ |
3609 | enum arm_vfp_cprc_base_type vfp_base_type; |
3610 | int vfp_base_count; | |
3611 | int may_use_core_reg = 1; | |
2dd604e7 | 3612 | |
df407dfe | 3613 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
3614 | len = TYPE_LENGTH (arg_type); |
3615 | target_type = TYPE_TARGET_TYPE (arg_type); | |
3616 | typecode = TYPE_CODE (arg_type); | |
8c6363cf | 3617 | val = value_contents (args[argnum]); |
2dd604e7 | 3618 | |
2af48f68 PB |
3619 | align = arm_type_align (arg_type); |
3620 | /* Round alignment up to a whole number of words. */ | |
3621 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
3622 | /* Different ABIs have different maximum alignments. */ | |
3623 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
3624 | { | |
3625 | /* The APCS ABI only requires word alignment. */ | |
3626 | align = INT_REGISTER_SIZE; | |
3627 | } | |
3628 | else | |
3629 | { | |
3630 | /* The AAPCS requires at most doubleword alignment. */ | |
3631 | if (align > INT_REGISTER_SIZE * 2) | |
3632 | align = INT_REGISTER_SIZE * 2; | |
3633 | } | |
3634 | ||
90445bd3 DJ |
3635 | if (use_vfp_abi |
3636 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
3637 | &vfp_base_count)) | |
3638 | { | |
3639 | int regno; | |
3640 | int unit_length; | |
3641 | int shift; | |
3642 | unsigned mask; | |
3643 | ||
3644 | /* Because this is a CPRC it cannot go in a core register or | |
3645 | cause a core register to be skipped for alignment. | |
3646 | Either it goes in VFP registers and the rest of this loop | |
3647 | iteration is skipped for this argument, or it goes on the | |
3648 | stack (and the stack alignment code is correct for this | |
3649 | case). */ | |
3650 | may_use_core_reg = 0; | |
3651 | ||
3652 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3653 | shift = unit_length / 4; | |
3654 | mask = (1 << (shift * vfp_base_count)) - 1; | |
3655 | for (regno = 0; regno < 16; regno += shift) | |
3656 | if (((vfp_regs_free >> regno) & mask) == mask) | |
3657 | break; | |
3658 | ||
3659 | if (regno < 16) | |
3660 | { | |
3661 | int reg_char; | |
3662 | int reg_scaled; | |
3663 | int i; | |
3664 | ||
3665 | vfp_regs_free &= ~(mask << regno); | |
3666 | reg_scaled = regno / shift; | |
3667 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3668 | for (i = 0; i < vfp_base_count; i++) | |
3669 | { | |
3670 | char name_buf[4]; | |
3671 | int regnum; | |
58d6951d DJ |
3672 | if (reg_char == 'q') |
3673 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 3674 | val + i * unit_length); |
58d6951d DJ |
3675 | else |
3676 | { | |
8c042590 PM |
3677 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
3678 | reg_char, reg_scaled + i); | |
58d6951d DJ |
3679 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
3680 | strlen (name_buf)); | |
3681 | regcache_cooked_write (regcache, regnum, | |
3682 | val + i * unit_length); | |
3683 | } | |
90445bd3 DJ |
3684 | } |
3685 | continue; | |
3686 | } | |
3687 | else | |
3688 | { | |
3689 | /* This CPRC could not go in VFP registers, so all VFP | |
3690 | registers are now marked as used. */ | |
3691 | vfp_regs_free = 0; | |
3692 | } | |
3693 | } | |
3694 | ||
2af48f68 PB |
3695 | /* Push stack padding for dowubleword alignment. */ |
3696 | if (nstack & (align - 1)) | |
3697 | { | |
3698 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
3699 | nstack += INT_REGISTER_SIZE; | |
3700 | } | |
3701 | ||
3702 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
3703 | if (may_use_core_reg |
3704 | && argreg <= ARM_LAST_ARG_REGNUM | |
2af48f68 PB |
3705 | && align > INT_REGISTER_SIZE |
3706 | && argreg & 1) | |
3707 | argreg++; | |
3708 | ||
2dd604e7 RE |
3709 | /* If the argument is a pointer to a function, and it is a |
3710 | Thumb function, create a LOCAL copy of the value and set | |
3711 | the THUMB bit in it. */ | |
3712 | if (TYPE_CODE_PTR == typecode | |
3713 | && target_type != NULL | |
f96b8fa0 | 3714 | && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type))) |
2dd604e7 | 3715 | { |
e17a4113 | 3716 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 3717 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 3718 | { |
224c3ddb | 3719 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 3720 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 3721 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 3722 | val = copy; |
2dd604e7 RE |
3723 | } |
3724 | } | |
3725 | ||
3726 | /* Copy the argument to general registers or the stack in | |
3727 | register-sized pieces. Large arguments are split between | |
3728 | registers and stack. */ | |
3729 | while (len > 0) | |
3730 | { | |
f0c9063c | 3731 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
ef9bd0b8 YQ |
3732 | CORE_ADDR regval |
3733 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 3734 | |
90445bd3 | 3735 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
3736 | { |
3737 | /* The argument is being passed in a general purpose | |
3738 | register. */ | |
e17a4113 | 3739 | if (byte_order == BFD_ENDIAN_BIG) |
8bf8793c | 3740 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
3741 | if (arm_debug) |
3742 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
3743 | argnum, |
3744 | gdbarch_register_name | |
2af46ca0 | 3745 | (gdbarch, argreg), |
f0c9063c | 3746 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
3747 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
3748 | argreg++; | |
3749 | } | |
3750 | else | |
3751 | { | |
ef9bd0b8 YQ |
3752 | gdb_byte buf[INT_REGISTER_SIZE]; |
3753 | ||
3754 | memset (buf, 0, sizeof (buf)); | |
3755 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
3756 | ||
2dd604e7 RE |
3757 | /* Push the arguments onto the stack. */ |
3758 | if (arm_debug) | |
3759 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
3760 | argnum, nstack); | |
ef9bd0b8 | 3761 | si = push_stack_item (si, buf, INT_REGISTER_SIZE); |
f0c9063c | 3762 | nstack += INT_REGISTER_SIZE; |
2dd604e7 RE |
3763 | } |
3764 | ||
3765 | len -= partial_len; | |
3766 | val += partial_len; | |
3767 | } | |
3768 | } | |
3769 | /* If we have an odd number of words to push, then decrement the stack | |
3770 | by one word now, so first stack argument will be dword aligned. */ | |
3771 | if (nstack & 4) | |
3772 | sp -= 4; | |
3773 | ||
3774 | while (si) | |
3775 | { | |
3776 | sp -= si->len; | |
3777 | write_memory (sp, si->data, si->len); | |
3778 | si = pop_stack_item (si); | |
3779 | } | |
3780 | ||
3781 | /* Finally, update teh SP register. */ | |
3782 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
3783 | ||
3784 | return sp; | |
3785 | } | |
3786 | ||
f53f0d0b PB |
3787 | |
3788 | /* Always align the frame to an 8-byte boundary. This is required on | |
3789 | some platforms and harmless on the rest. */ | |
3790 | ||
3791 | static CORE_ADDR | |
3792 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
3793 | { | |
3794 | /* Align the stack to eight bytes. */ | |
3795 | return sp & ~ (CORE_ADDR) 7; | |
3796 | } | |
3797 | ||
c906108c | 3798 | static void |
12b27276 | 3799 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 3800 | { |
c5aa993b | 3801 | if (flags & (1 << 0)) |
12b27276 | 3802 | fputs_filtered ("IVO ", file); |
c5aa993b | 3803 | if (flags & (1 << 1)) |
12b27276 | 3804 | fputs_filtered ("DVZ ", file); |
c5aa993b | 3805 | if (flags & (1 << 2)) |
12b27276 | 3806 | fputs_filtered ("OFL ", file); |
c5aa993b | 3807 | if (flags & (1 << 3)) |
12b27276 | 3808 | fputs_filtered ("UFL ", file); |
c5aa993b | 3809 | if (flags & (1 << 4)) |
12b27276 WN |
3810 | fputs_filtered ("INX ", file); |
3811 | fputc_filtered ('\n', file); | |
c906108c SS |
3812 | } |
3813 | ||
5e74b15c RE |
3814 | /* Print interesting information about the floating point processor |
3815 | (if present) or emulator. */ | |
34e8f22d | 3816 | static void |
d855c300 | 3817 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 3818 | struct frame_info *frame, const char *args) |
c906108c | 3819 | { |
9c9acae0 | 3820 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
3821 | int type; |
3822 | ||
3823 | type = (status >> 24) & 127; | |
edefbb7c | 3824 | if (status & (1 << 31)) |
12b27276 | 3825 | fprintf_filtered (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 3826 | else |
12b27276 | 3827 | fprintf_filtered (file, _("Software FPU type %d\n"), type); |
edefbb7c | 3828 | /* i18n: [floating point unit] mask */ |
12b27276 WN |
3829 | fputs_filtered (_("mask: "), file); |
3830 | print_fpu_flags (file, status >> 16); | |
edefbb7c | 3831 | /* i18n: [floating point unit] flags */ |
12b27276 WN |
3832 | fputs_filtered (_("flags: "), file); |
3833 | print_fpu_flags (file, status); | |
c906108c SS |
3834 | } |
3835 | ||
27067745 UW |
3836 | /* Construct the ARM extended floating point type. */ |
3837 | static struct type * | |
3838 | arm_ext_type (struct gdbarch *gdbarch) | |
3839 | { | |
3840 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3841 | ||
3842 | if (!tdep->arm_ext_type) | |
3843 | tdep->arm_ext_type | |
e9bb382b | 3844 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
3845 | floatformats_arm_ext); |
3846 | ||
3847 | return tdep->arm_ext_type; | |
3848 | } | |
3849 | ||
58d6951d DJ |
3850 | static struct type * |
3851 | arm_neon_double_type (struct gdbarch *gdbarch) | |
3852 | { | |
3853 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3854 | ||
3855 | if (tdep->neon_double_type == NULL) | |
3856 | { | |
3857 | struct type *t, *elem; | |
3858 | ||
3859 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
3860 | TYPE_CODE_UNION); | |
3861 | elem = builtin_type (gdbarch)->builtin_uint8; | |
3862 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
3863 | elem = builtin_type (gdbarch)->builtin_uint16; | |
3864 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
3865 | elem = builtin_type (gdbarch)->builtin_uint32; | |
3866 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
3867 | elem = builtin_type (gdbarch)->builtin_uint64; | |
3868 | append_composite_type_field (t, "u64", elem); | |
3869 | elem = builtin_type (gdbarch)->builtin_float; | |
3870 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
3871 | elem = builtin_type (gdbarch)->builtin_double; | |
3872 | append_composite_type_field (t, "f64", elem); | |
3873 | ||
3874 | TYPE_VECTOR (t) = 1; | |
3875 | TYPE_NAME (t) = "neon_d"; | |
3876 | tdep->neon_double_type = t; | |
3877 | } | |
3878 | ||
3879 | return tdep->neon_double_type; | |
3880 | } | |
3881 | ||
3882 | /* FIXME: The vector types are not correctly ordered on big-endian | |
3883 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
3884 | bits of d0 - regardless of what unit size is being held in d0. So | |
3885 | the offset of the first uint8 in d0 is 7, but the offset of the | |
3886 | first float is 4. This code works as-is for little-endian | |
3887 | targets. */ | |
3888 | ||
3889 | static struct type * | |
3890 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
3891 | { | |
3892 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3893 | ||
3894 | if (tdep->neon_quad_type == NULL) | |
3895 | { | |
3896 | struct type *t, *elem; | |
3897 | ||
3898 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
3899 | TYPE_CODE_UNION); | |
3900 | elem = builtin_type (gdbarch)->builtin_uint8; | |
3901 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
3902 | elem = builtin_type (gdbarch)->builtin_uint16; | |
3903 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
3904 | elem = builtin_type (gdbarch)->builtin_uint32; | |
3905 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
3906 | elem = builtin_type (gdbarch)->builtin_uint64; | |
3907 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
3908 | elem = builtin_type (gdbarch)->builtin_float; | |
3909 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
3910 | elem = builtin_type (gdbarch)->builtin_double; | |
3911 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
3912 | ||
3913 | TYPE_VECTOR (t) = 1; | |
3914 | TYPE_NAME (t) = "neon_q"; | |
3915 | tdep->neon_quad_type = t; | |
3916 | } | |
3917 | ||
3918 | return tdep->neon_quad_type; | |
3919 | } | |
3920 | ||
34e8f22d RE |
3921 | /* Return the GDB type object for the "standard" data type of data in |
3922 | register N. */ | |
3923 | ||
3924 | static struct type * | |
7a5ea0d4 | 3925 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 3926 | { |
58d6951d DJ |
3927 | int num_regs = gdbarch_num_regs (gdbarch); |
3928 | ||
3929 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
3930 | && regnum >= num_regs && regnum < num_regs + 32) | |
3931 | return builtin_type (gdbarch)->builtin_float; | |
3932 | ||
3933 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
3934 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
3935 | return arm_neon_quad_type (gdbarch); | |
3936 | ||
3937 | /* If the target description has register information, we are only | |
3938 | in this function so that we can override the types of | |
3939 | double-precision registers for NEON. */ | |
3940 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
3941 | { | |
3942 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
3943 | ||
3944 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
3945 | && TYPE_CODE (t) == TYPE_CODE_FLT | |
3946 | && gdbarch_tdep (gdbarch)->have_neon) | |
3947 | return arm_neon_double_type (gdbarch); | |
3948 | else | |
3949 | return t; | |
3950 | } | |
3951 | ||
34e8f22d | 3952 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
3953 | { |
3954 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
3955 | return builtin_type (gdbarch)->builtin_void; | |
3956 | ||
3957 | return arm_ext_type (gdbarch); | |
3958 | } | |
e4c16157 | 3959 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 3960 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 3961 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 3962 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
3963 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
3964 | /* These registers are only supported on targets which supply | |
3965 | an XML description. */ | |
df4df182 | 3966 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 3967 | else |
df4df182 | 3968 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
3969 | } |
3970 | ||
ff6f572f DJ |
3971 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
3972 | number. */ | |
3973 | ||
3974 | static int | |
d3f73121 | 3975 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
3976 | { |
3977 | /* Core integer regs. */ | |
3978 | if (reg >= 0 && reg <= 15) | |
3979 | return reg; | |
3980 | ||
3981 | /* Legacy FPA encoding. These were once used in a way which | |
3982 | overlapped with VFP register numbering, so their use is | |
3983 | discouraged, but GDB doesn't support the ARM toolchain | |
3984 | which used them for VFP. */ | |
3985 | if (reg >= 16 && reg <= 23) | |
3986 | return ARM_F0_REGNUM + reg - 16; | |
3987 | ||
3988 | /* New assignments for the FPA registers. */ | |
3989 | if (reg >= 96 && reg <= 103) | |
3990 | return ARM_F0_REGNUM + reg - 96; | |
3991 | ||
3992 | /* WMMX register assignments. */ | |
3993 | if (reg >= 104 && reg <= 111) | |
3994 | return ARM_WCGR0_REGNUM + reg - 104; | |
3995 | ||
3996 | if (reg >= 112 && reg <= 127) | |
3997 | return ARM_WR0_REGNUM + reg - 112; | |
3998 | ||
3999 | if (reg >= 192 && reg <= 199) | |
4000 | return ARM_WC0_REGNUM + reg - 192; | |
4001 | ||
58d6951d DJ |
4002 | /* VFP v2 registers. A double precision value is actually |
4003 | in d1 rather than s2, but the ABI only defines numbering | |
4004 | for the single precision registers. This will "just work" | |
4005 | in GDB for little endian targets (we'll read eight bytes, | |
4006 | starting in s0 and then progressing to s1), but will be | |
4007 | reversed on big endian targets with VFP. This won't | |
4008 | be a problem for the new Neon quad registers; you're supposed | |
4009 | to use DW_OP_piece for those. */ | |
4010 | if (reg >= 64 && reg <= 95) | |
4011 | { | |
4012 | char name_buf[4]; | |
4013 | ||
8c042590 | 4014 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4015 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4016 | strlen (name_buf)); | |
4017 | } | |
4018 | ||
4019 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4020 | registers, except that it now describes d0 instead of s0. */ | |
4021 | if (reg >= 256 && reg <= 287) | |
4022 | { | |
4023 | char name_buf[4]; | |
4024 | ||
8c042590 | 4025 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4026 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4027 | strlen (name_buf)); | |
4028 | } | |
4029 | ||
ff6f572f DJ |
4030 | return -1; |
4031 | } | |
4032 | ||
26216b98 AC |
4033 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4034 | static int | |
e7faf938 | 4035 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4036 | { |
4037 | int reg = regnum; | |
e7faf938 | 4038 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4039 | |
ff6f572f DJ |
4040 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4041 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4042 | ||
4043 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4044 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4045 | ||
4046 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4047 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4048 | ||
26216b98 AC |
4049 | if (reg < NUM_GREGS) |
4050 | return SIM_ARM_R0_REGNUM + reg; | |
4051 | reg -= NUM_GREGS; | |
4052 | ||
4053 | if (reg < NUM_FREGS) | |
4054 | return SIM_ARM_FP0_REGNUM + reg; | |
4055 | reg -= NUM_FREGS; | |
4056 | ||
4057 | if (reg < NUM_SREGS) | |
4058 | return SIM_ARM_FPS_REGNUM + reg; | |
4059 | reg -= NUM_SREGS; | |
4060 | ||
edefbb7c | 4061 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4062 | } |
34e8f22d | 4063 | |
a37b3cc0 AC |
4064 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
4065 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
4066 | It is thought that this is is the floating-point register format on | |
4067 | little-endian systems. */ | |
c906108c | 4068 | |
ed9a39eb | 4069 | static void |
b508a996 | 4070 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 4071 | void *dbl, int endianess) |
c906108c | 4072 | { |
a37b3cc0 | 4073 | DOUBLEST d; |
be8626e0 MD |
4074 | |
4075 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
4076 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
4077 | else | |
4078 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
4079 | ptr, &d); | |
b508a996 | 4080 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
4081 | } |
4082 | ||
34e8f22d | 4083 | static void |
be8626e0 MD |
4084 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
4085 | int endianess) | |
c906108c | 4086 | { |
a37b3cc0 | 4087 | DOUBLEST d; |
be8626e0 | 4088 | |
b508a996 | 4089 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 4090 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
4091 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
4092 | else | |
4093 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
4094 | &d, dbl); | |
c906108c | 4095 | } |
ed9a39eb | 4096 | |
d9311bfa AT |
4097 | /* Like insert_single_step_breakpoint, but make sure we use a breakpoint |
4098 | of the appropriate mode (as encoded in the PC value), even if this | |
4099 | differs from what would be expected according to the symbol tables. */ | |
4100 | ||
4101 | void | |
4102 | arm_insert_single_step_breakpoint (struct gdbarch *gdbarch, | |
4103 | struct address_space *aspace, | |
4104 | CORE_ADDR pc) | |
c906108c | 4105 | { |
d9311bfa AT |
4106 | struct cleanup *old_chain |
4107 | = make_cleanup_restore_integer (&arm_override_mode); | |
c5aa993b | 4108 | |
d9311bfa AT |
4109 | arm_override_mode = IS_THUMB_ADDR (pc); |
4110 | pc = gdbarch_addr_bits_remove (gdbarch, pc); | |
c5aa993b | 4111 | |
d9311bfa | 4112 | insert_single_step_breakpoint (gdbarch, aspace, pc); |
c906108c | 4113 | |
d9311bfa AT |
4114 | do_cleanups (old_chain); |
4115 | } | |
c5aa993b | 4116 | |
d9311bfa AT |
4117 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
4118 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
4119 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 4120 | |
d9311bfa AT |
4121 | static gdb_byte * |
4122 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
4123 | int old_len, int new_len) | |
4124 | { | |
4125 | gdb_byte *new_buf; | |
4126 | int bytes_to_read = new_len - old_len; | |
c906108c | 4127 | |
d9311bfa AT |
4128 | new_buf = (gdb_byte *) xmalloc (new_len); |
4129 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
4130 | xfree (buf); | |
4131 | if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0) | |
4132 | { | |
4133 | xfree (new_buf); | |
4134 | return NULL; | |
c906108c | 4135 | } |
d9311bfa | 4136 | return new_buf; |
c906108c SS |
4137 | } |
4138 | ||
d9311bfa AT |
4139 | /* An IT block is at most the 2-byte IT instruction followed by |
4140 | four 4-byte instructions. The furthest back we must search to | |
4141 | find an IT block that affects the current instruction is thus | |
4142 | 2 + 3 * 4 == 14 bytes. */ | |
4143 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 4144 | |
d9311bfa AT |
4145 | /* Use a quick scan if there are more than this many bytes of |
4146 | code. */ | |
4147 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 4148 | |
d9311bfa AT |
4149 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
4150 | A breakpoint in an IT block may not be hit, depending on the | |
4151 | condition flags. */ | |
ad527d2e | 4152 | static CORE_ADDR |
d9311bfa | 4153 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 4154 | { |
d9311bfa AT |
4155 | gdb_byte *buf; |
4156 | char map_type; | |
4157 | CORE_ADDR boundary, func_start; | |
4158 | int buf_len; | |
4159 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
4160 | int i, any, last_it, last_it_count; | |
177321bd | 4161 | |
d9311bfa AT |
4162 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
4163 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) | |
4164 | return bpaddr; | |
177321bd | 4165 | |
d9311bfa AT |
4166 | /* ARM mode does not have this problem. */ |
4167 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
4168 | return bpaddr; | |
177321bd | 4169 | |
d9311bfa AT |
4170 | /* We are setting a breakpoint in Thumb code that could potentially |
4171 | contain an IT block. The first step is to find how much Thumb | |
4172 | code there is; we do not need to read outside of known Thumb | |
4173 | sequences. */ | |
4174 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
4175 | if (map_type == 0) | |
4176 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
4177 | return bpaddr; | |
9dca5578 | 4178 | |
d9311bfa | 4179 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 4180 | |
d9311bfa AT |
4181 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
4182 | && func_start > boundary) | |
4183 | boundary = func_start; | |
9dca5578 | 4184 | |
d9311bfa AT |
4185 | /* Search for a candidate IT instruction. We have to do some fancy |
4186 | footwork to distinguish a real IT instruction from the second | |
4187 | half of a 32-bit instruction, but there is no need for that if | |
4188 | there's no candidate. */ | |
4189 | buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX); | |
4190 | if (buf_len == 0) | |
4191 | /* No room for an IT instruction. */ | |
4192 | return bpaddr; | |
c906108c | 4193 | |
d9311bfa AT |
4194 | buf = (gdb_byte *) xmalloc (buf_len); |
4195 | if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0) | |
4196 | return bpaddr; | |
4197 | any = 0; | |
4198 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 4199 | { |
d9311bfa AT |
4200 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
4201 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 4202 | { |
d9311bfa AT |
4203 | any = 1; |
4204 | break; | |
25b41d01 | 4205 | } |
c906108c | 4206 | } |
d9311bfa AT |
4207 | |
4208 | if (any == 0) | |
c906108c | 4209 | { |
d9311bfa AT |
4210 | xfree (buf); |
4211 | return bpaddr; | |
f9d67f43 DJ |
4212 | } |
4213 | ||
4214 | /* OK, the code bytes before this instruction contain at least one | |
4215 | halfword which resembles an IT instruction. We know that it's | |
4216 | Thumb code, but there are still two possibilities. Either the | |
4217 | halfword really is an IT instruction, or it is the second half of | |
4218 | a 32-bit Thumb instruction. The only way we can tell is to | |
4219 | scan forwards from a known instruction boundary. */ | |
4220 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
4221 | { | |
4222 | int definite; | |
4223 | ||
4224 | /* There's a lot of code before this instruction. Start with an | |
4225 | optimistic search; it's easy to recognize halfwords that can | |
4226 | not be the start of a 32-bit instruction, and use that to | |
4227 | lock on to the instruction boundaries. */ | |
4228 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
4229 | if (buf == NULL) | |
4230 | return bpaddr; | |
4231 | buf_len = IT_SCAN_THRESHOLD; | |
4232 | ||
4233 | definite = 0; | |
4234 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
4235 | { | |
4236 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4237 | if (thumb_insn_size (inst1) == 2) | |
4238 | { | |
4239 | definite = 1; | |
4240 | break; | |
4241 | } | |
4242 | } | |
4243 | ||
4244 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
4245 | are sure that we know the instruction boundaries, and it is far | |
4246 | enough from BPADDR that we could not miss an IT instruction | |
4247 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
4248 | known boundary. */ | |
4249 | if (! definite) | |
4250 | { | |
0963b4bd MS |
4251 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
4252 | bpaddr - boundary); | |
f9d67f43 DJ |
4253 | if (buf == NULL) |
4254 | return bpaddr; | |
4255 | buf_len = bpaddr - boundary; | |
4256 | i = 0; | |
4257 | } | |
4258 | } | |
4259 | else | |
4260 | { | |
4261 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
4262 | if (buf == NULL) | |
4263 | return bpaddr; | |
4264 | buf_len = bpaddr - boundary; | |
4265 | i = 0; | |
4266 | } | |
4267 | ||
4268 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
4269 | last_it = -1; | |
4270 | last_it_count = 0; | |
4271 | while (i < buf_len) | |
4272 | { | |
4273 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4274 | last_it_count--; | |
4275 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
4276 | { | |
4277 | last_it = i; | |
4278 | if (inst1 & 0x0001) | |
4279 | last_it_count = 4; | |
4280 | else if (inst1 & 0x0002) | |
4281 | last_it_count = 3; | |
4282 | else if (inst1 & 0x0004) | |
4283 | last_it_count = 2; | |
4284 | else | |
4285 | last_it_count = 1; | |
4286 | } | |
4287 | i += thumb_insn_size (inst1); | |
4288 | } | |
4289 | ||
4290 | xfree (buf); | |
4291 | ||
4292 | if (last_it == -1) | |
4293 | /* There wasn't really an IT instruction after all. */ | |
4294 | return bpaddr; | |
4295 | ||
4296 | if (last_it_count < 1) | |
4297 | /* It was too far away. */ | |
4298 | return bpaddr; | |
4299 | ||
4300 | /* This really is a trouble spot. Move the breakpoint to the IT | |
4301 | instruction. */ | |
4302 | return bpaddr - buf_len + last_it; | |
4303 | } | |
4304 | ||
cca44b1b | 4305 | /* ARM displaced stepping support. |
c906108c | 4306 | |
cca44b1b | 4307 | Generally ARM displaced stepping works as follows: |
c906108c | 4308 | |
cca44b1b JB |
4309 | 1. When an instruction is to be single-stepped, it is first decoded by |
4310 | arm_process_displaced_insn (called from arm_displaced_step_copy_insn). | |
4311 | Depending on the type of instruction, it is then copied to a scratch | |
4312 | location, possibly in a modified form. The copy_* set of functions | |
0963b4bd | 4313 | performs such modification, as necessary. A breakpoint is placed after |
cca44b1b JB |
4314 | the modified instruction in the scratch space to return control to GDB. |
4315 | Note in particular that instructions which modify the PC will no longer | |
4316 | do so after modification. | |
c5aa993b | 4317 | |
cca44b1b JB |
4318 | 2. The instruction is single-stepped, by setting the PC to the scratch |
4319 | location address, and resuming. Control returns to GDB when the | |
4320 | breakpoint is hit. | |
c5aa993b | 4321 | |
cca44b1b JB |
4322 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
4323 | function used for the current instruction. This function's job is to | |
4324 | put the CPU/memory state back to what it would have been if the | |
4325 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 4326 | |
cca44b1b JB |
4327 | /* NOP instruction (mov r0, r0). */ |
4328 | #define ARM_NOP 0xe1a00000 | |
34518530 | 4329 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
4330 | |
4331 | /* Helper for register reads for displaced stepping. In particular, this | |
4332 | returns the PC as it would be seen by the instruction at its original | |
4333 | location. */ | |
4334 | ||
4335 | ULONGEST | |
36073a92 YQ |
4336 | displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, |
4337 | int regno) | |
cca44b1b JB |
4338 | { |
4339 | ULONGEST ret; | |
36073a92 | 4340 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 4341 | |
bf9f652a | 4342 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 4343 | { |
4db71c0b YQ |
4344 | /* Compute pipeline offset: |
4345 | - When executing an ARM instruction, PC reads as the address of the | |
4346 | current instruction plus 8. | |
4347 | - When executing a Thumb instruction, PC reads as the address of the | |
4348 | current instruction plus 4. */ | |
4349 | ||
36073a92 | 4350 | if (!dsc->is_thumb) |
4db71c0b YQ |
4351 | from += 8; |
4352 | else | |
4353 | from += 4; | |
4354 | ||
cca44b1b JB |
4355 | if (debug_displaced) |
4356 | fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", | |
4db71c0b YQ |
4357 | (unsigned long) from); |
4358 | return (ULONGEST) from; | |
cca44b1b | 4359 | } |
c906108c | 4360 | else |
cca44b1b JB |
4361 | { |
4362 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
4363 | if (debug_displaced) | |
4364 | fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", | |
4365 | regno, (unsigned long) ret); | |
4366 | return ret; | |
4367 | } | |
c906108c SS |
4368 | } |
4369 | ||
cca44b1b JB |
4370 | static int |
4371 | displaced_in_arm_mode (struct regcache *regs) | |
4372 | { | |
4373 | ULONGEST ps; | |
9779414d | 4374 | ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); |
66e810cd | 4375 | |
cca44b1b | 4376 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 4377 | |
9779414d | 4378 | return (ps & t_bit) == 0; |
cca44b1b | 4379 | } |
66e810cd | 4380 | |
cca44b1b | 4381 | /* Write to the PC as from a branch instruction. */ |
c906108c | 4382 | |
cca44b1b | 4383 | static void |
36073a92 YQ |
4384 | branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
4385 | ULONGEST val) | |
c906108c | 4386 | { |
36073a92 | 4387 | if (!dsc->is_thumb) |
cca44b1b JB |
4388 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
4389 | architecture versions < 6. */ | |
0963b4bd MS |
4390 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4391 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 4392 | else |
0963b4bd MS |
4393 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4394 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 4395 | } |
66e810cd | 4396 | |
cca44b1b JB |
4397 | /* Write to the PC as from a branch-exchange instruction. */ |
4398 | ||
4399 | static void | |
4400 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
4401 | { | |
4402 | ULONGEST ps; | |
9779414d | 4403 | ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); |
cca44b1b JB |
4404 | |
4405 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
4406 | ||
4407 | if ((val & 1) == 1) | |
c906108c | 4408 | { |
9779414d | 4409 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
4410 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
4411 | } | |
4412 | else if ((val & 2) == 0) | |
4413 | { | |
9779414d | 4414 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4415 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
4416 | } |
4417 | else | |
4418 | { | |
cca44b1b JB |
4419 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
4420 | mode, align dest to 4 bytes). */ | |
4421 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 4422 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4423 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
4424 | } |
4425 | } | |
ed9a39eb | 4426 | |
cca44b1b | 4427 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 4428 | |
34e8f22d | 4429 | static void |
36073a92 YQ |
4430 | load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
4431 | ULONGEST val) | |
ed9a39eb | 4432 | { |
cca44b1b JB |
4433 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
4434 | bx_write_pc (regs, val); | |
4435 | else | |
36073a92 | 4436 | branch_write_pc (regs, dsc, val); |
cca44b1b | 4437 | } |
be8626e0 | 4438 | |
cca44b1b JB |
4439 | /* Write to the PC as if from an ALU instruction. */ |
4440 | ||
4441 | static void | |
36073a92 YQ |
4442 | alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
4443 | ULONGEST val) | |
cca44b1b | 4444 | { |
36073a92 | 4445 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
4446 | bx_write_pc (regs, val); |
4447 | else | |
36073a92 | 4448 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
4449 | } |
4450 | ||
4451 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
4452 | has a varying effects depending on the instruction which does the write: | |
4453 | this is controlled by the WRITE_PC argument. */ | |
4454 | ||
4455 | void | |
4456 | displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, | |
4457 | int regno, ULONGEST val, enum pc_write_style write_pc) | |
4458 | { | |
bf9f652a | 4459 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 4460 | { |
cca44b1b JB |
4461 | if (debug_displaced) |
4462 | fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", | |
4463 | (unsigned long) val); | |
4464 | switch (write_pc) | |
08216dd7 | 4465 | { |
cca44b1b | 4466 | case BRANCH_WRITE_PC: |
36073a92 | 4467 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
4468 | break; |
4469 | ||
cca44b1b JB |
4470 | case BX_WRITE_PC: |
4471 | bx_write_pc (regs, val); | |
4472 | break; | |
4473 | ||
4474 | case LOAD_WRITE_PC: | |
36073a92 | 4475 | load_write_pc (regs, dsc, val); |
cca44b1b JB |
4476 | break; |
4477 | ||
4478 | case ALU_WRITE_PC: | |
36073a92 | 4479 | alu_write_pc (regs, dsc, val); |
cca44b1b JB |
4480 | break; |
4481 | ||
4482 | case CANNOT_WRITE_PC: | |
4483 | warning (_("Instruction wrote to PC in an unexpected way when " | |
4484 | "single-stepping")); | |
08216dd7 RE |
4485 | break; |
4486 | ||
4487 | default: | |
97b9747c JB |
4488 | internal_error (__FILE__, __LINE__, |
4489 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 4490 | } |
b508a996 | 4491 | |
cca44b1b | 4492 | dsc->wrote_to_pc = 1; |
b508a996 | 4493 | } |
ed9a39eb | 4494 | else |
b508a996 | 4495 | { |
cca44b1b JB |
4496 | if (debug_displaced) |
4497 | fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", | |
4498 | regno, (unsigned long) val); | |
4499 | regcache_cooked_write_unsigned (regs, regno, val); | |
b508a996 | 4500 | } |
34e8f22d RE |
4501 | } |
4502 | ||
cca44b1b JB |
4503 | /* This function is used to concisely determine if an instruction INSN |
4504 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
4505 | corresponding fields of BITMASK set to 0b1111. The function |
4506 | returns return 1 if any of these fields in INSN reference the PC | |
4507 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
4508 | |
4509 | static int | |
cca44b1b | 4510 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 4511 | { |
cca44b1b | 4512 | uint32_t lowbit = 1; |
67255d04 | 4513 | |
cca44b1b JB |
4514 | while (bitmask != 0) |
4515 | { | |
4516 | uint32_t mask; | |
44e1a9eb | 4517 | |
cca44b1b JB |
4518 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
4519 | ; | |
67255d04 | 4520 | |
cca44b1b JB |
4521 | if (!lowbit) |
4522 | break; | |
67255d04 | 4523 | |
cca44b1b | 4524 | mask = lowbit * 0xf; |
67255d04 | 4525 | |
cca44b1b JB |
4526 | if ((insn & mask) == mask) |
4527 | return 1; | |
4528 | ||
4529 | bitmask &= ~mask; | |
67255d04 RE |
4530 | } |
4531 | ||
cca44b1b JB |
4532 | return 0; |
4533 | } | |
2af48f68 | 4534 | |
cca44b1b JB |
4535 | /* The simplest copy function. Many instructions have the same effect no |
4536 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 4537 | |
cca44b1b | 4538 | static int |
7ff120b4 YQ |
4539 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, |
4540 | const char *iname, struct displaced_step_closure *dsc) | |
cca44b1b JB |
4541 | { |
4542 | if (debug_displaced) | |
4543 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " | |
4544 | "opcode/class '%s' unmodified\n", (unsigned long) insn, | |
4545 | iname); | |
67255d04 | 4546 | |
cca44b1b | 4547 | dsc->modinsn[0] = insn; |
67255d04 | 4548 | |
cca44b1b JB |
4549 | return 0; |
4550 | } | |
4551 | ||
34518530 YQ |
4552 | static int |
4553 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
4554 | uint16_t insn2, const char *iname, | |
4555 | struct displaced_step_closure *dsc) | |
4556 | { | |
4557 | if (debug_displaced) | |
4558 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, " | |
4559 | "opcode/class '%s' unmodified\n", insn1, insn2, | |
4560 | iname); | |
4561 | ||
4562 | dsc->modinsn[0] = insn1; | |
4563 | dsc->modinsn[1] = insn2; | |
4564 | dsc->numinsns = 2; | |
4565 | ||
4566 | return 0; | |
4567 | } | |
4568 | ||
4569 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
4570 | modification. */ | |
4571 | static int | |
4572 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn, | |
4573 | const char *iname, | |
4574 | struct displaced_step_closure *dsc) | |
4575 | { | |
4576 | if (debug_displaced) | |
4577 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, " | |
4578 | "opcode/class '%s' unmodified\n", insn, | |
4579 | iname); | |
4580 | ||
4581 | dsc->modinsn[0] = insn; | |
4582 | ||
4583 | return 0; | |
4584 | } | |
4585 | ||
cca44b1b JB |
4586 | /* Preload instructions with immediate offset. */ |
4587 | ||
4588 | static void | |
6e39997a | 4589 | cleanup_preload (struct gdbarch *gdbarch, |
cca44b1b JB |
4590 | struct regcache *regs, struct displaced_step_closure *dsc) |
4591 | { | |
4592 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4593 | if (!dsc->u.preload.immed) | |
4594 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
4595 | } | |
4596 | ||
7ff120b4 YQ |
4597 | static void |
4598 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
4599 | struct displaced_step_closure *dsc, unsigned int rn) | |
cca44b1b | 4600 | { |
cca44b1b | 4601 | ULONGEST rn_val; |
cca44b1b JB |
4602 | /* Preload instructions: |
4603 | ||
4604 | {pli/pld} [rn, #+/-imm] | |
4605 | -> | |
4606 | {pli/pld} [r0, #+/-imm]. */ | |
4607 | ||
36073a92 YQ |
4608 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4609 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 4610 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
4611 | dsc->u.preload.immed = 1; |
4612 | ||
cca44b1b | 4613 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
4614 | } |
4615 | ||
cca44b1b | 4616 | static int |
7ff120b4 | 4617 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
cca44b1b JB |
4618 | struct displaced_step_closure *dsc) |
4619 | { | |
4620 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 4621 | |
7ff120b4 YQ |
4622 | if (!insn_references_pc (insn, 0x000f0000ul)) |
4623 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b JB |
4624 | |
4625 | if (debug_displaced) | |
4626 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
4627 | (unsigned long) insn); | |
4628 | ||
7ff120b4 YQ |
4629 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4630 | ||
4631 | install_preload (gdbarch, regs, dsc, rn); | |
4632 | ||
4633 | return 0; | |
4634 | } | |
4635 | ||
34518530 YQ |
4636 | static int |
4637 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
4638 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4639 | { | |
4640 | unsigned int rn = bits (insn1, 0, 3); | |
4641 | unsigned int u_bit = bit (insn1, 7); | |
4642 | int imm12 = bits (insn2, 0, 11); | |
4643 | ULONGEST pc_val; | |
4644 | ||
4645 | if (rn != ARM_PC_REGNUM) | |
4646 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
4647 | ||
4648 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
4649 | PLD (literal) Encoding T1. */ | |
4650 | if (debug_displaced) | |
4651 | fprintf_unfiltered (gdb_stdlog, | |
4652 | "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n", | |
4653 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
4654 | imm12); | |
4655 | ||
4656 | if (!u_bit) | |
4657 | imm12 = -1 * imm12; | |
4658 | ||
4659 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
4660 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
4661 | ||
4662 | {pli/pld} [r0, r1] | |
4663 | ||
4664 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
4665 | ||
4666 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
4667 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4668 | ||
4669 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
4670 | ||
4671 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
4672 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
4673 | dsc->u.preload.immed = 0; | |
4674 | ||
4675 | /* {pli/pld} [r0, r1] */ | |
4676 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4677 | dsc->modinsn[1] = 0xf001; | |
4678 | dsc->numinsns = 2; | |
4679 | ||
4680 | dsc->cleanup = &cleanup_preload; | |
4681 | return 0; | |
4682 | } | |
4683 | ||
7ff120b4 YQ |
4684 | /* Preload instructions with register offset. */ |
4685 | ||
4686 | static void | |
4687 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
4688 | struct displaced_step_closure *dsc, unsigned int rn, | |
4689 | unsigned int rm) | |
4690 | { | |
4691 | ULONGEST rn_val, rm_val; | |
4692 | ||
cca44b1b JB |
4693 | /* Preload register-offset instructions: |
4694 | ||
4695 | {pli/pld} [rn, rm {, shift}] | |
4696 | -> | |
4697 | {pli/pld} [r0, r1 {, shift}]. */ | |
4698 | ||
36073a92 YQ |
4699 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4700 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4701 | rn_val = displaced_read_reg (regs, dsc, rn); | |
4702 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
4703 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4704 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
4705 | dsc->u.preload.immed = 0; |
4706 | ||
cca44b1b | 4707 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
4708 | } |
4709 | ||
4710 | static int | |
4711 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
4712 | struct regcache *regs, | |
4713 | struct displaced_step_closure *dsc) | |
4714 | { | |
4715 | unsigned int rn = bits (insn, 16, 19); | |
4716 | unsigned int rm = bits (insn, 0, 3); | |
4717 | ||
4718 | ||
4719 | if (!insn_references_pc (insn, 0x000f000ful)) | |
4720 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
4721 | ||
4722 | if (debug_displaced) | |
4723 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
4724 | (unsigned long) insn); | |
4725 | ||
4726 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 4727 | |
7ff120b4 | 4728 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
4729 | return 0; |
4730 | } | |
4731 | ||
4732 | /* Copy/cleanup coprocessor load and store instructions. */ | |
4733 | ||
4734 | static void | |
6e39997a | 4735 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b JB |
4736 | struct regcache *regs, |
4737 | struct displaced_step_closure *dsc) | |
4738 | { | |
36073a92 | 4739 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
4740 | |
4741 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4742 | ||
4743 | if (dsc->u.ldst.writeback) | |
4744 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
4745 | } | |
4746 | ||
7ff120b4 YQ |
4747 | static void |
4748 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
4749 | struct displaced_step_closure *dsc, | |
4750 | int writeback, unsigned int rn) | |
cca44b1b | 4751 | { |
cca44b1b | 4752 | ULONGEST rn_val; |
cca44b1b | 4753 | |
cca44b1b JB |
4754 | /* Coprocessor load/store instructions: |
4755 | ||
4756 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
4757 | -> | |
4758 | {stc/stc2} [r0, #+/-imm]. | |
4759 | ||
4760 | ldc/ldc2 are handled identically. */ | |
4761 | ||
36073a92 YQ |
4762 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4763 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
4764 | /* PC should be 4-byte aligned. */ |
4765 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
4766 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4767 | ||
7ff120b4 | 4768 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
4769 | dsc->u.ldst.rn = rn; |
4770 | ||
7ff120b4 YQ |
4771 | dsc->cleanup = &cleanup_copro_load_store; |
4772 | } | |
4773 | ||
4774 | static int | |
4775 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
4776 | struct regcache *regs, | |
4777 | struct displaced_step_closure *dsc) | |
4778 | { | |
4779 | unsigned int rn = bits (insn, 16, 19); | |
4780 | ||
4781 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
4782 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
4783 | ||
4784 | if (debug_displaced) | |
4785 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " | |
4786 | "load/store insn %.8lx\n", (unsigned long) insn); | |
4787 | ||
cca44b1b JB |
4788 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4789 | ||
7ff120b4 | 4790 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
4791 | |
4792 | return 0; | |
4793 | } | |
4794 | ||
34518530 YQ |
4795 | static int |
4796 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
4797 | uint16_t insn2, struct regcache *regs, | |
4798 | struct displaced_step_closure *dsc) | |
4799 | { | |
4800 | unsigned int rn = bits (insn1, 0, 3); | |
4801 | ||
4802 | if (rn != ARM_PC_REGNUM) | |
4803 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
4804 | "copro load/store", dsc); | |
4805 | ||
4806 | if (debug_displaced) | |
4807 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " | |
4808 | "load/store insn %.4x%.4x\n", insn1, insn2); | |
4809 | ||
4810 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4811 | dsc->modinsn[1] = insn2; | |
4812 | dsc->numinsns = 2; | |
4813 | ||
4814 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
4815 | doesn't support writeback, so pass 0. */ | |
4816 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
4817 | ||
4818 | return 0; | |
4819 | } | |
4820 | ||
cca44b1b JB |
4821 | /* Clean up branch instructions (actually perform the branch, by setting |
4822 | PC). */ | |
4823 | ||
4824 | static void | |
6e39997a | 4825 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
4826 | struct displaced_step_closure *dsc) |
4827 | { | |
36073a92 | 4828 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
4829 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
4830 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
4831 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
4832 | ||
4833 | if (!branch_taken) | |
4834 | return; | |
4835 | ||
4836 | if (dsc->u.branch.link) | |
4837 | { | |
8c8dba6d YQ |
4838 | /* The value of LR should be the next insn of current one. In order |
4839 | not to confuse logic hanlding later insn `bx lr', if current insn mode | |
4840 | is Thumb, the bit 0 of LR value should be set to 1. */ | |
4841 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
4842 | ||
4843 | if (dsc->is_thumb) | |
4844 | next_insn_addr |= 0x1; | |
4845 | ||
4846 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
4847 | CANNOT_WRITE_PC); | |
cca44b1b JB |
4848 | } |
4849 | ||
bf9f652a | 4850 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
4851 | } |
4852 | ||
4853 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
4854 | ||
7ff120b4 YQ |
4855 | static void |
4856 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
4857 | struct displaced_step_closure *dsc, | |
4858 | unsigned int cond, int exchange, int link, long offset) | |
4859 | { | |
4860 | /* Implement "BL<cond> <label>" as: | |
4861 | ||
4862 | Preparation: cond <- instruction condition | |
4863 | Insn: mov r0, r0 (nop) | |
4864 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
4865 | ||
4866 | B<cond> similar, but don't set r14 in cleanup. */ | |
4867 | ||
4868 | dsc->u.branch.cond = cond; | |
4869 | dsc->u.branch.link = link; | |
4870 | dsc->u.branch.exchange = exchange; | |
4871 | ||
2b16b2e3 YQ |
4872 | dsc->u.branch.dest = dsc->insn_addr; |
4873 | if (link && exchange) | |
4874 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
4875 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
4876 | ||
7ff120b4 | 4877 | if (dsc->is_thumb) |
2b16b2e3 | 4878 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 4879 | else |
2b16b2e3 | 4880 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
4881 | |
4882 | dsc->cleanup = &cleanup_branch; | |
4883 | } | |
cca44b1b | 4884 | static int |
7ff120b4 YQ |
4885 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
4886 | struct regcache *regs, struct displaced_step_closure *dsc) | |
cca44b1b JB |
4887 | { |
4888 | unsigned int cond = bits (insn, 28, 31); | |
4889 | int exchange = (cond == 0xf); | |
4890 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
4891 | long offset; |
4892 | ||
4893 | if (debug_displaced) | |
4894 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " | |
4895 | "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", | |
4896 | (unsigned long) insn); | |
cca44b1b JB |
4897 | if (exchange) |
4898 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
4899 | then arrange the switch into Thumb mode. */ | |
4900 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
4901 | else | |
4902 | offset = bits (insn, 0, 23) << 2; | |
4903 | ||
4904 | if (bit (offset, 25)) | |
4905 | offset = offset | ~0x3ffffff; | |
4906 | ||
cca44b1b JB |
4907 | dsc->modinsn[0] = ARM_NOP; |
4908 | ||
7ff120b4 | 4909 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
4910 | return 0; |
4911 | } | |
4912 | ||
34518530 YQ |
4913 | static int |
4914 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
4915 | uint16_t insn2, struct regcache *regs, | |
4916 | struct displaced_step_closure *dsc) | |
4917 | { | |
4918 | int link = bit (insn2, 14); | |
4919 | int exchange = link && !bit (insn2, 12); | |
4920 | int cond = INST_AL; | |
4921 | long offset = 0; | |
4922 | int j1 = bit (insn2, 13); | |
4923 | int j2 = bit (insn2, 11); | |
4924 | int s = sbits (insn1, 10, 10); | |
4925 | int i1 = !(j1 ^ bit (insn1, 10)); | |
4926 | int i2 = !(j2 ^ bit (insn1, 10)); | |
4927 | ||
4928 | if (!link && !exchange) /* B */ | |
4929 | { | |
4930 | offset = (bits (insn2, 0, 10) << 1); | |
4931 | if (bit (insn2, 12)) /* Encoding T4 */ | |
4932 | { | |
4933 | offset |= (bits (insn1, 0, 9) << 12) | |
4934 | | (i2 << 22) | |
4935 | | (i1 << 23) | |
4936 | | (s << 24); | |
4937 | cond = INST_AL; | |
4938 | } | |
4939 | else /* Encoding T3 */ | |
4940 | { | |
4941 | offset |= (bits (insn1, 0, 5) << 12) | |
4942 | | (j1 << 18) | |
4943 | | (j2 << 19) | |
4944 | | (s << 20); | |
4945 | cond = bits (insn1, 6, 9); | |
4946 | } | |
4947 | } | |
4948 | else | |
4949 | { | |
4950 | offset = (bits (insn1, 0, 9) << 12); | |
4951 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
4952 | offset |= exchange ? | |
4953 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
4954 | } | |
4955 | ||
4956 | if (debug_displaced) | |
4957 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn " | |
4958 | "%.4x %.4x with offset %.8lx\n", | |
4959 | link ? (exchange) ? "blx" : "bl" : "b", | |
4960 | insn1, insn2, offset); | |
4961 | ||
4962 | dsc->modinsn[0] = THUMB_NOP; | |
4963 | ||
4964 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
4965 | return 0; | |
4966 | } | |
4967 | ||
4968 | /* Copy B Thumb instructions. */ | |
4969 | static int | |
4970 | thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn, | |
4971 | struct displaced_step_closure *dsc) | |
4972 | { | |
4973 | unsigned int cond = 0; | |
4974 | int offset = 0; | |
4975 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
4976 | CORE_ADDR from = dsc->insn_addr; | |
4977 | ||
4978 | if (bit_12_15 == 0xd) | |
4979 | { | |
4980 | /* offset = SignExtend (imm8:0, 32) */ | |
4981 | offset = sbits ((insn << 1), 0, 8); | |
4982 | cond = bits (insn, 8, 11); | |
4983 | } | |
4984 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
4985 | { | |
4986 | offset = sbits ((insn << 1), 0, 11); | |
4987 | cond = INST_AL; | |
4988 | } | |
4989 | ||
4990 | if (debug_displaced) | |
4991 | fprintf_unfiltered (gdb_stdlog, | |
4992 | "displaced: copying b immediate insn %.4x " | |
4993 | "with offset %d\n", insn, offset); | |
4994 | ||
4995 | dsc->u.branch.cond = cond; | |
4996 | dsc->u.branch.link = 0; | |
4997 | dsc->u.branch.exchange = 0; | |
4998 | dsc->u.branch.dest = from + 4 + offset; | |
4999 | ||
5000 | dsc->modinsn[0] = THUMB_NOP; | |
5001 | ||
5002 | dsc->cleanup = &cleanup_branch; | |
5003 | ||
5004 | return 0; | |
5005 | } | |
5006 | ||
cca44b1b JB |
5007 | /* Copy BX/BLX with register-specified destinations. */ |
5008 | ||
7ff120b4 YQ |
5009 | static void |
5010 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
5011 | struct displaced_step_closure *dsc, int link, | |
5012 | unsigned int cond, unsigned int rm) | |
cca44b1b | 5013 | { |
cca44b1b JB |
5014 | /* Implement {BX,BLX}<cond> <reg>" as: |
5015 | ||
5016 | Preparation: cond <- instruction condition | |
5017 | Insn: mov r0, r0 (nop) | |
5018 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5019 | ||
5020 | Don't set r14 in cleanup for BX. */ | |
5021 | ||
36073a92 | 5022 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5023 | |
5024 | dsc->u.branch.cond = cond; | |
5025 | dsc->u.branch.link = link; | |
cca44b1b | 5026 | |
7ff120b4 | 5027 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
5028 | |
5029 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 5030 | } |
cca44b1b | 5031 | |
7ff120b4 YQ |
5032 | static int |
5033 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5034 | struct regcache *regs, struct displaced_step_closure *dsc) | |
5035 | { | |
5036 | unsigned int cond = bits (insn, 28, 31); | |
5037 | /* BX: x12xxx1x | |
5038 | BLX: x12xxx3x. */ | |
5039 | int link = bit (insn, 5); | |
5040 | unsigned int rm = bits (insn, 0, 3); | |
5041 | ||
5042 | if (debug_displaced) | |
5043 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx", | |
5044 | (unsigned long) insn); | |
5045 | ||
5046 | dsc->modinsn[0] = ARM_NOP; | |
5047 | ||
5048 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
5049 | return 0; |
5050 | } | |
5051 | ||
34518530 YQ |
5052 | static int |
5053 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5054 | struct regcache *regs, | |
5055 | struct displaced_step_closure *dsc) | |
5056 | { | |
5057 | int link = bit (insn, 7); | |
5058 | unsigned int rm = bits (insn, 3, 6); | |
5059 | ||
5060 | if (debug_displaced) | |
5061 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x", | |
5062 | (unsigned short) insn); | |
5063 | ||
5064 | dsc->modinsn[0] = THUMB_NOP; | |
5065 | ||
5066 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
5067 | ||
5068 | return 0; | |
5069 | } | |
5070 | ||
5071 | ||
0963b4bd | 5072 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
5073 | |
5074 | static void | |
6e39997a | 5075 | cleanup_alu_imm (struct gdbarch *gdbarch, |
cca44b1b JB |
5076 | struct regcache *regs, struct displaced_step_closure *dsc) |
5077 | { | |
36073a92 | 5078 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5079 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
5080 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5081 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5082 | } | |
5083 | ||
5084 | static int | |
7ff120b4 YQ |
5085 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
5086 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
5087 | { |
5088 | unsigned int rn = bits (insn, 16, 19); | |
5089 | unsigned int rd = bits (insn, 12, 15); | |
5090 | unsigned int op = bits (insn, 21, 24); | |
5091 | int is_mov = (op == 0xd); | |
5092 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
5093 | |
5094 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 5095 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b JB |
5096 | |
5097 | if (debug_displaced) | |
5098 | fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn " | |
5099 | "%.8lx\n", is_mov ? "move" : "ALU", | |
5100 | (unsigned long) insn); | |
5101 | ||
5102 | /* Instruction is of form: | |
5103 | ||
5104 | <op><cond> rd, [rn,] #imm | |
5105 | ||
5106 | Rewrite as: | |
5107 | ||
5108 | Preparation: tmp1, tmp2 <- r0, r1; | |
5109 | r0, r1 <- rd, rn | |
5110 | Insn: <op><cond> r0, r1, #imm | |
5111 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5112 | */ | |
5113 | ||
36073a92 YQ |
5114 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5115 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5116 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5117 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
5118 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5119 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5120 | dsc->rd = rd; | |
5121 | ||
5122 | if (is_mov) | |
5123 | dsc->modinsn[0] = insn & 0xfff00fff; | |
5124 | else | |
5125 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
5126 | ||
5127 | dsc->cleanup = &cleanup_alu_imm; | |
5128 | ||
5129 | return 0; | |
5130 | } | |
5131 | ||
34518530 YQ |
5132 | static int |
5133 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5134 | uint16_t insn2, struct regcache *regs, | |
5135 | struct displaced_step_closure *dsc) | |
5136 | { | |
5137 | unsigned int op = bits (insn1, 5, 8); | |
5138 | unsigned int rn, rm, rd; | |
5139 | ULONGEST rd_val, rn_val; | |
5140 | ||
5141 | rn = bits (insn1, 0, 3); /* Rn */ | |
5142 | rm = bits (insn2, 0, 3); /* Rm */ | |
5143 | rd = bits (insn2, 8, 11); /* Rd */ | |
5144 | ||
5145 | /* This routine is only called for instruction MOV. */ | |
5146 | gdb_assert (op == 0x2 && rn == 0xf); | |
5147 | ||
5148 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
5149 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
5150 | ||
5151 | if (debug_displaced) | |
5152 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n", | |
5153 | "ALU", insn1, insn2); | |
5154 | ||
5155 | /* Instruction is of form: | |
5156 | ||
5157 | <op><cond> rd, [rn,] #imm | |
5158 | ||
5159 | Rewrite as: | |
5160 | ||
5161 | Preparation: tmp1, tmp2 <- r0, r1; | |
5162 | r0, r1 <- rd, rn | |
5163 | Insn: <op><cond> r0, r1, #imm | |
5164 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5165 | */ | |
5166 | ||
5167 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5168 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5169 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5170 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5171 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
5172 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5173 | dsc->rd = rd; | |
5174 | ||
5175 | dsc->modinsn[0] = insn1; | |
5176 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
5177 | dsc->numinsns = 2; | |
5178 | ||
5179 | dsc->cleanup = &cleanup_alu_imm; | |
5180 | ||
5181 | return 0; | |
5182 | } | |
5183 | ||
cca44b1b JB |
5184 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
5185 | ||
5186 | static void | |
6e39997a | 5187 | cleanup_alu_reg (struct gdbarch *gdbarch, |
cca44b1b JB |
5188 | struct regcache *regs, struct displaced_step_closure *dsc) |
5189 | { | |
5190 | ULONGEST rd_val; | |
5191 | int i; | |
5192 | ||
36073a92 | 5193 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5194 | |
5195 | for (i = 0; i < 3; i++) | |
5196 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5197 | ||
5198 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5199 | } | |
5200 | ||
7ff120b4 YQ |
5201 | static void |
5202 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
5203 | struct displaced_step_closure *dsc, | |
5204 | unsigned int rd, unsigned int rn, unsigned int rm) | |
cca44b1b | 5205 | { |
cca44b1b | 5206 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 5207 | |
cca44b1b JB |
5208 | /* Instruction is of form: |
5209 | ||
5210 | <op><cond> rd, [rn,] rm [, <shift>] | |
5211 | ||
5212 | Rewrite as: | |
5213 | ||
5214 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
5215 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 5216 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
5217 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
5218 | */ | |
5219 | ||
36073a92 YQ |
5220 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5221 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5222 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5223 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5224 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5225 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5226 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5227 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5228 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5229 | dsc->rd = rd; | |
5230 | ||
7ff120b4 YQ |
5231 | dsc->cleanup = &cleanup_alu_reg; |
5232 | } | |
5233 | ||
5234 | static int | |
5235 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
5236 | struct displaced_step_closure *dsc) | |
5237 | { | |
5238 | unsigned int op = bits (insn, 21, 24); | |
5239 | int is_mov = (op == 0xd); | |
5240 | ||
5241 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5242 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
5243 | ||
5244 | if (debug_displaced) | |
5245 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n", | |
5246 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
5247 | ||
cca44b1b JB |
5248 | if (is_mov) |
5249 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
5250 | else | |
5251 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
5252 | ||
7ff120b4 YQ |
5253 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
5254 | bits (insn, 0, 3)); | |
cca44b1b JB |
5255 | return 0; |
5256 | } | |
5257 | ||
34518530 YQ |
5258 | static int |
5259 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5260 | struct regcache *regs, | |
5261 | struct displaced_step_closure *dsc) | |
5262 | { | |
ef713951 | 5263 | unsigned rm, rd; |
34518530 | 5264 | |
ef713951 YQ |
5265 | rm = bits (insn, 3, 6); |
5266 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 5267 | |
ef713951 | 5268 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
5269 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
5270 | ||
5271 | if (debug_displaced) | |
ef713951 YQ |
5272 | fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n", |
5273 | (unsigned short) insn); | |
34518530 | 5274 | |
ef713951 | 5275 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 5276 | |
ef713951 | 5277 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
5278 | |
5279 | return 0; | |
5280 | } | |
5281 | ||
cca44b1b JB |
5282 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
5283 | ||
5284 | static void | |
6e39997a | 5285 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b JB |
5286 | struct regcache *regs, |
5287 | struct displaced_step_closure *dsc) | |
5288 | { | |
36073a92 | 5289 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5290 | int i; |
5291 | ||
5292 | for (i = 0; i < 4; i++) | |
5293 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5294 | ||
5295 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5296 | } | |
5297 | ||
7ff120b4 YQ |
5298 | static void |
5299 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
5300 | struct displaced_step_closure *dsc, | |
5301 | unsigned int rd, unsigned int rn, unsigned int rm, | |
5302 | unsigned rs) | |
cca44b1b | 5303 | { |
7ff120b4 | 5304 | int i; |
cca44b1b | 5305 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 5306 | |
cca44b1b JB |
5307 | /* Instruction is of form: |
5308 | ||
5309 | <op><cond> rd, [rn,] rm, <shift> rs | |
5310 | ||
5311 | Rewrite as: | |
5312 | ||
5313 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
5314 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
5315 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
5316 | Cleanup: tmp5 <- r0 | |
5317 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
5318 | rd <- tmp5 | |
5319 | */ | |
5320 | ||
5321 | for (i = 0; i < 4; i++) | |
36073a92 | 5322 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 5323 | |
36073a92 YQ |
5324 | rd_val = displaced_read_reg (regs, dsc, rd); |
5325 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5326 | rm_val = displaced_read_reg (regs, dsc, rm); | |
5327 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
5328 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5329 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5330 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5331 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
5332 | dsc->rd = rd; | |
7ff120b4 YQ |
5333 | dsc->cleanup = &cleanup_alu_shifted_reg; |
5334 | } | |
5335 | ||
5336 | static int | |
5337 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5338 | struct regcache *regs, | |
5339 | struct displaced_step_closure *dsc) | |
5340 | { | |
5341 | unsigned int op = bits (insn, 21, 24); | |
5342 | int is_mov = (op == 0xd); | |
5343 | unsigned int rd, rn, rm, rs; | |
5344 | ||
5345 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
5346 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
5347 | ||
5348 | if (debug_displaced) | |
5349 | fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn " | |
5350 | "%.8lx\n", is_mov ? "move" : "ALU", | |
5351 | (unsigned long) insn); | |
5352 | ||
5353 | rn = bits (insn, 16, 19); | |
5354 | rm = bits (insn, 0, 3); | |
5355 | rs = bits (insn, 8, 11); | |
5356 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
5357 | |
5358 | if (is_mov) | |
5359 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
5360 | else | |
5361 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
5362 | ||
7ff120b4 | 5363 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
5364 | |
5365 | return 0; | |
5366 | } | |
5367 | ||
5368 | /* Clean up load instructions. */ | |
5369 | ||
5370 | static void | |
6e39997a | 5371 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
5372 | struct displaced_step_closure *dsc) |
5373 | { | |
5374 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 5375 | |
36073a92 | 5376 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 5377 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
5378 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
5379 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
5380 | |
5381 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5382 | if (dsc->u.ldst.xfersize > 4) | |
5383 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5384 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5385 | if (!dsc->u.ldst.immed) | |
5386 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5387 | ||
5388 | /* Handle register writeback. */ | |
5389 | if (dsc->u.ldst.writeback) | |
5390 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5391 | /* Put result in right place. */ | |
5392 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
5393 | if (dsc->u.ldst.xfersize == 8) | |
5394 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
5395 | } | |
5396 | ||
5397 | /* Clean up store instructions. */ | |
5398 | ||
5399 | static void | |
6e39997a | 5400 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
5401 | struct displaced_step_closure *dsc) |
5402 | { | |
36073a92 | 5403 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
5404 | |
5405 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5406 | if (dsc->u.ldst.xfersize > 4) | |
5407 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5408 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5409 | if (!dsc->u.ldst.immed) | |
5410 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5411 | if (!dsc->u.ldst.restore_r4) | |
5412 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
5413 | ||
5414 | /* Writeback. */ | |
5415 | if (dsc->u.ldst.writeback) | |
5416 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5417 | } | |
5418 | ||
5419 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
5420 | transfers, which have a different encoding to byte/word transfers. */ | |
5421 | ||
5422 | static int | |
550dc4e2 | 5423 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
7ff120b4 | 5424 | struct regcache *regs, struct displaced_step_closure *dsc) |
cca44b1b JB |
5425 | { |
5426 | unsigned int op1 = bits (insn, 20, 24); | |
5427 | unsigned int op2 = bits (insn, 5, 6); | |
5428 | unsigned int rt = bits (insn, 12, 15); | |
5429 | unsigned int rn = bits (insn, 16, 19); | |
5430 | unsigned int rm = bits (insn, 0, 3); | |
5431 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
5432 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
5433 | int immed = (op1 & 0x4) != 0; | |
5434 | int opcode; | |
5435 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
5436 | |
5437 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 5438 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b JB |
5439 | |
5440 | if (debug_displaced) | |
5441 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " | |
550dc4e2 | 5442 | "insn %.8lx\n", unprivileged ? "unprivileged " : "", |
cca44b1b JB |
5443 | (unsigned long) insn); |
5444 | ||
5445 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
5446 | ||
5447 | if (opcode < 0) | |
5448 | internal_error (__FILE__, __LINE__, | |
5449 | _("copy_extra_ld_st: instruction decode error")); | |
5450 | ||
36073a92 YQ |
5451 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5452 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5453 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5454 | if (!immed) |
36073a92 | 5455 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5456 | |
36073a92 | 5457 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 5458 | if (bytesize[opcode] == 8) |
36073a92 YQ |
5459 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
5460 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5461 | if (!immed) |
36073a92 | 5462 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5463 | |
5464 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5465 | if (bytesize[opcode] == 8) | |
5466 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
5467 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5468 | if (!immed) | |
5469 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
5470 | ||
5471 | dsc->rd = rt; | |
5472 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
5473 | dsc->u.ldst.rn = rn; | |
5474 | dsc->u.ldst.immed = immed; | |
5475 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
5476 | dsc->u.ldst.restore_r4 = 0; | |
5477 | ||
5478 | if (immed) | |
5479 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
5480 | -> | |
5481 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
5482 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5483 | else | |
5484 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
5485 | -> | |
5486 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
5487 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5488 | ||
5489 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
5490 | ||
5491 | return 0; | |
5492 | } | |
5493 | ||
0f6f04ba | 5494 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 5495 | |
7ff120b4 | 5496 | static void |
0f6f04ba YQ |
5497 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
5498 | struct displaced_step_closure *dsc, int load, | |
5499 | int immed, int writeback, int size, int usermode, | |
5500 | int rt, int rm, int rn) | |
cca44b1b | 5501 | { |
cca44b1b | 5502 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 5503 | |
36073a92 YQ |
5504 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5505 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5506 | if (!immed) |
36073a92 | 5507 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5508 | if (!load) |
36073a92 | 5509 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 5510 | |
36073a92 YQ |
5511 | rt_val = displaced_read_reg (regs, dsc, rt); |
5512 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5513 | if (!immed) |
36073a92 | 5514 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5515 | |
5516 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5517 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5518 | if (!immed) | |
5519 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 5520 | dsc->rd = rt; |
0f6f04ba | 5521 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
5522 | dsc->u.ldst.rn = rn; |
5523 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 5524 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5525 | |
5526 | /* To write PC we can do: | |
5527 | ||
494e194e YQ |
5528 | Before this sequence of instructions: |
5529 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
5530 | r2 is the Rn value got from dispalced_read_reg. | |
5531 | ||
5532 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
5533 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
5534 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
5535 | = addr(Insn1) + offset - addr(Insn3) - 8 | |
5536 | = offset - 16 | |
5537 | Insn4: add r4, r4, #8 r4 = offset - 8 | |
5538 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
5539 | = from + offset | |
5540 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) | |
cca44b1b JB |
5541 | |
5542 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
5543 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
5544 | of this can be found in Section "Saving from r15" in | |
5545 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 5546 | |
7ff120b4 YQ |
5547 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
5548 | } | |
5549 | ||
34518530 YQ |
5550 | |
5551 | static int | |
5552 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
5553 | uint16_t insn2, struct regcache *regs, | |
5554 | struct displaced_step_closure *dsc, int size) | |
5555 | { | |
5556 | unsigned int u_bit = bit (insn1, 7); | |
5557 | unsigned int rt = bits (insn2, 12, 15); | |
5558 | int imm12 = bits (insn2, 0, 11); | |
5559 | ULONGEST pc_val; | |
5560 | ||
5561 | if (debug_displaced) | |
5562 | fprintf_unfiltered (gdb_stdlog, | |
5563 | "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n", | |
5564 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
5565 | imm12); | |
5566 | ||
5567 | if (!u_bit) | |
5568 | imm12 = -1 * imm12; | |
5569 | ||
5570 | /* Rewrite instruction LDR Rt imm12 into: | |
5571 | ||
5572 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
5573 | ||
5574 | LDR R0, R2, R3, | |
5575 | ||
5576 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
5577 | ||
5578 | ||
5579 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5580 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5581 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
5582 | ||
5583 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5584 | ||
5585 | pc_val = pc_val & 0xfffffffc; | |
5586 | ||
5587 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
5588 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
5589 | ||
5590 | dsc->rd = rt; | |
5591 | ||
5592 | dsc->u.ldst.xfersize = size; | |
5593 | dsc->u.ldst.immed = 0; | |
5594 | dsc->u.ldst.writeback = 0; | |
5595 | dsc->u.ldst.restore_r4 = 0; | |
5596 | ||
5597 | /* LDR R0, R2, R3 */ | |
5598 | dsc->modinsn[0] = 0xf852; | |
5599 | dsc->modinsn[1] = 0x3; | |
5600 | dsc->numinsns = 2; | |
5601 | ||
5602 | dsc->cleanup = &cleanup_load; | |
5603 | ||
5604 | return 0; | |
5605 | } | |
5606 | ||
5607 | static int | |
5608 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5609 | uint16_t insn2, struct regcache *regs, | |
5610 | struct displaced_step_closure *dsc, | |
5611 | int writeback, int immed) | |
5612 | { | |
5613 | unsigned int rt = bits (insn2, 12, 15); | |
5614 | unsigned int rn = bits (insn1, 0, 3); | |
5615 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
5616 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
5617 | be PC, so we don't have to check it. */ | |
5618 | ||
5619 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
5620 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
5621 | dsc); | |
5622 | ||
5623 | if (debug_displaced) | |
5624 | fprintf_unfiltered (gdb_stdlog, | |
5625 | "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n", | |
5626 | rt, rn, insn1, insn2); | |
5627 | ||
5628 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
5629 | 0, rt, rm, rn); | |
5630 | ||
5631 | dsc->u.ldst.restore_r4 = 0; | |
5632 | ||
5633 | if (immed) | |
5634 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
5635 | -> | |
5636 | ldr[b]<cond> r0, [r2, #imm]. */ | |
5637 | { | |
5638 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5639 | dsc->modinsn[1] = insn2 & 0x0fff; | |
5640 | } | |
5641 | else | |
5642 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
5643 | -> | |
5644 | ldr[b]<cond> r0, [r2, r3]. */ | |
5645 | { | |
5646 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5647 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
5648 | } | |
5649 | ||
5650 | dsc->numinsns = 2; | |
5651 | ||
5652 | return 0; | |
5653 | } | |
5654 | ||
5655 | ||
7ff120b4 YQ |
5656 | static int |
5657 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
5658 | struct regcache *regs, | |
5659 | struct displaced_step_closure *dsc, | |
0f6f04ba | 5660 | int load, int size, int usermode) |
7ff120b4 YQ |
5661 | { |
5662 | int immed = !bit (insn, 25); | |
5663 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
5664 | unsigned int rt = bits (insn, 12, 15); | |
5665 | unsigned int rn = bits (insn, 16, 19); | |
5666 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
5667 | ||
5668 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5669 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
5670 | ||
5671 | if (debug_displaced) | |
5672 | fprintf_unfiltered (gdb_stdlog, | |
5673 | "displaced: copying %s%s r%d [r%d] insn %.8lx\n", | |
0f6f04ba YQ |
5674 | load ? (size == 1 ? "ldrb" : "ldr") |
5675 | : (size == 1 ? "strb" : "str"), usermode ? "t" : "", | |
7ff120b4 YQ |
5676 | rt, rn, |
5677 | (unsigned long) insn); | |
5678 | ||
0f6f04ba YQ |
5679 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
5680 | usermode, rt, rm, rn); | |
7ff120b4 | 5681 | |
bf9f652a | 5682 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
5683 | { |
5684 | dsc->u.ldst.restore_r4 = 0; | |
5685 | ||
5686 | if (immed) | |
5687 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
5688 | -> | |
5689 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
5690 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5691 | else | |
5692 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
5693 | -> | |
5694 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
5695 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5696 | } | |
5697 | else | |
5698 | { | |
5699 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
5700 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
5701 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
5702 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
5703 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
5704 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
5705 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
5706 | ||
5707 | /* As above. */ | |
5708 | if (immed) | |
5709 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
5710 | else | |
5711 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
5712 | ||
cca44b1b JB |
5713 | dsc->numinsns = 6; |
5714 | } | |
5715 | ||
5716 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
5717 | ||
5718 | return 0; | |
5719 | } | |
5720 | ||
5721 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
5722 | unfortunate corner case: it's impossible to implement correctly by modifying | |
5723 | the instruction. The issue is as follows: we have an instruction, | |
5724 | ||
5725 | ldm rN, {r0-r15} | |
5726 | ||
5727 | which we must rewrite to avoid loading PC. A possible solution would be to | |
5728 | do the load in two halves, something like (with suitable cleanup | |
5729 | afterwards): | |
5730 | ||
5731 | mov r8, rN | |
5732 | ldm[id][ab] r8!, {r0-r7} | |
5733 | str r7, <temp> | |
5734 | ldm[id][ab] r8, {r7-r14} | |
5735 | <bkpt> | |
5736 | ||
5737 | but at present there's no suitable place for <temp>, since the scratch space | |
5738 | is overwritten before the cleanup routine is called. For now, we simply | |
5739 | emulate the instruction. */ | |
5740 | ||
5741 | static void | |
5742 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
5743 | struct displaced_step_closure *dsc) | |
5744 | { | |
cca44b1b JB |
5745 | int inc = dsc->u.block.increment; |
5746 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
5747 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
5748 | uint32_t regmask = dsc->u.block.regmask; | |
5749 | int regno = inc ? 0 : 15; | |
5750 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
5751 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
5752 | && (regmask & 0x8000) != 0; | |
36073a92 | 5753 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5754 | int do_transfer = condition_true (dsc->u.block.cond, status); |
5755 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5756 | ||
5757 | if (!do_transfer) | |
5758 | return; | |
5759 | ||
5760 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
5761 | sensible we can do here. Complain loudly. */ | |
5762 | if (exception_return) | |
5763 | error (_("Cannot single-step exception return")); | |
5764 | ||
5765 | /* We don't handle any stores here for now. */ | |
5766 | gdb_assert (dsc->u.block.load != 0); | |
5767 | ||
5768 | if (debug_displaced) | |
5769 | fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: " | |
5770 | "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm", | |
5771 | dsc->u.block.increment ? "inc" : "dec", | |
5772 | dsc->u.block.before ? "before" : "after"); | |
5773 | ||
5774 | while (regmask) | |
5775 | { | |
5776 | uint32_t memword; | |
5777 | ||
5778 | if (inc) | |
bf9f652a | 5779 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
5780 | regno++; |
5781 | else | |
5782 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
5783 | regno--; | |
5784 | ||
5785 | xfer_addr += bump_before; | |
5786 | ||
5787 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
5788 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
5789 | ||
5790 | xfer_addr += bump_after; | |
5791 | ||
5792 | regmask &= ~(1 << regno); | |
5793 | } | |
5794 | ||
5795 | if (dsc->u.block.writeback) | |
5796 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
5797 | CANNOT_WRITE_PC); | |
5798 | } | |
5799 | ||
5800 | /* Clean up an STM which included the PC in the register list. */ | |
5801 | ||
5802 | static void | |
5803 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
5804 | struct displaced_step_closure *dsc) | |
5805 | { | |
36073a92 | 5806 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5807 | int store_executed = condition_true (dsc->u.block.cond, status); |
5808 | CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask); | |
5809 | CORE_ADDR stm_insn_addr; | |
5810 | uint32_t pc_val; | |
5811 | long offset; | |
5812 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5813 | ||
5814 | /* If condition code fails, there's nothing else to do. */ | |
5815 | if (!store_executed) | |
5816 | return; | |
5817 | ||
5818 | if (dsc->u.block.increment) | |
5819 | { | |
5820 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
5821 | ||
5822 | if (dsc->u.block.before) | |
5823 | pc_stored_at += 4; | |
5824 | } | |
5825 | else | |
5826 | { | |
5827 | pc_stored_at = dsc->u.block.xfer_addr; | |
5828 | ||
5829 | if (dsc->u.block.before) | |
5830 | pc_stored_at -= 4; | |
5831 | } | |
5832 | ||
5833 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
5834 | stm_insn_addr = dsc->scratch_base; | |
5835 | offset = pc_val - stm_insn_addr; | |
5836 | ||
5837 | if (debug_displaced) | |
5838 | fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for " | |
5839 | "STM instruction\n", offset); | |
5840 | ||
5841 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
5842 | instruction. */ | |
5843 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
5844 | dsc->insn_addr + offset); | |
5845 | } | |
5846 | ||
5847 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
5848 | the registers in the transferred list into a contiguous range r0...rX (to | |
5849 | avoid loading PC directly and losing control of the debugged program), so we | |
5850 | must undo that here. */ | |
5851 | ||
5852 | static void | |
6e39997a | 5853 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b JB |
5854 | struct regcache *regs, |
5855 | struct displaced_step_closure *dsc) | |
5856 | { | |
36073a92 | 5857 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 5858 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 5859 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
cca44b1b JB |
5860 | unsigned int regs_loaded = bitcount (mask); |
5861 | unsigned int num_to_shuffle = regs_loaded, clobbered; | |
5862 | ||
5863 | /* The method employed here will fail if the register list is fully populated | |
5864 | (we need to avoid loading PC directly). */ | |
5865 | gdb_assert (num_to_shuffle < 16); | |
5866 | ||
5867 | if (!load_executed) | |
5868 | return; | |
5869 | ||
5870 | clobbered = (1 << num_to_shuffle) - 1; | |
5871 | ||
5872 | while (num_to_shuffle > 0) | |
5873 | { | |
5874 | if ((mask & (1 << write_reg)) != 0) | |
5875 | { | |
5876 | unsigned int read_reg = num_to_shuffle - 1; | |
5877 | ||
5878 | if (read_reg != write_reg) | |
5879 | { | |
36073a92 | 5880 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b JB |
5881 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
5882 | if (debug_displaced) | |
5883 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move " | |
5884 | "loaded register r%d to r%d\n"), read_reg, | |
5885 | write_reg); | |
5886 | } | |
5887 | else if (debug_displaced) | |
5888 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register " | |
5889 | "r%d already in the right place\n"), | |
5890 | write_reg); | |
5891 | ||
5892 | clobbered &= ~(1 << write_reg); | |
5893 | ||
5894 | num_to_shuffle--; | |
5895 | } | |
5896 | ||
5897 | write_reg--; | |
5898 | } | |
5899 | ||
5900 | /* Restore any registers we scribbled over. */ | |
5901 | for (write_reg = 0; clobbered != 0; write_reg++) | |
5902 | { | |
5903 | if ((clobbered & (1 << write_reg)) != 0) | |
5904 | { | |
5905 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
5906 | CANNOT_WRITE_PC); | |
5907 | if (debug_displaced) | |
5908 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored " | |
5909 | "clobbered register r%d\n"), write_reg); | |
5910 | clobbered &= ~(1 << write_reg); | |
5911 | } | |
5912 | } | |
5913 | ||
5914 | /* Perform register writeback manually. */ | |
5915 | if (dsc->u.block.writeback) | |
5916 | { | |
5917 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
5918 | ||
5919 | if (dsc->u.block.increment) | |
5920 | new_rn_val += regs_loaded * 4; | |
5921 | else | |
5922 | new_rn_val -= regs_loaded * 4; | |
5923 | ||
5924 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
5925 | CANNOT_WRITE_PC); | |
5926 | } | |
5927 | } | |
5928 | ||
5929 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
5930 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
5931 | ||
5932 | static int | |
7ff120b4 YQ |
5933 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
5934 | struct regcache *regs, | |
5935 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
5936 | { |
5937 | int load = bit (insn, 20); | |
5938 | int user = bit (insn, 22); | |
5939 | int increment = bit (insn, 23); | |
5940 | int before = bit (insn, 24); | |
5941 | int writeback = bit (insn, 21); | |
5942 | int rn = bits (insn, 16, 19); | |
cca44b1b | 5943 | |
0963b4bd MS |
5944 | /* Block transfers which don't mention PC can be run directly |
5945 | out-of-line. */ | |
bf9f652a | 5946 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 5947 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 5948 | |
bf9f652a | 5949 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 5950 | { |
0963b4bd MS |
5951 | warning (_("displaced: Unpredictable LDM or STM with " |
5952 | "base register r15")); | |
7ff120b4 | 5953 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
5954 | } |
5955 | ||
5956 | if (debug_displaced) | |
5957 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " | |
5958 | "%.8lx\n", (unsigned long) insn); | |
5959 | ||
36073a92 | 5960 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
5961 | dsc->u.block.rn = rn; |
5962 | ||
5963 | dsc->u.block.load = load; | |
5964 | dsc->u.block.user = user; | |
5965 | dsc->u.block.increment = increment; | |
5966 | dsc->u.block.before = before; | |
5967 | dsc->u.block.writeback = writeback; | |
5968 | dsc->u.block.cond = bits (insn, 28, 31); | |
5969 | ||
5970 | dsc->u.block.regmask = insn & 0xffff; | |
5971 | ||
5972 | if (load) | |
5973 | { | |
5974 | if ((insn & 0xffff) == 0xffff) | |
5975 | { | |
5976 | /* LDM with a fully-populated register list. This case is | |
5977 | particularly tricky. Implement for now by fully emulating the | |
5978 | instruction (which might not behave perfectly in all cases, but | |
5979 | these instructions should be rare enough for that not to matter | |
5980 | too much). */ | |
5981 | dsc->modinsn[0] = ARM_NOP; | |
5982 | ||
5983 | dsc->cleanup = &cleanup_block_load_all; | |
5984 | } | |
5985 | else | |
5986 | { | |
5987 | /* LDM of a list of registers which includes PC. Implement by | |
5988 | rewriting the list of registers to be transferred into a | |
5989 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
5990 | registers into the correct places in the cleanup routine. */ | |
5991 | unsigned int regmask = insn & 0xffff; | |
5992 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; | |
5993 | unsigned int to = 0, from = 0, i, new_rn; | |
5994 | ||
5995 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 5996 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
5997 | |
5998 | /* Writeback makes things complicated. We need to avoid clobbering | |
5999 | the base register with one of the registers in our modified | |
6000 | register list, but just using a different register can't work in | |
6001 | all cases, e.g.: | |
6002 | ||
6003 | ldm r14!, {r0-r13,pc} | |
6004 | ||
6005 | which would need to be rewritten as: | |
6006 | ||
6007 | ldm rN!, {r0-r14} | |
6008 | ||
6009 | but that can't work, because there's no free register for N. | |
6010 | ||
6011 | Solve this by turning off the writeback bit, and emulating | |
6012 | writeback manually in the cleanup routine. */ | |
6013 | ||
6014 | if (writeback) | |
6015 | insn &= ~(1 << 21); | |
6016 | ||
6017 | new_regmask = (1 << num_in_list) - 1; | |
6018 | ||
6019 | if (debug_displaced) | |
6020 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " | |
6021 | "{..., pc}: original reg list %.4x, modified " | |
6022 | "list %.4x\n"), rn, writeback ? "!" : "", | |
6023 | (int) insn & 0xffff, new_regmask); | |
6024 | ||
6025 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6026 | ||
6027 | dsc->cleanup = &cleanup_block_load_pc; | |
6028 | } | |
6029 | } | |
6030 | else | |
6031 | { | |
6032 | /* STM of a list of registers which includes PC. Run the instruction | |
6033 | as-is, but out of line: this will store the wrong value for the PC, | |
6034 | so we must manually fix up the memory in the cleanup routine. | |
6035 | Doing things this way has the advantage that we can auto-detect | |
6036 | the offset of the PC write (which is architecture-dependent) in | |
6037 | the cleanup routine. */ | |
6038 | dsc->modinsn[0] = insn; | |
6039 | ||
6040 | dsc->cleanup = &cleanup_block_store_pc; | |
6041 | } | |
6042 | ||
6043 | return 0; | |
6044 | } | |
6045 | ||
34518530 YQ |
6046 | static int |
6047 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6048 | struct regcache *regs, | |
6049 | struct displaced_step_closure *dsc) | |
cca44b1b | 6050 | { |
34518530 YQ |
6051 | int rn = bits (insn1, 0, 3); |
6052 | int load = bit (insn1, 4); | |
6053 | int writeback = bit (insn1, 5); | |
cca44b1b | 6054 | |
34518530 YQ |
6055 | /* Block transfers which don't mention PC can be run directly |
6056 | out-of-line. */ | |
6057 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
6058 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 6059 | |
34518530 YQ |
6060 | if (rn == ARM_PC_REGNUM) |
6061 | { | |
6062 | warning (_("displaced: Unpredictable LDM or STM with " | |
6063 | "base register r15")); | |
6064 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6065 | "unpredictable ldm/stm", dsc); | |
6066 | } | |
cca44b1b JB |
6067 | |
6068 | if (debug_displaced) | |
34518530 YQ |
6069 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " |
6070 | "%.4x%.4x\n", insn1, insn2); | |
cca44b1b | 6071 | |
34518530 YQ |
6072 | /* Clear bit 13, since it should be always zero. */ |
6073 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
6074 | dsc->u.block.rn = rn; | |
cca44b1b | 6075 | |
34518530 YQ |
6076 | dsc->u.block.load = load; |
6077 | dsc->u.block.user = 0; | |
6078 | dsc->u.block.increment = bit (insn1, 7); | |
6079 | dsc->u.block.before = bit (insn1, 8); | |
6080 | dsc->u.block.writeback = writeback; | |
6081 | dsc->u.block.cond = INST_AL; | |
6082 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6083 | |
34518530 YQ |
6084 | if (load) |
6085 | { | |
6086 | if (dsc->u.block.regmask == 0xffff) | |
6087 | { | |
6088 | /* This branch is impossible to happen. */ | |
6089 | gdb_assert (0); | |
6090 | } | |
6091 | else | |
6092 | { | |
6093 | unsigned int regmask = dsc->u.block.regmask; | |
6094 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; | |
6095 | unsigned int to = 0, from = 0, i, new_rn; | |
6096 | ||
6097 | for (i = 0; i < num_in_list; i++) | |
6098 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
6099 | ||
6100 | if (writeback) | |
6101 | insn1 &= ~(1 << 5); | |
6102 | ||
6103 | new_regmask = (1 << num_in_list) - 1; | |
6104 | ||
6105 | if (debug_displaced) | |
6106 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " | |
6107 | "{..., pc}: original reg list %.4x, modified " | |
6108 | "list %.4x\n"), rn, writeback ? "!" : "", | |
6109 | (int) dsc->u.block.regmask, new_regmask); | |
6110 | ||
6111 | dsc->modinsn[0] = insn1; | |
6112 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
6113 | dsc->numinsns = 2; | |
6114 | ||
6115 | dsc->cleanup = &cleanup_block_load_pc; | |
6116 | } | |
6117 | } | |
6118 | else | |
6119 | { | |
6120 | dsc->modinsn[0] = insn1; | |
6121 | dsc->modinsn[1] = insn2; | |
6122 | dsc->numinsns = 2; | |
6123 | dsc->cleanup = &cleanup_block_store_pc; | |
6124 | } | |
6125 | return 0; | |
6126 | } | |
6127 | ||
d9311bfa AT |
6128 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
6129 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
6130 | ||
6131 | ULONGEST | |
6132 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
6133 | int byte_order) | |
6134 | { | |
5f2dfcfd AT |
6135 | return read_memory_unsigned_integer (memaddr, len, |
6136 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
6137 | } |
6138 | ||
6139 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
6140 | ||
6141 | CORE_ADDR | |
6142 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
6143 | CORE_ADDR val) | |
6144 | { | |
6145 | return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val); | |
6146 | } | |
6147 | ||
6148 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
6149 | ||
e7cf25a8 YQ |
6150 | static CORE_ADDR |
6151 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, | |
6152 | CORE_ADDR pc) | |
d9311bfa | 6153 | { |
d9311bfa AT |
6154 | return 0; |
6155 | } | |
6156 | ||
6157 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
6158 | ||
6159 | int | |
6160 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
6161 | { | |
6162 | return arm_is_thumb (self->regcache); | |
6163 | } | |
6164 | ||
6165 | /* single_step() is called just before we want to resume the inferior, | |
6166 | if we want to single-step it but there is no hardware or kernel | |
6167 | single-step support. We find the target of the coming instructions | |
6168 | and breakpoint them. */ | |
6169 | ||
6170 | int | |
6171 | arm_software_single_step (struct frame_info *frame) | |
6172 | { | |
6173 | struct regcache *regcache = get_current_regcache (); | |
6174 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6175 | struct address_space *aspace = get_regcache_aspace (regcache); | |
6176 | struct arm_get_next_pcs next_pcs_ctx; | |
6177 | CORE_ADDR pc; | |
6178 | int i; | |
6179 | VEC (CORE_ADDR) *next_pcs = NULL; | |
6180 | struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); | |
6181 | ||
6182 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
6183 | &arm_get_next_pcs_ops, | |
6184 | gdbarch_byte_order (gdbarch), | |
6185 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 6186 | 0, |
d9311bfa AT |
6187 | regcache); |
6188 | ||
4d18591b | 6189 | next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
6190 | |
6191 | for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) | |
6192 | arm_insert_single_step_breakpoint (gdbarch, aspace, pc); | |
6193 | ||
6194 | do_cleanups (old_chain); | |
6195 | ||
6196 | return 1; | |
6197 | } | |
6198 | ||
34518530 YQ |
6199 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
6200 | for Linux, where some SVC instructions must be treated specially. */ | |
6201 | ||
6202 | static void | |
6203 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
6204 | struct displaced_step_closure *dsc) | |
6205 | { | |
6206 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
6207 | ||
6208 | if (debug_displaced) | |
6209 | fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at " | |
6210 | "%.8lx\n", (unsigned long) resume_addr); | |
6211 | ||
6212 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
6213 | } | |
6214 | ||
6215 | ||
6216 | /* Common copy routine for svc instruciton. */ | |
6217 | ||
6218 | static int | |
6219 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
6220 | struct displaced_step_closure *dsc) | |
6221 | { | |
6222 | /* Preparation: none. | |
6223 | Insn: unmodified svc. | |
6224 | Cleanup: pc <- insn_addr + insn_size. */ | |
6225 | ||
6226 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
6227 | instruction. */ | |
6228 | dsc->wrote_to_pc = 1; | |
6229 | ||
6230 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
6231 | if (dsc->u.svc.copy_svc_os) |
6232 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
6233 | else | |
6234 | { | |
6235 | dsc->cleanup = &cleanup_svc; | |
6236 | return 0; | |
6237 | } | |
34518530 YQ |
6238 | } |
6239 | ||
6240 | static int | |
6241 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
6242 | struct regcache *regs, struct displaced_step_closure *dsc) | |
6243 | { | |
6244 | ||
6245 | if (debug_displaced) | |
6246 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n", | |
6247 | (unsigned long) insn); | |
6248 | ||
6249 | dsc->modinsn[0] = insn; | |
6250 | ||
6251 | return install_svc (gdbarch, regs, dsc); | |
6252 | } | |
6253 | ||
6254 | static int | |
6255 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
6256 | struct regcache *regs, struct displaced_step_closure *dsc) | |
6257 | { | |
6258 | ||
6259 | if (debug_displaced) | |
6260 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n", | |
6261 | insn); | |
bd18283a | 6262 | |
34518530 YQ |
6263 | dsc->modinsn[0] = insn; |
6264 | ||
6265 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
6266 | } |
6267 | ||
6268 | /* Copy undefined instructions. */ | |
6269 | ||
6270 | static int | |
7ff120b4 YQ |
6271 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
6272 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6273 | { |
6274 | if (debug_displaced) | |
0963b4bd MS |
6275 | fprintf_unfiltered (gdb_stdlog, |
6276 | "displaced: copying undefined insn %.8lx\n", | |
cca44b1b JB |
6277 | (unsigned long) insn); |
6278 | ||
6279 | dsc->modinsn[0] = insn; | |
6280 | ||
6281 | return 0; | |
6282 | } | |
6283 | ||
34518530 YQ |
6284 | static int |
6285 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6286 | struct displaced_step_closure *dsc) | |
6287 | { | |
6288 | ||
6289 | if (debug_displaced) | |
6290 | fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn " | |
6291 | "%.4x %.4x\n", (unsigned short) insn1, | |
6292 | (unsigned short) insn2); | |
6293 | ||
6294 | dsc->modinsn[0] = insn1; | |
6295 | dsc->modinsn[1] = insn2; | |
6296 | dsc->numinsns = 2; | |
6297 | ||
6298 | return 0; | |
6299 | } | |
6300 | ||
cca44b1b JB |
6301 | /* Copy unpredictable instructions. */ |
6302 | ||
6303 | static int | |
7ff120b4 YQ |
6304 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
6305 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6306 | { |
6307 | if (debug_displaced) | |
6308 | fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn " | |
6309 | "%.8lx\n", (unsigned long) insn); | |
6310 | ||
6311 | dsc->modinsn[0] = insn; | |
6312 | ||
6313 | return 0; | |
6314 | } | |
6315 | ||
6316 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
6317 | the presentation in the ARM ARM. */ | |
6318 | ||
6319 | static int | |
7ff120b4 YQ |
6320 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
6321 | struct regcache *regs, | |
6322 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6323 | { |
6324 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
6325 | unsigned int rn = bits (insn, 16, 19); | |
6326 | ||
6327 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0) | |
7ff120b4 | 6328 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
cca44b1b | 6329 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1) |
7ff120b4 | 6330 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 6331 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 6332 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 6333 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
6334 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
6335 | dsc); | |
cca44b1b | 6336 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 6337 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6338 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 6339 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
6340 | else if ((op1 & 0x77) == 0x51) |
6341 | { | |
6342 | if (rn != 0xf) | |
7ff120b4 | 6343 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 6344 | else |
7ff120b4 | 6345 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6346 | } |
6347 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 6348 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
6349 | else if (op1 == 0x57) |
6350 | switch (op2) | |
6351 | { | |
7ff120b4 YQ |
6352 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
6353 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
6354 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
6355 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
6356 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
6357 | } |
6358 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 6359 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6360 | else if ((op2 & 0x1) == 0x0) |
6361 | switch (op1 & ~0x80) | |
6362 | { | |
6363 | case 0x61: | |
7ff120b4 | 6364 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6365 | case 0x65: |
7ff120b4 | 6366 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b JB |
6367 | case 0x71: case 0x75: |
6368 | /* pld/pldw reg. */ | |
7ff120b4 | 6369 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6370 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 6371 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 6372 | default: |
7ff120b4 | 6373 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6374 | } |
6375 | else | |
7ff120b4 | 6376 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
6377 | } |
6378 | ||
6379 | static int | |
7ff120b4 YQ |
6380 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
6381 | struct regcache *regs, | |
6382 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6383 | { |
6384 | if (bit (insn, 27) == 0) | |
7ff120b4 | 6385 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6386 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
6387 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
6388 | { | |
6389 | case 0x0: case 0x2: | |
7ff120b4 | 6390 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
6391 | |
6392 | case 0x1: case 0x3: | |
7ff120b4 | 6393 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
6394 | |
6395 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 6396 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6397 | |
6398 | case 0x8: | |
6399 | switch ((insn & 0xe00000) >> 21) | |
6400 | { | |
6401 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
6402 | /* stc/stc2. */ | |
7ff120b4 | 6403 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6404 | |
6405 | case 0x2: | |
7ff120b4 | 6406 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
6407 | |
6408 | default: | |
7ff120b4 | 6409 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6410 | } |
6411 | ||
6412 | case 0x9: | |
6413 | { | |
6414 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
6415 | switch ((insn & 0xe00000) >> 21) | |
6416 | { | |
6417 | case 0x1: case 0x3: | |
6418 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
6419 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
6420 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
6421 | |
6422 | case 0x2: | |
7ff120b4 | 6423 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6424 | |
6425 | case 0x4: case 0x5: case 0x6: case 0x7: | |
6426 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
6427 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
6428 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
6429 | |
6430 | default: | |
7ff120b4 | 6431 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6432 | } |
6433 | } | |
6434 | ||
6435 | case 0xa: | |
7ff120b4 | 6436 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
6437 | |
6438 | case 0xb: | |
6439 | if (bits (insn, 16, 19) == 0xf) | |
6440 | /* ldc/ldc2 lit. */ | |
7ff120b4 | 6441 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6442 | else |
7ff120b4 | 6443 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6444 | |
6445 | case 0xc: | |
6446 | if (bit (insn, 4)) | |
7ff120b4 | 6447 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6448 | else |
7ff120b4 | 6449 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6450 | |
6451 | case 0xd: | |
6452 | if (bit (insn, 4)) | |
7ff120b4 | 6453 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6454 | else |
7ff120b4 | 6455 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6456 | |
6457 | default: | |
7ff120b4 | 6458 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6459 | } |
6460 | } | |
6461 | ||
6462 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
6463 | ||
6464 | static int | |
7ff120b4 YQ |
6465 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
6466 | struct regcache *regs, | |
6467 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6468 | { |
6469 | unsigned int op2 = bits (insn, 4, 6); | |
6470 | unsigned int op = bits (insn, 21, 22); | |
6471 | unsigned int op1 = bits (insn, 16, 19); | |
6472 | ||
6473 | switch (op2) | |
6474 | { | |
6475 | case 0x0: | |
7ff120b4 | 6476 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
6477 | |
6478 | case 0x1: | |
6479 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 6480 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6481 | else if (op == 0x3) |
7ff120b4 | 6482 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 6483 | else |
7ff120b4 | 6484 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6485 | |
6486 | case 0x2: | |
6487 | if (op == 0x1) | |
6488 | /* Not really supported. */ | |
7ff120b4 | 6489 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 6490 | else |
7ff120b4 | 6491 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6492 | |
6493 | case 0x3: | |
6494 | if (op == 0x1) | |
7ff120b4 | 6495 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 6496 | regs, dsc); /* blx register. */ |
cca44b1b | 6497 | else |
7ff120b4 | 6498 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6499 | |
6500 | case 0x5: | |
7ff120b4 | 6501 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
6502 | |
6503 | case 0x7: | |
6504 | if (op == 0x1) | |
7ff120b4 | 6505 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b JB |
6506 | else if (op == 0x3) |
6507 | /* Not really supported. */ | |
7ff120b4 | 6508 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
cca44b1b JB |
6509 | |
6510 | default: | |
7ff120b4 | 6511 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6512 | } |
6513 | } | |
6514 | ||
6515 | static int | |
7ff120b4 YQ |
6516 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
6517 | struct regcache *regs, | |
6518 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6519 | { |
6520 | if (bit (insn, 25)) | |
6521 | switch (bits (insn, 20, 24)) | |
6522 | { | |
6523 | case 0x10: | |
7ff120b4 | 6524 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
6525 | |
6526 | case 0x14: | |
7ff120b4 | 6527 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
6528 | |
6529 | case 0x12: case 0x16: | |
7ff120b4 | 6530 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
6531 | |
6532 | default: | |
7ff120b4 | 6533 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6534 | } |
6535 | else | |
6536 | { | |
6537 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
6538 | ||
6539 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 6540 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6541 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 6542 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6543 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 6544 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 6545 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 6546 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 6547 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 6548 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 6549 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 6550 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 6551 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 6552 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
6553 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
6554 | dsc); | |
cca44b1b JB |
6555 | } |
6556 | ||
6557 | /* Should be unreachable. */ | |
6558 | return 1; | |
6559 | } | |
6560 | ||
6561 | static int | |
7ff120b4 YQ |
6562 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
6563 | struct regcache *regs, | |
6564 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6565 | { |
6566 | int a = bit (insn, 25), b = bit (insn, 4); | |
6567 | uint32_t op1 = bits (insn, 20, 24); | |
6568 | int rn_f = bits (insn, 16, 19) == 0xf; | |
6569 | ||
6570 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
6571 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 6572 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
6573 | else if ((!a && (op1 & 0x17) == 0x02) |
6574 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 6575 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
6576 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
6577 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 6578 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
6579 | else if ((!a && (op1 & 0x17) == 0x03) |
6580 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 6581 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
6582 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
6583 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 6584 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
6585 | else if ((!a && (op1 & 0x17) == 0x06) |
6586 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 6587 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
6588 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
6589 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 6590 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
6591 | else if ((!a && (op1 & 0x17) == 0x07) |
6592 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 6593 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
6594 | |
6595 | /* Should be unreachable. */ | |
6596 | return 1; | |
6597 | } | |
6598 | ||
6599 | static int | |
7ff120b4 YQ |
6600 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
6601 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6602 | { |
6603 | switch (bits (insn, 20, 24)) | |
6604 | { | |
6605 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 6606 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
6607 | |
6608 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 6609 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
6610 | |
6611 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
6612 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 6613 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
6614 | "decode/pack/unpack/saturate/reverse", dsc); |
6615 | ||
6616 | case 0x18: | |
6617 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
6618 | { | |
6619 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 6620 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 6621 | else |
7ff120b4 | 6622 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
6623 | } |
6624 | else | |
7ff120b4 | 6625 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6626 | |
6627 | case 0x1a: case 0x1b: | |
6628 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6629 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 6630 | else |
7ff120b4 | 6631 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6632 | |
6633 | case 0x1c: case 0x1d: | |
6634 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
6635 | { | |
6636 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 6637 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 6638 | else |
7ff120b4 | 6639 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
6640 | } |
6641 | else | |
7ff120b4 | 6642 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6643 | |
6644 | case 0x1e: case 0x1f: | |
6645 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6646 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 6647 | else |
7ff120b4 | 6648 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6649 | } |
6650 | ||
6651 | /* Should be unreachable. */ | |
6652 | return 1; | |
6653 | } | |
6654 | ||
6655 | static int | |
7ff120b4 YQ |
6656 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn, |
6657 | struct regcache *regs, | |
6658 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6659 | { |
6660 | if (bit (insn, 25)) | |
7ff120b4 | 6661 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 6662 | else |
7ff120b4 | 6663 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6664 | } |
6665 | ||
6666 | static int | |
7ff120b4 YQ |
6667 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
6668 | struct regcache *regs, | |
6669 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6670 | { |
6671 | unsigned int opcode = bits (insn, 20, 24); | |
6672 | ||
6673 | switch (opcode) | |
6674 | { | |
6675 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 6676 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
6677 | |
6678 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
6679 | case 0x12: case 0x16: | |
7ff120b4 | 6680 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
6681 | |
6682 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
6683 | case 0x13: case 0x17: | |
7ff120b4 | 6684 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
6685 | |
6686 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6687 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6688 | /* Note: no writeback for these instructions. Bit 25 will always be | |
6689 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 6690 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6691 | } |
6692 | ||
6693 | /* Should be unreachable. */ | |
6694 | return 1; | |
6695 | } | |
6696 | ||
34518530 YQ |
6697 | /* Decode shifted register instructions. */ |
6698 | ||
6699 | static int | |
6700 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
6701 | uint16_t insn2, struct regcache *regs, | |
6702 | struct displaced_step_closure *dsc) | |
6703 | { | |
6704 | /* PC is only allowed to be used in instruction MOV. */ | |
6705 | ||
6706 | unsigned int op = bits (insn1, 5, 8); | |
6707 | unsigned int rn = bits (insn1, 0, 3); | |
6708 | ||
6709 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
6710 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
6711 | else | |
6712 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6713 | "dp (shift reg)", dsc); | |
6714 | } | |
6715 | ||
6716 | ||
6717 | /* Decode extension register load/store. Exactly the same as | |
6718 | arm_decode_ext_reg_ld_st. */ | |
6719 | ||
6720 | static int | |
6721 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
6722 | uint16_t insn2, struct regcache *regs, | |
6723 | struct displaced_step_closure *dsc) | |
6724 | { | |
6725 | unsigned int opcode = bits (insn1, 4, 8); | |
6726 | ||
6727 | switch (opcode) | |
6728 | { | |
6729 | case 0x04: case 0x05: | |
6730 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6731 | "vfp/neon vmov", dsc); | |
6732 | ||
6733 | case 0x08: case 0x0c: /* 01x00 */ | |
6734 | case 0x0a: case 0x0e: /* 01x10 */ | |
6735 | case 0x12: case 0x16: /* 10x10 */ | |
6736 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6737 | "vfp/neon vstm/vpush", dsc); | |
6738 | ||
6739 | case 0x09: case 0x0d: /* 01x01 */ | |
6740 | case 0x0b: case 0x0f: /* 01x11 */ | |
6741 | case 0x13: case 0x17: /* 10x11 */ | |
6742 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6743 | "vfp/neon vldm/vpop", dsc); | |
6744 | ||
6745 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6746 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6747 | "vstr", dsc); | |
6748 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6749 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
6750 | } | |
6751 | ||
6752 | /* Should be unreachable. */ | |
6753 | return 1; | |
6754 | } | |
6755 | ||
cca44b1b | 6756 | static int |
7ff120b4 YQ |
6757 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, |
6758 | struct regcache *regs, struct displaced_step_closure *dsc) | |
cca44b1b JB |
6759 | { |
6760 | unsigned int op1 = bits (insn, 20, 25); | |
6761 | int op = bit (insn, 4); | |
6762 | unsigned int coproc = bits (insn, 8, 11); | |
6763 | unsigned int rn = bits (insn, 16, 19); | |
6764 | ||
6765 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 6766 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6767 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
6768 | && (coproc & 0xe) != 0xa) | |
6769 | /* stc/stc2. */ | |
7ff120b4 | 6770 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6771 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
6772 | && (coproc & 0xe) != 0xa) | |
6773 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 6774 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6775 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 6776 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 6777 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 6778 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 6779 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6780 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 6781 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6782 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6783 | else if ((op1 & 0x30) == 0x20 && !op) |
6784 | { | |
6785 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 6786 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 6787 | else |
7ff120b4 | 6788 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6789 | } |
6790 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 6791 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 6792 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6793 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6794 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6795 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6796 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 6797 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 6798 | else |
7ff120b4 | 6799 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
6800 | } |
6801 | ||
34518530 YQ |
6802 | static int |
6803 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
6804 | uint16_t insn2, struct regcache *regs, | |
6805 | struct displaced_step_closure *dsc) | |
6806 | { | |
6807 | unsigned int coproc = bits (insn2, 8, 11); | |
6808 | unsigned int op1 = bits (insn1, 4, 9); | |
6809 | unsigned int bit_5_8 = bits (insn1, 5, 8); | |
6810 | unsigned int bit_9 = bit (insn1, 9); | |
6811 | unsigned int bit_4 = bit (insn1, 4); | |
6812 | unsigned int rn = bits (insn1, 0, 3); | |
6813 | ||
6814 | if (bit_9 == 0) | |
6815 | { | |
6816 | if (bit_5_8 == 2) | |
6817 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6818 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
6819 | dsc); | |
6820 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
6821 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
6822 | else | |
6823 | { | |
6824 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
6825 | if ((coproc & 0xe) == 0xa) | |
6826 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
6827 | dsc); | |
6828 | else /* coproc is not 101x. */ | |
6829 | { | |
6830 | if (bit_4 == 0) /* STC/STC2. */ | |
6831 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6832 | "stc/stc2", dsc); | |
6833 | else /* LDC/LDC2 {literal, immeidate}. */ | |
6834 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, | |
6835 | regs, dsc); | |
6836 | } | |
6837 | } | |
6838 | } | |
6839 | else | |
6840 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
6841 | ||
6842 | return 0; | |
6843 | } | |
6844 | ||
6845 | static void | |
6846 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
6847 | struct displaced_step_closure *dsc, int rd) | |
6848 | { | |
6849 | /* ADR Rd, #imm | |
6850 | ||
6851 | Rewrite as: | |
6852 | ||
6853 | Preparation: Rd <- PC | |
6854 | Insn: ADD Rd, #imm | |
6855 | Cleanup: Null. | |
6856 | */ | |
6857 | ||
6858 | /* Rd <- PC */ | |
6859 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6860 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
6861 | } | |
6862 | ||
6863 | static int | |
6864 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
6865 | struct displaced_step_closure *dsc, | |
6866 | int rd, unsigned int imm) | |
6867 | { | |
6868 | ||
6869 | /* Encoding T2: ADDS Rd, #imm */ | |
6870 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
6871 | ||
6872 | install_pc_relative (gdbarch, regs, dsc, rd); | |
6873 | ||
6874 | return 0; | |
6875 | } | |
6876 | ||
6877 | static int | |
6878 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
6879 | struct regcache *regs, | |
6880 | struct displaced_step_closure *dsc) | |
6881 | { | |
6882 | unsigned int rd = bits (insn, 8, 10); | |
6883 | unsigned int imm8 = bits (insn, 0, 7); | |
6884 | ||
6885 | if (debug_displaced) | |
6886 | fprintf_unfiltered (gdb_stdlog, | |
6887 | "displaced: copying thumb adr r%d, #%d insn %.4x\n", | |
6888 | rd, imm8, insn); | |
6889 | ||
6890 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
6891 | } | |
6892 | ||
6893 | static int | |
6894 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
6895 | uint16_t insn2, struct regcache *regs, | |
6896 | struct displaced_step_closure *dsc) | |
6897 | { | |
6898 | unsigned int rd = bits (insn2, 8, 11); | |
6899 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
6900 | extract raw immediate encoding rather than computing immediate. When | |
6901 | generating ADD or SUB instruction, we can simply perform OR operation to | |
6902 | set immediate into ADD. */ | |
6903 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
6904 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
6905 | ||
6906 | if (debug_displaced) | |
6907 | fprintf_unfiltered (gdb_stdlog, | |
6908 | "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n", | |
6909 | rd, imm_i, imm_3_8, insn1, insn2); | |
6910 | ||
6911 | if (bit (insn1, 7)) /* Encoding T2 */ | |
6912 | { | |
6913 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
6914 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
6915 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6916 | } | |
6917 | else /* Encoding T3 */ | |
6918 | { | |
6919 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
6920 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
6921 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6922 | } | |
6923 | dsc->numinsns = 2; | |
6924 | ||
6925 | install_pc_relative (gdbarch, regs, dsc, rd); | |
6926 | ||
6927 | return 0; | |
6928 | } | |
6929 | ||
6930 | static int | |
6931 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1, | |
6932 | struct regcache *regs, | |
6933 | struct displaced_step_closure *dsc) | |
6934 | { | |
6935 | unsigned int rt = bits (insn1, 8, 10); | |
6936 | unsigned int pc; | |
6937 | int imm8 = (bits (insn1, 0, 7) << 2); | |
6938 | CORE_ADDR from = dsc->insn_addr; | |
6939 | ||
6940 | /* LDR Rd, #imm8 | |
6941 | ||
6942 | Rwrite as: | |
6943 | ||
6944 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
6945 | ||
6946 | Insn: LDR R0, [R2, R3]; | |
6947 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
6948 | ||
6949 | if (debug_displaced) | |
6950 | fprintf_unfiltered (gdb_stdlog, | |
6951 | "displaced: copying thumb ldr r%d [pc #%d]\n" | |
6952 | , rt, imm8); | |
6953 | ||
6954 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6955 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6956 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
6957 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6958 | /* The assembler calculates the required value of the offset from the | |
6959 | Align(PC,4) value of this instruction to the label. */ | |
6960 | pc = pc & 0xfffffffc; | |
6961 | ||
6962 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
6963 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
6964 | ||
6965 | dsc->rd = rt; | |
6966 | dsc->u.ldst.xfersize = 4; | |
6967 | dsc->u.ldst.rn = 0; | |
6968 | dsc->u.ldst.immed = 0; | |
6969 | dsc->u.ldst.writeback = 0; | |
6970 | dsc->u.ldst.restore_r4 = 0; | |
6971 | ||
6972 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
6973 | ||
6974 | dsc->cleanup = &cleanup_load; | |
6975 | ||
6976 | return 0; | |
6977 | } | |
6978 | ||
6979 | /* Copy Thumb cbnz/cbz insruction. */ | |
6980 | ||
6981 | static int | |
6982 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
6983 | struct regcache *regs, | |
6984 | struct displaced_step_closure *dsc) | |
6985 | { | |
6986 | int non_zero = bit (insn1, 11); | |
6987 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
6988 | CORE_ADDR from = dsc->insn_addr; | |
6989 | int rn = bits (insn1, 0, 2); | |
6990 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
6991 | ||
6992 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
6993 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
6994 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
6995 | condition is false, let it be, cleanup_branch will do nothing. */ | |
6996 | if (dsc->u.branch.cond) | |
6997 | { | |
6998 | dsc->u.branch.cond = INST_AL; | |
6999 | dsc->u.branch.dest = from + 4 + imm5; | |
7000 | } | |
7001 | else | |
7002 | dsc->u.branch.dest = from + 2; | |
7003 | ||
7004 | dsc->u.branch.link = 0; | |
7005 | dsc->u.branch.exchange = 0; | |
7006 | ||
7007 | if (debug_displaced) | |
7008 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]" | |
7009 | " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz", | |
7010 | rn, rn_val, insn1, dsc->u.branch.dest); | |
7011 | ||
7012 | dsc->modinsn[0] = THUMB_NOP; | |
7013 | ||
7014 | dsc->cleanup = &cleanup_branch; | |
7015 | return 0; | |
7016 | } | |
7017 | ||
7018 | /* Copy Table Branch Byte/Halfword */ | |
7019 | static int | |
7020 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7021 | uint16_t insn2, struct regcache *regs, | |
7022 | struct displaced_step_closure *dsc) | |
7023 | { | |
7024 | ULONGEST rn_val, rm_val; | |
7025 | int is_tbh = bit (insn2, 4); | |
7026 | CORE_ADDR halfwords = 0; | |
7027 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7028 | ||
7029 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7030 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7031 | ||
7032 | if (is_tbh) | |
7033 | { | |
7034 | gdb_byte buf[2]; | |
7035 | ||
7036 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7037 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7038 | } | |
7039 | else | |
7040 | { | |
7041 | gdb_byte buf[1]; | |
7042 | ||
7043 | target_read_memory (rn_val + rm_val, buf, 1); | |
7044 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7045 | } | |
7046 | ||
7047 | if (debug_displaced) | |
7048 | fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x" | |
7049 | " offset 0x%x\n", is_tbh ? "tbh" : "tbb", | |
7050 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7051 | (unsigned int) halfwords); | |
7052 | ||
7053 | dsc->u.branch.cond = INST_AL; | |
7054 | dsc->u.branch.link = 0; | |
7055 | dsc->u.branch.exchange = 0; | |
7056 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7057 | ||
7058 | dsc->cleanup = &cleanup_branch; | |
7059 | ||
7060 | return 0; | |
7061 | } | |
7062 | ||
7063 | static void | |
7064 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
7065 | struct displaced_step_closure *dsc) | |
7066 | { | |
7067 | /* PC <- r7 */ | |
7068 | int val = displaced_read_reg (regs, dsc, 7); | |
7069 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7070 | ||
7071 | /* r7 <- r8 */ | |
7072 | val = displaced_read_reg (regs, dsc, 8); | |
7073 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7074 | ||
7075 | /* r8 <- tmp[0] */ | |
7076 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7077 | ||
7078 | } | |
7079 | ||
7080 | static int | |
7081 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1, | |
7082 | struct regcache *regs, | |
7083 | struct displaced_step_closure *dsc) | |
7084 | { | |
7085 | dsc->u.block.regmask = insn1 & 0x00ff; | |
7086 | ||
7087 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
7088 | to : | |
7089 | ||
7090 | (1) register list is full, that is, r0-r7 are used. | |
7091 | Prepare: tmp[0] <- r8 | |
7092 | ||
7093 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
7094 | MOV r8, r7; Move value of r7 to r8; | |
7095 | POP {r7}; Store PC value into r7. | |
7096 | ||
7097 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
7098 | ||
7099 | (2) register list is not full, supposing there are N registers in | |
7100 | register list (except PC, 0 <= N <= 7). | |
7101 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
7102 | ||
7103 | POP {r0, r1, ...., rN}; | |
7104 | ||
7105 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
7106 | from tmp[] properly. | |
7107 | */ | |
7108 | if (debug_displaced) | |
7109 | fprintf_unfiltered (gdb_stdlog, | |
7110 | "displaced: copying thumb pop {%.8x, pc} insn %.4x\n", | |
7111 | dsc->u.block.regmask, insn1); | |
7112 | ||
7113 | if (dsc->u.block.regmask == 0xff) | |
7114 | { | |
7115 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
7116 | ||
7117 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
7118 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
7119 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
7120 | ||
7121 | dsc->numinsns = 3; | |
7122 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
7123 | } | |
7124 | else | |
7125 | { | |
7126 | unsigned int num_in_list = bitcount (dsc->u.block.regmask); | |
7127 | unsigned int new_regmask, bit = 1; | |
7128 | unsigned int to = 0, from = 0, i, new_rn; | |
7129 | ||
7130 | for (i = 0; i < num_in_list + 1; i++) | |
7131 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7132 | ||
7133 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
7134 | ||
7135 | if (debug_displaced) | |
7136 | fprintf_unfiltered (gdb_stdlog, _("displaced: POP " | |
7137 | "{..., pc}: original reg list %.4x," | |
7138 | " modified list %.4x\n"), | |
7139 | (int) dsc->u.block.regmask, new_regmask); | |
7140 | ||
7141 | dsc->u.block.regmask |= 0x8000; | |
7142 | dsc->u.block.writeback = 0; | |
7143 | dsc->u.block.cond = INST_AL; | |
7144 | ||
7145 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
7146 | ||
7147 | dsc->cleanup = &cleanup_block_load_pc; | |
7148 | } | |
7149 | ||
7150 | return 0; | |
7151 | } | |
7152 | ||
7153 | static void | |
7154 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7155 | struct regcache *regs, | |
7156 | struct displaced_step_closure *dsc) | |
7157 | { | |
7158 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
7159 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
7160 | int err = 0; | |
7161 | ||
7162 | /* 16-bit thumb instructions. */ | |
7163 | switch (op_bit_12_15) | |
7164 | { | |
7165 | /* Shift (imme), add, subtract, move and compare. */ | |
7166 | case 0: case 1: case 2: case 3: | |
7167 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7168 | "shift/add/sub/mov/cmp", | |
7169 | dsc); | |
7170 | break; | |
7171 | case 4: | |
7172 | switch (op_bit_10_11) | |
7173 | { | |
7174 | case 0: /* Data-processing */ | |
7175 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7176 | "data-processing", | |
7177 | dsc); | |
7178 | break; | |
7179 | case 1: /* Special data instructions and branch and exchange. */ | |
7180 | { | |
7181 | unsigned short op = bits (insn1, 7, 9); | |
7182 | if (op == 6 || op == 7) /* BX or BLX */ | |
7183 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
7184 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
7185 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
7186 | else | |
7187 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
7188 | dsc); | |
7189 | } | |
7190 | break; | |
7191 | default: /* LDR (literal) */ | |
7192 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
7193 | } | |
7194 | break; | |
7195 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
7196 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
7197 | break; | |
7198 | case 10: | |
7199 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
7200 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
7201 | else /* Generate SP-relative address */ | |
7202 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
7203 | break; | |
7204 | case 11: /* Misc 16-bit instructions */ | |
7205 | { | |
7206 | switch (bits (insn1, 8, 11)) | |
7207 | { | |
7208 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
7209 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
7210 | break; | |
7211 | case 12: case 13: /* POP */ | |
7212 | if (bit (insn1, 8)) /* PC is in register list. */ | |
7213 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
7214 | else | |
7215 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
7216 | break; | |
7217 | case 15: /* If-Then, and hints */ | |
7218 | if (bits (insn1, 0, 3)) | |
7219 | /* If-Then makes up to four following instructions conditional. | |
7220 | IT instruction itself is not conditional, so handle it as a | |
7221 | common unmodified instruction. */ | |
7222 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
7223 | dsc); | |
7224 | else | |
7225 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
7226 | break; | |
7227 | default: | |
7228 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
7229 | } | |
7230 | } | |
7231 | break; | |
7232 | case 12: | |
7233 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
7234 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
7235 | else /* Load multiple registers */ | |
7236 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
7237 | break; | |
7238 | case 13: /* Conditional branch and supervisor call */ | |
7239 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
7240 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7241 | else | |
7242 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
7243 | break; | |
7244 | case 14: /* Unconditional branch */ | |
7245 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7246 | break; | |
7247 | default: | |
7248 | err = 1; | |
7249 | } | |
7250 | ||
7251 | if (err) | |
7252 | internal_error (__FILE__, __LINE__, | |
7253 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
7254 | } | |
7255 | ||
7256 | static int | |
7257 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
7258 | uint16_t insn1, uint16_t insn2, | |
7259 | struct regcache *regs, | |
7260 | struct displaced_step_closure *dsc) | |
7261 | { | |
7262 | int rt = bits (insn2, 12, 15); | |
7263 | int rn = bits (insn1, 0, 3); | |
7264 | int op1 = bits (insn1, 7, 8); | |
7265 | int err = 0; | |
7266 | ||
7267 | switch (bits (insn1, 5, 6)) | |
7268 | { | |
7269 | case 0: /* Load byte and memory hints */ | |
7270 | if (rt == 0xf) /* PLD/PLI */ | |
7271 | { | |
7272 | if (rn == 0xf) | |
7273 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
7274 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
7275 | else | |
7276 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7277 | "pli/pld", dsc); | |
7278 | } | |
7279 | else | |
7280 | { | |
7281 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
7282 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7283 | 1); | |
7284 | else | |
7285 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7286 | "ldrb{reg, immediate}/ldrbt", | |
7287 | dsc); | |
7288 | } | |
7289 | ||
7290 | break; | |
7291 | case 1: /* Load halfword and memory hints. */ | |
7292 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
7293 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7294 | "pld/unalloc memhint", dsc); | |
7295 | else | |
7296 | { | |
7297 | if (rn == 0xf) | |
7298 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7299 | 2); | |
7300 | else | |
7301 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7302 | "ldrh/ldrht", dsc); | |
7303 | } | |
7304 | break; | |
7305 | case 2: /* Load word */ | |
7306 | { | |
7307 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
7308 | ||
7309 | if (rn == 0xf) | |
7310 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
7311 | else if (op1 == 0x1) /* Encoding T3 */ | |
7312 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
7313 | 0, 1); | |
7314 | else /* op1 == 0x0 */ | |
7315 | { | |
7316 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
7317 | /* LDR (immediate) */ | |
7318 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7319 | dsc, bit (insn2, 8), 1); | |
7320 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
7321 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7322 | "ldrt", dsc); | |
7323 | else | |
7324 | /* LDR (register) */ | |
7325 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7326 | dsc, 0, 0); | |
7327 | } | |
7328 | break; | |
7329 | } | |
7330 | default: | |
7331 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7332 | break; | |
7333 | } | |
7334 | return 0; | |
7335 | } | |
7336 | ||
7337 | static void | |
7338 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7339 | uint16_t insn2, struct regcache *regs, | |
7340 | struct displaced_step_closure *dsc) | |
7341 | { | |
7342 | int err = 0; | |
7343 | unsigned short op = bit (insn2, 15); | |
7344 | unsigned int op1 = bits (insn1, 11, 12); | |
7345 | ||
7346 | switch (op1) | |
7347 | { | |
7348 | case 1: | |
7349 | { | |
7350 | switch (bits (insn1, 9, 10)) | |
7351 | { | |
7352 | case 0: | |
7353 | if (bit (insn1, 6)) | |
7354 | { | |
7355 | /* Load/store {dual, execlusive}, table branch. */ | |
7356 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 | |
7357 | && bits (insn2, 5, 7) == 0) | |
7358 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
7359 | dsc); | |
7360 | else | |
7361 | /* PC is not allowed to use in load/store {dual, exclusive} | |
7362 | instructions. */ | |
7363 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7364 | "load/store dual/ex", dsc); | |
7365 | } | |
7366 | else /* load/store multiple */ | |
7367 | { | |
7368 | switch (bits (insn1, 7, 8)) | |
7369 | { | |
7370 | case 0: case 3: /* SRS, RFE */ | |
7371 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7372 | "srs/rfe", dsc); | |
7373 | break; | |
7374 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
7375 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
7376 | break; | |
7377 | } | |
7378 | } | |
7379 | break; | |
7380 | ||
7381 | case 1: | |
7382 | /* Data-processing (shift register). */ | |
7383 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
7384 | dsc); | |
7385 | break; | |
7386 | default: /* Coprocessor instructions. */ | |
7387 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7388 | break; | |
7389 | } | |
7390 | break; | |
7391 | } | |
7392 | case 2: /* op1 = 2 */ | |
7393 | if (op) /* Branch and misc control. */ | |
7394 | { | |
7395 | if (bit (insn2, 14) /* BLX/BL */ | |
7396 | || bit (insn2, 12) /* Unconditional branch */ | |
7397 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
7398 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
7399 | else | |
7400 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7401 | "misc ctrl", dsc); | |
7402 | } | |
7403 | else | |
7404 | { | |
7405 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
7406 | { | |
7407 | int op = bits (insn1, 4, 8); | |
7408 | int rn = bits (insn1, 0, 3); | |
7409 | if ((op == 0 || op == 0xa) && rn == 0xf) | |
7410 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, | |
7411 | regs, dsc); | |
7412 | else | |
7413 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7414 | "dp/pb", dsc); | |
7415 | } | |
7416 | else /* Data processing (modified immeidate) */ | |
7417 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7418 | "dp/mi", dsc); | |
7419 | } | |
7420 | break; | |
7421 | case 3: /* op1 = 3 */ | |
7422 | switch (bits (insn1, 9, 10)) | |
7423 | { | |
7424 | case 0: | |
7425 | if (bit (insn1, 4)) | |
7426 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
7427 | regs, dsc); | |
7428 | else /* NEON Load/Store and Store single data item */ | |
7429 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7430 | "neon elt/struct load/store", | |
7431 | dsc); | |
7432 | break; | |
7433 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
7434 | switch (bits (insn1, 7, 8)) | |
7435 | { | |
7436 | case 0: case 1: /* Data processing (register) */ | |
7437 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7438 | "dp(reg)", dsc); | |
7439 | break; | |
7440 | case 2: /* Multiply and absolute difference */ | |
7441 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7442 | "mul/mua/diff", dsc); | |
7443 | break; | |
7444 | case 3: /* Long multiply and divide */ | |
7445 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7446 | "lmul/lmua", dsc); | |
7447 | break; | |
7448 | } | |
7449 | break; | |
7450 | default: /* Coprocessor instructions */ | |
7451 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7452 | break; | |
7453 | } | |
7454 | break; | |
7455 | default: | |
7456 | err = 1; | |
7457 | } | |
7458 | ||
7459 | if (err) | |
7460 | internal_error (__FILE__, __LINE__, | |
7461 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
7462 | ||
7463 | } | |
7464 | ||
b434a28f YQ |
7465 | static void |
7466 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
7467 | CORE_ADDR to, struct regcache *regs, | |
7468 | struct displaced_step_closure *dsc) | |
7469 | { | |
34518530 YQ |
7470 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7471 | uint16_t insn1 | |
7472 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
7473 | ||
7474 | if (debug_displaced) | |
7475 | fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x " | |
7476 | "at %.8lx\n", insn1, (unsigned long) from); | |
7477 | ||
7478 | dsc->is_thumb = 1; | |
7479 | dsc->insn_size = thumb_insn_size (insn1); | |
7480 | if (thumb_insn_size (insn1) == 4) | |
7481 | { | |
7482 | uint16_t insn2 | |
7483 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
7484 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
7485 | } | |
7486 | else | |
7487 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
7488 | } |
7489 | ||
cca44b1b | 7490 | void |
b434a28f YQ |
7491 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
7492 | CORE_ADDR to, struct regcache *regs, | |
cca44b1b JB |
7493 | struct displaced_step_closure *dsc) |
7494 | { | |
7495 | int err = 0; | |
b434a28f YQ |
7496 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7497 | uint32_t insn; | |
cca44b1b JB |
7498 | |
7499 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
7500 | here and override below if/when necessary. */ | |
7501 | dsc->numinsns = 1; | |
7502 | dsc->insn_addr = from; | |
7503 | dsc->scratch_base = to; | |
7504 | dsc->cleanup = NULL; | |
7505 | dsc->wrote_to_pc = 0; | |
7506 | ||
b434a28f YQ |
7507 | if (!displaced_in_arm_mode (regs)) |
7508 | return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc); | |
7509 | ||
4db71c0b YQ |
7510 | dsc->is_thumb = 0; |
7511 | dsc->insn_size = 4; | |
b434a28f YQ |
7512 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
7513 | if (debug_displaced) | |
7514 | fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " | |
7515 | "at %.8lx\n", (unsigned long) insn, | |
7516 | (unsigned long) from); | |
7517 | ||
cca44b1b | 7518 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 7519 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7520 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
7521 | { | |
7522 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 7523 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7524 | break; |
7525 | ||
7526 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 7527 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7528 | break; |
7529 | ||
7530 | case 0x7: | |
7ff120b4 | 7531 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
7532 | break; |
7533 | ||
7534 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 7535 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7536 | break; |
7537 | ||
7538 | case 0xc: case 0xd: case 0xe: case 0xf: | |
7ff120b4 | 7539 | err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc); |
cca44b1b JB |
7540 | break; |
7541 | } | |
7542 | ||
7543 | if (err) | |
7544 | internal_error (__FILE__, __LINE__, | |
7545 | _("arm_process_displaced_insn: Instruction decode error")); | |
7546 | } | |
7547 | ||
7548 | /* Actually set up the scratch space for a displaced instruction. */ | |
7549 | ||
7550 | void | |
7551 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
7552 | CORE_ADDR to, struct displaced_step_closure *dsc) | |
7553 | { | |
7554 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4db71c0b | 7555 | unsigned int i, len, offset; |
cca44b1b | 7556 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 7557 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 7558 | const gdb_byte *bkp_insn; |
cca44b1b | 7559 | |
4db71c0b | 7560 | offset = 0; |
cca44b1b JB |
7561 | /* Poke modified instruction(s). */ |
7562 | for (i = 0; i < dsc->numinsns; i++) | |
7563 | { | |
7564 | if (debug_displaced) | |
4db71c0b YQ |
7565 | { |
7566 | fprintf_unfiltered (gdb_stdlog, "displaced: writing insn "); | |
7567 | if (size == 4) | |
7568 | fprintf_unfiltered (gdb_stdlog, "%.8lx", | |
7569 | dsc->modinsn[i]); | |
7570 | else if (size == 2) | |
7571 | fprintf_unfiltered (gdb_stdlog, "%.4x", | |
7572 | (unsigned short)dsc->modinsn[i]); | |
7573 | ||
7574 | fprintf_unfiltered (gdb_stdlog, " at %.8lx\n", | |
7575 | (unsigned long) to + offset); | |
7576 | ||
7577 | } | |
7578 | write_memory_unsigned_integer (to + offset, size, | |
7579 | byte_order_for_code, | |
cca44b1b | 7580 | dsc->modinsn[i]); |
4db71c0b YQ |
7581 | offset += size; |
7582 | } | |
7583 | ||
7584 | /* Choose the correct breakpoint instruction. */ | |
7585 | if (dsc->is_thumb) | |
7586 | { | |
7587 | bkp_insn = tdep->thumb_breakpoint; | |
7588 | len = tdep->thumb_breakpoint_size; | |
7589 | } | |
7590 | else | |
7591 | { | |
7592 | bkp_insn = tdep->arm_breakpoint; | |
7593 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
7594 | } |
7595 | ||
7596 | /* Put breakpoint afterwards. */ | |
4db71c0b | 7597 | write_memory (to + offset, bkp_insn, len); |
cca44b1b JB |
7598 | |
7599 | if (debug_displaced) | |
7600 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
7601 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
7602 | } | |
7603 | ||
7604 | /* Entry point for copying an instruction into scratch space for displaced | |
7605 | stepping. */ | |
7606 | ||
7607 | struct displaced_step_closure * | |
7608 | arm_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
7609 | CORE_ADDR from, CORE_ADDR to, | |
7610 | struct regcache *regs) | |
7611 | { | |
8d749320 SM |
7612 | struct displaced_step_closure *dsc = XNEW (struct displaced_step_closure); |
7613 | ||
b434a28f | 7614 | arm_process_displaced_insn (gdbarch, from, to, regs, dsc); |
cca44b1b JB |
7615 | arm_displaced_init_closure (gdbarch, from, to, dsc); |
7616 | ||
7617 | return dsc; | |
7618 | } | |
7619 | ||
7620 | /* Entry point for cleaning things up after a displaced instruction has been | |
7621 | single-stepped. */ | |
7622 | ||
7623 | void | |
7624 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
7625 | struct displaced_step_closure *dsc, | |
7626 | CORE_ADDR from, CORE_ADDR to, | |
7627 | struct regcache *regs) | |
7628 | { | |
7629 | if (dsc->cleanup) | |
7630 | dsc->cleanup (gdbarch, regs, dsc); | |
7631 | ||
7632 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
7633 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
7634 | dsc->insn_addr + dsc->insn_size); | |
7635 | ||
cca44b1b JB |
7636 | } |
7637 | ||
7638 | #include "bfd-in2.h" | |
7639 | #include "libcoff.h" | |
7640 | ||
7641 | static int | |
7642 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
7643 | { | |
9a3c8263 | 7644 | struct gdbarch *gdbarch = (struct gdbarch *) info->application_data; |
9779414d DJ |
7645 | |
7646 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
7647 | { |
7648 | static asymbol *asym; | |
7649 | static combined_entry_type ce; | |
7650 | static struct coff_symbol_struct csym; | |
7651 | static struct bfd fake_bfd; | |
7652 | static bfd_target fake_target; | |
7653 | ||
7654 | if (csym.native == NULL) | |
7655 | { | |
7656 | /* Create a fake symbol vector containing a Thumb symbol. | |
7657 | This is solely so that the code in print_insn_little_arm() | |
7658 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
7659 | the presence of a Thumb symbol and switch to decoding | |
7660 | Thumb instructions. */ | |
7661 | ||
7662 | fake_target.flavour = bfd_target_coff_flavour; | |
7663 | fake_bfd.xvec = &fake_target; | |
7664 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
7665 | csym.native = &ce; | |
7666 | csym.symbol.the_bfd = &fake_bfd; | |
7667 | csym.symbol.name = "fake"; | |
7668 | asym = (asymbol *) & csym; | |
7669 | } | |
7670 | ||
7671 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
7672 | info->symbols = &asym; | |
7673 | } | |
7674 | else | |
7675 | info->symbols = NULL; | |
7676 | ||
7677 | if (info->endian == BFD_ENDIAN_BIG) | |
7678 | return print_insn_big_arm (memaddr, info); | |
7679 | else | |
7680 | return print_insn_little_arm (memaddr, info); | |
7681 | } | |
7682 | ||
7683 | /* The following define instruction sequences that will cause ARM | |
7684 | cpu's to take an undefined instruction trap. These are used to | |
7685 | signal a breakpoint to GDB. | |
7686 | ||
7687 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
7688 | modes. A different instruction is required for each mode. The ARM | |
7689 | cpu's can also be big or little endian. Thus four different | |
7690 | instructions are needed to support all cases. | |
7691 | ||
7692 | Note: ARMv4 defines several new instructions that will take the | |
7693 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
7694 | not in fact add the new instructions. The new undefined | |
7695 | instructions in ARMv4 are all instructions that had no defined | |
7696 | behaviour in earlier chips. There is no guarantee that they will | |
7697 | raise an exception, but may be treated as NOP's. In practice, it | |
7698 | may only safe to rely on instructions matching: | |
7699 | ||
7700 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
7701 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
7702 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
7703 | ||
0963b4bd | 7704 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
7705 | following use a condition predicate of ALWAYS so it is always TRUE. |
7706 | ||
7707 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
7708 | and NetBSD all use a software interrupt rather than an undefined | |
7709 | instruction to force a trap. This can be handled by by the | |
7710 | abi-specific code during establishment of the gdbarch vector. */ | |
7711 | ||
7712 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
7713 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
7714 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
7715 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
7716 | ||
948f8e3d PA |
7717 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
7718 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
7719 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
7720 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b JB |
7721 | |
7722 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses | |
7723 | the program counter value to determine whether a 16-bit or 32-bit | |
7724 | breakpoint should be used. It returns a pointer to a string of | |
7725 | bytes that encode a breakpoint instruction, stores the length of | |
7726 | the string to *lenptr, and adjusts the program counter (if | |
7727 | necessary) to point to the actual memory location where the | |
7728 | breakpoint should be inserted. */ | |
7729 | ||
7730 | static const unsigned char * | |
7731 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) | |
7732 | { | |
7733 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
177321bd | 7734 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 7735 | |
9779414d | 7736 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
7737 | { |
7738 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
7739 | |
7740 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
7741 | check whether we are replacing a 32-bit instruction. */ | |
7742 | if (tdep->thumb2_breakpoint != NULL) | |
7743 | { | |
7744 | gdb_byte buf[2]; | |
7745 | if (target_read_memory (*pcptr, buf, 2) == 0) | |
7746 | { | |
7747 | unsigned short inst1; | |
7748 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
db24da6d | 7749 | if (thumb_insn_size (inst1) == 4) |
177321bd DJ |
7750 | { |
7751 | *lenptr = tdep->thumb2_breakpoint_size; | |
7752 | return tdep->thumb2_breakpoint; | |
7753 | } | |
7754 | } | |
7755 | } | |
7756 | ||
cca44b1b JB |
7757 | *lenptr = tdep->thumb_breakpoint_size; |
7758 | return tdep->thumb_breakpoint; | |
7759 | } | |
7760 | else | |
7761 | { | |
7762 | *lenptr = tdep->arm_breakpoint_size; | |
7763 | return tdep->arm_breakpoint; | |
7764 | } | |
7765 | } | |
7766 | ||
177321bd DJ |
7767 | static void |
7768 | arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
7769 | int *kindptr) | |
7770 | { | |
177321bd DJ |
7771 | arm_breakpoint_from_pc (gdbarch, pcptr, kindptr); |
7772 | ||
9779414d | 7773 | if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4) |
177321bd DJ |
7774 | /* The documented magic value for a 32-bit Thumb-2 breakpoint, so |
7775 | that this is not confused with a 32-bit ARM breakpoint. */ | |
7776 | *kindptr = 3; | |
7777 | } | |
7778 | ||
cca44b1b JB |
7779 | /* Extract from an array REGBUF containing the (raw) register state a |
7780 | function return value of type TYPE, and copy that, in virtual | |
7781 | format, into VALBUF. */ | |
7782 | ||
7783 | static void | |
7784 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
7785 | gdb_byte *valbuf) | |
7786 | { | |
7787 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
7788 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7789 | ||
7790 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
7791 | { | |
7792 | switch (gdbarch_tdep (gdbarch)->fp_model) | |
7793 | { | |
7794 | case ARM_FLOAT_FPA: | |
7795 | { | |
7796 | /* The value is in register F0 in internal format. We need to | |
7797 | extract the raw value and then convert it to the desired | |
7798 | internal type. */ | |
7799 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; | |
7800 | ||
7801 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
7802 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
7803 | valbuf, gdbarch_byte_order (gdbarch)); | |
7804 | } | |
7805 | break; | |
7806 | ||
7807 | case ARM_FLOAT_SOFT_FPA: | |
7808 | case ARM_FLOAT_SOFT_VFP: | |
7809 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
7810 | not using the VFP ABI code. */ | |
7811 | case ARM_FLOAT_VFP: | |
7812 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); | |
7813 | if (TYPE_LENGTH (type) > 4) | |
7814 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7815 | valbuf + INT_REGISTER_SIZE); | |
7816 | break; | |
7817 | ||
7818 | default: | |
0963b4bd MS |
7819 | internal_error (__FILE__, __LINE__, |
7820 | _("arm_extract_return_value: " | |
7821 | "Floating point model not supported")); | |
cca44b1b JB |
7822 | break; |
7823 | } | |
7824 | } | |
7825 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
7826 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
7827 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
7828 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
7829 | || TYPE_CODE (type) == TYPE_CODE_REF | |
7830 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
7831 | { | |
b021a221 MS |
7832 | /* If the type is a plain integer, then the access is |
7833 | straight-forward. Otherwise we have to play around a bit | |
7834 | more. */ | |
cca44b1b JB |
7835 | int len = TYPE_LENGTH (type); |
7836 | int regno = ARM_A1_REGNUM; | |
7837 | ULONGEST tmp; | |
7838 | ||
7839 | while (len > 0) | |
7840 | { | |
7841 | /* By using store_unsigned_integer we avoid having to do | |
7842 | anything special for small big-endian values. */ | |
7843 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
7844 | store_unsigned_integer (valbuf, | |
7845 | (len > INT_REGISTER_SIZE | |
7846 | ? INT_REGISTER_SIZE : len), | |
7847 | byte_order, tmp); | |
7848 | len -= INT_REGISTER_SIZE; | |
7849 | valbuf += INT_REGISTER_SIZE; | |
7850 | } | |
7851 | } | |
7852 | else | |
7853 | { | |
7854 | /* For a structure or union the behaviour is as if the value had | |
7855 | been stored to word-aligned memory and then loaded into | |
7856 | registers with 32-bit load instruction(s). */ | |
7857 | int len = TYPE_LENGTH (type); | |
7858 | int regno = ARM_A1_REGNUM; | |
7859 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; | |
7860 | ||
7861 | while (len > 0) | |
7862 | { | |
7863 | regcache_cooked_read (regs, regno++, tmpbuf); | |
7864 | memcpy (valbuf, tmpbuf, | |
7865 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); | |
7866 | len -= INT_REGISTER_SIZE; | |
7867 | valbuf += INT_REGISTER_SIZE; | |
7868 | } | |
7869 | } | |
7870 | } | |
7871 | ||
7872 | ||
7873 | /* Will a function return an aggregate type in memory or in a | |
7874 | register? Return 0 if an aggregate type can be returned in a | |
7875 | register, 1 if it must be returned in memory. */ | |
7876 | ||
7877 | static int | |
7878 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
7879 | { | |
cca44b1b JB |
7880 | enum type_code code; |
7881 | ||
f168693b | 7882 | type = check_typedef (type); |
cca44b1b | 7883 | |
b13c8ab2 YQ |
7884 | /* Simple, non-aggregate types (ie not including vectors and |
7885 | complex) are always returned in a register (or registers). */ | |
7886 | code = TYPE_CODE (type); | |
7887 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code | |
7888 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
7889 | return 0; | |
cca44b1b | 7890 | |
c4312b19 YQ |
7891 | if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type)) |
7892 | { | |
7893 | /* Vector values should be returned using ARM registers if they | |
7894 | are not over 16 bytes. */ | |
7895 | return (TYPE_LENGTH (type) > 16); | |
7896 | } | |
7897 | ||
b13c8ab2 | 7898 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
cca44b1b | 7899 | { |
b13c8ab2 YQ |
7900 | /* The AAPCS says all aggregates not larger than a word are returned |
7901 | in a register. */ | |
7902 | if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE) | |
7903 | return 0; | |
7904 | ||
cca44b1b JB |
7905 | return 1; |
7906 | } | |
b13c8ab2 YQ |
7907 | else |
7908 | { | |
7909 | int nRc; | |
cca44b1b | 7910 | |
b13c8ab2 YQ |
7911 | /* All aggregate types that won't fit in a register must be returned |
7912 | in memory. */ | |
7913 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) | |
7914 | return 1; | |
cca44b1b | 7915 | |
b13c8ab2 YQ |
7916 | /* In the ARM ABI, "integer" like aggregate types are returned in |
7917 | registers. For an aggregate type to be integer like, its size | |
7918 | must be less than or equal to INT_REGISTER_SIZE and the | |
7919 | offset of each addressable subfield must be zero. Note that bit | |
7920 | fields are not addressable, and all addressable subfields of | |
7921 | unions always start at offset zero. | |
cca44b1b | 7922 | |
b13c8ab2 YQ |
7923 | This function is based on the behaviour of GCC 2.95.1. |
7924 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 7925 | |
b13c8ab2 YQ |
7926 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
7927 | parameters correctly for a function returning the following | |
7928 | structure: struct { float f;}; This should be returned in memory, | |
7929 | not a register. Richard Earnshaw sent me a patch, but I do not | |
7930 | know of any way to detect if a function like the above has been | |
7931 | compiled with the correct calling convention. */ | |
7932 | ||
7933 | /* Assume all other aggregate types can be returned in a register. | |
7934 | Run a check for structures, unions and arrays. */ | |
7935 | nRc = 0; | |
67255d04 | 7936 | |
b13c8ab2 YQ |
7937 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
7938 | { | |
7939 | int i; | |
7940 | /* Need to check if this struct/union is "integer" like. For | |
7941 | this to be true, its size must be less than or equal to | |
7942 | INT_REGISTER_SIZE and the offset of each addressable | |
7943 | subfield must be zero. Note that bit fields are not | |
7944 | addressable, and unions always start at offset zero. If any | |
7945 | of the subfields is a floating point type, the struct/union | |
7946 | cannot be an integer type. */ | |
7947 | ||
7948 | /* For each field in the object, check: | |
7949 | 1) Is it FP? --> yes, nRc = 1; | |
7950 | 2) Is it addressable (bitpos != 0) and | |
7951 | not packed (bitsize == 0)? | |
7952 | --> yes, nRc = 1 | |
7953 | */ | |
7954 | ||
7955 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
67255d04 | 7956 | { |
b13c8ab2 YQ |
7957 | enum type_code field_type_code; |
7958 | ||
7959 | field_type_code | |
7960 | = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, | |
7961 | i))); | |
7962 | ||
7963 | /* Is it a floating point type field? */ | |
7964 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
7965 | { |
7966 | nRc = 1; | |
7967 | break; | |
7968 | } | |
b13c8ab2 YQ |
7969 | |
7970 | /* If bitpos != 0, then we have to care about it. */ | |
7971 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
7972 | { | |
7973 | /* Bitfields are not addressable. If the field bitsize is | |
7974 | zero, then the field is not packed. Hence it cannot be | |
7975 | a bitfield or any other packed type. */ | |
7976 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
7977 | { | |
7978 | nRc = 1; | |
7979 | break; | |
7980 | } | |
7981 | } | |
67255d04 RE |
7982 | } |
7983 | } | |
67255d04 | 7984 | |
b13c8ab2 YQ |
7985 | return nRc; |
7986 | } | |
67255d04 RE |
7987 | } |
7988 | ||
34e8f22d RE |
7989 | /* Write into appropriate registers a function return value of type |
7990 | TYPE, given in virtual format. */ | |
7991 | ||
7992 | static void | |
b508a996 | 7993 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 7994 | const gdb_byte *valbuf) |
34e8f22d | 7995 | { |
be8626e0 | 7996 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 7997 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 7998 | |
34e8f22d RE |
7999 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
8000 | { | |
e362b510 | 8001 | gdb_byte buf[MAX_REGISTER_SIZE]; |
34e8f22d | 8002 | |
be8626e0 | 8003 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
8004 | { |
8005 | case ARM_FLOAT_FPA: | |
8006 | ||
be8626e0 MD |
8007 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
8008 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 8009 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
8010 | break; |
8011 | ||
fd50bc42 | 8012 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8013 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8014 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8015 | not using the VFP ABI code. */ | |
8016 | case ARM_FLOAT_VFP: | |
b508a996 RE |
8017 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
8018 | if (TYPE_LENGTH (type) > 4) | |
8019 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 8020 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
8021 | break; |
8022 | ||
8023 | default: | |
9b20d036 MS |
8024 | internal_error (__FILE__, __LINE__, |
8025 | _("arm_store_return_value: Floating " | |
8026 | "point model not supported")); | |
08216dd7 RE |
8027 | break; |
8028 | } | |
34e8f22d | 8029 | } |
b508a996 RE |
8030 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
8031 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
8032 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
8033 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
8034 | || TYPE_CODE (type) == TYPE_CODE_REF | |
8035 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
8036 | { | |
8037 | if (TYPE_LENGTH (type) <= 4) | |
8038 | { | |
8039 | /* Values of one word or less are zero/sign-extended and | |
8040 | returned in r0. */ | |
7a5ea0d4 | 8041 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
8042 | LONGEST val = unpack_long (type, valbuf); |
8043 | ||
e17a4113 | 8044 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
b508a996 RE |
8045 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
8046 | } | |
8047 | else | |
8048 | { | |
8049 | /* Integral values greater than one word are stored in consecutive | |
8050 | registers starting with r0. This will always be a multiple of | |
8051 | the regiser size. */ | |
8052 | int len = TYPE_LENGTH (type); | |
8053 | int regno = ARM_A1_REGNUM; | |
8054 | ||
8055 | while (len > 0) | |
8056 | { | |
8057 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
8058 | len -= INT_REGISTER_SIZE; |
8059 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
8060 | } |
8061 | } | |
8062 | } | |
34e8f22d | 8063 | else |
b508a996 RE |
8064 | { |
8065 | /* For a structure or union the behaviour is as if the value had | |
8066 | been stored to word-aligned memory and then loaded into | |
8067 | registers with 32-bit load instruction(s). */ | |
8068 | int len = TYPE_LENGTH (type); | |
8069 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 8070 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
8071 | |
8072 | while (len > 0) | |
8073 | { | |
8074 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 8075 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 8076 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
8077 | len -= INT_REGISTER_SIZE; |
8078 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
8079 | } |
8080 | } | |
34e8f22d RE |
8081 | } |
8082 | ||
2af48f68 PB |
8083 | |
8084 | /* Handle function return values. */ | |
8085 | ||
8086 | static enum return_value_convention | |
6a3a010b | 8087 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
8088 | struct type *valtype, struct regcache *regcache, |
8089 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 8090 | { |
7c00367c | 8091 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 8092 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
8093 | enum arm_vfp_cprc_base_type vfp_base_type; |
8094 | int vfp_base_count; | |
8095 | ||
8096 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
8097 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
8098 | { | |
8099 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
8100 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
8101 | int i; | |
8102 | for (i = 0; i < vfp_base_count; i++) | |
8103 | { | |
58d6951d DJ |
8104 | if (reg_char == 'q') |
8105 | { | |
8106 | if (writebuf) | |
8107 | arm_neon_quad_write (gdbarch, regcache, i, | |
8108 | writebuf + i * unit_length); | |
8109 | ||
8110 | if (readbuf) | |
8111 | arm_neon_quad_read (gdbarch, regcache, i, | |
8112 | readbuf + i * unit_length); | |
8113 | } | |
8114 | else | |
8115 | { | |
8116 | char name_buf[4]; | |
8117 | int regnum; | |
8118 | ||
8c042590 | 8119 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
8120 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8121 | strlen (name_buf)); | |
8122 | if (writebuf) | |
8123 | regcache_cooked_write (regcache, regnum, | |
8124 | writebuf + i * unit_length); | |
8125 | if (readbuf) | |
8126 | regcache_cooked_read (regcache, regnum, | |
8127 | readbuf + i * unit_length); | |
8128 | } | |
90445bd3 DJ |
8129 | } |
8130 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8131 | } | |
7c00367c | 8132 | |
2af48f68 PB |
8133 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
8134 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
8135 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
8136 | { | |
7c00367c MK |
8137 | if (tdep->struct_return == pcc_struct_return |
8138 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
8139 | return RETURN_VALUE_STRUCT_CONVENTION; |
8140 | } | |
b13c8ab2 YQ |
8141 | else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX) |
8142 | { | |
8143 | if (arm_return_in_memory (gdbarch, valtype)) | |
8144 | return RETURN_VALUE_STRUCT_CONVENTION; | |
8145 | } | |
7052e42c | 8146 | |
2af48f68 PB |
8147 | if (writebuf) |
8148 | arm_store_return_value (valtype, regcache, writebuf); | |
8149 | ||
8150 | if (readbuf) | |
8151 | arm_extract_return_value (valtype, regcache, readbuf); | |
8152 | ||
8153 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8154 | } | |
8155 | ||
8156 | ||
9df628e0 | 8157 | static int |
60ade65d | 8158 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 8159 | { |
e17a4113 UW |
8160 | struct gdbarch *gdbarch = get_frame_arch (frame); |
8161 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8162 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 8163 | CORE_ADDR jb_addr; |
e362b510 | 8164 | gdb_byte buf[INT_REGISTER_SIZE]; |
9df628e0 | 8165 | |
60ade65d | 8166 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
8167 | |
8168 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 8169 | INT_REGISTER_SIZE)) |
9df628e0 RE |
8170 | return 0; |
8171 | ||
e17a4113 | 8172 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
8173 | return 1; |
8174 | } | |
8175 | ||
faa95490 DJ |
8176 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
8177 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
8178 | |
8179 | CORE_ADDR | |
52f729a7 | 8180 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 8181 | { |
2c02bd72 | 8182 | const char *name; |
faa95490 | 8183 | int namelen; |
c906108c SS |
8184 | CORE_ADDR start_addr; |
8185 | ||
8186 | /* Find the starting address and name of the function containing the PC. */ | |
8187 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
8188 | { |
8189 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
8190 | check here. */ | |
8191 | start_addr = arm_skip_bx_reg (frame, pc); | |
8192 | if (start_addr != 0) | |
8193 | return start_addr; | |
8194 | ||
8195 | return 0; | |
8196 | } | |
c906108c | 8197 | |
faa95490 DJ |
8198 | /* If PC is in a Thumb call or return stub, return the address of the |
8199 | target PC, which is in a register. The thunk functions are called | |
8200 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
8201 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
8202 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
8203 | if (startswith (name, "_call_via_") |
8204 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 8205 | { |
ed9a39eb JM |
8206 | /* Use the name suffix to determine which register contains the |
8207 | target PC. */ | |
c5aa993b JM |
8208 | static char *table[15] = |
8209 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8210 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
8211 | }; | |
c906108c | 8212 | int regno; |
faa95490 | 8213 | int offset = strlen (name) - 2; |
c906108c SS |
8214 | |
8215 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 8216 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 8217 | return get_frame_register_unsigned (frame, regno); |
c906108c | 8218 | } |
ed9a39eb | 8219 | |
faa95490 DJ |
8220 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
8221 | non-interworking calls to foo. We could decode the stubs | |
8222 | to find the target but it's easier to use the symbol table. */ | |
8223 | namelen = strlen (name); | |
8224 | if (name[0] == '_' && name[1] == '_' | |
8225 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 8226 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 8227 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 8228 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
8229 | { |
8230 | char *target_name; | |
8231 | int target_len = namelen - 2; | |
3b7344d5 | 8232 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
8233 | struct objfile *objfile; |
8234 | struct obj_section *sec; | |
8235 | ||
8236 | if (name[namelen - 1] == 'b') | |
8237 | target_len -= strlen ("_from_thumb"); | |
8238 | else | |
8239 | target_len -= strlen ("_from_arm"); | |
8240 | ||
224c3ddb | 8241 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
8242 | memcpy (target_name, name + 2, target_len); |
8243 | target_name[target_len] = '\0'; | |
8244 | ||
8245 | sec = find_pc_section (pc); | |
8246 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
8247 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 8248 | if (minsym.minsym != NULL) |
77e371c0 | 8249 | return BMSYMBOL_VALUE_ADDRESS (minsym); |
faa95490 DJ |
8250 | else |
8251 | return 0; | |
8252 | } | |
8253 | ||
c5aa993b | 8254 | return 0; /* not a stub */ |
c906108c SS |
8255 | } |
8256 | ||
afd7eef0 RE |
8257 | static void |
8258 | set_arm_command (char *args, int from_tty) | |
8259 | { | |
edefbb7c AC |
8260 | printf_unfiltered (_("\ |
8261 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
8262 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
8263 | } | |
8264 | ||
8265 | static void | |
8266 | show_arm_command (char *args, int from_tty) | |
8267 | { | |
26304000 | 8268 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
8269 | } |
8270 | ||
28e97307 DJ |
8271 | static void |
8272 | arm_update_current_architecture (void) | |
fd50bc42 | 8273 | { |
28e97307 | 8274 | struct gdbarch_info info; |
fd50bc42 | 8275 | |
28e97307 | 8276 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 8277 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 8278 | return; |
fd50bc42 | 8279 | |
28e97307 DJ |
8280 | /* Update the architecture. */ |
8281 | gdbarch_info_init (&info); | |
fd50bc42 | 8282 | |
28e97307 | 8283 | if (!gdbarch_update_p (info)) |
9b20d036 | 8284 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
8285 | } |
8286 | ||
8287 | static void | |
8288 | set_fp_model_sfunc (char *args, int from_tty, | |
8289 | struct cmd_list_element *c) | |
8290 | { | |
570dc176 | 8291 | int fp_model; |
fd50bc42 RE |
8292 | |
8293 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
8294 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
8295 | { | |
aead7601 | 8296 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
8297 | break; |
8298 | } | |
8299 | ||
8300 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 8301 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
8302 | current_fp_model); |
8303 | ||
28e97307 | 8304 | arm_update_current_architecture (); |
fd50bc42 RE |
8305 | } |
8306 | ||
8307 | static void | |
08546159 AC |
8308 | show_fp_model (struct ui_file *file, int from_tty, |
8309 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 8310 | { |
f5656ead | 8311 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
fd50bc42 | 8312 | |
28e97307 | 8313 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 8314 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8315 | fprintf_filtered (file, _("\ |
8316 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
8317 | fp_model_strings[tdep->fp_model]); | |
8318 | else | |
8319 | fprintf_filtered (file, _("\ | |
8320 | The current ARM floating point model is \"%s\".\n"), | |
8321 | fp_model_strings[arm_fp_model]); | |
8322 | } | |
8323 | ||
8324 | static void | |
8325 | arm_set_abi (char *args, int from_tty, | |
8326 | struct cmd_list_element *c) | |
8327 | { | |
570dc176 | 8328 | int arm_abi; |
28e97307 DJ |
8329 | |
8330 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
8331 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
8332 | { | |
aead7601 | 8333 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
8334 | break; |
8335 | } | |
8336 | ||
8337 | if (arm_abi == ARM_ABI_LAST) | |
8338 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
8339 | arm_abi_string); | |
8340 | ||
8341 | arm_update_current_architecture (); | |
8342 | } | |
8343 | ||
8344 | static void | |
8345 | arm_show_abi (struct ui_file *file, int from_tty, | |
8346 | struct cmd_list_element *c, const char *value) | |
8347 | { | |
f5656ead | 8348 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
28e97307 DJ |
8349 | |
8350 | if (arm_abi_global == ARM_ABI_AUTO | |
f5656ead | 8351 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8352 | fprintf_filtered (file, _("\ |
8353 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
8354 | arm_abi_strings[tdep->arm_abi]); | |
8355 | else | |
8356 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
8357 | arm_abi_string); | |
fd50bc42 RE |
8358 | } |
8359 | ||
0428b8f5 DJ |
8360 | static void |
8361 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
8362 | struct cmd_list_element *c, const char *value) | |
8363 | { | |
0963b4bd MS |
8364 | fprintf_filtered (file, |
8365 | _("The current execution mode assumed " | |
8366 | "(when symbols are unavailable) is \"%s\".\n"), | |
0428b8f5 DJ |
8367 | arm_fallback_mode_string); |
8368 | } | |
8369 | ||
8370 | static void | |
8371 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
8372 | struct cmd_list_element *c, const char *value) | |
8373 | { | |
f5656ead | 8374 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
0428b8f5 | 8375 | |
0963b4bd MS |
8376 | fprintf_filtered (file, |
8377 | _("The current execution mode assumed " | |
8378 | "(even when symbols are available) is \"%s\".\n"), | |
0428b8f5 DJ |
8379 | arm_force_mode_string); |
8380 | } | |
8381 | ||
afd7eef0 RE |
8382 | /* If the user changes the register disassembly style used for info |
8383 | register and other commands, we have to also switch the style used | |
8384 | in opcodes for disassembly output. This function is run in the "set | |
8385 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
8386 | |
8387 | static void | |
afd7eef0 | 8388 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
8389 | struct cmd_list_element *c) |
8390 | { | |
afd7eef0 | 8391 | set_disassembly_style (); |
bc90b915 FN |
8392 | } |
8393 | \f | |
966fbf70 | 8394 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 8395 | static const char * |
d93859e2 | 8396 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 8397 | { |
58d6951d DJ |
8398 | const int num_regs = gdbarch_num_regs (gdbarch); |
8399 | ||
8400 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
8401 | && i >= num_regs && i < num_regs + 32) | |
8402 | { | |
8403 | static const char *const vfp_pseudo_names[] = { | |
8404 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
8405 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
8406 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
8407 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
8408 | }; | |
8409 | ||
8410 | return vfp_pseudo_names[i - num_regs]; | |
8411 | } | |
8412 | ||
8413 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
8414 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
8415 | { | |
8416 | static const char *const neon_pseudo_names[] = { | |
8417 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
8418 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
8419 | }; | |
8420 | ||
8421 | return neon_pseudo_names[i - num_regs - 32]; | |
8422 | } | |
8423 | ||
ff6f572f DJ |
8424 | if (i >= ARRAY_SIZE (arm_register_names)) |
8425 | /* These registers are only supported on targets which supply | |
8426 | an XML description. */ | |
8427 | return ""; | |
8428 | ||
966fbf70 RE |
8429 | return arm_register_names[i]; |
8430 | } | |
8431 | ||
bc90b915 | 8432 | static void |
afd7eef0 | 8433 | set_disassembly_style (void) |
bc90b915 | 8434 | { |
123dc839 | 8435 | int current; |
bc90b915 | 8436 | |
123dc839 DJ |
8437 | /* Find the style that the user wants. */ |
8438 | for (current = 0; current < num_disassembly_options; current++) | |
8439 | if (disassembly_style == valid_disassembly_styles[current]) | |
8440 | break; | |
8441 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 8442 | |
94c30b78 | 8443 | /* Synchronize the disassembler. */ |
bc90b915 FN |
8444 | set_arm_regname_option (current); |
8445 | } | |
8446 | ||
082fc60d RE |
8447 | /* Test whether the coff symbol specific value corresponds to a Thumb |
8448 | function. */ | |
8449 | ||
8450 | static int | |
8451 | coff_sym_is_thumb (int val) | |
8452 | { | |
f8bf5763 PM |
8453 | return (val == C_THUMBEXT |
8454 | || val == C_THUMBSTAT | |
8455 | || val == C_THUMBEXTFUNC | |
8456 | || val == C_THUMBSTATFUNC | |
8457 | || val == C_THUMBLABEL); | |
082fc60d RE |
8458 | } |
8459 | ||
8460 | /* arm_coff_make_msymbol_special() | |
8461 | arm_elf_make_msymbol_special() | |
8462 | ||
8463 | These functions test whether the COFF or ELF symbol corresponds to | |
8464 | an address in thumb code, and set a "special" bit in a minimal | |
8465 | symbol to indicate that it does. */ | |
8466 | ||
34e8f22d | 8467 | static void |
082fc60d RE |
8468 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
8469 | { | |
467d42c4 UW |
8470 | if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym) |
8471 | == ST_BRANCH_TO_THUMB) | |
082fc60d RE |
8472 | MSYMBOL_SET_SPECIAL (msym); |
8473 | } | |
8474 | ||
34e8f22d | 8475 | static void |
082fc60d RE |
8476 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
8477 | { | |
8478 | if (coff_sym_is_thumb (val)) | |
8479 | MSYMBOL_SET_SPECIAL (msym); | |
8480 | } | |
8481 | ||
60c5725c | 8482 | static void |
c1bd65d0 | 8483 | arm_objfile_data_free (struct objfile *objfile, void *arg) |
60c5725c | 8484 | { |
9a3c8263 | 8485 | struct arm_per_objfile *data = (struct arm_per_objfile *) arg; |
60c5725c DJ |
8486 | unsigned int i; |
8487 | ||
8488 | for (i = 0; i < objfile->obfd->section_count; i++) | |
8489 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); | |
8490 | } | |
8491 | ||
8492 | static void | |
8493 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
8494 | asymbol *sym) | |
8495 | { | |
8496 | const char *name = bfd_asymbol_name (sym); | |
8497 | struct arm_per_objfile *data; | |
8498 | VEC(arm_mapping_symbol_s) **map_p; | |
8499 | struct arm_mapping_symbol new_map_sym; | |
8500 | ||
8501 | gdb_assert (name[0] == '$'); | |
8502 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
8503 | return; | |
8504 | ||
9a3c8263 SM |
8505 | data = (struct arm_per_objfile *) objfile_data (objfile, |
8506 | arm_objfile_data_key); | |
60c5725c DJ |
8507 | if (data == NULL) |
8508 | { | |
8509 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, | |
8510 | struct arm_per_objfile); | |
8511 | set_objfile_data (objfile, arm_objfile_data_key, data); | |
8512 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
8513 | objfile->obfd->section_count, | |
8514 | VEC(arm_mapping_symbol_s) *); | |
8515 | } | |
8516 | map_p = &data->section_maps[bfd_get_section (sym)->index]; | |
8517 | ||
8518 | new_map_sym.value = sym->value; | |
8519 | new_map_sym.type = name[1]; | |
8520 | ||
8521 | /* Assume that most mapping symbols appear in order of increasing | |
8522 | value. If they were randomly distributed, it would be faster to | |
8523 | always push here and then sort at first use. */ | |
8524 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) | |
8525 | { | |
8526 | struct arm_mapping_symbol *prev_map_sym; | |
8527 | ||
8528 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); | |
8529 | if (prev_map_sym->value >= sym->value) | |
8530 | { | |
8531 | unsigned int idx; | |
8532 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, | |
8533 | arm_compare_mapping_symbols); | |
8534 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); | |
8535 | return; | |
8536 | } | |
8537 | } | |
8538 | ||
8539 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); | |
8540 | } | |
8541 | ||
756fe439 | 8542 | static void |
61a1198a | 8543 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 8544 | { |
9779414d | 8545 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
61a1198a | 8546 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
8547 | |
8548 | /* If necessary, set the T bit. */ | |
8549 | if (arm_apcs_32) | |
8550 | { | |
9779414d | 8551 | ULONGEST val, t_bit; |
61a1198a | 8552 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
8553 | t_bit = arm_psr_thumb_bit (gdbarch); |
8554 | if (arm_pc_is_thumb (gdbarch, pc)) | |
8555 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
8556 | val | t_bit); | |
756fe439 | 8557 | else |
61a1198a | 8558 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 8559 | val & ~t_bit); |
756fe439 DJ |
8560 | } |
8561 | } | |
123dc839 | 8562 | |
58d6951d DJ |
8563 | /* Read the contents of a NEON quad register, by reading from two |
8564 | double registers. This is used to implement the quad pseudo | |
8565 | registers, and for argument passing in case the quad registers are | |
8566 | missing; vectors are passed in quad registers when using the VFP | |
8567 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
8568 | the quad register, in [0, 15]. */ | |
8569 | ||
05d1431c | 8570 | static enum register_status |
58d6951d DJ |
8571 | arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, |
8572 | int regnum, gdb_byte *buf) | |
8573 | { | |
8574 | char name_buf[4]; | |
8575 | gdb_byte reg_buf[8]; | |
8576 | int offset, double_regnum; | |
05d1431c | 8577 | enum register_status status; |
58d6951d | 8578 | |
8c042590 | 8579 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8580 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8581 | strlen (name_buf)); | |
8582 | ||
8583 | /* d0 is always the least significant half of q0. */ | |
8584 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8585 | offset = 8; | |
8586 | else | |
8587 | offset = 0; | |
8588 | ||
05d1431c PA |
8589 | status = regcache_raw_read (regcache, double_regnum, reg_buf); |
8590 | if (status != REG_VALID) | |
8591 | return status; | |
58d6951d DJ |
8592 | memcpy (buf + offset, reg_buf, 8); |
8593 | ||
8594 | offset = 8 - offset; | |
05d1431c PA |
8595 | status = regcache_raw_read (regcache, double_regnum + 1, reg_buf); |
8596 | if (status != REG_VALID) | |
8597 | return status; | |
58d6951d | 8598 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
8599 | |
8600 | return REG_VALID; | |
58d6951d DJ |
8601 | } |
8602 | ||
05d1431c | 8603 | static enum register_status |
58d6951d DJ |
8604 | arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache, |
8605 | int regnum, gdb_byte *buf) | |
8606 | { | |
8607 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8608 | char name_buf[4]; | |
8609 | gdb_byte reg_buf[8]; | |
8610 | int offset, double_regnum; | |
8611 | ||
8612 | gdb_assert (regnum >= num_regs); | |
8613 | regnum -= num_regs; | |
8614 | ||
8615 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8616 | /* Quad-precision register. */ | |
05d1431c | 8617 | return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); |
58d6951d DJ |
8618 | else |
8619 | { | |
05d1431c PA |
8620 | enum register_status status; |
8621 | ||
58d6951d DJ |
8622 | /* Single-precision register. */ |
8623 | gdb_assert (regnum < 32); | |
8624 | ||
8625 | /* s0 is always the least significant half of d0. */ | |
8626 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8627 | offset = (regnum & 1) ? 0 : 4; | |
8628 | else | |
8629 | offset = (regnum & 1) ? 4 : 0; | |
8630 | ||
8c042590 | 8631 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8632 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8633 | strlen (name_buf)); | |
8634 | ||
05d1431c PA |
8635 | status = regcache_raw_read (regcache, double_regnum, reg_buf); |
8636 | if (status == REG_VALID) | |
8637 | memcpy (buf, reg_buf + offset, 4); | |
8638 | return status; | |
58d6951d DJ |
8639 | } |
8640 | } | |
8641 | ||
8642 | /* Store the contents of BUF to a NEON quad register, by writing to | |
8643 | two double registers. This is used to implement the quad pseudo | |
8644 | registers, and for argument passing in case the quad registers are | |
8645 | missing; vectors are passed in quad registers when using the VFP | |
8646 | ABI, even if a NEON unit is not present. REGNUM is the index | |
8647 | of the quad register, in [0, 15]. */ | |
8648 | ||
8649 | static void | |
8650 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8651 | int regnum, const gdb_byte *buf) | |
8652 | { | |
8653 | char name_buf[4]; | |
58d6951d DJ |
8654 | int offset, double_regnum; |
8655 | ||
8c042590 | 8656 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8657 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8658 | strlen (name_buf)); | |
8659 | ||
8660 | /* d0 is always the least significant half of q0. */ | |
8661 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8662 | offset = 8; | |
8663 | else | |
8664 | offset = 0; | |
8665 | ||
8666 | regcache_raw_write (regcache, double_regnum, buf + offset); | |
8667 | offset = 8 - offset; | |
8668 | regcache_raw_write (regcache, double_regnum + 1, buf + offset); | |
8669 | } | |
8670 | ||
8671 | static void | |
8672 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8673 | int regnum, const gdb_byte *buf) | |
8674 | { | |
8675 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8676 | char name_buf[4]; | |
8677 | gdb_byte reg_buf[8]; | |
8678 | int offset, double_regnum; | |
8679 | ||
8680 | gdb_assert (regnum >= num_regs); | |
8681 | regnum -= num_regs; | |
8682 | ||
8683 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8684 | /* Quad-precision register. */ | |
8685 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
8686 | else | |
8687 | { | |
8688 | /* Single-precision register. */ | |
8689 | gdb_assert (regnum < 32); | |
8690 | ||
8691 | /* s0 is always the least significant half of d0. */ | |
8692 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8693 | offset = (regnum & 1) ? 0 : 4; | |
8694 | else | |
8695 | offset = (regnum & 1) ? 4 : 0; | |
8696 | ||
8c042590 | 8697 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8698 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8699 | strlen (name_buf)); | |
8700 | ||
8701 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
8702 | memcpy (reg_buf + offset, buf, 4); | |
8703 | regcache_raw_write (regcache, double_regnum, reg_buf); | |
8704 | } | |
8705 | } | |
8706 | ||
123dc839 DJ |
8707 | static struct value * |
8708 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
8709 | { | |
9a3c8263 | 8710 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
8711 | return value_of_register (*reg_p, frame); |
8712 | } | |
97e03143 | 8713 | \f |
70f80edf JT |
8714 | static enum gdb_osabi |
8715 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 8716 | { |
2af48f68 | 8717 | unsigned int elfosabi; |
70f80edf | 8718 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 8719 | |
70f80edf | 8720 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 8721 | |
28e97307 DJ |
8722 | if (elfosabi == ELFOSABI_ARM) |
8723 | /* GNU tools use this value. Check note sections in this case, | |
8724 | as well. */ | |
8725 | bfd_map_over_sections (abfd, | |
8726 | generic_elf_osabi_sniff_abi_tag_sections, | |
8727 | &osabi); | |
97e03143 | 8728 | |
28e97307 | 8729 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 8730 | return osabi; |
97e03143 RE |
8731 | } |
8732 | ||
54483882 YQ |
8733 | static int |
8734 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
8735 | struct reggroup *group) | |
8736 | { | |
2c291032 YQ |
8737 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
8738 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
8739 | all_reggroup, of course. */ | |
54483882 | 8740 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
8741 | return (group == float_reggroup |
8742 | || group == save_reggroup | |
8743 | || group == restore_reggroup | |
8744 | || group == all_reggroup); | |
54483882 YQ |
8745 | else |
8746 | return default_register_reggroup_p (gdbarch, regnum, group); | |
8747 | } | |
8748 | ||
25f8c692 JL |
8749 | \f |
8750 | /* For backward-compatibility we allow two 'g' packet lengths with | |
8751 | the remote protocol depending on whether FPA registers are | |
8752 | supplied. M-profile targets do not have FPA registers, but some | |
8753 | stubs already exist in the wild which use a 'g' packet which | |
8754 | supplies them albeit with dummy values. The packet format which | |
8755 | includes FPA registers should be considered deprecated for | |
8756 | M-profile targets. */ | |
8757 | ||
8758 | static void | |
8759 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8760 | { | |
8761 | if (gdbarch_tdep (gdbarch)->is_m) | |
8762 | { | |
8763 | /* If we know from the executable this is an M-profile target, | |
8764 | cater for remote targets whose register set layout is the | |
8765 | same as the FPA layout. */ | |
8766 | register_remote_g_packet_guess (gdbarch, | |
03145bf4 | 8767 | /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */ |
25f8c692 JL |
8768 | (16 * INT_REGISTER_SIZE) |
8769 | + (8 * FP_REGISTER_SIZE) | |
8770 | + (2 * INT_REGISTER_SIZE), | |
8771 | tdesc_arm_with_m_fpa_layout); | |
8772 | ||
8773 | /* The regular M-profile layout. */ | |
8774 | register_remote_g_packet_guess (gdbarch, | |
8775 | /* r0-r12,sp,lr,pc; xpsr */ | |
8776 | (16 * INT_REGISTER_SIZE) | |
8777 | + INT_REGISTER_SIZE, | |
8778 | tdesc_arm_with_m); | |
3184d3f9 JL |
8779 | |
8780 | /* M-profile plus M4F VFP. */ | |
8781 | register_remote_g_packet_guess (gdbarch, | |
8782 | /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */ | |
8783 | (16 * INT_REGISTER_SIZE) | |
8784 | + (16 * VFP_REGISTER_SIZE) | |
8785 | + (2 * INT_REGISTER_SIZE), | |
8786 | tdesc_arm_with_m_vfp_d16); | |
25f8c692 JL |
8787 | } |
8788 | ||
8789 | /* Otherwise we don't have a useful guess. */ | |
8790 | } | |
8791 | ||
70f80edf | 8792 | \f |
da3c6d4a MS |
8793 | /* Initialize the current architecture based on INFO. If possible, |
8794 | re-use an architecture from ARCHES, which is a list of | |
8795 | architectures already created during this debugging session. | |
97e03143 | 8796 | |
da3c6d4a MS |
8797 | Called e.g. at program startup, when reading a core file, and when |
8798 | reading a binary file. */ | |
97e03143 | 8799 | |
39bbf761 RE |
8800 | static struct gdbarch * |
8801 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8802 | { | |
97e03143 | 8803 | struct gdbarch_tdep *tdep; |
39bbf761 | 8804 | struct gdbarch *gdbarch; |
28e97307 DJ |
8805 | struct gdbarch_list *best_arch; |
8806 | enum arm_abi_kind arm_abi = arm_abi_global; | |
8807 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 | 8808 | struct tdesc_arch_data *tdesc_data = NULL; |
9779414d | 8809 | int i, is_m = 0; |
330c6ca9 | 8810 | int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; |
a56cc1ce | 8811 | int have_wmmx_registers = 0; |
58d6951d | 8812 | int have_neon = 0; |
ff6f572f | 8813 | int have_fpa_registers = 1; |
9779414d DJ |
8814 | const struct target_desc *tdesc = info.target_desc; |
8815 | ||
8816 | /* If we have an object to base this architecture on, try to determine | |
8817 | its ABI. */ | |
8818 | ||
8819 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
8820 | { | |
8821 | int ei_osabi, e_flags; | |
8822 | ||
8823 | switch (bfd_get_flavour (info.abfd)) | |
8824 | { | |
8825 | case bfd_target_aout_flavour: | |
8826 | /* Assume it's an old APCS-style ABI. */ | |
8827 | arm_abi = ARM_ABI_APCS; | |
8828 | break; | |
8829 | ||
8830 | case bfd_target_coff_flavour: | |
8831 | /* Assume it's an old APCS-style ABI. */ | |
8832 | /* XXX WinCE? */ | |
8833 | arm_abi = ARM_ABI_APCS; | |
8834 | break; | |
8835 | ||
8836 | case bfd_target_elf_flavour: | |
8837 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
8838 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
8839 | ||
8840 | if (ei_osabi == ELFOSABI_ARM) | |
8841 | { | |
8842 | /* GNU tools used to use this value, but do not for EABI | |
8843 | objects. There's nowhere to tag an EABI version | |
8844 | anyway, so assume APCS. */ | |
8845 | arm_abi = ARM_ABI_APCS; | |
8846 | } | |
d403db27 | 8847 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
8848 | { |
8849 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
8850 | int attr_arch, attr_profile; | |
8851 | ||
8852 | switch (eabi_ver) | |
8853 | { | |
8854 | case EF_ARM_EABI_UNKNOWN: | |
8855 | /* Assume GNU tools. */ | |
8856 | arm_abi = ARM_ABI_APCS; | |
8857 | break; | |
8858 | ||
8859 | case EF_ARM_EABI_VER4: | |
8860 | case EF_ARM_EABI_VER5: | |
8861 | arm_abi = ARM_ABI_AAPCS; | |
8862 | /* EABI binaries default to VFP float ordering. | |
8863 | They may also contain build attributes that can | |
8864 | be used to identify if the VFP argument-passing | |
8865 | ABI is in use. */ | |
8866 | if (fp_model == ARM_FLOAT_AUTO) | |
8867 | { | |
8868 | #ifdef HAVE_ELF | |
8869 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
8870 | OBJ_ATTR_PROC, | |
8871 | Tag_ABI_VFP_args)) | |
8872 | { | |
b35b0298 | 8873 | case AEABI_VFP_args_base: |
9779414d DJ |
8874 | /* "The user intended FP parameter/result |
8875 | passing to conform to AAPCS, base | |
8876 | variant". */ | |
8877 | fp_model = ARM_FLOAT_SOFT_VFP; | |
8878 | break; | |
b35b0298 | 8879 | case AEABI_VFP_args_vfp: |
9779414d DJ |
8880 | /* "The user intended FP parameter/result |
8881 | passing to conform to AAPCS, VFP | |
8882 | variant". */ | |
8883 | fp_model = ARM_FLOAT_VFP; | |
8884 | break; | |
b35b0298 | 8885 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
8886 | /* "The user intended FP parameter/result |
8887 | passing to conform to tool chain-specific | |
8888 | conventions" - we don't know any such | |
8889 | conventions, so leave it as "auto". */ | |
8890 | break; | |
b35b0298 | 8891 | case AEABI_VFP_args_compatible: |
5c294fee TG |
8892 | /* "Code is compatible with both the base |
8893 | and VFP variants; the user did not permit | |
8894 | non-variadic functions to pass FP | |
8895 | parameters/results" - leave it as | |
8896 | "auto". */ | |
8897 | break; | |
9779414d DJ |
8898 | default: |
8899 | /* Attribute value not mentioned in the | |
5c294fee | 8900 | November 2012 ABI, so leave it as |
9779414d DJ |
8901 | "auto". */ |
8902 | break; | |
8903 | } | |
8904 | #else | |
8905 | fp_model = ARM_FLOAT_SOFT_VFP; | |
8906 | #endif | |
8907 | } | |
8908 | break; | |
8909 | ||
8910 | default: | |
8911 | /* Leave it as "auto". */ | |
8912 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
8913 | break; | |
8914 | } | |
8915 | ||
8916 | #ifdef HAVE_ELF | |
8917 | /* Detect M-profile programs. This only works if the | |
8918 | executable file includes build attributes; GCC does | |
8919 | copy them to the executable, but e.g. RealView does | |
8920 | not. */ | |
8921 | attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
8922 | Tag_CPU_arch); | |
0963b4bd MS |
8923 | attr_profile = bfd_elf_get_obj_attr_int (info.abfd, |
8924 | OBJ_ATTR_PROC, | |
9779414d DJ |
8925 | Tag_CPU_arch_profile); |
8926 | /* GCC specifies the profile for v6-M; RealView only | |
8927 | specifies the profile for architectures starting with | |
8928 | V7 (as opposed to architectures with a tag | |
8929 | numerically greater than TAG_CPU_ARCH_V7). */ | |
8930 | if (!tdesc_has_registers (tdesc) | |
8931 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
8932 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
8933 | || attr_profile == 'M')) | |
25f8c692 | 8934 | is_m = 1; |
9779414d DJ |
8935 | #endif |
8936 | } | |
8937 | ||
8938 | if (fp_model == ARM_FLOAT_AUTO) | |
8939 | { | |
8940 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
8941 | ||
8942 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
8943 | { | |
8944 | case 0: | |
8945 | /* Leave it as "auto". Strictly speaking this case | |
8946 | means FPA, but almost nobody uses that now, and | |
8947 | many toolchains fail to set the appropriate bits | |
8948 | for the floating-point model they use. */ | |
8949 | break; | |
8950 | case EF_ARM_SOFT_FLOAT: | |
8951 | fp_model = ARM_FLOAT_SOFT_FPA; | |
8952 | break; | |
8953 | case EF_ARM_VFP_FLOAT: | |
8954 | fp_model = ARM_FLOAT_VFP; | |
8955 | break; | |
8956 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
8957 | fp_model = ARM_FLOAT_SOFT_VFP; | |
8958 | break; | |
8959 | } | |
8960 | } | |
8961 | ||
8962 | if (e_flags & EF_ARM_BE8) | |
8963 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
8964 | ||
8965 | break; | |
8966 | ||
8967 | default: | |
8968 | /* Leave it as "auto". */ | |
8969 | break; | |
8970 | } | |
8971 | } | |
123dc839 DJ |
8972 | |
8973 | /* Check any target description for validity. */ | |
9779414d | 8974 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
8975 | { |
8976 | /* For most registers we require GDB's default names; but also allow | |
8977 | the numeric names for sp / lr / pc, as a convenience. */ | |
8978 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
8979 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
8980 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
8981 | ||
8982 | const struct tdesc_feature *feature; | |
58d6951d | 8983 | int valid_p; |
123dc839 | 8984 | |
9779414d | 8985 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
8986 | "org.gnu.gdb.arm.core"); |
8987 | if (feature == NULL) | |
9779414d DJ |
8988 | { |
8989 | feature = tdesc_find_feature (tdesc, | |
8990 | "org.gnu.gdb.arm.m-profile"); | |
8991 | if (feature == NULL) | |
8992 | return NULL; | |
8993 | else | |
8994 | is_m = 1; | |
8995 | } | |
123dc839 DJ |
8996 | |
8997 | tdesc_data = tdesc_data_alloc (); | |
8998 | ||
8999 | valid_p = 1; | |
9000 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
9001 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
9002 | arm_register_names[i]); | |
9003 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
9004 | ARM_SP_REGNUM, | |
9005 | arm_sp_names); | |
9006 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
9007 | ARM_LR_REGNUM, | |
9008 | arm_lr_names); | |
9009 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
9010 | ARM_PC_REGNUM, | |
9011 | arm_pc_names); | |
9779414d DJ |
9012 | if (is_m) |
9013 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
9014 | ARM_PS_REGNUM, "xpsr"); | |
9015 | else | |
9016 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
9017 | ARM_PS_REGNUM, "cpsr"); | |
123dc839 DJ |
9018 | |
9019 | if (!valid_p) | |
9020 | { | |
9021 | tdesc_data_cleanup (tdesc_data); | |
9022 | return NULL; | |
9023 | } | |
9024 | ||
9779414d | 9025 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9026 | "org.gnu.gdb.arm.fpa"); |
9027 | if (feature != NULL) | |
9028 | { | |
9029 | valid_p = 1; | |
9030 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
9031 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
9032 | arm_register_names[i]); | |
9033 | if (!valid_p) | |
9034 | { | |
9035 | tdesc_data_cleanup (tdesc_data); | |
9036 | return NULL; | |
9037 | } | |
9038 | } | |
ff6f572f DJ |
9039 | else |
9040 | have_fpa_registers = 0; | |
9041 | ||
9779414d | 9042 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
9043 | "org.gnu.gdb.xscale.iwmmxt"); |
9044 | if (feature != NULL) | |
9045 | { | |
9046 | static const char *const iwmmxt_names[] = { | |
9047 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
9048 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
9049 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
9050 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
9051 | }; | |
9052 | ||
9053 | valid_p = 1; | |
9054 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
9055 | valid_p | |
9056 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
9057 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
9058 | ||
9059 | /* Check for the control registers, but do not fail if they | |
9060 | are missing. */ | |
9061 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
9062 | tdesc_numbered_register (feature, tdesc_data, i, | |
9063 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
9064 | ||
9065 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
9066 | valid_p | |
9067 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
9068 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
9069 | ||
9070 | if (!valid_p) | |
9071 | { | |
9072 | tdesc_data_cleanup (tdesc_data); | |
9073 | return NULL; | |
9074 | } | |
a56cc1ce YQ |
9075 | |
9076 | have_wmmx_registers = 1; | |
ff6f572f | 9077 | } |
58d6951d DJ |
9078 | |
9079 | /* If we have a VFP unit, check whether the single precision registers | |
9080 | are present. If not, then we will synthesize them as pseudo | |
9081 | registers. */ | |
9779414d | 9082 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9083 | "org.gnu.gdb.arm.vfp"); |
9084 | if (feature != NULL) | |
9085 | { | |
9086 | static const char *const vfp_double_names[] = { | |
9087 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
9088 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
9089 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
9090 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
9091 | }; | |
9092 | ||
9093 | /* Require the double precision registers. There must be either | |
9094 | 16 or 32. */ | |
9095 | valid_p = 1; | |
9096 | for (i = 0; i < 32; i++) | |
9097 | { | |
9098 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
9099 | ARM_D0_REGNUM + i, | |
9100 | vfp_double_names[i]); | |
9101 | if (!valid_p) | |
9102 | break; | |
9103 | } | |
2b9e5ea6 UW |
9104 | if (!valid_p && i == 16) |
9105 | valid_p = 1; | |
58d6951d | 9106 | |
2b9e5ea6 UW |
9107 | /* Also require FPSCR. */ |
9108 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
9109 | ARM_FPSCR_REGNUM, "fpscr"); | |
9110 | if (!valid_p) | |
58d6951d DJ |
9111 | { |
9112 | tdesc_data_cleanup (tdesc_data); | |
9113 | return NULL; | |
9114 | } | |
9115 | ||
9116 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
9117 | have_vfp_pseudos = 1; | |
9118 | ||
330c6ca9 | 9119 | vfp_register_count = i; |
58d6951d DJ |
9120 | |
9121 | /* If we have VFP, also check for NEON. The architecture allows | |
9122 | NEON without VFP (integer vector operations only), but GDB | |
9123 | does not support that. */ | |
9779414d | 9124 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9125 | "org.gnu.gdb.arm.neon"); |
9126 | if (feature != NULL) | |
9127 | { | |
9128 | /* NEON requires 32 double-precision registers. */ | |
9129 | if (i != 32) | |
9130 | { | |
9131 | tdesc_data_cleanup (tdesc_data); | |
9132 | return NULL; | |
9133 | } | |
9134 | ||
9135 | /* If there are quad registers defined by the stub, use | |
9136 | their type; otherwise (normally) provide them with | |
9137 | the default type. */ | |
9138 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
9139 | have_neon_pseudos = 1; | |
9140 | ||
9141 | have_neon = 1; | |
9142 | } | |
9143 | } | |
123dc839 | 9144 | } |
39bbf761 | 9145 | |
28e97307 DJ |
9146 | /* If there is already a candidate, use it. */ |
9147 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
9148 | best_arch != NULL; | |
9149 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
9150 | { | |
b8926edc DJ |
9151 | if (arm_abi != ARM_ABI_AUTO |
9152 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
9153 | continue; |
9154 | ||
b8926edc DJ |
9155 | if (fp_model != ARM_FLOAT_AUTO |
9156 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
9157 | continue; |
9158 | ||
58d6951d DJ |
9159 | /* There are various other properties in tdep that we do not |
9160 | need to check here: those derived from a target description, | |
9161 | since gdbarches with a different target description are | |
9162 | automatically disqualified. */ | |
9163 | ||
9779414d DJ |
9164 | /* Do check is_m, though, since it might come from the binary. */ |
9165 | if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m) | |
9166 | continue; | |
9167 | ||
28e97307 DJ |
9168 | /* Found a match. */ |
9169 | break; | |
9170 | } | |
97e03143 | 9171 | |
28e97307 | 9172 | if (best_arch != NULL) |
123dc839 DJ |
9173 | { |
9174 | if (tdesc_data != NULL) | |
9175 | tdesc_data_cleanup (tdesc_data); | |
9176 | return best_arch->gdbarch; | |
9177 | } | |
28e97307 | 9178 | |
8d749320 | 9179 | tdep = XCNEW (struct gdbarch_tdep); |
97e03143 RE |
9180 | gdbarch = gdbarch_alloc (&info, tdep); |
9181 | ||
28e97307 DJ |
9182 | /* Record additional information about the architecture we are defining. |
9183 | These are gdbarch discriminators, like the OSABI. */ | |
9184 | tdep->arm_abi = arm_abi; | |
9185 | tdep->fp_model = fp_model; | |
9779414d | 9186 | tdep->is_m = is_m; |
ff6f572f | 9187 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 9188 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
9189 | gdb_assert (vfp_register_count == 0 |
9190 | || vfp_register_count == 16 | |
9191 | || vfp_register_count == 32); | |
9192 | tdep->vfp_register_count = vfp_register_count; | |
58d6951d DJ |
9193 | tdep->have_vfp_pseudos = have_vfp_pseudos; |
9194 | tdep->have_neon_pseudos = have_neon_pseudos; | |
9195 | tdep->have_neon = have_neon; | |
08216dd7 | 9196 | |
25f8c692 JL |
9197 | arm_register_g_packet_guesses (gdbarch); |
9198 | ||
08216dd7 | 9199 | /* Breakpoints. */ |
9d4fde75 | 9200 | switch (info.byte_order_for_code) |
67255d04 RE |
9201 | { |
9202 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
9203 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
9204 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
9205 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
9206 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
9207 | ||
67255d04 RE |
9208 | break; |
9209 | ||
9210 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
9211 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
9212 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
9213 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
9214 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
9215 | ||
67255d04 RE |
9216 | break; |
9217 | ||
9218 | default: | |
9219 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 9220 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
9221 | } |
9222 | ||
d7b486e7 RE |
9223 | /* On ARM targets char defaults to unsigned. */ |
9224 | set_gdbarch_char_signed (gdbarch, 0); | |
9225 | ||
cca44b1b JB |
9226 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
9227 | of additional scratch space. This setting isn't used for anything beside | |
9228 | displaced stepping at present. */ | |
9229 | set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS); | |
9230 | ||
9df628e0 | 9231 | /* This should be low enough for everything. */ |
97e03143 | 9232 | tdep->lowest_pc = 0x20; |
94c30b78 | 9233 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 9234 | |
7c00367c MK |
9235 | /* The default, for both APCS and AAPCS, is to return small |
9236 | structures in registers. */ | |
9237 | tdep->struct_return = reg_struct_return; | |
9238 | ||
2dd604e7 | 9239 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 9240 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 9241 | |
756fe439 DJ |
9242 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
9243 | ||
148754e5 | 9244 | /* Frame handling. */ |
a262aec2 | 9245 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
9246 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
9247 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
9248 | ||
eb5492fa | 9249 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 9250 | |
34e8f22d | 9251 | /* Address manipulation. */ |
34e8f22d RE |
9252 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
9253 | ||
34e8f22d RE |
9254 | /* Advance PC across function entry code. */ |
9255 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
9256 | ||
c9cf6e20 MG |
9257 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
9258 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 9259 | |
190dce09 UW |
9260 | /* Skip trampolines. */ |
9261 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
9262 | ||
34e8f22d RE |
9263 | /* The stack grows downward. */ |
9264 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
9265 | ||
9266 | /* Breakpoint manipulation. */ | |
9267 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
177321bd DJ |
9268 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
9269 | arm_remote_breakpoint_from_pc); | |
34e8f22d RE |
9270 | |
9271 | /* Information about registers, etc. */ | |
34e8f22d RE |
9272 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
9273 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 9274 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 9275 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 9276 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 9277 | |
ff6f572f DJ |
9278 | /* This "info float" is FPA-specific. Use the generic version if we |
9279 | do not have FPA. */ | |
9280 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
9281 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
9282 | ||
26216b98 | 9283 | /* Internal <-> external register number maps. */ |
ff6f572f | 9284 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
9285 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
9286 | ||
34e8f22d RE |
9287 | set_gdbarch_register_name (gdbarch, arm_register_name); |
9288 | ||
9289 | /* Returning results. */ | |
2af48f68 | 9290 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 9291 | |
03d48a7d RE |
9292 | /* Disassembly. */ |
9293 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
9294 | ||
34e8f22d RE |
9295 | /* Minsymbol frobbing. */ |
9296 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
9297 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
9298 | arm_coff_make_msymbol_special); | |
60c5725c | 9299 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 9300 | |
f9d67f43 DJ |
9301 | /* Thumb-2 IT block support. */ |
9302 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
9303 | arm_adjust_breakpoint_address); | |
9304 | ||
0d5de010 DJ |
9305 | /* Virtual tables. */ |
9306 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
9307 | ||
97e03143 | 9308 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 9309 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 9310 | |
b39cc962 DJ |
9311 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
9312 | ||
eb5492fa | 9313 | /* Add some default predicates. */ |
2ae28aa9 YQ |
9314 | if (is_m) |
9315 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
9316 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
9317 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 9318 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
a262aec2 | 9319 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 9320 | |
97e03143 RE |
9321 | /* Now we have tuned the configuration, set a few final things, |
9322 | based on what the OS ABI has told us. */ | |
9323 | ||
b8926edc DJ |
9324 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
9325 | binaries are always marked. */ | |
9326 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
9327 | tdep->arm_abi = ARM_ABI_APCS; | |
9328 | ||
e3039479 UW |
9329 | /* Watchpoints are not steppable. */ |
9330 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
9331 | ||
b8926edc DJ |
9332 | /* We used to default to FPA for generic ARM, but almost nobody |
9333 | uses that now, and we now provide a way for the user to force | |
9334 | the model. So default to the most useful variant. */ | |
9335 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
9336 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
9337 | ||
9df628e0 RE |
9338 | if (tdep->jb_pc >= 0) |
9339 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
9340 | ||
08216dd7 | 9341 | /* Floating point sizes and format. */ |
8da61cc4 | 9342 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 9343 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 9344 | { |
8da61cc4 DJ |
9345 | set_gdbarch_double_format |
9346 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9347 | set_gdbarch_long_double_format | |
9348 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9349 | } | |
9350 | else | |
9351 | { | |
9352 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
9353 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
9354 | } |
9355 | ||
58d6951d DJ |
9356 | if (have_vfp_pseudos) |
9357 | { | |
9358 | /* NOTE: These are the only pseudo registers used by | |
9359 | the ARM target at the moment. If more are added, a | |
9360 | little more care in numbering will be needed. */ | |
9361 | ||
9362 | int num_pseudos = 32; | |
9363 | if (have_neon_pseudos) | |
9364 | num_pseudos += 16; | |
9365 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
9366 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
9367 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
9368 | } | |
9369 | ||
123dc839 | 9370 | if (tdesc_data) |
58d6951d DJ |
9371 | { |
9372 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
9373 | ||
9779414d | 9374 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
58d6951d DJ |
9375 | |
9376 | /* Override tdesc_register_type to adjust the types of VFP | |
9377 | registers for NEON. */ | |
9378 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
9379 | } | |
123dc839 DJ |
9380 | |
9381 | /* Add standard register aliases. We add aliases even for those | |
9382 | nanes which are used by the current architecture - it's simpler, | |
9383 | and does no harm, since nothing ever lists user registers. */ | |
9384 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
9385 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
9386 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
9387 | ||
39bbf761 RE |
9388 | return gdbarch; |
9389 | } | |
9390 | ||
97e03143 | 9391 | static void |
2af46ca0 | 9392 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 9393 | { |
2af46ca0 | 9394 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
9395 | |
9396 | if (tdep == NULL) | |
9397 | return; | |
9398 | ||
edefbb7c | 9399 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
9400 | (unsigned long) tdep->lowest_pc); |
9401 | } | |
9402 | ||
a78f21af AC |
9403 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
9404 | ||
c906108c | 9405 | void |
ed9a39eb | 9406 | _initialize_arm_tdep (void) |
c906108c | 9407 | { |
bc90b915 FN |
9408 | struct ui_file *stb; |
9409 | long length; | |
26304000 | 9410 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
9411 | const char *setname; |
9412 | const char *setdesc; | |
4bd7b427 | 9413 | const char *const *regnames; |
bc90b915 FN |
9414 | int numregs, i, j; |
9415 | static char *helptext; | |
edefbb7c AC |
9416 | char regdesc[1024], *rdptr = regdesc; |
9417 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 9418 | |
42cf1509 | 9419 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 9420 | |
60c5725c | 9421 | arm_objfile_data_key |
c1bd65d0 | 9422 | = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free); |
60c5725c | 9423 | |
0e9e9abd UW |
9424 | /* Add ourselves to objfile event chain. */ |
9425 | observer_attach_new_objfile (arm_exidx_new_objfile); | |
9426 | arm_exidx_data_key | |
9427 | = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free); | |
9428 | ||
70f80edf JT |
9429 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
9430 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
9431 | bfd_target_elf_flavour, | |
9432 | arm_elf_osabi_sniffer); | |
9433 | ||
9779414d DJ |
9434 | /* Initialize the standard target descriptions. */ |
9435 | initialize_tdesc_arm_with_m (); | |
25f8c692 | 9436 | initialize_tdesc_arm_with_m_fpa_layout (); |
3184d3f9 | 9437 | initialize_tdesc_arm_with_m_vfp_d16 (); |
ef7e8358 UW |
9438 | initialize_tdesc_arm_with_iwmmxt (); |
9439 | initialize_tdesc_arm_with_vfpv2 (); | |
9440 | initialize_tdesc_arm_with_vfpv3 (); | |
9441 | initialize_tdesc_arm_with_neon (); | |
9779414d | 9442 | |
94c30b78 | 9443 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
9444 | num_disassembly_options = get_arm_regname_num_options (); |
9445 | ||
9446 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
9447 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 9448 | _("Various ARM-specific commands."), |
afd7eef0 RE |
9449 | &setarmcmdlist, "set arm ", 0, &setlist); |
9450 | ||
9451 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 9452 | _("Various ARM-specific commands."), |
afd7eef0 | 9453 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 9454 | |
94c30b78 | 9455 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 9456 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 9457 | |
eefe576e AC |
9458 | /* Initialize the array that will be passed to |
9459 | add_setshow_enum_cmd(). */ | |
8d749320 SM |
9460 | valid_disassembly_styles = XNEWVEC (const char *, |
9461 | num_disassembly_options + 1); | |
afd7eef0 | 9462 | for (i = 0; i < num_disassembly_options; i++) |
bc90b915 FN |
9463 | { |
9464 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 9465 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
9466 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
9467 | rdptr += length; | |
9468 | rest -= length; | |
123dc839 DJ |
9469 | /* When we find the default names, tell the disassembler to use |
9470 | them. */ | |
bc90b915 FN |
9471 | if (!strcmp (setname, "std")) |
9472 | { | |
afd7eef0 | 9473 | disassembly_style = setname; |
bc90b915 FN |
9474 | set_arm_regname_option (i); |
9475 | } | |
9476 | } | |
94c30b78 | 9477 | /* Mark the end of valid options. */ |
afd7eef0 | 9478 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 9479 | |
edefbb7c AC |
9480 | /* Create the help text. */ |
9481 | stb = mem_fileopen (); | |
9482 | fprintf_unfiltered (stb, "%s%s%s", | |
9483 | _("The valid values are:\n"), | |
9484 | regdesc, | |
9485 | _("The default is \"std\".")); | |
759ef836 | 9486 | helptext = ui_file_xstrdup (stb, NULL); |
bc90b915 | 9487 | ui_file_delete (stb); |
ed9a39eb | 9488 | |
edefbb7c AC |
9489 | add_setshow_enum_cmd("disassembler", no_class, |
9490 | valid_disassembly_styles, &disassembly_style, | |
9491 | _("Set the disassembly style."), | |
9492 | _("Show the disassembly style."), | |
9493 | helptext, | |
2c5b56ce | 9494 | set_disassembly_style_sfunc, |
0963b4bd MS |
9495 | NULL, /* FIXME: i18n: The disassembly style is |
9496 | \"%s\". */ | |
7376b4c2 | 9497 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
9498 | |
9499 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
9500 | _("Set usage of ARM 32-bit mode."), | |
9501 | _("Show usage of ARM 32-bit mode."), | |
9502 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 9503 | NULL, |
0963b4bd MS |
9504 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
9505 | mode is %s. */ | |
26304000 | 9506 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 9507 | |
fd50bc42 | 9508 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
9509 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
9510 | _("Set the floating point type."), | |
9511 | _("Show the floating point type."), | |
9512 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
9513 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
9514 | fpa - FPA co-processor (GCC compiled).\n\ | |
9515 | softvfp - Software FP with pure-endian doubles.\n\ | |
9516 | vfp - VFP co-processor."), | |
edefbb7c | 9517 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 9518 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 9519 | |
28e97307 DJ |
9520 | /* Add a command to allow the user to force the ABI. */ |
9521 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
9522 | _("Set the ABI."), | |
9523 | _("Show the ABI."), | |
9524 | NULL, arm_set_abi, arm_show_abi, | |
9525 | &setarmcmdlist, &showarmcmdlist); | |
9526 | ||
0428b8f5 DJ |
9527 | /* Add two commands to allow the user to force the assumed |
9528 | execution mode. */ | |
9529 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
9530 | arm_mode_strings, &arm_fallback_mode_string, | |
9531 | _("Set the mode assumed when symbols are unavailable."), | |
9532 | _("Show the mode assumed when symbols are unavailable."), | |
9533 | NULL, NULL, arm_show_fallback_mode, | |
9534 | &setarmcmdlist, &showarmcmdlist); | |
9535 | add_setshow_enum_cmd ("force-mode", class_support, | |
9536 | arm_mode_strings, &arm_force_mode_string, | |
9537 | _("Set the mode assumed even when symbols are available."), | |
9538 | _("Show the mode assumed even when symbols are available."), | |
9539 | NULL, NULL, arm_show_force_mode, | |
9540 | &setarmcmdlist, &showarmcmdlist); | |
9541 | ||
6529d2dd | 9542 | /* Debugging flag. */ |
edefbb7c AC |
9543 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
9544 | _("Set ARM debugging."), | |
9545 | _("Show ARM debugging."), | |
9546 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 9547 | NULL, |
7915a72c | 9548 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 9549 | &setdebuglist, &showdebuglist); |
c906108c | 9550 | } |
72508ac0 PO |
9551 | |
9552 | /* ARM-reversible process record data structures. */ | |
9553 | ||
9554 | #define ARM_INSN_SIZE_BYTES 4 | |
9555 | #define THUMB_INSN_SIZE_BYTES 2 | |
9556 | #define THUMB2_INSN_SIZE_BYTES 4 | |
9557 | ||
9558 | ||
71e396f9 LM |
9559 | /* Position of the bit within a 32-bit ARM instruction |
9560 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
9561 | #define INSN_S_L_BIT_NUM 20 |
9562 | ||
9563 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
9564 | do \ | |
9565 | { \ | |
9566 | unsigned int reg_len = LENGTH; \ | |
9567 | if (reg_len) \ | |
9568 | { \ | |
9569 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
9570 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
9571 | } \ | |
9572 | } \ | |
9573 | while (0) | |
9574 | ||
9575 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
9576 | do \ | |
9577 | { \ | |
9578 | unsigned int mem_len = LENGTH; \ | |
9579 | if (mem_len) \ | |
9580 | { \ | |
9581 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
9582 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
9583 | sizeof(struct arm_mem_r) * LENGTH); \ | |
9584 | } \ | |
9585 | } \ | |
9586 | while (0) | |
9587 | ||
9588 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
9589 | #define INSN_RECORDED(ARM_RECORD) \ | |
9590 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) | |
9591 | ||
9592 | /* ARM memory record structure. */ | |
9593 | struct arm_mem_r | |
9594 | { | |
9595 | uint32_t len; /* Record length. */ | |
bfbbec00 | 9596 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
9597 | }; |
9598 | ||
9599 | /* ARM instruction record contains opcode of current insn | |
9600 | and execution state (before entry to decode_insn()), | |
9601 | contains list of to-be-modified registers and | |
9602 | memory blocks (on return from decode_insn()). */ | |
9603 | ||
9604 | typedef struct insn_decode_record_t | |
9605 | { | |
9606 | struct gdbarch *gdbarch; | |
9607 | struct regcache *regcache; | |
9608 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
9609 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
9610 | uint32_t cond; /* Condition code. */ | |
9611 | uint32_t opcode; /* Insn opcode. */ | |
9612 | uint32_t decode; /* Insn decode bits. */ | |
9613 | uint32_t mem_rec_count; /* No of mem records. */ | |
9614 | uint32_t reg_rec_count; /* No of reg records. */ | |
9615 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
9616 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
9617 | } insn_decode_record; | |
9618 | ||
9619 | ||
9620 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
9621 | ||
9622 | static int | |
9623 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
9624 | { | |
9625 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
9626 | ||
9627 | if (!len) | |
9628 | return 1; | |
9629 | ||
9630 | if (!sbo) | |
9631 | ones = ~ones; | |
9632 | ||
9633 | while (ones) | |
9634 | { | |
9635 | if (!(ones & sbo)) | |
9636 | { | |
9637 | return 0; | |
9638 | } | |
9639 | ones = ones >> 1; | |
9640 | } | |
9641 | return 1; | |
9642 | } | |
9643 | ||
c6ec2b30 OJ |
9644 | enum arm_record_result |
9645 | { | |
9646 | ARM_RECORD_SUCCESS = 0, | |
9647 | ARM_RECORD_FAILURE = 1 | |
9648 | }; | |
9649 | ||
72508ac0 PO |
9650 | typedef enum |
9651 | { | |
9652 | ARM_RECORD_STRH=1, | |
9653 | ARM_RECORD_STRD | |
9654 | } arm_record_strx_t; | |
9655 | ||
9656 | typedef enum | |
9657 | { | |
9658 | ARM_RECORD=1, | |
9659 | THUMB_RECORD, | |
9660 | THUMB2_RECORD | |
9661 | } record_type_t; | |
9662 | ||
9663 | ||
9664 | static int | |
9665 | arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, | |
9666 | uint32_t *record_buf_mem, arm_record_strx_t str_type) | |
9667 | { | |
9668 | ||
9669 | struct regcache *reg_cache = arm_insn_r->regcache; | |
9670 | ULONGEST u_regval[2]= {0}; | |
9671 | ||
9672 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
9673 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
9674 | uint32_t opcode1 = 0; | |
9675 | ||
9676 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
9677 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
9678 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
9679 | ||
9680 | ||
9681 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
9682 | { | |
9683 | /* 1) Handle misc store, immediate offset. */ | |
9684 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9685 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9686 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9687 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
9688 | &u_regval[0]); | |
9689 | if (ARM_PC_REGNUM == reg_src1) | |
9690 | { | |
9691 | /* If R15 was used as Rn, hence current PC+8. */ | |
9692 | u_regval[0] = u_regval[0] + 8; | |
9693 | } | |
9694 | offset_8 = (immed_high << 4) | immed_low; | |
9695 | /* Calculate target store address. */ | |
9696 | if (14 == arm_insn_r->opcode) | |
9697 | { | |
9698 | tgt_mem_addr = u_regval[0] + offset_8; | |
9699 | } | |
9700 | else | |
9701 | { | |
9702 | tgt_mem_addr = u_regval[0] - offset_8; | |
9703 | } | |
9704 | if (ARM_RECORD_STRH == str_type) | |
9705 | { | |
9706 | record_buf_mem[0] = 2; | |
9707 | record_buf_mem[1] = tgt_mem_addr; | |
9708 | arm_insn_r->mem_rec_count = 1; | |
9709 | } | |
9710 | else if (ARM_RECORD_STRD == str_type) | |
9711 | { | |
9712 | record_buf_mem[0] = 4; | |
9713 | record_buf_mem[1] = tgt_mem_addr; | |
9714 | record_buf_mem[2] = 4; | |
9715 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9716 | arm_insn_r->mem_rec_count = 2; | |
9717 | } | |
9718 | } | |
9719 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
9720 | { | |
9721 | /* 2) Store, register offset. */ | |
9722 | /* Get Rm. */ | |
9723 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9724 | /* Get Rn. */ | |
9725 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9726 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9727 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9728 | if (15 == reg_src2) | |
9729 | { | |
9730 | /* If R15 was used as Rn, hence current PC+8. */ | |
9731 | u_regval[0] = u_regval[0] + 8; | |
9732 | } | |
9733 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9734 | if (12 == arm_insn_r->opcode) | |
9735 | { | |
9736 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9737 | } | |
9738 | else | |
9739 | { | |
9740 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9741 | } | |
9742 | if (ARM_RECORD_STRH == str_type) | |
9743 | { | |
9744 | record_buf_mem[0] = 2; | |
9745 | record_buf_mem[1] = tgt_mem_addr; | |
9746 | arm_insn_r->mem_rec_count = 1; | |
9747 | } | |
9748 | else if (ARM_RECORD_STRD == str_type) | |
9749 | { | |
9750 | record_buf_mem[0] = 4; | |
9751 | record_buf_mem[1] = tgt_mem_addr; | |
9752 | record_buf_mem[2] = 4; | |
9753 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9754 | arm_insn_r->mem_rec_count = 2; | |
9755 | } | |
9756 | } | |
9757 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
9758 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
9759 | { | |
9760 | /* 3) Store, immediate pre-indexed. */ | |
9761 | /* 5) Store, immediate post-indexed. */ | |
9762 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9763 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9764 | offset_8 = (immed_high << 4) | immed_low; | |
9765 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9766 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9767 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9768 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
9769 | { | |
9770 | tgt_mem_addr = u_regval[0] + offset_8; | |
9771 | } | |
9772 | else | |
9773 | { | |
9774 | tgt_mem_addr = u_regval[0] - offset_8; | |
9775 | } | |
9776 | if (ARM_RECORD_STRH == str_type) | |
9777 | { | |
9778 | record_buf_mem[0] = 2; | |
9779 | record_buf_mem[1] = tgt_mem_addr; | |
9780 | arm_insn_r->mem_rec_count = 1; | |
9781 | } | |
9782 | else if (ARM_RECORD_STRD == str_type) | |
9783 | { | |
9784 | record_buf_mem[0] = 4; | |
9785 | record_buf_mem[1] = tgt_mem_addr; | |
9786 | record_buf_mem[2] = 4; | |
9787 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9788 | arm_insn_r->mem_rec_count = 2; | |
9789 | } | |
9790 | /* Record Rn also as it changes. */ | |
9791 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9792 | arm_insn_r->reg_rec_count = 1; | |
9793 | } | |
9794 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
9795 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
9796 | { | |
9797 | /* 4) Store, register pre-indexed. */ | |
9798 | /* 6) Store, register post -indexed. */ | |
9799 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9800 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9801 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9802 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9803 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9804 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
9805 | { | |
9806 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9807 | } | |
9808 | else | |
9809 | { | |
9810 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9811 | } | |
9812 | if (ARM_RECORD_STRH == str_type) | |
9813 | { | |
9814 | record_buf_mem[0] = 2; | |
9815 | record_buf_mem[1] = tgt_mem_addr; | |
9816 | arm_insn_r->mem_rec_count = 1; | |
9817 | } | |
9818 | else if (ARM_RECORD_STRD == str_type) | |
9819 | { | |
9820 | record_buf_mem[0] = 4; | |
9821 | record_buf_mem[1] = tgt_mem_addr; | |
9822 | record_buf_mem[2] = 4; | |
9823 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9824 | arm_insn_r->mem_rec_count = 2; | |
9825 | } | |
9826 | /* Record Rn also as it changes. */ | |
9827 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9828 | arm_insn_r->reg_rec_count = 1; | |
9829 | } | |
9830 | return 0; | |
9831 | } | |
9832 | ||
9833 | /* Handling ARM extension space insns. */ | |
9834 | ||
9835 | static int | |
9836 | arm_record_extension_space (insn_decode_record *arm_insn_r) | |
9837 | { | |
9838 | uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */ | |
9839 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; | |
9840 | uint32_t record_buf[8], record_buf_mem[8]; | |
9841 | uint32_t reg_src1 = 0; | |
9842 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
9843 | struct regcache *reg_cache = arm_insn_r->regcache; | |
9844 | ULONGEST u_regval = 0; | |
9845 | ||
9846 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
9847 | /* Handle unconditional insn extension space. */ | |
9848 | ||
9849 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
9850 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9851 | if (arm_insn_r->cond) | |
9852 | { | |
9853 | /* PLD has no affect on architectural state, it just affects | |
9854 | the caches. */ | |
9855 | if (5 == ((opcode1 & 0xE0) >> 5)) | |
9856 | { | |
9857 | /* BLX(1) */ | |
9858 | record_buf[0] = ARM_PS_REGNUM; | |
9859 | record_buf[1] = ARM_LR_REGNUM; | |
9860 | arm_insn_r->reg_rec_count = 2; | |
9861 | } | |
9862 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ | |
9863 | } | |
9864 | ||
9865 | ||
9866 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
9867 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
9868 | { | |
9869 | ret = -1; | |
9870 | /* Undefined instruction on ARM V5; need to handle if later | |
9871 | versions define it. */ | |
9872 | } | |
9873 | ||
9874 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
9875 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9876 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
9877 | ||
9878 | /* Handle arithmetic insn extension space. */ | |
9879 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
9880 | && !INSN_RECORDED(arm_insn_r)) | |
9881 | { | |
9882 | /* Handle MLA(S) and MUL(S). */ | |
9883 | if (0 <= insn_op1 && 3 >= insn_op1) | |
9884 | { | |
9885 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
9886 | record_buf[1] = ARM_PS_REGNUM; | |
9887 | arm_insn_r->reg_rec_count = 2; | |
9888 | } | |
9889 | else if (4 <= insn_op1 && 15 >= insn_op1) | |
9890 | { | |
9891 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
9892 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
9893 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
9894 | record_buf[2] = ARM_PS_REGNUM; | |
9895 | arm_insn_r->reg_rec_count = 3; | |
9896 | } | |
9897 | } | |
9898 | ||
9899 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
9900 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
9901 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
9902 | ||
9903 | /* Handle control insn extension space. */ | |
9904 | ||
9905 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
9906 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
9907 | { | |
9908 | if (!bit (arm_insn_r->arm_insn,25)) | |
9909 | { | |
9910 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
9911 | { | |
9912 | if ((0 == insn_op1) || (2 == insn_op1)) | |
9913 | { | |
9914 | /* MRS. */ | |
9915 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
9916 | arm_insn_r->reg_rec_count = 1; | |
9917 | } | |
9918 | else if (1 == insn_op1) | |
9919 | { | |
9920 | /* CSPR is going to be changed. */ | |
9921 | record_buf[0] = ARM_PS_REGNUM; | |
9922 | arm_insn_r->reg_rec_count = 1; | |
9923 | } | |
9924 | else if (3 == insn_op1) | |
9925 | { | |
9926 | /* SPSR is going to be changed. */ | |
9927 | /* We need to get SPSR value, which is yet to be done. */ | |
9928 | printf_unfiltered (_("Process record does not support " | |
9929 | "instruction 0x%0x at address %s.\n"), | |
9930 | arm_insn_r->arm_insn, | |
9931 | paddress (arm_insn_r->gdbarch, | |
9932 | arm_insn_r->this_addr)); | |
9933 | return -1; | |
9934 | } | |
9935 | } | |
9936 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
9937 | { | |
9938 | if (1 == insn_op1) | |
9939 | { | |
9940 | /* BX. */ | |
9941 | record_buf[0] = ARM_PS_REGNUM; | |
9942 | arm_insn_r->reg_rec_count = 1; | |
9943 | } | |
9944 | else if (3 == insn_op1) | |
9945 | { | |
9946 | /* CLZ. */ | |
9947 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
9948 | arm_insn_r->reg_rec_count = 1; | |
9949 | } | |
9950 | } | |
9951 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
9952 | { | |
9953 | /* BLX. */ | |
9954 | record_buf[0] = ARM_PS_REGNUM; | |
9955 | record_buf[1] = ARM_LR_REGNUM; | |
9956 | arm_insn_r->reg_rec_count = 2; | |
9957 | } | |
9958 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
9959 | { | |
9960 | /* QADD, QSUB, QDADD, QDSUB */ | |
9961 | record_buf[0] = ARM_PS_REGNUM; | |
9962 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
9963 | arm_insn_r->reg_rec_count = 2; | |
9964 | } | |
9965 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
9966 | { | |
9967 | /* BKPT. */ | |
9968 | record_buf[0] = ARM_PS_REGNUM; | |
9969 | record_buf[1] = ARM_LR_REGNUM; | |
9970 | arm_insn_r->reg_rec_count = 2; | |
9971 | ||
9972 | /* Save SPSR also;how? */ | |
9973 | printf_unfiltered (_("Process record does not support " | |
9974 | "instruction 0x%0x at address %s.\n"), | |
9975 | arm_insn_r->arm_insn, | |
9976 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
9977 | return -1; | |
9978 | } | |
9979 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
9980 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
9981 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
9982 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
9983 | ) | |
9984 | { | |
9985 | if (0 == insn_op1 || 1 == insn_op1) | |
9986 | { | |
9987 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
9988 | /* We dont do optimization for SMULW<y> where we | |
9989 | need only Rd. */ | |
9990 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
9991 | record_buf[1] = ARM_PS_REGNUM; | |
9992 | arm_insn_r->reg_rec_count = 2; | |
9993 | } | |
9994 | else if (2 == insn_op1) | |
9995 | { | |
9996 | /* SMLAL<x><y>. */ | |
9997 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
9998 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
9999 | arm_insn_r->reg_rec_count = 2; | |
10000 | } | |
10001 | else if (3 == insn_op1) | |
10002 | { | |
10003 | /* SMUL<x><y>. */ | |
10004 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10005 | arm_insn_r->reg_rec_count = 1; | |
10006 | } | |
10007 | } | |
10008 | } | |
10009 | else | |
10010 | { | |
10011 | /* MSR : immediate form. */ | |
10012 | if (1 == insn_op1) | |
10013 | { | |
10014 | /* CSPR is going to be changed. */ | |
10015 | record_buf[0] = ARM_PS_REGNUM; | |
10016 | arm_insn_r->reg_rec_count = 1; | |
10017 | } | |
10018 | else if (3 == insn_op1) | |
10019 | { | |
10020 | /* SPSR is going to be changed. */ | |
10021 | /* we need to get SPSR value, which is yet to be done */ | |
10022 | printf_unfiltered (_("Process record does not support " | |
10023 | "instruction 0x%0x at address %s.\n"), | |
10024 | arm_insn_r->arm_insn, | |
10025 | paddress (arm_insn_r->gdbarch, | |
10026 | arm_insn_r->this_addr)); | |
10027 | return -1; | |
10028 | } | |
10029 | } | |
10030 | } | |
10031 | ||
10032 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10033 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
10034 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
10035 | ||
10036 | /* Handle load/store insn extension space. */ | |
10037 | ||
10038 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
10039 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
10040 | && !INSN_RECORDED(arm_insn_r)) | |
10041 | { | |
10042 | /* SWP/SWPB. */ | |
10043 | if (0 == insn_op1) | |
10044 | { | |
10045 | /* These insn, changes register and memory as well. */ | |
10046 | /* SWP or SWPB insn. */ | |
10047 | /* Get memory address given by Rn. */ | |
10048 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10049 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
10050 | /* SWP insn ?, swaps word. */ | |
10051 | if (8 == arm_insn_r->opcode) | |
10052 | { | |
10053 | record_buf_mem[0] = 4; | |
10054 | } | |
10055 | else | |
10056 | { | |
10057 | /* SWPB insn, swaps only byte. */ | |
10058 | record_buf_mem[0] = 1; | |
10059 | } | |
10060 | record_buf_mem[1] = u_regval; | |
10061 | arm_insn_r->mem_rec_count = 1; | |
10062 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10063 | arm_insn_r->reg_rec_count = 1; | |
10064 | } | |
10065 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
10066 | { | |
10067 | /* STRH. */ | |
10068 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10069 | ARM_RECORD_STRH); | |
10070 | } | |
10071 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
10072 | { | |
10073 | /* LDRD. */ | |
10074 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10075 | record_buf[1] = record_buf[0] + 1; | |
10076 | arm_insn_r->reg_rec_count = 2; | |
10077 | } | |
10078 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
10079 | { | |
10080 | /* STRD. */ | |
10081 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10082 | ARM_RECORD_STRD); | |
10083 | } | |
10084 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) | |
10085 | { | |
10086 | /* LDRH, LDRSB, LDRSH. */ | |
10087 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10088 | arm_insn_r->reg_rec_count = 1; | |
10089 | } | |
10090 | ||
10091 | } | |
10092 | ||
10093 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
10094 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
10095 | && !INSN_RECORDED(arm_insn_r)) | |
10096 | { | |
10097 | ret = -1; | |
10098 | /* Handle coprocessor insn extension space. */ | |
10099 | } | |
10100 | ||
10101 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
10102 | if (-1 == ret) | |
10103 | printf_unfiltered (_("Process record does not support instruction x%0x " | |
10104 | "at address %s.\n"),arm_insn_r->arm_insn, | |
10105 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
10106 | ||
10107 | ||
10108 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10109 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10110 | ||
10111 | return ret; | |
10112 | } | |
10113 | ||
10114 | /* Handling opcode 000 insns. */ | |
10115 | ||
10116 | static int | |
10117 | arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) | |
10118 | { | |
10119 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10120 | uint32_t record_buf[8], record_buf_mem[8]; | |
10121 | ULONGEST u_regval[2] = {0}; | |
10122 | ||
10123 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
10124 | uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0; | |
10125 | uint32_t opcode1 = 0; | |
10126 | ||
10127 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10128 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10129 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
10130 | ||
10131 | /* Data processing insn /multiply insn. */ | |
10132 | if (9 == arm_insn_r->decode | |
10133 | && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
10134 | || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode))) | |
10135 | { | |
10136 | /* Handle multiply instructions. */ | |
10137 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
10138 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
10139 | { | |
10140 | /* Handle MLA and MUL. */ | |
10141 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10142 | record_buf[1] = ARM_PS_REGNUM; | |
10143 | arm_insn_r->reg_rec_count = 2; | |
10144 | } | |
10145 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
10146 | { | |
10147 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
10148 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10149 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10150 | record_buf[2] = ARM_PS_REGNUM; | |
10151 | arm_insn_r->reg_rec_count = 3; | |
10152 | } | |
10153 | } | |
10154 | else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
10155 | && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode)) | |
10156 | { | |
10157 | /* Handle misc load insns, as 20th bit (L = 1). */ | |
10158 | /* LDR insn has a capability to do branching, if | |
10159 | MOV LR, PC is precceded by LDR insn having Rn as R15 | |
10160 | in that case, it emulates branch and link insn, and hence we | |
10161 | need to save CSPR and PC as well. I am not sure this is right | |
10162 | place; as opcode = 010 LDR insn make this happen, if R15 was | |
10163 | used. */ | |
10164 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
10165 | if (15 != reg_dest) | |
10166 | { | |
10167 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10168 | arm_insn_r->reg_rec_count = 1; | |
10169 | } | |
10170 | else | |
10171 | { | |
10172 | record_buf[0] = reg_dest; | |
10173 | record_buf[1] = ARM_PS_REGNUM; | |
10174 | arm_insn_r->reg_rec_count = 2; | |
10175 | } | |
10176 | } | |
10177 | else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
10178 | && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0) | |
10179 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
10180 | && 2 == bits (arm_insn_r->arm_insn, 20, 21)) | |
10181 | { | |
10182 | /* Handle MSR insn. */ | |
10183 | if (9 == arm_insn_r->opcode) | |
10184 | { | |
10185 | /* CSPR is going to be changed. */ | |
10186 | record_buf[0] = ARM_PS_REGNUM; | |
10187 | arm_insn_r->reg_rec_count = 1; | |
10188 | } | |
10189 | else | |
10190 | { | |
10191 | /* SPSR is going to be changed. */ | |
10192 | /* How to read SPSR value? */ | |
10193 | printf_unfiltered (_("Process record does not support instruction " | |
10194 | "0x%0x at address %s.\n"), | |
10195 | arm_insn_r->arm_insn, | |
10196 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
10197 | return -1; | |
10198 | } | |
10199 | } | |
10200 | else if (9 == arm_insn_r->decode | |
10201 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10202 | && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10203 | { | |
10204 | /* Handling SWP, SWPB. */ | |
10205 | /* These insn, changes register and memory as well. */ | |
10206 | /* SWP or SWPB insn. */ | |
10207 | ||
10208 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10209 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10210 | /* SWP insn ?, swaps word. */ | |
10211 | if (8 == arm_insn_r->opcode) | |
10212 | { | |
10213 | record_buf_mem[0] = 4; | |
10214 | } | |
10215 | else | |
10216 | { | |
10217 | /* SWPB insn, swaps only byte. */ | |
10218 | record_buf_mem[0] = 1; | |
10219 | } | |
10220 | record_buf_mem[1] = u_regval[0]; | |
10221 | arm_insn_r->mem_rec_count = 1; | |
10222 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10223 | arm_insn_r->reg_rec_count = 1; | |
10224 | } | |
10225 | else if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
10226 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10227 | { | |
10228 | /* Handle BLX, branch and link/exchange. */ | |
10229 | if (9 == arm_insn_r->opcode) | |
10230 | { | |
10231 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
10232 | and R14 stores the return address. */ | |
10233 | record_buf[0] = ARM_PS_REGNUM; | |
10234 | record_buf[1] = ARM_LR_REGNUM; | |
10235 | arm_insn_r->reg_rec_count = 2; | |
10236 | } | |
10237 | } | |
10238 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
10239 | { | |
10240 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
10241 | /* CPSR is changed to be executed in ARM state, disabling normal | |
10242 | interrupts, entering abort mode. */ | |
10243 | /* According to high vector configuration PC is set. */ | |
10244 | /* user hit breakpoint and type reverse, in | |
10245 | that case, we need to go back with previous CPSR and | |
10246 | Program Counter. */ | |
10247 | record_buf[0] = ARM_PS_REGNUM; | |
10248 | record_buf[1] = ARM_LR_REGNUM; | |
10249 | arm_insn_r->reg_rec_count = 2; | |
10250 | ||
10251 | /* Save SPSR also; how? */ | |
10252 | printf_unfiltered (_("Process record does not support instruction " | |
10253 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
10254 | paddress (arm_insn_r->gdbarch, | |
10255 | arm_insn_r->this_addr)); | |
10256 | return -1; | |
10257 | } | |
10258 | else if (11 == arm_insn_r->decode | |
10259 | && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10260 | { | |
10261 | /* Handle enhanced store insns and DSP insns (e.g. LDRD). */ | |
10262 | ||
10263 | /* Handle str(x) insn */ | |
10264 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10265 | ARM_RECORD_STRH); | |
10266 | } | |
10267 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
10268 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10269 | { | |
10270 | /* Handle BX, branch and link/exchange. */ | |
10271 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
10272 | record_buf[0] = ARM_PS_REGNUM; | |
10273 | arm_insn_r->reg_rec_count = 1; | |
10274 | } | |
10275 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
10276 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
10277 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
10278 | { | |
10279 | /* Count leading zeros: CLZ. */ | |
10280 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10281 | arm_insn_r->reg_rec_count = 1; | |
10282 | } | |
10283 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
10284 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10285 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
10286 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0) | |
10287 | ) | |
10288 | { | |
10289 | /* Handle MRS insn. */ | |
10290 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10291 | arm_insn_r->reg_rec_count = 1; | |
10292 | } | |
10293 | else if (arm_insn_r->opcode <= 15) | |
10294 | { | |
10295 | /* Normal data processing insns. */ | |
10296 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
10297 | register, which is specified by 13-16 decode. */ | |
10298 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10299 | record_buf[1] = ARM_PS_REGNUM; | |
10300 | arm_insn_r->reg_rec_count = 2; | |
10301 | } | |
10302 | else | |
10303 | { | |
10304 | return -1; | |
10305 | } | |
10306 | ||
10307 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10308 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10309 | return 0; | |
10310 | } | |
10311 | ||
10312 | /* Handling opcode 001 insns. */ | |
10313 | ||
10314 | static int | |
10315 | arm_record_data_proc_imm (insn_decode_record *arm_insn_r) | |
10316 | { | |
10317 | uint32_t record_buf[8], record_buf_mem[8]; | |
10318 | ||
10319 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10320 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10321 | ||
10322 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
10323 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
10324 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
10325 | ) | |
10326 | { | |
10327 | /* Handle MSR insn. */ | |
10328 | if (9 == arm_insn_r->opcode) | |
10329 | { | |
10330 | /* CSPR is going to be changed. */ | |
10331 | record_buf[0] = ARM_PS_REGNUM; | |
10332 | arm_insn_r->reg_rec_count = 1; | |
10333 | } | |
10334 | else | |
10335 | { | |
10336 | /* SPSR is going to be changed. */ | |
10337 | } | |
10338 | } | |
10339 | else if (arm_insn_r->opcode <= 15) | |
10340 | { | |
10341 | /* Normal data processing insns. */ | |
10342 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
10343 | register, which is specified by 13-16 decode. */ | |
10344 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10345 | record_buf[1] = ARM_PS_REGNUM; | |
10346 | arm_insn_r->reg_rec_count = 2; | |
10347 | } | |
10348 | else | |
10349 | { | |
10350 | return -1; | |
10351 | } | |
10352 | ||
10353 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10354 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10355 | return 0; | |
10356 | } | |
10357 | ||
71e396f9 | 10358 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
10359 | |
10360 | static int | |
10361 | arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) | |
10362 | { | |
10363 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10364 | ||
71e396f9 LM |
10365 | uint32_t reg_base , reg_dest; |
10366 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 10367 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
10368 | unsigned char wback; |
10369 | ULONGEST u_regval; | |
72508ac0 | 10370 | |
71e396f9 LM |
10371 | /* Calculate wback. */ |
10372 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
10373 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 10374 | |
71e396f9 LM |
10375 | arm_insn_r->reg_rec_count = 0; |
10376 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
10377 | |
10378 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10379 | { | |
71e396f9 LM |
10380 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
10381 | and LDRT. */ | |
10382 | ||
72508ac0 | 10383 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
10384 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
10385 | ||
10386 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
10387 | preceeds a LDR instruction having R15 as reg_base, it | |
10388 | emulates a branch and link instruction, and hence we need to save | |
10389 | CPSR and PC as well. */ | |
10390 | if (ARM_PC_REGNUM == reg_dest) | |
10391 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
10392 | ||
10393 | /* If wback is true, also save the base register, which is going to be | |
10394 | written to. */ | |
10395 | if (wback) | |
10396 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10397 | } |
10398 | else | |
10399 | { | |
71e396f9 LM |
10400 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
10401 | ||
72508ac0 | 10402 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
10403 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
10404 | ||
10405 | /* Handle bit U. */ | |
72508ac0 | 10406 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
10407 | { |
10408 | /* U == 1: Add the offset. */ | |
10409 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
10410 | } | |
72508ac0 | 10411 | else |
71e396f9 LM |
10412 | { |
10413 | /* U == 0: subtract the offset. */ | |
10414 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
10415 | } | |
10416 | ||
10417 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
10418 | bytes. */ | |
10419 | if (bit (arm_insn_r->arm_insn, 22)) | |
10420 | { | |
10421 | /* STRB and STRBT: 1 byte. */ | |
10422 | record_buf_mem[0] = 1; | |
10423 | } | |
10424 | else | |
10425 | { | |
10426 | /* STR and STRT: 4 bytes. */ | |
10427 | record_buf_mem[0] = 4; | |
10428 | } | |
10429 | ||
10430 | /* Handle bit P. */ | |
10431 | if (bit (arm_insn_r->arm_insn, 24)) | |
10432 | record_buf_mem[1] = tgt_mem_addr; | |
10433 | else | |
10434 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 10435 | |
72508ac0 PO |
10436 | arm_insn_r->mem_rec_count = 1; |
10437 | ||
71e396f9 LM |
10438 | /* If wback is true, also save the base register, which is going to be |
10439 | written to. */ | |
10440 | if (wback) | |
10441 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10442 | } |
10443 | ||
10444 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10445 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10446 | return 0; | |
10447 | } | |
10448 | ||
10449 | /* Handling opcode 011 insns. */ | |
10450 | ||
10451 | static int | |
10452 | arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) | |
10453 | { | |
10454 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10455 | ||
10456 | uint32_t shift_imm = 0; | |
10457 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
10458 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
10459 | uint32_t record_buf[8], record_buf_mem[8]; | |
10460 | ||
10461 | LONGEST s_word; | |
10462 | ULONGEST u_regval[2]; | |
10463 | ||
10464 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10465 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10466 | ||
10467 | /* Handle enhanced store insns and LDRD DSP insn, | |
10468 | order begins according to addressing modes for store insns | |
10469 | STRH insn. */ | |
10470 | ||
10471 | /* LDR or STR? */ | |
10472 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10473 | { | |
10474 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
10475 | /* LDR insn has a capability to do branching, if | |
10476 | MOV LR, PC is precedded by LDR insn having Rn as R15 | |
10477 | in that case, it emulates branch and link insn, and hence we | |
10478 | need to save CSPR and PC as well. */ | |
10479 | if (15 != reg_dest) | |
10480 | { | |
10481 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10482 | arm_insn_r->reg_rec_count = 1; | |
10483 | } | |
10484 | else | |
10485 | { | |
10486 | record_buf[0] = reg_dest; | |
10487 | record_buf[1] = ARM_PS_REGNUM; | |
10488 | arm_insn_r->reg_rec_count = 2; | |
10489 | } | |
10490 | } | |
10491 | else | |
10492 | { | |
10493 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
10494 | { | |
10495 | /* Store insn, register offset and register pre-indexed, | |
10496 | register post-indexed. */ | |
10497 | /* Get Rm. */ | |
10498 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10499 | /* Get Rn. */ | |
10500 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10501 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
10502 | , &u_regval[0]); | |
10503 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
10504 | , &u_regval[1]); | |
10505 | if (15 == reg_src2) | |
10506 | { | |
10507 | /* If R15 was used as Rn, hence current PC+8. */ | |
10508 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
10509 | u_regval[0] = u_regval[0] + 8; | |
10510 | } | |
10511 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10512 | /* U == 1. */ | |
10513 | if (bit (arm_insn_r->arm_insn, 23)) | |
10514 | { | |
10515 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10516 | } | |
10517 | else | |
10518 | { | |
10519 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10520 | } | |
10521 | ||
10522 | switch (arm_insn_r->opcode) | |
10523 | { | |
10524 | /* STR. */ | |
10525 | case 8: | |
10526 | case 12: | |
10527 | /* STR. */ | |
10528 | case 9: | |
10529 | case 13: | |
10530 | /* STRT. */ | |
10531 | case 1: | |
10532 | case 5: | |
10533 | /* STR. */ | |
10534 | case 0: | |
10535 | case 4: | |
10536 | record_buf_mem[0] = 4; | |
10537 | break; | |
10538 | ||
10539 | /* STRB. */ | |
10540 | case 10: | |
10541 | case 14: | |
10542 | /* STRB. */ | |
10543 | case 11: | |
10544 | case 15: | |
10545 | /* STRBT. */ | |
10546 | case 3: | |
10547 | case 7: | |
10548 | /* STRB. */ | |
10549 | case 2: | |
10550 | case 6: | |
10551 | record_buf_mem[0] = 1; | |
10552 | break; | |
10553 | ||
10554 | default: | |
10555 | gdb_assert_not_reached ("no decoding pattern found"); | |
10556 | break; | |
10557 | } | |
10558 | record_buf_mem[1] = tgt_mem_addr; | |
10559 | arm_insn_r->mem_rec_count = 1; | |
10560 | ||
10561 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10562 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10563 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10564 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10565 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10566 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10567 | ) | |
10568 | { | |
10569 | /* Rn is going to be changed in pre-indexed mode and | |
10570 | post-indexed mode as well. */ | |
10571 | record_buf[0] = reg_src2; | |
10572 | arm_insn_r->reg_rec_count = 1; | |
10573 | } | |
10574 | } | |
10575 | else | |
10576 | { | |
10577 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
10578 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
10579 | /* Get Rm. */ | |
10580 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10581 | /* Get Rn. */ | |
10582 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10583 | /* Get shift_imm. */ | |
10584 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
10585 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10586 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
10587 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10588 | /* Offset_12 used as shift. */ | |
10589 | switch (offset_12) | |
10590 | { | |
10591 | case 0: | |
10592 | /* Offset_12 used as index. */ | |
10593 | offset_12 = u_regval[0] << shift_imm; | |
10594 | break; | |
10595 | ||
10596 | case 1: | |
10597 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
10598 | break; | |
10599 | ||
10600 | case 2: | |
10601 | if (!shift_imm) | |
10602 | { | |
10603 | if (bit (u_regval[0], 31)) | |
10604 | { | |
10605 | offset_12 = 0xFFFFFFFF; | |
10606 | } | |
10607 | else | |
10608 | { | |
10609 | offset_12 = 0; | |
10610 | } | |
10611 | } | |
10612 | else | |
10613 | { | |
10614 | /* This is arithmetic shift. */ | |
10615 | offset_12 = s_word >> shift_imm; | |
10616 | } | |
10617 | break; | |
10618 | ||
10619 | case 3: | |
10620 | if (!shift_imm) | |
10621 | { | |
10622 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
10623 | &u_regval[1]); | |
10624 | /* Get C flag value and shift it by 31. */ | |
10625 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
10626 | | (u_regval[0]) >> 1); | |
10627 | } | |
10628 | else | |
10629 | { | |
10630 | offset_12 = (u_regval[0] >> shift_imm) \ | |
10631 | | (u_regval[0] << | |
10632 | (sizeof(uint32_t) - shift_imm)); | |
10633 | } | |
10634 | break; | |
10635 | ||
10636 | default: | |
10637 | gdb_assert_not_reached ("no decoding pattern found"); | |
10638 | break; | |
10639 | } | |
10640 | ||
10641 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10642 | /* bit U set. */ | |
10643 | if (bit (arm_insn_r->arm_insn, 23)) | |
10644 | { | |
10645 | tgt_mem_addr = u_regval[1] + offset_12; | |
10646 | } | |
10647 | else | |
10648 | { | |
10649 | tgt_mem_addr = u_regval[1] - offset_12; | |
10650 | } | |
10651 | ||
10652 | switch (arm_insn_r->opcode) | |
10653 | { | |
10654 | /* STR. */ | |
10655 | case 8: | |
10656 | case 12: | |
10657 | /* STR. */ | |
10658 | case 9: | |
10659 | case 13: | |
10660 | /* STRT. */ | |
10661 | case 1: | |
10662 | case 5: | |
10663 | /* STR. */ | |
10664 | case 0: | |
10665 | case 4: | |
10666 | record_buf_mem[0] = 4; | |
10667 | break; | |
10668 | ||
10669 | /* STRB. */ | |
10670 | case 10: | |
10671 | case 14: | |
10672 | /* STRB. */ | |
10673 | case 11: | |
10674 | case 15: | |
10675 | /* STRBT. */ | |
10676 | case 3: | |
10677 | case 7: | |
10678 | /* STRB. */ | |
10679 | case 2: | |
10680 | case 6: | |
10681 | record_buf_mem[0] = 1; | |
10682 | break; | |
10683 | ||
10684 | default: | |
10685 | gdb_assert_not_reached ("no decoding pattern found"); | |
10686 | break; | |
10687 | } | |
10688 | record_buf_mem[1] = tgt_mem_addr; | |
10689 | arm_insn_r->mem_rec_count = 1; | |
10690 | ||
10691 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10692 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10693 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10694 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10695 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10696 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10697 | ) | |
10698 | { | |
10699 | /* Rn is going to be changed in register scaled pre-indexed | |
10700 | mode,and scaled post indexed mode. */ | |
10701 | record_buf[0] = reg_src2; | |
10702 | arm_insn_r->reg_rec_count = 1; | |
10703 | } | |
10704 | } | |
10705 | } | |
10706 | ||
10707 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10708 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10709 | return 0; | |
10710 | } | |
10711 | ||
71e396f9 | 10712 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
10713 | |
10714 | static int | |
10715 | arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) | |
10716 | { | |
10717 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
10718 | uint32_t register_count = 0, register_bits; |
10719 | uint32_t reg_base, addr_mode; | |
72508ac0 | 10720 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
10721 | uint32_t wback; |
10722 | ULONGEST u_regval; | |
72508ac0 | 10723 | |
71e396f9 LM |
10724 | /* Fetch the list of registers. */ |
10725 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
10726 | arm_insn_r->reg_rec_count = 0; | |
10727 | ||
10728 | /* Fetch the base register that contains the address we are loading data | |
10729 | to. */ | |
10730 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 10731 | |
71e396f9 LM |
10732 | /* Calculate wback. */ |
10733 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
10734 | |
10735 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10736 | { | |
71e396f9 | 10737 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 10738 | |
71e396f9 | 10739 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 10740 | while (register_bits) |
71e396f9 LM |
10741 | { |
10742 | if (register_bits & 0x00000001) | |
10743 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
10744 | register_bits = register_bits >> 1; | |
10745 | register_count++; | |
10746 | } | |
72508ac0 | 10747 | |
71e396f9 LM |
10748 | |
10749 | /* If wback is true, also save the base register, which is going to be | |
10750 | written to. */ | |
10751 | if (wback) | |
10752 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
10753 | ||
10754 | /* Save the CPSR register. */ | |
10755 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
10756 | } |
10757 | else | |
10758 | { | |
71e396f9 | 10759 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 10760 | |
71e396f9 LM |
10761 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
10762 | ||
10763 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
10764 | ||
10765 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 10766 | while (register_bits) |
71e396f9 LM |
10767 | { |
10768 | if (register_bits & 0x00000001) | |
10769 | register_count++; | |
10770 | register_bits = register_bits >> 1; | |
10771 | } | |
72508ac0 PO |
10772 | |
10773 | switch (addr_mode) | |
71e396f9 LM |
10774 | { |
10775 | /* STMDA (STMED): Decrement after. */ | |
10776 | case 0: | |
10777 | record_buf_mem[1] = (uint32_t) u_regval | |
10778 | - register_count * INT_REGISTER_SIZE + 4; | |
10779 | break; | |
10780 | /* STM (STMIA, STMEA): Increment after. */ | |
10781 | case 1: | |
10782 | record_buf_mem[1] = (uint32_t) u_regval; | |
10783 | break; | |
10784 | /* STMDB (STMFD): Decrement before. */ | |
10785 | case 2: | |
10786 | record_buf_mem[1] = (uint32_t) u_regval | |
10787 | - register_count * INT_REGISTER_SIZE; | |
10788 | break; | |
10789 | /* STMIB (STMFA): Increment before. */ | |
10790 | case 3: | |
10791 | record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE; | |
10792 | break; | |
10793 | default: | |
10794 | gdb_assert_not_reached ("no decoding pattern found"); | |
10795 | break; | |
10796 | } | |
72508ac0 | 10797 | |
71e396f9 LM |
10798 | record_buf_mem[0] = register_count * INT_REGISTER_SIZE; |
10799 | arm_insn_r->mem_rec_count = 1; | |
10800 | ||
10801 | /* If wback is true, also save the base register, which is going to be | |
10802 | written to. */ | |
10803 | if (wback) | |
10804 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10805 | } |
10806 | ||
10807 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10808 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10809 | return 0; | |
10810 | } | |
10811 | ||
10812 | /* Handling opcode 101 insns. */ | |
10813 | ||
10814 | static int | |
10815 | arm_record_b_bl (insn_decode_record *arm_insn_r) | |
10816 | { | |
10817 | uint32_t record_buf[8]; | |
10818 | ||
10819 | /* Handle B, BL, BLX(1) insns. */ | |
10820 | /* B simply branches so we do nothing here. */ | |
10821 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
10822 | extension space. */ | |
10823 | if (bit (arm_insn_r->arm_insn, 24)) | |
10824 | { | |
10825 | record_buf[0] = ARM_LR_REGNUM; | |
10826 | arm_insn_r->reg_rec_count = 1; | |
10827 | } | |
10828 | ||
10829 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10830 | ||
10831 | return 0; | |
10832 | } | |
10833 | ||
10834 | /* Handling opcode 110 insns. */ | |
10835 | ||
10836 | static int | |
c6ec2b30 | 10837 | arm_record_unsupported_insn (insn_decode_record *arm_insn_r) |
72508ac0 PO |
10838 | { |
10839 | printf_unfiltered (_("Process record does not support instruction " | |
10840 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
10841 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
10842 | ||
10843 | return -1; | |
10844 | } | |
10845 | ||
5a578da5 OJ |
10846 | /* Record handler for vector data transfer instructions. */ |
10847 | ||
10848 | static int | |
10849 | arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) | |
10850 | { | |
10851 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
10852 | uint32_t record_buf[4]; | |
10853 | ||
10854 | const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); | |
10855 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); | |
10856 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
10857 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
10858 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
10859 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
10860 | ||
10861 | /* Handle VMOV instruction. */ | |
10862 | if (bit_l && bit_c) | |
10863 | { | |
10864 | record_buf[0] = reg_t; | |
10865 | arm_insn_r->reg_rec_count = 1; | |
10866 | } | |
10867 | else if (bit_l && !bit_c) | |
10868 | { | |
10869 | /* Handle VMOV instruction. */ | |
10870 | if (bits_a == 0x00) | |
10871 | { | |
10872 | if (bit (arm_insn_r->arm_insn, 20)) | |
10873 | record_buf[0] = reg_t; | |
10874 | else | |
10875 | record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | | |
10876 | (reg_v << 1)); | |
10877 | ||
10878 | arm_insn_r->reg_rec_count = 1; | |
10879 | } | |
10880 | /* Handle VMRS instruction. */ | |
10881 | else if (bits_a == 0x07) | |
10882 | { | |
10883 | if (reg_t == 15) | |
10884 | reg_t = ARM_PS_REGNUM; | |
10885 | ||
10886 | record_buf[0] = reg_t; | |
10887 | arm_insn_r->reg_rec_count = 1; | |
10888 | } | |
10889 | } | |
10890 | else if (!bit_l && !bit_c) | |
10891 | { | |
10892 | /* Handle VMOV instruction. */ | |
10893 | if (bits_a == 0x00) | |
10894 | { | |
10895 | if (bit (arm_insn_r->arm_insn, 20)) | |
10896 | record_buf[0] = reg_t; | |
10897 | else | |
10898 | record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | | |
10899 | (reg_v << 1)); | |
10900 | ||
10901 | arm_insn_r->reg_rec_count = 1; | |
10902 | } | |
10903 | /* Handle VMSR instruction. */ | |
10904 | else if (bits_a == 0x07) | |
10905 | { | |
10906 | record_buf[0] = ARM_FPSCR_REGNUM; | |
10907 | arm_insn_r->reg_rec_count = 1; | |
10908 | } | |
10909 | } | |
10910 | else if (!bit_l && bit_c) | |
10911 | { | |
10912 | /* Handle VMOV instruction. */ | |
10913 | if (!(bits_a & 0x04)) | |
10914 | { | |
10915 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
10916 | + ARM_D0_REGNUM; | |
10917 | arm_insn_r->reg_rec_count = 1; | |
10918 | } | |
10919 | /* Handle VDUP instruction. */ | |
10920 | else | |
10921 | { | |
10922 | if (bit (arm_insn_r->arm_insn, 21)) | |
10923 | { | |
10924 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
10925 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
10926 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
10927 | arm_insn_r->reg_rec_count = 2; | |
10928 | } | |
10929 | else | |
10930 | { | |
10931 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
10932 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
10933 | arm_insn_r->reg_rec_count = 1; | |
10934 | } | |
10935 | } | |
10936 | } | |
10937 | ||
10938 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10939 | return 0; | |
10940 | } | |
10941 | ||
f20f80dd OJ |
10942 | /* Record handler for extension register load/store instructions. */ |
10943 | ||
10944 | static int | |
10945 | arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) | |
10946 | { | |
10947 | uint32_t opcode, single_reg; | |
10948 | uint8_t op_vldm_vstm; | |
10949 | uint32_t record_buf[8], record_buf_mem[128]; | |
10950 | ULONGEST u_regval = 0; | |
10951 | ||
10952 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10953 | const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); | |
10954 | ||
10955 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
10956 | single_reg = bit (arm_insn_r->arm_insn, 8); | |
10957 | op_vldm_vstm = opcode & 0x1b; | |
10958 | ||
10959 | /* Handle VMOV instructions. */ | |
10960 | if ((opcode & 0x1e) == 0x04) | |
10961 | { | |
10962 | if (bit (arm_insn_r->arm_insn, 4)) | |
10963 | { | |
10964 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10965 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
10966 | arm_insn_r->reg_rec_count = 2; | |
10967 | } | |
10968 | else | |
10969 | { | |
10970 | uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) | |
10971 | | bit (arm_insn_r->arm_insn, 5); | |
10972 | ||
10973 | if (!single_reg) | |
10974 | { | |
10975 | record_buf[0] = num_regs + reg_m; | |
10976 | record_buf[1] = num_regs + reg_m + 1; | |
10977 | arm_insn_r->reg_rec_count = 2; | |
10978 | } | |
10979 | else | |
10980 | { | |
10981 | record_buf[0] = reg_m + ARM_D0_REGNUM; | |
10982 | arm_insn_r->reg_rec_count = 1; | |
10983 | } | |
10984 | } | |
10985 | } | |
10986 | /* Handle VSTM and VPUSH instructions. */ | |
10987 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
10988 | || op_vldm_vstm == 0x12) | |
10989 | { | |
10990 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
10991 | uint32_t memory_index = 0; | |
10992 | ||
10993 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
10994 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
10995 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
10996 | imm_off32 = imm_off8 << 24; | |
10997 | memory_count = imm_off8; | |
10998 | ||
10999 | if (bit (arm_insn_r->arm_insn, 23)) | |
11000 | start_address = u_regval; | |
11001 | else | |
11002 | start_address = u_regval - imm_off32; | |
11003 | ||
11004 | if (bit (arm_insn_r->arm_insn, 21)) | |
11005 | { | |
11006 | record_buf[0] = reg_rn; | |
11007 | arm_insn_r->reg_rec_count = 1; | |
11008 | } | |
11009 | ||
11010 | while (memory_count > 0) | |
11011 | { | |
11012 | if (!single_reg) | |
11013 | { | |
11014 | record_buf_mem[memory_index] = start_address; | |
11015 | record_buf_mem[memory_index + 1] = 4; | |
11016 | start_address = start_address + 4; | |
11017 | memory_index = memory_index + 2; | |
11018 | } | |
11019 | else | |
11020 | { | |
11021 | record_buf_mem[memory_index] = start_address; | |
11022 | record_buf_mem[memory_index + 1] = 4; | |
11023 | record_buf_mem[memory_index + 2] = start_address + 4; | |
11024 | record_buf_mem[memory_index + 3] = 4; | |
11025 | start_address = start_address + 8; | |
11026 | memory_index = memory_index + 4; | |
11027 | } | |
11028 | memory_count--; | |
11029 | } | |
11030 | arm_insn_r->mem_rec_count = (memory_index >> 1); | |
11031 | } | |
11032 | /* Handle VLDM instructions. */ | |
11033 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
11034 | || op_vldm_vstm == 0x13) | |
11035 | { | |
11036 | uint32_t reg_count, reg_vd; | |
11037 | uint32_t reg_index = 0; | |
11038 | ||
11039 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11040 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
11041 | ||
11042 | if (single_reg) | |
11043 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
11044 | else | |
11045 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
11046 | ||
11047 | if (bit (arm_insn_r->arm_insn, 21)) | |
11048 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); | |
11049 | ||
11050 | while (reg_count > 0) | |
11051 | { | |
11052 | if (single_reg) | |
11053 | record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; | |
11054 | else | |
11055 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
11056 | ||
11057 | reg_count--; | |
11058 | } | |
11059 | arm_insn_r->reg_rec_count = reg_index; | |
11060 | } | |
11061 | /* VSTR Vector store register. */ | |
11062 | else if ((opcode & 0x13) == 0x10) | |
11063 | { | |
11064 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
11065 | uint32_t memory_index = 0; | |
11066 | ||
11067 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11068 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11069 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
11070 | imm_off32 = imm_off8 << 24; | |
11071 | memory_count = imm_off8; | |
11072 | ||
11073 | if (bit (arm_insn_r->arm_insn, 23)) | |
11074 | start_address = u_regval + imm_off32; | |
11075 | else | |
11076 | start_address = u_regval - imm_off32; | |
11077 | ||
11078 | if (single_reg) | |
11079 | { | |
11080 | record_buf_mem[memory_index] = start_address; | |
11081 | record_buf_mem[memory_index + 1] = 4; | |
11082 | arm_insn_r->mem_rec_count = 1; | |
11083 | } | |
11084 | else | |
11085 | { | |
11086 | record_buf_mem[memory_index] = start_address; | |
11087 | record_buf_mem[memory_index + 1] = 4; | |
11088 | record_buf_mem[memory_index + 2] = start_address + 4; | |
11089 | record_buf_mem[memory_index + 3] = 4; | |
11090 | arm_insn_r->mem_rec_count = 2; | |
11091 | } | |
11092 | } | |
11093 | /* VLDR Vector load register. */ | |
11094 | else if ((opcode & 0x13) == 0x11) | |
11095 | { | |
11096 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11097 | ||
11098 | if (!single_reg) | |
11099 | { | |
11100 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
11101 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
11102 | } | |
11103 | else | |
11104 | { | |
11105 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
11106 | record_buf[0] = num_regs + reg_vd; | |
11107 | } | |
11108 | arm_insn_r->reg_rec_count = 1; | |
11109 | } | |
11110 | ||
11111 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11112 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11113 | return 0; | |
11114 | } | |
11115 | ||
851f26ae OJ |
11116 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
11117 | ||
11118 | static int | |
11119 | arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) | |
11120 | { | |
11121 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
11122 | uint32_t record_buf[4]; | |
11123 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
11124 | enum insn_types curr_insn_type = INSN_INV; | |
11125 | ||
11126 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11127 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11128 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11129 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
11130 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
11131 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
11132 | opc1 = opc1 & 0x04; | |
11133 | ||
11134 | /* Handle VMLA, VMLS. */ | |
11135 | if (opc1 == 0x00) | |
11136 | { | |
11137 | if (bit (arm_insn_r->arm_insn, 10)) | |
11138 | { | |
11139 | if (bit (arm_insn_r->arm_insn, 6)) | |
11140 | curr_insn_type = INSN_T0; | |
11141 | else | |
11142 | curr_insn_type = INSN_T1; | |
11143 | } | |
11144 | else | |
11145 | { | |
11146 | if (dp_op_sz) | |
11147 | curr_insn_type = INSN_T1; | |
11148 | else | |
11149 | curr_insn_type = INSN_T2; | |
11150 | } | |
11151 | } | |
11152 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
11153 | else if (opc1 == 0x01) | |
11154 | { | |
11155 | if (dp_op_sz) | |
11156 | curr_insn_type = INSN_T1; | |
11157 | else | |
11158 | curr_insn_type = INSN_T2; | |
11159 | } | |
11160 | /* Handle VMUL. */ | |
11161 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
11162 | { | |
11163 | if (bit (arm_insn_r->arm_insn, 10)) | |
11164 | { | |
11165 | if (bit (arm_insn_r->arm_insn, 6)) | |
11166 | curr_insn_type = INSN_T0; | |
11167 | else | |
11168 | curr_insn_type = INSN_T1; | |
11169 | } | |
11170 | else | |
11171 | { | |
11172 | if (dp_op_sz) | |
11173 | curr_insn_type = INSN_T1; | |
11174 | else | |
11175 | curr_insn_type = INSN_T2; | |
11176 | } | |
11177 | } | |
11178 | /* Handle VADD, VSUB. */ | |
11179 | else if (opc1 == 0x03) | |
11180 | { | |
11181 | if (!bit (arm_insn_r->arm_insn, 9)) | |
11182 | { | |
11183 | if (bit (arm_insn_r->arm_insn, 6)) | |
11184 | curr_insn_type = INSN_T0; | |
11185 | else | |
11186 | curr_insn_type = INSN_T1; | |
11187 | } | |
11188 | else | |
11189 | { | |
11190 | if (dp_op_sz) | |
11191 | curr_insn_type = INSN_T1; | |
11192 | else | |
11193 | curr_insn_type = INSN_T2; | |
11194 | } | |
11195 | } | |
11196 | /* Handle VDIV. */ | |
11197 | else if (opc1 == 0x0b) | |
11198 | { | |
11199 | if (dp_op_sz) | |
11200 | curr_insn_type = INSN_T1; | |
11201 | else | |
11202 | curr_insn_type = INSN_T2; | |
11203 | } | |
11204 | /* Handle all other vfp data processing instructions. */ | |
11205 | else if (opc1 == 0x0b) | |
11206 | { | |
11207 | /* Handle VMOV. */ | |
11208 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
11209 | { | |
11210 | if (bit (arm_insn_r->arm_insn, 4)) | |
11211 | { | |
11212 | if (bit (arm_insn_r->arm_insn, 6)) | |
11213 | curr_insn_type = INSN_T0; | |
11214 | else | |
11215 | curr_insn_type = INSN_T1; | |
11216 | } | |
11217 | else | |
11218 | { | |
11219 | if (dp_op_sz) | |
11220 | curr_insn_type = INSN_T1; | |
11221 | else | |
11222 | curr_insn_type = INSN_T2; | |
11223 | } | |
11224 | } | |
11225 | /* Handle VNEG and VABS. */ | |
11226 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
11227 | || (opc2 == 0x00 && opc3 == 0x03)) | |
11228 | { | |
11229 | if (!bit (arm_insn_r->arm_insn, 11)) | |
11230 | { | |
11231 | if (bit (arm_insn_r->arm_insn, 6)) | |
11232 | curr_insn_type = INSN_T0; | |
11233 | else | |
11234 | curr_insn_type = INSN_T1; | |
11235 | } | |
11236 | else | |
11237 | { | |
11238 | if (dp_op_sz) | |
11239 | curr_insn_type = INSN_T1; | |
11240 | else | |
11241 | curr_insn_type = INSN_T2; | |
11242 | } | |
11243 | } | |
11244 | /* Handle VSQRT. */ | |
11245 | else if (opc2 == 0x01 && opc3 == 0x03) | |
11246 | { | |
11247 | if (dp_op_sz) | |
11248 | curr_insn_type = INSN_T1; | |
11249 | else | |
11250 | curr_insn_type = INSN_T2; | |
11251 | } | |
11252 | /* Handle VCVT. */ | |
11253 | else if (opc2 == 0x07 && opc3 == 0x03) | |
11254 | { | |
11255 | if (!dp_op_sz) | |
11256 | curr_insn_type = INSN_T1; | |
11257 | else | |
11258 | curr_insn_type = INSN_T2; | |
11259 | } | |
11260 | else if (opc3 & 0x01) | |
11261 | { | |
11262 | /* Handle VCVT. */ | |
11263 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
11264 | { | |
11265 | if (!bit (arm_insn_r->arm_insn, 18)) | |
11266 | curr_insn_type = INSN_T2; | |
11267 | else | |
11268 | { | |
11269 | if (dp_op_sz) | |
11270 | curr_insn_type = INSN_T1; | |
11271 | else | |
11272 | curr_insn_type = INSN_T2; | |
11273 | } | |
11274 | } | |
11275 | /* Handle VCVT. */ | |
11276 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
11277 | { | |
11278 | if (dp_op_sz) | |
11279 | curr_insn_type = INSN_T1; | |
11280 | else | |
11281 | curr_insn_type = INSN_T2; | |
11282 | } | |
11283 | /* Handle VCVTB, VCVTT. */ | |
11284 | else if ((opc2 & 0x0e) == 0x02) | |
11285 | curr_insn_type = INSN_T2; | |
11286 | /* Handle VCMP, VCMPE. */ | |
11287 | else if ((opc2 & 0x0e) == 0x04) | |
11288 | curr_insn_type = INSN_T3; | |
11289 | } | |
11290 | } | |
11291 | ||
11292 | switch (curr_insn_type) | |
11293 | { | |
11294 | case INSN_T0: | |
11295 | reg_vd = reg_vd | (bit_d << 4); | |
11296 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11297 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
11298 | arm_insn_r->reg_rec_count = 2; | |
11299 | break; | |
11300 | ||
11301 | case INSN_T1: | |
11302 | reg_vd = reg_vd | (bit_d << 4); | |
11303 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11304 | arm_insn_r->reg_rec_count = 1; | |
11305 | break; | |
11306 | ||
11307 | case INSN_T2: | |
11308 | reg_vd = (reg_vd << 1) | bit_d; | |
11309 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11310 | arm_insn_r->reg_rec_count = 1; | |
11311 | break; | |
11312 | ||
11313 | case INSN_T3: | |
11314 | record_buf[0] = ARM_FPSCR_REGNUM; | |
11315 | arm_insn_r->reg_rec_count = 1; | |
11316 | break; | |
11317 | ||
11318 | default: | |
11319 | gdb_assert_not_reached ("no decoding pattern found"); | |
11320 | break; | |
11321 | } | |
11322 | ||
11323 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11324 | return 0; | |
11325 | } | |
11326 | ||
60cc5e93 OJ |
11327 | /* Handling opcode 110 insns. */ |
11328 | ||
11329 | static int | |
11330 | arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) | |
11331 | { | |
11332 | uint32_t op, op1, op1_sbit, op1_ebit, coproc; | |
11333 | ||
11334 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
11335 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
11336 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
11337 | ||
11338 | if ((coproc & 0x0e) == 0x0a) | |
11339 | { | |
11340 | /* Handle extension register ld/st instructions. */ | |
11341 | if (!(op1 & 0x20)) | |
f20f80dd | 11342 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11343 | |
11344 | /* 64-bit transfers between arm core and extension registers. */ | |
11345 | if ((op1 & 0x3e) == 0x04) | |
f20f80dd | 11346 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11347 | } |
11348 | else | |
11349 | { | |
11350 | /* Handle coprocessor ld/st instructions. */ | |
11351 | if (!(op1 & 0x3a)) | |
11352 | { | |
11353 | /* Store. */ | |
11354 | if (!op1_ebit) | |
11355 | return arm_record_unsupported_insn (arm_insn_r); | |
11356 | else | |
11357 | /* Load. */ | |
11358 | return arm_record_unsupported_insn (arm_insn_r); | |
11359 | } | |
11360 | ||
11361 | /* Move to coprocessor from two arm core registers. */ | |
11362 | if (op1 == 0x4) | |
11363 | return arm_record_unsupported_insn (arm_insn_r); | |
11364 | ||
11365 | /* Move to two arm core registers from coprocessor. */ | |
11366 | if (op1 == 0x5) | |
11367 | { | |
11368 | uint32_t reg_t[2]; | |
11369 | ||
11370 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11371 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11372 | arm_insn_r->reg_rec_count = 2; | |
11373 | ||
11374 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); | |
11375 | return 0; | |
11376 | } | |
11377 | } | |
11378 | return arm_record_unsupported_insn (arm_insn_r); | |
11379 | } | |
11380 | ||
72508ac0 PO |
11381 | /* Handling opcode 111 insns. */ |
11382 | ||
11383 | static int | |
11384 | arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) | |
11385 | { | |
60cc5e93 | 11386 | uint32_t op, op1_sbit, op1_ebit, coproc; |
72508ac0 PO |
11387 | struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); |
11388 | struct regcache *reg_cache = arm_insn_r->regcache; | |
97dfe206 | 11389 | ULONGEST u_regval = 0; |
72508ac0 PO |
11390 | |
11391 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 OJ |
11392 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
11393 | op1_sbit = bit (arm_insn_r->arm_insn, 24); | |
11394 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
11395 | op = bit (arm_insn_r->arm_insn, 4); | |
97dfe206 OJ |
11396 | |
11397 | /* Handle arm SWI/SVC system call instructions. */ | |
60cc5e93 | 11398 | if (op1_sbit) |
97dfe206 OJ |
11399 | { |
11400 | if (tdep->arm_syscall_record != NULL) | |
11401 | { | |
11402 | ULONGEST svc_operand, svc_number; | |
11403 | ||
11404 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); | |
11405 | ||
11406 | if (svc_operand) /* OABI. */ | |
11407 | svc_number = svc_operand - 0x900000; | |
11408 | else /* EABI. */ | |
11409 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
11410 | ||
60cc5e93 | 11411 | return tdep->arm_syscall_record (reg_cache, svc_number); |
97dfe206 OJ |
11412 | } |
11413 | else | |
11414 | { | |
11415 | printf_unfiltered (_("no syscall record support\n")); | |
60cc5e93 | 11416 | return -1; |
97dfe206 OJ |
11417 | } |
11418 | } | |
60cc5e93 OJ |
11419 | |
11420 | if ((coproc & 0x0e) == 0x0a) | |
11421 | { | |
11422 | /* VFP data-processing instructions. */ | |
11423 | if (!op1_sbit && !op) | |
851f26ae | 11424 | return arm_record_vfp_data_proc_insn (arm_insn_r); |
60cc5e93 OJ |
11425 | |
11426 | /* Advanced SIMD, VFP instructions. */ | |
11427 | if (!op1_sbit && op) | |
5a578da5 | 11428 | return arm_record_vdata_transfer_insn (arm_insn_r); |
60cc5e93 | 11429 | } |
97dfe206 OJ |
11430 | else |
11431 | { | |
60cc5e93 OJ |
11432 | /* Coprocessor data operations. */ |
11433 | if (!op1_sbit && !op) | |
11434 | return arm_record_unsupported_insn (arm_insn_r); | |
11435 | ||
11436 | /* Move to Coprocessor from ARM core register. */ | |
11437 | if (!op1_sbit && !op1_ebit && op) | |
11438 | return arm_record_unsupported_insn (arm_insn_r); | |
11439 | ||
11440 | /* Move to arm core register from coprocessor. */ | |
11441 | if (!op1_sbit && op1_ebit && op) | |
11442 | { | |
11443 | uint32_t record_buf[1]; | |
11444 | ||
11445 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11446 | if (record_buf[0] == 15) | |
11447 | record_buf[0] = ARM_PS_REGNUM; | |
11448 | ||
11449 | arm_insn_r->reg_rec_count = 1; | |
11450 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
11451 | record_buf); | |
11452 | return 0; | |
11453 | } | |
97dfe206 | 11454 | } |
72508ac0 | 11455 | |
60cc5e93 | 11456 | return arm_record_unsupported_insn (arm_insn_r); |
72508ac0 PO |
11457 | } |
11458 | ||
11459 | /* Handling opcode 000 insns. */ | |
11460 | ||
11461 | static int | |
11462 | thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) | |
11463 | { | |
11464 | uint32_t record_buf[8]; | |
11465 | uint32_t reg_src1 = 0; | |
11466 | ||
11467 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11468 | ||
11469 | record_buf[0] = ARM_PS_REGNUM; | |
11470 | record_buf[1] = reg_src1; | |
11471 | thumb_insn_r->reg_rec_count = 2; | |
11472 | ||
11473 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11474 | ||
11475 | return 0; | |
11476 | } | |
11477 | ||
11478 | ||
11479 | /* Handling opcode 001 insns. */ | |
11480 | ||
11481 | static int | |
11482 | thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) | |
11483 | { | |
11484 | uint32_t record_buf[8]; | |
11485 | uint32_t reg_src1 = 0; | |
11486 | ||
11487 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11488 | ||
11489 | record_buf[0] = ARM_PS_REGNUM; | |
11490 | record_buf[1] = reg_src1; | |
11491 | thumb_insn_r->reg_rec_count = 2; | |
11492 | ||
11493 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11494 | ||
11495 | return 0; | |
11496 | } | |
11497 | ||
11498 | /* Handling opcode 010 insns. */ | |
11499 | ||
11500 | static int | |
11501 | thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) | |
11502 | { | |
11503 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11504 | uint32_t record_buf[8], record_buf_mem[8]; | |
11505 | ||
11506 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
11507 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
11508 | ||
11509 | ULONGEST u_regval[2] = {0}; | |
11510 | ||
11511 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
11512 | ||
11513 | if (bit (thumb_insn_r->arm_insn, 12)) | |
11514 | { | |
11515 | /* Handle load/store register offset. */ | |
11516 | opcode2 = bits (thumb_insn_r->arm_insn, 9, 10); | |
11517 | if (opcode2 >= 12 && opcode2 <= 15) | |
11518 | { | |
11519 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
11520 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
11521 | record_buf[0] = reg_src1; | |
11522 | thumb_insn_r->reg_rec_count = 1; | |
11523 | } | |
11524 | else if (opcode2 >= 8 && opcode2 <= 10) | |
11525 | { | |
11526 | /* STR(2), STRB(2), STRH(2) . */ | |
11527 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11528 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
11529 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11530 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11531 | if (8 == opcode2) | |
11532 | record_buf_mem[0] = 4; /* STR (2). */ | |
11533 | else if (10 == opcode2) | |
11534 | record_buf_mem[0] = 1; /* STRB (2). */ | |
11535 | else if (9 == opcode2) | |
11536 | record_buf_mem[0] = 2; /* STRH (2). */ | |
11537 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
11538 | thumb_insn_r->mem_rec_count = 1; | |
11539 | } | |
11540 | } | |
11541 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
11542 | { | |
11543 | /* Handle load from literal pool. */ | |
11544 | /* LDR(3). */ | |
11545 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11546 | record_buf[0] = reg_src1; | |
11547 | thumb_insn_r->reg_rec_count = 1; | |
11548 | } | |
11549 | else if (opcode1) | |
11550 | { | |
11551 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); | |
11552 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11553 | if ((3 == opcode2) && (!opcode3)) | |
11554 | { | |
11555 | /* Branch with exchange. */ | |
11556 | record_buf[0] = ARM_PS_REGNUM; | |
11557 | thumb_insn_r->reg_rec_count = 1; | |
11558 | } | |
11559 | else | |
11560 | { | |
11561 | /* Format 8; special data processing insns. */ | |
11562 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11563 | record_buf[0] = ARM_PS_REGNUM; | |
11564 | record_buf[1] = reg_src1; | |
11565 | thumb_insn_r->reg_rec_count = 2; | |
11566 | } | |
11567 | } | |
11568 | else | |
11569 | { | |
11570 | /* Format 5; data processing insns. */ | |
11571 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11572 | if (bit (thumb_insn_r->arm_insn, 7)) | |
11573 | { | |
11574 | reg_src1 = reg_src1 + 8; | |
11575 | } | |
11576 | record_buf[0] = ARM_PS_REGNUM; | |
11577 | record_buf[1] = reg_src1; | |
11578 | thumb_insn_r->reg_rec_count = 2; | |
11579 | } | |
11580 | ||
11581 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11582 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
11583 | record_buf_mem); | |
11584 | ||
11585 | return 0; | |
11586 | } | |
11587 | ||
11588 | /* Handling opcode 001 insns. */ | |
11589 | ||
11590 | static int | |
11591 | thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) | |
11592 | { | |
11593 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11594 | uint32_t record_buf[8], record_buf_mem[8]; | |
11595 | ||
11596 | uint32_t reg_src1 = 0; | |
11597 | uint32_t opcode = 0, immed_5 = 0; | |
11598 | ||
11599 | ULONGEST u_regval = 0; | |
11600 | ||
11601 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11602 | ||
11603 | if (opcode) | |
11604 | { | |
11605 | /* LDR(1). */ | |
11606 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11607 | record_buf[0] = reg_src1; | |
11608 | thumb_insn_r->reg_rec_count = 1; | |
11609 | } | |
11610 | else | |
11611 | { | |
11612 | /* STR(1). */ | |
11613 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11614 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
11615 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11616 | record_buf_mem[0] = 4; | |
11617 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
11618 | thumb_insn_r->mem_rec_count = 1; | |
11619 | } | |
11620 | ||
11621 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11622 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
11623 | record_buf_mem); | |
11624 | ||
11625 | return 0; | |
11626 | } | |
11627 | ||
11628 | /* Handling opcode 100 insns. */ | |
11629 | ||
11630 | static int | |
11631 | thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) | |
11632 | { | |
11633 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11634 | uint32_t record_buf[8], record_buf_mem[8]; | |
11635 | ||
11636 | uint32_t reg_src1 = 0; | |
11637 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
11638 | ||
11639 | ULONGEST u_regval = 0; | |
11640 | ||
11641 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11642 | ||
11643 | if (3 == opcode) | |
11644 | { | |
11645 | /* LDR(4). */ | |
11646 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11647 | record_buf[0] = reg_src1; | |
11648 | thumb_insn_r->reg_rec_count = 1; | |
11649 | } | |
11650 | else if (1 == opcode) | |
11651 | { | |
11652 | /* LDRH(1). */ | |
11653 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11654 | record_buf[0] = reg_src1; | |
11655 | thumb_insn_r->reg_rec_count = 1; | |
11656 | } | |
11657 | else if (2 == opcode) | |
11658 | { | |
11659 | /* STR(3). */ | |
11660 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
11661 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
11662 | record_buf_mem[0] = 4; | |
11663 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
11664 | thumb_insn_r->mem_rec_count = 1; | |
11665 | } | |
11666 | else if (0 == opcode) | |
11667 | { | |
11668 | /* STRH(1). */ | |
11669 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
11670 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11671 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11672 | record_buf_mem[0] = 2; | |
11673 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
11674 | thumb_insn_r->mem_rec_count = 1; | |
11675 | } | |
11676 | ||
11677 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11678 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
11679 | record_buf_mem); | |
11680 | ||
11681 | return 0; | |
11682 | } | |
11683 | ||
11684 | /* Handling opcode 101 insns. */ | |
11685 | ||
11686 | static int | |
11687 | thumb_record_misc (insn_decode_record *thumb_insn_r) | |
11688 | { | |
11689 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11690 | ||
11691 | uint32_t opcode = 0, opcode1 = 0, opcode2 = 0; | |
11692 | uint32_t register_bits = 0, register_count = 0; | |
11693 | uint32_t register_list[8] = {0}, index = 0, start_address = 0; | |
11694 | uint32_t record_buf[24], record_buf_mem[48]; | |
11695 | uint32_t reg_src1; | |
11696 | ||
11697 | ULONGEST u_regval = 0; | |
11698 | ||
11699 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11700 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
11701 | opcode2 = bits (thumb_insn_r->arm_insn, 9, 12); | |
11702 | ||
11703 | if (14 == opcode2) | |
11704 | { | |
11705 | /* POP. */ | |
11706 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
11707 | while (register_bits) | |
f969241e OJ |
11708 | { |
11709 | if (register_bits & 0x00000001) | |
11710 | record_buf[index++] = register_count; | |
11711 | register_bits = register_bits >> 1; | |
11712 | register_count++; | |
11713 | } | |
11714 | record_buf[index++] = ARM_PS_REGNUM; | |
11715 | record_buf[index++] = ARM_SP_REGNUM; | |
11716 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
11717 | } |
11718 | else if (10 == opcode2) | |
11719 | { | |
11720 | /* PUSH. */ | |
11721 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
9904a494 | 11722 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); |
72508ac0 PO |
11723 | while (register_bits) |
11724 | { | |
11725 | if (register_bits & 0x00000001) | |
11726 | register_count++; | |
11727 | register_bits = register_bits >> 1; | |
11728 | } | |
11729 | start_address = u_regval - \ | |
11730 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
11731 | thumb_insn_r->mem_rec_count = register_count; | |
11732 | while (register_count) | |
11733 | { | |
11734 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
11735 | record_buf_mem[(register_count * 2) - 2] = 4; | |
11736 | start_address = start_address + 4; | |
11737 | register_count--; | |
11738 | } | |
11739 | record_buf[0] = ARM_SP_REGNUM; | |
11740 | thumb_insn_r->reg_rec_count = 1; | |
11741 | } | |
11742 | else if (0x1E == opcode1) | |
11743 | { | |
11744 | /* BKPT insn. */ | |
11745 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
11746 | /* CPSR is changed to be executed in ARM state, disabling normal | |
11747 | interrupts, entering abort mode. */ | |
11748 | /* According to high vector configuration PC is set. */ | |
11749 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
11750 | previous CPSR and Program Counter. */ | |
11751 | record_buf[0] = ARM_PS_REGNUM; | |
11752 | record_buf[1] = ARM_LR_REGNUM; | |
11753 | thumb_insn_r->reg_rec_count = 2; | |
11754 | /* We need to save SPSR value, which is not yet done. */ | |
11755 | printf_unfiltered (_("Process record does not support instruction " | |
11756 | "0x%0x at address %s.\n"), | |
11757 | thumb_insn_r->arm_insn, | |
11758 | paddress (thumb_insn_r->gdbarch, | |
11759 | thumb_insn_r->this_addr)); | |
11760 | return -1; | |
11761 | } | |
11762 | else if ((0 == opcode) || (1 == opcode)) | |
11763 | { | |
11764 | /* ADD(5), ADD(6). */ | |
11765 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11766 | record_buf[0] = reg_src1; | |
11767 | thumb_insn_r->reg_rec_count = 1; | |
11768 | } | |
11769 | else if (2 == opcode) | |
11770 | { | |
11771 | /* ADD(7), SUB(4). */ | |
11772 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11773 | record_buf[0] = ARM_SP_REGNUM; | |
11774 | thumb_insn_r->reg_rec_count = 1; | |
11775 | } | |
11776 | ||
11777 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11778 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
11779 | record_buf_mem); | |
11780 | ||
11781 | return 0; | |
11782 | } | |
11783 | ||
11784 | /* Handling opcode 110 insns. */ | |
11785 | ||
11786 | static int | |
11787 | thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) | |
11788 | { | |
11789 | struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch); | |
11790 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11791 | ||
11792 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
11793 | uint32_t reg_src1 = 0; | |
11794 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
11795 | uint32_t register_list[8] = {0}, index = 0, start_address = 0; | |
11796 | uint32_t record_buf[24], record_buf_mem[48]; | |
11797 | ||
11798 | ULONGEST u_regval = 0; | |
11799 | ||
11800 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
11801 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
11802 | ||
11803 | if (1 == opcode2) | |
11804 | { | |
11805 | ||
11806 | /* LDMIA. */ | |
11807 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
11808 | /* Get Rn. */ | |
11809 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11810 | while (register_bits) | |
11811 | { | |
11812 | if (register_bits & 0x00000001) | |
f969241e | 11813 | record_buf[index++] = register_count; |
72508ac0 | 11814 | register_bits = register_bits >> 1; |
f969241e | 11815 | register_count++; |
72508ac0 | 11816 | } |
f969241e OJ |
11817 | record_buf[index++] = reg_src1; |
11818 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
11819 | } |
11820 | else if (0 == opcode2) | |
11821 | { | |
11822 | /* It handles both STMIA. */ | |
11823 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
11824 | /* Get Rn. */ | |
11825 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11826 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11827 | while (register_bits) | |
11828 | { | |
11829 | if (register_bits & 0x00000001) | |
11830 | register_count++; | |
11831 | register_bits = register_bits >> 1; | |
11832 | } | |
11833 | start_address = u_regval; | |
11834 | thumb_insn_r->mem_rec_count = register_count; | |
11835 | while (register_count) | |
11836 | { | |
11837 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
11838 | record_buf_mem[(register_count * 2) - 2] = 4; | |
11839 | start_address = start_address + 4; | |
11840 | register_count--; | |
11841 | } | |
11842 | } | |
11843 | else if (0x1F == opcode1) | |
11844 | { | |
11845 | /* Handle arm syscall insn. */ | |
97dfe206 | 11846 | if (tdep->arm_syscall_record != NULL) |
72508ac0 | 11847 | { |
97dfe206 OJ |
11848 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); |
11849 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
72508ac0 PO |
11850 | } |
11851 | else | |
11852 | { | |
11853 | printf_unfiltered (_("no syscall record support\n")); | |
11854 | return -1; | |
11855 | } | |
11856 | } | |
11857 | ||
11858 | /* B (1), conditional branch is automatically taken care in process_record, | |
11859 | as PC is saved there. */ | |
11860 | ||
11861 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11862 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
11863 | record_buf_mem); | |
11864 | ||
11865 | return ret; | |
11866 | } | |
11867 | ||
11868 | /* Handling opcode 111 insns. */ | |
11869 | ||
11870 | static int | |
11871 | thumb_record_branch (insn_decode_record *thumb_insn_r) | |
11872 | { | |
11873 | uint32_t record_buf[8]; | |
11874 | uint32_t bits_h = 0; | |
11875 | ||
11876 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
11877 | ||
11878 | if (2 == bits_h || 3 == bits_h) | |
11879 | { | |
11880 | /* BL */ | |
11881 | record_buf[0] = ARM_LR_REGNUM; | |
11882 | thumb_insn_r->reg_rec_count = 1; | |
11883 | } | |
11884 | else if (1 == bits_h) | |
11885 | { | |
11886 | /* BLX(1). */ | |
11887 | record_buf[0] = ARM_PS_REGNUM; | |
11888 | record_buf[1] = ARM_LR_REGNUM; | |
11889 | thumb_insn_r->reg_rec_count = 2; | |
11890 | } | |
11891 | ||
11892 | /* B(2) is automatically taken care in process_record, as PC is | |
11893 | saved there. */ | |
11894 | ||
11895 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11896 | ||
11897 | return 0; | |
11898 | } | |
11899 | ||
c6ec2b30 OJ |
11900 | /* Handler for thumb2 load/store multiple instructions. */ |
11901 | ||
11902 | static int | |
11903 | thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) | |
11904 | { | |
11905 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
11906 | ||
11907 | uint32_t reg_rn, op; | |
11908 | uint32_t register_bits = 0, register_count = 0; | |
11909 | uint32_t index = 0, start_address = 0; | |
11910 | uint32_t record_buf[24], record_buf_mem[48]; | |
11911 | ||
11912 | ULONGEST u_regval = 0; | |
11913 | ||
11914 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
11915 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
11916 | ||
11917 | if (0 == op || 3 == op) | |
11918 | { | |
11919 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11920 | { | |
11921 | /* Handle RFE instruction. */ | |
11922 | record_buf[0] = ARM_PS_REGNUM; | |
11923 | thumb2_insn_r->reg_rec_count = 1; | |
11924 | } | |
11925 | else | |
11926 | { | |
11927 | /* Handle SRS instruction after reading banked SP. */ | |
11928 | return arm_record_unsupported_insn (thumb2_insn_r); | |
11929 | } | |
11930 | } | |
11931 | else if (1 == op || 2 == op) | |
11932 | { | |
11933 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11934 | { | |
11935 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
11936 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
11937 | while (register_bits) | |
11938 | { | |
11939 | if (register_bits & 0x00000001) | |
11940 | record_buf[index++] = register_count; | |
11941 | ||
11942 | register_count++; | |
11943 | register_bits = register_bits >> 1; | |
11944 | } | |
11945 | record_buf[index++] = reg_rn; | |
11946 | record_buf[index++] = ARM_PS_REGNUM; | |
11947 | thumb2_insn_r->reg_rec_count = index; | |
11948 | } | |
11949 | else | |
11950 | { | |
11951 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
11952 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
11953 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11954 | while (register_bits) | |
11955 | { | |
11956 | if (register_bits & 0x00000001) | |
11957 | register_count++; | |
11958 | ||
11959 | register_bits = register_bits >> 1; | |
11960 | } | |
11961 | ||
11962 | if (1 == op) | |
11963 | { | |
11964 | /* Start address calculation for LDMDB/LDMEA. */ | |
11965 | start_address = u_regval; | |
11966 | } | |
11967 | else if (2 == op) | |
11968 | { | |
11969 | /* Start address calculation for LDMDB/LDMEA. */ | |
11970 | start_address = u_regval - register_count * 4; | |
11971 | } | |
11972 | ||
11973 | thumb2_insn_r->mem_rec_count = register_count; | |
11974 | while (register_count) | |
11975 | { | |
11976 | record_buf_mem[register_count * 2 - 1] = start_address; | |
11977 | record_buf_mem[register_count * 2 - 2] = 4; | |
11978 | start_address = start_address + 4; | |
11979 | register_count--; | |
11980 | } | |
11981 | record_buf[0] = reg_rn; | |
11982 | record_buf[1] = ARM_PS_REGNUM; | |
11983 | thumb2_insn_r->reg_rec_count = 2; | |
11984 | } | |
11985 | } | |
11986 | ||
11987 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
11988 | record_buf_mem); | |
11989 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
11990 | record_buf); | |
11991 | return ARM_RECORD_SUCCESS; | |
11992 | } | |
11993 | ||
11994 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
11995 | instructions. */ | |
11996 | ||
11997 | static int | |
11998 | thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) | |
11999 | { | |
12000 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12001 | ||
12002 | uint32_t reg_rd, reg_rn, offset_imm; | |
12003 | uint32_t reg_dest1, reg_dest2; | |
12004 | uint32_t address, offset_addr; | |
12005 | uint32_t record_buf[8], record_buf_mem[8]; | |
12006 | uint32_t op1, op2, op3; | |
12007 | LONGEST s_word; | |
12008 | ||
12009 | ULONGEST u_regval[2]; | |
12010 | ||
12011 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12012 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
12013 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12014 | ||
12015 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12016 | { | |
12017 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
12018 | { | |
12019 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12020 | record_buf[0] = reg_dest1; | |
12021 | record_buf[1] = ARM_PS_REGNUM; | |
12022 | thumb2_insn_r->reg_rec_count = 2; | |
12023 | } | |
12024 | ||
12025 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
12026 | { | |
12027 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12028 | record_buf[2] = reg_dest2; | |
12029 | thumb2_insn_r->reg_rec_count = 3; | |
12030 | } | |
12031 | } | |
12032 | else | |
12033 | { | |
12034 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12035 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12036 | ||
12037 | if (0 == op1 && 0 == op2) | |
12038 | { | |
12039 | /* Handle STREX. */ | |
12040 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12041 | address = u_regval[0] + (offset_imm * 4); | |
12042 | record_buf_mem[0] = 4; | |
12043 | record_buf_mem[1] = address; | |
12044 | thumb2_insn_r->mem_rec_count = 1; | |
12045 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12046 | record_buf[0] = reg_rd; | |
12047 | thumb2_insn_r->reg_rec_count = 1; | |
12048 | } | |
12049 | else if (1 == op1 && 0 == op2) | |
12050 | { | |
12051 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12052 | record_buf[0] = reg_rd; | |
12053 | thumb2_insn_r->reg_rec_count = 1; | |
12054 | address = u_regval[0]; | |
12055 | record_buf_mem[1] = address; | |
12056 | ||
12057 | if (4 == op3) | |
12058 | { | |
12059 | /* Handle STREXB. */ | |
12060 | record_buf_mem[0] = 1; | |
12061 | thumb2_insn_r->mem_rec_count = 1; | |
12062 | } | |
12063 | else if (5 == op3) | |
12064 | { | |
12065 | /* Handle STREXH. */ | |
12066 | record_buf_mem[0] = 2 ; | |
12067 | thumb2_insn_r->mem_rec_count = 1; | |
12068 | } | |
12069 | else if (7 == op3) | |
12070 | { | |
12071 | /* Handle STREXD. */ | |
12072 | address = u_regval[0]; | |
12073 | record_buf_mem[0] = 4; | |
12074 | record_buf_mem[2] = 4; | |
12075 | record_buf_mem[3] = address + 4; | |
12076 | thumb2_insn_r->mem_rec_count = 2; | |
12077 | } | |
12078 | } | |
12079 | else | |
12080 | { | |
12081 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12082 | ||
12083 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
12084 | { | |
12085 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12086 | offset_addr = u_regval[0] + (offset_imm * 4); | |
12087 | else | |
12088 | offset_addr = u_regval[0] - (offset_imm * 4); | |
12089 | ||
12090 | address = offset_addr; | |
12091 | } | |
12092 | else | |
12093 | address = u_regval[0]; | |
12094 | ||
12095 | record_buf_mem[0] = 4; | |
12096 | record_buf_mem[1] = address; | |
12097 | record_buf_mem[2] = 4; | |
12098 | record_buf_mem[3] = address + 4; | |
12099 | thumb2_insn_r->mem_rec_count = 2; | |
12100 | record_buf[0] = reg_rn; | |
12101 | thumb2_insn_r->reg_rec_count = 1; | |
12102 | } | |
12103 | } | |
12104 | ||
12105 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12106 | record_buf); | |
12107 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
12108 | record_buf_mem); | |
12109 | return ARM_RECORD_SUCCESS; | |
12110 | } | |
12111 | ||
12112 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
12113 | instructions. */ | |
12114 | ||
12115 | static int | |
12116 | thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) | |
12117 | { | |
12118 | uint32_t reg_rd, op; | |
12119 | uint32_t record_buf[8]; | |
12120 | ||
12121 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
12122 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12123 | ||
12124 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
12125 | { | |
12126 | record_buf[0] = ARM_PS_REGNUM; | |
12127 | thumb2_insn_r->reg_rec_count = 1; | |
12128 | } | |
12129 | else | |
12130 | { | |
12131 | record_buf[0] = reg_rd; | |
12132 | record_buf[1] = ARM_PS_REGNUM; | |
12133 | thumb2_insn_r->reg_rec_count = 2; | |
12134 | } | |
12135 | ||
12136 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12137 | record_buf); | |
12138 | return ARM_RECORD_SUCCESS; | |
12139 | } | |
12140 | ||
12141 | /* Generic handler for thumb2 instructions which effect destination and PS | |
12142 | registers. */ | |
12143 | ||
12144 | static int | |
12145 | thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) | |
12146 | { | |
12147 | uint32_t reg_rd; | |
12148 | uint32_t record_buf[8]; | |
12149 | ||
12150 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12151 | ||
12152 | record_buf[0] = reg_rd; | |
12153 | record_buf[1] = ARM_PS_REGNUM; | |
12154 | thumb2_insn_r->reg_rec_count = 2; | |
12155 | ||
12156 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12157 | record_buf); | |
12158 | return ARM_RECORD_SUCCESS; | |
12159 | } | |
12160 | ||
12161 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
12162 | ||
12163 | static int | |
12164 | thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) | |
12165 | { | |
12166 | uint32_t op, op1, op2; | |
12167 | uint32_t record_buf[8]; | |
12168 | ||
12169 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12170 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
12171 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12172 | ||
12173 | /* Handle MSR insn. */ | |
12174 | if (!(op1 & 0x2) && 0x38 == op) | |
12175 | { | |
12176 | if (!(op2 & 0x3)) | |
12177 | { | |
12178 | /* CPSR is going to be changed. */ | |
12179 | record_buf[0] = ARM_PS_REGNUM; | |
12180 | thumb2_insn_r->reg_rec_count = 1; | |
12181 | } | |
12182 | else | |
12183 | { | |
12184 | arm_record_unsupported_insn(thumb2_insn_r); | |
12185 | return -1; | |
12186 | } | |
12187 | } | |
12188 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
12189 | { | |
12190 | /* BLX. */ | |
12191 | record_buf[0] = ARM_PS_REGNUM; | |
12192 | record_buf[1] = ARM_LR_REGNUM; | |
12193 | thumb2_insn_r->reg_rec_count = 2; | |
12194 | } | |
12195 | ||
12196 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12197 | record_buf); | |
12198 | return ARM_RECORD_SUCCESS; | |
12199 | } | |
12200 | ||
12201 | /* Handler for thumb2 store single data item instructions. */ | |
12202 | ||
12203 | static int | |
12204 | thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) | |
12205 | { | |
12206 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12207 | ||
12208 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
12209 | uint32_t address, offset_addr; | |
12210 | uint32_t record_buf[8], record_buf_mem[8]; | |
12211 | uint32_t op1, op2; | |
12212 | ||
12213 | ULONGEST u_regval[2]; | |
12214 | ||
12215 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
12216 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
12217 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12218 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12219 | ||
12220 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12221 | { | |
12222 | /* T2 encoding. */ | |
12223 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
12224 | offset_addr = u_regval[0] + offset_imm; | |
12225 | address = offset_addr; | |
12226 | } | |
12227 | else | |
12228 | { | |
12229 | /* T3 encoding. */ | |
12230 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
12231 | { | |
12232 | /* Handle STRB (register). */ | |
12233 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12234 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
12235 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
12236 | offset_addr = u_regval[1] << shift_imm; | |
12237 | address = u_regval[0] + offset_addr; | |
12238 | } | |
12239 | else | |
12240 | { | |
12241 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12242 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
12243 | { | |
12244 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
12245 | offset_addr = u_regval[0] + offset_imm; | |
12246 | else | |
12247 | offset_addr = u_regval[0] - offset_imm; | |
12248 | ||
12249 | address = offset_addr; | |
12250 | } | |
12251 | else | |
12252 | address = u_regval[0]; | |
12253 | } | |
12254 | } | |
12255 | ||
12256 | switch (op1) | |
12257 | { | |
12258 | /* Store byte instructions. */ | |
12259 | case 4: | |
12260 | case 0: | |
12261 | record_buf_mem[0] = 1; | |
12262 | break; | |
12263 | /* Store half word instructions. */ | |
12264 | case 1: | |
12265 | case 5: | |
12266 | record_buf_mem[0] = 2; | |
12267 | break; | |
12268 | /* Store word instructions. */ | |
12269 | case 2: | |
12270 | case 6: | |
12271 | record_buf_mem[0] = 4; | |
12272 | break; | |
12273 | ||
12274 | default: | |
12275 | gdb_assert_not_reached ("no decoding pattern found"); | |
12276 | break; | |
12277 | } | |
12278 | ||
12279 | record_buf_mem[1] = address; | |
12280 | thumb2_insn_r->mem_rec_count = 1; | |
12281 | record_buf[0] = reg_rn; | |
12282 | thumb2_insn_r->reg_rec_count = 1; | |
12283 | ||
12284 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12285 | record_buf); | |
12286 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
12287 | record_buf_mem); | |
12288 | return ARM_RECORD_SUCCESS; | |
12289 | } | |
12290 | ||
12291 | /* Handler for thumb2 load memory hints instructions. */ | |
12292 | ||
12293 | static int | |
12294 | thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) | |
12295 | { | |
12296 | uint32_t record_buf[8]; | |
12297 | uint32_t reg_rt, reg_rn; | |
12298 | ||
12299 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12300 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12301 | ||
12302 | if (ARM_PC_REGNUM != reg_rt) | |
12303 | { | |
12304 | record_buf[0] = reg_rt; | |
12305 | record_buf[1] = reg_rn; | |
12306 | record_buf[2] = ARM_PS_REGNUM; | |
12307 | thumb2_insn_r->reg_rec_count = 3; | |
12308 | ||
12309 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12310 | record_buf); | |
12311 | return ARM_RECORD_SUCCESS; | |
12312 | } | |
12313 | ||
12314 | return ARM_RECORD_FAILURE; | |
12315 | } | |
12316 | ||
12317 | /* Handler for thumb2 load word instructions. */ | |
12318 | ||
12319 | static int | |
12320 | thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) | |
12321 | { | |
12322 | uint32_t opcode1 = 0, opcode2 = 0; | |
12323 | uint32_t record_buf[8]; | |
12324 | ||
12325 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12326 | record_buf[1] = ARM_PS_REGNUM; | |
12327 | thumb2_insn_r->reg_rec_count = 2; | |
12328 | ||
12329 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12330 | record_buf); | |
12331 | return ARM_RECORD_SUCCESS; | |
12332 | } | |
12333 | ||
12334 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
12335 | divide instructions. */ | |
12336 | ||
12337 | static int | |
12338 | thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) | |
12339 | { | |
12340 | uint32_t opcode1 = 0, opcode2 = 0; | |
12341 | uint32_t record_buf[8]; | |
12342 | uint32_t reg_src1 = 0; | |
12343 | ||
12344 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
12345 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12346 | ||
12347 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
12348 | { | |
12349 | /* Handle SMULL, UMULL, SMULAL. */ | |
12350 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
12351 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12352 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12353 | record_buf[2] = ARM_PS_REGNUM; | |
12354 | thumb2_insn_r->reg_rec_count = 3; | |
12355 | } | |
12356 | else if (1 == opcode1 || 3 == opcode2) | |
12357 | { | |
12358 | /* Handle SDIV and UDIV. */ | |
12359 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12360 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12361 | record_buf[2] = ARM_PS_REGNUM; | |
12362 | thumb2_insn_r->reg_rec_count = 3; | |
12363 | } | |
12364 | else | |
12365 | return ARM_RECORD_FAILURE; | |
12366 | ||
12367 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12368 | record_buf); | |
12369 | return ARM_RECORD_SUCCESS; | |
12370 | } | |
12371 | ||
60cc5e93 OJ |
12372 | /* Record handler for thumb32 coprocessor instructions. */ |
12373 | ||
12374 | static int | |
12375 | thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) | |
12376 | { | |
12377 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
12378 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
12379 | else | |
12380 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
12381 | } | |
12382 | ||
1e1b6563 OJ |
12383 | /* Record handler for advance SIMD structure load/store instructions. */ |
12384 | ||
12385 | static int | |
12386 | thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) | |
12387 | { | |
12388 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12389 | uint32_t l_bit, a_bit, b_bits; | |
12390 | uint32_t record_buf[128], record_buf_mem[128]; | |
12391 | uint32_t reg_rn, reg_vd, address, f_esize, f_elem; | |
12392 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; | |
12393 | uint8_t f_ebytes; | |
12394 | ||
12395 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
12396 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
12397 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12398 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12399 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12400 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
12401 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
12402 | f_esize = 8 * f_ebytes; | |
12403 | f_elem = 8 / f_ebytes; | |
12404 | ||
12405 | if (!l_bit) | |
12406 | { | |
12407 | ULONGEST u_regval = 0; | |
12408 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12409 | address = u_regval; | |
12410 | ||
12411 | if (!a_bit) | |
12412 | { | |
12413 | /* Handle VST1. */ | |
12414 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12415 | { | |
12416 | if (b_bits == 0x07) | |
12417 | bf_regs = 1; | |
12418 | else if (b_bits == 0x0a) | |
12419 | bf_regs = 2; | |
12420 | else if (b_bits == 0x06) | |
12421 | bf_regs = 3; | |
12422 | else if (b_bits == 0x02) | |
12423 | bf_regs = 4; | |
12424 | else | |
12425 | bf_regs = 0; | |
12426 | ||
12427 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12428 | { | |
12429 | for (index_e = 0; index_e < f_elem; index_e++) | |
12430 | { | |
12431 | record_buf_mem[index_m++] = f_ebytes; | |
12432 | record_buf_mem[index_m++] = address; | |
12433 | address = address + f_ebytes; | |
12434 | thumb2_insn_r->mem_rec_count += 1; | |
12435 | } | |
12436 | } | |
12437 | } | |
12438 | /* Handle VST2. */ | |
12439 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12440 | { | |
12441 | if (b_bits == 0x09 || b_bits == 0x08) | |
12442 | bf_regs = 1; | |
12443 | else if (b_bits == 0x03) | |
12444 | bf_regs = 2; | |
12445 | else | |
12446 | bf_regs = 0; | |
12447 | ||
12448 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12449 | for (index_e = 0; index_e < f_elem; index_e++) | |
12450 | { | |
12451 | for (loop_t = 0; loop_t < 2; loop_t++) | |
12452 | { | |
12453 | record_buf_mem[index_m++] = f_ebytes; | |
12454 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12455 | thumb2_insn_r->mem_rec_count += 1; | |
12456 | } | |
12457 | address = address + (2 * f_ebytes); | |
12458 | } | |
12459 | } | |
12460 | /* Handle VST3. */ | |
12461 | else if ((b_bits & 0x0e) == 0x04) | |
12462 | { | |
12463 | for (index_e = 0; index_e < f_elem; index_e++) | |
12464 | { | |
12465 | for (loop_t = 0; loop_t < 3; loop_t++) | |
12466 | { | |
12467 | record_buf_mem[index_m++] = f_ebytes; | |
12468 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12469 | thumb2_insn_r->mem_rec_count += 1; | |
12470 | } | |
12471 | address = address + (3 * f_ebytes); | |
12472 | } | |
12473 | } | |
12474 | /* Handle VST4. */ | |
12475 | else if (!(b_bits & 0x0e)) | |
12476 | { | |
12477 | for (index_e = 0; index_e < f_elem; index_e++) | |
12478 | { | |
12479 | for (loop_t = 0; loop_t < 4; loop_t++) | |
12480 | { | |
12481 | record_buf_mem[index_m++] = f_ebytes; | |
12482 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12483 | thumb2_insn_r->mem_rec_count += 1; | |
12484 | } | |
12485 | address = address + (4 * f_ebytes); | |
12486 | } | |
12487 | } | |
12488 | } | |
12489 | else | |
12490 | { | |
12491 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
12492 | ||
12493 | if (bft_size == 0x00) | |
12494 | f_ebytes = 1; | |
12495 | else if (bft_size == 0x01) | |
12496 | f_ebytes = 2; | |
12497 | else if (bft_size == 0x02) | |
12498 | f_ebytes = 4; | |
12499 | else | |
12500 | f_ebytes = 0; | |
12501 | ||
12502 | /* Handle VST1. */ | |
12503 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
12504 | thumb2_insn_r->mem_rec_count = 1; | |
12505 | /* Handle VST2. */ | |
12506 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
12507 | thumb2_insn_r->mem_rec_count = 2; | |
12508 | /* Handle VST3. */ | |
12509 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
12510 | thumb2_insn_r->mem_rec_count = 3; | |
12511 | /* Handle VST4. */ | |
12512 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
12513 | thumb2_insn_r->mem_rec_count = 4; | |
12514 | ||
12515 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
12516 | { | |
12517 | record_buf_mem[index_m] = f_ebytes; | |
12518 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
12519 | } | |
12520 | } | |
12521 | } | |
12522 | else | |
12523 | { | |
12524 | if (!a_bit) | |
12525 | { | |
12526 | /* Handle VLD1. */ | |
12527 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12528 | thumb2_insn_r->reg_rec_count = 1; | |
12529 | /* Handle VLD2. */ | |
12530 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12531 | thumb2_insn_r->reg_rec_count = 2; | |
12532 | /* Handle VLD3. */ | |
12533 | else if ((b_bits & 0x0e) == 0x04) | |
12534 | thumb2_insn_r->reg_rec_count = 3; | |
12535 | /* Handle VLD4. */ | |
12536 | else if (!(b_bits & 0x0e)) | |
12537 | thumb2_insn_r->reg_rec_count = 4; | |
12538 | } | |
12539 | else | |
12540 | { | |
12541 | /* Handle VLD1. */ | |
12542 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
12543 | thumb2_insn_r->reg_rec_count = 1; | |
12544 | /* Handle VLD2. */ | |
12545 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
12546 | thumb2_insn_r->reg_rec_count = 2; | |
12547 | /* Handle VLD3. */ | |
12548 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
12549 | thumb2_insn_r->reg_rec_count = 3; | |
12550 | /* Handle VLD4. */ | |
12551 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
12552 | thumb2_insn_r->reg_rec_count = 4; | |
12553 | ||
12554 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
12555 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
12556 | } | |
12557 | } | |
12558 | ||
12559 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
12560 | { | |
12561 | record_buf[index_r] = reg_rn; | |
12562 | thumb2_insn_r->reg_rec_count += 1; | |
12563 | } | |
12564 | ||
12565 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
12566 | record_buf); | |
12567 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
12568 | record_buf_mem); | |
12569 | return 0; | |
12570 | } | |
12571 | ||
c6ec2b30 OJ |
12572 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
12573 | ||
12574 | static unsigned int | |
12575 | thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) | |
12576 | { | |
12577 | uint32_t op, op1, op2; | |
12578 | ||
12579 | op = bit (thumb2_insn_r->arm_insn, 15); | |
12580 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
12581 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12582 | ||
12583 | if (op1 == 0x01) | |
12584 | { | |
12585 | if (!(op2 & 0x64 )) | |
12586 | { | |
12587 | /* Load/store multiple instruction. */ | |
12588 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
12589 | } | |
12590 | else if (!((op2 & 0x64) ^ 0x04)) | |
12591 | { | |
12592 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
12593 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
12594 | } | |
12595 | else if (!((op2 & 0x20) ^ 0x20)) | |
12596 | { | |
12597 | /* Data-processing (shifted register). */ | |
12598 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12599 | } | |
12600 | else if (op2 & 0x40) | |
12601 | { | |
12602 | /* Co-processor instructions. */ | |
60cc5e93 | 12603 | return thumb2_record_coproc_insn (thumb2_insn_r); |
c6ec2b30 OJ |
12604 | } |
12605 | } | |
12606 | else if (op1 == 0x02) | |
12607 | { | |
12608 | if (op) | |
12609 | { | |
12610 | /* Branches and miscellaneous control instructions. */ | |
12611 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
12612 | } | |
12613 | else if (op2 & 0x20) | |
12614 | { | |
12615 | /* Data-processing (plain binary immediate) instruction. */ | |
12616 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
12617 | } | |
12618 | else | |
12619 | { | |
12620 | /* Data-processing (modified immediate). */ | |
12621 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12622 | } | |
12623 | } | |
12624 | else if (op1 == 0x03) | |
12625 | { | |
12626 | if (!(op2 & 0x71 )) | |
12627 | { | |
12628 | /* Store single data item. */ | |
12629 | return thumb2_record_str_single_data (thumb2_insn_r); | |
12630 | } | |
12631 | else if (!((op2 & 0x71) ^ 0x10)) | |
12632 | { | |
12633 | /* Advanced SIMD or structure load/store instructions. */ | |
1e1b6563 | 12634 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); |
c6ec2b30 OJ |
12635 | } |
12636 | else if (!((op2 & 0x67) ^ 0x01)) | |
12637 | { | |
12638 | /* Load byte, memory hints instruction. */ | |
12639 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
12640 | } | |
12641 | else if (!((op2 & 0x67) ^ 0x03)) | |
12642 | { | |
12643 | /* Load halfword, memory hints instruction. */ | |
12644 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
12645 | } | |
12646 | else if (!((op2 & 0x67) ^ 0x05)) | |
12647 | { | |
12648 | /* Load word instruction. */ | |
12649 | return thumb2_record_ld_word (thumb2_insn_r); | |
12650 | } | |
12651 | else if (!((op2 & 0x70) ^ 0x20)) | |
12652 | { | |
12653 | /* Data-processing (register) instruction. */ | |
12654 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
12655 | } | |
12656 | else if (!((op2 & 0x78) ^ 0x30)) | |
12657 | { | |
12658 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
12659 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
12660 | } | |
12661 | else if (!((op2 & 0x78) ^ 0x38)) | |
12662 | { | |
12663 | /* Long multiply, long multiply accumulate, and divide. */ | |
12664 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
12665 | } | |
12666 | else if (op2 & 0x40) | |
12667 | { | |
12668 | /* Co-processor instructions. */ | |
60cc5e93 | 12669 | return thumb2_record_coproc_insn (thumb2_insn_r); |
c6ec2b30 OJ |
12670 | } |
12671 | } | |
12672 | ||
12673 | return -1; | |
12674 | } | |
72508ac0 PO |
12675 | |
12676 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success | |
12677 | and positive val on fauilure. */ | |
12678 | ||
12679 | static int | |
12680 | extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size) | |
12681 | { | |
12682 | gdb_byte buf[insn_size]; | |
12683 | ||
12684 | memset (&buf[0], 0, insn_size); | |
12685 | ||
12686 | if (target_read_memory (insn_record->this_addr, &buf[0], insn_size)) | |
12687 | return 1; | |
12688 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
12689 | insn_size, | |
2959fed9 | 12690 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
12691 | return 0; |
12692 | } | |
12693 | ||
12694 | typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); | |
12695 | ||
12696 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
12697 | dispatch it. */ | |
12698 | ||
12699 | static int | |
12700 | decode_insn (insn_decode_record *arm_record, record_type_t record_type, | |
12701 | uint32_t insn_size) | |
12702 | { | |
12703 | ||
12704 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */ | |
0fa9c223 | 12705 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
12706 | { |
12707 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
12708 | arm_record_data_proc_imm, /* 001. */ | |
12709 | arm_record_ld_st_imm_offset, /* 010. */ | |
12710 | arm_record_ld_st_reg_offset, /* 011. */ | |
12711 | arm_record_ld_st_multiple, /* 100. */ | |
12712 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 12713 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
12714 | arm_record_coproc_data_proc /* 111. */ |
12715 | }; | |
12716 | ||
12717 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */ | |
0fa9c223 | 12718 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
12719 | { \ |
12720 | thumb_record_shift_add_sub, /* 000. */ | |
12721 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
12722 | thumb_record_ld_st_reg_offset, /* 010. */ | |
12723 | thumb_record_ld_st_imm_offset, /* 011. */ | |
12724 | thumb_record_ld_st_stack, /* 100. */ | |
12725 | thumb_record_misc, /* 101. */ | |
12726 | thumb_record_ldm_stm_swi, /* 110. */ | |
12727 | thumb_record_branch /* 111. */ | |
12728 | }; | |
12729 | ||
12730 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
12731 | uint32_t insn_id = 0; | |
12732 | ||
12733 | if (extract_arm_insn (arm_record, insn_size)) | |
12734 | { | |
12735 | if (record_debug) | |
12736 | { | |
12737 | printf_unfiltered (_("Process record: error reading memory at " | |
12738 | "addr %s len = %d.\n"), | |
12739 | paddress (arm_record->gdbarch, arm_record->this_addr), insn_size); | |
12740 | } | |
12741 | return -1; | |
12742 | } | |
12743 | else if (ARM_RECORD == record_type) | |
12744 | { | |
12745 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
12746 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
12747 | ret = arm_record_extension_space (arm_record); | |
12748 | /* If this insn has fallen into extension space | |
12749 | then we need not decode it anymore. */ | |
12750 | if (ret != -1 && !INSN_RECORDED(arm_record)) | |
12751 | { | |
12752 | ret = arm_handle_insn[insn_id] (arm_record); | |
12753 | } | |
12754 | } | |
12755 | else if (THUMB_RECORD == record_type) | |
12756 | { | |
12757 | /* As thumb does not have condition codes, we set negative. */ | |
12758 | arm_record->cond = -1; | |
12759 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
12760 | ret = thumb_handle_insn[insn_id] (arm_record); | |
12761 | } | |
12762 | else if (THUMB2_RECORD == record_type) | |
12763 | { | |
c6ec2b30 OJ |
12764 | /* As thumb does not have condition codes, we set negative. */ |
12765 | arm_record->cond = -1; | |
12766 | ||
12767 | /* Swap first half of 32bit thumb instruction with second half. */ | |
12768 | arm_record->arm_insn | |
12769 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); | |
12770 | ||
12771 | insn_id = thumb2_record_decode_insn_handler (arm_record); | |
12772 | ||
12773 | if (insn_id != ARM_RECORD_SUCCESS) | |
12774 | { | |
12775 | arm_record_unsupported_insn (arm_record); | |
12776 | ret = -1; | |
12777 | } | |
72508ac0 PO |
12778 | } |
12779 | else | |
12780 | { | |
12781 | /* Throw assertion. */ | |
12782 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
12783 | } | |
12784 | ||
12785 | return ret; | |
12786 | } | |
12787 | ||
12788 | ||
12789 | /* Cleans up local record registers and memory allocations. */ | |
12790 | ||
12791 | static void | |
12792 | deallocate_reg_mem (insn_decode_record *record) | |
12793 | { | |
12794 | xfree (record->arm_regs); | |
12795 | xfree (record->arm_mems); | |
12796 | } | |
12797 | ||
12798 | ||
12799 | /* Parse the current instruction and record the values of the registers and | |
12800 | memory that will be changed in current instruction to record_arch_list". | |
12801 | Return -1 if something is wrong. */ | |
12802 | ||
12803 | int | |
12804 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
12805 | CORE_ADDR insn_addr) | |
12806 | { | |
12807 | ||
12808 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
12809 | uint32_t no_of_rec = 0; | |
12810 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
12811 | ULONGEST t_bit = 0, insn_id = 0; | |
12812 | ||
12813 | ULONGEST u_regval = 0; | |
12814 | ||
12815 | insn_decode_record arm_record; | |
12816 | ||
12817 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
12818 | arm_record.regcache = regcache; | |
12819 | arm_record.this_addr = insn_addr; | |
12820 | arm_record.gdbarch = gdbarch; | |
12821 | ||
12822 | ||
12823 | if (record_debug > 1) | |
12824 | { | |
12825 | fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " | |
12826 | "addr = %s\n", | |
12827 | paddress (gdbarch, arm_record.this_addr)); | |
12828 | } | |
12829 | ||
12830 | if (extract_arm_insn (&arm_record, 2)) | |
12831 | { | |
12832 | if (record_debug) | |
12833 | { | |
12834 | printf_unfiltered (_("Process record: error reading memory at " | |
12835 | "addr %s len = %d.\n"), | |
12836 | paddress (arm_record.gdbarch, | |
12837 | arm_record.this_addr), 2); | |
12838 | } | |
12839 | return -1; | |
12840 | } | |
12841 | ||
12842 | /* Check the insn, whether it is thumb or arm one. */ | |
12843 | ||
12844 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
12845 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
12846 | ||
12847 | ||
12848 | if (!(u_regval & t_bit)) | |
12849 | { | |
12850 | /* We are decoding arm insn. */ | |
12851 | ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); | |
12852 | } | |
12853 | else | |
12854 | { | |
12855 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
12856 | /* is it thumb2 insn? */ | |
12857 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
12858 | { | |
12859 | ret = decode_insn (&arm_record, THUMB2_RECORD, | |
12860 | THUMB2_INSN_SIZE_BYTES); | |
12861 | } | |
12862 | else | |
12863 | { | |
12864 | /* We are decoding thumb insn. */ | |
12865 | ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES); | |
12866 | } | |
12867 | } | |
12868 | ||
12869 | if (0 == ret) | |
12870 | { | |
12871 | /* Record registers. */ | |
25ea693b | 12872 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 PO |
12873 | if (arm_record.arm_regs) |
12874 | { | |
12875 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
12876 | { | |
25ea693b MM |
12877 | if (record_full_arch_list_add_reg |
12878 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) | |
72508ac0 PO |
12879 | ret = -1; |
12880 | } | |
12881 | } | |
12882 | /* Record memories. */ | |
12883 | if (arm_record.arm_mems) | |
12884 | { | |
12885 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
12886 | { | |
25ea693b | 12887 | if (record_full_arch_list_add_mem |
72508ac0 | 12888 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, |
25ea693b | 12889 | arm_record.arm_mems[no_of_rec].len)) |
72508ac0 PO |
12890 | ret = -1; |
12891 | } | |
12892 | } | |
12893 | ||
25ea693b | 12894 | if (record_full_arch_list_add_end ()) |
72508ac0 PO |
12895 | ret = -1; |
12896 | } | |
12897 | ||
12898 | ||
12899 | deallocate_reg_mem (&arm_record); | |
12900 | ||
12901 | return ret; | |
12902 | } | |
12903 |