Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
b811d2c2 | 3 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
82ca8957 | 41 | #include "dwarf2/frame.h" |
4de283e4 TT |
42 | #include "gdbtypes.h" |
43 | #include "prologue-value.h" | |
44 | #include "remote.h" | |
45 | #include "target-descriptions.h" | |
46 | #include "user-regs.h" | |
47 | #include "observable.h" | |
5f661e03 | 48 | #include "count-one-bits.h" |
4de283e4 | 49 | |
d55e5aa6 | 50 | #include "arch/arm.h" |
4de283e4 | 51 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 52 | #include "arm-tdep.h" |
4de283e4 TT |
53 | #include "gdb/sim-arm.h" |
54 | ||
d55e5aa6 | 55 | #include "elf-bfd.h" |
4de283e4 | 56 | #include "coff/internal.h" |
d55e5aa6 | 57 | #include "elf/arm.h" |
4de283e4 | 58 | |
4de283e4 TT |
59 | #include "record.h" |
60 | #include "record-full.h" | |
61 | #include <algorithm> | |
62 | ||
c2fd7fae AKS |
63 | #include "producer.h" |
64 | ||
b121eeb9 | 65 | #if GDB_SELF_TEST |
268a13a5 | 66 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
67 | #endif |
68 | ||
491144b5 | 69 | static bool arm_debug; |
6529d2dd | 70 | |
082fc60d RE |
71 | /* Macros for setting and testing a bit in a minimal symbol that marks |
72 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 73 | is used for this purpose. |
082fc60d RE |
74 | |
75 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 76 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 77 | |
0963b4bd | 78 | #define MSYMBOL_SET_SPECIAL(msym) \ |
b887350f | 79 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
80 | |
81 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 82 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 83 | |
60c5725c DJ |
84 | struct arm_mapping_symbol |
85 | { | |
227031b2 | 86 | CORE_ADDR value; |
60c5725c | 87 | char type; |
54cc7474 SM |
88 | |
89 | bool operator< (const arm_mapping_symbol &other) const | |
90 | { return this->value < other.value; } | |
60c5725c | 91 | }; |
54cc7474 SM |
92 | |
93 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 94 | |
bd5766ec | 95 | struct arm_per_bfd |
60c5725c | 96 | { |
bd5766ec | 97 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
98 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
99 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
100 | {} |
101 | ||
bd5766ec | 102 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
103 | |
104 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
105 | ||
106 | The format is an array of vectors of arm_mapping_symbols, there is one | |
107 | vector for each section of the objfile (the array is index by BFD section | |
108 | index). | |
109 | ||
110 | For each section, the vector of arm_mapping_symbol is sorted by | |
111 | symbol value (address). */ | |
112 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
113 | |
114 | /* For each corresponding element of section_maps above, is this vector | |
115 | sorted. */ | |
116 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
117 | }; |
118 | ||
bd5766ec LM |
119 | /* Per-bfd data used for mapping symbols. */ |
120 | static bfd_key<arm_per_bfd> arm_bfd_data_key; | |
1b7f24cd | 121 | |
afd7eef0 RE |
122 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
123 | static struct cmd_list_element *setarmcmdlist = NULL; | |
124 | static struct cmd_list_element *showarmcmdlist = NULL; | |
125 | ||
fd50bc42 RE |
126 | /* The type of floating-point to use. Keep this in sync with enum |
127 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 128 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
129 | { |
130 | "auto", | |
131 | "softfpa", | |
132 | "fpa", | |
133 | "softvfp", | |
28e97307 DJ |
134 | "vfp", |
135 | NULL | |
fd50bc42 RE |
136 | }; |
137 | ||
138 | /* A variable that can be configured by the user. */ | |
139 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
140 | static const char *current_fp_model = "auto"; | |
141 | ||
28e97307 | 142 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 143 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
144 | { |
145 | "auto", | |
146 | "APCS", | |
147 | "AAPCS", | |
148 | NULL | |
149 | }; | |
150 | ||
151 | /* A variable that can be configured by the user. */ | |
152 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
153 | static const char *arm_abi_string = "auto"; | |
154 | ||
0428b8f5 | 155 | /* The execution mode to assume. */ |
40478521 | 156 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
157 | { |
158 | "auto", | |
159 | "arm", | |
68770265 MGD |
160 | "thumb", |
161 | NULL | |
0428b8f5 DJ |
162 | }; |
163 | ||
164 | static const char *arm_fallback_mode_string = "auto"; | |
165 | static const char *arm_force_mode_string = "auto"; | |
166 | ||
f32bf4a4 YQ |
167 | /* The standard register names, and all the valid aliases for them. Note |
168 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
169 | have been added as builtin user registers in | |
170 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
171 | static const struct |
172 | { | |
173 | const char *name; | |
174 | int regnum; | |
175 | } arm_register_aliases[] = { | |
176 | /* Basic register numbers. */ | |
177 | { "r0", 0 }, | |
178 | { "r1", 1 }, | |
179 | { "r2", 2 }, | |
180 | { "r3", 3 }, | |
181 | { "r4", 4 }, | |
182 | { "r5", 5 }, | |
183 | { "r6", 6 }, | |
184 | { "r7", 7 }, | |
185 | { "r8", 8 }, | |
186 | { "r9", 9 }, | |
187 | { "r10", 10 }, | |
188 | { "r11", 11 }, | |
189 | { "r12", 12 }, | |
190 | { "r13", 13 }, | |
191 | { "r14", 14 }, | |
192 | { "r15", 15 }, | |
193 | /* Synonyms (argument and variable registers). */ | |
194 | { "a1", 0 }, | |
195 | { "a2", 1 }, | |
196 | { "a3", 2 }, | |
197 | { "a4", 3 }, | |
198 | { "v1", 4 }, | |
199 | { "v2", 5 }, | |
200 | { "v3", 6 }, | |
201 | { "v4", 7 }, | |
202 | { "v5", 8 }, | |
203 | { "v6", 9 }, | |
204 | { "v7", 10 }, | |
205 | { "v8", 11 }, | |
206 | /* Other platform-specific names for r9. */ | |
207 | { "sb", 9 }, | |
208 | { "tr", 9 }, | |
209 | /* Special names. */ | |
210 | { "ip", 12 }, | |
123dc839 | 211 | { "lr", 14 }, |
123dc839 DJ |
212 | /* Names used by GCC (not listed in the ARM EABI). */ |
213 | { "sl", 10 }, | |
123dc839 DJ |
214 | /* A special name from the older ATPCS. */ |
215 | { "wr", 7 }, | |
216 | }; | |
bc90b915 | 217 | |
123dc839 | 218 | static const char *const arm_register_names[] = |
da59e081 JM |
219 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
220 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
221 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
222 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
223 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
224 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 225 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 226 | |
65b48a81 PB |
227 | /* Holds the current set of options to be passed to the disassembler. */ |
228 | static char *arm_disassembler_options; | |
229 | ||
afd7eef0 RE |
230 | /* Valid register name styles. */ |
231 | static const char **valid_disassembly_styles; | |
ed9a39eb | 232 | |
afd7eef0 RE |
233 | /* Disassembly style to use. Default to "std" register names. */ |
234 | static const char *disassembly_style; | |
96baa820 | 235 | |
d105cce5 AH |
236 | /* All possible arm target descriptors. */ |
237 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID]; | |
238 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; | |
239 | ||
ed9a39eb | 240 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 241 | style. */ |
eb4c3f4a | 242 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 243 | struct cmd_list_element *); |
65b48a81 PB |
244 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
245 | struct cmd_list_element *, | |
246 | const char *); | |
ed9a39eb | 247 | |
05d1431c | 248 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 249 | readable_regcache *regcache, |
05d1431c | 250 | int regnum, gdb_byte *buf); |
58d6951d DJ |
251 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
252 | struct regcache *regcache, | |
253 | int regnum, const gdb_byte *buf); | |
254 | ||
e7cf25a8 | 255 | static CORE_ADDR |
553cb527 | 256 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
257 | |
258 | ||
d9311bfa AT |
259 | /* get_next_pcs operations. */ |
260 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
261 | arm_get_next_pcs_read_memory_unsigned_integer, | |
262 | arm_get_next_pcs_syscall_next_pc, | |
263 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
264 | arm_get_next_pcs_is_thumb, |
265 | NULL, | |
d9311bfa AT |
266 | }; |
267 | ||
9b8d791a | 268 | struct arm_prologue_cache |
c3b4394c | 269 | { |
eb5492fa DJ |
270 | /* The stack pointer at the time this frame was created; i.e. the |
271 | caller's stack pointer when this function was called. It is used | |
272 | to identify this frame. */ | |
273 | CORE_ADDR prev_sp; | |
274 | ||
4be43953 DJ |
275 | /* The frame base for this frame is just prev_sp - frame size. |
276 | FRAMESIZE is the distance from the frame pointer to the | |
277 | initial stack pointer. */ | |
eb5492fa | 278 | |
c3b4394c | 279 | int framesize; |
eb5492fa DJ |
280 | |
281 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 282 | int framereg; |
eb5492fa DJ |
283 | |
284 | /* Saved register offsets. */ | |
285 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 286 | }; |
ed9a39eb | 287 | |
9ecab40c SM |
288 | namespace { |
289 | ||
290 | /* Abstract class to read ARM instructions from memory. */ | |
291 | ||
292 | class arm_instruction_reader | |
293 | { | |
294 | public: | |
2c5b1849 | 295 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
296 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
297 | }; | |
298 | ||
299 | /* Read instructions from target memory. */ | |
300 | ||
301 | class target_arm_instruction_reader : public arm_instruction_reader | |
302 | { | |
303 | public: | |
304 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
305 | { | |
306 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
307 | } | |
308 | }; | |
309 | ||
310 | } /* namespace */ | |
311 | ||
312 | static CORE_ADDR arm_analyze_prologue | |
313 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
314 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 315 | |
cca44b1b JB |
316 | /* Architecture version for displaced stepping. This effects the behaviour of |
317 | certain instructions, and really should not be hard-wired. */ | |
318 | ||
319 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
320 | ||
c7ae7675 | 321 | /* See arm-tdep.h. */ |
c906108c | 322 | |
491144b5 | 323 | bool arm_apcs_32 = true; |
c906108c | 324 | |
9779414d DJ |
325 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
326 | ||
478fd957 | 327 | int |
9779414d DJ |
328 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
329 | { | |
330 | if (gdbarch_tdep (gdbarch)->is_m) | |
331 | return XPSR_T; | |
332 | else | |
333 | return CPSR_T; | |
334 | } | |
335 | ||
d0e59a68 AT |
336 | /* Determine if the processor is currently executing in Thumb mode. */ |
337 | ||
338 | int | |
339 | arm_is_thumb (struct regcache *regcache) | |
340 | { | |
341 | ULONGEST cpsr; | |
ac7936df | 342 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
343 | |
344 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
345 | ||
346 | return (cpsr & t_bit) != 0; | |
347 | } | |
348 | ||
b39cc962 DJ |
349 | /* Determine if FRAME is executing in Thumb mode. */ |
350 | ||
25b41d01 | 351 | int |
b39cc962 DJ |
352 | arm_frame_is_thumb (struct frame_info *frame) |
353 | { | |
354 | CORE_ADDR cpsr; | |
9779414d | 355 | ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); |
b39cc962 DJ |
356 | |
357 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
358 | directly (from a signal frame or dummy frame) or by interpreting | |
359 | the saved LR (from a prologue or DWARF frame). So consult it and | |
360 | trust the unwinders. */ | |
361 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
362 | ||
9779414d | 363 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
364 | } |
365 | ||
f9d67f43 DJ |
366 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
367 | return its type. Otherwise, return 0. If START is non-NULL, | |
368 | set *START to the location of the mapping symbol. */ | |
c906108c | 369 | |
f9d67f43 DJ |
370 | static char |
371 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 372 | { |
60c5725c | 373 | struct obj_section *sec; |
0428b8f5 | 374 | |
60c5725c DJ |
375 | /* If there are mapping symbols, consult them. */ |
376 | sec = find_pc_section (memaddr); | |
377 | if (sec != NULL) | |
378 | { | |
bd5766ec | 379 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd); |
60c5725c DJ |
380 | if (data != NULL) |
381 | { | |
4838e44c SM |
382 | unsigned int section_idx = sec->the_bfd_section->index; |
383 | arm_mapping_symbol_vec &map | |
384 | = data->section_maps[section_idx]; | |
385 | ||
386 | /* Sort the vector on first use. */ | |
387 | if (!data->section_maps_sorted[section_idx]) | |
388 | { | |
389 | std::sort (map.begin (), map.end ()); | |
390 | data->section_maps_sorted[section_idx] = true; | |
391 | } | |
392 | ||
54cc7474 SM |
393 | struct arm_mapping_symbol map_key |
394 | = { memaddr - obj_section_addr (sec), 0 }; | |
54cc7474 SM |
395 | arm_mapping_symbol_vec::const_iterator it |
396 | = std::lower_bound (map.begin (), map.end (), map_key); | |
397 | ||
398 | /* std::lower_bound finds the earliest ordered insertion | |
399 | point. If the symbol at this position starts at this exact | |
400 | address, we use that; otherwise, the preceding | |
401 | mapping symbol covers this address. */ | |
402 | if (it < map.end ()) | |
60c5725c | 403 | { |
54cc7474 | 404 | if (it->value == map_key.value) |
60c5725c | 405 | { |
f9d67f43 | 406 | if (start) |
54cc7474 SM |
407 | *start = it->value + obj_section_addr (sec); |
408 | return it->type; | |
60c5725c DJ |
409 | } |
410 | } | |
54cc7474 SM |
411 | |
412 | if (it > map.begin ()) | |
413 | { | |
414 | arm_mapping_symbol_vec::const_iterator prev_it | |
415 | = it - 1; | |
416 | ||
417 | if (start) | |
418 | *start = prev_it->value + obj_section_addr (sec); | |
419 | return prev_it->type; | |
420 | } | |
60c5725c DJ |
421 | } |
422 | } | |
423 | ||
f9d67f43 DJ |
424 | return 0; |
425 | } | |
426 | ||
427 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
428 | function. This function should be called for addresses unrelated to | |
429 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
430 | ||
e3039479 | 431 | int |
9779414d | 432 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 433 | { |
7cbd4a93 | 434 | struct bound_minimal_symbol sym; |
f9d67f43 | 435 | char type; |
187b041e SM |
436 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
437 | ||
438 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
439 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
440 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
441 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
442 | |
443 | /* If checking the mode of displaced instruction in copy area, the mode | |
444 | should be determined by instruction on the original address. */ | |
445 | if (dsc) | |
446 | { | |
136821d9 SM |
447 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
448 | (unsigned long) dsc->insn_addr, | |
449 | (unsigned long) memaddr); | |
a42244db YQ |
450 | memaddr = dsc->insn_addr; |
451 | } | |
f9d67f43 DJ |
452 | |
453 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
454 | if (IS_THUMB_ADDR (memaddr)) | |
455 | return 1; | |
456 | ||
457 | /* If the user wants to override the symbol table, let him. */ | |
458 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
459 | return 0; | |
460 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
461 | return 1; | |
462 | ||
9779414d DJ |
463 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
464 | if (gdbarch_tdep (gdbarch)->is_m) | |
465 | return 1; | |
466 | ||
f9d67f43 DJ |
467 | /* If there are mapping symbols, consult them. */ |
468 | type = arm_find_mapping_symbol (memaddr, NULL); | |
469 | if (type) | |
470 | return type == 't'; | |
471 | ||
ed9a39eb | 472 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 473 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
474 | if (sym.minsym) |
475 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
476 | |
477 | /* If the user wants to override the fallback mode, let them. */ | |
478 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
479 | return 0; | |
480 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
481 | return 1; | |
482 | ||
483 | /* If we couldn't find any symbol, but we're talking to a running | |
484 | target, then trust the current value of $cpsr. This lets | |
485 | "display/i $pc" always show the correct mode (though if there is | |
486 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 487 | displayed in the mode it will be executed). */ |
9dccd06e | 488 | if (target_has_registers ()) |
18819fa6 | 489 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
490 | |
491 | /* Otherwise we're out of luck; we assume ARM. */ | |
492 | return 0; | |
c906108c SS |
493 | } |
494 | ||
ca90e760 | 495 | /* Determine if the address specified equals any of these magic return |
55ea94da | 496 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
ca90e760 FH |
497 | architectures. |
498 | ||
499 | From ARMv6-M Reference Manual B1.5.8 | |
500 | Table B1-5 Exception return behavior | |
501 | ||
502 | EXC_RETURN Return To Return Stack | |
503 | 0xFFFFFFF1 Handler mode Main | |
504 | 0xFFFFFFF9 Thread mode Main | |
505 | 0xFFFFFFFD Thread mode Process | |
506 | ||
507 | From ARMv7-M Reference Manual B1.5.8 | |
508 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
509 | ||
510 | EXC_RETURN Return To Return Stack | |
511 | 0xFFFFFFF1 Handler mode Main | |
512 | 0xFFFFFFF9 Thread mode Main | |
513 | 0xFFFFFFFD Thread mode Process | |
514 | ||
515 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
516 | FP | |
517 | ||
518 | EXC_RETURN Return To Return Stack Frame Type | |
519 | 0xFFFFFFE1 Handler mode Main Extended | |
520 | 0xFFFFFFE9 Thread mode Main Extended | |
521 | 0xFFFFFFED Thread mode Process Extended | |
522 | 0xFFFFFFF1 Handler mode Main Basic | |
523 | 0xFFFFFFF9 Thread mode Main Basic | |
524 | 0xFFFFFFFD Thread mode Process Basic | |
525 | ||
526 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
527 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
528 | ||
529 | In the ARMv8-M Architecture Technical Reference also adds | |
530 | for implementations without the Security Extension: | |
531 | ||
532 | EXC_RETURN Condition | |
533 | 0xFFFFFFB0 Return to Handler mode. | |
534 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
535 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
536 | |
537 | static int | |
538 | arm_m_addr_is_magic (CORE_ADDR addr) | |
539 | { | |
540 | switch (addr) | |
541 | { | |
55ea94da FH |
542 | /* Values from ARMv8-M Architecture Technical Reference. */ |
543 | case 0xffffffb0: | |
544 | case 0xffffffb8: | |
545 | case 0xffffffbc: | |
ca90e760 FH |
546 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of |
547 | the exception return behavior. */ | |
548 | case 0xffffffe1: | |
549 | case 0xffffffe9: | |
550 | case 0xffffffed: | |
551 | case 0xfffffff1: | |
552 | case 0xfffffff9: | |
553 | case 0xfffffffd: | |
554 | /* Address is magic. */ | |
555 | return 1; | |
556 | ||
557 | default: | |
558 | /* Address is not magic. */ | |
559 | return 0; | |
560 | } | |
561 | } | |
562 | ||
181c1381 | 563 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 564 | static CORE_ADDR |
24568a2c | 565 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 566 | { |
2ae28aa9 YQ |
567 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
568 | (the magic exception return address). */ | |
569 | if (gdbarch_tdep (gdbarch)->is_m | |
ca90e760 | 570 | && arm_m_addr_is_magic (val)) |
2ae28aa9 YQ |
571 | return val; |
572 | ||
a3a2ee65 | 573 | if (arm_apcs_32) |
dd6be234 | 574 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 575 | else |
a3a2ee65 | 576 | return (val & 0x03fffffc); |
c906108c SS |
577 | } |
578 | ||
0d39a070 | 579 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
580 | can be safely ignored during prologue skipping. IS_THUMB is true |
581 | if the function is known to be a Thumb function due to the way it | |
582 | is being called. */ | |
0d39a070 | 583 | static int |
e0634ccf | 584 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 585 | { |
e0634ccf | 586 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 587 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
588 | |
589 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 590 | if (msym.minsym != NULL |
77e371c0 | 591 | && BMSYMBOL_VALUE_ADDRESS (msym) == pc |
c9d95fa3 | 592 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 593 | { |
c9d95fa3 | 594 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 595 | |
e0634ccf UW |
596 | /* The GNU linker's Thumb call stub to foo is named |
597 | __foo_from_thumb. */ | |
598 | if (strstr (name, "_from_thumb") != NULL) | |
599 | name += 2; | |
0d39a070 | 600 | |
e0634ccf UW |
601 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
602 | arguments to their argument types in non-prototyped | |
603 | functions. */ | |
61012eef | 604 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 605 | return 1; |
61012eef | 606 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 607 | return 1; |
0d39a070 | 608 | |
e0634ccf | 609 | /* Internal functions related to thread-local storage. */ |
61012eef | 610 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 611 | return 1; |
61012eef | 612 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
613 | return 1; |
614 | } | |
615 | else | |
616 | { | |
617 | /* If we run against a stripped glibc, we may be unable to identify | |
618 | special functions by name. Check for one important case, | |
619 | __aeabi_read_tp, by comparing the *code* against the default | |
620 | implementation (this is hand-written ARM assembler in glibc). */ | |
621 | ||
622 | if (!is_thumb | |
198cd59d | 623 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 624 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 625 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
626 | == 0xe240f01f) /* sub pc, r0, #31 */ |
627 | return 1; | |
628 | } | |
ec3d575a | 629 | |
0d39a070 DJ |
630 | return 0; |
631 | } | |
632 | ||
621c6d5b YQ |
633 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
634 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
635 | instruction. */ | |
636 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
637 | ((bits ((insn1), 0, 3) << 12) \ | |
638 | | (bits ((insn1), 10, 10) << 11) \ | |
639 | | (bits ((insn2), 12, 14) << 8) \ | |
640 | | bits ((insn2), 0, 7)) | |
641 | ||
642 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
643 | the 32-bit instruction. */ | |
644 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
645 | ((bits ((insn), 16, 19) << 12) \ | |
646 | | bits ((insn), 0, 11)) | |
647 | ||
ec3d575a UW |
648 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
649 | ||
650 | static unsigned int | |
651 | thumb_expand_immediate (unsigned int imm) | |
652 | { | |
653 | unsigned int count = imm >> 7; | |
654 | ||
655 | if (count < 8) | |
656 | switch (count / 2) | |
657 | { | |
658 | case 0: | |
659 | return imm & 0xff; | |
660 | case 1: | |
661 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
662 | case 2: | |
663 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
664 | case 3: | |
665 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
666 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
667 | } | |
668 | ||
669 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
670 | } | |
671 | ||
540314bd YQ |
672 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
673 | epilogue, 0 otherwise. */ | |
674 | ||
675 | static int | |
676 | thumb_instruction_restores_sp (unsigned short insn) | |
677 | { | |
678 | return (insn == 0x46bd /* mov sp, r7 */ | |
679 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
680 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
681 | } | |
682 | ||
29d73ae4 DJ |
683 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
684 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
685 | clobber the stack frame unexpectedly, or an unknown instruction. |
686 | Return the last address which is definitely safe to skip for an | |
687 | initial breakpoint. */ | |
c906108c SS |
688 | |
689 | static CORE_ADDR | |
29d73ae4 DJ |
690 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
691 | CORE_ADDR start, CORE_ADDR limit, | |
692 | struct arm_prologue_cache *cache) | |
c906108c | 693 | { |
0d39a070 | 694 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 695 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
696 | int i; |
697 | pv_t regs[16]; | |
29d73ae4 | 698 | CORE_ADDR offset; |
ec3d575a | 699 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 700 | |
29d73ae4 DJ |
701 | for (i = 0; i < 16; i++) |
702 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 703 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 704 | |
29d73ae4 | 705 | while (start < limit) |
c906108c | 706 | { |
29d73ae4 DJ |
707 | unsigned short insn; |
708 | ||
198cd59d | 709 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 710 | |
94c30b78 | 711 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 712 | { |
29d73ae4 DJ |
713 | int regno; |
714 | int mask; | |
4be43953 | 715 | |
f7b7ed97 | 716 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 717 | break; |
29d73ae4 DJ |
718 | |
719 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
720 | whether to save LR (R14). */ | |
721 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
722 | ||
723 | /* Calculate offsets of saved R0-R7 and LR. */ | |
724 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
725 | if (mask & (1 << regno)) | |
726 | { | |
29d73ae4 DJ |
727 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
728 | -4); | |
f7b7ed97 | 729 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 730 | } |
da59e081 | 731 | } |
1db01f22 | 732 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 733 | { |
29d73ae4 | 734 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
735 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
736 | -offset); | |
da59e081 | 737 | } |
808f7ab1 YQ |
738 | else if (thumb_instruction_restores_sp (insn)) |
739 | { | |
740 | /* Don't scan past the epilogue. */ | |
741 | break; | |
742 | } | |
0d39a070 DJ |
743 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
744 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
745 | (insn & 0xff) << 2); | |
746 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
747 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
748 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
749 | bits (insn, 6, 8)); | |
750 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
751 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
752 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
753 | bits (insn, 0, 7)); | |
754 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
755 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
756 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
757 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
758 | regs[bits (insn, 6, 8)]); | |
759 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
760 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
761 | { | |
762 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
763 | int rm = bits (insn, 3, 6); | |
764 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
765 | } | |
29d73ae4 | 766 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 767 | { |
29d73ae4 DJ |
768 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
769 | int src_reg = (insn & 0x78) >> 3; | |
770 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 771 | } |
29d73ae4 | 772 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 773 | { |
29d73ae4 DJ |
774 | /* Handle stores to the stack. Normally pushes are used, |
775 | but with GCC -mtpcs-frame, there may be other stores | |
776 | in the prologue to create the frame. */ | |
777 | int regno = (insn >> 8) & 0x7; | |
778 | pv_t addr; | |
779 | ||
780 | offset = (insn & 0xff) << 2; | |
781 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
782 | ||
f7b7ed97 | 783 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
784 | break; |
785 | ||
f7b7ed97 | 786 | stack.store (addr, 4, regs[regno]); |
da59e081 | 787 | } |
0d39a070 DJ |
788 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
789 | { | |
790 | int rd = bits (insn, 0, 2); | |
791 | int rn = bits (insn, 3, 5); | |
792 | pv_t addr; | |
793 | ||
794 | offset = bits (insn, 6, 10) << 2; | |
795 | addr = pv_add_constant (regs[rn], offset); | |
796 | ||
f7b7ed97 | 797 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
798 | break; |
799 | ||
f7b7ed97 | 800 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
801 | } |
802 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
803 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
804 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
805 | /* Ignore stores of argument registers to the stack. */ | |
806 | ; | |
807 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
808 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
809 | /* Ignore block loads from the stack, potentially copying | |
810 | parameters from memory. */ | |
811 | ; | |
812 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
813 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
814 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
815 | /* Similarly ignore single loads from the stack. */ | |
816 | ; | |
817 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
818 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
819 | /* Skip register copies, i.e. saves to another register | |
820 | instead of the stack. */ | |
821 | ; | |
822 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
823 | /* Recognize constant loads; even with small stacks these are necessary | |
824 | on Thumb. */ | |
825 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
826 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
827 | { | |
828 | /* Constant pool loads, for the same reason. */ | |
829 | unsigned int constant; | |
830 | CORE_ADDR loc; | |
831 | ||
832 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
833 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
834 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
835 | } | |
db24da6d | 836 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 837 | { |
0d39a070 DJ |
838 | unsigned short inst2; |
839 | ||
198cd59d YQ |
840 | inst2 = read_code_unsigned_integer (start + 2, 2, |
841 | byte_order_for_code); | |
0d39a070 DJ |
842 | |
843 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
844 | { | |
845 | /* BL, BLX. Allow some special function calls when | |
846 | skipping the prologue; GCC generates these before | |
847 | storing arguments to the stack. */ | |
848 | CORE_ADDR nextpc; | |
849 | int j1, j2, imm1, imm2; | |
850 | ||
851 | imm1 = sbits (insn, 0, 10); | |
852 | imm2 = bits (inst2, 0, 10); | |
853 | j1 = bit (inst2, 13); | |
854 | j2 = bit (inst2, 11); | |
855 | ||
856 | offset = ((imm1 << 12) + (imm2 << 1)); | |
857 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
858 | ||
859 | nextpc = start + 4 + offset; | |
860 | /* For BLX make sure to clear the low bits. */ | |
861 | if (bit (inst2, 12) == 0) | |
862 | nextpc = nextpc & 0xfffffffc; | |
863 | ||
e0634ccf UW |
864 | if (!skip_prologue_function (gdbarch, nextpc, |
865 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
866 | break; |
867 | } | |
ec3d575a | 868 | |
0963b4bd MS |
869 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
870 | { registers } */ | |
ec3d575a UW |
871 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
872 | { | |
873 | pv_t addr = regs[bits (insn, 0, 3)]; | |
874 | int regno; | |
875 | ||
f7b7ed97 | 876 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
877 | break; |
878 | ||
879 | /* Calculate offsets of saved registers. */ | |
880 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
881 | if (inst2 & (1 << regno)) | |
882 | { | |
883 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 884 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
885 | } |
886 | ||
887 | if (insn & 0x0020) | |
888 | regs[bits (insn, 0, 3)] = addr; | |
889 | } | |
890 | ||
0963b4bd MS |
891 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
892 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
893 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
894 | { | |
895 | int regno1 = bits (inst2, 12, 15); | |
896 | int regno2 = bits (inst2, 8, 11); | |
897 | pv_t addr = regs[bits (insn, 0, 3)]; | |
898 | ||
899 | offset = inst2 & 0xff; | |
900 | if (insn & 0x0080) | |
901 | addr = pv_add_constant (addr, offset); | |
902 | else | |
903 | addr = pv_add_constant (addr, -offset); | |
904 | ||
f7b7ed97 | 905 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
906 | break; |
907 | ||
f7b7ed97 TT |
908 | stack.store (addr, 4, regs[regno1]); |
909 | stack.store (pv_add_constant (addr, 4), | |
910 | 4, regs[regno2]); | |
ec3d575a UW |
911 | |
912 | if (insn & 0x0020) | |
913 | regs[bits (insn, 0, 3)] = addr; | |
914 | } | |
915 | ||
916 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
917 | && (inst2 & 0x0c00) == 0x0c00 | |
918 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
919 | { | |
920 | int regno = bits (inst2, 12, 15); | |
921 | pv_t addr = regs[bits (insn, 0, 3)]; | |
922 | ||
923 | offset = inst2 & 0xff; | |
924 | if (inst2 & 0x0200) | |
925 | addr = pv_add_constant (addr, offset); | |
926 | else | |
927 | addr = pv_add_constant (addr, -offset); | |
928 | ||
f7b7ed97 | 929 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
930 | break; |
931 | ||
f7b7ed97 | 932 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
933 | |
934 | if (inst2 & 0x0100) | |
935 | regs[bits (insn, 0, 3)] = addr; | |
936 | } | |
937 | ||
938 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
939 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
940 | { | |
941 | int regno = bits (inst2, 12, 15); | |
942 | pv_t addr; | |
943 | ||
944 | offset = inst2 & 0xfff; | |
945 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
946 | ||
f7b7ed97 | 947 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
948 | break; |
949 | ||
f7b7ed97 | 950 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
951 | } |
952 | ||
953 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 954 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 955 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 956 | ; |
ec3d575a UW |
957 | |
958 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
959 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 960 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 961 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 962 | ; |
ec3d575a | 963 | |
0963b4bd MS |
964 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
965 | { registers } */ | |
ec3d575a UW |
966 | && (inst2 & 0x8000) == 0x0000 |
967 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
968 | /* Ignore block loads from the stack, potentially copying | |
969 | parameters from memory. */ | |
0d39a070 | 970 | ; |
ec3d575a | 971 | |
f8c6d152 | 972 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 973 | [Rn, #+/-imm] */ |
0d39a070 | 974 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 975 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 976 | ; |
ec3d575a UW |
977 | |
978 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
979 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 980 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 981 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 982 | ; |
ec3d575a UW |
983 | |
984 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 985 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 986 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 987 | ; |
ec3d575a UW |
988 | |
989 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
990 | && (inst2 & 0x8000) == 0x0000) | |
991 | { | |
992 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
993 | | (bits (inst2, 12, 14) << 8) | |
994 | | bits (inst2, 0, 7)); | |
995 | ||
996 | regs[bits (inst2, 8, 11)] | |
997 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
998 | thumb_expand_immediate (imm)); | |
999 | } | |
1000 | ||
1001 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1002 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1003 | { |
ec3d575a UW |
1004 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1005 | | (bits (inst2, 12, 14) << 8) | |
1006 | | bits (inst2, 0, 7)); | |
1007 | ||
1008 | regs[bits (inst2, 8, 11)] | |
1009 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1010 | } | |
1011 | ||
1012 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1013 | && (inst2 & 0x8000) == 0x0000) | |
1014 | { | |
1015 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1016 | | (bits (inst2, 12, 14) << 8) | |
1017 | | bits (inst2, 0, 7)); | |
1018 | ||
1019 | regs[bits (inst2, 8, 11)] | |
1020 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1021 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1022 | } | |
1023 | ||
1024 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1025 | && (inst2 & 0x8000) == 0x0000) | |
1026 | { | |
1027 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1028 | | (bits (inst2, 12, 14) << 8) | |
1029 | | bits (inst2, 0, 7)); | |
1030 | ||
1031 | regs[bits (inst2, 8, 11)] | |
1032 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1033 | } | |
1034 | ||
1035 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1036 | { | |
1037 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1038 | | (bits (inst2, 12, 14) << 8) | |
1039 | | bits (inst2, 0, 7)); | |
1040 | ||
1041 | regs[bits (inst2, 8, 11)] | |
1042 | = pv_constant (thumb_expand_immediate (imm)); | |
1043 | } | |
1044 | ||
1045 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1046 | { | |
621c6d5b YQ |
1047 | unsigned int imm |
1048 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1049 | |
1050 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1051 | } | |
1052 | ||
1053 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1054 | && (inst2 & 0xf0f0) == 0) | |
1055 | { | |
1056 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1057 | int src_reg = inst2 & 0xf; | |
1058 | regs[dst_reg] = regs[src_reg]; | |
1059 | } | |
1060 | ||
1061 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1062 | { | |
1063 | /* Constant pool loads. */ | |
1064 | unsigned int constant; | |
1065 | CORE_ADDR loc; | |
1066 | ||
cac395ea | 1067 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1068 | if (insn & 0x0080) |
1069 | loc = start + 4 + offset; | |
1070 | else | |
1071 | loc = start + 4 - offset; | |
1072 | ||
1073 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1074 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1075 | } | |
1076 | ||
1077 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1078 | { | |
1079 | /* Constant pool loads. */ | |
1080 | unsigned int constant; | |
1081 | CORE_ADDR loc; | |
1082 | ||
cac395ea | 1083 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1084 | if (insn & 0x0080) |
1085 | loc = start + 4 + offset; | |
1086 | else | |
1087 | loc = start + 4 - offset; | |
1088 | ||
1089 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1090 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1091 | ||
1092 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1093 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1094 | } | |
1095 | ||
1096 | else if (thumb2_instruction_changes_pc (insn, inst2)) | |
1097 | { | |
1098 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1099 | break; |
1100 | } | |
ec3d575a UW |
1101 | else |
1102 | { | |
1103 | /* The optimizer might shove anything into the prologue, | |
1104 | so we just skip what we don't recognize. */ | |
1105 | unrecognized_pc = start; | |
1106 | } | |
0d39a070 DJ |
1107 | |
1108 | start += 2; | |
1109 | } | |
ec3d575a | 1110 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1111 | { |
ec3d575a | 1112 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1113 | break; |
3d74b771 | 1114 | } |
ec3d575a UW |
1115 | else |
1116 | { | |
1117 | /* The optimizer might shove anything into the prologue, | |
1118 | so we just skip what we don't recognize. */ | |
1119 | unrecognized_pc = start; | |
1120 | } | |
29d73ae4 DJ |
1121 | |
1122 | start += 2; | |
c906108c SS |
1123 | } |
1124 | ||
0d39a070 DJ |
1125 | if (arm_debug) |
1126 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1127 | paddress (gdbarch, start)); | |
1128 | ||
ec3d575a UW |
1129 | if (unrecognized_pc == 0) |
1130 | unrecognized_pc = start; | |
1131 | ||
29d73ae4 | 1132 | if (cache == NULL) |
f7b7ed97 | 1133 | return unrecognized_pc; |
29d73ae4 | 1134 | |
29d73ae4 DJ |
1135 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1136 | { | |
1137 | /* Frame pointer is fp. Frame size is constant. */ | |
1138 | cache->framereg = ARM_FP_REGNUM; | |
1139 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1140 | } | |
1141 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1142 | { | |
1143 | /* Frame pointer is r7. Frame size is constant. */ | |
1144 | cache->framereg = THUMB_FP_REGNUM; | |
1145 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1146 | } | |
72a2e3dc | 1147 | else |
29d73ae4 DJ |
1148 | { |
1149 | /* Try the stack pointer... this is a bit desperate. */ | |
1150 | cache->framereg = ARM_SP_REGNUM; | |
1151 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1152 | } | |
29d73ae4 DJ |
1153 | |
1154 | for (i = 0; i < 16; i++) | |
f7b7ed97 | 1155 | if (stack.find_reg (gdbarch, i, &offset)) |
29d73ae4 DJ |
1156 | cache->saved_regs[i].addr = offset; |
1157 | ||
ec3d575a | 1158 | return unrecognized_pc; |
c906108c SS |
1159 | } |
1160 | ||
621c6d5b YQ |
1161 | |
1162 | /* Try to analyze the instructions starting from PC, which load symbol | |
1163 | __stack_chk_guard. Return the address of instruction after loading this | |
1164 | symbol, set the dest register number to *BASEREG, and set the size of | |
1165 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1166 | not recognized. */ | |
1167 | ||
1168 | static CORE_ADDR | |
1169 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1170 | unsigned int *destreg, int *offset) | |
1171 | { | |
1172 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1173 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1174 | unsigned int low, high, address; | |
1175 | ||
1176 | address = 0; | |
1177 | if (is_thumb) | |
1178 | { | |
1179 | unsigned short insn1 | |
198cd59d | 1180 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1181 | |
1182 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1183 | { | |
1184 | *destreg = bits (insn1, 8, 10); | |
1185 | *offset = 2; | |
6ae274b7 YQ |
1186 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1187 | address = read_memory_unsigned_integer (address, 4, | |
1188 | byte_order_for_code); | |
621c6d5b YQ |
1189 | } |
1190 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1191 | { | |
1192 | unsigned short insn2 | |
198cd59d | 1193 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1194 | |
1195 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1196 | ||
1197 | insn1 | |
198cd59d | 1198 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1199 | insn2 |
198cd59d | 1200 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1201 | |
1202 | /* movt Rd, #const */ | |
1203 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1204 | { | |
1205 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1206 | *destreg = bits (insn2, 8, 11); | |
1207 | *offset = 8; | |
1208 | address = (high << 16 | low); | |
1209 | } | |
1210 | } | |
1211 | } | |
1212 | else | |
1213 | { | |
2e9e421f | 1214 | unsigned int insn |
198cd59d | 1215 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1216 | |
6ae274b7 | 1217 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1218 | { |
6ae274b7 YQ |
1219 | address = bits (insn, 0, 11) + pc + 8; |
1220 | address = read_memory_unsigned_integer (address, 4, | |
1221 | byte_order_for_code); | |
1222 | ||
2e9e421f UW |
1223 | *destreg = bits (insn, 12, 15); |
1224 | *offset = 4; | |
1225 | } | |
1226 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1227 | { | |
1228 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1229 | ||
1230 | insn | |
198cd59d | 1231 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1232 | |
1233 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1234 | { | |
1235 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1236 | *destreg = bits (insn, 12, 15); | |
1237 | *offset = 8; | |
1238 | address = (high << 16 | low); | |
1239 | } | |
1240 | } | |
621c6d5b YQ |
1241 | } |
1242 | ||
1243 | return address; | |
1244 | } | |
1245 | ||
1246 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1247 | points to the first instruction of this sequence, return the address of |
1248 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1249 | |
1250 | On arm, this sequence of instructions is composed of mainly three steps, | |
1251 | Step 1: load symbol __stack_chk_guard, | |
1252 | Step 2: load from address of __stack_chk_guard, | |
1253 | Step 3: store it to somewhere else. | |
1254 | ||
1255 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1256 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1257 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1258 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1259 | they are, | |
1260 | ||
1261 | movw Rn, #:lower16:__stack_chk_guard | |
1262 | movt Rn, #:upper16:__stack_chk_guard | |
1263 | ||
1264 | On ARMv5t, it is, | |
1265 | ||
1266 | ldr Rn, .Label | |
1267 | .... | |
1268 | .Lable: | |
1269 | .word __stack_chk_guard | |
1270 | ||
1271 | Since ldr/str is a very popular instruction, we can't use them as | |
1272 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1273 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1274 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1275 | ||
1276 | static CORE_ADDR | |
1277 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1278 | { | |
1279 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1280 | unsigned int basereg; |
7cbd4a93 | 1281 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1282 | int offset; |
1283 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1284 | CORE_ADDR addr; | |
1285 | ||
1286 | /* Try to parse the instructions in Step 1. */ | |
1287 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1288 | &basereg, &offset); | |
1289 | if (!addr) | |
1290 | return pc; | |
1291 | ||
1292 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1293 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1294 | Otherwise, this sequence cannot be for stack protector. */ | |
1295 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1296 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1297 | return pc; |
1298 | ||
1299 | if (is_thumb) | |
1300 | { | |
1301 | unsigned int destreg; | |
1302 | unsigned short insn | |
198cd59d | 1303 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1304 | |
1305 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1306 | if ((insn & 0xf800) != 0x6800) | |
1307 | return pc; | |
1308 | if (bits (insn, 3, 5) != basereg) | |
1309 | return pc; | |
1310 | destreg = bits (insn, 0, 2); | |
1311 | ||
198cd59d YQ |
1312 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1313 | byte_order_for_code); | |
621c6d5b YQ |
1314 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1315 | if ((insn & 0xf800) != 0x6000) | |
1316 | return pc; | |
1317 | if (destreg != bits (insn, 0, 2)) | |
1318 | return pc; | |
1319 | } | |
1320 | else | |
1321 | { | |
1322 | unsigned int destreg; | |
1323 | unsigned int insn | |
198cd59d | 1324 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1325 | |
1326 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1327 | if ((insn & 0x0e500000) != 0x04100000) | |
1328 | return pc; | |
1329 | if (bits (insn, 16, 19) != basereg) | |
1330 | return pc; | |
1331 | destreg = bits (insn, 12, 15); | |
1332 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1333 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1334 | 4, byte_order_for_code); |
1335 | if ((insn & 0x0e500000) != 0x04000000) | |
1336 | return pc; | |
1337 | if (bits (insn, 12, 15) != destreg) | |
1338 | return pc; | |
1339 | } | |
1340 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1341 | on arm. */ | |
1342 | if (is_thumb) | |
1343 | return pc + offset + 4; | |
1344 | else | |
1345 | return pc + offset + 8; | |
1346 | } | |
1347 | ||
da3c6d4a MS |
1348 | /* Advance the PC across any function entry prologue instructions to |
1349 | reach some "real" code. | |
34e8f22d RE |
1350 | |
1351 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1352 | prologue: |
c906108c | 1353 | |
c5aa993b JM |
1354 | mov ip, sp |
1355 | [stmfd sp!, {a1,a2,a3,a4}] | |
1356 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1357 | [stfe f7, [sp, #-12]!] |
1358 | [stfe f6, [sp, #-12]!] | |
1359 | [stfe f5, [sp, #-12]!] | |
1360 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1361 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1362 | |
34e8f22d | 1363 | static CORE_ADDR |
6093d2eb | 1364 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1365 | { |
a89fea3c | 1366 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1367 | |
a89fea3c JL |
1368 | /* See if we can determine the end of the prologue via the symbol table. |
1369 | If so, then return either PC, or the PC after the prologue, whichever | |
1370 | is greater. */ | |
1371 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1372 | { |
d80b854b UW |
1373 | CORE_ADDR post_prologue_pc |
1374 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1375 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1376 | |
621c6d5b YQ |
1377 | if (post_prologue_pc) |
1378 | post_prologue_pc | |
1379 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1380 | ||
1381 | ||
0d39a070 DJ |
1382 | /* GCC always emits a line note before the prologue and another |
1383 | one after, even if the two are at the same address or on the | |
1384 | same line. Take advantage of this so that we do not need to | |
1385 | know every instruction that might appear in the prologue. We | |
1386 | will have producer information for most binaries; if it is | |
1387 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1388 | if (post_prologue_pc | |
43f3e411 DE |
1389 | && (cust == NULL |
1390 | || COMPUNIT_PRODUCER (cust) == NULL | |
61012eef | 1391 | || startswith (COMPUNIT_PRODUCER (cust), "GNU ") |
c2fd7fae | 1392 | || producer_is_llvm (COMPUNIT_PRODUCER (cust)))) |
0d39a070 DJ |
1393 | return post_prologue_pc; |
1394 | ||
a89fea3c | 1395 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1396 | { |
1397 | CORE_ADDR analyzed_limit; | |
1398 | ||
1399 | /* For non-GCC compilers, make sure the entire line is an | |
1400 | acceptable prologue; GDB will round this function's | |
1401 | return value up to the end of the following line so we | |
1402 | can not skip just part of a line (and we do not want to). | |
1403 | ||
1404 | RealView does not treat the prologue specially, but does | |
1405 | associate prologue code with the opening brace; so this | |
1406 | lets us skip the first line if we think it is the opening | |
1407 | brace. */ | |
9779414d | 1408 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1409 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1410 | post_prologue_pc, NULL); | |
1411 | else | |
9ecab40c SM |
1412 | analyzed_limit |
1413 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1414 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1415 | |
1416 | if (analyzed_limit != post_prologue_pc) | |
1417 | return func_addr; | |
1418 | ||
1419 | return post_prologue_pc; | |
1420 | } | |
c906108c SS |
1421 | } |
1422 | ||
a89fea3c JL |
1423 | /* Can't determine prologue from the symbol table, need to examine |
1424 | instructions. */ | |
c906108c | 1425 | |
a89fea3c JL |
1426 | /* Find an upper limit on the function prologue using the debug |
1427 | information. If the debug information could not be used to provide | |
1428 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1429 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1430 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1431 | if (limit_pc == 0) |
1432 | limit_pc = pc + 64; /* Magic. */ | |
1433 | ||
c906108c | 1434 | |
29d73ae4 | 1435 | /* Check if this is Thumb code. */ |
9779414d | 1436 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1437 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1438 | else |
9ecab40c SM |
1439 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1440 | target_arm_instruction_reader ()); | |
c906108c | 1441 | } |
94c30b78 | 1442 | |
c5aa993b | 1443 | /* *INDENT-OFF* */ |
c906108c SS |
1444 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1445 | This function decodes a Thumb function prologue to determine: | |
1446 | 1) the size of the stack frame | |
1447 | 2) which registers are saved on it | |
1448 | 3) the offsets of saved regs | |
1449 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1450 | |
da59e081 JM |
1451 | A typical Thumb function prologue would create this stack frame |
1452 | (offsets relative to FP) | |
c906108c SS |
1453 | old SP -> 24 stack parameters |
1454 | 20 LR | |
1455 | 16 R7 | |
1456 | R7 -> 0 local variables (16 bytes) | |
1457 | SP -> -12 additional stack space (12 bytes) | |
1458 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1459 | 12 bytes. The frame register is R7. |
da59e081 | 1460 | |
da3c6d4a MS |
1461 | The comments for thumb_skip_prolog() describe the algorithm we use |
1462 | to detect the end of the prolog. */ | |
c5aa993b JM |
1463 | /* *INDENT-ON* */ |
1464 | ||
c906108c | 1465 | static void |
be8626e0 | 1466 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1467 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1468 | { |
1469 | CORE_ADDR prologue_start; | |
1470 | CORE_ADDR prologue_end; | |
c906108c | 1471 | |
b39cc962 DJ |
1472 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1473 | &prologue_end)) | |
c906108c | 1474 | { |
ec3d575a UW |
1475 | /* See comment in arm_scan_prologue for an explanation of |
1476 | this heuristics. */ | |
1477 | if (prologue_end > prologue_start + 64) | |
1478 | { | |
1479 | prologue_end = prologue_start + 64; | |
1480 | } | |
c906108c SS |
1481 | } |
1482 | else | |
f7060f85 DJ |
1483 | /* We're in the boondocks: we have no idea where the start of the |
1484 | function is. */ | |
1485 | return; | |
c906108c | 1486 | |
325fac50 | 1487 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1488 | |
be8626e0 | 1489 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1490 | } |
1491 | ||
f303bc3e YQ |
1492 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1493 | otherwise. */ | |
1494 | ||
1495 | static int | |
1496 | arm_instruction_restores_sp (unsigned int insn) | |
1497 | { | |
1498 | if (bits (insn, 28, 31) != INST_NV) | |
1499 | { | |
1500 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1501 | /* ADD SP (register or immediate). */ | |
1502 | || (insn & 0x0df0f000) == 0x0040d000 | |
1503 | /* SUB SP (register or immediate). */ | |
1504 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1505 | /* MOV SP. */ | |
1506 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1507 | /* POP (LDMIA). */ | |
1508 | || (insn & 0x0fff0000) == 0x049d0000) | |
1509 | /* POP of a single register. */ | |
1510 | return 1; | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
9ecab40c SM |
1516 | /* Implement immediate value decoding, as described in section A5.2.4 |
1517 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1518 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1519 | ||
1520 | static uint32_t | |
1521 | arm_expand_immediate (uint32_t imm) | |
1522 | { | |
1523 | /* Immediate values are 12 bits long. */ | |
1524 | gdb_assert ((imm & 0xfffff000) == 0); | |
1525 | ||
1526 | uint32_t unrotated_value = imm & 0xff; | |
1527 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1528 | ||
1529 | if (rotate_amount == 0) | |
1530 | return unrotated_value; | |
1531 | ||
1532 | return ((unrotated_value >> rotate_amount) | |
1533 | | (unrotated_value << (32 - rotate_amount))); | |
1534 | } | |
1535 | ||
0d39a070 DJ |
1536 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1537 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1538 | fill it in. Return the first address not recognized as a prologue | |
1539 | instruction. | |
eb5492fa | 1540 | |
0d39a070 DJ |
1541 | We recognize all the instructions typically found in ARM prologues, |
1542 | plus harmless instructions which can be skipped (either for analysis | |
1543 | purposes, or a more restrictive set that can be skipped when finding | |
1544 | the end of the prologue). */ | |
1545 | ||
1546 | static CORE_ADDR | |
1547 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1548 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1549 | struct arm_prologue_cache *cache, |
1550 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1551 | { |
0d39a070 DJ |
1552 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1553 | int regno; | |
1554 | CORE_ADDR offset, current_pc; | |
1555 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 DJ |
1556 | CORE_ADDR unrecognized_pc = 0; |
1557 | ||
1558 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1559 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1560 | |
96baa820 JM |
1561 | Be careful, however, and if it doesn't look like a prologue, |
1562 | don't try to scan it. If, for instance, a frameless function | |
1563 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1564 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1565 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1566 | traceback. */ |
d4473757 | 1567 | |
4be43953 DJ |
1568 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1569 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1570 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1571 | |
94c30b78 MS |
1572 | for (current_pc = prologue_start; |
1573 | current_pc < prologue_end; | |
f43845b3 | 1574 | current_pc += 4) |
96baa820 | 1575 | { |
9ecab40c | 1576 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1577 | |
94c30b78 | 1578 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1579 | { |
4be43953 | 1580 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1581 | continue; |
1582 | } | |
0d39a070 DJ |
1583 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1584 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1585 | { |
9ecab40c | 1586 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1587 | int rd = bits (insn, 12, 15); |
0d39a070 | 1588 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1589 | continue; |
1590 | } | |
0d39a070 DJ |
1591 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1592 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1593 | { |
9ecab40c | 1594 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1595 | int rd = bits (insn, 12, 15); |
0d39a070 | 1596 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1597 | continue; |
1598 | } | |
0963b4bd MS |
1599 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1600 | [sp, #-4]! */ | |
f43845b3 | 1601 | { |
f7b7ed97 | 1602 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1603 | break; |
1604 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
1605 | stack.store (regs[ARM_SP_REGNUM], 4, |
1606 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1607 | continue; |
1608 | } | |
1609 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1610 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1611 | or | |
1612 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1613 | { |
d4473757 | 1614 | int mask = insn & 0xffff; |
ed9a39eb | 1615 | |
f7b7ed97 | 1616 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1617 | break; |
1618 | ||
94c30b78 | 1619 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1620 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1621 | if (mask & (1 << regno)) |
1622 | { | |
0963b4bd MS |
1623 | regs[ARM_SP_REGNUM] |
1624 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 1625 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1626 | } |
1627 | } | |
0d39a070 DJ |
1628 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1629 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1630 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1631 | { |
1632 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1633 | continue; | |
1634 | } | |
0d39a070 DJ |
1635 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1636 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1637 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1638 | { |
1639 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1640 | continue; | |
1641 | } | |
0963b4bd MS |
1642 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1643 | { registers } */ | |
0d39a070 DJ |
1644 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1645 | { | |
1646 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1647 | continue; | |
1648 | } | |
d4473757 KB |
1649 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1650 | { | |
9ecab40c | 1651 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 1652 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1653 | } |
1654 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1655 | { | |
9ecab40c | 1656 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 1657 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1658 | } |
0963b4bd MS |
1659 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1660 | [sp, -#c]! */ | |
2af46ca0 | 1661 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 1662 | { |
f7b7ed97 | 1663 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1664 | break; |
1665 | ||
1666 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1667 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 1668 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1669 | } |
0963b4bd MS |
1670 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1671 | [sp!] */ | |
2af46ca0 | 1672 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
1673 | { |
1674 | int n_saved_fp_regs; | |
1675 | unsigned int fp_start_reg, fp_bound_reg; | |
1676 | ||
f7b7ed97 | 1677 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1678 | break; |
1679 | ||
94c30b78 | 1680 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1681 | { |
d4473757 KB |
1682 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1683 | n_saved_fp_regs = 3; | |
1684 | else | |
1685 | n_saved_fp_regs = 1; | |
96baa820 | 1686 | } |
d4473757 | 1687 | else |
96baa820 | 1688 | { |
d4473757 KB |
1689 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1690 | n_saved_fp_regs = 2; | |
1691 | else | |
1692 | n_saved_fp_regs = 4; | |
96baa820 | 1693 | } |
d4473757 | 1694 | |
34e8f22d | 1695 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1696 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1697 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1698 | { |
4be43953 | 1699 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
1700 | stack.store (regs[ARM_SP_REGNUM], 12, |
1701 | regs[fp_start_reg++]); | |
96baa820 | 1702 | } |
c906108c | 1703 | } |
0d39a070 DJ |
1704 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
1705 | { | |
1706 | /* Allow some special function calls when skipping the | |
1707 | prologue; GCC generates these before storing arguments to | |
1708 | the stack. */ | |
1709 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
1710 | ||
e0634ccf | 1711 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
1712 | continue; |
1713 | else | |
1714 | break; | |
1715 | } | |
d4473757 | 1716 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 1717 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
1718 | else if (arm_instruction_changes_pc (insn)) |
1719 | /* Don't scan past anything that might change control flow. */ | |
1720 | break; | |
f303bc3e YQ |
1721 | else if (arm_instruction_restores_sp (insn)) |
1722 | { | |
1723 | /* Don't scan past the epilogue. */ | |
1724 | break; | |
1725 | } | |
d19f7eee UW |
1726 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
1727 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1728 | /* Ignore block loads from the stack, potentially copying | |
1729 | parameters from memory. */ | |
1730 | continue; | |
1731 | else if ((insn & 0xfc500000) == 0xe4100000 | |
1732 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1733 | /* Similarly ignore single loads from the stack. */ | |
1734 | continue; | |
0d39a070 DJ |
1735 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
1736 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
1737 | register instead of the stack. */ | |
d4473757 | 1738 | continue; |
0d39a070 DJ |
1739 | else |
1740 | { | |
21daaaaf YQ |
1741 | /* The optimizer might shove anything into the prologue, if |
1742 | we build up cache (cache != NULL) from scanning prologue, | |
1743 | we just skip what we don't recognize and scan further to | |
1744 | make cache as complete as possible. However, if we skip | |
1745 | prologue, we'll stop immediately on unrecognized | |
1746 | instruction. */ | |
0d39a070 | 1747 | unrecognized_pc = current_pc; |
21daaaaf YQ |
1748 | if (cache != NULL) |
1749 | continue; | |
1750 | else | |
1751 | break; | |
0d39a070 | 1752 | } |
c906108c SS |
1753 | } |
1754 | ||
0d39a070 DJ |
1755 | if (unrecognized_pc == 0) |
1756 | unrecognized_pc = current_pc; | |
1757 | ||
0d39a070 DJ |
1758 | if (cache) |
1759 | { | |
4072f920 YQ |
1760 | int framereg, framesize; |
1761 | ||
1762 | /* The frame size is just the distance from the frame register | |
1763 | to the original stack pointer. */ | |
1764 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1765 | { | |
1766 | /* Frame pointer is fp. */ | |
1767 | framereg = ARM_FP_REGNUM; | |
1768 | framesize = -regs[ARM_FP_REGNUM].k; | |
1769 | } | |
1770 | else | |
1771 | { | |
1772 | /* Try the stack pointer... this is a bit desperate. */ | |
1773 | framereg = ARM_SP_REGNUM; | |
1774 | framesize = -regs[ARM_SP_REGNUM].k; | |
1775 | } | |
1776 | ||
0d39a070 DJ |
1777 | cache->framereg = framereg; |
1778 | cache->framesize = framesize; | |
1779 | ||
1780 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 1781 | if (stack.find_reg (gdbarch, regno, &offset)) |
0d39a070 DJ |
1782 | cache->saved_regs[regno].addr = offset; |
1783 | } | |
1784 | ||
1785 | if (arm_debug) | |
1786 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1787 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 1788 | |
0d39a070 DJ |
1789 | return unrecognized_pc; |
1790 | } | |
1791 | ||
1792 | static void | |
1793 | arm_scan_prologue (struct frame_info *this_frame, | |
1794 | struct arm_prologue_cache *cache) | |
1795 | { | |
1796 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1797 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 1798 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
1799 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
1800 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
0d39a070 DJ |
1801 | |
1802 | /* Assume there is no frame until proven otherwise. */ | |
1803 | cache->framereg = ARM_SP_REGNUM; | |
1804 | cache->framesize = 0; | |
1805 | ||
1806 | /* Check for Thumb prologue. */ | |
1807 | if (arm_frame_is_thumb (this_frame)) | |
1808 | { | |
1809 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
1810 | return; | |
1811 | } | |
1812 | ||
1813 | /* Find the function prologue. If we can't find the function in | |
1814 | the symbol table, peek in the stack frame to find the PC. */ | |
1815 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
1816 | &prologue_end)) | |
1817 | { | |
1818 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 1819 | for unoptimized code) is to do the following: |
0d39a070 DJ |
1820 | |
1821 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
1822 | ||
1823 | if (sal.line == 0) | |
1824 | prologue_end = prev_pc; | |
1825 | else if (sal.end < prologue_end) | |
1826 | prologue_end = sal.end; | |
1827 | ||
1828 | This mechanism is very accurate so long as the optimizer | |
1829 | doesn't move any instructions from the function body into the | |
1830 | prologue. If this happens, sal.end will be the last | |
1831 | instruction in the first hunk of prologue code just before | |
1832 | the first instruction that the scheduler has moved from | |
1833 | the body to the prologue. | |
1834 | ||
1835 | In order to make sure that we scan all of the prologue | |
1836 | instructions, we use a slightly less accurate mechanism which | |
1837 | may scan more than necessary. To help compensate for this | |
1838 | lack of accuracy, the prologue scanning loop below contains | |
1839 | several clauses which'll cause the loop to terminate early if | |
1840 | an implausible prologue instruction is encountered. | |
1841 | ||
1842 | The expression | |
1843 | ||
1844 | prologue_start + 64 | |
1845 | ||
1846 | is a suitable endpoint since it accounts for the largest | |
1847 | possible prologue plus up to five instructions inserted by | |
1848 | the scheduler. */ | |
1849 | ||
1850 | if (prologue_end > prologue_start + 64) | |
1851 | { | |
1852 | prologue_end = prologue_start + 64; /* See above. */ | |
1853 | } | |
1854 | } | |
1855 | else | |
1856 | { | |
1857 | /* We have no symbol information. Our only option is to assume this | |
1858 | function has a standard stack frame and the normal frame register. | |
1859 | Then, we can find the value of our frame pointer on entrance to | |
1860 | the callee (or at the present moment if this is the innermost frame). | |
1861 | The value stored there should be the address of the stmfd + 8. */ | |
1862 | CORE_ADDR frame_loc; | |
7913a64c | 1863 | ULONGEST return_value; |
0d39a070 | 1864 | |
9e237747 MM |
1865 | /* AAPCS does not use a frame register, so we can abort here. */ |
1866 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_AAPCS) | |
dda83cd7 | 1867 | return; |
9e237747 | 1868 | |
0d39a070 | 1869 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
1870 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
1871 | &return_value)) | |
dda83cd7 | 1872 | return; |
0d39a070 | 1873 | else |
dda83cd7 SM |
1874 | { |
1875 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 1876 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
1877 | prologue_end = prologue_start + 64; /* See above. */ |
1878 | } | |
0d39a070 DJ |
1879 | } |
1880 | ||
1881 | if (prev_pc < prologue_end) | |
1882 | prologue_end = prev_pc; | |
1883 | ||
9ecab40c SM |
1884 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
1885 | target_arm_instruction_reader ()); | |
c906108c SS |
1886 | } |
1887 | ||
eb5492fa | 1888 | static struct arm_prologue_cache * |
a262aec2 | 1889 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1890 | { |
eb5492fa DJ |
1891 | int reg; |
1892 | struct arm_prologue_cache *cache; | |
1893 | CORE_ADDR unwound_fp; | |
c5aa993b | 1894 | |
35d5d4ee | 1895 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1896 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1897 | |
a262aec2 | 1898 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1899 | |
a262aec2 | 1900 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1901 | if (unwound_fp == 0) |
1902 | return cache; | |
c906108c | 1903 | |
4be43953 | 1904 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1905 | |
eb5492fa DJ |
1906 | /* Calculate actual addresses of saved registers using offsets |
1907 | determined by arm_scan_prologue. */ | |
a262aec2 | 1908 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 1909 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
1910 | cache->saved_regs[reg].addr += cache->prev_sp; |
1911 | ||
1912 | return cache; | |
c906108c SS |
1913 | } |
1914 | ||
c1ee9414 LM |
1915 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
1916 | ||
1917 | static enum unwind_stop_reason | |
1918 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
1919 | void **this_cache) | |
1920 | { | |
1921 | struct arm_prologue_cache *cache; | |
1922 | CORE_ADDR pc; | |
1923 | ||
1924 | if (*this_cache == NULL) | |
1925 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 1926 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
1927 | |
1928 | /* This is meant to halt the backtrace at "_start". */ | |
1929 | pc = get_frame_pc (this_frame); | |
1930 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
1931 | return UNWIND_OUTERMOST; | |
1932 | ||
1933 | /* If we've hit a wall, stop. */ | |
1934 | if (cache->prev_sp == 0) | |
1935 | return UNWIND_OUTERMOST; | |
1936 | ||
1937 | return UNWIND_NO_REASON; | |
1938 | } | |
1939 | ||
eb5492fa DJ |
1940 | /* Our frame ID for a normal frame is the current function's starting PC |
1941 | and the caller's SP when we were called. */ | |
c906108c | 1942 | |
148754e5 | 1943 | static void |
a262aec2 | 1944 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1945 | void **this_cache, |
1946 | struct frame_id *this_id) | |
c906108c | 1947 | { |
eb5492fa DJ |
1948 | struct arm_prologue_cache *cache; |
1949 | struct frame_id id; | |
2c404490 | 1950 | CORE_ADDR pc, func; |
f079148d | 1951 | |
eb5492fa | 1952 | if (*this_cache == NULL) |
a262aec2 | 1953 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1954 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 1955 | |
0e9e9abd UW |
1956 | /* Use function start address as part of the frame ID. If we cannot |
1957 | identify the start address (due to missing symbol information), | |
1958 | fall back to just using the current PC. */ | |
c1ee9414 | 1959 | pc = get_frame_pc (this_frame); |
2c404490 | 1960 | func = get_frame_func (this_frame); |
0e9e9abd UW |
1961 | if (!func) |
1962 | func = pc; | |
1963 | ||
eb5492fa | 1964 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1965 | *this_id = id; |
c906108c SS |
1966 | } |
1967 | ||
a262aec2 DJ |
1968 | static struct value * |
1969 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1970 | void **this_cache, |
a262aec2 | 1971 | int prev_regnum) |
24de872b | 1972 | { |
24568a2c | 1973 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1974 | struct arm_prologue_cache *cache; |
1975 | ||
eb5492fa | 1976 | if (*this_cache == NULL) |
a262aec2 | 1977 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1978 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 1979 | |
eb5492fa | 1980 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1981 | instead. The prologue may save PC, but it will point into this |
1982 | frame's prologue, not the next frame's resume location. Also | |
1983 | strip the saved T bit. A valid LR may have the low bit set, but | |
1984 | a valid PC never does. */ | |
eb5492fa | 1985 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1986 | { |
1987 | CORE_ADDR lr; | |
1988 | ||
1989 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1990 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1991 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1992 | } |
24de872b | 1993 | |
eb5492fa | 1994 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1995 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1996 | The value was already reconstructed into PREV_SP. */ |
1997 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1998 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1999 | |
b39cc962 DJ |
2000 | /* The CPSR may have been changed by the call instruction and by the |
2001 | called function. The only bit we can reconstruct is the T bit, | |
2002 | by checking the low bit of LR as of the call. This is a reliable | |
2003 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2004 | Thumb code, which could get away with a clear low bit as long as | |
2005 | the called function did not use bx. Guess that all other | |
2006 | bits are unchanged; the condition flags are presumably lost, | |
2007 | but the processor status is likely valid. */ | |
2008 | if (prev_regnum == ARM_PS_REGNUM) | |
2009 | { | |
2010 | CORE_ADDR lr, cpsr; | |
9779414d | 2011 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
2012 | |
2013 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
2014 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2015 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 2016 | cpsr |= t_bit; |
b39cc962 | 2017 | else |
9779414d | 2018 | cpsr &= ~t_bit; |
b39cc962 DJ |
2019 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2020 | } | |
2021 | ||
a262aec2 DJ |
2022 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2023 | prev_regnum); | |
eb5492fa DJ |
2024 | } |
2025 | ||
2026 | struct frame_unwind arm_prologue_unwind = { | |
2027 | NORMAL_FRAME, | |
c1ee9414 | 2028 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2029 | arm_prologue_this_id, |
a262aec2 DJ |
2030 | arm_prologue_prev_register, |
2031 | NULL, | |
2032 | default_frame_sniffer | |
eb5492fa DJ |
2033 | }; |
2034 | ||
0e9e9abd UW |
2035 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2036 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2037 | personality routines; the cache will contain only the frame unwinding | |
2038 | instructions associated with the entry (not the descriptors). */ | |
2039 | ||
0e9e9abd UW |
2040 | struct arm_exidx_entry |
2041 | { | |
227031b2 | 2042 | CORE_ADDR addr; |
0e9e9abd | 2043 | gdb_byte *entry; |
7a5d944b TT |
2044 | |
2045 | bool operator< (const arm_exidx_entry &other) const | |
2046 | { | |
2047 | return addr < other.addr; | |
2048 | } | |
0e9e9abd | 2049 | }; |
0e9e9abd UW |
2050 | |
2051 | struct arm_exidx_data | |
2052 | { | |
7a5d944b | 2053 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2054 | }; |
2055 | ||
a2726d4f LM |
2056 | /* Per-BFD key to store exception handling information. */ |
2057 | static const struct bfd_key<arm_exidx_data> arm_exidx_data_key; | |
0e9e9abd UW |
2058 | |
2059 | static struct obj_section * | |
2060 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2061 | { | |
2062 | struct obj_section *osect; | |
2063 | ||
2064 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2065 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2066 | { |
2067 | bfd_vma start, size; | |
fd361982 AM |
2068 | start = bfd_section_vma (osect->the_bfd_section); |
2069 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2070 | |
2071 | if (start <= vma && vma < start + size) | |
2072 | return osect; | |
2073 | } | |
2074 | ||
2075 | return NULL; | |
2076 | } | |
2077 | ||
2078 | /* Parse contents of exception table and exception index sections | |
2079 | of OBJFILE, and fill in the exception table entry cache. | |
2080 | ||
2081 | For each entry that refers to a standard ARM-defined personality | |
2082 | routine, extract the frame unwinding instructions (from either | |
2083 | the index or the table section). The unwinding instructions | |
2084 | are normalized by: | |
2085 | - extracting them from the rest of the table data | |
2086 | - converting to host endianness | |
2087 | - appending the implicit 0xb0 ("Finish") code | |
2088 | ||
2089 | The extracted and normalized instructions are stored for later | |
2090 | retrieval by the arm_find_exidx_entry routine. */ | |
2091 | ||
2092 | static void | |
2093 | arm_exidx_new_objfile (struct objfile *objfile) | |
2094 | { | |
0e9e9abd UW |
2095 | struct arm_exidx_data *data; |
2096 | asection *exidx, *extab; | |
2097 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2098 | LONGEST i; |
2099 | ||
2100 | /* If we've already touched this file, do nothing. */ | |
a2726d4f | 2101 | if (!objfile || arm_exidx_data_key.get (objfile->obfd) != NULL) |
0e9e9abd UW |
2102 | return; |
2103 | ||
2104 | /* Read contents of exception table and index. */ | |
a5eda10c | 2105 | exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); |
984c7238 | 2106 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2107 | if (exidx) |
2108 | { | |
fd361982 AM |
2109 | exidx_vma = bfd_section_vma (exidx); |
2110 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd UW |
2111 | |
2112 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
984c7238 TT |
2113 | exidx_data.data (), 0, |
2114 | exidx_data.size ())) | |
2115 | return; | |
0e9e9abd UW |
2116 | } |
2117 | ||
2118 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
984c7238 | 2119 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2120 | if (extab) |
2121 | { | |
fd361982 AM |
2122 | extab_vma = bfd_section_vma (extab); |
2123 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd UW |
2124 | |
2125 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
984c7238 TT |
2126 | extab_data.data (), 0, |
2127 | extab_data.size ())) | |
2128 | return; | |
0e9e9abd UW |
2129 | } |
2130 | ||
2131 | /* Allocate exception table data structure. */ | |
a2726d4f | 2132 | data = arm_exidx_data_key.emplace (objfile->obfd); |
7a5d944b | 2133 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2134 | |
2135 | /* Fill in exception table. */ | |
984c7238 | 2136 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2137 | { |
2138 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2139 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2140 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2141 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2142 | bfd_vma addr = 0, word = 0; |
2143 | int n_bytes = 0, n_words = 0; | |
2144 | struct obj_section *sec; | |
2145 | gdb_byte *entry = NULL; | |
2146 | ||
2147 | /* Extract address of start of function. */ | |
2148 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2149 | idx += exidx_vma + i * 8; | |
2150 | ||
2151 | /* Find section containing function and compute section offset. */ | |
2152 | sec = arm_obj_section_from_vma (objfile, idx); | |
2153 | if (sec == NULL) | |
2154 | continue; | |
fd361982 | 2155 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2156 | |
2157 | /* Determine address of exception table entry. */ | |
2158 | if (val == 1) | |
2159 | { | |
2160 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2161 | } | |
2162 | else if ((val & 0xff000000) == 0x80000000) | |
2163 | { | |
2164 | /* Exception table entry embedded in .ARM.exidx | |
2165 | -- must be short form. */ | |
2166 | word = val; | |
2167 | n_bytes = 3; | |
2168 | } | |
2169 | else if (!(val & 0x80000000)) | |
2170 | { | |
2171 | /* Exception table entry in .ARM.extab. */ | |
2172 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2173 | addr += exidx_vma + i * 8 + 4; | |
2174 | ||
984c7238 | 2175 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2176 | { |
2177 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2178 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2179 | addr += 4; |
2180 | ||
2181 | if ((word & 0xff000000) == 0x80000000) | |
2182 | { | |
2183 | /* Short form. */ | |
2184 | n_bytes = 3; | |
2185 | } | |
2186 | else if ((word & 0xff000000) == 0x81000000 | |
2187 | || (word & 0xff000000) == 0x82000000) | |
2188 | { | |
2189 | /* Long form. */ | |
2190 | n_bytes = 2; | |
2191 | n_words = ((word >> 16) & 0xff); | |
2192 | } | |
2193 | else if (!(word & 0x80000000)) | |
2194 | { | |
2195 | bfd_vma pers; | |
2196 | struct obj_section *pers_sec; | |
2197 | int gnu_personality = 0; | |
2198 | ||
2199 | /* Custom personality routine. */ | |
2200 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2201 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2202 | ||
2203 | /* Check whether we've got one of the variants of the | |
2204 | GNU personality routines. */ | |
2205 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2206 | if (pers_sec) | |
2207 | { | |
2208 | static const char *personality[] = | |
2209 | { | |
2210 | "__gcc_personality_v0", | |
2211 | "__gxx_personality_v0", | |
2212 | "__gcj_personality_v0", | |
2213 | "__gnu_objc_personality_v0", | |
2214 | NULL | |
2215 | }; | |
2216 | ||
2217 | CORE_ADDR pc = pers + obj_section_offset (pers_sec); | |
2218 | int k; | |
2219 | ||
2220 | for (k = 0; personality[k]; k++) | |
2221 | if (lookup_minimal_symbol_by_pc_name | |
2222 | (pc, personality[k], objfile)) | |
2223 | { | |
2224 | gnu_personality = 1; | |
2225 | break; | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | /* If so, the next word contains a word count in the high | |
2230 | byte, followed by the same unwind instructions as the | |
2231 | pre-defined forms. */ | |
2232 | if (gnu_personality | |
984c7238 | 2233 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2234 | { |
2235 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2236 | (extab_data.data () |
2237 | + addr - extab_vma)); | |
0e9e9abd UW |
2238 | addr += 4; |
2239 | n_bytes = 3; | |
2240 | n_words = ((word >> 24) & 0xff); | |
2241 | } | |
2242 | } | |
2243 | } | |
2244 | } | |
2245 | ||
2246 | /* Sanity check address. */ | |
2247 | if (n_words) | |
984c7238 TT |
2248 | if (addr < extab_vma |
2249 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2250 | n_words = n_bytes = 0; |
2251 | ||
2252 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2253 | significant bytes are valid), followed by N_WORDS words in the | |
2254 | extab section starting at ADDR. */ | |
2255 | if (n_bytes || n_words) | |
2256 | { | |
224c3ddb SM |
2257 | gdb_byte *p = entry |
2258 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2259 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2260 | |
2261 | while (n_bytes--) | |
2262 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2263 | ||
2264 | while (n_words--) | |
2265 | { | |
2266 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2267 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2268 | addr += 4; |
2269 | ||
2270 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2271 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2272 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2273 | *p++ = (gdb_byte) (word & 0xff); | |
2274 | } | |
2275 | ||
2276 | /* Implied "Finish" to terminate the list. */ | |
2277 | *p++ = 0xb0; | |
2278 | } | |
2279 | ||
2280 | /* Push entry onto vector. They are guaranteed to always | |
2281 | appear in order of increasing addresses. */ | |
2282 | new_exidx_entry.addr = idx; | |
2283 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2284 | data->section_maps[sec->the_bfd_section->index].push_back |
2285 | (new_exidx_entry); | |
0e9e9abd | 2286 | } |
0e9e9abd UW |
2287 | } |
2288 | ||
2289 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2290 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2291 | set *START to the start of the region covered by this entry. */ | |
2292 | ||
2293 | static gdb_byte * | |
2294 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2295 | { | |
2296 | struct obj_section *sec; | |
2297 | ||
2298 | sec = find_pc_section (memaddr); | |
2299 | if (sec != NULL) | |
2300 | { | |
2301 | struct arm_exidx_data *data; | |
0e9e9abd | 2302 | struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 }; |
0e9e9abd | 2303 | |
a2726d4f | 2304 | data = arm_exidx_data_key.get (sec->objfile->obfd); |
0e9e9abd UW |
2305 | if (data != NULL) |
2306 | { | |
7a5d944b TT |
2307 | std::vector<arm_exidx_entry> &map |
2308 | = data->section_maps[sec->the_bfd_section->index]; | |
2309 | if (!map.empty ()) | |
0e9e9abd | 2310 | { |
7a5d944b | 2311 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2312 | |
7a5d944b | 2313 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2314 | point. If the following symbol starts at this exact |
2315 | address, we use that; otherwise, the preceding | |
2316 | exception table entry covers this address. */ | |
7a5d944b | 2317 | if (idx < map.end ()) |
0e9e9abd | 2318 | { |
7a5d944b | 2319 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2320 | { |
2321 | if (start) | |
7a5d944b TT |
2322 | *start = idx->addr + obj_section_addr (sec); |
2323 | return idx->entry; | |
0e9e9abd UW |
2324 | } |
2325 | } | |
2326 | ||
7a5d944b | 2327 | if (idx > map.begin ()) |
0e9e9abd | 2328 | { |
7a5d944b | 2329 | idx = idx - 1; |
0e9e9abd | 2330 | if (start) |
7a5d944b TT |
2331 | *start = idx->addr + obj_section_addr (sec); |
2332 | return idx->entry; | |
0e9e9abd UW |
2333 | } |
2334 | } | |
2335 | } | |
2336 | } | |
2337 | ||
2338 | return NULL; | |
2339 | } | |
2340 | ||
2341 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2342 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2343 | return a prologue cache structure describing how to unwind this frame. | |
2344 | ||
2345 | Return NULL if the unwinding instruction list contains a "spare", | |
2346 | "reserved" or "refuse to unwind" instruction as defined in section | |
2347 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2348 | for the ARM Architecture" document. */ | |
2349 | ||
2350 | static struct arm_prologue_cache * | |
2351 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2352 | { | |
2353 | CORE_ADDR vsp = 0; | |
2354 | int vsp_valid = 0; | |
2355 | ||
2356 | struct arm_prologue_cache *cache; | |
2357 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2358 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2359 | ||
2360 | for (;;) | |
2361 | { | |
2362 | gdb_byte insn; | |
2363 | ||
2364 | /* Whenever we reload SP, we actually have to retrieve its | |
2365 | actual value in the current frame. */ | |
2366 | if (!vsp_valid) | |
2367 | { | |
2368 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2369 | { | |
2370 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2371 | vsp = get_frame_register_unsigned (this_frame, reg); | |
2372 | } | |
2373 | else | |
2374 | { | |
2375 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr; | |
2376 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); | |
2377 | } | |
2378 | ||
2379 | vsp_valid = 1; | |
2380 | } | |
2381 | ||
2382 | /* Decode next unwind instruction. */ | |
2383 | insn = *entry++; | |
2384 | ||
2385 | if ((insn & 0xc0) == 0) | |
2386 | { | |
2387 | int offset = insn & 0x3f; | |
2388 | vsp += (offset << 2) + 4; | |
2389 | } | |
2390 | else if ((insn & 0xc0) == 0x40) | |
2391 | { | |
2392 | int offset = insn & 0x3f; | |
2393 | vsp -= (offset << 2) + 4; | |
2394 | } | |
2395 | else if ((insn & 0xf0) == 0x80) | |
2396 | { | |
2397 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2398 | int i; | |
2399 | ||
2400 | /* The special case of an all-zero mask identifies | |
2401 | "Refuse to unwind". We return NULL to fall back | |
2402 | to the prologue analyzer. */ | |
2403 | if (mask == 0) | |
2404 | return NULL; | |
2405 | ||
2406 | /* Pop registers r4..r15 under mask. */ | |
2407 | for (i = 0; i < 12; i++) | |
2408 | if (mask & (1 << i)) | |
2409 | { | |
dda83cd7 | 2410 | cache->saved_regs[4 + i].addr = vsp; |
0e9e9abd UW |
2411 | vsp += 4; |
2412 | } | |
2413 | ||
2414 | /* Special-case popping SP -- we need to reload vsp. */ | |
2415 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2416 | vsp_valid = 0; | |
2417 | } | |
2418 | else if ((insn & 0xf0) == 0x90) | |
2419 | { | |
2420 | int reg = insn & 0xf; | |
2421 | ||
2422 | /* Reserved cases. */ | |
2423 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2424 | return NULL; | |
2425 | ||
2426 | /* Set SP from another register and mark VSP for reload. */ | |
2427 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2428 | vsp_valid = 0; | |
2429 | } | |
2430 | else if ((insn & 0xf0) == 0xa0) | |
2431 | { | |
2432 | int count = insn & 0x7; | |
2433 | int pop_lr = (insn & 0x8) != 0; | |
2434 | int i; | |
2435 | ||
2436 | /* Pop r4..r[4+count]. */ | |
2437 | for (i = 0; i <= count; i++) | |
2438 | { | |
2439 | cache->saved_regs[4 + i].addr = vsp; | |
2440 | vsp += 4; | |
2441 | } | |
2442 | ||
2443 | /* If indicated by flag, pop LR as well. */ | |
2444 | if (pop_lr) | |
2445 | { | |
2446 | cache->saved_regs[ARM_LR_REGNUM].addr = vsp; | |
2447 | vsp += 4; | |
2448 | } | |
2449 | } | |
2450 | else if (insn == 0xb0) | |
2451 | { | |
2452 | /* We could only have updated PC by popping into it; if so, it | |
2453 | will show up as address. Otherwise, copy LR into PC. */ | |
2454 | if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM)) | |
2455 | cache->saved_regs[ARM_PC_REGNUM] | |
2456 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2457 | ||
2458 | /* We're done. */ | |
2459 | break; | |
2460 | } | |
2461 | else if (insn == 0xb1) | |
2462 | { | |
2463 | int mask = *entry++; | |
2464 | int i; | |
2465 | ||
2466 | /* All-zero mask and mask >= 16 is "spare". */ | |
2467 | if (mask == 0 || mask >= 16) | |
2468 | return NULL; | |
2469 | ||
2470 | /* Pop r0..r3 under mask. */ | |
2471 | for (i = 0; i < 4; i++) | |
2472 | if (mask & (1 << i)) | |
2473 | { | |
2474 | cache->saved_regs[i].addr = vsp; | |
2475 | vsp += 4; | |
2476 | } | |
2477 | } | |
2478 | else if (insn == 0xb2) | |
2479 | { | |
2480 | ULONGEST offset = 0; | |
2481 | unsigned shift = 0; | |
2482 | ||
2483 | do | |
2484 | { | |
2485 | offset |= (*entry & 0x7f) << shift; | |
2486 | shift += 7; | |
2487 | } | |
2488 | while (*entry++ & 0x80); | |
2489 | ||
2490 | vsp += 0x204 + (offset << 2); | |
2491 | } | |
2492 | else if (insn == 0xb3) | |
2493 | { | |
2494 | int start = *entry >> 4; | |
2495 | int count = (*entry++) & 0xf; | |
2496 | int i; | |
2497 | ||
2498 | /* Only registers D0..D15 are valid here. */ | |
2499 | if (start + count >= 16) | |
2500 | return NULL; | |
2501 | ||
2502 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2503 | for (i = 0; i <= count; i++) | |
2504 | { | |
2505 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2506 | vsp += 8; | |
2507 | } | |
2508 | ||
2509 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2510 | vsp += 4; | |
2511 | } | |
2512 | else if ((insn & 0xf8) == 0xb8) | |
2513 | { | |
2514 | int count = insn & 0x7; | |
2515 | int i; | |
2516 | ||
2517 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2518 | for (i = 0; i <= count; i++) | |
2519 | { | |
2520 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2521 | vsp += 8; | |
2522 | } | |
2523 | ||
2524 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2525 | vsp += 4; | |
2526 | } | |
2527 | else if (insn == 0xc6) | |
2528 | { | |
2529 | int start = *entry >> 4; | |
2530 | int count = (*entry++) & 0xf; | |
2531 | int i; | |
2532 | ||
2533 | /* Only registers WR0..WR15 are valid. */ | |
2534 | if (start + count >= 16) | |
2535 | return NULL; | |
2536 | ||
2537 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2538 | for (i = 0; i <= count; i++) | |
2539 | { | |
2540 | cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp; | |
2541 | vsp += 8; | |
2542 | } | |
2543 | } | |
2544 | else if (insn == 0xc7) | |
2545 | { | |
2546 | int mask = *entry++; | |
2547 | int i; | |
2548 | ||
2549 | /* All-zero mask and mask >= 16 is "spare". */ | |
2550 | if (mask == 0 || mask >= 16) | |
2551 | return NULL; | |
2552 | ||
2553 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2554 | for (i = 0; i < 4; i++) | |
2555 | if (mask & (1 << i)) | |
2556 | { | |
2557 | cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp; | |
2558 | vsp += 4; | |
2559 | } | |
2560 | } | |
2561 | else if ((insn & 0xf8) == 0xc0) | |
2562 | { | |
2563 | int count = insn & 0x7; | |
2564 | int i; | |
2565 | ||
2566 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2567 | for (i = 0; i <= count; i++) | |
2568 | { | |
2569 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp; | |
2570 | vsp += 8; | |
2571 | } | |
2572 | } | |
2573 | else if (insn == 0xc8) | |
2574 | { | |
2575 | int start = *entry >> 4; | |
2576 | int count = (*entry++) & 0xf; | |
2577 | int i; | |
2578 | ||
2579 | /* Only registers D0..D31 are valid. */ | |
2580 | if (start + count >= 16) | |
2581 | return NULL; | |
2582 | ||
2583 | /* Pop VFP double-precision registers | |
2584 | D[16+start]..D[16+start+count]. */ | |
2585 | for (i = 0; i <= count; i++) | |
2586 | { | |
2587 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp; | |
2588 | vsp += 8; | |
2589 | } | |
2590 | } | |
2591 | else if (insn == 0xc9) | |
2592 | { | |
2593 | int start = *entry >> 4; | |
2594 | int count = (*entry++) & 0xf; | |
2595 | int i; | |
2596 | ||
2597 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2598 | for (i = 0; i <= count; i++) | |
2599 | { | |
2600 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2601 | vsp += 8; | |
2602 | } | |
2603 | } | |
2604 | else if ((insn & 0xf8) == 0xd0) | |
2605 | { | |
2606 | int count = insn & 0x7; | |
2607 | int i; | |
2608 | ||
2609 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2610 | for (i = 0; i <= count; i++) | |
2611 | { | |
2612 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2613 | vsp += 8; | |
2614 | } | |
2615 | } | |
2616 | else | |
2617 | { | |
2618 | /* Everything else is "spare". */ | |
2619 | return NULL; | |
2620 | } | |
2621 | } | |
2622 | ||
2623 | /* If we restore SP from a register, assume this was the frame register. | |
2624 | Otherwise just fall back to SP as frame register. */ | |
2625 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2626 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2627 | else | |
2628 | cache->framereg = ARM_SP_REGNUM; | |
2629 | ||
2630 | /* Determine offset to previous frame. */ | |
2631 | cache->framesize | |
2632 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2633 | ||
2634 | /* We already got the previous SP. */ | |
2635 | cache->prev_sp = vsp; | |
2636 | ||
2637 | return cache; | |
2638 | } | |
2639 | ||
2640 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2641 | already computes a filled-in prologue cache, which is then used | |
2642 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2643 | routines also used for prologue-parsing based unwinding. */ | |
2644 | ||
2645 | static int | |
2646 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
2647 | struct frame_info *this_frame, | |
2648 | void **this_prologue_cache) | |
2649 | { | |
2650 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2651 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2652 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
2653 | struct arm_prologue_cache *cache; | |
2654 | gdb_byte *entry; | |
2655 | ||
2656 | /* See if we have an ARM exception table entry covering this address. */ | |
2657 | addr_in_block = get_frame_address_in_block (this_frame); | |
2658 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
2659 | if (!entry) | |
2660 | return 0; | |
2661 | ||
2662 | /* The ARM exception table does not describe unwind information | |
2663 | for arbitrary PC values, but is guaranteed to be correct only | |
2664 | at call sites. We have to decide here whether we want to use | |
2665 | ARM exception table information for this frame, or fall back | |
2666 | to using prologue parsing. (Note that if we have DWARF CFI, | |
2667 | this sniffer isn't even called -- CFI is always preferred.) | |
2668 | ||
2669 | Before we make this decision, however, we check whether we | |
2670 | actually have *symbol* information for the current frame. | |
2671 | If not, prologue parsing would not work anyway, so we might | |
2672 | as well use the exception table and hope for the best. */ | |
2673 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
2674 | { | |
2675 | int exc_valid = 0; | |
2676 | ||
2677 | /* If the next frame is "normal", we are at a call site in this | |
2678 | frame, so exception information is guaranteed to be valid. */ | |
2679 | if (get_next_frame (this_frame) | |
2680 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
2681 | exc_valid = 1; | |
2682 | ||
2683 | /* We also assume exception information is valid if we're currently | |
2684 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
2685 | ensure this, so that e.g. pthread cancellation works. */ |
2686 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 2687 | { |
7913a64c | 2688 | ULONGEST insn; |
416dc9c6 | 2689 | |
7913a64c YQ |
2690 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
2691 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
2692 | && (insn & 0xff00) == 0xdf00 /* svc */) |
2693 | exc_valid = 1; | |
0e9e9abd | 2694 | } |
d9311bfa AT |
2695 | else |
2696 | { | |
7913a64c | 2697 | ULONGEST insn; |
416dc9c6 | 2698 | |
7913a64c YQ |
2699 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
2700 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
2701 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
2702 | exc_valid = 1; | |
2703 | } | |
2704 | ||
0e9e9abd UW |
2705 | /* Bail out if we don't know that exception information is valid. */ |
2706 | if (!exc_valid) | |
2707 | return 0; | |
2708 | ||
2709 | /* The ARM exception index does not mark the *end* of the region | |
2710 | covered by the entry, and some functions will not have any entry. | |
2711 | To correctly recognize the end of the covered region, the linker | |
2712 | should have inserted dummy records with a CANTUNWIND marker. | |
2713 | ||
2714 | Unfortunately, current versions of GNU ld do not reliably do | |
2715 | this, and thus we may have found an incorrect entry above. | |
2716 | As a (temporary) sanity check, we only use the entry if it | |
2717 | lies *within* the bounds of the function. Note that this check | |
2718 | might reject perfectly valid entries that just happen to cover | |
2719 | multiple functions; therefore this check ought to be removed | |
2720 | once the linker is fixed. */ | |
2721 | if (func_start > exidx_region) | |
2722 | return 0; | |
2723 | } | |
2724 | ||
2725 | /* Decode the list of unwinding instructions into a prologue cache. | |
2726 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
2727 | cache = arm_exidx_fill_cache (this_frame, entry); | |
2728 | if (!cache) | |
2729 | return 0; | |
2730 | ||
2731 | *this_prologue_cache = cache; | |
2732 | return 1; | |
2733 | } | |
2734 | ||
2735 | struct frame_unwind arm_exidx_unwind = { | |
2736 | NORMAL_FRAME, | |
8fbca658 | 2737 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
2738 | arm_prologue_this_id, |
2739 | arm_prologue_prev_register, | |
2740 | NULL, | |
2741 | arm_exidx_unwind_sniffer | |
2742 | }; | |
2743 | ||
779aa56f YQ |
2744 | static struct arm_prologue_cache * |
2745 | arm_make_epilogue_frame_cache (struct frame_info *this_frame) | |
2746 | { | |
2747 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
2748 | int reg; |
2749 | ||
2750 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2751 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2752 | ||
2753 | /* Still rely on the offset calculated from prologue. */ | |
2754 | arm_scan_prologue (this_frame, cache); | |
2755 | ||
2756 | /* Since we are in epilogue, the SP has been restored. */ | |
2757 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
2758 | ||
2759 | /* Calculate actual addresses of saved registers using offsets | |
2760 | determined by arm_scan_prologue. */ | |
2761 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
2762 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
2763 | cache->saved_regs[reg].addr += cache->prev_sp; | |
2764 | ||
2765 | return cache; | |
2766 | } | |
2767 | ||
2768 | /* Implementation of function hook 'this_id' in | |
2769 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2770 | ||
2771 | static void | |
2772 | arm_epilogue_frame_this_id (struct frame_info *this_frame, | |
2773 | void **this_cache, | |
2774 | struct frame_id *this_id) | |
2775 | { | |
2776 | struct arm_prologue_cache *cache; | |
2777 | CORE_ADDR pc, func; | |
2778 | ||
2779 | if (*this_cache == NULL) | |
2780 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
2781 | cache = (struct arm_prologue_cache *) *this_cache; | |
2782 | ||
2783 | /* Use function start address as part of the frame ID. If we cannot | |
2784 | identify the start address (due to missing symbol information), | |
2785 | fall back to just using the current PC. */ | |
2786 | pc = get_frame_pc (this_frame); | |
2787 | func = get_frame_func (this_frame); | |
fb3f3d25 | 2788 | if (func == 0) |
779aa56f YQ |
2789 | func = pc; |
2790 | ||
2791 | (*this_id) = frame_id_build (cache->prev_sp, pc); | |
2792 | } | |
2793 | ||
2794 | /* Implementation of function hook 'prev_register' in | |
2795 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2796 | ||
2797 | static struct value * | |
2798 | arm_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2799 | void **this_cache, int regnum) | |
2800 | { | |
779aa56f YQ |
2801 | if (*this_cache == NULL) |
2802 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
2803 | |
2804 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
2805 | } | |
2806 | ||
2807 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
2808 | CORE_ADDR pc); | |
2809 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
2810 | CORE_ADDR pc); | |
2811 | ||
2812 | /* Implementation of function hook 'sniffer' in | |
2813 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2814 | ||
2815 | static int | |
2816 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2817 | struct frame_info *this_frame, | |
2818 | void **this_prologue_cache) | |
2819 | { | |
2820 | if (frame_relative_level (this_frame) == 0) | |
2821 | { | |
2822 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2823 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2824 | ||
2825 | if (arm_frame_is_thumb (this_frame)) | |
2826 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
2827 | else | |
2828 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
2829 | } | |
2830 | else | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | /* Frame unwinder from epilogue. */ | |
2835 | ||
2836 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
2837 | { | |
2838 | NORMAL_FRAME, | |
2839 | default_frame_unwind_stop_reason, | |
2840 | arm_epilogue_frame_this_id, | |
2841 | arm_epilogue_frame_prev_register, | |
2842 | NULL, | |
2843 | arm_epilogue_frame_sniffer, | |
2844 | }; | |
2845 | ||
80d8d390 YQ |
2846 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
2847 | trampoline, return the target PC. Otherwise return 0. | |
2848 | ||
2849 | void call0a (char c, short s, int i, long l) {} | |
2850 | ||
2851 | int main (void) | |
2852 | { | |
2853 | (*pointer_to_call0a) (c, s, i, l); | |
2854 | } | |
2855 | ||
2856 | Instead of calling a stub library function _call_via_xx (xx is | |
2857 | the register name), GCC may inline the trampoline in the object | |
2858 | file as below (register r2 has the address of call0a). | |
2859 | ||
2860 | .global main | |
2861 | .type main, %function | |
2862 | ... | |
2863 | bl .L1 | |
2864 | ... | |
2865 | .size main, .-main | |
2866 | ||
2867 | .L1: | |
2868 | bx r2 | |
2869 | ||
2870 | The trampoline 'bx r2' doesn't belong to main. */ | |
2871 | ||
2872 | static CORE_ADDR | |
2873 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
2874 | { | |
2875 | /* The heuristics of recognizing such trampoline is that FRAME is | |
2876 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
2877 | if (arm_frame_is_thumb (frame)) | |
2878 | { | |
2879 | gdb_byte buf[2]; | |
2880 | ||
2881 | if (target_read_memory (pc, buf, 2) == 0) | |
2882 | { | |
2883 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2884 | enum bfd_endian byte_order_for_code | |
2885 | = gdbarch_byte_order_for_code (gdbarch); | |
2886 | uint16_t insn | |
2887 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
2888 | ||
2889 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
2890 | { | |
2891 | CORE_ADDR dest | |
2892 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
2893 | ||
2894 | /* Clear the LSB so that gdb core sets step-resume | |
2895 | breakpoint at the right address. */ | |
2896 | return UNMAKE_THUMB_ADDR (dest); | |
2897 | } | |
2898 | } | |
2899 | } | |
2900 | ||
2901 | return 0; | |
2902 | } | |
2903 | ||
909cf6ea | 2904 | static struct arm_prologue_cache * |
a262aec2 | 2905 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 2906 | { |
909cf6ea | 2907 | struct arm_prologue_cache *cache; |
909cf6ea | 2908 | |
35d5d4ee | 2909 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 2910 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 2911 | |
a262aec2 | 2912 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
2913 | |
2914 | return cache; | |
2915 | } | |
2916 | ||
2917 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
2918 | ||
2919 | static void | |
a262aec2 | 2920 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
2921 | void **this_cache, |
2922 | struct frame_id *this_id) | |
2923 | { | |
2924 | struct arm_prologue_cache *cache; | |
2925 | ||
2926 | if (*this_cache == NULL) | |
a262aec2 | 2927 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 2928 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 2929 | |
a262aec2 | 2930 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
2931 | } |
2932 | ||
a262aec2 DJ |
2933 | static int |
2934 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
2935 | struct frame_info *this_frame, | |
2936 | void **this_prologue_cache) | |
909cf6ea | 2937 | { |
93d42b30 | 2938 | CORE_ADDR addr_in_block; |
948f8e3d | 2939 | gdb_byte dummy[4]; |
18d18ac8 YQ |
2940 | CORE_ADDR pc, start_addr; |
2941 | const char *name; | |
909cf6ea | 2942 | |
a262aec2 | 2943 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 2944 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 2945 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
2946 | /* We also use the stub winder if the target memory is unreadable |
2947 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
2948 | || target_read_memory (pc, dummy, 4) != 0) |
2949 | return 1; | |
2950 | ||
2951 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
2952 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 2953 | return 1; |
909cf6ea | 2954 | |
a262aec2 | 2955 | return 0; |
909cf6ea DJ |
2956 | } |
2957 | ||
a262aec2 DJ |
2958 | struct frame_unwind arm_stub_unwind = { |
2959 | NORMAL_FRAME, | |
8fbca658 | 2960 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
2961 | arm_stub_this_id, |
2962 | arm_prologue_prev_register, | |
2963 | NULL, | |
2964 | arm_stub_unwind_sniffer | |
2965 | }; | |
2966 | ||
2ae28aa9 YQ |
2967 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
2968 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
2969 | returned. */ | |
2970 | ||
2971 | static struct arm_prologue_cache * | |
2972 | arm_m_exception_cache (struct frame_info *this_frame) | |
2973 | { | |
2974 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2975 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2976 | struct arm_prologue_cache *cache; | |
55ea94da FH |
2977 | CORE_ADDR lr; |
2978 | CORE_ADDR sp; | |
2ae28aa9 YQ |
2979 | CORE_ADDR unwound_sp; |
2980 | LONGEST xpsr; | |
55ea94da FH |
2981 | uint32_t exc_return; |
2982 | uint32_t process_stack_used; | |
2983 | uint32_t extended_frame_used; | |
2984 | uint32_t secure_stack_used; | |
2ae28aa9 YQ |
2985 | |
2986 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2987 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2988 | ||
55ea94da FH |
2989 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
2990 | describes which bits in LR that define which stack was used prior | |
2991 | to the exception and if FPU is used (causing extended stack frame). */ | |
2992 | ||
2993 | lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2994 | sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
2995 | ||
2996 | /* Check EXC_RETURN indicator bits. */ | |
2997 | exc_return = (((lr >> 28) & 0xf) == 0xf); | |
2998 | ||
2999 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ | |
3000 | process_stack_used = ((lr & (1 << 2)) != 0); | |
3001 | if (exc_return && process_stack_used) | |
3002 | { | |
3003 | /* Thread (process) stack used. | |
dda83cd7 SM |
3004 | Potentially this could be other register defined by target, but PSP |
3005 | can be considered a standard name for the "Process Stack Pointer". | |
3006 | To be fully aware of system registers like MSP and PSP, these could | |
3007 | be added to a separate XML arm-m-system-profile that is valid for | |
3008 | ARMv6-M and ARMv7-M architectures. Also to be able to debug eg a | |
3009 | corefile off-line, then these registers must be defined by GDB, | |
3010 | and also be included in the corefile regsets. */ | |
55ea94da FH |
3011 | |
3012 | int psp_regnum = user_reg_map_name_to_regnum (gdbarch, "psp", -1); | |
3013 | if (psp_regnum == -1) | |
dda83cd7 SM |
3014 | { |
3015 | /* Thread (process) stack could not be fetched, | |
3016 | give warning and exit. */ | |
55ea94da | 3017 | |
dda83cd7 | 3018 | warning (_("no PSP thread stack unwinding supported.")); |
55ea94da | 3019 | |
dda83cd7 SM |
3020 | /* Terminate any further stack unwinding by refer to self. */ |
3021 | cache->prev_sp = sp; | |
3022 | return cache; | |
3023 | } | |
55ea94da | 3024 | else |
dda83cd7 SM |
3025 | { |
3026 | /* Thread (process) stack used, use PSP as SP. */ | |
3027 | unwound_sp = get_frame_register_unsigned (this_frame, psp_regnum); | |
3028 | } | |
55ea94da FH |
3029 | } |
3030 | else | |
3031 | { | |
3032 | /* Main stack used, use MSP as SP. */ | |
3033 | unwound_sp = sp; | |
3034 | } | |
2ae28aa9 YQ |
3035 | |
3036 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3037 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3038 | "B1.5.6 Exception entry behavior" in | |
3039 | "ARMv7-M Architecture Reference Manual". */ | |
3040 | cache->saved_regs[0].addr = unwound_sp; | |
3041 | cache->saved_regs[1].addr = unwound_sp + 4; | |
3042 | cache->saved_regs[2].addr = unwound_sp + 8; | |
3043 | cache->saved_regs[3].addr = unwound_sp + 12; | |
55ea94da FH |
3044 | cache->saved_regs[ARM_IP_REGNUM].addr = unwound_sp + 16; |
3045 | cache->saved_regs[ARM_LR_REGNUM].addr = unwound_sp + 20; | |
3046 | cache->saved_regs[ARM_PC_REGNUM].addr = unwound_sp + 24; | |
2ae28aa9 YQ |
3047 | cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28; |
3048 | ||
55ea94da FH |
3049 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) |
3050 | type used. */ | |
3051 | extended_frame_used = ((lr & (1 << 4)) == 0); | |
3052 | if (exc_return && extended_frame_used) | |
3053 | { | |
3054 | int i; | |
3055 | int fpu_regs_stack_offset; | |
3056 | ||
3057 | /* This code does not take into account the lazy stacking, see "Lazy | |
dda83cd7 SM |
3058 | context save of FP state", in B1.5.7, also ARM AN298, supported |
3059 | by Cortex-M4F architecture. | |
3060 | To fully handle this the FPCCR register (Floating-point Context | |
3061 | Control Register) needs to be read out and the bits ASPEN and LSPEN | |
3062 | could be checked to setup correct lazy stacked FP registers. | |
3063 | This register is located at address 0xE000EF34. */ | |
55ea94da FH |
3064 | |
3065 | /* Extended stack frame type used. */ | |
3066 | fpu_regs_stack_offset = unwound_sp + 0x20; | |
3067 | for (i = 0; i < 16; i++) | |
dda83cd7 SM |
3068 | { |
3069 | cache->saved_regs[ARM_D0_REGNUM + i].addr = fpu_regs_stack_offset; | |
3070 | fpu_regs_stack_offset += 4; | |
3071 | } | |
55ea94da FH |
3072 | cache->saved_regs[ARM_FPSCR_REGNUM].addr = unwound_sp + 0x60; |
3073 | ||
3074 | /* Offset 0x64 is reserved. */ | |
3075 | cache->prev_sp = unwound_sp + 0x68; | |
3076 | } | |
3077 | else | |
3078 | { | |
3079 | /* Standard stack frame type used. */ | |
3080 | cache->prev_sp = unwound_sp + 0x20; | |
3081 | } | |
3082 | ||
3083 | /* Check EXC_RETURN bit S if Secure or Non-secure stack used. */ | |
3084 | secure_stack_used = ((lr & (1 << 6)) != 0); | |
3085 | if (exc_return && secure_stack_used) | |
3086 | { | |
3087 | /* ARMv8-M Exception and interrupt handling is not considered here. | |
3088 | In the ARMv8-M architecture also EXC_RETURN bit S is controlling if | |
3089 | the Secure or Non-secure stack was used. To separate Secure and | |
3090 | Non-secure stacks, processors that are based on the ARMv8-M | |
3091 | architecture support 4 stack pointers: MSP_S, PSP_S, MSP_NS, PSP_NS. | |
3092 | In addition, a stack limit feature is provided using stack limit | |
3093 | registers (accessible using MSR and MRS instructions) in Privileged | |
3094 | level. */ | |
3095 | } | |
3096 | ||
2ae28aa9 YQ |
3097 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3098 | aligner between the top of the 32-byte stack frame and the | |
3099 | previous context's stack pointer. */ | |
2ae28aa9 YQ |
3100 | if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) |
3101 | && (xpsr & (1 << 9)) != 0) | |
3102 | cache->prev_sp += 4; | |
3103 | ||
3104 | return cache; | |
3105 | } | |
3106 | ||
3107 | /* Implementation of function hook 'this_id' in | |
3108 | 'struct frame_uwnind'. */ | |
3109 | ||
3110 | static void | |
3111 | arm_m_exception_this_id (struct frame_info *this_frame, | |
3112 | void **this_cache, | |
3113 | struct frame_id *this_id) | |
3114 | { | |
3115 | struct arm_prologue_cache *cache; | |
3116 | ||
3117 | if (*this_cache == NULL) | |
3118 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3119 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3120 | |
3121 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3122 | *this_id = frame_id_build (cache->prev_sp, | |
3123 | get_frame_pc (this_frame)); | |
3124 | } | |
3125 | ||
3126 | /* Implementation of function hook 'prev_register' in | |
3127 | 'struct frame_uwnind'. */ | |
3128 | ||
3129 | static struct value * | |
3130 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
3131 | void **this_cache, | |
3132 | int prev_regnum) | |
3133 | { | |
2ae28aa9 YQ |
3134 | struct arm_prologue_cache *cache; |
3135 | ||
3136 | if (*this_cache == NULL) | |
3137 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3138 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3139 | |
3140 | /* The value was already reconstructed into PREV_SP. */ | |
3141 | if (prev_regnum == ARM_SP_REGNUM) | |
3142 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3143 | cache->prev_sp); | |
3144 | ||
3145 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3146 | prev_regnum); | |
3147 | } | |
3148 | ||
3149 | /* Implementation of function hook 'sniffer' in | |
3150 | 'struct frame_uwnind'. */ | |
3151 | ||
3152 | static int | |
3153 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
3154 | struct frame_info *this_frame, | |
3155 | void **this_prologue_cache) | |
3156 | { | |
3157 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
3158 | ||
3159 | /* No need to check is_m; this sniffer is only registered for | |
3160 | M-profile architectures. */ | |
3161 | ||
ca90e760 FH |
3162 | /* Check if exception frame returns to a magic PC value. */ |
3163 | return arm_m_addr_is_magic (this_pc); | |
2ae28aa9 YQ |
3164 | } |
3165 | ||
3166 | /* Frame unwinder for M-profile exceptions. */ | |
3167 | ||
3168 | struct frame_unwind arm_m_exception_unwind = | |
3169 | { | |
3170 | SIGTRAMP_FRAME, | |
3171 | default_frame_unwind_stop_reason, | |
3172 | arm_m_exception_this_id, | |
3173 | arm_m_exception_prev_register, | |
3174 | NULL, | |
3175 | arm_m_exception_unwind_sniffer | |
3176 | }; | |
3177 | ||
24de872b | 3178 | static CORE_ADDR |
a262aec2 | 3179 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
3180 | { |
3181 | struct arm_prologue_cache *cache; | |
3182 | ||
eb5492fa | 3183 | if (*this_cache == NULL) |
a262aec2 | 3184 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3185 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3186 | |
4be43953 | 3187 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
3188 | } |
3189 | ||
eb5492fa DJ |
3190 | struct frame_base arm_normal_base = { |
3191 | &arm_prologue_unwind, | |
3192 | arm_normal_frame_base, | |
3193 | arm_normal_frame_base, | |
3194 | arm_normal_frame_base | |
3195 | }; | |
3196 | ||
b39cc962 DJ |
3197 | static struct value * |
3198 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
3199 | int regnum) | |
3200 | { | |
24568a2c | 3201 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 | 3202 | CORE_ADDR lr, cpsr; |
9779414d | 3203 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
3204 | |
3205 | switch (regnum) | |
3206 | { | |
3207 | case ARM_PC_REGNUM: | |
3208 | /* The PC is normally copied from the return column, which | |
3209 | describes saves of LR. However, that version may have an | |
3210 | extra bit set to indicate Thumb state. The bit is not | |
3211 | part of the PC. */ | |
3212 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
3213 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3214 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
3215 | |
3216 | case ARM_PS_REGNUM: | |
3217 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 3218 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
3219 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3220 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 3221 | cpsr |= t_bit; |
b39cc962 | 3222 | else |
9779414d | 3223 | cpsr &= ~t_bit; |
ca38c58e | 3224 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3225 | |
3226 | default: | |
3227 | internal_error (__FILE__, __LINE__, | |
3228 | _("Unexpected register %d"), regnum); | |
3229 | } | |
3230 | } | |
3231 | ||
3232 | static void | |
3233 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3234 | struct dwarf2_frame_state_reg *reg, | |
3235 | struct frame_info *this_frame) | |
3236 | { | |
3237 | switch (regnum) | |
3238 | { | |
3239 | case ARM_PC_REGNUM: | |
3240 | case ARM_PS_REGNUM: | |
3241 | reg->how = DWARF2_FRAME_REG_FN; | |
3242 | reg->loc.fn = arm_dwarf2_prev_register; | |
3243 | break; | |
3244 | case ARM_SP_REGNUM: | |
3245 | reg->how = DWARF2_FRAME_REG_CFA; | |
3246 | break; | |
3247 | } | |
3248 | } | |
3249 | ||
c9cf6e20 | 3250 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3251 | |
3252 | static int | |
c9cf6e20 | 3253 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3254 | { |
3255 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3256 | unsigned int insn, insn2; | |
3257 | int found_return = 0, found_stack_adjust = 0; | |
3258 | CORE_ADDR func_start, func_end; | |
3259 | CORE_ADDR scan_pc; | |
3260 | gdb_byte buf[4]; | |
3261 | ||
3262 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3263 | return 0; | |
3264 | ||
3265 | /* The epilogue is a sequence of instructions along the following lines: | |
3266 | ||
3267 | - add stack frame size to SP or FP | |
3268 | - [if frame pointer used] restore SP from FP | |
3269 | - restore registers from SP [may include PC] | |
3270 | - a return-type instruction [if PC wasn't already restored] | |
3271 | ||
3272 | In a first pass, we scan forward from the current PC and verify the | |
3273 | instructions we find as compatible with this sequence, ending in a | |
3274 | return instruction. | |
3275 | ||
3276 | However, this is not sufficient to distinguish indirect function calls | |
3277 | within a function from indirect tail calls in the epilogue in some cases. | |
3278 | Therefore, if we didn't already find any SP-changing instruction during | |
3279 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3280 | are in the epilogue. */ | |
3281 | ||
3282 | scan_pc = pc; | |
3283 | while (scan_pc < func_end && !found_return) | |
3284 | { | |
3285 | if (target_read_memory (scan_pc, buf, 2)) | |
3286 | break; | |
3287 | ||
3288 | scan_pc += 2; | |
3289 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3290 | ||
3291 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3292 | found_return = 1; | |
3293 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3294 | found_return = 1; | |
540314bd | 3295 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3296 | { |
b7576e5c | 3297 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3298 | found_return = 1; |
3299 | } | |
db24da6d | 3300 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3301 | { |
3302 | if (target_read_memory (scan_pc, buf, 2)) | |
3303 | break; | |
3304 | ||
3305 | scan_pc += 2; | |
3306 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3307 | ||
3308 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3309 | { | |
4024ca99 UW |
3310 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3311 | found_return = 1; | |
3312 | } | |
3313 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3314 | && (insn2 & 0x0fff) == 0x0b04) | |
3315 | { | |
4024ca99 UW |
3316 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3317 | found_return = 1; | |
3318 | } | |
3319 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3320 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3321 | ; |
4024ca99 UW |
3322 | else |
3323 | break; | |
3324 | } | |
3325 | else | |
3326 | break; | |
3327 | } | |
3328 | ||
3329 | if (!found_return) | |
3330 | return 0; | |
3331 | ||
3332 | /* Since any instruction in the epilogue sequence, with the possible | |
3333 | exception of return itself, updates the stack pointer, we need to | |
3334 | scan backwards for at most one instruction. Try either a 16-bit or | |
3335 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3336 | too much about false positives. */ |
4024ca99 | 3337 | |
6b65d1b6 YQ |
3338 | if (pc - 4 < func_start) |
3339 | return 0; | |
3340 | if (target_read_memory (pc - 4, buf, 4)) | |
3341 | return 0; | |
4024ca99 | 3342 | |
6b65d1b6 YQ |
3343 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3344 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3345 | ||
3346 | if (thumb_instruction_restores_sp (insn2)) | |
3347 | found_stack_adjust = 1; | |
3348 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3349 | found_stack_adjust = 1; | |
3350 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3351 | && (insn2 & 0x0fff) == 0x0b04) | |
3352 | found_stack_adjust = 1; | |
3353 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3354 | && (insn2 & 0x0e00) == 0x0a00) | |
3355 | found_stack_adjust = 1; | |
4024ca99 UW |
3356 | |
3357 | return found_stack_adjust; | |
3358 | } | |
3359 | ||
4024ca99 | 3360 | static int |
c58b006a | 3361 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3362 | { |
3363 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3364 | unsigned int insn; | |
f303bc3e | 3365 | int found_return; |
4024ca99 UW |
3366 | CORE_ADDR func_start, func_end; |
3367 | ||
4024ca99 UW |
3368 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
3369 | return 0; | |
3370 | ||
3371 | /* We are in the epilogue if the previous instruction was a stack | |
3372 | adjustment and the next instruction is a possible return (bx, mov | |
3373 | pc, or pop). We could have to scan backwards to find the stack | |
3374 | adjustment, or forwards to find the return, but this is a decent | |
3375 | approximation. First scan forwards. */ | |
3376 | ||
3377 | found_return = 0; | |
3378 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3379 | if (bits (insn, 28, 31) != INST_NV) | |
3380 | { | |
3381 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3382 | /* BX. */ | |
3383 | found_return = 1; | |
3384 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3385 | /* MOV PC. */ | |
3386 | found_return = 1; | |
3387 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3388 | && (insn & 0x0000c000) != 0) | |
3389 | /* POP (LDMIA), including PC or LR. */ | |
3390 | found_return = 1; | |
3391 | } | |
3392 | ||
3393 | if (!found_return) | |
3394 | return 0; | |
3395 | ||
3396 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3397 | false positives from mode changes. */ | |
3398 | ||
3399 | if (pc < func_start + 4) | |
3400 | return 0; | |
3401 | ||
3402 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3403 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3404 | return 1; |
3405 | ||
3406 | return 0; | |
3407 | } | |
3408 | ||
c58b006a YQ |
3409 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3410 | ||
3411 | static int | |
3412 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3413 | { | |
3414 | if (arm_pc_is_thumb (gdbarch, pc)) | |
3415 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3416 | else | |
3417 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3418 | } | |
4024ca99 | 3419 | |
2dd604e7 RE |
3420 | /* When arguments must be pushed onto the stack, they go on in reverse |
3421 | order. The code below implements a FILO (stack) to do this. */ | |
3422 | ||
3423 | struct stack_item | |
3424 | { | |
3425 | int len; | |
3426 | struct stack_item *prev; | |
7c543f7b | 3427 | gdb_byte *data; |
2dd604e7 RE |
3428 | }; |
3429 | ||
3430 | static struct stack_item * | |
df3b6708 | 3431 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2dd604e7 RE |
3432 | { |
3433 | struct stack_item *si; | |
8d749320 | 3434 | si = XNEW (struct stack_item); |
7c543f7b | 3435 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
3436 | si->len = len; |
3437 | si->prev = prev; | |
3438 | memcpy (si->data, contents, len); | |
3439 | return si; | |
3440 | } | |
3441 | ||
3442 | static struct stack_item * | |
3443 | pop_stack_item (struct stack_item *si) | |
3444 | { | |
3445 | struct stack_item *dead = si; | |
3446 | si = si->prev; | |
3447 | xfree (dead->data); | |
3448 | xfree (dead); | |
3449 | return si; | |
3450 | } | |
3451 | ||
030197b4 AB |
3452 | /* Implement the gdbarch type alignment method, overrides the generic |
3453 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 3454 | |
030197b4 AB |
3455 | static ULONGEST |
3456 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 3457 | { |
2af48f68 | 3458 | t = check_typedef (t); |
bd63c870 | 3459 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 3460 | { |
030197b4 AB |
3461 | /* Use the natural alignment for vector types (the same for |
3462 | scalar type), but the maximum alignment is 64-bit. */ | |
3463 | if (TYPE_LENGTH (t) > 8) | |
3464 | return 8; | |
c4312b19 | 3465 | else |
030197b4 | 3466 | return TYPE_LENGTH (t); |
2af48f68 | 3467 | } |
030197b4 AB |
3468 | |
3469 | /* Allow the common code to calculate the alignment. */ | |
3470 | return 0; | |
2af48f68 PB |
3471 | } |
3472 | ||
90445bd3 DJ |
3473 | /* Possible base types for a candidate for passing and returning in |
3474 | VFP registers. */ | |
3475 | ||
3476 | enum arm_vfp_cprc_base_type | |
3477 | { | |
3478 | VFP_CPRC_UNKNOWN, | |
3479 | VFP_CPRC_SINGLE, | |
3480 | VFP_CPRC_DOUBLE, | |
3481 | VFP_CPRC_VEC64, | |
3482 | VFP_CPRC_VEC128 | |
3483 | }; | |
3484 | ||
3485 | /* The length of one element of base type B. */ | |
3486 | ||
3487 | static unsigned | |
3488 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
3489 | { | |
3490 | switch (b) | |
3491 | { | |
3492 | case VFP_CPRC_SINGLE: | |
3493 | return 4; | |
3494 | case VFP_CPRC_DOUBLE: | |
3495 | return 8; | |
3496 | case VFP_CPRC_VEC64: | |
3497 | return 8; | |
3498 | case VFP_CPRC_VEC128: | |
3499 | return 16; | |
3500 | default: | |
3501 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3502 | (int) b); | |
3503 | } | |
3504 | } | |
3505 | ||
3506 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
3507 | for passing base type B. */ | |
3508 | ||
3509 | static int | |
3510 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
3511 | { | |
3512 | switch (b) | |
3513 | { | |
3514 | case VFP_CPRC_SINGLE: | |
3515 | return 's'; | |
3516 | case VFP_CPRC_DOUBLE: | |
3517 | return 'd'; | |
3518 | case VFP_CPRC_VEC64: | |
3519 | return 'd'; | |
3520 | case VFP_CPRC_VEC128: | |
3521 | return 'q'; | |
3522 | default: | |
3523 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3524 | (int) b); | |
3525 | } | |
3526 | } | |
3527 | ||
3528 | /* Determine whether T may be part of a candidate for passing and | |
3529 | returning in VFP registers, ignoring the limit on the total number | |
3530 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
3531 | classification of the first valid component found; if it is not | |
3532 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
3533 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
3534 | for passing and returning in VFP registers, a type differently | |
3535 | classified from *BASE_TYPE, or two types differently classified | |
3536 | from each other, return -1, otherwise return the total number of | |
3537 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
3538 | array). Vector types are not currently supported, matching the |
3539 | generic AAPCS support. */ | |
90445bd3 DJ |
3540 | |
3541 | static int | |
3542 | arm_vfp_cprc_sub_candidate (struct type *t, | |
3543 | enum arm_vfp_cprc_base_type *base_type) | |
3544 | { | |
3545 | t = check_typedef (t); | |
78134374 | 3546 | switch (t->code ()) |
90445bd3 DJ |
3547 | { |
3548 | case TYPE_CODE_FLT: | |
3549 | switch (TYPE_LENGTH (t)) | |
3550 | { | |
3551 | case 4: | |
3552 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3553 | *base_type = VFP_CPRC_SINGLE; | |
3554 | else if (*base_type != VFP_CPRC_SINGLE) | |
3555 | return -1; | |
3556 | return 1; | |
3557 | ||
3558 | case 8: | |
3559 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3560 | *base_type = VFP_CPRC_DOUBLE; | |
3561 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3562 | return -1; | |
3563 | return 1; | |
3564 | ||
3565 | default: | |
3566 | return -1; | |
3567 | } | |
3568 | break; | |
3569 | ||
817e0957 YQ |
3570 | case TYPE_CODE_COMPLEX: |
3571 | /* Arguments of complex T where T is one of the types float or | |
3572 | double get treated as if they are implemented as: | |
3573 | ||
3574 | struct complexT | |
3575 | { | |
3576 | T real; | |
3577 | T imag; | |
5f52445b YQ |
3578 | }; |
3579 | ||
3580 | */ | |
817e0957 YQ |
3581 | switch (TYPE_LENGTH (t)) |
3582 | { | |
3583 | case 8: | |
3584 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3585 | *base_type = VFP_CPRC_SINGLE; | |
3586 | else if (*base_type != VFP_CPRC_SINGLE) | |
3587 | return -1; | |
3588 | return 2; | |
3589 | ||
3590 | case 16: | |
3591 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3592 | *base_type = VFP_CPRC_DOUBLE; | |
3593 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3594 | return -1; | |
3595 | return 2; | |
3596 | ||
3597 | default: | |
3598 | return -1; | |
3599 | } | |
3600 | break; | |
3601 | ||
90445bd3 DJ |
3602 | case TYPE_CODE_ARRAY: |
3603 | { | |
bd63c870 | 3604 | if (t->is_vector ()) |
90445bd3 | 3605 | { |
c4312b19 YQ |
3606 | /* A 64-bit or 128-bit containerized vector type are VFP |
3607 | CPRCs. */ | |
3608 | switch (TYPE_LENGTH (t)) | |
3609 | { | |
3610 | case 8: | |
3611 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3612 | *base_type = VFP_CPRC_VEC64; | |
3613 | return 1; | |
3614 | case 16: | |
3615 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3616 | *base_type = VFP_CPRC_VEC128; | |
3617 | return 1; | |
3618 | default: | |
3619 | return -1; | |
3620 | } | |
3621 | } | |
3622 | else | |
3623 | { | |
3624 | int count; | |
3625 | unsigned unitlen; | |
3626 | ||
3627 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), | |
3628 | base_type); | |
3629 | if (count == -1) | |
3630 | return -1; | |
3631 | if (TYPE_LENGTH (t) == 0) | |
3632 | { | |
3633 | gdb_assert (count == 0); | |
3634 | return 0; | |
3635 | } | |
3636 | else if (count == 0) | |
3637 | return -1; | |
3638 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3639 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
3640 | return TYPE_LENGTH (t) / unitlen; | |
90445bd3 | 3641 | } |
90445bd3 DJ |
3642 | } |
3643 | break; | |
3644 | ||
3645 | case TYPE_CODE_STRUCT: | |
3646 | { | |
3647 | int count = 0; | |
3648 | unsigned unitlen; | |
3649 | int i; | |
1f704f76 | 3650 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3651 | { |
1040b979 YQ |
3652 | int sub_count = 0; |
3653 | ||
ceacbf6e | 3654 | if (!field_is_static (&t->field (i))) |
940da03e | 3655 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 3656 | base_type); |
90445bd3 DJ |
3657 | if (sub_count == -1) |
3658 | return -1; | |
3659 | count += sub_count; | |
3660 | } | |
3661 | if (TYPE_LENGTH (t) == 0) | |
3662 | { | |
3663 | gdb_assert (count == 0); | |
3664 | return 0; | |
3665 | } | |
3666 | else if (count == 0) | |
3667 | return -1; | |
3668 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3669 | if (TYPE_LENGTH (t) != unitlen * count) | |
3670 | return -1; | |
3671 | return count; | |
3672 | } | |
3673 | ||
3674 | case TYPE_CODE_UNION: | |
3675 | { | |
3676 | int count = 0; | |
3677 | unsigned unitlen; | |
3678 | int i; | |
1f704f76 | 3679 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3680 | { |
940da03e | 3681 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
3682 | base_type); |
3683 | if (sub_count == -1) | |
3684 | return -1; | |
3685 | count = (count > sub_count ? count : sub_count); | |
3686 | } | |
3687 | if (TYPE_LENGTH (t) == 0) | |
3688 | { | |
3689 | gdb_assert (count == 0); | |
3690 | return 0; | |
3691 | } | |
3692 | else if (count == 0) | |
3693 | return -1; | |
3694 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3695 | if (TYPE_LENGTH (t) != unitlen * count) | |
3696 | return -1; | |
3697 | return count; | |
3698 | } | |
3699 | ||
3700 | default: | |
3701 | break; | |
3702 | } | |
3703 | ||
3704 | return -1; | |
3705 | } | |
3706 | ||
3707 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
3708 | if passed to or returned from a non-variadic function with the VFP | |
3709 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
3710 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
3711 | elements of that base type before returning. */ | |
3712 | ||
3713 | static int | |
3714 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
3715 | int *count) | |
3716 | { | |
3717 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
3718 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
3719 | if (c <= 0 || c > 4) | |
3720 | return 0; | |
3721 | *base_type = b; | |
3722 | *count = c; | |
3723 | return 1; | |
3724 | } | |
3725 | ||
3726 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
3727 | returning values from a function of type FUNC_TYPE, 0 | |
3728 | otherwise. */ | |
3729 | ||
3730 | static int | |
3731 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
3732 | { | |
3733 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3734 | /* Variadic functions always use the base ABI. Assume that functions | |
3735 | without debug info are not variadic. */ | |
a409645d | 3736 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 DJ |
3737 | return 0; |
3738 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
3739 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
3740 | return 0; | |
3741 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
3742 | } | |
3743 | ||
3744 | /* We currently only support passing parameters in integer registers, which | |
3745 | conforms with GCC's default model, and VFP argument passing following | |
3746 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
3747 | we should probably support some of them based on the selected ABI. */ |
3748 | ||
3749 | static CORE_ADDR | |
7d9b040b | 3750 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 3751 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
3752 | struct value **args, CORE_ADDR sp, |
3753 | function_call_return_method return_method, | |
6a65450a | 3754 | CORE_ADDR struct_addr) |
2dd604e7 | 3755 | { |
e17a4113 | 3756 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
3757 | int argnum; |
3758 | int argreg; | |
3759 | int nstack; | |
3760 | struct stack_item *si = NULL; | |
90445bd3 DJ |
3761 | int use_vfp_abi; |
3762 | struct type *ftype; | |
3763 | unsigned vfp_regs_free = (1 << 16) - 1; | |
3764 | ||
3765 | /* Determine the type of this function and whether the VFP ABI | |
3766 | applies. */ | |
3767 | ftype = check_typedef (value_type (function)); | |
78134374 | 3768 | if (ftype->code () == TYPE_CODE_PTR) |
90445bd3 DJ |
3769 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
3770 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 3771 | |
6a65450a AC |
3772 | /* Set the return address. For the ARM, the return breakpoint is |
3773 | always at BP_ADDR. */ | |
9779414d | 3774 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 3775 | bp_addr |= 1; |
6a65450a | 3776 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
3777 | |
3778 | /* Walk through the list of args and determine how large a temporary | |
3779 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 3780 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
3781 | nstack = 0; |
3782 | ||
3783 | argreg = ARM_A1_REGNUM; | |
3784 | nstack = 0; | |
3785 | ||
2dd604e7 RE |
3786 | /* The struct_return pointer occupies the first parameter |
3787 | passing register. */ | |
cf84fa6b | 3788 | if (return_method == return_method_struct) |
2dd604e7 RE |
3789 | { |
3790 | if (arm_debug) | |
5af949e3 | 3791 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 3792 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 3793 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
3794 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
3795 | argreg++; | |
3796 | } | |
3797 | ||
3798 | for (argnum = 0; argnum < nargs; argnum++) | |
3799 | { | |
3800 | int len; | |
3801 | struct type *arg_type; | |
3802 | struct type *target_type; | |
3803 | enum type_code typecode; | |
8c6363cf | 3804 | const bfd_byte *val; |
2af48f68 | 3805 | int align; |
90445bd3 DJ |
3806 | enum arm_vfp_cprc_base_type vfp_base_type; |
3807 | int vfp_base_count; | |
3808 | int may_use_core_reg = 1; | |
2dd604e7 | 3809 | |
df407dfe | 3810 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
3811 | len = TYPE_LENGTH (arg_type); |
3812 | target_type = TYPE_TARGET_TYPE (arg_type); | |
78134374 | 3813 | typecode = arg_type->code (); |
8c6363cf | 3814 | val = value_contents (args[argnum]); |
2dd604e7 | 3815 | |
030197b4 | 3816 | align = type_align (arg_type); |
2af48f68 | 3817 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
3818 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
3819 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 PB |
3820 | /* Different ABIs have different maximum alignments. */ |
3821 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
3822 | { | |
3823 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 3824 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
3825 | } |
3826 | else | |
3827 | { | |
3828 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
3829 | if (align > ARM_INT_REGISTER_SIZE * 2) |
3830 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
3831 | } |
3832 | ||
90445bd3 DJ |
3833 | if (use_vfp_abi |
3834 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
3835 | &vfp_base_count)) | |
3836 | { | |
3837 | int regno; | |
3838 | int unit_length; | |
3839 | int shift; | |
3840 | unsigned mask; | |
3841 | ||
3842 | /* Because this is a CPRC it cannot go in a core register or | |
3843 | cause a core register to be skipped for alignment. | |
3844 | Either it goes in VFP registers and the rest of this loop | |
3845 | iteration is skipped for this argument, or it goes on the | |
3846 | stack (and the stack alignment code is correct for this | |
3847 | case). */ | |
3848 | may_use_core_reg = 0; | |
3849 | ||
3850 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3851 | shift = unit_length / 4; | |
3852 | mask = (1 << (shift * vfp_base_count)) - 1; | |
3853 | for (regno = 0; regno < 16; regno += shift) | |
3854 | if (((vfp_regs_free >> regno) & mask) == mask) | |
3855 | break; | |
3856 | ||
3857 | if (regno < 16) | |
3858 | { | |
3859 | int reg_char; | |
3860 | int reg_scaled; | |
3861 | int i; | |
3862 | ||
3863 | vfp_regs_free &= ~(mask << regno); | |
3864 | reg_scaled = regno / shift; | |
3865 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3866 | for (i = 0; i < vfp_base_count; i++) | |
3867 | { | |
3868 | char name_buf[4]; | |
3869 | int regnum; | |
58d6951d DJ |
3870 | if (reg_char == 'q') |
3871 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 3872 | val + i * unit_length); |
58d6951d DJ |
3873 | else |
3874 | { | |
8c042590 PM |
3875 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
3876 | reg_char, reg_scaled + i); | |
58d6951d DJ |
3877 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
3878 | strlen (name_buf)); | |
b66f5587 | 3879 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 3880 | } |
90445bd3 DJ |
3881 | } |
3882 | continue; | |
3883 | } | |
3884 | else | |
3885 | { | |
3886 | /* This CPRC could not go in VFP registers, so all VFP | |
3887 | registers are now marked as used. */ | |
3888 | vfp_regs_free = 0; | |
3889 | } | |
3890 | } | |
3891 | ||
85102364 | 3892 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
3893 | if (nstack & (align - 1)) |
3894 | { | |
f0452268 AH |
3895 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
3896 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
3897 | } |
3898 | ||
3899 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
3900 | if (may_use_core_reg |
3901 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 3902 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
3903 | && argreg & 1) |
3904 | argreg++; | |
3905 | ||
2dd604e7 RE |
3906 | /* If the argument is a pointer to a function, and it is a |
3907 | Thumb function, create a LOCAL copy of the value and set | |
3908 | the THUMB bit in it. */ | |
3909 | if (TYPE_CODE_PTR == typecode | |
3910 | && target_type != NULL | |
78134374 | 3911 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 3912 | { |
e17a4113 | 3913 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 3914 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 3915 | { |
224c3ddb | 3916 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 3917 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 3918 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 3919 | val = copy; |
2dd604e7 RE |
3920 | } |
3921 | } | |
3922 | ||
3923 | /* Copy the argument to general registers or the stack in | |
3924 | register-sized pieces. Large arguments are split between | |
3925 | registers and stack. */ | |
3926 | while (len > 0) | |
3927 | { | |
f0452268 AH |
3928 | int partial_len = len < ARM_INT_REGISTER_SIZE |
3929 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
3930 | CORE_ADDR regval |
3931 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 3932 | |
90445bd3 | 3933 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
3934 | { |
3935 | /* The argument is being passed in a general purpose | |
3936 | register. */ | |
e17a4113 | 3937 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 3938 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
3939 | if (arm_debug) |
3940 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
3941 | argnum, |
3942 | gdbarch_register_name | |
2af46ca0 | 3943 | (gdbarch, argreg), |
f0452268 | 3944 | phex (regval, ARM_INT_REGISTER_SIZE)); |
2dd604e7 RE |
3945 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
3946 | argreg++; | |
3947 | } | |
3948 | else | |
3949 | { | |
f0452268 | 3950 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
3951 | |
3952 | memset (buf, 0, sizeof (buf)); | |
3953 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
3954 | ||
2dd604e7 RE |
3955 | /* Push the arguments onto the stack. */ |
3956 | if (arm_debug) | |
3957 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
3958 | argnum, nstack); | |
f0452268 AH |
3959 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
3960 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
3961 | } |
3962 | ||
3963 | len -= partial_len; | |
3964 | val += partial_len; | |
3965 | } | |
3966 | } | |
3967 | /* If we have an odd number of words to push, then decrement the stack | |
3968 | by one word now, so first stack argument will be dword aligned. */ | |
3969 | if (nstack & 4) | |
3970 | sp -= 4; | |
3971 | ||
3972 | while (si) | |
3973 | { | |
3974 | sp -= si->len; | |
3975 | write_memory (sp, si->data, si->len); | |
3976 | si = pop_stack_item (si); | |
3977 | } | |
3978 | ||
3979 | /* Finally, update teh SP register. */ | |
3980 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
3981 | ||
3982 | return sp; | |
3983 | } | |
3984 | ||
f53f0d0b PB |
3985 | |
3986 | /* Always align the frame to an 8-byte boundary. This is required on | |
3987 | some platforms and harmless on the rest. */ | |
3988 | ||
3989 | static CORE_ADDR | |
3990 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
3991 | { | |
3992 | /* Align the stack to eight bytes. */ | |
3993 | return sp & ~ (CORE_ADDR) 7; | |
3994 | } | |
3995 | ||
c906108c | 3996 | static void |
12b27276 | 3997 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 3998 | { |
c5aa993b | 3999 | if (flags & (1 << 0)) |
12b27276 | 4000 | fputs_filtered ("IVO ", file); |
c5aa993b | 4001 | if (flags & (1 << 1)) |
12b27276 | 4002 | fputs_filtered ("DVZ ", file); |
c5aa993b | 4003 | if (flags & (1 << 2)) |
12b27276 | 4004 | fputs_filtered ("OFL ", file); |
c5aa993b | 4005 | if (flags & (1 << 3)) |
12b27276 | 4006 | fputs_filtered ("UFL ", file); |
c5aa993b | 4007 | if (flags & (1 << 4)) |
12b27276 WN |
4008 | fputs_filtered ("INX ", file); |
4009 | fputc_filtered ('\n', file); | |
c906108c SS |
4010 | } |
4011 | ||
5e74b15c RE |
4012 | /* Print interesting information about the floating point processor |
4013 | (if present) or emulator. */ | |
34e8f22d | 4014 | static void |
d855c300 | 4015 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 4016 | struct frame_info *frame, const char *args) |
c906108c | 4017 | { |
9c9acae0 | 4018 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4019 | int type; |
4020 | ||
4021 | type = (status >> 24) & 127; | |
edefbb7c | 4022 | if (status & (1 << 31)) |
12b27276 | 4023 | fprintf_filtered (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4024 | else |
12b27276 | 4025 | fprintf_filtered (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4026 | /* i18n: [floating point unit] mask */ |
12b27276 WN |
4027 | fputs_filtered (_("mask: "), file); |
4028 | print_fpu_flags (file, status >> 16); | |
edefbb7c | 4029 | /* i18n: [floating point unit] flags */ |
12b27276 WN |
4030 | fputs_filtered (_("flags: "), file); |
4031 | print_fpu_flags (file, status); | |
c906108c SS |
4032 | } |
4033 | ||
27067745 UW |
4034 | /* Construct the ARM extended floating point type. */ |
4035 | static struct type * | |
4036 | arm_ext_type (struct gdbarch *gdbarch) | |
4037 | { | |
4038 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4039 | ||
4040 | if (!tdep->arm_ext_type) | |
4041 | tdep->arm_ext_type | |
e9bb382b | 4042 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4043 | floatformats_arm_ext); |
4044 | ||
4045 | return tdep->arm_ext_type; | |
4046 | } | |
4047 | ||
58d6951d DJ |
4048 | static struct type * |
4049 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4050 | { | |
4051 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4052 | ||
4053 | if (tdep->neon_double_type == NULL) | |
4054 | { | |
4055 | struct type *t, *elem; | |
4056 | ||
4057 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4058 | TYPE_CODE_UNION); | |
4059 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4060 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4061 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4062 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4063 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4064 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4065 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4066 | append_composite_type_field (t, "u64", elem); | |
4067 | elem = builtin_type (gdbarch)->builtin_float; | |
4068 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4069 | elem = builtin_type (gdbarch)->builtin_double; | |
4070 | append_composite_type_field (t, "f64", elem); | |
4071 | ||
2062087b | 4072 | t->set_is_vector (true); |
d0e39ea2 | 4073 | t->set_name ("neon_d"); |
58d6951d DJ |
4074 | tdep->neon_double_type = t; |
4075 | } | |
4076 | ||
4077 | return tdep->neon_double_type; | |
4078 | } | |
4079 | ||
4080 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4081 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4082 | bits of d0 - regardless of what unit size is being held in d0. So | |
4083 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4084 | first float is 4. This code works as-is for little-endian | |
4085 | targets. */ | |
4086 | ||
4087 | static struct type * | |
4088 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4089 | { | |
4090 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4091 | ||
4092 | if (tdep->neon_quad_type == NULL) | |
4093 | { | |
4094 | struct type *t, *elem; | |
4095 | ||
4096 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4097 | TYPE_CODE_UNION); | |
4098 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4099 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4100 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4101 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4102 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4103 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4104 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4105 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4106 | elem = builtin_type (gdbarch)->builtin_float; | |
4107 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4108 | elem = builtin_type (gdbarch)->builtin_double; | |
4109 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4110 | ||
2062087b | 4111 | t->set_is_vector (true); |
d0e39ea2 | 4112 | t->set_name ("neon_q"); |
58d6951d DJ |
4113 | tdep->neon_quad_type = t; |
4114 | } | |
4115 | ||
4116 | return tdep->neon_quad_type; | |
4117 | } | |
4118 | ||
34e8f22d RE |
4119 | /* Return the GDB type object for the "standard" data type of data in |
4120 | register N. */ | |
4121 | ||
4122 | static struct type * | |
7a5ea0d4 | 4123 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4124 | { |
58d6951d DJ |
4125 | int num_regs = gdbarch_num_regs (gdbarch); |
4126 | ||
4127 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
4128 | && regnum >= num_regs && regnum < num_regs + 32) | |
4129 | return builtin_type (gdbarch)->builtin_float; | |
4130 | ||
4131 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
4132 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
4133 | return arm_neon_quad_type (gdbarch); | |
4134 | ||
4135 | /* If the target description has register information, we are only | |
4136 | in this function so that we can override the types of | |
4137 | double-precision registers for NEON. */ | |
4138 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4139 | { | |
4140 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4141 | ||
4142 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 4143 | && t->code () == TYPE_CODE_FLT |
58d6951d DJ |
4144 | && gdbarch_tdep (gdbarch)->have_neon) |
4145 | return arm_neon_double_type (gdbarch); | |
4146 | else | |
4147 | return t; | |
4148 | } | |
4149 | ||
34e8f22d | 4150 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
4151 | { |
4152 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
4153 | return builtin_type (gdbarch)->builtin_void; | |
4154 | ||
4155 | return arm_ext_type (gdbarch); | |
4156 | } | |
e4c16157 | 4157 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4158 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4159 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4160 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4161 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4162 | /* These registers are only supported on targets which supply | |
4163 | an XML description. */ | |
df4df182 | 4164 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4165 | else |
df4df182 | 4166 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4167 | } |
4168 | ||
ff6f572f DJ |
4169 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4170 | number. */ | |
4171 | ||
4172 | static int | |
d3f73121 | 4173 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4174 | { |
4175 | /* Core integer regs. */ | |
4176 | if (reg >= 0 && reg <= 15) | |
4177 | return reg; | |
4178 | ||
4179 | /* Legacy FPA encoding. These were once used in a way which | |
4180 | overlapped with VFP register numbering, so their use is | |
4181 | discouraged, but GDB doesn't support the ARM toolchain | |
4182 | which used them for VFP. */ | |
4183 | if (reg >= 16 && reg <= 23) | |
4184 | return ARM_F0_REGNUM + reg - 16; | |
4185 | ||
4186 | /* New assignments for the FPA registers. */ | |
4187 | if (reg >= 96 && reg <= 103) | |
4188 | return ARM_F0_REGNUM + reg - 96; | |
4189 | ||
4190 | /* WMMX register assignments. */ | |
4191 | if (reg >= 104 && reg <= 111) | |
4192 | return ARM_WCGR0_REGNUM + reg - 104; | |
4193 | ||
4194 | if (reg >= 112 && reg <= 127) | |
4195 | return ARM_WR0_REGNUM + reg - 112; | |
4196 | ||
4197 | if (reg >= 192 && reg <= 199) | |
4198 | return ARM_WC0_REGNUM + reg - 192; | |
4199 | ||
58d6951d DJ |
4200 | /* VFP v2 registers. A double precision value is actually |
4201 | in d1 rather than s2, but the ABI only defines numbering | |
4202 | for the single precision registers. This will "just work" | |
4203 | in GDB for little endian targets (we'll read eight bytes, | |
4204 | starting in s0 and then progressing to s1), but will be | |
4205 | reversed on big endian targets with VFP. This won't | |
4206 | be a problem for the new Neon quad registers; you're supposed | |
4207 | to use DW_OP_piece for those. */ | |
4208 | if (reg >= 64 && reg <= 95) | |
4209 | { | |
4210 | char name_buf[4]; | |
4211 | ||
8c042590 | 4212 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4213 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4214 | strlen (name_buf)); | |
4215 | } | |
4216 | ||
4217 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4218 | registers, except that it now describes d0 instead of s0. */ | |
4219 | if (reg >= 256 && reg <= 287) | |
4220 | { | |
4221 | char name_buf[4]; | |
4222 | ||
8c042590 | 4223 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4224 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4225 | strlen (name_buf)); | |
4226 | } | |
4227 | ||
ff6f572f DJ |
4228 | return -1; |
4229 | } | |
4230 | ||
26216b98 AC |
4231 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4232 | static int | |
e7faf938 | 4233 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4234 | { |
4235 | int reg = regnum; | |
e7faf938 | 4236 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4237 | |
ff6f572f DJ |
4238 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4239 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4240 | ||
4241 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4242 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4243 | ||
4244 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4245 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4246 | ||
26216b98 AC |
4247 | if (reg < NUM_GREGS) |
4248 | return SIM_ARM_R0_REGNUM + reg; | |
4249 | reg -= NUM_GREGS; | |
4250 | ||
4251 | if (reg < NUM_FREGS) | |
4252 | return SIM_ARM_FP0_REGNUM + reg; | |
4253 | reg -= NUM_FREGS; | |
4254 | ||
4255 | if (reg < NUM_SREGS) | |
4256 | return SIM_ARM_FPS_REGNUM + reg; | |
4257 | reg -= NUM_SREGS; | |
4258 | ||
edefbb7c | 4259 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4260 | } |
34e8f22d | 4261 | |
d9311bfa AT |
4262 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
4263 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
4264 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 4265 | |
d9311bfa AT |
4266 | static gdb_byte * |
4267 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
4268 | int old_len, int new_len) | |
4269 | { | |
4270 | gdb_byte *new_buf; | |
4271 | int bytes_to_read = new_len - old_len; | |
c906108c | 4272 | |
d9311bfa AT |
4273 | new_buf = (gdb_byte *) xmalloc (new_len); |
4274 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
4275 | xfree (buf); | |
198cd59d | 4276 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
4277 | { |
4278 | xfree (new_buf); | |
4279 | return NULL; | |
c906108c | 4280 | } |
d9311bfa | 4281 | return new_buf; |
c906108c SS |
4282 | } |
4283 | ||
d9311bfa AT |
4284 | /* An IT block is at most the 2-byte IT instruction followed by |
4285 | four 4-byte instructions. The furthest back we must search to | |
4286 | find an IT block that affects the current instruction is thus | |
4287 | 2 + 3 * 4 == 14 bytes. */ | |
4288 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 4289 | |
d9311bfa AT |
4290 | /* Use a quick scan if there are more than this many bytes of |
4291 | code. */ | |
4292 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 4293 | |
d9311bfa AT |
4294 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
4295 | A breakpoint in an IT block may not be hit, depending on the | |
4296 | condition flags. */ | |
ad527d2e | 4297 | static CORE_ADDR |
d9311bfa | 4298 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 4299 | { |
d9311bfa AT |
4300 | gdb_byte *buf; |
4301 | char map_type; | |
4302 | CORE_ADDR boundary, func_start; | |
4303 | int buf_len; | |
4304 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
4305 | int i, any, last_it, last_it_count; | |
177321bd | 4306 | |
d9311bfa AT |
4307 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
4308 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) | |
4309 | return bpaddr; | |
177321bd | 4310 | |
d9311bfa AT |
4311 | /* ARM mode does not have this problem. */ |
4312 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
4313 | return bpaddr; | |
177321bd | 4314 | |
d9311bfa AT |
4315 | /* We are setting a breakpoint in Thumb code that could potentially |
4316 | contain an IT block. The first step is to find how much Thumb | |
4317 | code there is; we do not need to read outside of known Thumb | |
4318 | sequences. */ | |
4319 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
4320 | if (map_type == 0) | |
4321 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
4322 | return bpaddr; | |
9dca5578 | 4323 | |
d9311bfa | 4324 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 4325 | |
d9311bfa AT |
4326 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
4327 | && func_start > boundary) | |
4328 | boundary = func_start; | |
9dca5578 | 4329 | |
d9311bfa AT |
4330 | /* Search for a candidate IT instruction. We have to do some fancy |
4331 | footwork to distinguish a real IT instruction from the second | |
4332 | half of a 32-bit instruction, but there is no need for that if | |
4333 | there's no candidate. */ | |
325fac50 | 4334 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
4335 | if (buf_len == 0) |
4336 | /* No room for an IT instruction. */ | |
4337 | return bpaddr; | |
c906108c | 4338 | |
d9311bfa | 4339 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 4340 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
4341 | return bpaddr; |
4342 | any = 0; | |
4343 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 4344 | { |
d9311bfa AT |
4345 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
4346 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 4347 | { |
d9311bfa AT |
4348 | any = 1; |
4349 | break; | |
25b41d01 | 4350 | } |
c906108c | 4351 | } |
d9311bfa AT |
4352 | |
4353 | if (any == 0) | |
c906108c | 4354 | { |
d9311bfa AT |
4355 | xfree (buf); |
4356 | return bpaddr; | |
f9d67f43 DJ |
4357 | } |
4358 | ||
4359 | /* OK, the code bytes before this instruction contain at least one | |
4360 | halfword which resembles an IT instruction. We know that it's | |
4361 | Thumb code, but there are still two possibilities. Either the | |
4362 | halfword really is an IT instruction, or it is the second half of | |
4363 | a 32-bit Thumb instruction. The only way we can tell is to | |
4364 | scan forwards from a known instruction boundary. */ | |
4365 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
4366 | { | |
4367 | int definite; | |
4368 | ||
4369 | /* There's a lot of code before this instruction. Start with an | |
4370 | optimistic search; it's easy to recognize halfwords that can | |
4371 | not be the start of a 32-bit instruction, and use that to | |
4372 | lock on to the instruction boundaries. */ | |
4373 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
4374 | if (buf == NULL) | |
4375 | return bpaddr; | |
4376 | buf_len = IT_SCAN_THRESHOLD; | |
4377 | ||
4378 | definite = 0; | |
4379 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
4380 | { | |
4381 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4382 | if (thumb_insn_size (inst1) == 2) | |
4383 | { | |
4384 | definite = 1; | |
4385 | break; | |
4386 | } | |
4387 | } | |
4388 | ||
4389 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
4390 | are sure that we know the instruction boundaries, and it is far | |
4391 | enough from BPADDR that we could not miss an IT instruction | |
4392 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
4393 | known boundary. */ | |
4394 | if (! definite) | |
4395 | { | |
0963b4bd MS |
4396 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
4397 | bpaddr - boundary); | |
f9d67f43 DJ |
4398 | if (buf == NULL) |
4399 | return bpaddr; | |
4400 | buf_len = bpaddr - boundary; | |
4401 | i = 0; | |
4402 | } | |
4403 | } | |
4404 | else | |
4405 | { | |
4406 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
4407 | if (buf == NULL) | |
4408 | return bpaddr; | |
4409 | buf_len = bpaddr - boundary; | |
4410 | i = 0; | |
4411 | } | |
4412 | ||
4413 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
4414 | last_it = -1; | |
4415 | last_it_count = 0; | |
4416 | while (i < buf_len) | |
4417 | { | |
4418 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4419 | last_it_count--; | |
4420 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
4421 | { | |
4422 | last_it = i; | |
4423 | if (inst1 & 0x0001) | |
4424 | last_it_count = 4; | |
4425 | else if (inst1 & 0x0002) | |
4426 | last_it_count = 3; | |
4427 | else if (inst1 & 0x0004) | |
4428 | last_it_count = 2; | |
4429 | else | |
4430 | last_it_count = 1; | |
4431 | } | |
4432 | i += thumb_insn_size (inst1); | |
4433 | } | |
4434 | ||
4435 | xfree (buf); | |
4436 | ||
4437 | if (last_it == -1) | |
4438 | /* There wasn't really an IT instruction after all. */ | |
4439 | return bpaddr; | |
4440 | ||
4441 | if (last_it_count < 1) | |
4442 | /* It was too far away. */ | |
4443 | return bpaddr; | |
4444 | ||
4445 | /* This really is a trouble spot. Move the breakpoint to the IT | |
4446 | instruction. */ | |
4447 | return bpaddr - buf_len + last_it; | |
4448 | } | |
4449 | ||
cca44b1b | 4450 | /* ARM displaced stepping support. |
c906108c | 4451 | |
cca44b1b | 4452 | Generally ARM displaced stepping works as follows: |
c906108c | 4453 | |
cca44b1b | 4454 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
4455 | arm_process_displaced_insn. Depending on the type of instruction, it is |
4456 | then copied to a scratch location, possibly in a modified form. The | |
4457 | copy_* set of functions performs such modification, as necessary. A | |
4458 | breakpoint is placed after the modified instruction in the scratch space | |
4459 | to return control to GDB. Note in particular that instructions which | |
4460 | modify the PC will no longer do so after modification. | |
c5aa993b | 4461 | |
cca44b1b JB |
4462 | 2. The instruction is single-stepped, by setting the PC to the scratch |
4463 | location address, and resuming. Control returns to GDB when the | |
4464 | breakpoint is hit. | |
c5aa993b | 4465 | |
cca44b1b JB |
4466 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
4467 | function used for the current instruction. This function's job is to | |
4468 | put the CPU/memory state back to what it would have been if the | |
4469 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 4470 | |
cca44b1b JB |
4471 | /* NOP instruction (mov r0, r0). */ |
4472 | #define ARM_NOP 0xe1a00000 | |
34518530 | 4473 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
4474 | |
4475 | /* Helper for register reads for displaced stepping. In particular, this | |
4476 | returns the PC as it would be seen by the instruction at its original | |
4477 | location. */ | |
4478 | ||
4479 | ULONGEST | |
1152d984 | 4480 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4481 | int regno) |
cca44b1b JB |
4482 | { |
4483 | ULONGEST ret; | |
36073a92 | 4484 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 4485 | |
bf9f652a | 4486 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 4487 | { |
4db71c0b YQ |
4488 | /* Compute pipeline offset: |
4489 | - When executing an ARM instruction, PC reads as the address of the | |
4490 | current instruction plus 8. | |
4491 | - When executing a Thumb instruction, PC reads as the address of the | |
4492 | current instruction plus 4. */ | |
4493 | ||
36073a92 | 4494 | if (!dsc->is_thumb) |
4db71c0b YQ |
4495 | from += 8; |
4496 | else | |
4497 | from += 4; | |
4498 | ||
136821d9 SM |
4499 | displaced_debug_printf ("read pc value %.8lx", |
4500 | (unsigned long) from); | |
4db71c0b | 4501 | return (ULONGEST) from; |
cca44b1b | 4502 | } |
c906108c | 4503 | else |
cca44b1b JB |
4504 | { |
4505 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
4506 | |
4507 | displaced_debug_printf ("read r%d value %.8lx", | |
4508 | regno, (unsigned long) ret); | |
4509 | ||
cca44b1b JB |
4510 | return ret; |
4511 | } | |
c906108c SS |
4512 | } |
4513 | ||
cca44b1b JB |
4514 | static int |
4515 | displaced_in_arm_mode (struct regcache *regs) | |
4516 | { | |
4517 | ULONGEST ps; | |
ac7936df | 4518 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 4519 | |
cca44b1b | 4520 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 4521 | |
9779414d | 4522 | return (ps & t_bit) == 0; |
cca44b1b | 4523 | } |
66e810cd | 4524 | |
cca44b1b | 4525 | /* Write to the PC as from a branch instruction. */ |
c906108c | 4526 | |
cca44b1b | 4527 | static void |
1152d984 | 4528 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4529 | ULONGEST val) |
c906108c | 4530 | { |
36073a92 | 4531 | if (!dsc->is_thumb) |
cca44b1b JB |
4532 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
4533 | architecture versions < 6. */ | |
0963b4bd MS |
4534 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4535 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 4536 | else |
0963b4bd MS |
4537 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4538 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 4539 | } |
66e810cd | 4540 | |
cca44b1b JB |
4541 | /* Write to the PC as from a branch-exchange instruction. */ |
4542 | ||
4543 | static void | |
4544 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
4545 | { | |
4546 | ULONGEST ps; | |
ac7936df | 4547 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
4548 | |
4549 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
4550 | ||
4551 | if ((val & 1) == 1) | |
c906108c | 4552 | { |
9779414d | 4553 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
4554 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
4555 | } | |
4556 | else if ((val & 2) == 0) | |
4557 | { | |
9779414d | 4558 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4559 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
4560 | } |
4561 | else | |
4562 | { | |
cca44b1b JB |
4563 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
4564 | mode, align dest to 4 bytes). */ | |
4565 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 4566 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4567 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
4568 | } |
4569 | } | |
ed9a39eb | 4570 | |
cca44b1b | 4571 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 4572 | |
34e8f22d | 4573 | static void |
1152d984 | 4574 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4575 | ULONGEST val) |
ed9a39eb | 4576 | { |
cca44b1b JB |
4577 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
4578 | bx_write_pc (regs, val); | |
4579 | else | |
36073a92 | 4580 | branch_write_pc (regs, dsc, val); |
cca44b1b | 4581 | } |
be8626e0 | 4582 | |
cca44b1b JB |
4583 | /* Write to the PC as if from an ALU instruction. */ |
4584 | ||
4585 | static void | |
1152d984 | 4586 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4587 | ULONGEST val) |
cca44b1b | 4588 | { |
36073a92 | 4589 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
4590 | bx_write_pc (regs, val); |
4591 | else | |
36073a92 | 4592 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
4593 | } |
4594 | ||
4595 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
4596 | has a varying effects depending on the instruction which does the write: | |
4597 | this is controlled by the WRITE_PC argument. */ | |
4598 | ||
4599 | void | |
1152d984 | 4600 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
4601 | int regno, ULONGEST val, enum pc_write_style write_pc) |
4602 | { | |
bf9f652a | 4603 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 4604 | { |
136821d9 SM |
4605 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
4606 | ||
cca44b1b | 4607 | switch (write_pc) |
08216dd7 | 4608 | { |
cca44b1b | 4609 | case BRANCH_WRITE_PC: |
36073a92 | 4610 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
4611 | break; |
4612 | ||
cca44b1b JB |
4613 | case BX_WRITE_PC: |
4614 | bx_write_pc (regs, val); | |
4615 | break; | |
4616 | ||
4617 | case LOAD_WRITE_PC: | |
36073a92 | 4618 | load_write_pc (regs, dsc, val); |
cca44b1b JB |
4619 | break; |
4620 | ||
4621 | case ALU_WRITE_PC: | |
36073a92 | 4622 | alu_write_pc (regs, dsc, val); |
cca44b1b JB |
4623 | break; |
4624 | ||
4625 | case CANNOT_WRITE_PC: | |
4626 | warning (_("Instruction wrote to PC in an unexpected way when " | |
4627 | "single-stepping")); | |
08216dd7 RE |
4628 | break; |
4629 | ||
4630 | default: | |
97b9747c JB |
4631 | internal_error (__FILE__, __LINE__, |
4632 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 4633 | } |
b508a996 | 4634 | |
cca44b1b | 4635 | dsc->wrote_to_pc = 1; |
b508a996 | 4636 | } |
ed9a39eb | 4637 | else |
b508a996 | 4638 | { |
136821d9 SM |
4639 | displaced_debug_printf ("writing r%d value %.8lx", |
4640 | regno, (unsigned long) val); | |
cca44b1b | 4641 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 4642 | } |
34e8f22d RE |
4643 | } |
4644 | ||
cca44b1b JB |
4645 | /* This function is used to concisely determine if an instruction INSN |
4646 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
4647 | corresponding fields of BITMASK set to 0b1111. The function |
4648 | returns return 1 if any of these fields in INSN reference the PC | |
4649 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
4650 | |
4651 | static int | |
cca44b1b | 4652 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 4653 | { |
cca44b1b | 4654 | uint32_t lowbit = 1; |
67255d04 | 4655 | |
cca44b1b JB |
4656 | while (bitmask != 0) |
4657 | { | |
4658 | uint32_t mask; | |
44e1a9eb | 4659 | |
cca44b1b JB |
4660 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
4661 | ; | |
67255d04 | 4662 | |
cca44b1b JB |
4663 | if (!lowbit) |
4664 | break; | |
67255d04 | 4665 | |
cca44b1b | 4666 | mask = lowbit * 0xf; |
67255d04 | 4667 | |
cca44b1b JB |
4668 | if ((insn & mask) == mask) |
4669 | return 1; | |
4670 | ||
4671 | bitmask &= ~mask; | |
67255d04 RE |
4672 | } |
4673 | ||
cca44b1b JB |
4674 | return 0; |
4675 | } | |
2af48f68 | 4676 | |
cca44b1b JB |
4677 | /* The simplest copy function. Many instructions have the same effect no |
4678 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 4679 | |
cca44b1b | 4680 | static int |
1152d984 SM |
4681 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
4682 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 4683 | { |
136821d9 SM |
4684 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
4685 | (unsigned long) insn, iname); | |
67255d04 | 4686 | |
cca44b1b | 4687 | dsc->modinsn[0] = insn; |
67255d04 | 4688 | |
cca44b1b JB |
4689 | return 0; |
4690 | } | |
4691 | ||
34518530 YQ |
4692 | static int |
4693 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
4694 | uint16_t insn2, const char *iname, | |
1152d984 | 4695 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4696 | { |
136821d9 SM |
4697 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
4698 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
4699 | |
4700 | dsc->modinsn[0] = insn1; | |
4701 | dsc->modinsn[1] = insn2; | |
4702 | dsc->numinsns = 2; | |
4703 | ||
4704 | return 0; | |
4705 | } | |
4706 | ||
4707 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
4708 | modification. */ | |
4709 | static int | |
615234c1 | 4710 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 4711 | const char *iname, |
1152d984 | 4712 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4713 | { |
136821d9 SM |
4714 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
4715 | insn, iname); | |
34518530 YQ |
4716 | |
4717 | dsc->modinsn[0] = insn; | |
4718 | ||
4719 | return 0; | |
4720 | } | |
4721 | ||
cca44b1b JB |
4722 | /* Preload instructions with immediate offset. */ |
4723 | ||
4724 | static void | |
1152d984 SM |
4725 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
4726 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
4727 | { |
4728 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4729 | if (!dsc->u.preload.immed) | |
4730 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
4731 | } | |
4732 | ||
7ff120b4 YQ |
4733 | static void |
4734 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4735 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 4736 | { |
cca44b1b | 4737 | ULONGEST rn_val; |
cca44b1b JB |
4738 | /* Preload instructions: |
4739 | ||
4740 | {pli/pld} [rn, #+/-imm] | |
4741 | -> | |
4742 | {pli/pld} [r0, #+/-imm]. */ | |
4743 | ||
36073a92 YQ |
4744 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4745 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 4746 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
4747 | dsc->u.preload.immed = 1; |
4748 | ||
cca44b1b | 4749 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
4750 | } |
4751 | ||
cca44b1b | 4752 | static int |
7ff120b4 | 4753 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 4754 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
4755 | { |
4756 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 4757 | |
7ff120b4 YQ |
4758 | if (!insn_references_pc (insn, 0x000f0000ul)) |
4759 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 4760 | |
136821d9 | 4761 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 4762 | |
7ff120b4 YQ |
4763 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4764 | ||
4765 | install_preload (gdbarch, regs, dsc, rn); | |
4766 | ||
4767 | return 0; | |
4768 | } | |
4769 | ||
34518530 YQ |
4770 | static int |
4771 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 4772 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
4773 | { |
4774 | unsigned int rn = bits (insn1, 0, 3); | |
4775 | unsigned int u_bit = bit (insn1, 7); | |
4776 | int imm12 = bits (insn2, 0, 11); | |
4777 | ULONGEST pc_val; | |
4778 | ||
4779 | if (rn != ARM_PC_REGNUM) | |
4780 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
4781 | ||
4782 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
4783 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
4784 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
4785 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
4786 | imm12); | |
34518530 YQ |
4787 | |
4788 | if (!u_bit) | |
4789 | imm12 = -1 * imm12; | |
4790 | ||
4791 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
4792 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
4793 | ||
4794 | {pli/pld} [r0, r1] | |
4795 | ||
4796 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
4797 | ||
4798 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
4799 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4800 | ||
4801 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
4802 | ||
4803 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
4804 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
4805 | dsc->u.preload.immed = 0; | |
4806 | ||
4807 | /* {pli/pld} [r0, r1] */ | |
4808 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4809 | dsc->modinsn[1] = 0xf001; | |
4810 | dsc->numinsns = 2; | |
4811 | ||
4812 | dsc->cleanup = &cleanup_preload; | |
4813 | return 0; | |
4814 | } | |
4815 | ||
7ff120b4 YQ |
4816 | /* Preload instructions with register offset. */ |
4817 | ||
4818 | static void | |
4819 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4820 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
4821 | unsigned int rm) |
4822 | { | |
4823 | ULONGEST rn_val, rm_val; | |
4824 | ||
cca44b1b JB |
4825 | /* Preload register-offset instructions: |
4826 | ||
4827 | {pli/pld} [rn, rm {, shift}] | |
4828 | -> | |
4829 | {pli/pld} [r0, r1 {, shift}]. */ | |
4830 | ||
36073a92 YQ |
4831 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4832 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4833 | rn_val = displaced_read_reg (regs, dsc, rn); | |
4834 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
4835 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4836 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
4837 | dsc->u.preload.immed = 0; |
4838 | ||
cca44b1b | 4839 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
4840 | } |
4841 | ||
4842 | static int | |
4843 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
4844 | struct regcache *regs, | |
1152d984 | 4845 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
4846 | { |
4847 | unsigned int rn = bits (insn, 16, 19); | |
4848 | unsigned int rm = bits (insn, 0, 3); | |
4849 | ||
4850 | ||
4851 | if (!insn_references_pc (insn, 0x000f000ful)) | |
4852 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
4853 | ||
136821d9 SM |
4854 | displaced_debug_printf ("copying preload insn %.8lx", |
4855 | (unsigned long) insn); | |
7ff120b4 YQ |
4856 | |
4857 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 4858 | |
7ff120b4 | 4859 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
4860 | return 0; |
4861 | } | |
4862 | ||
4863 | /* Copy/cleanup coprocessor load and store instructions. */ | |
4864 | ||
4865 | static void | |
6e39997a | 4866 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 4867 | struct regcache *regs, |
1152d984 | 4868 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 4869 | { |
36073a92 | 4870 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
4871 | |
4872 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4873 | ||
4874 | if (dsc->u.ldst.writeback) | |
4875 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
4876 | } | |
4877 | ||
7ff120b4 YQ |
4878 | static void |
4879 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4880 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 4881 | int writeback, unsigned int rn) |
cca44b1b | 4882 | { |
cca44b1b | 4883 | ULONGEST rn_val; |
cca44b1b | 4884 | |
cca44b1b JB |
4885 | /* Coprocessor load/store instructions: |
4886 | ||
4887 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
4888 | -> | |
4889 | {stc/stc2} [r0, #+/-imm]. | |
4890 | ||
4891 | ldc/ldc2 are handled identically. */ | |
4892 | ||
36073a92 YQ |
4893 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4894 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
4895 | /* PC should be 4-byte aligned. */ |
4896 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
4897 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4898 | ||
7ff120b4 | 4899 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
4900 | dsc->u.ldst.rn = rn; |
4901 | ||
7ff120b4 YQ |
4902 | dsc->cleanup = &cleanup_copro_load_store; |
4903 | } | |
4904 | ||
4905 | static int | |
4906 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
4907 | struct regcache *regs, | |
1152d984 | 4908 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
4909 | { |
4910 | unsigned int rn = bits (insn, 16, 19); | |
4911 | ||
4912 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
4913 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
4914 | ||
136821d9 SM |
4915 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
4916 | (unsigned long) insn); | |
7ff120b4 | 4917 | |
cca44b1b JB |
4918 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4919 | ||
7ff120b4 | 4920 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
4921 | |
4922 | return 0; | |
4923 | } | |
4924 | ||
34518530 YQ |
4925 | static int |
4926 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
4927 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 4928 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
4929 | { |
4930 | unsigned int rn = bits (insn1, 0, 3); | |
4931 | ||
4932 | if (rn != ARM_PC_REGNUM) | |
4933 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
4934 | "copro load/store", dsc); | |
4935 | ||
136821d9 SM |
4936 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
4937 | insn1, insn2); | |
34518530 YQ |
4938 | |
4939 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4940 | dsc->modinsn[1] = insn2; | |
4941 | dsc->numinsns = 2; | |
4942 | ||
4943 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
4944 | doesn't support writeback, so pass 0. */ | |
4945 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
4946 | ||
4947 | return 0; | |
4948 | } | |
4949 | ||
cca44b1b JB |
4950 | /* Clean up branch instructions (actually perform the branch, by setting |
4951 | PC). */ | |
4952 | ||
4953 | static void | |
6e39997a | 4954 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 4955 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 4956 | { |
36073a92 | 4957 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
4958 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
4959 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
4960 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
4961 | ||
4962 | if (!branch_taken) | |
4963 | return; | |
4964 | ||
4965 | if (dsc->u.branch.link) | |
4966 | { | |
8c8dba6d | 4967 | /* The value of LR should be the next insn of current one. In order |
85102364 | 4968 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
4969 | is Thumb, the bit 0 of LR value should be set to 1. */ |
4970 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
4971 | ||
4972 | if (dsc->is_thumb) | |
4973 | next_insn_addr |= 0x1; | |
4974 | ||
4975 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
4976 | CANNOT_WRITE_PC); | |
cca44b1b JB |
4977 | } |
4978 | ||
bf9f652a | 4979 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
4980 | } |
4981 | ||
4982 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
4983 | ||
7ff120b4 YQ |
4984 | static void |
4985 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4986 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
4987 | unsigned int cond, int exchange, int link, long offset) |
4988 | { | |
4989 | /* Implement "BL<cond> <label>" as: | |
4990 | ||
4991 | Preparation: cond <- instruction condition | |
4992 | Insn: mov r0, r0 (nop) | |
4993 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
4994 | ||
4995 | B<cond> similar, but don't set r14 in cleanup. */ | |
4996 | ||
4997 | dsc->u.branch.cond = cond; | |
4998 | dsc->u.branch.link = link; | |
4999 | dsc->u.branch.exchange = exchange; | |
5000 | ||
2b16b2e3 YQ |
5001 | dsc->u.branch.dest = dsc->insn_addr; |
5002 | if (link && exchange) | |
5003 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5004 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5005 | ||
7ff120b4 | 5006 | if (dsc->is_thumb) |
2b16b2e3 | 5007 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5008 | else |
2b16b2e3 | 5009 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5010 | |
5011 | dsc->cleanup = &cleanup_branch; | |
5012 | } | |
cca44b1b | 5013 | static int |
7ff120b4 | 5014 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5015 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5016 | { |
5017 | unsigned int cond = bits (insn, 28, 31); | |
5018 | int exchange = (cond == 0xf); | |
5019 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5020 | long offset; |
5021 | ||
136821d9 SM |
5022 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5023 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5024 | (unsigned long) insn); | |
cca44b1b JB |
5025 | if (exchange) |
5026 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5027 | then arrange the switch into Thumb mode. */ | |
5028 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5029 | else | |
5030 | offset = bits (insn, 0, 23) << 2; | |
5031 | ||
5032 | if (bit (offset, 25)) | |
5033 | offset = offset | ~0x3ffffff; | |
5034 | ||
cca44b1b JB |
5035 | dsc->modinsn[0] = ARM_NOP; |
5036 | ||
7ff120b4 | 5037 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5038 | return 0; |
5039 | } | |
5040 | ||
34518530 YQ |
5041 | static int |
5042 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5043 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5044 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5045 | { |
5046 | int link = bit (insn2, 14); | |
5047 | int exchange = link && !bit (insn2, 12); | |
5048 | int cond = INST_AL; | |
5049 | long offset = 0; | |
5050 | int j1 = bit (insn2, 13); | |
5051 | int j2 = bit (insn2, 11); | |
5052 | int s = sbits (insn1, 10, 10); | |
5053 | int i1 = !(j1 ^ bit (insn1, 10)); | |
5054 | int i2 = !(j2 ^ bit (insn1, 10)); | |
5055 | ||
5056 | if (!link && !exchange) /* B */ | |
5057 | { | |
5058 | offset = (bits (insn2, 0, 10) << 1); | |
5059 | if (bit (insn2, 12)) /* Encoding T4 */ | |
5060 | { | |
5061 | offset |= (bits (insn1, 0, 9) << 12) | |
5062 | | (i2 << 22) | |
5063 | | (i1 << 23) | |
5064 | | (s << 24); | |
5065 | cond = INST_AL; | |
5066 | } | |
5067 | else /* Encoding T3 */ | |
5068 | { | |
5069 | offset |= (bits (insn1, 0, 5) << 12) | |
5070 | | (j1 << 18) | |
5071 | | (j2 << 19) | |
5072 | | (s << 20); | |
5073 | cond = bits (insn1, 6, 9); | |
5074 | } | |
5075 | } | |
5076 | else | |
5077 | { | |
5078 | offset = (bits (insn1, 0, 9) << 12); | |
5079 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
5080 | offset |= exchange ? | |
5081 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
5082 | } | |
5083 | ||
136821d9 SM |
5084 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
5085 | link ? (exchange) ? "blx" : "bl" : "b", | |
5086 | insn1, insn2, offset); | |
34518530 YQ |
5087 | |
5088 | dsc->modinsn[0] = THUMB_NOP; | |
5089 | ||
5090 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
5091 | return 0; | |
5092 | } | |
5093 | ||
5094 | /* Copy B Thumb instructions. */ | |
5095 | static int | |
615234c1 | 5096 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 5097 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5098 | { |
5099 | unsigned int cond = 0; | |
5100 | int offset = 0; | |
5101 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
5102 | CORE_ADDR from = dsc->insn_addr; | |
5103 | ||
5104 | if (bit_12_15 == 0xd) | |
5105 | { | |
5106 | /* offset = SignExtend (imm8:0, 32) */ | |
5107 | offset = sbits ((insn << 1), 0, 8); | |
5108 | cond = bits (insn, 8, 11); | |
5109 | } | |
5110 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
5111 | { | |
5112 | offset = sbits ((insn << 1), 0, 11); | |
5113 | cond = INST_AL; | |
5114 | } | |
5115 | ||
136821d9 SM |
5116 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
5117 | insn, offset); | |
34518530 YQ |
5118 | |
5119 | dsc->u.branch.cond = cond; | |
5120 | dsc->u.branch.link = 0; | |
5121 | dsc->u.branch.exchange = 0; | |
5122 | dsc->u.branch.dest = from + 4 + offset; | |
5123 | ||
5124 | dsc->modinsn[0] = THUMB_NOP; | |
5125 | ||
5126 | dsc->cleanup = &cleanup_branch; | |
5127 | ||
5128 | return 0; | |
5129 | } | |
5130 | ||
cca44b1b JB |
5131 | /* Copy BX/BLX with register-specified destinations. */ |
5132 | ||
7ff120b4 YQ |
5133 | static void |
5134 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5135 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 5136 | unsigned int cond, unsigned int rm) |
cca44b1b | 5137 | { |
cca44b1b JB |
5138 | /* Implement {BX,BLX}<cond> <reg>" as: |
5139 | ||
5140 | Preparation: cond <- instruction condition | |
5141 | Insn: mov r0, r0 (nop) | |
5142 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5143 | ||
5144 | Don't set r14 in cleanup for BX. */ | |
5145 | ||
36073a92 | 5146 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5147 | |
5148 | dsc->u.branch.cond = cond; | |
5149 | dsc->u.branch.link = link; | |
cca44b1b | 5150 | |
7ff120b4 | 5151 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
5152 | |
5153 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 5154 | } |
cca44b1b | 5155 | |
7ff120b4 YQ |
5156 | static int |
5157 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 5158 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5159 | { |
5160 | unsigned int cond = bits (insn, 28, 31); | |
5161 | /* BX: x12xxx1x | |
5162 | BLX: x12xxx3x. */ | |
5163 | int link = bit (insn, 5); | |
5164 | unsigned int rm = bits (insn, 0, 3); | |
5165 | ||
136821d9 | 5166 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
5167 | |
5168 | dsc->modinsn[0] = ARM_NOP; | |
5169 | ||
5170 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
5171 | return 0; |
5172 | } | |
5173 | ||
34518530 YQ |
5174 | static int |
5175 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5176 | struct regcache *regs, | |
1152d984 | 5177 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5178 | { |
5179 | int link = bit (insn, 7); | |
5180 | unsigned int rm = bits (insn, 3, 6); | |
5181 | ||
136821d9 | 5182 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
5183 | |
5184 | dsc->modinsn[0] = THUMB_NOP; | |
5185 | ||
5186 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
5187 | ||
5188 | return 0; | |
5189 | } | |
5190 | ||
5191 | ||
0963b4bd | 5192 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
5193 | |
5194 | static void | |
6e39997a | 5195 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 5196 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5197 | { |
36073a92 | 5198 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5199 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
5200 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5201 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5202 | } | |
5203 | ||
5204 | static int | |
7ff120b4 | 5205 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5206 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5207 | { |
5208 | unsigned int rn = bits (insn, 16, 19); | |
5209 | unsigned int rd = bits (insn, 12, 15); | |
5210 | unsigned int op = bits (insn, 21, 24); | |
5211 | int is_mov = (op == 0xd); | |
5212 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
5213 | |
5214 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 5215 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 5216 | |
136821d9 SM |
5217 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
5218 | is_mov ? "move" : "ALU", | |
5219 | (unsigned long) insn); | |
cca44b1b JB |
5220 | |
5221 | /* Instruction is of form: | |
5222 | ||
5223 | <op><cond> rd, [rn,] #imm | |
5224 | ||
5225 | Rewrite as: | |
5226 | ||
5227 | Preparation: tmp1, tmp2 <- r0, r1; | |
5228 | r0, r1 <- rd, rn | |
5229 | Insn: <op><cond> r0, r1, #imm | |
5230 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5231 | */ | |
5232 | ||
36073a92 YQ |
5233 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5234 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5235 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5236 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
5237 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5238 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5239 | dsc->rd = rd; | |
5240 | ||
5241 | if (is_mov) | |
5242 | dsc->modinsn[0] = insn & 0xfff00fff; | |
5243 | else | |
5244 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
5245 | ||
5246 | dsc->cleanup = &cleanup_alu_imm; | |
5247 | ||
5248 | return 0; | |
5249 | } | |
5250 | ||
34518530 YQ |
5251 | static int |
5252 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5253 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5254 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5255 | { |
5256 | unsigned int op = bits (insn1, 5, 8); | |
5257 | unsigned int rn, rm, rd; | |
5258 | ULONGEST rd_val, rn_val; | |
5259 | ||
5260 | rn = bits (insn1, 0, 3); /* Rn */ | |
5261 | rm = bits (insn2, 0, 3); /* Rm */ | |
5262 | rd = bits (insn2, 8, 11); /* Rd */ | |
5263 | ||
5264 | /* This routine is only called for instruction MOV. */ | |
5265 | gdb_assert (op == 0x2 && rn == 0xf); | |
5266 | ||
5267 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
5268 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
5269 | ||
136821d9 | 5270 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
5271 | |
5272 | /* Instruction is of form: | |
5273 | ||
5274 | <op><cond> rd, [rn,] #imm | |
5275 | ||
5276 | Rewrite as: | |
5277 | ||
5278 | Preparation: tmp1, tmp2 <- r0, r1; | |
5279 | r0, r1 <- rd, rn | |
5280 | Insn: <op><cond> r0, r1, #imm | |
5281 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5282 | */ | |
5283 | ||
5284 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5285 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5286 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5287 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5288 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
5289 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5290 | dsc->rd = rd; | |
5291 | ||
5292 | dsc->modinsn[0] = insn1; | |
5293 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
5294 | dsc->numinsns = 2; | |
5295 | ||
5296 | dsc->cleanup = &cleanup_alu_imm; | |
5297 | ||
5298 | return 0; | |
5299 | } | |
5300 | ||
cca44b1b JB |
5301 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
5302 | ||
5303 | static void | |
6e39997a | 5304 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 5305 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5306 | { |
5307 | ULONGEST rd_val; | |
5308 | int i; | |
5309 | ||
36073a92 | 5310 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5311 | |
5312 | for (i = 0; i < 3; i++) | |
5313 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5314 | ||
5315 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5316 | } | |
5317 | ||
7ff120b4 YQ |
5318 | static void |
5319 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5320 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5321 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 5322 | { |
cca44b1b | 5323 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 5324 | |
cca44b1b JB |
5325 | /* Instruction is of form: |
5326 | ||
5327 | <op><cond> rd, [rn,] rm [, <shift>] | |
5328 | ||
5329 | Rewrite as: | |
5330 | ||
5331 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
5332 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 5333 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
5334 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
5335 | */ | |
5336 | ||
36073a92 YQ |
5337 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5338 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5339 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5340 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5341 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5342 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5343 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5344 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5345 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5346 | dsc->rd = rd; | |
5347 | ||
7ff120b4 YQ |
5348 | dsc->cleanup = &cleanup_alu_reg; |
5349 | } | |
5350 | ||
5351 | static int | |
5352 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 5353 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5354 | { |
5355 | unsigned int op = bits (insn, 21, 24); | |
5356 | int is_mov = (op == 0xd); | |
5357 | ||
5358 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5359 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
5360 | ||
136821d9 SM |
5361 | displaced_debug_printf ("copying reg %s insn %.8lx", |
5362 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 5363 | |
cca44b1b JB |
5364 | if (is_mov) |
5365 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
5366 | else | |
5367 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
5368 | ||
7ff120b4 YQ |
5369 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
5370 | bits (insn, 0, 3)); | |
cca44b1b JB |
5371 | return 0; |
5372 | } | |
5373 | ||
34518530 YQ |
5374 | static int |
5375 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5376 | struct regcache *regs, | |
1152d984 | 5377 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5378 | { |
ef713951 | 5379 | unsigned rm, rd; |
34518530 | 5380 | |
ef713951 YQ |
5381 | rm = bits (insn, 3, 6); |
5382 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 5383 | |
ef713951 | 5384 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
5385 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
5386 | ||
136821d9 | 5387 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 5388 | |
ef713951 | 5389 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 5390 | |
ef713951 | 5391 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
5392 | |
5393 | return 0; | |
5394 | } | |
5395 | ||
cca44b1b JB |
5396 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
5397 | ||
5398 | static void | |
6e39997a | 5399 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 5400 | struct regcache *regs, |
1152d984 | 5401 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5402 | { |
36073a92 | 5403 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5404 | int i; |
5405 | ||
5406 | for (i = 0; i < 4; i++) | |
5407 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5408 | ||
5409 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5410 | } | |
5411 | ||
7ff120b4 YQ |
5412 | static void |
5413 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5414 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5415 | unsigned int rd, unsigned int rn, unsigned int rm, |
5416 | unsigned rs) | |
cca44b1b | 5417 | { |
7ff120b4 | 5418 | int i; |
cca44b1b | 5419 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 5420 | |
cca44b1b JB |
5421 | /* Instruction is of form: |
5422 | ||
5423 | <op><cond> rd, [rn,] rm, <shift> rs | |
5424 | ||
5425 | Rewrite as: | |
5426 | ||
5427 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
5428 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
5429 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
5430 | Cleanup: tmp5 <- r0 | |
5431 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
5432 | rd <- tmp5 | |
5433 | */ | |
5434 | ||
5435 | for (i = 0; i < 4; i++) | |
36073a92 | 5436 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 5437 | |
36073a92 YQ |
5438 | rd_val = displaced_read_reg (regs, dsc, rd); |
5439 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5440 | rm_val = displaced_read_reg (regs, dsc, rm); | |
5441 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
5442 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5443 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5444 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5445 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
5446 | dsc->rd = rd; | |
7ff120b4 YQ |
5447 | dsc->cleanup = &cleanup_alu_shifted_reg; |
5448 | } | |
5449 | ||
5450 | static int | |
5451 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5452 | struct regcache *regs, | |
1152d984 | 5453 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5454 | { |
5455 | unsigned int op = bits (insn, 21, 24); | |
5456 | int is_mov = (op == 0xd); | |
5457 | unsigned int rd, rn, rm, rs; | |
5458 | ||
5459 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
5460 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
5461 | ||
136821d9 SM |
5462 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
5463 | is_mov ? "move" : "ALU", | |
5464 | (unsigned long) insn); | |
7ff120b4 YQ |
5465 | |
5466 | rn = bits (insn, 16, 19); | |
5467 | rm = bits (insn, 0, 3); | |
5468 | rs = bits (insn, 8, 11); | |
5469 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
5470 | |
5471 | if (is_mov) | |
5472 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
5473 | else | |
5474 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
5475 | ||
7ff120b4 | 5476 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
5477 | |
5478 | return 0; | |
5479 | } | |
5480 | ||
5481 | /* Clean up load instructions. */ | |
5482 | ||
5483 | static void | |
6e39997a | 5484 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5485 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5486 | { |
5487 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 5488 | |
36073a92 | 5489 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 5490 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
5491 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
5492 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
5493 | |
5494 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5495 | if (dsc->u.ldst.xfersize > 4) | |
5496 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5497 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5498 | if (!dsc->u.ldst.immed) | |
5499 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5500 | ||
5501 | /* Handle register writeback. */ | |
5502 | if (dsc->u.ldst.writeback) | |
5503 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5504 | /* Put result in right place. */ | |
5505 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
5506 | if (dsc->u.ldst.xfersize == 8) | |
5507 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
5508 | } | |
5509 | ||
5510 | /* Clean up store instructions. */ | |
5511 | ||
5512 | static void | |
6e39997a | 5513 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5514 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5515 | { |
36073a92 | 5516 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
5517 | |
5518 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5519 | if (dsc->u.ldst.xfersize > 4) | |
5520 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5521 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5522 | if (!dsc->u.ldst.immed) | |
5523 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5524 | if (!dsc->u.ldst.restore_r4) | |
5525 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
5526 | ||
5527 | /* Writeback. */ | |
5528 | if (dsc->u.ldst.writeback) | |
5529 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5530 | } | |
5531 | ||
5532 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
5533 | transfers, which have a different encoding to byte/word transfers. */ | |
5534 | ||
5535 | static int | |
550dc4e2 | 5536 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 5537 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5538 | { |
5539 | unsigned int op1 = bits (insn, 20, 24); | |
5540 | unsigned int op2 = bits (insn, 5, 6); | |
5541 | unsigned int rt = bits (insn, 12, 15); | |
5542 | unsigned int rn = bits (insn, 16, 19); | |
5543 | unsigned int rm = bits (insn, 0, 3); | |
5544 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
5545 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
5546 | int immed = (op1 & 0x4) != 0; | |
5547 | int opcode; | |
5548 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
5549 | |
5550 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 5551 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 5552 | |
136821d9 SM |
5553 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
5554 | unprivileged ? "unprivileged " : "", | |
5555 | (unsigned long) insn); | |
cca44b1b JB |
5556 | |
5557 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
5558 | ||
5559 | if (opcode < 0) | |
5560 | internal_error (__FILE__, __LINE__, | |
5561 | _("copy_extra_ld_st: instruction decode error")); | |
5562 | ||
36073a92 YQ |
5563 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5564 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5565 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5566 | if (!immed) |
36073a92 | 5567 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5568 | |
36073a92 | 5569 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 5570 | if (bytesize[opcode] == 8) |
36073a92 YQ |
5571 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
5572 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5573 | if (!immed) |
36073a92 | 5574 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5575 | |
5576 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5577 | if (bytesize[opcode] == 8) | |
5578 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
5579 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5580 | if (!immed) | |
5581 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
5582 | ||
5583 | dsc->rd = rt; | |
5584 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
5585 | dsc->u.ldst.rn = rn; | |
5586 | dsc->u.ldst.immed = immed; | |
5587 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
5588 | dsc->u.ldst.restore_r4 = 0; | |
5589 | ||
5590 | if (immed) | |
5591 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
5592 | -> | |
5593 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
5594 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5595 | else | |
5596 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
5597 | -> | |
5598 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
5599 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5600 | ||
5601 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
5602 | ||
5603 | return 0; | |
5604 | } | |
5605 | ||
0f6f04ba | 5606 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 5607 | |
7ff120b4 | 5608 | static void |
0f6f04ba | 5609 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5610 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
5611 | int immed, int writeback, int size, int usermode, |
5612 | int rt, int rm, int rn) | |
cca44b1b | 5613 | { |
cca44b1b | 5614 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 5615 | |
36073a92 YQ |
5616 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5617 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5618 | if (!immed) |
36073a92 | 5619 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5620 | if (!load) |
36073a92 | 5621 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 5622 | |
36073a92 YQ |
5623 | rt_val = displaced_read_reg (regs, dsc, rt); |
5624 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5625 | if (!immed) |
36073a92 | 5626 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5627 | |
5628 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5629 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5630 | if (!immed) | |
5631 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 5632 | dsc->rd = rt; |
0f6f04ba | 5633 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
5634 | dsc->u.ldst.rn = rn; |
5635 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 5636 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5637 | |
5638 | /* To write PC we can do: | |
5639 | ||
494e194e YQ |
5640 | Before this sequence of instructions: |
5641 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 5642 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
5643 | |
5644 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
5645 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
5646 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
5647 | = addr(Insn1) + offset - addr(Insn3) - 8 |
5648 | = offset - 16 | |
494e194e YQ |
5649 | Insn4: add r4, r4, #8 r4 = offset - 8 |
5650 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 5651 | = from + offset |
494e194e | 5652 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
5653 | |
5654 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
5655 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
5656 | of this can be found in Section "Saving from r15" in | |
5657 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 5658 | |
7ff120b4 YQ |
5659 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
5660 | } | |
5661 | ||
34518530 YQ |
5662 | |
5663 | static int | |
5664 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
5665 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5666 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
5667 | { |
5668 | unsigned int u_bit = bit (insn1, 7); | |
5669 | unsigned int rt = bits (insn2, 12, 15); | |
5670 | int imm12 = bits (insn2, 0, 11); | |
5671 | ULONGEST pc_val; | |
5672 | ||
136821d9 SM |
5673 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
5674 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
5675 | imm12); | |
34518530 YQ |
5676 | |
5677 | if (!u_bit) | |
5678 | imm12 = -1 * imm12; | |
5679 | ||
5680 | /* Rewrite instruction LDR Rt imm12 into: | |
5681 | ||
5682 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
5683 | ||
5684 | LDR R0, R2, R3, | |
5685 | ||
5686 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
5687 | ||
5688 | ||
5689 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5690 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5691 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
5692 | ||
5693 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5694 | ||
5695 | pc_val = pc_val & 0xfffffffc; | |
5696 | ||
5697 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
5698 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
5699 | ||
5700 | dsc->rd = rt; | |
5701 | ||
5702 | dsc->u.ldst.xfersize = size; | |
5703 | dsc->u.ldst.immed = 0; | |
5704 | dsc->u.ldst.writeback = 0; | |
5705 | dsc->u.ldst.restore_r4 = 0; | |
5706 | ||
5707 | /* LDR R0, R2, R3 */ | |
5708 | dsc->modinsn[0] = 0xf852; | |
5709 | dsc->modinsn[1] = 0x3; | |
5710 | dsc->numinsns = 2; | |
5711 | ||
5712 | dsc->cleanup = &cleanup_load; | |
5713 | ||
5714 | return 0; | |
5715 | } | |
5716 | ||
5717 | static int | |
5718 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5719 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5720 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
5721 | int writeback, int immed) |
5722 | { | |
5723 | unsigned int rt = bits (insn2, 12, 15); | |
5724 | unsigned int rn = bits (insn1, 0, 3); | |
5725 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
5726 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
5727 | be PC, so we don't have to check it. */ | |
5728 | ||
5729 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
5730 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
5731 | dsc); | |
5732 | ||
136821d9 SM |
5733 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
5734 | rt, rn, insn1, insn2); | |
34518530 YQ |
5735 | |
5736 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
5737 | 0, rt, rm, rn); | |
5738 | ||
5739 | dsc->u.ldst.restore_r4 = 0; | |
5740 | ||
5741 | if (immed) | |
5742 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
5743 | -> | |
5744 | ldr[b]<cond> r0, [r2, #imm]. */ | |
5745 | { | |
5746 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5747 | dsc->modinsn[1] = insn2 & 0x0fff; | |
5748 | } | |
5749 | else | |
5750 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
5751 | -> | |
5752 | ldr[b]<cond> r0, [r2, r3]. */ | |
5753 | { | |
5754 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5755 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
5756 | } | |
5757 | ||
5758 | dsc->numinsns = 2; | |
5759 | ||
5760 | return 0; | |
5761 | } | |
5762 | ||
5763 | ||
7ff120b4 YQ |
5764 | static int |
5765 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
5766 | struct regcache *regs, | |
1152d984 | 5767 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 5768 | int load, int size, int usermode) |
7ff120b4 YQ |
5769 | { |
5770 | int immed = !bit (insn, 25); | |
5771 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
5772 | unsigned int rt = bits (insn, 12, 15); | |
5773 | unsigned int rn = bits (insn, 16, 19); | |
5774 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
5775 | ||
5776 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5777 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
5778 | ||
136821d9 SM |
5779 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
5780 | load ? (size == 1 ? "ldrb" : "ldr") | |
5781 | : (size == 1 ? "strb" : "str"), | |
5782 | usermode ? "t" : "", | |
5783 | rt, rn, | |
5784 | (unsigned long) insn); | |
7ff120b4 | 5785 | |
0f6f04ba YQ |
5786 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
5787 | usermode, rt, rm, rn); | |
7ff120b4 | 5788 | |
bf9f652a | 5789 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
5790 | { |
5791 | dsc->u.ldst.restore_r4 = 0; | |
5792 | ||
5793 | if (immed) | |
5794 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
5795 | -> | |
5796 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
5797 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5798 | else | |
5799 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
5800 | -> | |
5801 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
5802 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5803 | } | |
5804 | else | |
5805 | { | |
5806 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
5807 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
5808 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
5809 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
5810 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
5811 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
5812 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
5813 | ||
5814 | /* As above. */ | |
5815 | if (immed) | |
5816 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
5817 | else | |
5818 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
5819 | ||
cca44b1b JB |
5820 | dsc->numinsns = 6; |
5821 | } | |
5822 | ||
5823 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
5824 | ||
5825 | return 0; | |
5826 | } | |
5827 | ||
5828 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
5829 | unfortunate corner case: it's impossible to implement correctly by modifying | |
5830 | the instruction. The issue is as follows: we have an instruction, | |
5831 | ||
5832 | ldm rN, {r0-r15} | |
5833 | ||
5834 | which we must rewrite to avoid loading PC. A possible solution would be to | |
5835 | do the load in two halves, something like (with suitable cleanup | |
5836 | afterwards): | |
5837 | ||
5838 | mov r8, rN | |
5839 | ldm[id][ab] r8!, {r0-r7} | |
5840 | str r7, <temp> | |
5841 | ldm[id][ab] r8, {r7-r14} | |
5842 | <bkpt> | |
5843 | ||
5844 | but at present there's no suitable place for <temp>, since the scratch space | |
5845 | is overwritten before the cleanup routine is called. For now, we simply | |
5846 | emulate the instruction. */ | |
5847 | ||
5848 | static void | |
5849 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5850 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5851 | { |
cca44b1b JB |
5852 | int inc = dsc->u.block.increment; |
5853 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
5854 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
5855 | uint32_t regmask = dsc->u.block.regmask; | |
5856 | int regno = inc ? 0 : 15; | |
5857 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
5858 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
5859 | && (regmask & 0x8000) != 0; | |
36073a92 | 5860 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5861 | int do_transfer = condition_true (dsc->u.block.cond, status); |
5862 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5863 | ||
5864 | if (!do_transfer) | |
5865 | return; | |
5866 | ||
5867 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
5868 | sensible we can do here. Complain loudly. */ | |
5869 | if (exception_return) | |
5870 | error (_("Cannot single-step exception return")); | |
5871 | ||
5872 | /* We don't handle any stores here for now. */ | |
5873 | gdb_assert (dsc->u.block.load != 0); | |
5874 | ||
136821d9 SM |
5875 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
5876 | dsc->u.block.load ? "ldm" : "stm", | |
5877 | dsc->u.block.increment ? "inc" : "dec", | |
5878 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
5879 | |
5880 | while (regmask) | |
5881 | { | |
5882 | uint32_t memword; | |
5883 | ||
5884 | if (inc) | |
bf9f652a | 5885 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
5886 | regno++; |
5887 | else | |
5888 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
5889 | regno--; | |
5890 | ||
5891 | xfer_addr += bump_before; | |
5892 | ||
5893 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
5894 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
5895 | ||
5896 | xfer_addr += bump_after; | |
5897 | ||
5898 | regmask &= ~(1 << regno); | |
5899 | } | |
5900 | ||
5901 | if (dsc->u.block.writeback) | |
5902 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
5903 | CANNOT_WRITE_PC); | |
5904 | } | |
5905 | ||
5906 | /* Clean up an STM which included the PC in the register list. */ | |
5907 | ||
5908 | static void | |
5909 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5910 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5911 | { |
36073a92 | 5912 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 5913 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
5914 | CORE_ADDR pc_stored_at, transferred_regs |
5915 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
5916 | CORE_ADDR stm_insn_addr; |
5917 | uint32_t pc_val; | |
5918 | long offset; | |
5919 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5920 | ||
5921 | /* If condition code fails, there's nothing else to do. */ | |
5922 | if (!store_executed) | |
5923 | return; | |
5924 | ||
5925 | if (dsc->u.block.increment) | |
5926 | { | |
5927 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
5928 | ||
5929 | if (dsc->u.block.before) | |
5930 | pc_stored_at += 4; | |
5931 | } | |
5932 | else | |
5933 | { | |
5934 | pc_stored_at = dsc->u.block.xfer_addr; | |
5935 | ||
5936 | if (dsc->u.block.before) | |
5937 | pc_stored_at -= 4; | |
5938 | } | |
5939 | ||
5940 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
5941 | stm_insn_addr = dsc->scratch_base; | |
5942 | offset = pc_val - stm_insn_addr; | |
5943 | ||
136821d9 SM |
5944 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
5945 | offset); | |
cca44b1b JB |
5946 | |
5947 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
5948 | instruction. */ | |
5949 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
5950 | dsc->insn_addr + offset); | |
5951 | } | |
5952 | ||
5953 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
5954 | the registers in the transferred list into a contiguous range r0...rX (to | |
5955 | avoid loading PC directly and losing control of the debugged program), so we | |
5956 | must undo that here. */ | |
5957 | ||
5958 | static void | |
6e39997a | 5959 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 5960 | struct regcache *regs, |
1152d984 | 5961 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5962 | { |
36073a92 | 5963 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 5964 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 5965 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 5966 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
5967 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
5968 | ||
5969 | /* The method employed here will fail if the register list is fully populated | |
5970 | (we need to avoid loading PC directly). */ | |
5971 | gdb_assert (num_to_shuffle < 16); | |
5972 | ||
5973 | if (!load_executed) | |
5974 | return; | |
5975 | ||
5976 | clobbered = (1 << num_to_shuffle) - 1; | |
5977 | ||
5978 | while (num_to_shuffle > 0) | |
5979 | { | |
5980 | if ((mask & (1 << write_reg)) != 0) | |
5981 | { | |
5982 | unsigned int read_reg = num_to_shuffle - 1; | |
5983 | ||
5984 | if (read_reg != write_reg) | |
5985 | { | |
36073a92 | 5986 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 5987 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
5988 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
5989 | read_reg, write_reg); | |
cca44b1b | 5990 | } |
136821d9 SM |
5991 | else |
5992 | displaced_debug_printf ("LDM: register r%d already in the right " | |
5993 | "place", write_reg); | |
cca44b1b JB |
5994 | |
5995 | clobbered &= ~(1 << write_reg); | |
5996 | ||
5997 | num_to_shuffle--; | |
5998 | } | |
5999 | ||
6000 | write_reg--; | |
6001 | } | |
6002 | ||
6003 | /* Restore any registers we scribbled over. */ | |
6004 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6005 | { | |
6006 | if ((clobbered & (1 << write_reg)) != 0) | |
6007 | { | |
6008 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6009 | CANNOT_WRITE_PC); | |
136821d9 SM |
6010 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6011 | write_reg); | |
cca44b1b JB |
6012 | clobbered &= ~(1 << write_reg); |
6013 | } | |
6014 | } | |
6015 | ||
6016 | /* Perform register writeback manually. */ | |
6017 | if (dsc->u.block.writeback) | |
6018 | { | |
6019 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6020 | ||
6021 | if (dsc->u.block.increment) | |
6022 | new_rn_val += regs_loaded * 4; | |
6023 | else | |
6024 | new_rn_val -= regs_loaded * 4; | |
6025 | ||
6026 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6027 | CANNOT_WRITE_PC); | |
6028 | } | |
6029 | } | |
6030 | ||
6031 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6032 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6033 | ||
6034 | static int | |
7ff120b4 YQ |
6035 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6036 | struct regcache *regs, | |
1152d984 | 6037 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6038 | { |
6039 | int load = bit (insn, 20); | |
6040 | int user = bit (insn, 22); | |
6041 | int increment = bit (insn, 23); | |
6042 | int before = bit (insn, 24); | |
6043 | int writeback = bit (insn, 21); | |
6044 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6045 | |
0963b4bd MS |
6046 | /* Block transfers which don't mention PC can be run directly |
6047 | out-of-line. */ | |
bf9f652a | 6048 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 6049 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 6050 | |
bf9f652a | 6051 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 6052 | { |
0963b4bd MS |
6053 | warning (_("displaced: Unpredictable LDM or STM with " |
6054 | "base register r15")); | |
7ff120b4 | 6055 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
6056 | } |
6057 | ||
136821d9 SM |
6058 | displaced_debug_printf ("copying block transfer insn %.8lx", |
6059 | (unsigned long) insn); | |
cca44b1b | 6060 | |
36073a92 | 6061 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
6062 | dsc->u.block.rn = rn; |
6063 | ||
6064 | dsc->u.block.load = load; | |
6065 | dsc->u.block.user = user; | |
6066 | dsc->u.block.increment = increment; | |
6067 | dsc->u.block.before = before; | |
6068 | dsc->u.block.writeback = writeback; | |
6069 | dsc->u.block.cond = bits (insn, 28, 31); | |
6070 | ||
6071 | dsc->u.block.regmask = insn & 0xffff; | |
6072 | ||
6073 | if (load) | |
6074 | { | |
6075 | if ((insn & 0xffff) == 0xffff) | |
6076 | { | |
6077 | /* LDM with a fully-populated register list. This case is | |
6078 | particularly tricky. Implement for now by fully emulating the | |
6079 | instruction (which might not behave perfectly in all cases, but | |
6080 | these instructions should be rare enough for that not to matter | |
6081 | too much). */ | |
6082 | dsc->modinsn[0] = ARM_NOP; | |
6083 | ||
6084 | dsc->cleanup = &cleanup_block_load_all; | |
6085 | } | |
6086 | else | |
6087 | { | |
6088 | /* LDM of a list of registers which includes PC. Implement by | |
6089 | rewriting the list of registers to be transferred into a | |
6090 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
6091 | registers into the correct places in the cleanup routine. */ | |
6092 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 6093 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6094 | unsigned int i; |
cca44b1b JB |
6095 | |
6096 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 6097 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
6098 | |
6099 | /* Writeback makes things complicated. We need to avoid clobbering | |
6100 | the base register with one of the registers in our modified | |
6101 | register list, but just using a different register can't work in | |
6102 | all cases, e.g.: | |
6103 | ||
6104 | ldm r14!, {r0-r13,pc} | |
6105 | ||
6106 | which would need to be rewritten as: | |
6107 | ||
6108 | ldm rN!, {r0-r14} | |
6109 | ||
6110 | but that can't work, because there's no free register for N. | |
6111 | ||
6112 | Solve this by turning off the writeback bit, and emulating | |
6113 | writeback manually in the cleanup routine. */ | |
6114 | ||
6115 | if (writeback) | |
6116 | insn &= ~(1 << 21); | |
6117 | ||
6118 | new_regmask = (1 << num_in_list) - 1; | |
6119 | ||
136821d9 SM |
6120 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6121 | "%.4x, modified list %.4x", | |
6122 | rn, writeback ? "!" : "", | |
6123 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
6124 | |
6125 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6126 | ||
6127 | dsc->cleanup = &cleanup_block_load_pc; | |
6128 | } | |
6129 | } | |
6130 | else | |
6131 | { | |
6132 | /* STM of a list of registers which includes PC. Run the instruction | |
6133 | as-is, but out of line: this will store the wrong value for the PC, | |
6134 | so we must manually fix up the memory in the cleanup routine. | |
6135 | Doing things this way has the advantage that we can auto-detect | |
6136 | the offset of the PC write (which is architecture-dependent) in | |
6137 | the cleanup routine. */ | |
6138 | dsc->modinsn[0] = insn; | |
6139 | ||
6140 | dsc->cleanup = &cleanup_block_store_pc; | |
6141 | } | |
6142 | ||
6143 | return 0; | |
6144 | } | |
6145 | ||
34518530 YQ |
6146 | static int |
6147 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6148 | struct regcache *regs, | |
1152d984 | 6149 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6150 | { |
34518530 YQ |
6151 | int rn = bits (insn1, 0, 3); |
6152 | int load = bit (insn1, 4); | |
6153 | int writeback = bit (insn1, 5); | |
cca44b1b | 6154 | |
34518530 YQ |
6155 | /* Block transfers which don't mention PC can be run directly |
6156 | out-of-line. */ | |
6157 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
6158 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 6159 | |
34518530 YQ |
6160 | if (rn == ARM_PC_REGNUM) |
6161 | { | |
6162 | warning (_("displaced: Unpredictable LDM or STM with " | |
6163 | "base register r15")); | |
6164 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6165 | "unpredictable ldm/stm", dsc); | |
6166 | } | |
cca44b1b | 6167 | |
136821d9 SM |
6168 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
6169 | insn1, insn2); | |
cca44b1b | 6170 | |
34518530 YQ |
6171 | /* Clear bit 13, since it should be always zero. */ |
6172 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
6173 | dsc->u.block.rn = rn; | |
cca44b1b | 6174 | |
34518530 YQ |
6175 | dsc->u.block.load = load; |
6176 | dsc->u.block.user = 0; | |
6177 | dsc->u.block.increment = bit (insn1, 7); | |
6178 | dsc->u.block.before = bit (insn1, 8); | |
6179 | dsc->u.block.writeback = writeback; | |
6180 | dsc->u.block.cond = INST_AL; | |
6181 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6182 | |
34518530 YQ |
6183 | if (load) |
6184 | { | |
6185 | if (dsc->u.block.regmask == 0xffff) | |
6186 | { | |
6187 | /* This branch is impossible to happen. */ | |
6188 | gdb_assert (0); | |
6189 | } | |
6190 | else | |
6191 | { | |
6192 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 6193 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6194 | unsigned int i; |
34518530 YQ |
6195 | |
6196 | for (i = 0; i < num_in_list; i++) | |
6197 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
6198 | ||
6199 | if (writeback) | |
6200 | insn1 &= ~(1 << 5); | |
6201 | ||
6202 | new_regmask = (1 << num_in_list) - 1; | |
6203 | ||
136821d9 SM |
6204 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6205 | "%.4x, modified list %.4x", | |
6206 | rn, writeback ? "!" : "", | |
6207 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
6208 | |
6209 | dsc->modinsn[0] = insn1; | |
6210 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
6211 | dsc->numinsns = 2; | |
6212 | ||
6213 | dsc->cleanup = &cleanup_block_load_pc; | |
6214 | } | |
6215 | } | |
6216 | else | |
6217 | { | |
6218 | dsc->modinsn[0] = insn1; | |
6219 | dsc->modinsn[1] = insn2; | |
6220 | dsc->numinsns = 2; | |
6221 | dsc->cleanup = &cleanup_block_store_pc; | |
6222 | } | |
6223 | return 0; | |
6224 | } | |
6225 | ||
d9311bfa AT |
6226 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
6227 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
6228 | ||
6229 | ULONGEST | |
6230 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
6231 | int byte_order) | |
6232 | { | |
5f2dfcfd AT |
6233 | return read_memory_unsigned_integer (memaddr, len, |
6234 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
6235 | } |
6236 | ||
6237 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
6238 | ||
6239 | CORE_ADDR | |
6240 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
6241 | CORE_ADDR val) | |
6242 | { | |
ac7936df | 6243 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
6244 | } |
6245 | ||
6246 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
6247 | ||
e7cf25a8 | 6248 | static CORE_ADDR |
553cb527 | 6249 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 6250 | { |
d9311bfa AT |
6251 | return 0; |
6252 | } | |
6253 | ||
6254 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
6255 | ||
6256 | int | |
6257 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
6258 | { | |
6259 | return arm_is_thumb (self->regcache); | |
6260 | } | |
6261 | ||
6262 | /* single_step() is called just before we want to resume the inferior, | |
6263 | if we want to single-step it but there is no hardware or kernel | |
6264 | single-step support. We find the target of the coming instructions | |
6265 | and breakpoint them. */ | |
6266 | ||
a0ff9e1a | 6267 | std::vector<CORE_ADDR> |
f5ea389a | 6268 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 6269 | { |
ac7936df | 6270 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 6271 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
6272 | |
6273 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
6274 | &arm_get_next_pcs_ops, | |
6275 | gdbarch_byte_order (gdbarch), | |
6276 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 6277 | 0, |
d9311bfa AT |
6278 | regcache); |
6279 | ||
a0ff9e1a | 6280 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 6281 | |
a0ff9e1a SM |
6282 | for (CORE_ADDR &pc_ref : next_pcs) |
6283 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 6284 | |
93f9a11f | 6285 | return next_pcs; |
d9311bfa AT |
6286 | } |
6287 | ||
34518530 YQ |
6288 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
6289 | for Linux, where some SVC instructions must be treated specially. */ | |
6290 | ||
6291 | static void | |
6292 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6293 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6294 | { |
6295 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
6296 | ||
136821d9 SM |
6297 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
6298 | (unsigned long) resume_addr); | |
34518530 YQ |
6299 | |
6300 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
6301 | } | |
6302 | ||
6303 | ||
85102364 | 6304 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
6305 | |
6306 | static int | |
6307 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6308 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6309 | { |
6310 | /* Preparation: none. | |
6311 | Insn: unmodified svc. | |
6312 | Cleanup: pc <- insn_addr + insn_size. */ | |
6313 | ||
6314 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
6315 | instruction. */ | |
6316 | dsc->wrote_to_pc = 1; | |
6317 | ||
6318 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
6319 | if (dsc->u.svc.copy_svc_os) |
6320 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
6321 | else | |
6322 | { | |
6323 | dsc->cleanup = &cleanup_svc; | |
6324 | return 0; | |
6325 | } | |
34518530 YQ |
6326 | } |
6327 | ||
6328 | static int | |
6329 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 6330 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6331 | { |
6332 | ||
136821d9 SM |
6333 | displaced_debug_printf ("copying svc insn %.8lx", |
6334 | (unsigned long) insn); | |
34518530 YQ |
6335 | |
6336 | dsc->modinsn[0] = insn; | |
6337 | ||
6338 | return install_svc (gdbarch, regs, dsc); | |
6339 | } | |
6340 | ||
6341 | static int | |
6342 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 6343 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6344 | { |
6345 | ||
136821d9 | 6346 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 6347 | |
34518530 YQ |
6348 | dsc->modinsn[0] = insn; |
6349 | ||
6350 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
6351 | } |
6352 | ||
6353 | /* Copy undefined instructions. */ | |
6354 | ||
6355 | static int | |
7ff120b4 | 6356 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6357 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6358 | { |
136821d9 SM |
6359 | displaced_debug_printf ("copying undefined insn %.8lx", |
6360 | (unsigned long) insn); | |
cca44b1b JB |
6361 | |
6362 | dsc->modinsn[0] = insn; | |
6363 | ||
6364 | return 0; | |
6365 | } | |
6366 | ||
34518530 YQ |
6367 | static int |
6368 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 6369 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6370 | { |
6371 | ||
136821d9 SM |
6372 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
6373 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
6374 | |
6375 | dsc->modinsn[0] = insn1; | |
6376 | dsc->modinsn[1] = insn2; | |
6377 | dsc->numinsns = 2; | |
6378 | ||
6379 | return 0; | |
6380 | } | |
6381 | ||
cca44b1b JB |
6382 | /* Copy unpredictable instructions. */ |
6383 | ||
6384 | static int | |
7ff120b4 | 6385 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6386 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6387 | { |
136821d9 SM |
6388 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
6389 | (unsigned long) insn); | |
cca44b1b JB |
6390 | |
6391 | dsc->modinsn[0] = insn; | |
6392 | ||
6393 | return 0; | |
6394 | } | |
6395 | ||
6396 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
6397 | the presentation in the ARM ARM. */ | |
6398 | ||
6399 | static int | |
7ff120b4 YQ |
6400 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
6401 | struct regcache *regs, | |
1152d984 | 6402 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6403 | { |
6404 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
6405 | unsigned int rn = bits (insn, 16, 19); | |
6406 | ||
2f924de6 | 6407 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 6408 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 6409 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 6410 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 6411 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 6412 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 6413 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
6414 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
6415 | dsc); | |
cca44b1b | 6416 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 6417 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6418 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 6419 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
6420 | else if ((op1 & 0x77) == 0x51) |
6421 | { | |
6422 | if (rn != 0xf) | |
7ff120b4 | 6423 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 6424 | else |
7ff120b4 | 6425 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6426 | } |
6427 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 6428 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
6429 | else if (op1 == 0x57) |
6430 | switch (op2) | |
6431 | { | |
7ff120b4 YQ |
6432 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
6433 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
6434 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
6435 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
6436 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
6437 | } |
6438 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 6439 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6440 | else if ((op2 & 0x1) == 0x0) |
6441 | switch (op1 & ~0x80) | |
6442 | { | |
6443 | case 0x61: | |
7ff120b4 | 6444 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6445 | case 0x65: |
7ff120b4 | 6446 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 6447 | case 0x71: case 0x75: |
dda83cd7 | 6448 | /* pld/pldw reg. */ |
7ff120b4 | 6449 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6450 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 6451 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 6452 | default: |
7ff120b4 | 6453 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6454 | } |
6455 | else | |
7ff120b4 | 6456 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
6457 | } |
6458 | ||
6459 | static int | |
7ff120b4 YQ |
6460 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
6461 | struct regcache *regs, | |
1152d984 | 6462 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6463 | { |
6464 | if (bit (insn, 27) == 0) | |
7ff120b4 | 6465 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6466 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
6467 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
6468 | { | |
6469 | case 0x0: case 0x2: | |
7ff120b4 | 6470 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
6471 | |
6472 | case 0x1: case 0x3: | |
7ff120b4 | 6473 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
6474 | |
6475 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 6476 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6477 | |
6478 | case 0x8: | |
6479 | switch ((insn & 0xe00000) >> 21) | |
6480 | { | |
6481 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
6482 | /* stc/stc2. */ | |
7ff120b4 | 6483 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6484 | |
6485 | case 0x2: | |
7ff120b4 | 6486 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
6487 | |
6488 | default: | |
7ff120b4 | 6489 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6490 | } |
6491 | ||
6492 | case 0x9: | |
6493 | { | |
6494 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
6495 | switch ((insn & 0xe00000) >> 21) | |
6496 | { | |
6497 | case 0x1: case 0x3: | |
6498 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
6499 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
6500 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
6501 | |
6502 | case 0x2: | |
7ff120b4 | 6503 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6504 | |
6505 | case 0x4: case 0x5: case 0x6: case 0x7: | |
6506 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
6507 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
6508 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
6509 | |
6510 | default: | |
7ff120b4 | 6511 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6512 | } |
6513 | } | |
6514 | ||
6515 | case 0xa: | |
7ff120b4 | 6516 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
6517 | |
6518 | case 0xb: | |
6519 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 6520 | /* ldc/ldc2 lit. */ |
7ff120b4 | 6521 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6522 | else |
7ff120b4 | 6523 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6524 | |
6525 | case 0xc: | |
6526 | if (bit (insn, 4)) | |
7ff120b4 | 6527 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6528 | else |
7ff120b4 | 6529 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6530 | |
6531 | case 0xd: | |
6532 | if (bit (insn, 4)) | |
7ff120b4 | 6533 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6534 | else |
7ff120b4 | 6535 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6536 | |
6537 | default: | |
7ff120b4 | 6538 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6539 | } |
6540 | } | |
6541 | ||
6542 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
6543 | ||
6544 | static int | |
7ff120b4 YQ |
6545 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
6546 | struct regcache *regs, | |
1152d984 | 6547 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6548 | { |
6549 | unsigned int op2 = bits (insn, 4, 6); | |
6550 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
6551 | |
6552 | switch (op2) | |
6553 | { | |
6554 | case 0x0: | |
7ff120b4 | 6555 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
6556 | |
6557 | case 0x1: | |
6558 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 6559 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6560 | else if (op == 0x3) |
7ff120b4 | 6561 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 6562 | else |
7ff120b4 | 6563 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6564 | |
6565 | case 0x2: | |
6566 | if (op == 0x1) | |
dda83cd7 | 6567 | /* Not really supported. */ |
7ff120b4 | 6568 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 6569 | else |
7ff120b4 | 6570 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6571 | |
6572 | case 0x3: | |
6573 | if (op == 0x1) | |
7ff120b4 | 6574 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 6575 | regs, dsc); /* blx register. */ |
cca44b1b | 6576 | else |
7ff120b4 | 6577 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6578 | |
6579 | case 0x5: | |
7ff120b4 | 6580 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
6581 | |
6582 | case 0x7: | |
6583 | if (op == 0x1) | |
7ff120b4 | 6584 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 6585 | else if (op == 0x3) |
dda83cd7 | 6586 | /* Not really supported. */ |
7ff120b4 | 6587 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 6588 | /* Fall through. */ |
cca44b1b JB |
6589 | |
6590 | default: | |
7ff120b4 | 6591 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6592 | } |
6593 | } | |
6594 | ||
6595 | static int | |
7ff120b4 YQ |
6596 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
6597 | struct regcache *regs, | |
1152d984 | 6598 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6599 | { |
6600 | if (bit (insn, 25)) | |
6601 | switch (bits (insn, 20, 24)) | |
6602 | { | |
6603 | case 0x10: | |
7ff120b4 | 6604 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
6605 | |
6606 | case 0x14: | |
7ff120b4 | 6607 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
6608 | |
6609 | case 0x12: case 0x16: | |
7ff120b4 | 6610 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
6611 | |
6612 | default: | |
7ff120b4 | 6613 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6614 | } |
6615 | else | |
6616 | { | |
6617 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
6618 | ||
6619 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 6620 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6621 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 6622 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6623 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 6624 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 6625 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 6626 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 6627 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 6628 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 6629 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 6630 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 6631 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 6632 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
6633 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
6634 | dsc); | |
cca44b1b JB |
6635 | } |
6636 | ||
6637 | /* Should be unreachable. */ | |
6638 | return 1; | |
6639 | } | |
6640 | ||
6641 | static int | |
7ff120b4 YQ |
6642 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
6643 | struct regcache *regs, | |
1152d984 | 6644 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6645 | { |
6646 | int a = bit (insn, 25), b = bit (insn, 4); | |
6647 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
6648 | |
6649 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
6650 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 6651 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
6652 | else if ((!a && (op1 & 0x17) == 0x02) |
6653 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 6654 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
6655 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
6656 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 6657 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
6658 | else if ((!a && (op1 & 0x17) == 0x03) |
6659 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 6660 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
6661 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
6662 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 6663 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
6664 | else if ((!a && (op1 & 0x17) == 0x06) |
6665 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 6666 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
6667 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
6668 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 6669 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
6670 | else if ((!a && (op1 & 0x17) == 0x07) |
6671 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 6672 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
6673 | |
6674 | /* Should be unreachable. */ | |
6675 | return 1; | |
6676 | } | |
6677 | ||
6678 | static int | |
7ff120b4 | 6679 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6680 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6681 | { |
6682 | switch (bits (insn, 20, 24)) | |
6683 | { | |
6684 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 6685 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
6686 | |
6687 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 6688 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
6689 | |
6690 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
6691 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 6692 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
6693 | "decode/pack/unpack/saturate/reverse", dsc); |
6694 | ||
6695 | case 0x18: | |
6696 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
6697 | { | |
6698 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 6699 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 6700 | else |
7ff120b4 | 6701 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
6702 | } |
6703 | else | |
7ff120b4 | 6704 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6705 | |
6706 | case 0x1a: case 0x1b: | |
6707 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6708 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 6709 | else |
7ff120b4 | 6710 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6711 | |
6712 | case 0x1c: case 0x1d: | |
6713 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
6714 | { | |
6715 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 6716 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 6717 | else |
7ff120b4 | 6718 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
6719 | } |
6720 | else | |
7ff120b4 | 6721 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6722 | |
6723 | case 0x1e: case 0x1f: | |
6724 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6725 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 6726 | else |
7ff120b4 | 6727 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6728 | } |
6729 | ||
6730 | /* Should be unreachable. */ | |
6731 | return 1; | |
6732 | } | |
6733 | ||
6734 | static int | |
615234c1 | 6735 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 6736 | struct regcache *regs, |
1152d984 | 6737 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6738 | { |
6739 | if (bit (insn, 25)) | |
7ff120b4 | 6740 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 6741 | else |
7ff120b4 | 6742 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6743 | } |
6744 | ||
6745 | static int | |
7ff120b4 YQ |
6746 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
6747 | struct regcache *regs, | |
1152d984 | 6748 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6749 | { |
6750 | unsigned int opcode = bits (insn, 20, 24); | |
6751 | ||
6752 | switch (opcode) | |
6753 | { | |
6754 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 6755 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
6756 | |
6757 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
6758 | case 0x12: case 0x16: | |
7ff120b4 | 6759 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
6760 | |
6761 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
6762 | case 0x13: case 0x17: | |
7ff120b4 | 6763 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
6764 | |
6765 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6766 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6767 | /* Note: no writeback for these instructions. Bit 25 will always be | |
6768 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 6769 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6770 | } |
6771 | ||
6772 | /* Should be unreachable. */ | |
6773 | return 1; | |
6774 | } | |
6775 | ||
34518530 YQ |
6776 | /* Decode shifted register instructions. */ |
6777 | ||
6778 | static int | |
6779 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
6780 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6781 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6782 | { |
6783 | /* PC is only allowed to be used in instruction MOV. */ | |
6784 | ||
6785 | unsigned int op = bits (insn1, 5, 8); | |
6786 | unsigned int rn = bits (insn1, 0, 3); | |
6787 | ||
6788 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
6789 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
6790 | else | |
6791 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6792 | "dp (shift reg)", dsc); | |
6793 | } | |
6794 | ||
6795 | ||
6796 | /* Decode extension register load/store. Exactly the same as | |
6797 | arm_decode_ext_reg_ld_st. */ | |
6798 | ||
6799 | static int | |
6800 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
6801 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6802 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6803 | { |
6804 | unsigned int opcode = bits (insn1, 4, 8); | |
6805 | ||
6806 | switch (opcode) | |
6807 | { | |
6808 | case 0x04: case 0x05: | |
6809 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6810 | "vfp/neon vmov", dsc); | |
6811 | ||
6812 | case 0x08: case 0x0c: /* 01x00 */ | |
6813 | case 0x0a: case 0x0e: /* 01x10 */ | |
6814 | case 0x12: case 0x16: /* 10x10 */ | |
6815 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6816 | "vfp/neon vstm/vpush", dsc); | |
6817 | ||
6818 | case 0x09: case 0x0d: /* 01x01 */ | |
6819 | case 0x0b: case 0x0f: /* 01x11 */ | |
6820 | case 0x13: case 0x17: /* 10x11 */ | |
6821 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6822 | "vfp/neon vldm/vpop", dsc); | |
6823 | ||
6824 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6825 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6826 | "vstr", dsc); | |
6827 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6828 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
6829 | } | |
6830 | ||
6831 | /* Should be unreachable. */ | |
6832 | return 1; | |
6833 | } | |
6834 | ||
cca44b1b | 6835 | static int |
12545665 | 6836 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6837 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6838 | { |
6839 | unsigned int op1 = bits (insn, 20, 25); | |
6840 | int op = bit (insn, 4); | |
6841 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
6842 | |
6843 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 6844 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6845 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
6846 | && (coproc & 0xe) != 0xa) | |
6847 | /* stc/stc2. */ | |
7ff120b4 | 6848 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6849 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
6850 | && (coproc & 0xe) != 0xa) | |
6851 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 6852 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6853 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 6854 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 6855 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 6856 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 6857 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6858 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 6859 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6860 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6861 | else if ((op1 & 0x30) == 0x20 && !op) |
6862 | { | |
6863 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 6864 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 6865 | else |
7ff120b4 | 6866 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6867 | } |
6868 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 6869 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 6870 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6871 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6872 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6873 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6874 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 6875 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 6876 | else |
7ff120b4 | 6877 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
6878 | } |
6879 | ||
34518530 YQ |
6880 | static int |
6881 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
6882 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6883 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6884 | { |
6885 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
6886 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
6887 | unsigned int bit_9 = bit (insn1, 9); | |
6888 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
6889 | |
6890 | if (bit_9 == 0) | |
6891 | { | |
6892 | if (bit_5_8 == 2) | |
6893 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6894 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
6895 | dsc); | |
6896 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
6897 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
6898 | else | |
6899 | { | |
6900 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
6901 | if ((coproc & 0xe) == 0xa) | |
6902 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
6903 | dsc); | |
6904 | else /* coproc is not 101x. */ | |
6905 | { | |
6906 | if (bit_4 == 0) /* STC/STC2. */ | |
6907 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6908 | "stc/stc2", dsc); | |
405feb71 | 6909 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
6910 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
6911 | regs, dsc); | |
6912 | } | |
6913 | } | |
6914 | } | |
6915 | else | |
6916 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
6917 | ||
6918 | return 0; | |
6919 | } | |
6920 | ||
6921 | static void | |
6922 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6923 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
6924 | { |
6925 | /* ADR Rd, #imm | |
6926 | ||
6927 | Rewrite as: | |
6928 | ||
6929 | Preparation: Rd <- PC | |
6930 | Insn: ADD Rd, #imm | |
6931 | Cleanup: Null. | |
6932 | */ | |
6933 | ||
6934 | /* Rd <- PC */ | |
6935 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6936 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
6937 | } | |
6938 | ||
6939 | static int | |
6940 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6941 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
6942 | int rd, unsigned int imm) |
6943 | { | |
6944 | ||
6945 | /* Encoding T2: ADDS Rd, #imm */ | |
6946 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
6947 | ||
6948 | install_pc_relative (gdbarch, regs, dsc, rd); | |
6949 | ||
6950 | return 0; | |
6951 | } | |
6952 | ||
6953 | static int | |
6954 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
6955 | struct regcache *regs, | |
1152d984 | 6956 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6957 | { |
6958 | unsigned int rd = bits (insn, 8, 10); | |
6959 | unsigned int imm8 = bits (insn, 0, 7); | |
6960 | ||
136821d9 SM |
6961 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
6962 | rd, imm8, insn); | |
34518530 YQ |
6963 | |
6964 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
6965 | } | |
6966 | ||
6967 | static int | |
6968 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
6969 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6970 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6971 | { |
6972 | unsigned int rd = bits (insn2, 8, 11); | |
6973 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
6974 | extract raw immediate encoding rather than computing immediate. When | |
6975 | generating ADD or SUB instruction, we can simply perform OR operation to | |
6976 | set immediate into ADD. */ | |
6977 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
6978 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
6979 | ||
136821d9 SM |
6980 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
6981 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
6982 | |
6983 | if (bit (insn1, 7)) /* Encoding T2 */ | |
6984 | { | |
6985 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
6986 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
6987 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6988 | } | |
6989 | else /* Encoding T3 */ | |
6990 | { | |
6991 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
6992 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
6993 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6994 | } | |
6995 | dsc->numinsns = 2; | |
6996 | ||
6997 | install_pc_relative (gdbarch, regs, dsc, rd); | |
6998 | ||
6999 | return 0; | |
7000 | } | |
7001 | ||
7002 | static int | |
615234c1 | 7003 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7004 | struct regcache *regs, |
1152d984 | 7005 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7006 | { |
7007 | unsigned int rt = bits (insn1, 8, 10); | |
7008 | unsigned int pc; | |
7009 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7010 | |
7011 | /* LDR Rd, #imm8 | |
7012 | ||
7013 | Rwrite as: | |
7014 | ||
7015 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7016 | ||
7017 | Insn: LDR R0, [R2, R3]; | |
7018 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7019 | ||
136821d9 | 7020 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7021 | |
7022 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7023 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7024 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7025 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7026 | /* The assembler calculates the required value of the offset from the | |
7027 | Align(PC,4) value of this instruction to the label. */ | |
7028 | pc = pc & 0xfffffffc; | |
7029 | ||
7030 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7031 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7032 | ||
7033 | dsc->rd = rt; | |
7034 | dsc->u.ldst.xfersize = 4; | |
7035 | dsc->u.ldst.rn = 0; | |
7036 | dsc->u.ldst.immed = 0; | |
7037 | dsc->u.ldst.writeback = 0; | |
7038 | dsc->u.ldst.restore_r4 = 0; | |
7039 | ||
7040 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7041 | ||
7042 | dsc->cleanup = &cleanup_load; | |
7043 | ||
7044 | return 0; | |
7045 | } | |
7046 | ||
405feb71 | 7047 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
7048 | |
7049 | static int | |
7050 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
7051 | struct regcache *regs, | |
1152d984 | 7052 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7053 | { |
7054 | int non_zero = bit (insn1, 11); | |
7055 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
7056 | CORE_ADDR from = dsc->insn_addr; | |
7057 | int rn = bits (insn1, 0, 2); | |
7058 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
7059 | ||
7060 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
7061 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
7062 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
7063 | condition is false, let it be, cleanup_branch will do nothing. */ | |
7064 | if (dsc->u.branch.cond) | |
7065 | { | |
7066 | dsc->u.branch.cond = INST_AL; | |
7067 | dsc->u.branch.dest = from + 4 + imm5; | |
7068 | } | |
7069 | else | |
7070 | dsc->u.branch.dest = from + 2; | |
7071 | ||
7072 | dsc->u.branch.link = 0; | |
7073 | dsc->u.branch.exchange = 0; | |
7074 | ||
136821d9 SM |
7075 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
7076 | non_zero ? "cbnz" : "cbz", | |
7077 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
7078 | |
7079 | dsc->modinsn[0] = THUMB_NOP; | |
7080 | ||
7081 | dsc->cleanup = &cleanup_branch; | |
7082 | return 0; | |
7083 | } | |
7084 | ||
7085 | /* Copy Table Branch Byte/Halfword */ | |
7086 | static int | |
7087 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7088 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7089 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7090 | { |
7091 | ULONGEST rn_val, rm_val; | |
7092 | int is_tbh = bit (insn2, 4); | |
7093 | CORE_ADDR halfwords = 0; | |
7094 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7095 | ||
7096 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7097 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7098 | ||
7099 | if (is_tbh) | |
7100 | { | |
7101 | gdb_byte buf[2]; | |
7102 | ||
7103 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7104 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7105 | } | |
7106 | else | |
7107 | { | |
7108 | gdb_byte buf[1]; | |
7109 | ||
7110 | target_read_memory (rn_val + rm_val, buf, 1); | |
7111 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7112 | } | |
7113 | ||
136821d9 SM |
7114 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
7115 | is_tbh ? "tbh" : "tbb", | |
7116 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7117 | (unsigned int) halfwords); | |
34518530 YQ |
7118 | |
7119 | dsc->u.branch.cond = INST_AL; | |
7120 | dsc->u.branch.link = 0; | |
7121 | dsc->u.branch.exchange = 0; | |
7122 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7123 | ||
7124 | dsc->cleanup = &cleanup_branch; | |
7125 | ||
7126 | return 0; | |
7127 | } | |
7128 | ||
7129 | static void | |
7130 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7131 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7132 | { |
7133 | /* PC <- r7 */ | |
7134 | int val = displaced_read_reg (regs, dsc, 7); | |
7135 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7136 | ||
7137 | /* r7 <- r8 */ | |
7138 | val = displaced_read_reg (regs, dsc, 8); | |
7139 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7140 | ||
7141 | /* r8 <- tmp[0] */ | |
7142 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7143 | ||
7144 | } | |
7145 | ||
7146 | static int | |
615234c1 | 7147 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7148 | struct regcache *regs, |
1152d984 | 7149 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7150 | { |
7151 | dsc->u.block.regmask = insn1 & 0x00ff; | |
7152 | ||
7153 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
7154 | to : | |
7155 | ||
7156 | (1) register list is full, that is, r0-r7 are used. | |
7157 | Prepare: tmp[0] <- r8 | |
7158 | ||
7159 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
7160 | MOV r8, r7; Move value of r7 to r8; | |
7161 | POP {r7}; Store PC value into r7. | |
7162 | ||
7163 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
7164 | ||
7165 | (2) register list is not full, supposing there are N registers in | |
7166 | register list (except PC, 0 <= N <= 7). | |
7167 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
7168 | ||
7169 | POP {r0, r1, ...., rN}; | |
7170 | ||
7171 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
7172 | from tmp[] properly. | |
7173 | */ | |
136821d9 SM |
7174 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
7175 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
7176 | |
7177 | if (dsc->u.block.regmask == 0xff) | |
7178 | { | |
7179 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
7180 | ||
7181 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
7182 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
7183 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
7184 | ||
7185 | dsc->numinsns = 3; | |
7186 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
7187 | } | |
7188 | else | |
7189 | { | |
5f661e03 | 7190 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
7191 | unsigned int i; |
7192 | unsigned int new_regmask; | |
34518530 YQ |
7193 | |
7194 | for (i = 0; i < num_in_list + 1; i++) | |
7195 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7196 | ||
7197 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
7198 | ||
136821d9 SM |
7199 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
7200 | "modified list %.4x", | |
7201 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7202 | |
7203 | dsc->u.block.regmask |= 0x8000; | |
7204 | dsc->u.block.writeback = 0; | |
7205 | dsc->u.block.cond = INST_AL; | |
7206 | ||
7207 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
7208 | ||
7209 | dsc->cleanup = &cleanup_block_load_pc; | |
7210 | } | |
7211 | ||
7212 | return 0; | |
7213 | } | |
7214 | ||
7215 | static void | |
7216 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7217 | struct regcache *regs, | |
1152d984 | 7218 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7219 | { |
7220 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
7221 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
7222 | int err = 0; | |
7223 | ||
7224 | /* 16-bit thumb instructions. */ | |
7225 | switch (op_bit_12_15) | |
7226 | { | |
7227 | /* Shift (imme), add, subtract, move and compare. */ | |
7228 | case 0: case 1: case 2: case 3: | |
7229 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7230 | "shift/add/sub/mov/cmp", | |
7231 | dsc); | |
7232 | break; | |
7233 | case 4: | |
7234 | switch (op_bit_10_11) | |
7235 | { | |
7236 | case 0: /* Data-processing */ | |
7237 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7238 | "data-processing", | |
7239 | dsc); | |
7240 | break; | |
7241 | case 1: /* Special data instructions and branch and exchange. */ | |
7242 | { | |
7243 | unsigned short op = bits (insn1, 7, 9); | |
7244 | if (op == 6 || op == 7) /* BX or BLX */ | |
7245 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
7246 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
7247 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
7248 | else | |
7249 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
7250 | dsc); | |
7251 | } | |
7252 | break; | |
7253 | default: /* LDR (literal) */ | |
7254 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
7255 | } | |
7256 | break; | |
7257 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
7258 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
7259 | break; | |
7260 | case 10: | |
7261 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
7262 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
7263 | else /* Generate SP-relative address */ | |
7264 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
7265 | break; | |
7266 | case 11: /* Misc 16-bit instructions */ | |
7267 | { | |
7268 | switch (bits (insn1, 8, 11)) | |
7269 | { | |
7270 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
7271 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
7272 | break; | |
7273 | case 12: case 13: /* POP */ | |
7274 | if (bit (insn1, 8)) /* PC is in register list. */ | |
7275 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
7276 | else | |
7277 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
7278 | break; | |
7279 | case 15: /* If-Then, and hints */ | |
7280 | if (bits (insn1, 0, 3)) | |
7281 | /* If-Then makes up to four following instructions conditional. | |
7282 | IT instruction itself is not conditional, so handle it as a | |
7283 | common unmodified instruction. */ | |
7284 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
7285 | dsc); | |
7286 | else | |
7287 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
7288 | break; | |
7289 | default: | |
7290 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
7291 | } | |
7292 | } | |
7293 | break; | |
7294 | case 12: | |
7295 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
7296 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
7297 | else /* Load multiple registers */ | |
7298 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
7299 | break; | |
7300 | case 13: /* Conditional branch and supervisor call */ | |
7301 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
7302 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7303 | else | |
7304 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
7305 | break; | |
7306 | case 14: /* Unconditional branch */ | |
7307 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7308 | break; | |
7309 | default: | |
7310 | err = 1; | |
7311 | } | |
7312 | ||
7313 | if (err) | |
7314 | internal_error (__FILE__, __LINE__, | |
7315 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
7316 | } | |
7317 | ||
7318 | static int | |
7319 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
7320 | uint16_t insn1, uint16_t insn2, | |
7321 | struct regcache *regs, | |
1152d984 | 7322 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7323 | { |
7324 | int rt = bits (insn2, 12, 15); | |
7325 | int rn = bits (insn1, 0, 3); | |
7326 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
7327 | |
7328 | switch (bits (insn1, 5, 6)) | |
7329 | { | |
7330 | case 0: /* Load byte and memory hints */ | |
7331 | if (rt == 0xf) /* PLD/PLI */ | |
7332 | { | |
7333 | if (rn == 0xf) | |
7334 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
7335 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
7336 | else | |
7337 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7338 | "pli/pld", dsc); | |
7339 | } | |
7340 | else | |
7341 | { | |
7342 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
7343 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7344 | 1); | |
7345 | else | |
7346 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7347 | "ldrb{reg, immediate}/ldrbt", | |
7348 | dsc); | |
7349 | } | |
7350 | ||
7351 | break; | |
7352 | case 1: /* Load halfword and memory hints. */ | |
7353 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
7354 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7355 | "pld/unalloc memhint", dsc); | |
7356 | else | |
7357 | { | |
7358 | if (rn == 0xf) | |
7359 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7360 | 2); | |
7361 | else | |
7362 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7363 | "ldrh/ldrht", dsc); | |
7364 | } | |
7365 | break; | |
7366 | case 2: /* Load word */ | |
7367 | { | |
7368 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
7369 | ||
7370 | if (rn == 0xf) | |
7371 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
7372 | else if (op1 == 0x1) /* Encoding T3 */ | |
7373 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
7374 | 0, 1); | |
7375 | else /* op1 == 0x0 */ | |
7376 | { | |
7377 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
7378 | /* LDR (immediate) */ | |
7379 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7380 | dsc, bit (insn2, 8), 1); | |
7381 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
7382 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7383 | "ldrt", dsc); | |
7384 | else | |
7385 | /* LDR (register) */ | |
7386 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7387 | dsc, 0, 0); | |
7388 | } | |
7389 | break; | |
7390 | } | |
7391 | default: | |
7392 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7393 | break; | |
7394 | } | |
7395 | return 0; | |
7396 | } | |
7397 | ||
7398 | static void | |
7399 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7400 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7401 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7402 | { |
7403 | int err = 0; | |
7404 | unsigned short op = bit (insn2, 15); | |
7405 | unsigned int op1 = bits (insn1, 11, 12); | |
7406 | ||
7407 | switch (op1) | |
7408 | { | |
7409 | case 1: | |
7410 | { | |
7411 | switch (bits (insn1, 9, 10)) | |
7412 | { | |
7413 | case 0: | |
7414 | if (bit (insn1, 6)) | |
7415 | { | |
405feb71 | 7416 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
7417 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
7418 | && bits (insn2, 5, 7) == 0) | |
7419 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
7420 | dsc); | |
7421 | else | |
7422 | /* PC is not allowed to use in load/store {dual, exclusive} | |
7423 | instructions. */ | |
7424 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7425 | "load/store dual/ex", dsc); | |
7426 | } | |
7427 | else /* load/store multiple */ | |
7428 | { | |
7429 | switch (bits (insn1, 7, 8)) | |
7430 | { | |
7431 | case 0: case 3: /* SRS, RFE */ | |
7432 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7433 | "srs/rfe", dsc); | |
7434 | break; | |
7435 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
7436 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
7437 | break; | |
7438 | } | |
7439 | } | |
7440 | break; | |
7441 | ||
7442 | case 1: | |
7443 | /* Data-processing (shift register). */ | |
7444 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
7445 | dsc); | |
7446 | break; | |
7447 | default: /* Coprocessor instructions. */ | |
7448 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7449 | break; | |
7450 | } | |
7451 | break; | |
7452 | } | |
7453 | case 2: /* op1 = 2 */ | |
7454 | if (op) /* Branch and misc control. */ | |
7455 | { | |
7456 | if (bit (insn2, 14) /* BLX/BL */ | |
7457 | || bit (insn2, 12) /* Unconditional branch */ | |
7458 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
7459 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
7460 | else | |
7461 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7462 | "misc ctrl", dsc); | |
7463 | } | |
7464 | else | |
7465 | { | |
7466 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
7467 | { | |
b926417a | 7468 | int dp_op = bits (insn1, 4, 8); |
34518530 | 7469 | int rn = bits (insn1, 0, 3); |
b926417a | 7470 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
7471 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
7472 | regs, dsc); | |
7473 | else | |
7474 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7475 | "dp/pb", dsc); | |
7476 | } | |
405feb71 | 7477 | else /* Data processing (modified immediate) */ |
34518530 YQ |
7478 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
7479 | "dp/mi", dsc); | |
7480 | } | |
7481 | break; | |
7482 | case 3: /* op1 = 3 */ | |
7483 | switch (bits (insn1, 9, 10)) | |
7484 | { | |
7485 | case 0: | |
7486 | if (bit (insn1, 4)) | |
7487 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
7488 | regs, dsc); | |
7489 | else /* NEON Load/Store and Store single data item */ | |
7490 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7491 | "neon elt/struct load/store", | |
7492 | dsc); | |
7493 | break; | |
7494 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
7495 | switch (bits (insn1, 7, 8)) | |
7496 | { | |
7497 | case 0: case 1: /* Data processing (register) */ | |
7498 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7499 | "dp(reg)", dsc); | |
7500 | break; | |
7501 | case 2: /* Multiply and absolute difference */ | |
7502 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7503 | "mul/mua/diff", dsc); | |
7504 | break; | |
7505 | case 3: /* Long multiply and divide */ | |
7506 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7507 | "lmul/lmua", dsc); | |
7508 | break; | |
7509 | } | |
7510 | break; | |
7511 | default: /* Coprocessor instructions */ | |
7512 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7513 | break; | |
7514 | } | |
7515 | break; | |
7516 | default: | |
7517 | err = 1; | |
7518 | } | |
7519 | ||
7520 | if (err) | |
7521 | internal_error (__FILE__, __LINE__, | |
7522 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
7523 | ||
7524 | } | |
7525 | ||
b434a28f YQ |
7526 | static void |
7527 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 7528 | struct regcache *regs, |
1152d984 | 7529 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 7530 | { |
34518530 YQ |
7531 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7532 | uint16_t insn1 | |
7533 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
7534 | ||
136821d9 SM |
7535 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
7536 | insn1, (unsigned long) from); | |
34518530 YQ |
7537 | |
7538 | dsc->is_thumb = 1; | |
7539 | dsc->insn_size = thumb_insn_size (insn1); | |
7540 | if (thumb_insn_size (insn1) == 4) | |
7541 | { | |
7542 | uint16_t insn2 | |
7543 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
7544 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
7545 | } | |
7546 | else | |
7547 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
7548 | } |
7549 | ||
cca44b1b | 7550 | void |
b434a28f YQ |
7551 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
7552 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 7553 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7554 | { |
7555 | int err = 0; | |
b434a28f YQ |
7556 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7557 | uint32_t insn; | |
cca44b1b JB |
7558 | |
7559 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
7560 | here and override below if/when necessary. */ | |
7561 | dsc->numinsns = 1; | |
7562 | dsc->insn_addr = from; | |
7563 | dsc->scratch_base = to; | |
7564 | dsc->cleanup = NULL; | |
7565 | dsc->wrote_to_pc = 0; | |
7566 | ||
b434a28f | 7567 | if (!displaced_in_arm_mode (regs)) |
12545665 | 7568 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 7569 | |
4db71c0b YQ |
7570 | dsc->is_thumb = 0; |
7571 | dsc->insn_size = 4; | |
b434a28f | 7572 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
7573 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
7574 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 7575 | |
cca44b1b | 7576 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 7577 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7578 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
7579 | { | |
7580 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 7581 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7582 | break; |
7583 | ||
7584 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 7585 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7586 | break; |
7587 | ||
7588 | case 0x7: | |
7ff120b4 | 7589 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
7590 | break; |
7591 | ||
7592 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 7593 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7594 | break; |
7595 | ||
7596 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 7597 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7598 | break; |
7599 | } | |
7600 | ||
7601 | if (err) | |
7602 | internal_error (__FILE__, __LINE__, | |
7603 | _("arm_process_displaced_insn: Instruction decode error")); | |
7604 | } | |
7605 | ||
7606 | /* Actually set up the scratch space for a displaced instruction. */ | |
7607 | ||
7608 | void | |
7609 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
7610 | CORE_ADDR to, |
7611 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
7612 | { |
7613 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4db71c0b | 7614 | unsigned int i, len, offset; |
cca44b1b | 7615 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 7616 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 7617 | const gdb_byte *bkp_insn; |
cca44b1b | 7618 | |
4db71c0b | 7619 | offset = 0; |
cca44b1b JB |
7620 | /* Poke modified instruction(s). */ |
7621 | for (i = 0; i < dsc->numinsns; i++) | |
7622 | { | |
136821d9 SM |
7623 | if (size == 4) |
7624 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
7625 | dsc->modinsn[i], (unsigned long) to + offset); | |
7626 | else if (size == 2) | |
7627 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
7628 | (unsigned short) dsc->modinsn[i], | |
7629 | (unsigned long) to + offset); | |
4db71c0b | 7630 | |
4db71c0b YQ |
7631 | write_memory_unsigned_integer (to + offset, size, |
7632 | byte_order_for_code, | |
cca44b1b | 7633 | dsc->modinsn[i]); |
4db71c0b YQ |
7634 | offset += size; |
7635 | } | |
7636 | ||
7637 | /* Choose the correct breakpoint instruction. */ | |
7638 | if (dsc->is_thumb) | |
7639 | { | |
7640 | bkp_insn = tdep->thumb_breakpoint; | |
7641 | len = tdep->thumb_breakpoint_size; | |
7642 | } | |
7643 | else | |
7644 | { | |
7645 | bkp_insn = tdep->arm_breakpoint; | |
7646 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
7647 | } |
7648 | ||
7649 | /* Put breakpoint afterwards. */ | |
4db71c0b | 7650 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 7651 | |
136821d9 SM |
7652 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
7653 | paddress (gdbarch, to)); | |
cca44b1b JB |
7654 | } |
7655 | ||
cca44b1b JB |
7656 | /* Entry point for cleaning things up after a displaced instruction has been |
7657 | single-stepped. */ | |
7658 | ||
7659 | void | |
7660 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 7661 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
7662 | CORE_ADDR from, CORE_ADDR to, |
7663 | struct regcache *regs) | |
7664 | { | |
1152d984 SM |
7665 | arm_displaced_step_copy_insn_closure *dsc |
7666 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 7667 | |
cca44b1b JB |
7668 | if (dsc->cleanup) |
7669 | dsc->cleanup (gdbarch, regs, dsc); | |
7670 | ||
7671 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
7672 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
7673 | dsc->insn_addr + dsc->insn_size); | |
7674 | ||
cca44b1b JB |
7675 | } |
7676 | ||
7677 | #include "bfd-in2.h" | |
7678 | #include "libcoff.h" | |
7679 | ||
7680 | static int | |
7681 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
7682 | { | |
e47ad6c0 YQ |
7683 | gdb_disassembler *di |
7684 | = static_cast<gdb_disassembler *>(info->application_data); | |
7685 | struct gdbarch *gdbarch = di->arch (); | |
9779414d DJ |
7686 | |
7687 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
7688 | { |
7689 | static asymbol *asym; | |
7690 | static combined_entry_type ce; | |
7691 | static struct coff_symbol_struct csym; | |
7692 | static struct bfd fake_bfd; | |
7693 | static bfd_target fake_target; | |
7694 | ||
7695 | if (csym.native == NULL) | |
7696 | { | |
7697 | /* Create a fake symbol vector containing a Thumb symbol. | |
7698 | This is solely so that the code in print_insn_little_arm() | |
7699 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
7700 | the presence of a Thumb symbol and switch to decoding | |
7701 | Thumb instructions. */ | |
7702 | ||
7703 | fake_target.flavour = bfd_target_coff_flavour; | |
7704 | fake_bfd.xvec = &fake_target; | |
7705 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
7706 | csym.native = &ce; | |
7707 | csym.symbol.the_bfd = &fake_bfd; | |
7708 | csym.symbol.name = "fake"; | |
7709 | asym = (asymbol *) & csym; | |
7710 | } | |
7711 | ||
7712 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
7713 | info->symbols = &asym; | |
7714 | } | |
7715 | else | |
7716 | info->symbols = NULL; | |
7717 | ||
e60eb288 YQ |
7718 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
7719 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
7720 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
7721 | the assert on the mismatch of info->mach and |
7722 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
7723 | default_print_insn. */ | |
7724 | if (current_program_space->exec_bfd () != NULL) | |
e60eb288 YQ |
7725 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
7726 | ||
6394c606 | 7727 | return default_print_insn (memaddr, info); |
cca44b1b JB |
7728 | } |
7729 | ||
7730 | /* The following define instruction sequences that will cause ARM | |
7731 | cpu's to take an undefined instruction trap. These are used to | |
7732 | signal a breakpoint to GDB. | |
7733 | ||
7734 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
7735 | modes. A different instruction is required for each mode. The ARM | |
7736 | cpu's can also be big or little endian. Thus four different | |
7737 | instructions are needed to support all cases. | |
7738 | ||
7739 | Note: ARMv4 defines several new instructions that will take the | |
7740 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
7741 | not in fact add the new instructions. The new undefined | |
7742 | instructions in ARMv4 are all instructions that had no defined | |
7743 | behaviour in earlier chips. There is no guarantee that they will | |
7744 | raise an exception, but may be treated as NOP's. In practice, it | |
7745 | may only safe to rely on instructions matching: | |
7746 | ||
7747 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
7748 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
7749 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
7750 | ||
0963b4bd | 7751 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
7752 | following use a condition predicate of ALWAYS so it is always TRUE. |
7753 | ||
7754 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
7755 | and NetBSD all use a software interrupt rather than an undefined | |
7756 | instruction to force a trap. This can be handled by by the | |
7757 | abi-specific code during establishment of the gdbarch vector. */ | |
7758 | ||
7759 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
7760 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
7761 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
7762 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
7763 | ||
948f8e3d PA |
7764 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
7765 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
7766 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
7767 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 7768 | |
cd6c3b4f YQ |
7769 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7770 | ||
d19280ad YQ |
7771 | static int |
7772 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b JB |
7773 | { |
7774 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
177321bd | 7775 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 7776 | |
9779414d | 7777 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
7778 | { |
7779 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
7780 | |
7781 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
7782 | check whether we are replacing a 32-bit instruction. */ | |
7783 | if (tdep->thumb2_breakpoint != NULL) | |
7784 | { | |
7785 | gdb_byte buf[2]; | |
d19280ad | 7786 | |
177321bd DJ |
7787 | if (target_read_memory (*pcptr, buf, 2) == 0) |
7788 | { | |
7789 | unsigned short inst1; | |
d19280ad | 7790 | |
177321bd | 7791 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 7792 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 7793 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
7794 | } |
7795 | } | |
7796 | ||
d19280ad | 7797 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
7798 | } |
7799 | else | |
d19280ad YQ |
7800 | return ARM_BP_KIND_ARM; |
7801 | ||
7802 | } | |
7803 | ||
cd6c3b4f YQ |
7804 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7805 | ||
d19280ad YQ |
7806 | static const gdb_byte * |
7807 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7808 | { | |
7809 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7810 | ||
7811 | switch (kind) | |
cca44b1b | 7812 | { |
d19280ad YQ |
7813 | case ARM_BP_KIND_ARM: |
7814 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 7815 | return tdep->arm_breakpoint; |
d19280ad YQ |
7816 | case ARM_BP_KIND_THUMB: |
7817 | *size = tdep->thumb_breakpoint_size; | |
7818 | return tdep->thumb_breakpoint; | |
7819 | case ARM_BP_KIND_THUMB2: | |
7820 | *size = tdep->thumb2_breakpoint_size; | |
7821 | return tdep->thumb2_breakpoint; | |
7822 | default: | |
7823 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
7824 | } |
7825 | } | |
7826 | ||
833b7ab5 YQ |
7827 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
7828 | ||
7829 | static int | |
7830 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
7831 | struct regcache *regcache, | |
7832 | CORE_ADDR *pcptr) | |
7833 | { | |
7834 | gdb_byte buf[4]; | |
7835 | ||
7836 | /* Check the memory pointed by PC is readable. */ | |
7837 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
7838 | { | |
7839 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
7840 | |
7841 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
7842 | &arm_get_next_pcs_ops, | |
7843 | gdbarch_byte_order (gdbarch), | |
7844 | gdbarch_byte_order_for_code (gdbarch), | |
7845 | 0, | |
7846 | regcache); | |
7847 | ||
a0ff9e1a | 7848 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
7849 | |
7850 | /* If MEMADDR is the next instruction of current pc, do the | |
7851 | software single step computation, and get the thumb mode by | |
7852 | the destination address. */ | |
a0ff9e1a | 7853 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
7854 | { |
7855 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
7856 | { | |
833b7ab5 YQ |
7857 | if (IS_THUMB_ADDR (pc)) |
7858 | { | |
7859 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
7860 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
7861 | } | |
7862 | else | |
7863 | return ARM_BP_KIND_ARM; | |
7864 | } | |
7865 | } | |
833b7ab5 YQ |
7866 | } |
7867 | ||
7868 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
7869 | } | |
7870 | ||
cca44b1b JB |
7871 | /* Extract from an array REGBUF containing the (raw) register state a |
7872 | function return value of type TYPE, and copy that, in virtual | |
7873 | format, into VALBUF. */ | |
7874 | ||
7875 | static void | |
7876 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
7877 | gdb_byte *valbuf) | |
7878 | { | |
ac7936df | 7879 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b JB |
7880 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7881 | ||
78134374 | 7882 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b JB |
7883 | { |
7884 | switch (gdbarch_tdep (gdbarch)->fp_model) | |
7885 | { | |
7886 | case ARM_FLOAT_FPA: | |
7887 | { | |
7888 | /* The value is in register F0 in internal format. We need to | |
7889 | extract the raw value and then convert it to the desired | |
7890 | internal type. */ | |
f0452268 | 7891 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 7892 | |
dca08e1f | 7893 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
7894 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
7895 | valbuf, type); | |
cca44b1b JB |
7896 | } |
7897 | break; | |
7898 | ||
7899 | case ARM_FLOAT_SOFT_FPA: | |
7900 | case ARM_FLOAT_SOFT_VFP: | |
7901 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
7902 | not using the VFP ABI code. */ | |
7903 | case ARM_FLOAT_VFP: | |
dca08e1f | 7904 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
cca44b1b | 7905 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
7906 | regs->cooked_read (ARM_A1_REGNUM + 1, |
7907 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
7908 | break; |
7909 | ||
7910 | default: | |
0963b4bd MS |
7911 | internal_error (__FILE__, __LINE__, |
7912 | _("arm_extract_return_value: " | |
7913 | "Floating point model not supported")); | |
cca44b1b JB |
7914 | break; |
7915 | } | |
7916 | } | |
78134374 SM |
7917 | else if (type->code () == TYPE_CODE_INT |
7918 | || type->code () == TYPE_CODE_CHAR | |
7919 | || type->code () == TYPE_CODE_BOOL | |
7920 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 7921 | || TYPE_IS_REFERENCE (type) |
78134374 | 7922 | || type->code () == TYPE_CODE_ENUM) |
cca44b1b | 7923 | { |
b021a221 MS |
7924 | /* If the type is a plain integer, then the access is |
7925 | straight-forward. Otherwise we have to play around a bit | |
7926 | more. */ | |
cca44b1b JB |
7927 | int len = TYPE_LENGTH (type); |
7928 | int regno = ARM_A1_REGNUM; | |
7929 | ULONGEST tmp; | |
7930 | ||
7931 | while (len > 0) | |
7932 | { | |
7933 | /* By using store_unsigned_integer we avoid having to do | |
7934 | anything special for small big-endian values. */ | |
7935 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
7936 | store_unsigned_integer (valbuf, | |
f0452268 AH |
7937 | (len > ARM_INT_REGISTER_SIZE |
7938 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 7939 | byte_order, tmp); |
f0452268 AH |
7940 | len -= ARM_INT_REGISTER_SIZE; |
7941 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
7942 | } |
7943 | } | |
7944 | else | |
7945 | { | |
7946 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
7947 | been stored to word-aligned memory and then loaded into |
7948 | registers with 32-bit load instruction(s). */ | |
cca44b1b JB |
7949 | int len = TYPE_LENGTH (type); |
7950 | int regno = ARM_A1_REGNUM; | |
f0452268 | 7951 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
7952 | |
7953 | while (len > 0) | |
7954 | { | |
dca08e1f | 7955 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 7956 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
7957 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
7958 | len -= ARM_INT_REGISTER_SIZE; | |
7959 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
7960 | } |
7961 | } | |
7962 | } | |
7963 | ||
7964 | ||
7965 | /* Will a function return an aggregate type in memory or in a | |
7966 | register? Return 0 if an aggregate type can be returned in a | |
7967 | register, 1 if it must be returned in memory. */ | |
7968 | ||
7969 | static int | |
7970 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
7971 | { | |
cca44b1b JB |
7972 | enum type_code code; |
7973 | ||
f168693b | 7974 | type = check_typedef (type); |
cca44b1b | 7975 | |
b13c8ab2 YQ |
7976 | /* Simple, non-aggregate types (ie not including vectors and |
7977 | complex) are always returned in a register (or registers). */ | |
78134374 | 7978 | code = type->code (); |
b13c8ab2 YQ |
7979 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
7980 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
7981 | return 0; | |
cca44b1b | 7982 | |
bd63c870 | 7983 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
7984 | { |
7985 | /* Vector values should be returned using ARM registers if they | |
7986 | are not over 16 bytes. */ | |
7987 | return (TYPE_LENGTH (type) > 16); | |
7988 | } | |
7989 | ||
b13c8ab2 | 7990 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
cca44b1b | 7991 | { |
b13c8ab2 YQ |
7992 | /* The AAPCS says all aggregates not larger than a word are returned |
7993 | in a register. */ | |
f0452268 | 7994 | if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE) |
b13c8ab2 YQ |
7995 | return 0; |
7996 | ||
cca44b1b JB |
7997 | return 1; |
7998 | } | |
b13c8ab2 YQ |
7999 | else |
8000 | { | |
8001 | int nRc; | |
cca44b1b | 8002 | |
b13c8ab2 YQ |
8003 | /* All aggregate types that won't fit in a register must be returned |
8004 | in memory. */ | |
f0452268 | 8005 | if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE) |
b13c8ab2 | 8006 | return 1; |
cca44b1b | 8007 | |
b13c8ab2 YQ |
8008 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8009 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8010 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8011 | offset of each addressable subfield must be zero. Note that bit |
8012 | fields are not addressable, and all addressable subfields of | |
8013 | unions always start at offset zero. | |
cca44b1b | 8014 | |
b13c8ab2 YQ |
8015 | This function is based on the behaviour of GCC 2.95.1. |
8016 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8017 | |
b13c8ab2 YQ |
8018 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8019 | parameters correctly for a function returning the following | |
8020 | structure: struct { float f;}; This should be returned in memory, | |
8021 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8022 | know of any way to detect if a function like the above has been | |
8023 | compiled with the correct calling convention. */ | |
8024 | ||
8025 | /* Assume all other aggregate types can be returned in a register. | |
8026 | Run a check for structures, unions and arrays. */ | |
8027 | nRc = 0; | |
67255d04 | 8028 | |
b13c8ab2 YQ |
8029 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8030 | { | |
8031 | int i; | |
8032 | /* Need to check if this struct/union is "integer" like. For | |
8033 | this to be true, its size must be less than or equal to | |
f0452268 | 8034 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8035 | subfield must be zero. Note that bit fields are not |
8036 | addressable, and unions always start at offset zero. If any | |
8037 | of the subfields is a floating point type, the struct/union | |
8038 | cannot be an integer type. */ | |
8039 | ||
8040 | /* For each field in the object, check: | |
8041 | 1) Is it FP? --> yes, nRc = 1; | |
8042 | 2) Is it addressable (bitpos != 0) and | |
8043 | not packed (bitsize == 0)? | |
8044 | --> yes, nRc = 1 | |
8045 | */ | |
8046 | ||
1f704f76 | 8047 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 8048 | { |
b13c8ab2 YQ |
8049 | enum type_code field_type_code; |
8050 | ||
8051 | field_type_code | |
940da03e | 8052 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
8053 | |
8054 | /* Is it a floating point type field? */ | |
8055 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
8056 | { |
8057 | nRc = 1; | |
8058 | break; | |
8059 | } | |
b13c8ab2 YQ |
8060 | |
8061 | /* If bitpos != 0, then we have to care about it. */ | |
8062 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
8063 | { | |
8064 | /* Bitfields are not addressable. If the field bitsize is | |
8065 | zero, then the field is not packed. Hence it cannot be | |
8066 | a bitfield or any other packed type. */ | |
8067 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
8068 | { | |
8069 | nRc = 1; | |
8070 | break; | |
8071 | } | |
8072 | } | |
67255d04 RE |
8073 | } |
8074 | } | |
67255d04 | 8075 | |
b13c8ab2 YQ |
8076 | return nRc; |
8077 | } | |
67255d04 RE |
8078 | } |
8079 | ||
34e8f22d RE |
8080 | /* Write into appropriate registers a function return value of type |
8081 | TYPE, given in virtual format. */ | |
8082 | ||
8083 | static void | |
b508a996 | 8084 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 8085 | const gdb_byte *valbuf) |
34e8f22d | 8086 | { |
ac7936df | 8087 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 8088 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 8089 | |
78134374 | 8090 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 8091 | { |
f0452268 | 8092 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
34e8f22d | 8093 | |
be8626e0 | 8094 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
8095 | { |
8096 | case ARM_FLOAT_FPA: | |
8097 | ||
3b2ca824 | 8098 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 8099 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
8100 | break; |
8101 | ||
fd50bc42 | 8102 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8103 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8104 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8105 | not using the VFP ABI code. */ | |
8106 | case ARM_FLOAT_VFP: | |
b66f5587 | 8107 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
b508a996 | 8108 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8109 | regs->cooked_write (ARM_A1_REGNUM + 1, |
8110 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
8111 | break; |
8112 | ||
8113 | default: | |
9b20d036 MS |
8114 | internal_error (__FILE__, __LINE__, |
8115 | _("arm_store_return_value: Floating " | |
8116 | "point model not supported")); | |
08216dd7 RE |
8117 | break; |
8118 | } | |
34e8f22d | 8119 | } |
78134374 SM |
8120 | else if (type->code () == TYPE_CODE_INT |
8121 | || type->code () == TYPE_CODE_CHAR | |
8122 | || type->code () == TYPE_CODE_BOOL | |
8123 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8124 | || TYPE_IS_REFERENCE (type) |
78134374 | 8125 | || type->code () == TYPE_CODE_ENUM) |
b508a996 RE |
8126 | { |
8127 | if (TYPE_LENGTH (type) <= 4) | |
8128 | { | |
8129 | /* Values of one word or less are zero/sign-extended and | |
8130 | returned in r0. */ | |
f0452268 | 8131 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8132 | LONGEST val = unpack_long (type, valbuf); |
8133 | ||
f0452268 | 8134 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 8135 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
8136 | } |
8137 | else | |
8138 | { | |
8139 | /* Integral values greater than one word are stored in consecutive | |
8140 | registers starting with r0. This will always be a multiple of | |
8141 | the regiser size. */ | |
8142 | int len = TYPE_LENGTH (type); | |
8143 | int regno = ARM_A1_REGNUM; | |
8144 | ||
8145 | while (len > 0) | |
8146 | { | |
b66f5587 | 8147 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
8148 | len -= ARM_INT_REGISTER_SIZE; |
8149 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8150 | } |
8151 | } | |
8152 | } | |
34e8f22d | 8153 | else |
b508a996 RE |
8154 | { |
8155 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8156 | been stored to word-aligned memory and then loaded into |
8157 | registers with 32-bit load instruction(s). */ | |
b508a996 RE |
8158 | int len = TYPE_LENGTH (type); |
8159 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8160 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8161 | |
8162 | while (len > 0) | |
8163 | { | |
8164 | memcpy (tmpbuf, valbuf, | |
f0452268 | 8165 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 8166 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
8167 | len -= ARM_INT_REGISTER_SIZE; |
8168 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8169 | } |
8170 | } | |
34e8f22d RE |
8171 | } |
8172 | ||
2af48f68 PB |
8173 | |
8174 | /* Handle function return values. */ | |
8175 | ||
8176 | static enum return_value_convention | |
6a3a010b | 8177 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
8178 | struct type *valtype, struct regcache *regcache, |
8179 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 8180 | { |
7c00367c | 8181 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 8182 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
8183 | enum arm_vfp_cprc_base_type vfp_base_type; |
8184 | int vfp_base_count; | |
8185 | ||
8186 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
8187 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
8188 | { | |
8189 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
8190 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
8191 | int i; | |
8192 | for (i = 0; i < vfp_base_count; i++) | |
8193 | { | |
58d6951d DJ |
8194 | if (reg_char == 'q') |
8195 | { | |
8196 | if (writebuf) | |
8197 | arm_neon_quad_write (gdbarch, regcache, i, | |
8198 | writebuf + i * unit_length); | |
8199 | ||
8200 | if (readbuf) | |
8201 | arm_neon_quad_read (gdbarch, regcache, i, | |
8202 | readbuf + i * unit_length); | |
8203 | } | |
8204 | else | |
8205 | { | |
8206 | char name_buf[4]; | |
8207 | int regnum; | |
8208 | ||
8c042590 | 8209 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
8210 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8211 | strlen (name_buf)); | |
8212 | if (writebuf) | |
b66f5587 | 8213 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 8214 | if (readbuf) |
dca08e1f | 8215 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 8216 | } |
90445bd3 DJ |
8217 | } |
8218 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8219 | } | |
7c00367c | 8220 | |
78134374 SM |
8221 | if (valtype->code () == TYPE_CODE_STRUCT |
8222 | || valtype->code () == TYPE_CODE_UNION | |
8223 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 8224 | { |
7c00367c MK |
8225 | if (tdep->struct_return == pcc_struct_return |
8226 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
8227 | return RETURN_VALUE_STRUCT_CONVENTION; |
8228 | } | |
78134374 | 8229 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
8230 | { |
8231 | if (arm_return_in_memory (gdbarch, valtype)) | |
8232 | return RETURN_VALUE_STRUCT_CONVENTION; | |
8233 | } | |
7052e42c | 8234 | |
2af48f68 PB |
8235 | if (writebuf) |
8236 | arm_store_return_value (valtype, regcache, writebuf); | |
8237 | ||
8238 | if (readbuf) | |
8239 | arm_extract_return_value (valtype, regcache, readbuf); | |
8240 | ||
8241 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8242 | } | |
8243 | ||
8244 | ||
9df628e0 | 8245 | static int |
60ade65d | 8246 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 8247 | { |
e17a4113 UW |
8248 | struct gdbarch *gdbarch = get_frame_arch (frame); |
8249 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8250 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 8251 | CORE_ADDR jb_addr; |
f0452268 | 8252 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 8253 | |
60ade65d | 8254 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
8255 | |
8256 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 8257 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
8258 | return 0; |
8259 | ||
f0452268 | 8260 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
8261 | return 1; |
8262 | } | |
40eadf04 SP |
8263 | /* A call to cmse secure entry function "foo" at "a" is modified by |
8264 | GNU ld as "b". | |
8265 | a) bl xxxx <foo> | |
8266 | ||
8267 | <foo> | |
8268 | xxxx: | |
8269 | ||
8270 | b) bl yyyy <__acle_se_foo> | |
8271 | ||
8272 | section .gnu.sgstubs: | |
8273 | <foo> | |
8274 | yyyy: sg // secure gateway | |
8275 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
8276 | ||
8277 | <__acle_se_foo> | |
8278 | xxxx: | |
8279 | ||
8280 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
8281 | trampoline and does not exist in source code. This function returns the | |
8282 | target pc "xxxx". For more details please refer to section 5.4 | |
8283 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
8284 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
8285 | document on www.developer.arm.com. */ | |
8286 | ||
8287 | static CORE_ADDR | |
8288 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
8289 | { | |
8290 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
8291 | char *target_name = (char *) alloca (target_len); | |
8292 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
8293 | ||
8294 | struct bound_minimal_symbol minsym | |
8295 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
8296 | ||
8297 | if (minsym.minsym != nullptr) | |
8298 | return BMSYMBOL_VALUE_ADDRESS (minsym); | |
8299 | ||
8300 | return 0; | |
8301 | } | |
8302 | ||
8303 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
8304 | ||
8305 | static bool | |
8306 | arm_is_sgstubs_section (struct obj_section *sec) | |
8307 | { | |
8308 | return (sec != nullptr | |
8309 | && sec->the_bfd_section != nullptr | |
8310 | && sec->the_bfd_section->name != nullptr | |
8311 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
8312 | } | |
9df628e0 | 8313 | |
faa95490 DJ |
8314 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
8315 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
8316 | |
8317 | CORE_ADDR | |
52f729a7 | 8318 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 8319 | { |
2c02bd72 | 8320 | const char *name; |
faa95490 | 8321 | int namelen; |
c906108c SS |
8322 | CORE_ADDR start_addr; |
8323 | ||
8324 | /* Find the starting address and name of the function containing the PC. */ | |
8325 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
8326 | { |
8327 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
8328 | check here. */ | |
8329 | start_addr = arm_skip_bx_reg (frame, pc); | |
8330 | if (start_addr != 0) | |
8331 | return start_addr; | |
8332 | ||
8333 | return 0; | |
8334 | } | |
c906108c | 8335 | |
faa95490 DJ |
8336 | /* If PC is in a Thumb call or return stub, return the address of the |
8337 | target PC, which is in a register. The thunk functions are called | |
8338 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
8339 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
8340 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
8341 | if (startswith (name, "_call_via_") |
8342 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 8343 | { |
ed9a39eb | 8344 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 8345 | target PC. */ |
a121b7c1 | 8346 | static const char *table[15] = |
c5aa993b JM |
8347 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
8348 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
8349 | }; | |
c906108c | 8350 | int regno; |
faa95490 | 8351 | int offset = strlen (name) - 2; |
c906108c SS |
8352 | |
8353 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 8354 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 8355 | return get_frame_register_unsigned (frame, regno); |
c906108c | 8356 | } |
ed9a39eb | 8357 | |
faa95490 DJ |
8358 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
8359 | non-interworking calls to foo. We could decode the stubs | |
8360 | to find the target but it's easier to use the symbol table. */ | |
8361 | namelen = strlen (name); | |
8362 | if (name[0] == '_' && name[1] == '_' | |
8363 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 8364 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 8365 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 8366 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
8367 | { |
8368 | char *target_name; | |
8369 | int target_len = namelen - 2; | |
3b7344d5 | 8370 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
8371 | struct objfile *objfile; |
8372 | struct obj_section *sec; | |
8373 | ||
8374 | if (name[namelen - 1] == 'b') | |
8375 | target_len -= strlen ("_from_thumb"); | |
8376 | else | |
8377 | target_len -= strlen ("_from_arm"); | |
8378 | ||
224c3ddb | 8379 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
8380 | memcpy (target_name, name + 2, target_len); |
8381 | target_name[target_len] = '\0'; | |
8382 | ||
8383 | sec = find_pc_section (pc); | |
8384 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
8385 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 8386 | if (minsym.minsym != NULL) |
77e371c0 | 8387 | return BMSYMBOL_VALUE_ADDRESS (minsym); |
faa95490 DJ |
8388 | else |
8389 | return 0; | |
8390 | } | |
8391 | ||
40eadf04 SP |
8392 | struct obj_section *section = find_pc_section (pc); |
8393 | ||
8394 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
8395 | if (arm_is_sgstubs_section (section)) | |
8396 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
8397 | ||
c5aa993b | 8398 | return 0; /* not a stub */ |
c906108c SS |
8399 | } |
8400 | ||
28e97307 DJ |
8401 | static void |
8402 | arm_update_current_architecture (void) | |
fd50bc42 | 8403 | { |
28e97307 | 8404 | struct gdbarch_info info; |
fd50bc42 | 8405 | |
28e97307 | 8406 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 8407 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 8408 | return; |
fd50bc42 | 8409 | |
28e97307 DJ |
8410 | /* Update the architecture. */ |
8411 | gdbarch_info_init (&info); | |
fd50bc42 | 8412 | |
28e97307 | 8413 | if (!gdbarch_update_p (info)) |
9b20d036 | 8414 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
8415 | } |
8416 | ||
8417 | static void | |
eb4c3f4a | 8418 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
8419 | struct cmd_list_element *c) |
8420 | { | |
570dc176 | 8421 | int fp_model; |
fd50bc42 RE |
8422 | |
8423 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
8424 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
8425 | { | |
aead7601 | 8426 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
8427 | break; |
8428 | } | |
8429 | ||
8430 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 8431 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
8432 | current_fp_model); |
8433 | ||
28e97307 | 8434 | arm_update_current_architecture (); |
fd50bc42 RE |
8435 | } |
8436 | ||
8437 | static void | |
08546159 AC |
8438 | show_fp_model (struct ui_file *file, int from_tty, |
8439 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 8440 | { |
f5656ead | 8441 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
fd50bc42 | 8442 | |
28e97307 | 8443 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 8444 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8445 | fprintf_filtered (file, _("\ |
8446 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
8447 | fp_model_strings[tdep->fp_model]); | |
8448 | else | |
8449 | fprintf_filtered (file, _("\ | |
8450 | The current ARM floating point model is \"%s\".\n"), | |
8451 | fp_model_strings[arm_fp_model]); | |
8452 | } | |
8453 | ||
8454 | static void | |
eb4c3f4a | 8455 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
8456 | struct cmd_list_element *c) |
8457 | { | |
570dc176 | 8458 | int arm_abi; |
28e97307 DJ |
8459 | |
8460 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
8461 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
8462 | { | |
aead7601 | 8463 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
8464 | break; |
8465 | } | |
8466 | ||
8467 | if (arm_abi == ARM_ABI_LAST) | |
8468 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
8469 | arm_abi_string); | |
8470 | ||
8471 | arm_update_current_architecture (); | |
8472 | } | |
8473 | ||
8474 | static void | |
8475 | arm_show_abi (struct ui_file *file, int from_tty, | |
8476 | struct cmd_list_element *c, const char *value) | |
8477 | { | |
f5656ead | 8478 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
28e97307 DJ |
8479 | |
8480 | if (arm_abi_global == ARM_ABI_AUTO | |
f5656ead | 8481 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8482 | fprintf_filtered (file, _("\ |
8483 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
8484 | arm_abi_strings[tdep->arm_abi]); | |
8485 | else | |
8486 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
8487 | arm_abi_string); | |
fd50bc42 RE |
8488 | } |
8489 | ||
0428b8f5 DJ |
8490 | static void |
8491 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
8492 | struct cmd_list_element *c, const char *value) | |
8493 | { | |
0963b4bd MS |
8494 | fprintf_filtered (file, |
8495 | _("The current execution mode assumed " | |
8496 | "(when symbols are unavailable) is \"%s\".\n"), | |
0428b8f5 DJ |
8497 | arm_fallback_mode_string); |
8498 | } | |
8499 | ||
8500 | static void | |
8501 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
8502 | struct cmd_list_element *c, const char *value) | |
8503 | { | |
0963b4bd MS |
8504 | fprintf_filtered (file, |
8505 | _("The current execution mode assumed " | |
8506 | "(even when symbols are available) is \"%s\".\n"), | |
0428b8f5 DJ |
8507 | arm_force_mode_string); |
8508 | } | |
8509 | ||
afd7eef0 RE |
8510 | /* If the user changes the register disassembly style used for info |
8511 | register and other commands, we have to also switch the style used | |
8512 | in opcodes for disassembly output. This function is run in the "set | |
8513 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
8514 | |
8515 | static void | |
eb4c3f4a | 8516 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 8517 | struct cmd_list_element *c) |
bc90b915 | 8518 | { |
65b48a81 PB |
8519 | /* Convert the short style name into the long style name (eg, reg-names-*) |
8520 | before calling the generic set_disassembler_options() function. */ | |
8521 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
8522 | set_disassembler_options (&long_name[0]); | |
8523 | } | |
8524 | ||
8525 | static void | |
8526 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
8527 | struct cmd_list_element *c, const char *value) | |
8528 | { | |
8529 | struct gdbarch *gdbarch = get_current_arch (); | |
8530 | char *options = get_disassembler_options (gdbarch); | |
8531 | const char *style = ""; | |
8532 | int len = 0; | |
f995bbe8 | 8533 | const char *opt; |
65b48a81 PB |
8534 | |
8535 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
8536 | if (CONST_STRNEQ (opt, "reg-names-")) | |
8537 | { | |
8538 | style = &opt[strlen ("reg-names-")]; | |
8539 | len = strcspn (style, ","); | |
8540 | } | |
8541 | ||
8542 | fprintf_unfiltered (file, "The disassembly style is \"%.*s\".\n", len, style); | |
bc90b915 FN |
8543 | } |
8544 | \f | |
966fbf70 | 8545 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 8546 | static const char * |
d93859e2 | 8547 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 8548 | { |
58d6951d DJ |
8549 | const int num_regs = gdbarch_num_regs (gdbarch); |
8550 | ||
8551 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
8552 | && i >= num_regs && i < num_regs + 32) | |
8553 | { | |
8554 | static const char *const vfp_pseudo_names[] = { | |
8555 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
8556 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
8557 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
8558 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
8559 | }; | |
8560 | ||
8561 | return vfp_pseudo_names[i - num_regs]; | |
8562 | } | |
8563 | ||
8564 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
8565 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
8566 | { | |
8567 | static const char *const neon_pseudo_names[] = { | |
8568 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
8569 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
8570 | }; | |
8571 | ||
8572 | return neon_pseudo_names[i - num_regs - 32]; | |
8573 | } | |
8574 | ||
ff6f572f DJ |
8575 | if (i >= ARRAY_SIZE (arm_register_names)) |
8576 | /* These registers are only supported on targets which supply | |
8577 | an XML description. */ | |
8578 | return ""; | |
8579 | ||
966fbf70 RE |
8580 | return arm_register_names[i]; |
8581 | } | |
8582 | ||
082fc60d RE |
8583 | /* Test whether the coff symbol specific value corresponds to a Thumb |
8584 | function. */ | |
8585 | ||
8586 | static int | |
8587 | coff_sym_is_thumb (int val) | |
8588 | { | |
f8bf5763 PM |
8589 | return (val == C_THUMBEXT |
8590 | || val == C_THUMBSTAT | |
8591 | || val == C_THUMBEXTFUNC | |
8592 | || val == C_THUMBSTATFUNC | |
8593 | || val == C_THUMBLABEL); | |
082fc60d RE |
8594 | } |
8595 | ||
8596 | /* arm_coff_make_msymbol_special() | |
8597 | arm_elf_make_msymbol_special() | |
8598 | ||
8599 | These functions test whether the COFF or ELF symbol corresponds to | |
8600 | an address in thumb code, and set a "special" bit in a minimal | |
8601 | symbol to indicate that it does. */ | |
8602 | ||
34e8f22d | 8603 | static void |
082fc60d RE |
8604 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
8605 | { | |
39d911fc TP |
8606 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
8607 | ||
8608 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 8609 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
8610 | MSYMBOL_SET_SPECIAL (msym); |
8611 | } | |
8612 | ||
34e8f22d | 8613 | static void |
082fc60d RE |
8614 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
8615 | { | |
8616 | if (coff_sym_is_thumb (val)) | |
8617 | MSYMBOL_SET_SPECIAL (msym); | |
8618 | } | |
8619 | ||
60c5725c DJ |
8620 | static void |
8621 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
8622 | asymbol *sym) | |
8623 | { | |
8624 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 8625 | struct arm_per_bfd *data; |
60c5725c DJ |
8626 | struct arm_mapping_symbol new_map_sym; |
8627 | ||
8628 | gdb_assert (name[0] == '$'); | |
8629 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
8630 | return; | |
8631 | ||
bd5766ec | 8632 | data = arm_bfd_data_key.get (objfile->obfd); |
60c5725c | 8633 | if (data == NULL) |
bd5766ec LM |
8634 | data = arm_bfd_data_key.emplace (objfile->obfd, |
8635 | objfile->obfd->section_count); | |
54cc7474 | 8636 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 8637 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
8638 | |
8639 | new_map_sym.value = sym->value; | |
8640 | new_map_sym.type = name[1]; | |
8641 | ||
4838e44c SM |
8642 | /* Insert at the end, the vector will be sorted on first use. */ |
8643 | map.push_back (new_map_sym); | |
60c5725c DJ |
8644 | } |
8645 | ||
756fe439 | 8646 | static void |
61a1198a | 8647 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 8648 | { |
ac7936df | 8649 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 8650 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
8651 | |
8652 | /* If necessary, set the T bit. */ | |
8653 | if (arm_apcs_32) | |
8654 | { | |
9779414d | 8655 | ULONGEST val, t_bit; |
61a1198a | 8656 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
8657 | t_bit = arm_psr_thumb_bit (gdbarch); |
8658 | if (arm_pc_is_thumb (gdbarch, pc)) | |
8659 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
8660 | val | t_bit); | |
756fe439 | 8661 | else |
61a1198a | 8662 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 8663 | val & ~t_bit); |
756fe439 DJ |
8664 | } |
8665 | } | |
123dc839 | 8666 | |
58d6951d DJ |
8667 | /* Read the contents of a NEON quad register, by reading from two |
8668 | double registers. This is used to implement the quad pseudo | |
8669 | registers, and for argument passing in case the quad registers are | |
8670 | missing; vectors are passed in quad registers when using the VFP | |
8671 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
8672 | the quad register, in [0, 15]. */ | |
8673 | ||
05d1431c | 8674 | static enum register_status |
849d0ba8 | 8675 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8676 | int regnum, gdb_byte *buf) |
8677 | { | |
8678 | char name_buf[4]; | |
8679 | gdb_byte reg_buf[8]; | |
8680 | int offset, double_regnum; | |
05d1431c | 8681 | enum register_status status; |
58d6951d | 8682 | |
8c042590 | 8683 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8684 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8685 | strlen (name_buf)); | |
8686 | ||
8687 | /* d0 is always the least significant half of q0. */ | |
8688 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8689 | offset = 8; | |
8690 | else | |
8691 | offset = 0; | |
8692 | ||
03f50fc8 | 8693 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
8694 | if (status != REG_VALID) |
8695 | return status; | |
58d6951d DJ |
8696 | memcpy (buf + offset, reg_buf, 8); |
8697 | ||
8698 | offset = 8 - offset; | |
03f50fc8 | 8699 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
8700 | if (status != REG_VALID) |
8701 | return status; | |
58d6951d | 8702 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
8703 | |
8704 | return REG_VALID; | |
58d6951d DJ |
8705 | } |
8706 | ||
05d1431c | 8707 | static enum register_status |
849d0ba8 | 8708 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8709 | int regnum, gdb_byte *buf) |
8710 | { | |
8711 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8712 | char name_buf[4]; | |
8713 | gdb_byte reg_buf[8]; | |
8714 | int offset, double_regnum; | |
8715 | ||
8716 | gdb_assert (regnum >= num_regs); | |
8717 | regnum -= num_regs; | |
8718 | ||
8719 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8720 | /* Quad-precision register. */ | |
05d1431c | 8721 | return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); |
58d6951d DJ |
8722 | else |
8723 | { | |
05d1431c PA |
8724 | enum register_status status; |
8725 | ||
58d6951d DJ |
8726 | /* Single-precision register. */ |
8727 | gdb_assert (regnum < 32); | |
8728 | ||
8729 | /* s0 is always the least significant half of d0. */ | |
8730 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8731 | offset = (regnum & 1) ? 0 : 4; | |
8732 | else | |
8733 | offset = (regnum & 1) ? 4 : 0; | |
8734 | ||
8c042590 | 8735 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8736 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8737 | strlen (name_buf)); | |
8738 | ||
03f50fc8 | 8739 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
8740 | if (status == REG_VALID) |
8741 | memcpy (buf, reg_buf + offset, 4); | |
8742 | return status; | |
58d6951d DJ |
8743 | } |
8744 | } | |
8745 | ||
8746 | /* Store the contents of BUF to a NEON quad register, by writing to | |
8747 | two double registers. This is used to implement the quad pseudo | |
8748 | registers, and for argument passing in case the quad registers are | |
8749 | missing; vectors are passed in quad registers when using the VFP | |
8750 | ABI, even if a NEON unit is not present. REGNUM is the index | |
8751 | of the quad register, in [0, 15]. */ | |
8752 | ||
8753 | static void | |
8754 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8755 | int regnum, const gdb_byte *buf) | |
8756 | { | |
8757 | char name_buf[4]; | |
58d6951d DJ |
8758 | int offset, double_regnum; |
8759 | ||
8c042590 | 8760 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8761 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8762 | strlen (name_buf)); | |
8763 | ||
8764 | /* d0 is always the least significant half of q0. */ | |
8765 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8766 | offset = 8; | |
8767 | else | |
8768 | offset = 0; | |
8769 | ||
10eaee5f | 8770 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 8771 | offset = 8 - offset; |
10eaee5f | 8772 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
8773 | } |
8774 | ||
8775 | static void | |
8776 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8777 | int regnum, const gdb_byte *buf) | |
8778 | { | |
8779 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8780 | char name_buf[4]; | |
8781 | gdb_byte reg_buf[8]; | |
8782 | int offset, double_regnum; | |
8783 | ||
8784 | gdb_assert (regnum >= num_regs); | |
8785 | regnum -= num_regs; | |
8786 | ||
8787 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8788 | /* Quad-precision register. */ | |
8789 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
8790 | else | |
8791 | { | |
8792 | /* Single-precision register. */ | |
8793 | gdb_assert (regnum < 32); | |
8794 | ||
8795 | /* s0 is always the least significant half of d0. */ | |
8796 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8797 | offset = (regnum & 1) ? 0 : 4; | |
8798 | else | |
8799 | offset = (regnum & 1) ? 4 : 0; | |
8800 | ||
8c042590 | 8801 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8802 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8803 | strlen (name_buf)); | |
8804 | ||
0b883586 | 8805 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 8806 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 8807 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
8808 | } |
8809 | } | |
8810 | ||
123dc839 DJ |
8811 | static struct value * |
8812 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
8813 | { | |
9a3c8263 | 8814 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
8815 | return value_of_register (*reg_p, frame); |
8816 | } | |
97e03143 | 8817 | \f |
70f80edf JT |
8818 | static enum gdb_osabi |
8819 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 8820 | { |
2af48f68 | 8821 | unsigned int elfosabi; |
70f80edf | 8822 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 8823 | |
70f80edf | 8824 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 8825 | |
28e97307 DJ |
8826 | if (elfosabi == ELFOSABI_ARM) |
8827 | /* GNU tools use this value. Check note sections in this case, | |
8828 | as well. */ | |
b35c1d1c TT |
8829 | { |
8830 | for (asection *sect : gdb_bfd_sections (abfd)) | |
8831 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
8832 | } | |
97e03143 | 8833 | |
28e97307 | 8834 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 8835 | return osabi; |
97e03143 RE |
8836 | } |
8837 | ||
54483882 YQ |
8838 | static int |
8839 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
8840 | struct reggroup *group) | |
8841 | { | |
2c291032 YQ |
8842 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
8843 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
8844 | all_reggroup, of course. */ | |
54483882 | 8845 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
8846 | return (group == float_reggroup |
8847 | || group == save_reggroup | |
8848 | || group == restore_reggroup | |
8849 | || group == all_reggroup); | |
54483882 YQ |
8850 | else |
8851 | return default_register_reggroup_p (gdbarch, regnum, group); | |
8852 | } | |
8853 | ||
25f8c692 JL |
8854 | /* For backward-compatibility we allow two 'g' packet lengths with |
8855 | the remote protocol depending on whether FPA registers are | |
8856 | supplied. M-profile targets do not have FPA registers, but some | |
8857 | stubs already exist in the wild which use a 'g' packet which | |
8858 | supplies them albeit with dummy values. The packet format which | |
8859 | includes FPA registers should be considered deprecated for | |
8860 | M-profile targets. */ | |
8861 | ||
8862 | static void | |
8863 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8864 | { | |
8865 | if (gdbarch_tdep (gdbarch)->is_m) | |
8866 | { | |
d105cce5 AH |
8867 | const target_desc *tdesc; |
8868 | ||
25f8c692 JL |
8869 | /* If we know from the executable this is an M-profile target, |
8870 | cater for remote targets whose register set layout is the | |
8871 | same as the FPA layout. */ | |
d105cce5 | 8872 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 8873 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 8874 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 8875 | tdesc); |
25f8c692 JL |
8876 | |
8877 | /* The regular M-profile layout. */ | |
d105cce5 | 8878 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 8879 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 8880 | tdesc); |
3184d3f9 JL |
8881 | |
8882 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 8883 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 8884 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 8885 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 8886 | tdesc); |
25f8c692 JL |
8887 | } |
8888 | ||
8889 | /* Otherwise we don't have a useful guess. */ | |
8890 | } | |
8891 | ||
7eb89530 YQ |
8892 | /* Implement the code_of_frame_writable gdbarch method. */ |
8893 | ||
8894 | static int | |
8895 | arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame) | |
8896 | { | |
8897 | if (gdbarch_tdep (gdbarch)->is_m | |
8898 | && get_frame_type (frame) == SIGTRAMP_FRAME) | |
8899 | { | |
8900 | /* M-profile exception frames return to some magic PCs, where | |
8901 | isn't writable at all. */ | |
8902 | return 0; | |
8903 | } | |
8904 | else | |
8905 | return 1; | |
8906 | } | |
8907 | ||
3426ae57 AH |
8908 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
8909 | to be postfixed by a version (eg armv7hl). */ | |
8910 | ||
8911 | static const char * | |
8912 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
8913 | { | |
8914 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
8915 | return "arm(v[^- ]*)?"; | |
8916 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
8917 | } | |
8918 | ||
da3c6d4a MS |
8919 | /* Initialize the current architecture based on INFO. If possible, |
8920 | re-use an architecture from ARCHES, which is a list of | |
8921 | architectures already created during this debugging session. | |
97e03143 | 8922 | |
da3c6d4a MS |
8923 | Called e.g. at program startup, when reading a core file, and when |
8924 | reading a binary file. */ | |
97e03143 | 8925 | |
39bbf761 RE |
8926 | static struct gdbarch * |
8927 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8928 | { | |
97e03143 | 8929 | struct gdbarch_tdep *tdep; |
39bbf761 | 8930 | struct gdbarch *gdbarch; |
28e97307 DJ |
8931 | struct gdbarch_list *best_arch; |
8932 | enum arm_abi_kind arm_abi = arm_abi_global; | |
8933 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 8934 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
8935 | int i; |
8936 | bool is_m = false; | |
8937 | int vfp_register_count = 0; | |
8938 | bool have_vfp_pseudos = false, have_neon_pseudos = false; | |
8939 | bool have_wmmx_registers = false; | |
8940 | bool have_neon = false; | |
8941 | bool have_fpa_registers = true; | |
9779414d DJ |
8942 | const struct target_desc *tdesc = info.target_desc; |
8943 | ||
8944 | /* If we have an object to base this architecture on, try to determine | |
8945 | its ABI. */ | |
8946 | ||
8947 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
8948 | { | |
8949 | int ei_osabi, e_flags; | |
8950 | ||
8951 | switch (bfd_get_flavour (info.abfd)) | |
8952 | { | |
9779414d DJ |
8953 | case bfd_target_coff_flavour: |
8954 | /* Assume it's an old APCS-style ABI. */ | |
8955 | /* XXX WinCE? */ | |
8956 | arm_abi = ARM_ABI_APCS; | |
8957 | break; | |
8958 | ||
8959 | case bfd_target_elf_flavour: | |
8960 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
8961 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
8962 | ||
8963 | if (ei_osabi == ELFOSABI_ARM) | |
8964 | { | |
8965 | /* GNU tools used to use this value, but do not for EABI | |
8966 | objects. There's nowhere to tag an EABI version | |
8967 | anyway, so assume APCS. */ | |
8968 | arm_abi = ARM_ABI_APCS; | |
8969 | } | |
d403db27 | 8970 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
8971 | { |
8972 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
8973 | |
8974 | switch (eabi_ver) | |
8975 | { | |
8976 | case EF_ARM_EABI_UNKNOWN: | |
8977 | /* Assume GNU tools. */ | |
8978 | arm_abi = ARM_ABI_APCS; | |
8979 | break; | |
8980 | ||
8981 | case EF_ARM_EABI_VER4: | |
8982 | case EF_ARM_EABI_VER5: | |
8983 | arm_abi = ARM_ABI_AAPCS; | |
8984 | /* EABI binaries default to VFP float ordering. | |
8985 | They may also contain build attributes that can | |
8986 | be used to identify if the VFP argument-passing | |
8987 | ABI is in use. */ | |
8988 | if (fp_model == ARM_FLOAT_AUTO) | |
8989 | { | |
8990 | #ifdef HAVE_ELF | |
8991 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
8992 | OBJ_ATTR_PROC, | |
8993 | Tag_ABI_VFP_args)) | |
8994 | { | |
b35b0298 | 8995 | case AEABI_VFP_args_base: |
9779414d DJ |
8996 | /* "The user intended FP parameter/result |
8997 | passing to conform to AAPCS, base | |
8998 | variant". */ | |
8999 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9000 | break; | |
b35b0298 | 9001 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9002 | /* "The user intended FP parameter/result |
9003 | passing to conform to AAPCS, VFP | |
9004 | variant". */ | |
9005 | fp_model = ARM_FLOAT_VFP; | |
9006 | break; | |
b35b0298 | 9007 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9008 | /* "The user intended FP parameter/result |
9009 | passing to conform to tool chain-specific | |
9010 | conventions" - we don't know any such | |
9011 | conventions, so leave it as "auto". */ | |
9012 | break; | |
b35b0298 | 9013 | case AEABI_VFP_args_compatible: |
5c294fee TG |
9014 | /* "Code is compatible with both the base |
9015 | and VFP variants; the user did not permit | |
9016 | non-variadic functions to pass FP | |
9017 | parameters/results" - leave it as | |
9018 | "auto". */ | |
9019 | break; | |
9779414d DJ |
9020 | default: |
9021 | /* Attribute value not mentioned in the | |
5c294fee | 9022 | November 2012 ABI, so leave it as |
9779414d DJ |
9023 | "auto". */ |
9024 | break; | |
9025 | } | |
9026 | #else | |
9027 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9028 | #endif | |
9029 | } | |
9030 | break; | |
9031 | ||
9032 | default: | |
9033 | /* Leave it as "auto". */ | |
9034 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
9035 | break; | |
9036 | } | |
9037 | ||
9038 | #ifdef HAVE_ELF | |
9039 | /* Detect M-profile programs. This only works if the | |
9040 | executable file includes build attributes; GCC does | |
9041 | copy them to the executable, but e.g. RealView does | |
9042 | not. */ | |
17cbafdb SM |
9043 | int attr_arch |
9044 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9045 | Tag_CPU_arch); | |
9046 | int attr_profile | |
9047 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9048 | Tag_CPU_arch_profile); | |
9049 | ||
9779414d DJ |
9050 | /* GCC specifies the profile for v6-M; RealView only |
9051 | specifies the profile for architectures starting with | |
9052 | V7 (as opposed to architectures with a tag | |
9053 | numerically greater than TAG_CPU_ARCH_V7). */ | |
9054 | if (!tdesc_has_registers (tdesc) | |
9055 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
9056 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
9057 | || attr_profile == 'M')) | |
7559c217 | 9058 | is_m = true; |
9779414d DJ |
9059 | #endif |
9060 | } | |
9061 | ||
9062 | if (fp_model == ARM_FLOAT_AUTO) | |
9063 | { | |
9779414d DJ |
9064 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
9065 | { | |
9066 | case 0: | |
9067 | /* Leave it as "auto". Strictly speaking this case | |
9068 | means FPA, but almost nobody uses that now, and | |
9069 | many toolchains fail to set the appropriate bits | |
9070 | for the floating-point model they use. */ | |
9071 | break; | |
9072 | case EF_ARM_SOFT_FLOAT: | |
9073 | fp_model = ARM_FLOAT_SOFT_FPA; | |
9074 | break; | |
9075 | case EF_ARM_VFP_FLOAT: | |
9076 | fp_model = ARM_FLOAT_VFP; | |
9077 | break; | |
9078 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
9079 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9080 | break; | |
9081 | } | |
9082 | } | |
9083 | ||
9084 | if (e_flags & EF_ARM_BE8) | |
9085 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
9086 | ||
9087 | break; | |
9088 | ||
9089 | default: | |
9090 | /* Leave it as "auto". */ | |
9091 | break; | |
9092 | } | |
9093 | } | |
123dc839 DJ |
9094 | |
9095 | /* Check any target description for validity. */ | |
9779414d | 9096 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
9097 | { |
9098 | /* For most registers we require GDB's default names; but also allow | |
9099 | the numeric names for sp / lr / pc, as a convenience. */ | |
9100 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
9101 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
9102 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
9103 | ||
9104 | const struct tdesc_feature *feature; | |
58d6951d | 9105 | int valid_p; |
123dc839 | 9106 | |
9779414d | 9107 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9108 | "org.gnu.gdb.arm.core"); |
9109 | if (feature == NULL) | |
9779414d DJ |
9110 | { |
9111 | feature = tdesc_find_feature (tdesc, | |
9112 | "org.gnu.gdb.arm.m-profile"); | |
9113 | if (feature == NULL) | |
9114 | return NULL; | |
9115 | else | |
7559c217 | 9116 | is_m = true; |
9779414d | 9117 | } |
123dc839 DJ |
9118 | |
9119 | tdesc_data = tdesc_data_alloc (); | |
9120 | ||
9121 | valid_p = 1; | |
9122 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 9123 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 9124 | arm_register_names[i]); |
c1e1314d | 9125 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9126 | ARM_SP_REGNUM, |
9127 | arm_sp_names); | |
c1e1314d | 9128 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9129 | ARM_LR_REGNUM, |
9130 | arm_lr_names); | |
c1e1314d | 9131 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9132 | ARM_PC_REGNUM, |
9133 | arm_pc_names); | |
9779414d | 9134 | if (is_m) |
c1e1314d | 9135 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
9136 | ARM_PS_REGNUM, "xpsr"); |
9137 | else | |
c1e1314d | 9138 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 9139 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
9140 | |
9141 | if (!valid_p) | |
c1e1314d | 9142 | return NULL; |
123dc839 | 9143 | |
9779414d | 9144 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9145 | "org.gnu.gdb.arm.fpa"); |
9146 | if (feature != NULL) | |
9147 | { | |
9148 | valid_p = 1; | |
9149 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 9150 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
9151 | arm_register_names[i]); |
9152 | if (!valid_p) | |
c1e1314d | 9153 | return NULL; |
123dc839 | 9154 | } |
ff6f572f | 9155 | else |
7559c217 | 9156 | have_fpa_registers = false; |
ff6f572f | 9157 | |
9779414d | 9158 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
9159 | "org.gnu.gdb.xscale.iwmmxt"); |
9160 | if (feature != NULL) | |
9161 | { | |
9162 | static const char *const iwmmxt_names[] = { | |
9163 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
9164 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
9165 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
9166 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
9167 | }; | |
9168 | ||
9169 | valid_p = 1; | |
9170 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
9171 | valid_p | |
c1e1314d | 9172 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9173 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9174 | ||
9175 | /* Check for the control registers, but do not fail if they | |
9176 | are missing. */ | |
9177 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 9178 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9179 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9180 | ||
9181 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
9182 | valid_p | |
c1e1314d | 9183 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9184 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9185 | ||
9186 | if (!valid_p) | |
c1e1314d | 9187 | return NULL; |
a56cc1ce | 9188 | |
7559c217 | 9189 | have_wmmx_registers = true; |
ff6f572f | 9190 | } |
58d6951d DJ |
9191 | |
9192 | /* If we have a VFP unit, check whether the single precision registers | |
9193 | are present. If not, then we will synthesize them as pseudo | |
9194 | registers. */ | |
9779414d | 9195 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9196 | "org.gnu.gdb.arm.vfp"); |
9197 | if (feature != NULL) | |
9198 | { | |
9199 | static const char *const vfp_double_names[] = { | |
9200 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
9201 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
9202 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
9203 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
9204 | }; | |
9205 | ||
9206 | /* Require the double precision registers. There must be either | |
9207 | 16 or 32. */ | |
9208 | valid_p = 1; | |
9209 | for (i = 0; i < 32; i++) | |
9210 | { | |
c1e1314d | 9211 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
9212 | ARM_D0_REGNUM + i, |
9213 | vfp_double_names[i]); | |
9214 | if (!valid_p) | |
9215 | break; | |
9216 | } | |
2b9e5ea6 UW |
9217 | if (!valid_p && i == 16) |
9218 | valid_p = 1; | |
58d6951d | 9219 | |
2b9e5ea6 | 9220 | /* Also require FPSCR. */ |
c1e1314d | 9221 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
9222 | ARM_FPSCR_REGNUM, "fpscr"); |
9223 | if (!valid_p) | |
c1e1314d | 9224 | return NULL; |
58d6951d DJ |
9225 | |
9226 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
7559c217 | 9227 | have_vfp_pseudos = true; |
58d6951d | 9228 | |
330c6ca9 | 9229 | vfp_register_count = i; |
58d6951d DJ |
9230 | |
9231 | /* If we have VFP, also check for NEON. The architecture allows | |
9232 | NEON without VFP (integer vector operations only), but GDB | |
9233 | does not support that. */ | |
9779414d | 9234 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9235 | "org.gnu.gdb.arm.neon"); |
9236 | if (feature != NULL) | |
9237 | { | |
9238 | /* NEON requires 32 double-precision registers. */ | |
9239 | if (i != 32) | |
c1e1314d | 9240 | return NULL; |
58d6951d DJ |
9241 | |
9242 | /* If there are quad registers defined by the stub, use | |
9243 | their type; otherwise (normally) provide them with | |
9244 | the default type. */ | |
9245 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
7559c217 | 9246 | have_neon_pseudos = true; |
58d6951d | 9247 | |
7559c217 | 9248 | have_neon = true; |
58d6951d DJ |
9249 | } |
9250 | } | |
123dc839 | 9251 | } |
39bbf761 | 9252 | |
28e97307 DJ |
9253 | /* If there is already a candidate, use it. */ |
9254 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
9255 | best_arch != NULL; | |
9256 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
9257 | { | |
b8926edc DJ |
9258 | if (arm_abi != ARM_ABI_AUTO |
9259 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
9260 | continue; |
9261 | ||
b8926edc DJ |
9262 | if (fp_model != ARM_FLOAT_AUTO |
9263 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
9264 | continue; |
9265 | ||
58d6951d DJ |
9266 | /* There are various other properties in tdep that we do not |
9267 | need to check here: those derived from a target description, | |
9268 | since gdbarches with a different target description are | |
9269 | automatically disqualified. */ | |
9270 | ||
9779414d DJ |
9271 | /* Do check is_m, though, since it might come from the binary. */ |
9272 | if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m) | |
9273 | continue; | |
9274 | ||
28e97307 DJ |
9275 | /* Found a match. */ |
9276 | break; | |
9277 | } | |
97e03143 | 9278 | |
28e97307 | 9279 | if (best_arch != NULL) |
c1e1314d | 9280 | return best_arch->gdbarch; |
28e97307 | 9281 | |
8d749320 | 9282 | tdep = XCNEW (struct gdbarch_tdep); |
97e03143 RE |
9283 | gdbarch = gdbarch_alloc (&info, tdep); |
9284 | ||
28e97307 DJ |
9285 | /* Record additional information about the architecture we are defining. |
9286 | These are gdbarch discriminators, like the OSABI. */ | |
9287 | tdep->arm_abi = arm_abi; | |
9288 | tdep->fp_model = fp_model; | |
9779414d | 9289 | tdep->is_m = is_m; |
ff6f572f | 9290 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 9291 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
9292 | gdb_assert (vfp_register_count == 0 |
9293 | || vfp_register_count == 16 | |
9294 | || vfp_register_count == 32); | |
9295 | tdep->vfp_register_count = vfp_register_count; | |
58d6951d DJ |
9296 | tdep->have_vfp_pseudos = have_vfp_pseudos; |
9297 | tdep->have_neon_pseudos = have_neon_pseudos; | |
9298 | tdep->have_neon = have_neon; | |
08216dd7 | 9299 | |
25f8c692 JL |
9300 | arm_register_g_packet_guesses (gdbarch); |
9301 | ||
08216dd7 | 9302 | /* Breakpoints. */ |
9d4fde75 | 9303 | switch (info.byte_order_for_code) |
67255d04 RE |
9304 | { |
9305 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
9306 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
9307 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
9308 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
9309 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
9310 | ||
67255d04 RE |
9311 | break; |
9312 | ||
9313 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
9314 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
9315 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
9316 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
9317 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
9318 | ||
67255d04 RE |
9319 | break; |
9320 | ||
9321 | default: | |
9322 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 9323 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
9324 | } |
9325 | ||
d7b486e7 RE |
9326 | /* On ARM targets char defaults to unsigned. */ |
9327 | set_gdbarch_char_signed (gdbarch, 0); | |
9328 | ||
53375380 PA |
9329 | /* wchar_t is unsigned under the AAPCS. */ |
9330 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
9331 | set_gdbarch_wchar_signed (gdbarch, 0); | |
9332 | else | |
9333 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 9334 | |
030197b4 AB |
9335 | /* Compute type alignment. */ |
9336 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
9337 | ||
cca44b1b JB |
9338 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
9339 | of additional scratch space. This setting isn't used for anything beside | |
9340 | displaced stepping at present. */ | |
e935475c | 9341 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 9342 | |
9df628e0 | 9343 | /* This should be low enough for everything. */ |
97e03143 | 9344 | tdep->lowest_pc = 0x20; |
94c30b78 | 9345 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 9346 | |
7c00367c MK |
9347 | /* The default, for both APCS and AAPCS, is to return small |
9348 | structures in registers. */ | |
9349 | tdep->struct_return = reg_struct_return; | |
9350 | ||
2dd604e7 | 9351 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 9352 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 9353 | |
7eb89530 YQ |
9354 | if (is_m) |
9355 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
9356 | ||
756fe439 DJ |
9357 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
9358 | ||
eb5492fa | 9359 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 9360 | |
34e8f22d | 9361 | /* Address manipulation. */ |
34e8f22d RE |
9362 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
9363 | ||
34e8f22d RE |
9364 | /* Advance PC across function entry code. */ |
9365 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
9366 | ||
c9cf6e20 MG |
9367 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
9368 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 9369 | |
190dce09 UW |
9370 | /* Skip trampolines. */ |
9371 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
9372 | ||
34e8f22d RE |
9373 | /* The stack grows downward. */ |
9374 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
9375 | ||
9376 | /* Breakpoint manipulation. */ | |
04180708 YQ |
9377 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
9378 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
9379 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
9380 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
9381 | |
9382 | /* Information about registers, etc. */ | |
34e8f22d RE |
9383 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
9384 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 9385 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 9386 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 9387 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 9388 | |
ff6f572f DJ |
9389 | /* This "info float" is FPA-specific. Use the generic version if we |
9390 | do not have FPA. */ | |
9391 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
9392 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
9393 | ||
26216b98 | 9394 | /* Internal <-> external register number maps. */ |
ff6f572f | 9395 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
9396 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
9397 | ||
34e8f22d RE |
9398 | set_gdbarch_register_name (gdbarch, arm_register_name); |
9399 | ||
9400 | /* Returning results. */ | |
2af48f68 | 9401 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 9402 | |
03d48a7d RE |
9403 | /* Disassembly. */ |
9404 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
9405 | ||
34e8f22d RE |
9406 | /* Minsymbol frobbing. */ |
9407 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
9408 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
9409 | arm_coff_make_msymbol_special); | |
60c5725c | 9410 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 9411 | |
f9d67f43 DJ |
9412 | /* Thumb-2 IT block support. */ |
9413 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
9414 | arm_adjust_breakpoint_address); | |
9415 | ||
0d5de010 DJ |
9416 | /* Virtual tables. */ |
9417 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
9418 | ||
97e03143 | 9419 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 9420 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 9421 | |
b39cc962 DJ |
9422 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
9423 | ||
eb5492fa | 9424 | /* Add some default predicates. */ |
2ae28aa9 YQ |
9425 | if (is_m) |
9426 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
9427 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
9428 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 9429 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 9430 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 9431 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 9432 | |
97e03143 RE |
9433 | /* Now we have tuned the configuration, set a few final things, |
9434 | based on what the OS ABI has told us. */ | |
9435 | ||
b8926edc DJ |
9436 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
9437 | binaries are always marked. */ | |
9438 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
9439 | tdep->arm_abi = ARM_ABI_APCS; | |
9440 | ||
e3039479 UW |
9441 | /* Watchpoints are not steppable. */ |
9442 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
9443 | ||
b8926edc DJ |
9444 | /* We used to default to FPA for generic ARM, but almost nobody |
9445 | uses that now, and we now provide a way for the user to force | |
9446 | the model. So default to the most useful variant. */ | |
9447 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
9448 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
9449 | ||
9df628e0 RE |
9450 | if (tdep->jb_pc >= 0) |
9451 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
9452 | ||
08216dd7 | 9453 | /* Floating point sizes and format. */ |
8da61cc4 | 9454 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 9455 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 9456 | { |
8da61cc4 DJ |
9457 | set_gdbarch_double_format |
9458 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9459 | set_gdbarch_long_double_format | |
9460 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9461 | } | |
9462 | else | |
9463 | { | |
9464 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
9465 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
9466 | } |
9467 | ||
58d6951d DJ |
9468 | if (have_vfp_pseudos) |
9469 | { | |
9470 | /* NOTE: These are the only pseudo registers used by | |
9471 | the ARM target at the moment. If more are added, a | |
9472 | little more care in numbering will be needed. */ | |
9473 | ||
9474 | int num_pseudos = 32; | |
9475 | if (have_neon_pseudos) | |
9476 | num_pseudos += 16; | |
9477 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
9478 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
9479 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
9480 | } | |
9481 | ||
c1e1314d | 9482 | if (tdesc_data != nullptr) |
58d6951d DJ |
9483 | { |
9484 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
9485 | ||
c1e1314d | 9486 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
58d6951d DJ |
9487 | |
9488 | /* Override tdesc_register_type to adjust the types of VFP | |
9489 | registers for NEON. */ | |
9490 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
9491 | } | |
123dc839 DJ |
9492 | |
9493 | /* Add standard register aliases. We add aliases even for those | |
85102364 | 9494 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
9495 | and does no harm, since nothing ever lists user registers. */ |
9496 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
9497 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
9498 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
9499 | ||
65b48a81 PB |
9500 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
9501 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
9502 | ||
3426ae57 AH |
9503 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
9504 | ||
39bbf761 RE |
9505 | return gdbarch; |
9506 | } | |
9507 | ||
97e03143 | 9508 | static void |
2af46ca0 | 9509 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 9510 | { |
2af46ca0 | 9511 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
9512 | |
9513 | if (tdep == NULL) | |
9514 | return; | |
9515 | ||
aeefc73c CB |
9516 | fprintf_unfiltered (file, _("arm_dump_tdep: fp_model = %i\n"), |
9517 | (int) tdep->fp_model); | |
9518 | fprintf_unfiltered (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
9519 | (int) tdep->have_fpa_registers); | |
9520 | fprintf_unfiltered (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
9521 | (int) tdep->have_wmmx_registers); | |
9522 | fprintf_unfiltered (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
9523 | (int) tdep->vfp_register_count); | |
9524 | fprintf_unfiltered (file, _("arm_dump_tdep: have_vfp_pseudos = %i\n"), | |
9525 | (int) tdep->have_vfp_pseudos); | |
9526 | fprintf_unfiltered (file, _("arm_dump_tdep: have_neon_pseudos = %i\n"), | |
9527 | (int) tdep->have_neon_pseudos); | |
9528 | fprintf_unfiltered (file, _("arm_dump_tdep: have_neon = %i\n"), | |
9529 | (int) tdep->have_neon); | |
754e1564 | 9530 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), |
97e03143 RE |
9531 | (unsigned long) tdep->lowest_pc); |
9532 | } | |
9533 | ||
0d4c07af | 9534 | #if GDB_SELF_TEST |
b121eeb9 YQ |
9535 | namespace selftests |
9536 | { | |
9537 | static void arm_record_test (void); | |
9ecab40c | 9538 | static void arm_analyze_prologue_test (); |
b121eeb9 | 9539 | } |
0d4c07af | 9540 | #endif |
b121eeb9 | 9541 | |
6c265988 | 9542 | void _initialize_arm_tdep (); |
c906108c | 9543 | void |
6c265988 | 9544 | _initialize_arm_tdep () |
c906108c | 9545 | { |
bc90b915 | 9546 | long length; |
65b48a81 | 9547 | int i, j; |
edefbb7c AC |
9548 | char regdesc[1024], *rdptr = regdesc; |
9549 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 9550 | |
42cf1509 | 9551 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 9552 | |
0e9e9abd | 9553 | /* Add ourselves to objfile event chain. */ |
76727919 | 9554 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile); |
0e9e9abd | 9555 | |
70f80edf JT |
9556 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
9557 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
9558 | bfd_target_elf_flavour, | |
9559 | arm_elf_osabi_sniffer); | |
9560 | ||
afd7eef0 | 9561 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
0743fc83 TT |
9562 | add_basic_prefix_cmd ("arm", no_class, |
9563 | _("Various ARM-specific commands."), | |
9564 | &setarmcmdlist, "set arm ", 0, &setlist); | |
afd7eef0 | 9565 | |
0743fc83 TT |
9566 | add_show_prefix_cmd ("arm", no_class, |
9567 | _("Various ARM-specific commands."), | |
9568 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 9569 | |
c5aa993b | 9570 | |
65b48a81 | 9571 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
9572 | const disasm_options_t *disasm_options |
9573 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
9574 | int num_disassembly_styles = 0; |
9575 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
9576 | if (CONST_STRNEQ (disasm_options->name[i], "reg-names-")) | |
9577 | num_disassembly_styles++; | |
9578 | ||
9579 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 9580 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
9581 | num_disassembly_styles + 1); |
9582 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
9583 | if (CONST_STRNEQ (disasm_options->name[i], "reg-names-")) | |
9584 | { | |
9585 | size_t offset = strlen ("reg-names-"); | |
9586 | const char *style = disasm_options->name[i]; | |
9587 | valid_disassembly_styles[j++] = &style[offset]; | |
9588 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], | |
9589 | disasm_options->description[i]); | |
9590 | rdptr += length; | |
9591 | rest -= length; | |
9592 | } | |
94c30b78 | 9593 | /* Mark the end of valid options. */ |
65b48a81 | 9594 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 9595 | |
edefbb7c | 9596 | /* Create the help text. */ |
d7e74731 PA |
9597 | std::string helptext = string_printf ("%s%s%s", |
9598 | _("The valid values are:\n"), | |
9599 | regdesc, | |
9600 | _("The default is \"std\".")); | |
ed9a39eb | 9601 | |
edefbb7c AC |
9602 | add_setshow_enum_cmd("disassembler", no_class, |
9603 | valid_disassembly_styles, &disassembly_style, | |
9604 | _("Set the disassembly style."), | |
9605 | _("Show the disassembly style."), | |
09b0e4b0 | 9606 | helptext.c_str (), |
2c5b56ce | 9607 | set_disassembly_style_sfunc, |
65b48a81 | 9608 | show_disassembly_style_sfunc, |
7376b4c2 | 9609 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
9610 | |
9611 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
9612 | _("Set usage of ARM 32-bit mode."), | |
9613 | _("Show usage of ARM 32-bit mode."), | |
9614 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 9615 | NULL, |
0963b4bd MS |
9616 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
9617 | mode is %s. */ | |
26304000 | 9618 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 9619 | |
fd50bc42 | 9620 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
9621 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
9622 | _("Set the floating point type."), | |
9623 | _("Show the floating point type."), | |
9624 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
9625 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
9626 | fpa - FPA co-processor (GCC compiled).\n\ | |
9627 | softvfp - Software FP with pure-endian doubles.\n\ | |
9628 | vfp - VFP co-processor."), | |
edefbb7c | 9629 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 9630 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 9631 | |
28e97307 DJ |
9632 | /* Add a command to allow the user to force the ABI. */ |
9633 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
9634 | _("Set the ABI."), | |
9635 | _("Show the ABI."), | |
9636 | NULL, arm_set_abi, arm_show_abi, | |
9637 | &setarmcmdlist, &showarmcmdlist); | |
9638 | ||
0428b8f5 DJ |
9639 | /* Add two commands to allow the user to force the assumed |
9640 | execution mode. */ | |
9641 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
9642 | arm_mode_strings, &arm_fallback_mode_string, | |
9643 | _("Set the mode assumed when symbols are unavailable."), | |
9644 | _("Show the mode assumed when symbols are unavailable."), | |
9645 | NULL, NULL, arm_show_fallback_mode, | |
9646 | &setarmcmdlist, &showarmcmdlist); | |
9647 | add_setshow_enum_cmd ("force-mode", class_support, | |
9648 | arm_mode_strings, &arm_force_mode_string, | |
9649 | _("Set the mode assumed even when symbols are available."), | |
9650 | _("Show the mode assumed even when symbols are available."), | |
9651 | NULL, NULL, arm_show_force_mode, | |
9652 | &setarmcmdlist, &showarmcmdlist); | |
9653 | ||
6529d2dd | 9654 | /* Debugging flag. */ |
edefbb7c AC |
9655 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
9656 | _("Set ARM debugging."), | |
9657 | _("Show ARM debugging."), | |
9658 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 9659 | NULL, |
7915a72c | 9660 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 9661 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
9662 | |
9663 | #if GDB_SELF_TEST | |
1526853e | 9664 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 9665 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
9666 | #endif |
9667 | ||
c906108c | 9668 | } |
72508ac0 PO |
9669 | |
9670 | /* ARM-reversible process record data structures. */ | |
9671 | ||
9672 | #define ARM_INSN_SIZE_BYTES 4 | |
9673 | #define THUMB_INSN_SIZE_BYTES 2 | |
9674 | #define THUMB2_INSN_SIZE_BYTES 4 | |
9675 | ||
9676 | ||
71e396f9 LM |
9677 | /* Position of the bit within a 32-bit ARM instruction |
9678 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
9679 | #define INSN_S_L_BIT_NUM 20 |
9680 | ||
9681 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
9682 | do \ |
9683 | { \ | |
9684 | unsigned int reg_len = LENGTH; \ | |
9685 | if (reg_len) \ | |
9686 | { \ | |
9687 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
9688 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
9689 | } \ | |
9690 | } \ | |
9691 | while (0) | |
72508ac0 PO |
9692 | |
9693 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
9694 | do \ |
9695 | { \ | |
9696 | unsigned int mem_len = LENGTH; \ | |
9697 | if (mem_len) \ | |
9698 | { \ | |
9699 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
9700 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
9701 | sizeof(struct arm_mem_r) * LENGTH); \ | |
9702 | } \ | |
9703 | } \ | |
9704 | while (0) | |
72508ac0 PO |
9705 | |
9706 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
9707 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 9708 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
9709 | |
9710 | /* ARM memory record structure. */ | |
9711 | struct arm_mem_r | |
9712 | { | |
9713 | uint32_t len; /* Record length. */ | |
bfbbec00 | 9714 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
9715 | }; |
9716 | ||
9717 | /* ARM instruction record contains opcode of current insn | |
9718 | and execution state (before entry to decode_insn()), | |
9719 | contains list of to-be-modified registers and | |
9720 | memory blocks (on return from decode_insn()). */ | |
9721 | ||
9722 | typedef struct insn_decode_record_t | |
9723 | { | |
9724 | struct gdbarch *gdbarch; | |
9725 | struct regcache *regcache; | |
9726 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
9727 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
9728 | uint32_t cond; /* Condition code. */ | |
9729 | uint32_t opcode; /* Insn opcode. */ | |
9730 | uint32_t decode; /* Insn decode bits. */ | |
9731 | uint32_t mem_rec_count; /* No of mem records. */ | |
9732 | uint32_t reg_rec_count; /* No of reg records. */ | |
9733 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
9734 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
9735 | } insn_decode_record; | |
9736 | ||
9737 | ||
9738 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
9739 | ||
9740 | static int | |
9741 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
9742 | { | |
9743 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
9744 | ||
9745 | if (!len) | |
9746 | return 1; | |
9747 | ||
9748 | if (!sbo) | |
9749 | ones = ~ones; | |
9750 | ||
9751 | while (ones) | |
9752 | { | |
9753 | if (!(ones & sbo)) | |
dda83cd7 SM |
9754 | { |
9755 | return 0; | |
9756 | } | |
72508ac0 PO |
9757 | ones = ones >> 1; |
9758 | } | |
9759 | return 1; | |
9760 | } | |
9761 | ||
c6ec2b30 OJ |
9762 | enum arm_record_result |
9763 | { | |
9764 | ARM_RECORD_SUCCESS = 0, | |
9765 | ARM_RECORD_FAILURE = 1 | |
9766 | }; | |
9767 | ||
72508ac0 PO |
9768 | typedef enum |
9769 | { | |
9770 | ARM_RECORD_STRH=1, | |
9771 | ARM_RECORD_STRD | |
9772 | } arm_record_strx_t; | |
9773 | ||
9774 | typedef enum | |
9775 | { | |
9776 | ARM_RECORD=1, | |
9777 | THUMB_RECORD, | |
9778 | THUMB2_RECORD | |
9779 | } record_type_t; | |
9780 | ||
9781 | ||
9782 | static int | |
9783 | arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, | |
dda83cd7 | 9784 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
9785 | { |
9786 | ||
9787 | struct regcache *reg_cache = arm_insn_r->regcache; | |
9788 | ULONGEST u_regval[2]= {0}; | |
9789 | ||
9790 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
9791 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
9792 | |
9793 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
9794 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
9795 | |
9796 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
9797 | { | |
9798 | /* 1) Handle misc store, immediate offset. */ | |
9799 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9800 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9801 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9802 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 9803 | &u_regval[0]); |
72508ac0 | 9804 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
9805 | { |
9806 | /* If R15 was used as Rn, hence current PC+8. */ | |
9807 | u_regval[0] = u_regval[0] + 8; | |
9808 | } | |
72508ac0 PO |
9809 | offset_8 = (immed_high << 4) | immed_low; |
9810 | /* Calculate target store address. */ | |
9811 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
9812 | { |
9813 | tgt_mem_addr = u_regval[0] + offset_8; | |
9814 | } | |
72508ac0 | 9815 | else |
dda83cd7 SM |
9816 | { |
9817 | tgt_mem_addr = u_regval[0] - offset_8; | |
9818 | } | |
72508ac0 | 9819 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9820 | { |
9821 | record_buf_mem[0] = 2; | |
9822 | record_buf_mem[1] = tgt_mem_addr; | |
9823 | arm_insn_r->mem_rec_count = 1; | |
9824 | } | |
72508ac0 | 9825 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9826 | { |
9827 | record_buf_mem[0] = 4; | |
9828 | record_buf_mem[1] = tgt_mem_addr; | |
9829 | record_buf_mem[2] = 4; | |
9830 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9831 | arm_insn_r->mem_rec_count = 2; | |
9832 | } | |
72508ac0 PO |
9833 | } |
9834 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
9835 | { | |
9836 | /* 2) Store, register offset. */ | |
9837 | /* Get Rm. */ | |
9838 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9839 | /* Get Rn. */ | |
9840 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9841 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9842 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9843 | if (15 == reg_src2) | |
dda83cd7 SM |
9844 | { |
9845 | /* If R15 was used as Rn, hence current PC+8. */ | |
9846 | u_regval[0] = u_regval[0] + 8; | |
9847 | } | |
72508ac0 PO |
9848 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
9849 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
9850 | { |
9851 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9852 | } | |
72508ac0 | 9853 | else |
dda83cd7 SM |
9854 | { |
9855 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9856 | } | |
72508ac0 | 9857 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9858 | { |
9859 | record_buf_mem[0] = 2; | |
9860 | record_buf_mem[1] = tgt_mem_addr; | |
9861 | arm_insn_r->mem_rec_count = 1; | |
9862 | } | |
72508ac0 | 9863 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9864 | { |
9865 | record_buf_mem[0] = 4; | |
9866 | record_buf_mem[1] = tgt_mem_addr; | |
9867 | record_buf_mem[2] = 4; | |
9868 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9869 | arm_insn_r->mem_rec_count = 2; | |
9870 | } | |
72508ac0 PO |
9871 | } |
9872 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 9873 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
9874 | { |
9875 | /* 3) Store, immediate pre-indexed. */ | |
9876 | /* 5) Store, immediate post-indexed. */ | |
9877 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9878 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9879 | offset_8 = (immed_high << 4) | immed_low; | |
9880 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9881 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9882 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9883 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
9884 | { |
9885 | tgt_mem_addr = u_regval[0] + offset_8; | |
9886 | } | |
72508ac0 | 9887 | else |
dda83cd7 SM |
9888 | { |
9889 | tgt_mem_addr = u_regval[0] - offset_8; | |
9890 | } | |
72508ac0 | 9891 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9892 | { |
9893 | record_buf_mem[0] = 2; | |
9894 | record_buf_mem[1] = tgt_mem_addr; | |
9895 | arm_insn_r->mem_rec_count = 1; | |
9896 | } | |
72508ac0 | 9897 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9898 | { |
9899 | record_buf_mem[0] = 4; | |
9900 | record_buf_mem[1] = tgt_mem_addr; | |
9901 | record_buf_mem[2] = 4; | |
9902 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9903 | arm_insn_r->mem_rec_count = 2; | |
9904 | } | |
72508ac0 PO |
9905 | /* Record Rn also as it changes. */ |
9906 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9907 | arm_insn_r->reg_rec_count = 1; | |
9908 | } | |
9909 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 9910 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
9911 | { |
9912 | /* 4) Store, register pre-indexed. */ | |
9913 | /* 6) Store, register post -indexed. */ | |
9914 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9915 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9916 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9917 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9918 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9919 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
9920 | { |
9921 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9922 | } | |
72508ac0 | 9923 | else |
dda83cd7 SM |
9924 | { |
9925 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9926 | } | |
72508ac0 | 9927 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9928 | { |
9929 | record_buf_mem[0] = 2; | |
9930 | record_buf_mem[1] = tgt_mem_addr; | |
9931 | arm_insn_r->mem_rec_count = 1; | |
9932 | } | |
72508ac0 | 9933 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9934 | { |
9935 | record_buf_mem[0] = 4; | |
9936 | record_buf_mem[1] = tgt_mem_addr; | |
9937 | record_buf_mem[2] = 4; | |
9938 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9939 | arm_insn_r->mem_rec_count = 2; | |
9940 | } | |
72508ac0 PO |
9941 | /* Record Rn also as it changes. */ |
9942 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9943 | arm_insn_r->reg_rec_count = 1; | |
9944 | } | |
9945 | return 0; | |
9946 | } | |
9947 | ||
9948 | /* Handling ARM extension space insns. */ | |
9949 | ||
9950 | static int | |
9951 | arm_record_extension_space (insn_decode_record *arm_insn_r) | |
9952 | { | |
df95a9cf | 9953 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
9954 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
9955 | uint32_t record_buf[8], record_buf_mem[8]; | |
9956 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
9957 | struct regcache *reg_cache = arm_insn_r->regcache; |
9958 | ULONGEST u_regval = 0; | |
9959 | ||
9960 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
9961 | /* Handle unconditional insn extension space. */ | |
9962 | ||
9963 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
9964 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9965 | if (arm_insn_r->cond) | |
9966 | { | |
9967 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 9968 | the caches. */ |
72508ac0 | 9969 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
9970 | { |
9971 | /* BLX(1) */ | |
9972 | record_buf[0] = ARM_PS_REGNUM; | |
9973 | record_buf[1] = ARM_LR_REGNUM; | |
9974 | arm_insn_r->reg_rec_count = 2; | |
9975 | } | |
72508ac0 PO |
9976 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
9977 | } | |
9978 | ||
9979 | ||
9980 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
9981 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
9982 | { | |
9983 | ret = -1; | |
9984 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 9985 | versions define it. */ |
72508ac0 PO |
9986 | } |
9987 | ||
9988 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
9989 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9990 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
9991 | ||
9992 | /* Handle arithmetic insn extension space. */ | |
9993 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
9994 | && !INSN_RECORDED(arm_insn_r)) | |
9995 | { | |
9996 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 9997 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
72508ac0 | 9998 | { |
dda83cd7 SM |
9999 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10000 | record_buf[1] = ARM_PS_REGNUM; | |
10001 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 10002 | } |
b020ff80 | 10003 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
72508ac0 | 10004 | { |
dda83cd7 SM |
10005 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ |
10006 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10007 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10008 | record_buf[2] = ARM_PS_REGNUM; | |
10009 | arm_insn_r->reg_rec_count = 3; | |
72508ac0 PO |
10010 | } |
10011 | } | |
10012 | ||
10013 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
10014 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
10015 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
10016 | ||
10017 | /* Handle control insn extension space. */ | |
10018 | ||
10019 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
10020 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
10021 | { | |
10022 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
10023 | { |
10024 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
10025 | { | |
10026 | if ((0 == insn_op1) || (2 == insn_op1)) | |
10027 | { | |
10028 | /* MRS. */ | |
10029 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10030 | arm_insn_r->reg_rec_count = 1; | |
10031 | } | |
10032 | else if (1 == insn_op1) | |
10033 | { | |
10034 | /* CSPR is going to be changed. */ | |
10035 | record_buf[0] = ARM_PS_REGNUM; | |
10036 | arm_insn_r->reg_rec_count = 1; | |
10037 | } | |
10038 | else if (3 == insn_op1) | |
10039 | { | |
10040 | /* SPSR is going to be changed. */ | |
10041 | /* We need to get SPSR value, which is yet to be done. */ | |
10042 | return -1; | |
10043 | } | |
10044 | } | |
10045 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10046 | { | |
10047 | if (1 == insn_op1) | |
10048 | { | |
10049 | /* BX. */ | |
10050 | record_buf[0] = ARM_PS_REGNUM; | |
10051 | arm_insn_r->reg_rec_count = 1; | |
10052 | } | |
10053 | else if (3 == insn_op1) | |
10054 | { | |
10055 | /* CLZ. */ | |
10056 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10057 | arm_insn_r->reg_rec_count = 1; | |
10058 | } | |
10059 | } | |
10060 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10061 | { | |
10062 | /* BLX. */ | |
10063 | record_buf[0] = ARM_PS_REGNUM; | |
10064 | record_buf[1] = ARM_LR_REGNUM; | |
10065 | arm_insn_r->reg_rec_count = 2; | |
10066 | } | |
10067 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10068 | { | |
10069 | /* QADD, QSUB, QDADD, QDSUB */ | |
10070 | record_buf[0] = ARM_PS_REGNUM; | |
10071 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10072 | arm_insn_r->reg_rec_count = 2; | |
10073 | } | |
10074 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10075 | { | |
10076 | /* BKPT. */ | |
10077 | record_buf[0] = ARM_PS_REGNUM; | |
10078 | record_buf[1] = ARM_LR_REGNUM; | |
10079 | arm_insn_r->reg_rec_count = 2; | |
10080 | ||
10081 | /* Save SPSR also;how? */ | |
10082 | return -1; | |
10083 | } | |
10084 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
10085 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
10086 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
10087 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
10088 | ) | |
10089 | { | |
10090 | if (0 == insn_op1 || 1 == insn_op1) | |
10091 | { | |
10092 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
10093 | /* We dont do optimization for SMULW<y> where we | |
10094 | need only Rd. */ | |
10095 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10096 | record_buf[1] = ARM_PS_REGNUM; | |
10097 | arm_insn_r->reg_rec_count = 2; | |
10098 | } | |
10099 | else if (2 == insn_op1) | |
10100 | { | |
10101 | /* SMLAL<x><y>. */ | |
10102 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10103 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
10104 | arm_insn_r->reg_rec_count = 2; | |
10105 | } | |
10106 | else if (3 == insn_op1) | |
10107 | { | |
10108 | /* SMUL<x><y>. */ | |
10109 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10110 | arm_insn_r->reg_rec_count = 1; | |
10111 | } | |
10112 | } | |
10113 | } | |
72508ac0 | 10114 | else |
dda83cd7 SM |
10115 | { |
10116 | /* MSR : immediate form. */ | |
10117 | if (1 == insn_op1) | |
10118 | { | |
10119 | /* CSPR is going to be changed. */ | |
10120 | record_buf[0] = ARM_PS_REGNUM; | |
10121 | arm_insn_r->reg_rec_count = 1; | |
10122 | } | |
10123 | else if (3 == insn_op1) | |
10124 | { | |
10125 | /* SPSR is going to be changed. */ | |
10126 | /* we need to get SPSR value, which is yet to be done */ | |
10127 | return -1; | |
10128 | } | |
10129 | } | |
72508ac0 PO |
10130 | } |
10131 | ||
10132 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10133 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
10134 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
10135 | ||
10136 | /* Handle load/store insn extension space. */ | |
10137 | ||
10138 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
10139 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
10140 | && !INSN_RECORDED(arm_insn_r)) | |
10141 | { | |
10142 | /* SWP/SWPB. */ | |
10143 | if (0 == insn_op1) | |
dda83cd7 SM |
10144 | { |
10145 | /* These insn, changes register and memory as well. */ | |
10146 | /* SWP or SWPB insn. */ | |
10147 | /* Get memory address given by Rn. */ | |
10148 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10149 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
10150 | /* SWP insn ?, swaps word. */ | |
10151 | if (8 == arm_insn_r->opcode) | |
10152 | { | |
10153 | record_buf_mem[0] = 4; | |
10154 | } | |
10155 | else | |
10156 | { | |
10157 | /* SWPB insn, swaps only byte. */ | |
10158 | record_buf_mem[0] = 1; | |
10159 | } | |
10160 | record_buf_mem[1] = u_regval; | |
10161 | arm_insn_r->mem_rec_count = 1; | |
10162 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10163 | arm_insn_r->reg_rec_count = 1; | |
10164 | } | |
72508ac0 | 10165 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10166 | { |
10167 | /* STRH. */ | |
10168 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10169 | ARM_RECORD_STRH); | |
10170 | } | |
72508ac0 | 10171 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10172 | { |
10173 | /* LDRD. */ | |
10174 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10175 | record_buf[1] = record_buf[0] + 1; | |
10176 | arm_insn_r->reg_rec_count = 2; | |
10177 | } | |
72508ac0 | 10178 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10179 | { |
10180 | /* STRD. */ | |
10181 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10182 | ARM_RECORD_STRD); | |
10183 | } | |
72508ac0 | 10184 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
10185 | { |
10186 | /* LDRH, LDRSB, LDRSH. */ | |
10187 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10188 | arm_insn_r->reg_rec_count = 1; | |
10189 | } | |
72508ac0 PO |
10190 | |
10191 | } | |
10192 | ||
10193 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
10194 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
10195 | && !INSN_RECORDED(arm_insn_r)) | |
10196 | { | |
10197 | ret = -1; | |
10198 | /* Handle coprocessor insn extension space. */ | |
10199 | } | |
10200 | ||
10201 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
10202 | if (-1 == ret) | |
ca92db2d | 10203 | return ret; |
72508ac0 PO |
10204 | |
10205 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10206 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10207 | ||
10208 | return ret; | |
10209 | } | |
10210 | ||
10211 | /* Handling opcode 000 insns. */ | |
10212 | ||
10213 | static int | |
10214 | arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) | |
10215 | { | |
10216 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10217 | uint32_t record_buf[8], record_buf_mem[8]; | |
10218 | ULONGEST u_regval[2] = {0}; | |
10219 | ||
8d49165d | 10220 | uint32_t reg_src1 = 0; |
72508ac0 PO |
10221 | uint32_t opcode1 = 0; |
10222 | ||
10223 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10224 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10225 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
10226 | ||
2d9e6acb | 10227 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10228 | { |
2d9e6acb YQ |
10229 | /* Data-processing (register) and Data-processing (register-shifted |
10230 | register */ | |
10231 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
10232 | register, which is specified by 13-16 decode. */ | |
10233 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10234 | record_buf[1] = ARM_PS_REGNUM; | |
10235 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 10236 | } |
2d9e6acb | 10237 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10238 | { |
2d9e6acb YQ |
10239 | /* Miscellaneous instructions */ |
10240 | ||
10241 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
10242 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10243 | { | |
10244 | /* Handle BLX, branch and link/exchange. */ | |
10245 | if (9 == arm_insn_r->opcode) | |
10246 | { | |
10247 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
10248 | and R14 stores the return address. */ | |
10249 | record_buf[0] = ARM_PS_REGNUM; | |
10250 | record_buf[1] = ARM_LR_REGNUM; | |
10251 | arm_insn_r->reg_rec_count = 2; | |
10252 | } | |
10253 | } | |
10254 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
10255 | { | |
10256 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
10257 | /* CPSR is changed to be executed in ARM state, disabling normal | |
10258 | interrupts, entering abort mode. */ | |
10259 | /* According to high vector configuration PC is set. */ | |
10260 | /* user hit breakpoint and type reverse, in | |
10261 | that case, we need to go back with previous CPSR and | |
10262 | Program Counter. */ | |
10263 | record_buf[0] = ARM_PS_REGNUM; | |
10264 | record_buf[1] = ARM_LR_REGNUM; | |
10265 | arm_insn_r->reg_rec_count = 2; | |
10266 | ||
10267 | /* Save SPSR also; how? */ | |
10268 | return -1; | |
10269 | } | |
10270 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
10271 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10272 | { | |
10273 | /* Handle BX, branch and link/exchange. */ | |
10274 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
10275 | record_buf[0] = ARM_PS_REGNUM; | |
10276 | arm_insn_r->reg_rec_count = 1; | |
10277 | } | |
10278 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
10279 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
10280 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
10281 | { | |
10282 | /* Count leading zeros: CLZ. */ | |
10283 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10284 | arm_insn_r->reg_rec_count = 1; | |
10285 | } | |
10286 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
10287 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10288 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
10289 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
10290 | { | |
10291 | /* Handle MRS insn. */ | |
10292 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10293 | arm_insn_r->reg_rec_count = 1; | |
10294 | } | |
72508ac0 | 10295 | } |
2d9e6acb | 10296 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 10297 | { |
2d9e6acb YQ |
10298 | /* Multiply and multiply-accumulate */ |
10299 | ||
10300 | /* Handle multiply instructions. */ | |
10301 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
10302 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
10303 | { | |
10304 | /* Handle MLA and MUL. */ | |
10305 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10306 | record_buf[1] = ARM_PS_REGNUM; | |
10307 | arm_insn_r->reg_rec_count = 2; | |
10308 | } | |
10309 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
10310 | { | |
10311 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
10312 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10313 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10314 | record_buf[2] = ARM_PS_REGNUM; | |
10315 | arm_insn_r->reg_rec_count = 3; | |
10316 | } | |
10317 | } | |
10318 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
10319 | { | |
10320 | /* Synchronization primitives */ | |
10321 | ||
72508ac0 PO |
10322 | /* Handling SWP, SWPB. */ |
10323 | /* These insn, changes register and memory as well. */ | |
10324 | /* SWP or SWPB insn. */ | |
10325 | ||
10326 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10327 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10328 | /* SWP insn ?, swaps word. */ | |
10329 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
10330 | { |
10331 | record_buf_mem[0] = 4; | |
10332 | } | |
10333 | else | |
10334 | { | |
10335 | /* SWPB insn, swaps only byte. */ | |
10336 | record_buf_mem[0] = 1; | |
10337 | } | |
72508ac0 PO |
10338 | record_buf_mem[1] = u_regval[0]; |
10339 | arm_insn_r->mem_rec_count = 1; | |
10340 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10341 | arm_insn_r->reg_rec_count = 1; | |
10342 | } | |
2d9e6acb YQ |
10343 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
10344 | || 15 == arm_insn_r->decode) | |
72508ac0 | 10345 | { |
2d9e6acb YQ |
10346 | if ((opcode1 & 0x12) == 2) |
10347 | { | |
10348 | /* Extra load/store (unprivileged) */ | |
10349 | return -1; | |
10350 | } | |
10351 | else | |
10352 | { | |
10353 | /* Extra load/store */ | |
10354 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
10355 | { | |
10356 | case 1: | |
10357 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
10358 | { | |
10359 | /* STRH (register), STRH (immediate) */ | |
10360 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10361 | &record_buf_mem[0], ARM_RECORD_STRH); | |
10362 | } | |
10363 | else if ((opcode1 & 0x05) == 0x1) | |
10364 | { | |
10365 | /* LDRH (register) */ | |
10366 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10367 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 10368 | |
2d9e6acb YQ |
10369 | if (bit (arm_insn_r->arm_insn, 21)) |
10370 | { | |
10371 | /* Write back to Rn. */ | |
10372 | record_buf[arm_insn_r->reg_rec_count++] | |
10373 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10374 | } | |
10375 | } | |
10376 | else if ((opcode1 & 0x05) == 0x5) | |
10377 | { | |
10378 | /* LDRH (immediate), LDRH (literal) */ | |
10379 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 10380 | |
2d9e6acb YQ |
10381 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10382 | arm_insn_r->reg_rec_count = 1; | |
10383 | ||
10384 | if (rn != 15) | |
10385 | { | |
10386 | /*LDRH (immediate) */ | |
10387 | if (bit (arm_insn_r->arm_insn, 21)) | |
10388 | { | |
10389 | /* Write back to Rn. */ | |
10390 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10391 | } | |
10392 | } | |
10393 | } | |
10394 | else | |
10395 | return -1; | |
10396 | break; | |
10397 | case 2: | |
10398 | if ((opcode1 & 0x05) == 0x0) | |
10399 | { | |
10400 | /* LDRD (register) */ | |
10401 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10402 | record_buf[1] = record_buf[0] + 1; | |
10403 | arm_insn_r->reg_rec_count = 2; | |
10404 | ||
10405 | if (bit (arm_insn_r->arm_insn, 21)) | |
10406 | { | |
10407 | /* Write back to Rn. */ | |
10408 | record_buf[arm_insn_r->reg_rec_count++] | |
10409 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10410 | } | |
10411 | } | |
10412 | else if ((opcode1 & 0x05) == 0x1) | |
10413 | { | |
10414 | /* LDRSB (register) */ | |
10415 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10416 | arm_insn_r->reg_rec_count = 1; | |
10417 | ||
10418 | if (bit (arm_insn_r->arm_insn, 21)) | |
10419 | { | |
10420 | /* Write back to Rn. */ | |
10421 | record_buf[arm_insn_r->reg_rec_count++] | |
10422 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10423 | } | |
10424 | } | |
10425 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
10426 | { | |
10427 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
10428 | LDRSB (literal) */ | |
10429 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
10430 | ||
10431 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10432 | arm_insn_r->reg_rec_count = 1; | |
10433 | ||
10434 | if (rn != 15) | |
10435 | { | |
10436 | /*LDRD (immediate), LDRSB (immediate) */ | |
10437 | if (bit (arm_insn_r->arm_insn, 21)) | |
10438 | { | |
10439 | /* Write back to Rn. */ | |
10440 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10441 | } | |
10442 | } | |
10443 | } | |
10444 | else | |
10445 | return -1; | |
10446 | break; | |
10447 | case 3: | |
10448 | if ((opcode1 & 0x05) == 0x0) | |
10449 | { | |
10450 | /* STRD (register) */ | |
10451 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10452 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10453 | } | |
10454 | else if ((opcode1 & 0x05) == 0x1) | |
10455 | { | |
10456 | /* LDRSH (register) */ | |
10457 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10458 | arm_insn_r->reg_rec_count = 1; | |
10459 | ||
10460 | if (bit (arm_insn_r->arm_insn, 21)) | |
10461 | { | |
10462 | /* Write back to Rn. */ | |
10463 | record_buf[arm_insn_r->reg_rec_count++] | |
10464 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10465 | } | |
10466 | } | |
10467 | else if ((opcode1 & 0x05) == 0x4) | |
10468 | { | |
10469 | /* STRD (immediate) */ | |
10470 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10471 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10472 | } | |
10473 | else if ((opcode1 & 0x05) == 0x5) | |
10474 | { | |
10475 | /* LDRSH (immediate), LDRSH (literal) */ | |
10476 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10477 | arm_insn_r->reg_rec_count = 1; | |
10478 | ||
10479 | if (bit (arm_insn_r->arm_insn, 21)) | |
10480 | { | |
10481 | /* Write back to Rn. */ | |
10482 | record_buf[arm_insn_r->reg_rec_count++] | |
10483 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10484 | } | |
10485 | } | |
10486 | else | |
10487 | return -1; | |
10488 | break; | |
10489 | default: | |
10490 | return -1; | |
10491 | } | |
10492 | } | |
72508ac0 PO |
10493 | } |
10494 | else | |
10495 | { | |
10496 | return -1; | |
10497 | } | |
10498 | ||
10499 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10500 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10501 | return 0; | |
10502 | } | |
10503 | ||
10504 | /* Handling opcode 001 insns. */ | |
10505 | ||
10506 | static int | |
10507 | arm_record_data_proc_imm (insn_decode_record *arm_insn_r) | |
10508 | { | |
10509 | uint32_t record_buf[8], record_buf_mem[8]; | |
10510 | ||
10511 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10512 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10513 | ||
10514 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
10515 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
10516 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
10517 | ) | |
10518 | { | |
10519 | /* Handle MSR insn. */ | |
10520 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
10521 | { |
10522 | /* CSPR is going to be changed. */ | |
10523 | record_buf[0] = ARM_PS_REGNUM; | |
10524 | arm_insn_r->reg_rec_count = 1; | |
10525 | } | |
72508ac0 | 10526 | else |
dda83cd7 SM |
10527 | { |
10528 | /* SPSR is going to be changed. */ | |
10529 | } | |
72508ac0 PO |
10530 | } |
10531 | else if (arm_insn_r->opcode <= 15) | |
10532 | { | |
10533 | /* Normal data processing insns. */ | |
10534 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 10535 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
10536 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10537 | record_buf[1] = ARM_PS_REGNUM; | |
10538 | arm_insn_r->reg_rec_count = 2; | |
10539 | } | |
10540 | else | |
10541 | { | |
10542 | return -1; | |
10543 | } | |
10544 | ||
10545 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10546 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10547 | return 0; | |
10548 | } | |
10549 | ||
c55978a6 YQ |
10550 | static int |
10551 | arm_record_media (insn_decode_record *arm_insn_r) | |
10552 | { | |
10553 | uint32_t record_buf[8]; | |
10554 | ||
10555 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
10556 | { | |
10557 | case 0: | |
10558 | /* Parallel addition and subtraction, signed */ | |
10559 | case 1: | |
10560 | /* Parallel addition and subtraction, unsigned */ | |
10561 | case 2: | |
10562 | case 3: | |
10563 | /* Packing, unpacking, saturation and reversal */ | |
10564 | { | |
10565 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
10566 | ||
10567 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
10568 | } | |
10569 | break; | |
10570 | ||
10571 | case 4: | |
10572 | case 5: | |
10573 | /* Signed multiplies */ | |
10574 | { | |
10575 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
10576 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
10577 | ||
10578 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
10579 | if (op1 == 0x0) | |
10580 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
10581 | else if (op1 == 0x4) | |
10582 | record_buf[arm_insn_r->reg_rec_count++] | |
10583 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10584 | } | |
10585 | break; | |
10586 | ||
10587 | case 6: | |
10588 | { | |
10589 | if (bit (arm_insn_r->arm_insn, 21) | |
10590 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
10591 | { | |
10592 | /* SBFX */ | |
10593 | record_buf[arm_insn_r->reg_rec_count++] | |
10594 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10595 | } | |
10596 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
10597 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
10598 | { | |
10599 | /* USAD8 and USADA8 */ | |
10600 | record_buf[arm_insn_r->reg_rec_count++] | |
10601 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10602 | } | |
10603 | } | |
10604 | break; | |
10605 | ||
10606 | case 7: | |
10607 | { | |
10608 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
10609 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
10610 | { | |
10611 | /* Permanently UNDEFINED */ | |
10612 | return -1; | |
10613 | } | |
10614 | else | |
10615 | { | |
10616 | /* BFC, BFI and UBFX */ | |
10617 | record_buf[arm_insn_r->reg_rec_count++] | |
10618 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10619 | } | |
10620 | } | |
10621 | break; | |
10622 | ||
10623 | default: | |
10624 | return -1; | |
10625 | } | |
10626 | ||
10627 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10628 | ||
10629 | return 0; | |
10630 | } | |
10631 | ||
71e396f9 | 10632 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
10633 | |
10634 | static int | |
10635 | arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) | |
10636 | { | |
10637 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10638 | ||
71e396f9 LM |
10639 | uint32_t reg_base , reg_dest; |
10640 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 10641 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
10642 | unsigned char wback; |
10643 | ULONGEST u_regval; | |
72508ac0 | 10644 | |
71e396f9 LM |
10645 | /* Calculate wback. */ |
10646 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
10647 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 10648 | |
71e396f9 LM |
10649 | arm_insn_r->reg_rec_count = 0; |
10650 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
10651 | |
10652 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10653 | { | |
71e396f9 LM |
10654 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
10655 | and LDRT. */ | |
10656 | ||
72508ac0 | 10657 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
10658 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
10659 | ||
10660 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
10661 | preceeds a LDR instruction having R15 as reg_base, it | |
10662 | emulates a branch and link instruction, and hence we need to save | |
10663 | CPSR and PC as well. */ | |
10664 | if (ARM_PC_REGNUM == reg_dest) | |
10665 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
10666 | ||
10667 | /* If wback is true, also save the base register, which is going to be | |
10668 | written to. */ | |
10669 | if (wback) | |
10670 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10671 | } |
10672 | else | |
10673 | { | |
71e396f9 LM |
10674 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
10675 | ||
72508ac0 | 10676 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
10677 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
10678 | ||
10679 | /* Handle bit U. */ | |
72508ac0 | 10680 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
10681 | { |
10682 | /* U == 1: Add the offset. */ | |
10683 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
10684 | } | |
72508ac0 | 10685 | else |
71e396f9 LM |
10686 | { |
10687 | /* U == 0: subtract the offset. */ | |
10688 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
10689 | } | |
10690 | ||
10691 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
10692 | bytes. */ | |
10693 | if (bit (arm_insn_r->arm_insn, 22)) | |
10694 | { | |
10695 | /* STRB and STRBT: 1 byte. */ | |
10696 | record_buf_mem[0] = 1; | |
10697 | } | |
10698 | else | |
10699 | { | |
10700 | /* STR and STRT: 4 bytes. */ | |
10701 | record_buf_mem[0] = 4; | |
10702 | } | |
10703 | ||
10704 | /* Handle bit P. */ | |
10705 | if (bit (arm_insn_r->arm_insn, 24)) | |
10706 | record_buf_mem[1] = tgt_mem_addr; | |
10707 | else | |
10708 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 10709 | |
72508ac0 PO |
10710 | arm_insn_r->mem_rec_count = 1; |
10711 | ||
71e396f9 LM |
10712 | /* If wback is true, also save the base register, which is going to be |
10713 | written to. */ | |
10714 | if (wback) | |
10715 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10716 | } |
10717 | ||
10718 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10719 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10720 | return 0; | |
10721 | } | |
10722 | ||
10723 | /* Handling opcode 011 insns. */ | |
10724 | ||
10725 | static int | |
10726 | arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) | |
10727 | { | |
10728 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10729 | ||
10730 | uint32_t shift_imm = 0; | |
10731 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
10732 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
10733 | uint32_t record_buf[8], record_buf_mem[8]; | |
10734 | ||
10735 | LONGEST s_word; | |
10736 | ULONGEST u_regval[2]; | |
10737 | ||
c55978a6 YQ |
10738 | if (bit (arm_insn_r->arm_insn, 4)) |
10739 | return arm_record_media (arm_insn_r); | |
10740 | ||
72508ac0 PO |
10741 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
10742 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10743 | ||
10744 | /* Handle enhanced store insns and LDRD DSP insn, | |
10745 | order begins according to addressing modes for store insns | |
10746 | STRH insn. */ | |
10747 | ||
10748 | /* LDR or STR? */ | |
10749 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10750 | { | |
10751 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
10752 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
10753 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
10754 | in that case, it emulates branch and link insn, and hence we | |
10755 | need to save CSPR and PC as well. */ | |
72508ac0 | 10756 | if (15 != reg_dest) |
dda83cd7 SM |
10757 | { |
10758 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10759 | arm_insn_r->reg_rec_count = 1; | |
10760 | } | |
72508ac0 | 10761 | else |
dda83cd7 SM |
10762 | { |
10763 | record_buf[0] = reg_dest; | |
10764 | record_buf[1] = ARM_PS_REGNUM; | |
10765 | arm_insn_r->reg_rec_count = 2; | |
10766 | } | |
72508ac0 PO |
10767 | } |
10768 | else | |
10769 | { | |
10770 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
10771 | { |
10772 | /* Store insn, register offset and register pre-indexed, | |
10773 | register post-indexed. */ | |
10774 | /* Get Rm. */ | |
10775 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10776 | /* Get Rn. */ | |
10777 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10778 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
10779 | , &u_regval[0]); | |
10780 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
10781 | , &u_regval[1]); | |
10782 | if (15 == reg_src2) | |
10783 | { | |
10784 | /* If R15 was used as Rn, hence current PC+8. */ | |
10785 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
10786 | u_regval[0] = u_regval[0] + 8; | |
10787 | } | |
10788 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10789 | /* U == 1. */ | |
10790 | if (bit (arm_insn_r->arm_insn, 23)) | |
10791 | { | |
10792 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10793 | } | |
10794 | else | |
10795 | { | |
10796 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10797 | } | |
10798 | ||
10799 | switch (arm_insn_r->opcode) | |
10800 | { | |
10801 | /* STR. */ | |
10802 | case 8: | |
10803 | case 12: | |
10804 | /* STR. */ | |
10805 | case 9: | |
10806 | case 13: | |
10807 | /* STRT. */ | |
10808 | case 1: | |
10809 | case 5: | |
10810 | /* STR. */ | |
10811 | case 0: | |
10812 | case 4: | |
10813 | record_buf_mem[0] = 4; | |
10814 | break; | |
10815 | ||
10816 | /* STRB. */ | |
10817 | case 10: | |
10818 | case 14: | |
10819 | /* STRB. */ | |
10820 | case 11: | |
10821 | case 15: | |
10822 | /* STRBT. */ | |
10823 | case 3: | |
10824 | case 7: | |
10825 | /* STRB. */ | |
10826 | case 2: | |
10827 | case 6: | |
10828 | record_buf_mem[0] = 1; | |
10829 | break; | |
10830 | ||
10831 | default: | |
10832 | gdb_assert_not_reached ("no decoding pattern found"); | |
10833 | break; | |
10834 | } | |
10835 | record_buf_mem[1] = tgt_mem_addr; | |
10836 | arm_insn_r->mem_rec_count = 1; | |
10837 | ||
10838 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10839 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10840 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10841 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10842 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10843 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10844 | ) | |
10845 | { | |
10846 | /* Rn is going to be changed in pre-indexed mode and | |
10847 | post-indexed mode as well. */ | |
10848 | record_buf[0] = reg_src2; | |
10849 | arm_insn_r->reg_rec_count = 1; | |
10850 | } | |
10851 | } | |
72508ac0 | 10852 | else |
dda83cd7 SM |
10853 | { |
10854 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
10855 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
10856 | /* Get Rm. */ | |
10857 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10858 | /* Get Rn. */ | |
10859 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10860 | /* Get shift_imm. */ | |
10861 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
10862 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10863 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
10864 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10865 | /* Offset_12 used as shift. */ | |
10866 | switch (offset_12) | |
10867 | { | |
10868 | case 0: | |
10869 | /* Offset_12 used as index. */ | |
10870 | offset_12 = u_regval[0] << shift_imm; | |
10871 | break; | |
10872 | ||
10873 | case 1: | |
10874 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
10875 | break; | |
10876 | ||
10877 | case 2: | |
10878 | if (!shift_imm) | |
10879 | { | |
10880 | if (bit (u_regval[0], 31)) | |
10881 | { | |
10882 | offset_12 = 0xFFFFFFFF; | |
10883 | } | |
10884 | else | |
10885 | { | |
10886 | offset_12 = 0; | |
10887 | } | |
10888 | } | |
10889 | else | |
10890 | { | |
10891 | /* This is arithmetic shift. */ | |
10892 | offset_12 = s_word >> shift_imm; | |
10893 | } | |
10894 | break; | |
10895 | ||
10896 | case 3: | |
10897 | if (!shift_imm) | |
10898 | { | |
10899 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
10900 | &u_regval[1]); | |
10901 | /* Get C flag value and shift it by 31. */ | |
10902 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
10903 | | (u_regval[0]) >> 1); | |
10904 | } | |
10905 | else | |
10906 | { | |
10907 | offset_12 = (u_regval[0] >> shift_imm) \ | |
10908 | | (u_regval[0] << | |
10909 | (sizeof(uint32_t) - shift_imm)); | |
10910 | } | |
10911 | break; | |
10912 | ||
10913 | default: | |
10914 | gdb_assert_not_reached ("no decoding pattern found"); | |
10915 | break; | |
10916 | } | |
10917 | ||
10918 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10919 | /* bit U set. */ | |
10920 | if (bit (arm_insn_r->arm_insn, 23)) | |
10921 | { | |
10922 | tgt_mem_addr = u_regval[1] + offset_12; | |
10923 | } | |
10924 | else | |
10925 | { | |
10926 | tgt_mem_addr = u_regval[1] - offset_12; | |
10927 | } | |
10928 | ||
10929 | switch (arm_insn_r->opcode) | |
10930 | { | |
10931 | /* STR. */ | |
10932 | case 8: | |
10933 | case 12: | |
10934 | /* STR. */ | |
10935 | case 9: | |
10936 | case 13: | |
10937 | /* STRT. */ | |
10938 | case 1: | |
10939 | case 5: | |
10940 | /* STR. */ | |
10941 | case 0: | |
10942 | case 4: | |
10943 | record_buf_mem[0] = 4; | |
10944 | break; | |
10945 | ||
10946 | /* STRB. */ | |
10947 | case 10: | |
10948 | case 14: | |
10949 | /* STRB. */ | |
10950 | case 11: | |
10951 | case 15: | |
10952 | /* STRBT. */ | |
10953 | case 3: | |
10954 | case 7: | |
10955 | /* STRB. */ | |
10956 | case 2: | |
10957 | case 6: | |
10958 | record_buf_mem[0] = 1; | |
10959 | break; | |
10960 | ||
10961 | default: | |
10962 | gdb_assert_not_reached ("no decoding pattern found"); | |
10963 | break; | |
10964 | } | |
10965 | record_buf_mem[1] = tgt_mem_addr; | |
10966 | arm_insn_r->mem_rec_count = 1; | |
10967 | ||
10968 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10969 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10970 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10971 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10972 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10973 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10974 | ) | |
10975 | { | |
10976 | /* Rn is going to be changed in register scaled pre-indexed | |
10977 | mode,and scaled post indexed mode. */ | |
10978 | record_buf[0] = reg_src2; | |
10979 | arm_insn_r->reg_rec_count = 1; | |
10980 | } | |
10981 | } | |
72508ac0 PO |
10982 | } |
10983 | ||
10984 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10985 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10986 | return 0; | |
10987 | } | |
10988 | ||
71e396f9 | 10989 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
10990 | |
10991 | static int | |
10992 | arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) | |
10993 | { | |
10994 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
10995 | uint32_t register_count = 0, register_bits; |
10996 | uint32_t reg_base, addr_mode; | |
72508ac0 | 10997 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
10998 | uint32_t wback; |
10999 | ULONGEST u_regval; | |
72508ac0 | 11000 | |
71e396f9 LM |
11001 | /* Fetch the list of registers. */ |
11002 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
11003 | arm_insn_r->reg_rec_count = 0; | |
11004 | ||
11005 | /* Fetch the base register that contains the address we are loading data | |
11006 | to. */ | |
11007 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11008 | |
71e396f9 LM |
11009 | /* Calculate wback. */ |
11010 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
11011 | |
11012 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11013 | { | |
71e396f9 | 11014 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 11015 | |
71e396f9 | 11016 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 11017 | while (register_bits) |
71e396f9 LM |
11018 | { |
11019 | if (register_bits & 0x00000001) | |
11020 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
11021 | register_bits = register_bits >> 1; | |
11022 | register_count++; | |
11023 | } | |
72508ac0 | 11024 | |
71e396f9 LM |
11025 | |
11026 | /* If wback is true, also save the base register, which is going to be | |
11027 | written to. */ | |
11028 | if (wback) | |
11029 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
11030 | ||
11031 | /* Save the CPSR register. */ | |
11032 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
11033 | } |
11034 | else | |
11035 | { | |
71e396f9 | 11036 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 11037 | |
71e396f9 LM |
11038 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
11039 | ||
11040 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
11041 | ||
11042 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 11043 | while (register_bits) |
71e396f9 LM |
11044 | { |
11045 | if (register_bits & 0x00000001) | |
11046 | register_count++; | |
11047 | register_bits = register_bits >> 1; | |
11048 | } | |
72508ac0 PO |
11049 | |
11050 | switch (addr_mode) | |
71e396f9 LM |
11051 | { |
11052 | /* STMDA (STMED): Decrement after. */ | |
11053 | case 0: | |
11054 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11055 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
11056 | break; |
11057 | /* STM (STMIA, STMEA): Increment after. */ | |
11058 | case 1: | |
11059 | record_buf_mem[1] = (uint32_t) u_regval; | |
11060 | break; | |
11061 | /* STMDB (STMFD): Decrement before. */ | |
11062 | case 2: | |
11063 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11064 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11065 | break; |
11066 | /* STMIB (STMFA): Increment before. */ | |
11067 | case 3: | |
f0452268 | 11068 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11069 | break; |
11070 | default: | |
11071 | gdb_assert_not_reached ("no decoding pattern found"); | |
11072 | break; | |
11073 | } | |
72508ac0 | 11074 | |
f0452268 | 11075 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11076 | arm_insn_r->mem_rec_count = 1; |
11077 | ||
11078 | /* If wback is true, also save the base register, which is going to be | |
11079 | written to. */ | |
11080 | if (wback) | |
11081 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11082 | } |
11083 | ||
11084 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11085 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11086 | return 0; | |
11087 | } | |
11088 | ||
11089 | /* Handling opcode 101 insns. */ | |
11090 | ||
11091 | static int | |
11092 | arm_record_b_bl (insn_decode_record *arm_insn_r) | |
11093 | { | |
11094 | uint32_t record_buf[8]; | |
11095 | ||
11096 | /* Handle B, BL, BLX(1) insns. */ | |
11097 | /* B simply branches so we do nothing here. */ | |
11098 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
11099 | extension space. */ | |
11100 | if (bit (arm_insn_r->arm_insn, 24)) | |
11101 | { | |
11102 | record_buf[0] = ARM_LR_REGNUM; | |
11103 | arm_insn_r->reg_rec_count = 1; | |
11104 | } | |
11105 | ||
11106 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11107 | ||
11108 | return 0; | |
11109 | } | |
11110 | ||
72508ac0 | 11111 | static int |
c6ec2b30 | 11112 | arm_record_unsupported_insn (insn_decode_record *arm_insn_r) |
72508ac0 PO |
11113 | { |
11114 | printf_unfiltered (_("Process record does not support instruction " | |
01e57735 YQ |
11115 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, |
11116 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
11117 | |
11118 | return -1; | |
11119 | } | |
11120 | ||
5a578da5 OJ |
11121 | /* Record handler for vector data transfer instructions. */ |
11122 | ||
11123 | static int | |
11124 | arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) | |
11125 | { | |
11126 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
11127 | uint32_t record_buf[4]; | |
11128 | ||
5a578da5 OJ |
11129 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
11130 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
11131 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
11132 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
11133 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
11134 | ||
11135 | /* Handle VMOV instruction. */ | |
11136 | if (bit_l && bit_c) | |
11137 | { | |
11138 | record_buf[0] = reg_t; | |
11139 | arm_insn_r->reg_rec_count = 1; | |
11140 | } | |
11141 | else if (bit_l && !bit_c) | |
11142 | { | |
11143 | /* Handle VMOV instruction. */ | |
11144 | if (bits_a == 0x00) | |
dda83cd7 | 11145 | { |
f1771dce | 11146 | record_buf[0] = reg_t; |
dda83cd7 SM |
11147 | arm_insn_r->reg_rec_count = 1; |
11148 | } | |
5a578da5 OJ |
11149 | /* Handle VMRS instruction. */ |
11150 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11151 | { |
11152 | if (reg_t == 15) | |
11153 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 11154 | |
dda83cd7 SM |
11155 | record_buf[0] = reg_t; |
11156 | arm_insn_r->reg_rec_count = 1; | |
11157 | } | |
5a578da5 OJ |
11158 | } |
11159 | else if (!bit_l && !bit_c) | |
11160 | { | |
11161 | /* Handle VMOV instruction. */ | |
11162 | if (bits_a == 0x00) | |
dda83cd7 | 11163 | { |
f1771dce | 11164 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 11165 | |
dda83cd7 SM |
11166 | arm_insn_r->reg_rec_count = 1; |
11167 | } | |
5a578da5 OJ |
11168 | /* Handle VMSR instruction. */ |
11169 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11170 | { |
11171 | record_buf[0] = ARM_FPSCR_REGNUM; | |
11172 | arm_insn_r->reg_rec_count = 1; | |
11173 | } | |
5a578da5 OJ |
11174 | } |
11175 | else if (!bit_l && bit_c) | |
11176 | { | |
11177 | /* Handle VMOV instruction. */ | |
11178 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
11179 | { |
11180 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
11181 | + ARM_D0_REGNUM; | |
11182 | arm_insn_r->reg_rec_count = 1; | |
11183 | } | |
5a578da5 OJ |
11184 | /* Handle VDUP instruction. */ |
11185 | else | |
dda83cd7 SM |
11186 | { |
11187 | if (bit (arm_insn_r->arm_insn, 21)) | |
11188 | { | |
11189 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11190 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11191 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
11192 | arm_insn_r->reg_rec_count = 2; | |
11193 | } | |
11194 | else | |
11195 | { | |
11196 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11197 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11198 | arm_insn_r->reg_rec_count = 1; | |
11199 | } | |
11200 | } | |
11201 | } | |
11202 | ||
11203 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11204 | return 0; | |
11205 | } | |
11206 | ||
f20f80dd OJ |
11207 | /* Record handler for extension register load/store instructions. */ |
11208 | ||
11209 | static int | |
11210 | arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) | |
11211 | { | |
11212 | uint32_t opcode, single_reg; | |
11213 | uint8_t op_vldm_vstm; | |
11214 | uint32_t record_buf[8], record_buf_mem[128]; | |
11215 | ULONGEST u_regval = 0; | |
11216 | ||
11217 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
11218 | |
11219 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 11220 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
11221 | op_vldm_vstm = opcode & 0x1b; |
11222 | ||
11223 | /* Handle VMOV instructions. */ | |
11224 | if ((opcode & 0x1e) == 0x04) | |
11225 | { | |
9fde51ed | 11226 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
11227 | { |
11228 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11229 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11230 | arm_insn_r->reg_rec_count = 2; | |
11231 | } | |
f20f80dd | 11232 | else |
01e57735 | 11233 | { |
9fde51ed YQ |
11234 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
11235 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 11236 | |
9fde51ed | 11237 | if (single_reg) |
01e57735 | 11238 | { |
9fde51ed YQ |
11239 | /* The first S register number m is REG_M:M (M is bit 5), |
11240 | the corresponding D register number is REG_M:M / 2, which | |
11241 | is REG_M. */ | |
11242 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
11243 | /* The second S register number is REG_M:M + 1, the | |
11244 | corresponding D register number is (REG_M:M + 1) / 2. | |
11245 | IOW, if bit M is 1, the first and second S registers | |
11246 | are mapped to different D registers, otherwise, they are | |
11247 | in the same D register. */ | |
11248 | if (bit_m) | |
11249 | { | |
11250 | record_buf[arm_insn_r->reg_rec_count++] | |
11251 | = ARM_D0_REGNUM + reg_m + 1; | |
11252 | } | |
01e57735 YQ |
11253 | } |
11254 | else | |
11255 | { | |
9fde51ed | 11256 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
11257 | arm_insn_r->reg_rec_count = 1; |
11258 | } | |
11259 | } | |
f20f80dd OJ |
11260 | } |
11261 | /* Handle VSTM and VPUSH instructions. */ | |
11262 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 11263 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
11264 | { |
11265 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
11266 | uint32_t memory_index = 0; | |
11267 | ||
11268 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11269 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11270 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11271 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11272 | memory_count = imm_off8; |
11273 | ||
11274 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11275 | start_address = u_regval; |
f20f80dd | 11276 | else |
01e57735 | 11277 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11278 | |
11279 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
11280 | { |
11281 | record_buf[0] = reg_rn; | |
11282 | arm_insn_r->reg_rec_count = 1; | |
11283 | } | |
f20f80dd OJ |
11284 | |
11285 | while (memory_count > 0) | |
01e57735 | 11286 | { |
9fde51ed | 11287 | if (single_reg) |
01e57735 | 11288 | { |
9fde51ed YQ |
11289 | record_buf_mem[memory_index] = 4; |
11290 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11291 | start_address = start_address + 4; |
11292 | memory_index = memory_index + 2; | |
11293 | } | |
11294 | else | |
11295 | { | |
9fde51ed YQ |
11296 | record_buf_mem[memory_index] = 4; |
11297 | record_buf_mem[memory_index + 1] = start_address; | |
11298 | record_buf_mem[memory_index + 2] = 4; | |
11299 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11300 | start_address = start_address + 8; |
11301 | memory_index = memory_index + 4; | |
11302 | } | |
11303 | memory_count--; | |
11304 | } | |
f20f80dd OJ |
11305 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
11306 | } | |
11307 | /* Handle VLDM instructions. */ | |
11308 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 11309 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
11310 | { |
11311 | uint32_t reg_count, reg_vd; | |
11312 | uint32_t reg_index = 0; | |
9fde51ed | 11313 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
11314 | |
11315 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11316 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
11317 | ||
9fde51ed YQ |
11318 | /* REG_VD is the first D register number. If the instruction |
11319 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
11320 | number is (REG_VD << 1 | bit D), so the corresponding D | |
11321 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
11322 | if (!single_reg) | |
11323 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 11324 | |
9fde51ed | 11325 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 11326 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 11327 | |
9fde51ed YQ |
11328 | /* If the instruction loads memory to D register, REG_COUNT should |
11329 | be divided by 2, according to the ARM Architecture Reference | |
11330 | Manual. If the instruction loads memory to S register, divide by | |
11331 | 2 as well because two S registers are mapped to D register. */ | |
11332 | reg_count = reg_count / 2; | |
11333 | if (single_reg && bit_d) | |
01e57735 | 11334 | { |
9fde51ed YQ |
11335 | /* Increase the register count if S register list starts from |
11336 | an odd number (bit d is one). */ | |
11337 | reg_count++; | |
11338 | } | |
f20f80dd | 11339 | |
9fde51ed YQ |
11340 | while (reg_count > 0) |
11341 | { | |
11342 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
11343 | reg_count--; |
11344 | } | |
f20f80dd OJ |
11345 | arm_insn_r->reg_rec_count = reg_index; |
11346 | } | |
11347 | /* VSTR Vector store register. */ | |
11348 | else if ((opcode & 0x13) == 0x10) | |
11349 | { | |
bec2ab5a | 11350 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
11351 | uint32_t memory_index = 0; |
11352 | ||
11353 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11354 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11355 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11356 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11357 | |
11358 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11359 | start_address = u_regval + imm_off32; |
f20f80dd | 11360 | else |
01e57735 | 11361 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11362 | |
11363 | if (single_reg) | |
01e57735 | 11364 | { |
9fde51ed YQ |
11365 | record_buf_mem[memory_index] = 4; |
11366 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11367 | arm_insn_r->mem_rec_count = 1; |
11368 | } | |
f20f80dd | 11369 | else |
01e57735 | 11370 | { |
9fde51ed YQ |
11371 | record_buf_mem[memory_index] = 4; |
11372 | record_buf_mem[memory_index + 1] = start_address; | |
11373 | record_buf_mem[memory_index + 2] = 4; | |
11374 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11375 | arm_insn_r->mem_rec_count = 2; |
11376 | } | |
f20f80dd OJ |
11377 | } |
11378 | /* VLDR Vector load register. */ | |
11379 | else if ((opcode & 0x13) == 0x11) | |
11380 | { | |
11381 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11382 | ||
11383 | if (!single_reg) | |
01e57735 YQ |
11384 | { |
11385 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
11386 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
11387 | } | |
f20f80dd | 11388 | else |
01e57735 YQ |
11389 | { |
11390 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
11391 | /* Record register D rather than pseudo register S. */ |
11392 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 11393 | } |
f20f80dd OJ |
11394 | arm_insn_r->reg_rec_count = 1; |
11395 | } | |
11396 | ||
11397 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11398 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11399 | return 0; | |
11400 | } | |
11401 | ||
851f26ae OJ |
11402 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
11403 | ||
11404 | static int | |
11405 | arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) | |
11406 | { | |
11407 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
11408 | uint32_t record_buf[4]; | |
11409 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
11410 | enum insn_types curr_insn_type = INSN_INV; | |
11411 | ||
11412 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11413 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11414 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11415 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
11416 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
11417 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
11418 | /* Mask off the "D" bit. */ |
11419 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
11420 | |
11421 | /* Handle VMLA, VMLS. */ | |
11422 | if (opc1 == 0x00) | |
11423 | { | |
11424 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11425 | { |
11426 | if (bit (arm_insn_r->arm_insn, 6)) | |
11427 | curr_insn_type = INSN_T0; | |
11428 | else | |
11429 | curr_insn_type = INSN_T1; | |
11430 | } | |
851f26ae | 11431 | else |
dda83cd7 SM |
11432 | { |
11433 | if (dp_op_sz) | |
11434 | curr_insn_type = INSN_T1; | |
11435 | else | |
11436 | curr_insn_type = INSN_T2; | |
11437 | } | |
851f26ae OJ |
11438 | } |
11439 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
11440 | else if (opc1 == 0x01) | |
11441 | { | |
11442 | if (dp_op_sz) | |
dda83cd7 | 11443 | curr_insn_type = INSN_T1; |
851f26ae | 11444 | else |
dda83cd7 | 11445 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11446 | } |
11447 | /* Handle VMUL. */ | |
11448 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
11449 | { | |
11450 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11451 | { |
11452 | if (bit (arm_insn_r->arm_insn, 6)) | |
11453 | curr_insn_type = INSN_T0; | |
11454 | else | |
11455 | curr_insn_type = INSN_T1; | |
11456 | } | |
851f26ae | 11457 | else |
dda83cd7 SM |
11458 | { |
11459 | if (dp_op_sz) | |
11460 | curr_insn_type = INSN_T1; | |
11461 | else | |
11462 | curr_insn_type = INSN_T2; | |
11463 | } | |
851f26ae OJ |
11464 | } |
11465 | /* Handle VADD, VSUB. */ | |
11466 | else if (opc1 == 0x03) | |
11467 | { | |
11468 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
11469 | { |
11470 | if (bit (arm_insn_r->arm_insn, 6)) | |
11471 | curr_insn_type = INSN_T0; | |
11472 | else | |
11473 | curr_insn_type = INSN_T1; | |
11474 | } | |
851f26ae | 11475 | else |
dda83cd7 SM |
11476 | { |
11477 | if (dp_op_sz) | |
11478 | curr_insn_type = INSN_T1; | |
11479 | else | |
11480 | curr_insn_type = INSN_T2; | |
11481 | } | |
851f26ae OJ |
11482 | } |
11483 | /* Handle VDIV. */ | |
ce887586 | 11484 | else if (opc1 == 0x08) |
851f26ae OJ |
11485 | { |
11486 | if (dp_op_sz) | |
dda83cd7 | 11487 | curr_insn_type = INSN_T1; |
851f26ae | 11488 | else |
dda83cd7 | 11489 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11490 | } |
11491 | /* Handle all other vfp data processing instructions. */ | |
11492 | else if (opc1 == 0x0b) | |
11493 | { | |
11494 | /* Handle VMOV. */ | |
11495 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
11496 | { |
11497 | if (bit (arm_insn_r->arm_insn, 4)) | |
11498 | { | |
11499 | if (bit (arm_insn_r->arm_insn, 6)) | |
11500 | curr_insn_type = INSN_T0; | |
11501 | else | |
11502 | curr_insn_type = INSN_T1; | |
11503 | } | |
11504 | else | |
11505 | { | |
11506 | if (dp_op_sz) | |
11507 | curr_insn_type = INSN_T1; | |
11508 | else | |
11509 | curr_insn_type = INSN_T2; | |
11510 | } | |
11511 | } | |
851f26ae OJ |
11512 | /* Handle VNEG and VABS. */ |
11513 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
11514 | || (opc2 == 0x00 && opc3 == 0x03)) |
11515 | { | |
11516 | if (!bit (arm_insn_r->arm_insn, 11)) | |
11517 | { | |
11518 | if (bit (arm_insn_r->arm_insn, 6)) | |
11519 | curr_insn_type = INSN_T0; | |
11520 | else | |
11521 | curr_insn_type = INSN_T1; | |
11522 | } | |
11523 | else | |
11524 | { | |
11525 | if (dp_op_sz) | |
11526 | curr_insn_type = INSN_T1; | |
11527 | else | |
11528 | curr_insn_type = INSN_T2; | |
11529 | } | |
11530 | } | |
851f26ae OJ |
11531 | /* Handle VSQRT. */ |
11532 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
11533 | { |
11534 | if (dp_op_sz) | |
11535 | curr_insn_type = INSN_T1; | |
11536 | else | |
11537 | curr_insn_type = INSN_T2; | |
11538 | } | |
851f26ae OJ |
11539 | /* Handle VCVT. */ |
11540 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
11541 | { |
11542 | if (!dp_op_sz) | |
11543 | curr_insn_type = INSN_T1; | |
11544 | else | |
11545 | curr_insn_type = INSN_T2; | |
11546 | } | |
851f26ae | 11547 | else if (opc3 & 0x01) |
dda83cd7 SM |
11548 | { |
11549 | /* Handle VCVT. */ | |
11550 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
11551 | { | |
11552 | if (!bit (arm_insn_r->arm_insn, 18)) | |
11553 | curr_insn_type = INSN_T2; | |
11554 | else | |
11555 | { | |
11556 | if (dp_op_sz) | |
11557 | curr_insn_type = INSN_T1; | |
11558 | else | |
11559 | curr_insn_type = INSN_T2; | |
11560 | } | |
11561 | } | |
11562 | /* Handle VCVT. */ | |
11563 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
11564 | { | |
11565 | if (dp_op_sz) | |
11566 | curr_insn_type = INSN_T1; | |
11567 | else | |
11568 | curr_insn_type = INSN_T2; | |
11569 | } | |
11570 | /* Handle VCVTB, VCVTT. */ | |
11571 | else if ((opc2 & 0x0e) == 0x02) | |
11572 | curr_insn_type = INSN_T2; | |
11573 | /* Handle VCMP, VCMPE. */ | |
11574 | else if ((opc2 & 0x0e) == 0x04) | |
11575 | curr_insn_type = INSN_T3; | |
11576 | } | |
851f26ae OJ |
11577 | } |
11578 | ||
11579 | switch (curr_insn_type) | |
11580 | { | |
11581 | case INSN_T0: | |
dda83cd7 SM |
11582 | reg_vd = reg_vd | (bit_d << 4); |
11583 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11584 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
11585 | arm_insn_r->reg_rec_count = 2; | |
11586 | break; | |
851f26ae OJ |
11587 | |
11588 | case INSN_T1: | |
dda83cd7 SM |
11589 | reg_vd = reg_vd | (bit_d << 4); |
11590 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11591 | arm_insn_r->reg_rec_count = 1; | |
11592 | break; | |
851f26ae OJ |
11593 | |
11594 | case INSN_T2: | |
dda83cd7 SM |
11595 | reg_vd = (reg_vd << 1) | bit_d; |
11596 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11597 | arm_insn_r->reg_rec_count = 1; | |
11598 | break; | |
851f26ae OJ |
11599 | |
11600 | case INSN_T3: | |
dda83cd7 SM |
11601 | record_buf[0] = ARM_FPSCR_REGNUM; |
11602 | arm_insn_r->reg_rec_count = 1; | |
11603 | break; | |
851f26ae OJ |
11604 | |
11605 | default: | |
dda83cd7 SM |
11606 | gdb_assert_not_reached ("no decoding pattern found"); |
11607 | break; | |
851f26ae OJ |
11608 | } |
11609 | ||
11610 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11611 | return 0; | |
11612 | } | |
11613 | ||
60cc5e93 OJ |
11614 | /* Handling opcode 110 insns. */ |
11615 | ||
11616 | static int | |
11617 | arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) | |
11618 | { | |
bec2ab5a | 11619 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
11620 | |
11621 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
11622 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
11623 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
11624 | ||
11625 | if ((coproc & 0x0e) == 0x0a) | |
11626 | { | |
11627 | /* Handle extension register ld/st instructions. */ | |
11628 | if (!(op1 & 0x20)) | |
dda83cd7 | 11629 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11630 | |
11631 | /* 64-bit transfers between arm core and extension registers. */ | |
11632 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 11633 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11634 | } |
11635 | else | |
11636 | { | |
11637 | /* Handle coprocessor ld/st instructions. */ | |
11638 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
11639 | { |
11640 | /* Store. */ | |
11641 | if (!op1_ebit) | |
11642 | return arm_record_unsupported_insn (arm_insn_r); | |
11643 | else | |
11644 | /* Load. */ | |
11645 | return arm_record_unsupported_insn (arm_insn_r); | |
11646 | } | |
60cc5e93 OJ |
11647 | |
11648 | /* Move to coprocessor from two arm core registers. */ | |
11649 | if (op1 == 0x4) | |
dda83cd7 | 11650 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
11651 | |
11652 | /* Move to two arm core registers from coprocessor. */ | |
11653 | if (op1 == 0x5) | |
dda83cd7 SM |
11654 | { |
11655 | uint32_t reg_t[2]; | |
60cc5e93 | 11656 | |
dda83cd7 SM |
11657 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11658 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11659 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 11660 | |
dda83cd7 SM |
11661 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
11662 | return 0; | |
60cc5e93 OJ |
11663 | } |
11664 | } | |
11665 | return arm_record_unsupported_insn (arm_insn_r); | |
11666 | } | |
11667 | ||
72508ac0 PO |
11668 | /* Handling opcode 111 insns. */ |
11669 | ||
11670 | static int | |
11671 | arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) | |
11672 | { | |
2d9e6acb | 11673 | uint32_t op, op1_ebit, coproc, bits_24_25; |
72508ac0 PO |
11674 | struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); |
11675 | struct regcache *reg_cache = arm_insn_r->regcache; | |
72508ac0 PO |
11676 | |
11677 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 11678 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
11679 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
11680 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 11681 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
11682 | |
11683 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 11684 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
11685 | { |
11686 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
11687 | { |
11688 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 11689 | |
dda83cd7 | 11690 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 11691 | |
dda83cd7 SM |
11692 | if (svc_operand) /* OABI. */ |
11693 | svc_number = svc_operand - 0x900000; | |
11694 | else /* EABI. */ | |
11695 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 11696 | |
dda83cd7 SM |
11697 | return tdep->arm_syscall_record (reg_cache, svc_number); |
11698 | } | |
97dfe206 | 11699 | else |
dda83cd7 SM |
11700 | { |
11701 | printf_unfiltered (_("no syscall record support\n")); | |
11702 | return -1; | |
11703 | } | |
97dfe206 | 11704 | } |
2d9e6acb | 11705 | else if (bits_24_25 == 0x02) |
60cc5e93 | 11706 | { |
2d9e6acb YQ |
11707 | if (op) |
11708 | { | |
11709 | if ((coproc & 0x0e) == 0x0a) | |
11710 | { | |
11711 | /* 8, 16, and 32-bit transfer */ | |
11712 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
11713 | } | |
11714 | else | |
11715 | { | |
11716 | if (op1_ebit) | |
11717 | { | |
11718 | /* MRC, MRC2 */ | |
11719 | uint32_t record_buf[1]; | |
11720 | ||
11721 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11722 | if (record_buf[0] == 15) | |
11723 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 11724 | |
2d9e6acb YQ |
11725 | arm_insn_r->reg_rec_count = 1; |
11726 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
11727 | record_buf); | |
11728 | return 0; | |
11729 | } | |
11730 | else | |
11731 | { | |
11732 | /* MCR, MCR2 */ | |
11733 | return -1; | |
11734 | } | |
11735 | } | |
11736 | } | |
11737 | else | |
11738 | { | |
11739 | if ((coproc & 0x0e) == 0x0a) | |
11740 | { | |
11741 | /* VFP data-processing instructions. */ | |
11742 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
11743 | } | |
11744 | else | |
11745 | { | |
11746 | /* CDP, CDP2 */ | |
11747 | return -1; | |
11748 | } | |
11749 | } | |
60cc5e93 | 11750 | } |
97dfe206 OJ |
11751 | else |
11752 | { | |
2d9e6acb | 11753 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 11754 | |
2d9e6acb YQ |
11755 | if (op1 == 5) |
11756 | { | |
11757 | if ((coproc & 0x0e) != 0x0a) | |
11758 | { | |
11759 | /* MRRC, MRRC2 */ | |
11760 | return -1; | |
11761 | } | |
11762 | } | |
11763 | else if (op1 == 4 || op1 == 5) | |
11764 | { | |
11765 | if ((coproc & 0x0e) == 0x0a) | |
11766 | { | |
11767 | /* 64-bit transfers between ARM core and extension */ | |
11768 | return -1; | |
11769 | } | |
11770 | else if (op1 == 4) | |
11771 | { | |
11772 | /* MCRR, MCRR2 */ | |
11773 | return -1; | |
11774 | } | |
11775 | } | |
11776 | else if (op1 == 0 || op1 == 1) | |
11777 | { | |
11778 | /* UNDEFINED */ | |
11779 | return -1; | |
11780 | } | |
11781 | else | |
11782 | { | |
11783 | if ((coproc & 0x0e) == 0x0a) | |
11784 | { | |
11785 | /* Extension register load/store */ | |
11786 | } | |
11787 | else | |
11788 | { | |
11789 | /* STC, STC2, LDC, LDC2 */ | |
11790 | } | |
11791 | return -1; | |
11792 | } | |
97dfe206 | 11793 | } |
72508ac0 | 11794 | |
2d9e6acb | 11795 | return -1; |
72508ac0 PO |
11796 | } |
11797 | ||
11798 | /* Handling opcode 000 insns. */ | |
11799 | ||
11800 | static int | |
11801 | thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) | |
11802 | { | |
11803 | uint32_t record_buf[8]; | |
11804 | uint32_t reg_src1 = 0; | |
11805 | ||
11806 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11807 | ||
11808 | record_buf[0] = ARM_PS_REGNUM; | |
11809 | record_buf[1] = reg_src1; | |
11810 | thumb_insn_r->reg_rec_count = 2; | |
11811 | ||
11812 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11813 | ||
11814 | return 0; | |
11815 | } | |
11816 | ||
11817 | ||
11818 | /* Handling opcode 001 insns. */ | |
11819 | ||
11820 | static int | |
11821 | thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) | |
11822 | { | |
11823 | uint32_t record_buf[8]; | |
11824 | uint32_t reg_src1 = 0; | |
11825 | ||
11826 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11827 | ||
11828 | record_buf[0] = ARM_PS_REGNUM; | |
11829 | record_buf[1] = reg_src1; | |
11830 | thumb_insn_r->reg_rec_count = 2; | |
11831 | ||
11832 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11833 | ||
11834 | return 0; | |
11835 | } | |
11836 | ||
11837 | /* Handling opcode 010 insns. */ | |
11838 | ||
11839 | static int | |
11840 | thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) | |
11841 | { | |
11842 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11843 | uint32_t record_buf[8], record_buf_mem[8]; | |
11844 | ||
11845 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
11846 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
11847 | ||
11848 | ULONGEST u_regval[2] = {0}; | |
11849 | ||
11850 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
11851 | ||
11852 | if (bit (thumb_insn_r->arm_insn, 12)) | |
11853 | { | |
11854 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
11855 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
11856 | ||
b020ff80 | 11857 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
11858 | { |
11859 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
11860 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
11861 | record_buf[0] = reg_src1; | |
11862 | thumb_insn_r->reg_rec_count = 1; | |
11863 | } | |
b020ff80 | 11864 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
11865 | { |
11866 | /* STR(2), STRB(2), STRH(2) . */ | |
11867 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11868 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
11869 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11870 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11871 | if (0 == opB) | |
11872 | record_buf_mem[0] = 4; /* STR (2). */ | |
11873 | else if (2 == opB) | |
11874 | record_buf_mem[0] = 1; /* STRB (2). */ | |
11875 | else if (1 == opB) | |
11876 | record_buf_mem[0] = 2; /* STRH (2). */ | |
11877 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
11878 | thumb_insn_r->mem_rec_count = 1; | |
11879 | } | |
72508ac0 PO |
11880 | } |
11881 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
11882 | { | |
11883 | /* Handle load from literal pool. */ | |
11884 | /* LDR(3). */ | |
11885 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11886 | record_buf[0] = reg_src1; | |
11887 | thumb_insn_r->reg_rec_count = 1; | |
11888 | } | |
11889 | else if (opcode1) | |
11890 | { | |
b121eeb9 | 11891 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
11892 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
11893 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11894 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
11895 | { |
11896 | /* Branch with exchange. */ | |
11897 | record_buf[0] = ARM_PS_REGNUM; | |
11898 | thumb_insn_r->reg_rec_count = 1; | |
11899 | } | |
72508ac0 | 11900 | else |
dda83cd7 | 11901 | { |
1f33efec YQ |
11902 | /* Format 8; special data processing insns. */ |
11903 | record_buf[0] = ARM_PS_REGNUM; | |
11904 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
11905 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
11906 | thumb_insn_r->reg_rec_count = 2; |
11907 | } | |
72508ac0 PO |
11908 | } |
11909 | else | |
11910 | { | |
11911 | /* Format 5; data processing insns. */ | |
11912 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11913 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
11914 | { |
11915 | reg_src1 = reg_src1 + 8; | |
11916 | } | |
72508ac0 PO |
11917 | record_buf[0] = ARM_PS_REGNUM; |
11918 | record_buf[1] = reg_src1; | |
11919 | thumb_insn_r->reg_rec_count = 2; | |
11920 | } | |
11921 | ||
11922 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11923 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 11924 | record_buf_mem); |
72508ac0 PO |
11925 | |
11926 | return 0; | |
11927 | } | |
11928 | ||
11929 | /* Handling opcode 001 insns. */ | |
11930 | ||
11931 | static int | |
11932 | thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) | |
11933 | { | |
11934 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11935 | uint32_t record_buf[8], record_buf_mem[8]; | |
11936 | ||
11937 | uint32_t reg_src1 = 0; | |
11938 | uint32_t opcode = 0, immed_5 = 0; | |
11939 | ||
11940 | ULONGEST u_regval = 0; | |
11941 | ||
11942 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11943 | ||
11944 | if (opcode) | |
11945 | { | |
11946 | /* LDR(1). */ | |
11947 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11948 | record_buf[0] = reg_src1; | |
11949 | thumb_insn_r->reg_rec_count = 1; | |
11950 | } | |
11951 | else | |
11952 | { | |
11953 | /* STR(1). */ | |
11954 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11955 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
11956 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11957 | record_buf_mem[0] = 4; | |
11958 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
11959 | thumb_insn_r->mem_rec_count = 1; | |
11960 | } | |
11961 | ||
11962 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11963 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 11964 | record_buf_mem); |
72508ac0 PO |
11965 | |
11966 | return 0; | |
11967 | } | |
11968 | ||
11969 | /* Handling opcode 100 insns. */ | |
11970 | ||
11971 | static int | |
11972 | thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) | |
11973 | { | |
11974 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11975 | uint32_t record_buf[8], record_buf_mem[8]; | |
11976 | ||
11977 | uint32_t reg_src1 = 0; | |
11978 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
11979 | ||
11980 | ULONGEST u_regval = 0; | |
11981 | ||
11982 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11983 | ||
11984 | if (3 == opcode) | |
11985 | { | |
11986 | /* LDR(4). */ | |
11987 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11988 | record_buf[0] = reg_src1; | |
11989 | thumb_insn_r->reg_rec_count = 1; | |
11990 | } | |
11991 | else if (1 == opcode) | |
11992 | { | |
11993 | /* LDRH(1). */ | |
11994 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11995 | record_buf[0] = reg_src1; | |
11996 | thumb_insn_r->reg_rec_count = 1; | |
11997 | } | |
11998 | else if (2 == opcode) | |
11999 | { | |
12000 | /* STR(3). */ | |
12001 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
12002 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12003 | record_buf_mem[0] = 4; | |
12004 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
12005 | thumb_insn_r->mem_rec_count = 1; | |
12006 | } | |
12007 | else if (0 == opcode) | |
12008 | { | |
12009 | /* STRH(1). */ | |
12010 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12011 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12012 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12013 | record_buf_mem[0] = 2; | |
12014 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
12015 | thumb_insn_r->mem_rec_count = 1; | |
12016 | } | |
12017 | ||
12018 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12019 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12020 | record_buf_mem); |
72508ac0 PO |
12021 | |
12022 | return 0; | |
12023 | } | |
12024 | ||
12025 | /* Handling opcode 101 insns. */ | |
12026 | ||
12027 | static int | |
12028 | thumb_record_misc (insn_decode_record *thumb_insn_r) | |
12029 | { | |
12030 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12031 | ||
b121eeb9 | 12032 | uint32_t opcode = 0; |
72508ac0 | 12033 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 12034 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12035 | uint32_t record_buf[24], record_buf_mem[48]; |
12036 | uint32_t reg_src1; | |
12037 | ||
12038 | ULONGEST u_regval = 0; | |
12039 | ||
12040 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 12041 | |
b121eeb9 | 12042 | if (opcode == 0 || opcode == 1) |
72508ac0 | 12043 | { |
b121eeb9 YQ |
12044 | /* ADR and ADD (SP plus immediate) */ |
12045 | ||
72508ac0 PO |
12046 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
12047 | record_buf[0] = reg_src1; | |
12048 | thumb_insn_r->reg_rec_count = 1; | |
12049 | } | |
b121eeb9 | 12050 | else |
72508ac0 | 12051 | { |
b121eeb9 YQ |
12052 | /* Miscellaneous 16-bit instructions */ |
12053 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
12054 | ||
12055 | switch (opcode2) | |
12056 | { | |
12057 | case 6: | |
12058 | /* SETEND and CPS */ | |
12059 | break; | |
12060 | case 0: | |
12061 | /* ADD/SUB (SP plus immediate) */ | |
12062 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12063 | record_buf[0] = ARM_SP_REGNUM; | |
12064 | thumb_insn_r->reg_rec_count = 1; | |
12065 | break; | |
12066 | case 1: /* fall through */ | |
12067 | case 3: /* fall through */ | |
12068 | case 9: /* fall through */ | |
12069 | case 11: | |
12070 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
12071 | break; |
12072 | case 2: | |
12073 | /* SXTH, SXTB, UXTH, UXTB */ | |
12074 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
12075 | thumb_insn_r->reg_rec_count = 1; | |
12076 | break; | |
12077 | case 4: /* fall through */ | |
12078 | case 5: | |
12079 | /* PUSH. */ | |
12080 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12081 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12082 | while (register_bits) | |
12083 | { | |
12084 | if (register_bits & 0x00000001) | |
12085 | register_count++; | |
12086 | register_bits = register_bits >> 1; | |
12087 | } | |
12088 | start_address = u_regval - \ | |
12089 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
12090 | thumb_insn_r->mem_rec_count = register_count; | |
12091 | while (register_count) | |
12092 | { | |
12093 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12094 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12095 | start_address = start_address + 4; | |
12096 | register_count--; | |
12097 | } | |
12098 | record_buf[0] = ARM_SP_REGNUM; | |
12099 | thumb_insn_r->reg_rec_count = 1; | |
12100 | break; | |
12101 | case 10: | |
12102 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
12103 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
12104 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
12105 | break; |
12106 | case 12: /* fall through */ | |
12107 | case 13: | |
12108 | /* POP. */ | |
12109 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12110 | while (register_bits) | |
12111 | { | |
12112 | if (register_bits & 0x00000001) | |
12113 | record_buf[index++] = register_count; | |
12114 | register_bits = register_bits >> 1; | |
12115 | register_count++; | |
12116 | } | |
12117 | record_buf[index++] = ARM_PS_REGNUM; | |
12118 | record_buf[index++] = ARM_SP_REGNUM; | |
12119 | thumb_insn_r->reg_rec_count = index; | |
12120 | break; | |
12121 | case 0xe: | |
12122 | /* BKPT insn. */ | |
12123 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
12124 | /* CPSR is changed to be executed in ARM state, disabling normal | |
12125 | interrupts, entering abort mode. */ | |
12126 | /* According to high vector configuration PC is set. */ | |
12127 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
12128 | previous CPSR and Program Counter. */ | |
12129 | record_buf[0] = ARM_PS_REGNUM; | |
12130 | record_buf[1] = ARM_LR_REGNUM; | |
12131 | thumb_insn_r->reg_rec_count = 2; | |
12132 | /* We need to save SPSR value, which is not yet done. */ | |
12133 | printf_unfiltered (_("Process record does not support instruction " | |
12134 | "0x%0x at address %s.\n"), | |
12135 | thumb_insn_r->arm_insn, | |
12136 | paddress (thumb_insn_r->gdbarch, | |
12137 | thumb_insn_r->this_addr)); | |
12138 | return -1; | |
12139 | ||
12140 | case 0xf: | |
12141 | /* If-Then, and hints */ | |
12142 | break; | |
12143 | default: | |
12144 | return -1; | |
12145 | }; | |
72508ac0 PO |
12146 | } |
12147 | ||
12148 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12149 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12150 | record_buf_mem); |
72508ac0 PO |
12151 | |
12152 | return 0; | |
12153 | } | |
12154 | ||
12155 | /* Handling opcode 110 insns. */ | |
12156 | ||
12157 | static int | |
12158 | thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) | |
12159 | { | |
12160 | struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch); | |
12161 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12162 | ||
12163 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
12164 | uint32_t reg_src1 = 0; | |
12165 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 12166 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12167 | uint32_t record_buf[24], record_buf_mem[48]; |
12168 | ||
12169 | ULONGEST u_regval = 0; | |
12170 | ||
12171 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
12172 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
12173 | ||
12174 | if (1 == opcode2) | |
12175 | { | |
12176 | ||
12177 | /* LDMIA. */ | |
12178 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12179 | /* Get Rn. */ | |
12180 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12181 | while (register_bits) | |
dda83cd7 SM |
12182 | { |
12183 | if (register_bits & 0x00000001) | |
12184 | record_buf[index++] = register_count; | |
12185 | register_bits = register_bits >> 1; | |
12186 | register_count++; | |
12187 | } | |
f969241e OJ |
12188 | record_buf[index++] = reg_src1; |
12189 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
12190 | } |
12191 | else if (0 == opcode2) | |
12192 | { | |
12193 | /* It handles both STMIA. */ | |
12194 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12195 | /* Get Rn. */ | |
12196 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12197 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12198 | while (register_bits) | |
dda83cd7 SM |
12199 | { |
12200 | if (register_bits & 0x00000001) | |
12201 | register_count++; | |
12202 | register_bits = register_bits >> 1; | |
12203 | } | |
72508ac0 PO |
12204 | start_address = u_regval; |
12205 | thumb_insn_r->mem_rec_count = register_count; | |
12206 | while (register_count) | |
dda83cd7 SM |
12207 | { |
12208 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12209 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12210 | start_address = start_address + 4; | |
12211 | register_count--; | |
12212 | } | |
72508ac0 PO |
12213 | } |
12214 | else if (0x1F == opcode1) | |
12215 | { | |
dda83cd7 SM |
12216 | /* Handle arm syscall insn. */ |
12217 | if (tdep->arm_syscall_record != NULL) | |
12218 | { | |
12219 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
12220 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
12221 | } | |
12222 | else | |
12223 | { | |
12224 | printf_unfiltered (_("no syscall record support\n")); | |
12225 | return -1; | |
12226 | } | |
72508ac0 PO |
12227 | } |
12228 | ||
12229 | /* B (1), conditional branch is automatically taken care in process_record, | |
12230 | as PC is saved there. */ | |
12231 | ||
12232 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12233 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12234 | record_buf_mem); |
72508ac0 PO |
12235 | |
12236 | return ret; | |
12237 | } | |
12238 | ||
12239 | /* Handling opcode 111 insns. */ | |
12240 | ||
12241 | static int | |
12242 | thumb_record_branch (insn_decode_record *thumb_insn_r) | |
12243 | { | |
12244 | uint32_t record_buf[8]; | |
12245 | uint32_t bits_h = 0; | |
12246 | ||
12247 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
12248 | ||
12249 | if (2 == bits_h || 3 == bits_h) | |
12250 | { | |
12251 | /* BL */ | |
12252 | record_buf[0] = ARM_LR_REGNUM; | |
12253 | thumb_insn_r->reg_rec_count = 1; | |
12254 | } | |
12255 | else if (1 == bits_h) | |
12256 | { | |
12257 | /* BLX(1). */ | |
12258 | record_buf[0] = ARM_PS_REGNUM; | |
12259 | record_buf[1] = ARM_LR_REGNUM; | |
12260 | thumb_insn_r->reg_rec_count = 2; | |
12261 | } | |
12262 | ||
12263 | /* B(2) is automatically taken care in process_record, as PC is | |
12264 | saved there. */ | |
12265 | ||
12266 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12267 | ||
12268 | return 0; | |
12269 | } | |
12270 | ||
c6ec2b30 OJ |
12271 | /* Handler for thumb2 load/store multiple instructions. */ |
12272 | ||
12273 | static int | |
12274 | thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) | |
12275 | { | |
12276 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12277 | ||
12278 | uint32_t reg_rn, op; | |
12279 | uint32_t register_bits = 0, register_count = 0; | |
12280 | uint32_t index = 0, start_address = 0; | |
12281 | uint32_t record_buf[24], record_buf_mem[48]; | |
12282 | ||
12283 | ULONGEST u_regval = 0; | |
12284 | ||
12285 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12286 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12287 | ||
12288 | if (0 == op || 3 == op) | |
12289 | { | |
12290 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12291 | { |
12292 | /* Handle RFE instruction. */ | |
12293 | record_buf[0] = ARM_PS_REGNUM; | |
12294 | thumb2_insn_r->reg_rec_count = 1; | |
12295 | } | |
c6ec2b30 | 12296 | else |
dda83cd7 SM |
12297 | { |
12298 | /* Handle SRS instruction after reading banked SP. */ | |
12299 | return arm_record_unsupported_insn (thumb2_insn_r); | |
12300 | } | |
c6ec2b30 OJ |
12301 | } |
12302 | else if (1 == op || 2 == op) | |
12303 | { | |
12304 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12305 | { |
12306 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
12307 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12308 | while (register_bits) | |
12309 | { | |
12310 | if (register_bits & 0x00000001) | |
12311 | record_buf[index++] = register_count; | |
12312 | ||
12313 | register_count++; | |
12314 | register_bits = register_bits >> 1; | |
12315 | } | |
12316 | record_buf[index++] = reg_rn; | |
12317 | record_buf[index++] = ARM_PS_REGNUM; | |
12318 | thumb2_insn_r->reg_rec_count = index; | |
12319 | } | |
c6ec2b30 | 12320 | else |
dda83cd7 SM |
12321 | { |
12322 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
12323 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12324 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12325 | while (register_bits) | |
12326 | { | |
12327 | if (register_bits & 0x00000001) | |
12328 | register_count++; | |
12329 | ||
12330 | register_bits = register_bits >> 1; | |
12331 | } | |
12332 | ||
12333 | if (1 == op) | |
12334 | { | |
12335 | /* Start address calculation for LDMDB/LDMEA. */ | |
12336 | start_address = u_regval; | |
12337 | } | |
12338 | else if (2 == op) | |
12339 | { | |
12340 | /* Start address calculation for LDMDB/LDMEA. */ | |
12341 | start_address = u_regval - register_count * 4; | |
12342 | } | |
12343 | ||
12344 | thumb2_insn_r->mem_rec_count = register_count; | |
12345 | while (register_count) | |
12346 | { | |
12347 | record_buf_mem[register_count * 2 - 1] = start_address; | |
12348 | record_buf_mem[register_count * 2 - 2] = 4; | |
12349 | start_address = start_address + 4; | |
12350 | register_count--; | |
12351 | } | |
12352 | record_buf[0] = reg_rn; | |
12353 | record_buf[1] = ARM_PS_REGNUM; | |
12354 | thumb2_insn_r->reg_rec_count = 2; | |
12355 | } | |
c6ec2b30 OJ |
12356 | } |
12357 | ||
12358 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 12359 | record_buf_mem); |
c6ec2b30 | 12360 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 12361 | record_buf); |
c6ec2b30 OJ |
12362 | return ARM_RECORD_SUCCESS; |
12363 | } | |
12364 | ||
12365 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
12366 | instructions. */ | |
12367 | ||
12368 | static int | |
12369 | thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) | |
12370 | { | |
12371 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12372 | ||
12373 | uint32_t reg_rd, reg_rn, offset_imm; | |
12374 | uint32_t reg_dest1, reg_dest2; | |
12375 | uint32_t address, offset_addr; | |
12376 | uint32_t record_buf[8], record_buf_mem[8]; | |
12377 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
12378 | |
12379 | ULONGEST u_regval[2]; | |
12380 | ||
12381 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12382 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
12383 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12384 | ||
12385 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12386 | { | |
12387 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
12388 | { |
12389 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12390 | record_buf[0] = reg_dest1; | |
12391 | record_buf[1] = ARM_PS_REGNUM; | |
12392 | thumb2_insn_r->reg_rec_count = 2; | |
12393 | } | |
c6ec2b30 OJ |
12394 | |
12395 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
12396 | { |
12397 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12398 | record_buf[2] = reg_dest2; | |
12399 | thumb2_insn_r->reg_rec_count = 3; | |
12400 | } | |
c6ec2b30 OJ |
12401 | } |
12402 | else | |
12403 | { | |
12404 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12405 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12406 | ||
12407 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
12408 | { |
12409 | /* Handle STREX. */ | |
12410 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12411 | address = u_regval[0] + (offset_imm * 4); | |
12412 | record_buf_mem[0] = 4; | |
12413 | record_buf_mem[1] = address; | |
12414 | thumb2_insn_r->mem_rec_count = 1; | |
12415 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12416 | record_buf[0] = reg_rd; | |
12417 | thumb2_insn_r->reg_rec_count = 1; | |
12418 | } | |
c6ec2b30 | 12419 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
12420 | { |
12421 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12422 | record_buf[0] = reg_rd; | |
12423 | thumb2_insn_r->reg_rec_count = 1; | |
12424 | address = u_regval[0]; | |
12425 | record_buf_mem[1] = address; | |
12426 | ||
12427 | if (4 == op3) | |
12428 | { | |
12429 | /* Handle STREXB. */ | |
12430 | record_buf_mem[0] = 1; | |
12431 | thumb2_insn_r->mem_rec_count = 1; | |
12432 | } | |
12433 | else if (5 == op3) | |
12434 | { | |
12435 | /* Handle STREXH. */ | |
12436 | record_buf_mem[0] = 2 ; | |
12437 | thumb2_insn_r->mem_rec_count = 1; | |
12438 | } | |
12439 | else if (7 == op3) | |
12440 | { | |
12441 | /* Handle STREXD. */ | |
12442 | address = u_regval[0]; | |
12443 | record_buf_mem[0] = 4; | |
12444 | record_buf_mem[2] = 4; | |
12445 | record_buf_mem[3] = address + 4; | |
12446 | thumb2_insn_r->mem_rec_count = 2; | |
12447 | } | |
12448 | } | |
c6ec2b30 | 12449 | else |
dda83cd7 SM |
12450 | { |
12451 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12452 | ||
12453 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
12454 | { | |
12455 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12456 | offset_addr = u_regval[0] + (offset_imm * 4); | |
12457 | else | |
12458 | offset_addr = u_regval[0] - (offset_imm * 4); | |
12459 | ||
12460 | address = offset_addr; | |
12461 | } | |
12462 | else | |
12463 | address = u_regval[0]; | |
12464 | ||
12465 | record_buf_mem[0] = 4; | |
12466 | record_buf_mem[1] = address; | |
12467 | record_buf_mem[2] = 4; | |
12468 | record_buf_mem[3] = address + 4; | |
12469 | thumb2_insn_r->mem_rec_count = 2; | |
12470 | record_buf[0] = reg_rn; | |
12471 | thumb2_insn_r->reg_rec_count = 1; | |
12472 | } | |
c6ec2b30 OJ |
12473 | } |
12474 | ||
12475 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12476 | record_buf); |
c6ec2b30 | 12477 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12478 | record_buf_mem); |
c6ec2b30 OJ |
12479 | return ARM_RECORD_SUCCESS; |
12480 | } | |
12481 | ||
12482 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
12483 | instructions. */ | |
12484 | ||
12485 | static int | |
12486 | thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) | |
12487 | { | |
12488 | uint32_t reg_rd, op; | |
12489 | uint32_t record_buf[8]; | |
12490 | ||
12491 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
12492 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12493 | ||
12494 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
12495 | { | |
12496 | record_buf[0] = ARM_PS_REGNUM; | |
12497 | thumb2_insn_r->reg_rec_count = 1; | |
12498 | } | |
12499 | else | |
12500 | { | |
12501 | record_buf[0] = reg_rd; | |
12502 | record_buf[1] = ARM_PS_REGNUM; | |
12503 | thumb2_insn_r->reg_rec_count = 2; | |
12504 | } | |
12505 | ||
12506 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12507 | record_buf); |
c6ec2b30 OJ |
12508 | return ARM_RECORD_SUCCESS; |
12509 | } | |
12510 | ||
12511 | /* Generic handler for thumb2 instructions which effect destination and PS | |
12512 | registers. */ | |
12513 | ||
12514 | static int | |
12515 | thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) | |
12516 | { | |
12517 | uint32_t reg_rd; | |
12518 | uint32_t record_buf[8]; | |
12519 | ||
12520 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12521 | ||
12522 | record_buf[0] = reg_rd; | |
12523 | record_buf[1] = ARM_PS_REGNUM; | |
12524 | thumb2_insn_r->reg_rec_count = 2; | |
12525 | ||
12526 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12527 | record_buf); |
c6ec2b30 OJ |
12528 | return ARM_RECORD_SUCCESS; |
12529 | } | |
12530 | ||
12531 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
12532 | ||
12533 | static int | |
12534 | thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) | |
12535 | { | |
12536 | uint32_t op, op1, op2; | |
12537 | uint32_t record_buf[8]; | |
12538 | ||
12539 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12540 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
12541 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12542 | ||
12543 | /* Handle MSR insn. */ | |
12544 | if (!(op1 & 0x2) && 0x38 == op) | |
12545 | { | |
12546 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
12547 | { |
12548 | /* CPSR is going to be changed. */ | |
12549 | record_buf[0] = ARM_PS_REGNUM; | |
12550 | thumb2_insn_r->reg_rec_count = 1; | |
12551 | } | |
c6ec2b30 | 12552 | else |
dda83cd7 SM |
12553 | { |
12554 | arm_record_unsupported_insn(thumb2_insn_r); | |
12555 | return -1; | |
12556 | } | |
c6ec2b30 OJ |
12557 | } |
12558 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
12559 | { | |
12560 | /* BLX. */ | |
12561 | record_buf[0] = ARM_PS_REGNUM; | |
12562 | record_buf[1] = ARM_LR_REGNUM; | |
12563 | thumb2_insn_r->reg_rec_count = 2; | |
12564 | } | |
12565 | ||
12566 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12567 | record_buf); |
c6ec2b30 OJ |
12568 | return ARM_RECORD_SUCCESS; |
12569 | } | |
12570 | ||
12571 | /* Handler for thumb2 store single data item instructions. */ | |
12572 | ||
12573 | static int | |
12574 | thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) | |
12575 | { | |
12576 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12577 | ||
12578 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
12579 | uint32_t address, offset_addr; | |
12580 | uint32_t record_buf[8], record_buf_mem[8]; | |
12581 | uint32_t op1, op2; | |
12582 | ||
12583 | ULONGEST u_regval[2]; | |
12584 | ||
12585 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
12586 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
12587 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12588 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12589 | ||
12590 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12591 | { | |
12592 | /* T2 encoding. */ | |
12593 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
12594 | offset_addr = u_regval[0] + offset_imm; | |
12595 | address = offset_addr; | |
12596 | } | |
12597 | else | |
12598 | { | |
12599 | /* T3 encoding. */ | |
12600 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
12601 | { |
12602 | /* Handle STRB (register). */ | |
12603 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12604 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
12605 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
12606 | offset_addr = u_regval[1] << shift_imm; | |
12607 | address = u_regval[0] + offset_addr; | |
12608 | } | |
c6ec2b30 | 12609 | else |
dda83cd7 SM |
12610 | { |
12611 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12612 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
12613 | { | |
12614 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
12615 | offset_addr = u_regval[0] + offset_imm; | |
12616 | else | |
12617 | offset_addr = u_regval[0] - offset_imm; | |
12618 | ||
12619 | address = offset_addr; | |
12620 | } | |
12621 | else | |
12622 | address = u_regval[0]; | |
12623 | } | |
c6ec2b30 OJ |
12624 | } |
12625 | ||
12626 | switch (op1) | |
12627 | { | |
12628 | /* Store byte instructions. */ | |
12629 | case 4: | |
12630 | case 0: | |
dda83cd7 SM |
12631 | record_buf_mem[0] = 1; |
12632 | break; | |
c6ec2b30 OJ |
12633 | /* Store half word instructions. */ |
12634 | case 1: | |
12635 | case 5: | |
dda83cd7 SM |
12636 | record_buf_mem[0] = 2; |
12637 | break; | |
c6ec2b30 OJ |
12638 | /* Store word instructions. */ |
12639 | case 2: | |
12640 | case 6: | |
dda83cd7 SM |
12641 | record_buf_mem[0] = 4; |
12642 | break; | |
c6ec2b30 OJ |
12643 | |
12644 | default: | |
dda83cd7 SM |
12645 | gdb_assert_not_reached ("no decoding pattern found"); |
12646 | break; | |
c6ec2b30 OJ |
12647 | } |
12648 | ||
12649 | record_buf_mem[1] = address; | |
12650 | thumb2_insn_r->mem_rec_count = 1; | |
12651 | record_buf[0] = reg_rn; | |
12652 | thumb2_insn_r->reg_rec_count = 1; | |
12653 | ||
12654 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12655 | record_buf); |
c6ec2b30 | 12656 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12657 | record_buf_mem); |
c6ec2b30 OJ |
12658 | return ARM_RECORD_SUCCESS; |
12659 | } | |
12660 | ||
12661 | /* Handler for thumb2 load memory hints instructions. */ | |
12662 | ||
12663 | static int | |
12664 | thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) | |
12665 | { | |
12666 | uint32_t record_buf[8]; | |
12667 | uint32_t reg_rt, reg_rn; | |
12668 | ||
12669 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12670 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12671 | ||
12672 | if (ARM_PC_REGNUM != reg_rt) | |
12673 | { | |
12674 | record_buf[0] = reg_rt; | |
12675 | record_buf[1] = reg_rn; | |
12676 | record_buf[2] = ARM_PS_REGNUM; | |
12677 | thumb2_insn_r->reg_rec_count = 3; | |
12678 | ||
12679 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12680 | record_buf); |
c6ec2b30 OJ |
12681 | return ARM_RECORD_SUCCESS; |
12682 | } | |
12683 | ||
12684 | return ARM_RECORD_FAILURE; | |
12685 | } | |
12686 | ||
12687 | /* Handler for thumb2 load word instructions. */ | |
12688 | ||
12689 | static int | |
12690 | thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) | |
12691 | { | |
c6ec2b30 OJ |
12692 | uint32_t record_buf[8]; |
12693 | ||
12694 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12695 | record_buf[1] = ARM_PS_REGNUM; | |
12696 | thumb2_insn_r->reg_rec_count = 2; | |
12697 | ||
12698 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12699 | record_buf); |
c6ec2b30 OJ |
12700 | return ARM_RECORD_SUCCESS; |
12701 | } | |
12702 | ||
12703 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
12704 | divide instructions. */ | |
12705 | ||
12706 | static int | |
12707 | thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) | |
12708 | { | |
12709 | uint32_t opcode1 = 0, opcode2 = 0; | |
12710 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
12711 | |
12712 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
12713 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12714 | ||
12715 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
12716 | { | |
12717 | /* Handle SMULL, UMULL, SMULAL. */ | |
12718 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
12719 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12720 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12721 | record_buf[2] = ARM_PS_REGNUM; | |
12722 | thumb2_insn_r->reg_rec_count = 3; | |
12723 | } | |
12724 | else if (1 == opcode1 || 3 == opcode2) | |
12725 | { | |
12726 | /* Handle SDIV and UDIV. */ | |
12727 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12728 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12729 | record_buf[2] = ARM_PS_REGNUM; | |
12730 | thumb2_insn_r->reg_rec_count = 3; | |
12731 | } | |
12732 | else | |
12733 | return ARM_RECORD_FAILURE; | |
12734 | ||
12735 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12736 | record_buf); |
c6ec2b30 OJ |
12737 | return ARM_RECORD_SUCCESS; |
12738 | } | |
12739 | ||
60cc5e93 OJ |
12740 | /* Record handler for thumb32 coprocessor instructions. */ |
12741 | ||
12742 | static int | |
12743 | thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) | |
12744 | { | |
12745 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
12746 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
12747 | else | |
12748 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
12749 | } | |
12750 | ||
1e1b6563 OJ |
12751 | /* Record handler for advance SIMD structure load/store instructions. */ |
12752 | ||
12753 | static int | |
12754 | thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) | |
12755 | { | |
12756 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12757 | uint32_t l_bit, a_bit, b_bits; | |
12758 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 12759 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
12760 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
12761 | uint8_t f_ebytes; | |
12762 | ||
12763 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
12764 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
12765 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12766 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12767 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12768 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
12769 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
12770 | f_elem = 8 / f_ebytes; |
12771 | ||
12772 | if (!l_bit) | |
12773 | { | |
12774 | ULONGEST u_regval = 0; | |
12775 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12776 | address = u_regval; | |
12777 | ||
12778 | if (!a_bit) | |
dda83cd7 SM |
12779 | { |
12780 | /* Handle VST1. */ | |
12781 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12782 | { | |
12783 | if (b_bits == 0x07) | |
12784 | bf_regs = 1; | |
12785 | else if (b_bits == 0x0a) | |
12786 | bf_regs = 2; | |
12787 | else if (b_bits == 0x06) | |
12788 | bf_regs = 3; | |
12789 | else if (b_bits == 0x02) | |
12790 | bf_regs = 4; | |
12791 | else | |
12792 | bf_regs = 0; | |
12793 | ||
12794 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12795 | { | |
12796 | for (index_e = 0; index_e < f_elem; index_e++) | |
12797 | { | |
12798 | record_buf_mem[index_m++] = f_ebytes; | |
12799 | record_buf_mem[index_m++] = address; | |
12800 | address = address + f_ebytes; | |
12801 | thumb2_insn_r->mem_rec_count += 1; | |
12802 | } | |
12803 | } | |
12804 | } | |
12805 | /* Handle VST2. */ | |
12806 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12807 | { | |
12808 | if (b_bits == 0x09 || b_bits == 0x08) | |
12809 | bf_regs = 1; | |
12810 | else if (b_bits == 0x03) | |
12811 | bf_regs = 2; | |
12812 | else | |
12813 | bf_regs = 0; | |
12814 | ||
12815 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12816 | for (index_e = 0; index_e < f_elem; index_e++) | |
12817 | { | |
12818 | for (loop_t = 0; loop_t < 2; loop_t++) | |
12819 | { | |
12820 | record_buf_mem[index_m++] = f_ebytes; | |
12821 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12822 | thumb2_insn_r->mem_rec_count += 1; | |
12823 | } | |
12824 | address = address + (2 * f_ebytes); | |
12825 | } | |
12826 | } | |
12827 | /* Handle VST3. */ | |
12828 | else if ((b_bits & 0x0e) == 0x04) | |
12829 | { | |
12830 | for (index_e = 0; index_e < f_elem; index_e++) | |
12831 | { | |
12832 | for (loop_t = 0; loop_t < 3; loop_t++) | |
12833 | { | |
12834 | record_buf_mem[index_m++] = f_ebytes; | |
12835 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12836 | thumb2_insn_r->mem_rec_count += 1; | |
12837 | } | |
12838 | address = address + (3 * f_ebytes); | |
12839 | } | |
12840 | } | |
12841 | /* Handle VST4. */ | |
12842 | else if (!(b_bits & 0x0e)) | |
12843 | { | |
12844 | for (index_e = 0; index_e < f_elem; index_e++) | |
12845 | { | |
12846 | for (loop_t = 0; loop_t < 4; loop_t++) | |
12847 | { | |
12848 | record_buf_mem[index_m++] = f_ebytes; | |
12849 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12850 | thumb2_insn_r->mem_rec_count += 1; | |
12851 | } | |
12852 | address = address + (4 * f_ebytes); | |
12853 | } | |
12854 | } | |
12855 | } | |
1e1b6563 | 12856 | else |
dda83cd7 SM |
12857 | { |
12858 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
12859 | ||
12860 | if (bft_size == 0x00) | |
12861 | f_ebytes = 1; | |
12862 | else if (bft_size == 0x01) | |
12863 | f_ebytes = 2; | |
12864 | else if (bft_size == 0x02) | |
12865 | f_ebytes = 4; | |
12866 | else | |
12867 | f_ebytes = 0; | |
12868 | ||
12869 | /* Handle VST1. */ | |
12870 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
12871 | thumb2_insn_r->mem_rec_count = 1; | |
12872 | /* Handle VST2. */ | |
12873 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
12874 | thumb2_insn_r->mem_rec_count = 2; | |
12875 | /* Handle VST3. */ | |
12876 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
12877 | thumb2_insn_r->mem_rec_count = 3; | |
12878 | /* Handle VST4. */ | |
12879 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
12880 | thumb2_insn_r->mem_rec_count = 4; | |
12881 | ||
12882 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
12883 | { | |
12884 | record_buf_mem[index_m] = f_ebytes; | |
12885 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
12886 | } | |
12887 | } | |
1e1b6563 OJ |
12888 | } |
12889 | else | |
12890 | { | |
12891 | if (!a_bit) | |
dda83cd7 SM |
12892 | { |
12893 | /* Handle VLD1. */ | |
12894 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12895 | thumb2_insn_r->reg_rec_count = 1; | |
12896 | /* Handle VLD2. */ | |
12897 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12898 | thumb2_insn_r->reg_rec_count = 2; | |
12899 | /* Handle VLD3. */ | |
12900 | else if ((b_bits & 0x0e) == 0x04) | |
12901 | thumb2_insn_r->reg_rec_count = 3; | |
12902 | /* Handle VLD4. */ | |
12903 | else if (!(b_bits & 0x0e)) | |
12904 | thumb2_insn_r->reg_rec_count = 4; | |
12905 | } | |
1e1b6563 | 12906 | else |
dda83cd7 SM |
12907 | { |
12908 | /* Handle VLD1. */ | |
12909 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
12910 | thumb2_insn_r->reg_rec_count = 1; | |
12911 | /* Handle VLD2. */ | |
12912 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
12913 | thumb2_insn_r->reg_rec_count = 2; | |
12914 | /* Handle VLD3. */ | |
12915 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
12916 | thumb2_insn_r->reg_rec_count = 3; | |
12917 | /* Handle VLD4. */ | |
12918 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
12919 | thumb2_insn_r->reg_rec_count = 4; | |
12920 | ||
12921 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
12922 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
12923 | } | |
1e1b6563 OJ |
12924 | } |
12925 | ||
12926 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
12927 | { | |
12928 | record_buf[index_r] = reg_rn; | |
12929 | thumb2_insn_r->reg_rec_count += 1; | |
12930 | } | |
12931 | ||
12932 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12933 | record_buf); |
1e1b6563 | 12934 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12935 | record_buf_mem); |
1e1b6563 OJ |
12936 | return 0; |
12937 | } | |
12938 | ||
c6ec2b30 OJ |
12939 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
12940 | ||
12941 | static unsigned int | |
12942 | thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) | |
12943 | { | |
12944 | uint32_t op, op1, op2; | |
12945 | ||
12946 | op = bit (thumb2_insn_r->arm_insn, 15); | |
12947 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
12948 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12949 | ||
12950 | if (op1 == 0x01) | |
12951 | { | |
12952 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
12953 | { |
12954 | /* Load/store multiple instruction. */ | |
12955 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
12956 | } | |
b121eeb9 | 12957 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
12958 | { |
12959 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
12960 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
12961 | } | |
b121eeb9 | 12962 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
12963 | { |
12964 | /* Data-processing (shifted register). */ | |
12965 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12966 | } | |
c6ec2b30 | 12967 | else if (op2 & 0x40) |
dda83cd7 SM |
12968 | { |
12969 | /* Co-processor instructions. */ | |
12970 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
12971 | } | |
c6ec2b30 OJ |
12972 | } |
12973 | else if (op1 == 0x02) | |
12974 | { | |
12975 | if (op) | |
dda83cd7 SM |
12976 | { |
12977 | /* Branches and miscellaneous control instructions. */ | |
12978 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
12979 | } | |
c6ec2b30 | 12980 | else if (op2 & 0x20) |
dda83cd7 SM |
12981 | { |
12982 | /* Data-processing (plain binary immediate) instruction. */ | |
12983 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
12984 | } | |
c6ec2b30 | 12985 | else |
dda83cd7 SM |
12986 | { |
12987 | /* Data-processing (modified immediate). */ | |
12988 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12989 | } | |
c6ec2b30 OJ |
12990 | } |
12991 | else if (op1 == 0x03) | |
12992 | { | |
12993 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
12994 | { |
12995 | /* Store single data item. */ | |
12996 | return thumb2_record_str_single_data (thumb2_insn_r); | |
12997 | } | |
c6ec2b30 | 12998 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
12999 | { |
13000 | /* Advanced SIMD or structure load/store instructions. */ | |
13001 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
13002 | } | |
c6ec2b30 | 13003 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
13004 | { |
13005 | /* Load byte, memory hints instruction. */ | |
13006 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13007 | } | |
c6ec2b30 | 13008 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
13009 | { |
13010 | /* Load halfword, memory hints instruction. */ | |
13011 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13012 | } | |
c6ec2b30 | 13013 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
13014 | { |
13015 | /* Load word instruction. */ | |
13016 | return thumb2_record_ld_word (thumb2_insn_r); | |
13017 | } | |
c6ec2b30 | 13018 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
13019 | { |
13020 | /* Data-processing (register) instruction. */ | |
13021 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13022 | } | |
c6ec2b30 | 13023 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
13024 | { |
13025 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
13026 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13027 | } | |
c6ec2b30 | 13028 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
13029 | { |
13030 | /* Long multiply, long multiply accumulate, and divide. */ | |
13031 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
13032 | } | |
c6ec2b30 | 13033 | else if (op2 & 0x40) |
dda83cd7 SM |
13034 | { |
13035 | /* Co-processor instructions. */ | |
13036 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
13037 | } | |
c6ec2b30 OJ |
13038 | } |
13039 | ||
13040 | return -1; | |
13041 | } | |
72508ac0 | 13042 | |
ffdbe864 | 13043 | namespace { |
728a7913 YQ |
13044 | /* Abstract memory reader. */ |
13045 | ||
13046 | class abstract_memory_reader | |
13047 | { | |
13048 | public: | |
13049 | /* Read LEN bytes of target memory at address MEMADDR, placing the | |
13050 | results in GDB's memory at BUF. Return true on success. */ | |
13051 | ||
13052 | virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0; | |
13053 | }; | |
13054 | ||
13055 | /* Instruction reader from real target. */ | |
13056 | ||
13057 | class instruction_reader : public abstract_memory_reader | |
13058 | { | |
13059 | public: | |
632e107b | 13060 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
728a7913 YQ |
13061 | { |
13062 | if (target_read_memory (memaddr, buf, len)) | |
13063 | return false; | |
13064 | else | |
13065 | return true; | |
13066 | } | |
13067 | }; | |
13068 | ||
ffdbe864 YQ |
13069 | } // namespace |
13070 | ||
72508ac0 | 13071 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success |
85102364 | 13072 | and positive val on failure. */ |
72508ac0 PO |
13073 | |
13074 | static int | |
728a7913 YQ |
13075 | extract_arm_insn (abstract_memory_reader& reader, |
13076 | insn_decode_record *insn_record, uint32_t insn_size) | |
72508ac0 PO |
13077 | { |
13078 | gdb_byte buf[insn_size]; | |
13079 | ||
13080 | memset (&buf[0], 0, insn_size); | |
13081 | ||
728a7913 | 13082 | if (!reader.read (insn_record->this_addr, buf, insn_size)) |
72508ac0 PO |
13083 | return 1; |
13084 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
dda83cd7 | 13085 | insn_size, |
2959fed9 | 13086 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
13087 | return 0; |
13088 | } | |
13089 | ||
13090 | typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); | |
13091 | ||
13092 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
13093 | dispatch it. */ | |
13094 | ||
13095 | static int | |
728a7913 YQ |
13096 | decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record, |
13097 | record_type_t record_type, uint32_t insn_size) | |
72508ac0 PO |
13098 | { |
13099 | ||
01e57735 YQ |
13100 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
13101 | instruction. */ | |
0fa9c223 | 13102 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
13103 | { |
13104 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
13105 | arm_record_data_proc_imm, /* 001. */ | |
13106 | arm_record_ld_st_imm_offset, /* 010. */ | |
13107 | arm_record_ld_st_reg_offset, /* 011. */ | |
13108 | arm_record_ld_st_multiple, /* 100. */ | |
13109 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 13110 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
13111 | arm_record_coproc_data_proc /* 111. */ |
13112 | }; | |
13113 | ||
01e57735 YQ |
13114 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
13115 | instruction. */ | |
0fa9c223 | 13116 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
13117 | { \ |
13118 | thumb_record_shift_add_sub, /* 000. */ | |
13119 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
13120 | thumb_record_ld_st_reg_offset, /* 010. */ | |
13121 | thumb_record_ld_st_imm_offset, /* 011. */ | |
13122 | thumb_record_ld_st_stack, /* 100. */ | |
13123 | thumb_record_misc, /* 101. */ | |
13124 | thumb_record_ldm_stm_swi, /* 110. */ | |
13125 | thumb_record_branch /* 111. */ | |
13126 | }; | |
13127 | ||
13128 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
13129 | uint32_t insn_id = 0; | |
13130 | ||
728a7913 | 13131 | if (extract_arm_insn (reader, arm_record, insn_size)) |
72508ac0 PO |
13132 | { |
13133 | if (record_debug) | |
01e57735 YQ |
13134 | { |
13135 | printf_unfiltered (_("Process record: error reading memory at " | |
13136 | "addr %s len = %d.\n"), | |
13137 | paddress (arm_record->gdbarch, | |
13138 | arm_record->this_addr), insn_size); | |
13139 | } | |
72508ac0 PO |
13140 | return -1; |
13141 | } | |
13142 | else if (ARM_RECORD == record_type) | |
13143 | { | |
13144 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
13145 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
13146 | |
13147 | if (arm_record->cond == 0xf) | |
13148 | ret = arm_record_extension_space (arm_record); | |
13149 | else | |
01e57735 | 13150 | { |
ca92db2d YQ |
13151 | /* If this insn has fallen into extension space |
13152 | then we need not decode it anymore. */ | |
01e57735 YQ |
13153 | ret = arm_handle_insn[insn_id] (arm_record); |
13154 | } | |
ca92db2d YQ |
13155 | if (ret != ARM_RECORD_SUCCESS) |
13156 | { | |
13157 | arm_record_unsupported_insn (arm_record); | |
13158 | ret = -1; | |
13159 | } | |
72508ac0 PO |
13160 | } |
13161 | else if (THUMB_RECORD == record_type) | |
13162 | { | |
13163 | /* As thumb does not have condition codes, we set negative. */ | |
13164 | arm_record->cond = -1; | |
13165 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
13166 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
13167 | if (ret != ARM_RECORD_SUCCESS) |
13168 | { | |
13169 | arm_record_unsupported_insn (arm_record); | |
13170 | ret = -1; | |
13171 | } | |
72508ac0 PO |
13172 | } |
13173 | else if (THUMB2_RECORD == record_type) | |
13174 | { | |
c6ec2b30 OJ |
13175 | /* As thumb does not have condition codes, we set negative. */ |
13176 | arm_record->cond = -1; | |
13177 | ||
13178 | /* Swap first half of 32bit thumb instruction with second half. */ | |
13179 | arm_record->arm_insn | |
01e57735 | 13180 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 13181 | |
ca92db2d | 13182 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 13183 | |
ca92db2d | 13184 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
13185 | { |
13186 | arm_record_unsupported_insn (arm_record); | |
13187 | ret = -1; | |
13188 | } | |
72508ac0 PO |
13189 | } |
13190 | else | |
13191 | { | |
13192 | /* Throw assertion. */ | |
13193 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
13194 | } | |
13195 | ||
13196 | return ret; | |
13197 | } | |
13198 | ||
b121eeb9 YQ |
13199 | #if GDB_SELF_TEST |
13200 | namespace selftests { | |
13201 | ||
13202 | /* Provide both 16-bit and 32-bit thumb instructions. */ | |
13203 | ||
13204 | class instruction_reader_thumb : public abstract_memory_reader | |
13205 | { | |
13206 | public: | |
13207 | template<size_t SIZE> | |
13208 | instruction_reader_thumb (enum bfd_endian endian, | |
13209 | const uint16_t (&insns)[SIZE]) | |
13210 | : m_endian (endian), m_insns (insns), m_insns_size (SIZE) | |
13211 | {} | |
13212 | ||
632e107b | 13213 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
b121eeb9 YQ |
13214 | { |
13215 | SELF_CHECK (len == 4 || len == 2); | |
13216 | SELF_CHECK (memaddr % 2 == 0); | |
13217 | SELF_CHECK ((memaddr / 2) < m_insns_size); | |
13218 | ||
13219 | store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]); | |
13220 | if (len == 4) | |
13221 | { | |
13222 | store_unsigned_integer (&buf[2], 2, m_endian, | |
13223 | m_insns[memaddr / 2 + 1]); | |
13224 | } | |
13225 | return true; | |
13226 | } | |
13227 | ||
13228 | private: | |
13229 | enum bfd_endian m_endian; | |
13230 | const uint16_t *m_insns; | |
13231 | size_t m_insns_size; | |
13232 | }; | |
13233 | ||
13234 | static void | |
13235 | arm_record_test (void) | |
13236 | { | |
13237 | struct gdbarch_info info; | |
13238 | gdbarch_info_init (&info); | |
13239 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
13240 | ||
13241 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13242 | ||
13243 | SELF_CHECK (gdbarch != NULL); | |
13244 | ||
13245 | /* 16-bit Thumb instructions. */ | |
13246 | { | |
13247 | insn_decode_record arm_record; | |
13248 | ||
13249 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13250 | arm_record.gdbarch = gdbarch; | |
13251 | ||
13252 | static const uint16_t insns[] = { | |
13253 | /* db b2 uxtb r3, r3 */ | |
13254 | 0xb2db, | |
13255 | /* cd 58 ldr r5, [r1, r3] */ | |
13256 | 0x58cd, | |
13257 | }; | |
13258 | ||
13259 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13260 | instruction_reader_thumb reader (endian, insns); | |
13261 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13262 | THUMB_INSN_SIZE_BYTES); | |
13263 | ||
13264 | SELF_CHECK (ret == 0); | |
13265 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13266 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13267 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
13268 | ||
13269 | arm_record.this_addr += 2; | |
13270 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13271 | THUMB_INSN_SIZE_BYTES); | |
13272 | ||
13273 | SELF_CHECK (ret == 0); | |
13274 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13275 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13276 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
13277 | } | |
13278 | ||
13279 | /* 32-bit Thumb-2 instructions. */ | |
13280 | { | |
13281 | insn_decode_record arm_record; | |
13282 | ||
13283 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13284 | arm_record.gdbarch = gdbarch; | |
13285 | ||
13286 | static const uint16_t insns[] = { | |
13287 | /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ | |
13288 | 0xee1d, 0x7f70, | |
13289 | }; | |
13290 | ||
13291 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13292 | instruction_reader_thumb reader (endian, insns); | |
13293 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, | |
13294 | THUMB2_INSN_SIZE_BYTES); | |
13295 | ||
13296 | SELF_CHECK (ret == 0); | |
13297 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13298 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13299 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
13300 | } | |
13301 | } | |
9ecab40c SM |
13302 | |
13303 | /* Instruction reader from manually cooked instruction sequences. */ | |
13304 | ||
13305 | class test_arm_instruction_reader : public arm_instruction_reader | |
13306 | { | |
13307 | public: | |
13308 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
13309 | : m_insns (insns) | |
13310 | {} | |
13311 | ||
13312 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
13313 | { | |
13314 | SELF_CHECK (memaddr % 4 == 0); | |
13315 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
13316 | ||
13317 | return m_insns[memaddr / 4]; | |
13318 | } | |
13319 | ||
13320 | private: | |
13321 | const gdb::array_view<const uint32_t> m_insns; | |
13322 | }; | |
13323 | ||
13324 | static void | |
13325 | arm_analyze_prologue_test () | |
13326 | { | |
13327 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
13328 | { | |
13329 | struct gdbarch_info info; | |
13330 | gdbarch_info_init (&info); | |
13331 | info.byte_order = endianness; | |
13332 | info.byte_order_for_code = endianness; | |
13333 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
13334 | ||
13335 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13336 | ||
13337 | SELF_CHECK (gdbarch != NULL); | |
13338 | ||
13339 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
13340 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
13341 | UBSan. */ | |
13342 | const uint32_t insns[] = { | |
13343 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
13344 | 0xe1a05000, /* mov r5, r0 */ | |
13345 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
13346 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
13347 | }; | |
13348 | ||
13349 | test_arm_instruction_reader mem_reader (insns); | |
13350 | arm_prologue_cache cache; | |
13351 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
13352 | ||
13353 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
13354 | } | |
13355 | } | |
13356 | ||
b121eeb9 YQ |
13357 | } // namespace selftests |
13358 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
13359 | |
13360 | /* Cleans up local record registers and memory allocations. */ | |
13361 | ||
13362 | static void | |
13363 | deallocate_reg_mem (insn_decode_record *record) | |
13364 | { | |
13365 | xfree (record->arm_regs); | |
13366 | xfree (record->arm_mems); | |
13367 | } | |
13368 | ||
13369 | ||
01e57735 | 13370 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
13371 | memory that will be changed in current instruction to record_arch_list". |
13372 | Return -1 if something is wrong. */ | |
13373 | ||
13374 | int | |
01e57735 YQ |
13375 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
13376 | CORE_ADDR insn_addr) | |
72508ac0 PO |
13377 | { |
13378 | ||
72508ac0 PO |
13379 | uint32_t no_of_rec = 0; |
13380 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
13381 | ULONGEST t_bit = 0, insn_id = 0; | |
13382 | ||
13383 | ULONGEST u_regval = 0; | |
13384 | ||
13385 | insn_decode_record arm_record; | |
13386 | ||
13387 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13388 | arm_record.regcache = regcache; | |
13389 | arm_record.this_addr = insn_addr; | |
13390 | arm_record.gdbarch = gdbarch; | |
13391 | ||
13392 | ||
13393 | if (record_debug > 1) | |
13394 | { | |
13395 | fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " | |
01e57735 | 13396 | "addr = %s\n", |
72508ac0 PO |
13397 | paddress (gdbarch, arm_record.this_addr)); |
13398 | } | |
13399 | ||
728a7913 YQ |
13400 | instruction_reader reader; |
13401 | if (extract_arm_insn (reader, &arm_record, 2)) | |
72508ac0 PO |
13402 | { |
13403 | if (record_debug) | |
01e57735 YQ |
13404 | { |
13405 | printf_unfiltered (_("Process record: error reading memory at " | |
13406 | "addr %s len = %d.\n"), | |
13407 | paddress (arm_record.gdbarch, | |
13408 | arm_record.this_addr), 2); | |
13409 | } | |
72508ac0 PO |
13410 | return -1; |
13411 | } | |
13412 | ||
13413 | /* Check the insn, whether it is thumb or arm one. */ | |
13414 | ||
13415 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
13416 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
13417 | ||
13418 | ||
13419 | if (!(u_regval & t_bit)) | |
13420 | { | |
13421 | /* We are decoding arm insn. */ | |
728a7913 | 13422 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
13423 | } |
13424 | else | |
13425 | { | |
13426 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
13427 | /* is it thumb2 insn? */ | |
13428 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 13429 | { |
728a7913 | 13430 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
13431 | THUMB2_INSN_SIZE_BYTES); |
13432 | } | |
72508ac0 | 13433 | else |
01e57735 YQ |
13434 | { |
13435 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
13436 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
13437 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 13438 | } |
72508ac0 PO |
13439 | } |
13440 | ||
13441 | if (0 == ret) | |
13442 | { | |
13443 | /* Record registers. */ | |
25ea693b | 13444 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 13445 | if (arm_record.arm_regs) |
01e57735 YQ |
13446 | { |
13447 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
13448 | { | |
13449 | if (record_full_arch_list_add_reg | |
25ea693b | 13450 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
13451 | ret = -1; |
13452 | } | |
13453 | } | |
72508ac0 PO |
13454 | /* Record memories. */ |
13455 | if (arm_record.arm_mems) | |
01e57735 YQ |
13456 | { |
13457 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
13458 | { | |
13459 | if (record_full_arch_list_add_mem | |
13460 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 13461 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
13462 | ret = -1; |
13463 | } | |
13464 | } | |
72508ac0 | 13465 | |
25ea693b | 13466 | if (record_full_arch_list_add_end ()) |
01e57735 | 13467 | ret = -1; |
72508ac0 PO |
13468 | } |
13469 | ||
13470 | ||
13471 | deallocate_reg_mem (&arm_record); | |
13472 | ||
13473 | return ret; | |
13474 | } | |
d105cce5 AH |
13475 | |
13476 | /* See arm-tdep.h. */ | |
13477 | ||
13478 | const target_desc * | |
13479 | arm_read_description (arm_fp_type fp_type) | |
13480 | { | |
13481 | struct target_desc *tdesc = tdesc_arm_list[fp_type]; | |
13482 | ||
13483 | if (tdesc == nullptr) | |
13484 | { | |
13485 | tdesc = arm_create_target_description (fp_type); | |
13486 | tdesc_arm_list[fp_type] = tdesc; | |
13487 | } | |
13488 | ||
13489 | return tdesc; | |
13490 | } | |
13491 | ||
13492 | /* See arm-tdep.h. */ | |
13493 | ||
13494 | const target_desc * | |
13495 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
13496 | { | |
13497 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
13498 | ||
13499 | if (tdesc == nullptr) | |
13500 | { | |
13501 | tdesc = arm_create_mprofile_target_description (m_type); | |
13502 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
13503 | } | |
13504 | ||
13505 | return tdesc; | |
13506 | } |