Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
32d0add0 | 3 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
0963b4bd | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
45741a9c | 26 | #include "infrun.h" |
c906108c SS |
27 | #include "gdbcmd.h" |
28 | #include "gdbcore.h" | |
0963b4bd | 29 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 30 | #include "regcache.h" |
54483882 | 31 | #include "reggroups.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
25f8c692 | 43 | #include "remote.h" |
123dc839 DJ |
44 | #include "target-descriptions.h" |
45 | #include "user-regs.h" | |
0e9e9abd | 46 | #include "observer.h" |
34e8f22d RE |
47 | |
48 | #include "arm-tdep.h" | |
26216b98 | 49 | #include "gdb/sim-arm.h" |
34e8f22d | 50 | |
082fc60d RE |
51 | #include "elf-bfd.h" |
52 | #include "coff/internal.h" | |
97e03143 | 53 | #include "elf/arm.h" |
c906108c | 54 | |
60c5725c | 55 | #include "vec.h" |
26216b98 | 56 | |
72508ac0 | 57 | #include "record.h" |
d02ed0bb | 58 | #include "record-full.h" |
72508ac0 | 59 | |
9779414d | 60 | #include "features/arm-with-m.c" |
25f8c692 | 61 | #include "features/arm-with-m-fpa-layout.c" |
3184d3f9 | 62 | #include "features/arm-with-m-vfp-d16.c" |
ef7e8358 UW |
63 | #include "features/arm-with-iwmmxt.c" |
64 | #include "features/arm-with-vfpv2.c" | |
65 | #include "features/arm-with-vfpv3.c" | |
66 | #include "features/arm-with-neon.c" | |
9779414d | 67 | |
6529d2dd AC |
68 | static int arm_debug; |
69 | ||
082fc60d RE |
70 | /* Macros for setting and testing a bit in a minimal symbol that marks |
71 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 72 | is used for this purpose. |
082fc60d RE |
73 | |
74 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 75 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 76 | |
0963b4bd | 77 | #define MSYMBOL_SET_SPECIAL(msym) \ |
b887350f | 78 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
79 | |
80 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 81 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 82 | |
60c5725c DJ |
83 | /* Per-objfile data used for mapping symbols. */ |
84 | static const struct objfile_data *arm_objfile_data_key; | |
85 | ||
86 | struct arm_mapping_symbol | |
87 | { | |
88 | bfd_vma value; | |
89 | char type; | |
90 | }; | |
91 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; | |
92 | DEF_VEC_O(arm_mapping_symbol_s); | |
93 | ||
94 | struct arm_per_objfile | |
95 | { | |
96 | VEC(arm_mapping_symbol_s) **section_maps; | |
97 | }; | |
98 | ||
afd7eef0 RE |
99 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
100 | static struct cmd_list_element *setarmcmdlist = NULL; | |
101 | static struct cmd_list_element *showarmcmdlist = NULL; | |
102 | ||
fd50bc42 RE |
103 | /* The type of floating-point to use. Keep this in sync with enum |
104 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 105 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
106 | { |
107 | "auto", | |
108 | "softfpa", | |
109 | "fpa", | |
110 | "softvfp", | |
28e97307 DJ |
111 | "vfp", |
112 | NULL | |
fd50bc42 RE |
113 | }; |
114 | ||
115 | /* A variable that can be configured by the user. */ | |
116 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
117 | static const char *current_fp_model = "auto"; | |
118 | ||
28e97307 | 119 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 120 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
121 | { |
122 | "auto", | |
123 | "APCS", | |
124 | "AAPCS", | |
125 | NULL | |
126 | }; | |
127 | ||
128 | /* A variable that can be configured by the user. */ | |
129 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
130 | static const char *arm_abi_string = "auto"; | |
131 | ||
0428b8f5 | 132 | /* The execution mode to assume. */ |
40478521 | 133 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
134 | { |
135 | "auto", | |
136 | "arm", | |
68770265 MGD |
137 | "thumb", |
138 | NULL | |
0428b8f5 DJ |
139 | }; |
140 | ||
141 | static const char *arm_fallback_mode_string = "auto"; | |
142 | static const char *arm_force_mode_string = "auto"; | |
143 | ||
18819fa6 UW |
144 | /* Internal override of the execution mode. -1 means no override, |
145 | 0 means override to ARM mode, 1 means override to Thumb mode. | |
146 | The effect is the same as if arm_force_mode has been set by the | |
147 | user (except the internal override has precedence over a user's | |
148 | arm_force_mode override). */ | |
149 | static int arm_override_mode = -1; | |
150 | ||
94c30b78 | 151 | /* Number of different reg name sets (options). */ |
afd7eef0 | 152 | static int num_disassembly_options; |
bc90b915 | 153 | |
f32bf4a4 YQ |
154 | /* The standard register names, and all the valid aliases for them. Note |
155 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
156 | have been added as builtin user registers in | |
157 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
158 | static const struct |
159 | { | |
160 | const char *name; | |
161 | int regnum; | |
162 | } arm_register_aliases[] = { | |
163 | /* Basic register numbers. */ | |
164 | { "r0", 0 }, | |
165 | { "r1", 1 }, | |
166 | { "r2", 2 }, | |
167 | { "r3", 3 }, | |
168 | { "r4", 4 }, | |
169 | { "r5", 5 }, | |
170 | { "r6", 6 }, | |
171 | { "r7", 7 }, | |
172 | { "r8", 8 }, | |
173 | { "r9", 9 }, | |
174 | { "r10", 10 }, | |
175 | { "r11", 11 }, | |
176 | { "r12", 12 }, | |
177 | { "r13", 13 }, | |
178 | { "r14", 14 }, | |
179 | { "r15", 15 }, | |
180 | /* Synonyms (argument and variable registers). */ | |
181 | { "a1", 0 }, | |
182 | { "a2", 1 }, | |
183 | { "a3", 2 }, | |
184 | { "a4", 3 }, | |
185 | { "v1", 4 }, | |
186 | { "v2", 5 }, | |
187 | { "v3", 6 }, | |
188 | { "v4", 7 }, | |
189 | { "v5", 8 }, | |
190 | { "v6", 9 }, | |
191 | { "v7", 10 }, | |
192 | { "v8", 11 }, | |
193 | /* Other platform-specific names for r9. */ | |
194 | { "sb", 9 }, | |
195 | { "tr", 9 }, | |
196 | /* Special names. */ | |
197 | { "ip", 12 }, | |
123dc839 | 198 | { "lr", 14 }, |
123dc839 DJ |
199 | /* Names used by GCC (not listed in the ARM EABI). */ |
200 | { "sl", 10 }, | |
123dc839 DJ |
201 | /* A special name from the older ATPCS. */ |
202 | { "wr", 7 }, | |
203 | }; | |
bc90b915 | 204 | |
123dc839 | 205 | static const char *const arm_register_names[] = |
da59e081 JM |
206 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
207 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
208 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
209 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
210 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
211 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 212 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 213 | |
afd7eef0 RE |
214 | /* Valid register name styles. */ |
215 | static const char **valid_disassembly_styles; | |
ed9a39eb | 216 | |
afd7eef0 RE |
217 | /* Disassembly style to use. Default to "std" register names. */ |
218 | static const char *disassembly_style; | |
96baa820 | 219 | |
ed9a39eb | 220 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
221 | style. */ |
222 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 223 | struct cmd_list_element *); |
afd7eef0 | 224 | static void set_disassembly_style (void); |
ed9a39eb | 225 | |
b508a996 | 226 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 227 | void *, int); |
b508a996 | 228 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 229 | const void *, int); |
ed9a39eb | 230 | |
05d1431c PA |
231 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
232 | struct regcache *regcache, | |
233 | int regnum, gdb_byte *buf); | |
58d6951d DJ |
234 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
235 | struct regcache *regcache, | |
236 | int regnum, const gdb_byte *buf); | |
237 | ||
db24da6d YQ |
238 | static int thumb_insn_size (unsigned short inst1); |
239 | ||
9b8d791a | 240 | struct arm_prologue_cache |
c3b4394c | 241 | { |
eb5492fa DJ |
242 | /* The stack pointer at the time this frame was created; i.e. the |
243 | caller's stack pointer when this function was called. It is used | |
244 | to identify this frame. */ | |
245 | CORE_ADDR prev_sp; | |
246 | ||
4be43953 DJ |
247 | /* The frame base for this frame is just prev_sp - frame size. |
248 | FRAMESIZE is the distance from the frame pointer to the | |
249 | initial stack pointer. */ | |
eb5492fa | 250 | |
c3b4394c | 251 | int framesize; |
eb5492fa DJ |
252 | |
253 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 254 | int framereg; |
eb5492fa DJ |
255 | |
256 | /* Saved register offsets. */ | |
257 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 258 | }; |
ed9a39eb | 259 | |
0d39a070 DJ |
260 | static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, |
261 | CORE_ADDR prologue_start, | |
262 | CORE_ADDR prologue_end, | |
263 | struct arm_prologue_cache *cache); | |
264 | ||
cca44b1b JB |
265 | /* Architecture version for displaced stepping. This effects the behaviour of |
266 | certain instructions, and really should not be hard-wired. */ | |
267 | ||
268 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
269 | ||
bc90b915 FN |
270 | /* Addresses for calling Thumb functions have the bit 0 set. |
271 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
272 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
273 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
274 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
275 | ||
94c30b78 | 276 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
277 | |
278 | int arm_apcs_32 = 1; | |
279 | ||
9779414d DJ |
280 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
281 | ||
478fd957 | 282 | int |
9779414d DJ |
283 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
284 | { | |
285 | if (gdbarch_tdep (gdbarch)->is_m) | |
286 | return XPSR_T; | |
287 | else | |
288 | return CPSR_T; | |
289 | } | |
290 | ||
b39cc962 DJ |
291 | /* Determine if FRAME is executing in Thumb mode. */ |
292 | ||
25b41d01 | 293 | int |
b39cc962 DJ |
294 | arm_frame_is_thumb (struct frame_info *frame) |
295 | { | |
296 | CORE_ADDR cpsr; | |
9779414d | 297 | ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); |
b39cc962 DJ |
298 | |
299 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
300 | directly (from a signal frame or dummy frame) or by interpreting | |
301 | the saved LR (from a prologue or DWARF frame). So consult it and | |
302 | trust the unwinders. */ | |
303 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
304 | ||
9779414d | 305 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
306 | } |
307 | ||
60c5725c DJ |
308 | /* Callback for VEC_lower_bound. */ |
309 | ||
310 | static inline int | |
311 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, | |
312 | const struct arm_mapping_symbol *rhs) | |
313 | { | |
314 | return lhs->value < rhs->value; | |
315 | } | |
316 | ||
f9d67f43 DJ |
317 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
318 | return its type. Otherwise, return 0. If START is non-NULL, | |
319 | set *START to the location of the mapping symbol. */ | |
c906108c | 320 | |
f9d67f43 DJ |
321 | static char |
322 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 323 | { |
60c5725c | 324 | struct obj_section *sec; |
0428b8f5 | 325 | |
60c5725c DJ |
326 | /* If there are mapping symbols, consult them. */ |
327 | sec = find_pc_section (memaddr); | |
328 | if (sec != NULL) | |
329 | { | |
330 | struct arm_per_objfile *data; | |
331 | VEC(arm_mapping_symbol_s) *map; | |
aded6f54 PA |
332 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
333 | 0 }; | |
60c5725c DJ |
334 | unsigned int idx; |
335 | ||
336 | data = objfile_data (sec->objfile, arm_objfile_data_key); | |
337 | if (data != NULL) | |
338 | { | |
339 | map = data->section_maps[sec->the_bfd_section->index]; | |
340 | if (!VEC_empty (arm_mapping_symbol_s, map)) | |
341 | { | |
342 | struct arm_mapping_symbol *map_sym; | |
343 | ||
344 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, | |
345 | arm_compare_mapping_symbols); | |
346 | ||
347 | /* VEC_lower_bound finds the earliest ordered insertion | |
348 | point. If the following symbol starts at this exact | |
349 | address, we use that; otherwise, the preceding | |
350 | mapping symbol covers this address. */ | |
351 | if (idx < VEC_length (arm_mapping_symbol_s, map)) | |
352 | { | |
353 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); | |
354 | if (map_sym->value == map_key.value) | |
f9d67f43 DJ |
355 | { |
356 | if (start) | |
357 | *start = map_sym->value + obj_section_addr (sec); | |
358 | return map_sym->type; | |
359 | } | |
60c5725c DJ |
360 | } |
361 | ||
362 | if (idx > 0) | |
363 | { | |
364 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); | |
f9d67f43 DJ |
365 | if (start) |
366 | *start = map_sym->value + obj_section_addr (sec); | |
367 | return map_sym->type; | |
60c5725c DJ |
368 | } |
369 | } | |
370 | } | |
371 | } | |
372 | ||
f9d67f43 DJ |
373 | return 0; |
374 | } | |
375 | ||
376 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
377 | function. This function should be called for addresses unrelated to | |
378 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
379 | ||
e3039479 | 380 | int |
9779414d | 381 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 382 | { |
7cbd4a93 | 383 | struct bound_minimal_symbol sym; |
f9d67f43 | 384 | char type; |
a42244db YQ |
385 | struct displaced_step_closure* dsc |
386 | = get_displaced_step_closure_by_addr(memaddr); | |
387 | ||
388 | /* If checking the mode of displaced instruction in copy area, the mode | |
389 | should be determined by instruction on the original address. */ | |
390 | if (dsc) | |
391 | { | |
392 | if (debug_displaced) | |
393 | fprintf_unfiltered (gdb_stdlog, | |
394 | "displaced: check mode of %.8lx instead of %.8lx\n", | |
395 | (unsigned long) dsc->insn_addr, | |
396 | (unsigned long) memaddr); | |
397 | memaddr = dsc->insn_addr; | |
398 | } | |
f9d67f43 DJ |
399 | |
400 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
401 | if (IS_THUMB_ADDR (memaddr)) | |
402 | return 1; | |
403 | ||
18819fa6 UW |
404 | /* Respect internal mode override if active. */ |
405 | if (arm_override_mode != -1) | |
406 | return arm_override_mode; | |
407 | ||
f9d67f43 DJ |
408 | /* If the user wants to override the symbol table, let him. */ |
409 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
410 | return 0; | |
411 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
412 | return 1; | |
413 | ||
9779414d DJ |
414 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
415 | if (gdbarch_tdep (gdbarch)->is_m) | |
416 | return 1; | |
417 | ||
f9d67f43 DJ |
418 | /* If there are mapping symbols, consult them. */ |
419 | type = arm_find_mapping_symbol (memaddr, NULL); | |
420 | if (type) | |
421 | return type == 't'; | |
422 | ||
ed9a39eb | 423 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 424 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
425 | if (sym.minsym) |
426 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
427 | |
428 | /* If the user wants to override the fallback mode, let them. */ | |
429 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
430 | return 0; | |
431 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
432 | return 1; | |
433 | ||
434 | /* If we couldn't find any symbol, but we're talking to a running | |
435 | target, then trust the current value of $cpsr. This lets | |
436 | "display/i $pc" always show the correct mode (though if there is | |
437 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 438 | displayed in the mode it will be executed). */ |
0428b8f5 | 439 | if (target_has_registers) |
18819fa6 | 440 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
441 | |
442 | /* Otherwise we're out of luck; we assume ARM. */ | |
443 | return 0; | |
c906108c SS |
444 | } |
445 | ||
181c1381 | 446 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 447 | static CORE_ADDR |
24568a2c | 448 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 449 | { |
2ae28aa9 YQ |
450 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
451 | (the magic exception return address). */ | |
452 | if (gdbarch_tdep (gdbarch)->is_m | |
453 | && (val & 0xfffffff0) == 0xfffffff0) | |
454 | return val; | |
455 | ||
a3a2ee65 | 456 | if (arm_apcs_32) |
dd6be234 | 457 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 458 | else |
a3a2ee65 | 459 | return (val & 0x03fffffc); |
c906108c SS |
460 | } |
461 | ||
0d39a070 | 462 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
463 | can be safely ignored during prologue skipping. IS_THUMB is true |
464 | if the function is known to be a Thumb function due to the way it | |
465 | is being called. */ | |
0d39a070 | 466 | static int |
e0634ccf | 467 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 468 | { |
e0634ccf | 469 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 470 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
471 | |
472 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 473 | if (msym.minsym != NULL |
77e371c0 | 474 | && BMSYMBOL_VALUE_ADDRESS (msym) == pc |
efd66ac6 | 475 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL) |
e0634ccf | 476 | { |
efd66ac6 | 477 | const char *name = MSYMBOL_LINKAGE_NAME (msym.minsym); |
0d39a070 | 478 | |
e0634ccf UW |
479 | /* The GNU linker's Thumb call stub to foo is named |
480 | __foo_from_thumb. */ | |
481 | if (strstr (name, "_from_thumb") != NULL) | |
482 | name += 2; | |
0d39a070 | 483 | |
e0634ccf UW |
484 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
485 | arguments to their argument types in non-prototyped | |
486 | functions. */ | |
61012eef | 487 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 488 | return 1; |
61012eef | 489 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 490 | return 1; |
0d39a070 | 491 | |
e0634ccf | 492 | /* Internal functions related to thread-local storage. */ |
61012eef | 493 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 494 | return 1; |
61012eef | 495 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
496 | return 1; |
497 | } | |
498 | else | |
499 | { | |
500 | /* If we run against a stripped glibc, we may be unable to identify | |
501 | special functions by name. Check for one important case, | |
502 | __aeabi_read_tp, by comparing the *code* against the default | |
503 | implementation (this is hand-written ARM assembler in glibc). */ | |
504 | ||
505 | if (!is_thumb | |
506 | && read_memory_unsigned_integer (pc, 4, byte_order_for_code) | |
507 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ | |
508 | && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code) | |
509 | == 0xe240f01f) /* sub pc, r0, #31 */ | |
510 | return 1; | |
511 | } | |
ec3d575a | 512 | |
0d39a070 DJ |
513 | return 0; |
514 | } | |
515 | ||
516 | /* Support routines for instruction parsing. */ | |
517 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
518 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
519 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
520 | #define sbits(obj,st,fn) \ | |
521 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
522 | #define BranchDest(addr,instr) \ | |
9991b207 | 523 | ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
0d39a070 | 524 | |
621c6d5b YQ |
525 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
526 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
527 | instruction. */ | |
528 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
529 | ((bits ((insn1), 0, 3) << 12) \ | |
530 | | (bits ((insn1), 10, 10) << 11) \ | |
531 | | (bits ((insn2), 12, 14) << 8) \ | |
532 | | bits ((insn2), 0, 7)) | |
533 | ||
534 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
535 | the 32-bit instruction. */ | |
536 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
537 | ((bits ((insn), 16, 19) << 12) \ | |
538 | | bits ((insn), 0, 11)) | |
539 | ||
ec3d575a UW |
540 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
541 | ||
542 | static unsigned int | |
543 | thumb_expand_immediate (unsigned int imm) | |
544 | { | |
545 | unsigned int count = imm >> 7; | |
546 | ||
547 | if (count < 8) | |
548 | switch (count / 2) | |
549 | { | |
550 | case 0: | |
551 | return imm & 0xff; | |
552 | case 1: | |
553 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
554 | case 2: | |
555 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
556 | case 3: | |
557 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
558 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
559 | } | |
560 | ||
561 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
562 | } | |
563 | ||
564 | /* Return 1 if the 16-bit Thumb instruction INST might change | |
565 | control flow, 0 otherwise. */ | |
566 | ||
567 | static int | |
568 | thumb_instruction_changes_pc (unsigned short inst) | |
569 | { | |
570 | if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
571 | return 1; | |
572 | ||
573 | if ((inst & 0xf000) == 0xd000) /* conditional branch */ | |
574 | return 1; | |
575 | ||
576 | if ((inst & 0xf800) == 0xe000) /* unconditional branch */ | |
577 | return 1; | |
578 | ||
579 | if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */ | |
580 | return 1; | |
581 | ||
ad8b5167 UW |
582 | if ((inst & 0xff87) == 0x4687) /* mov pc, REG */ |
583 | return 1; | |
584 | ||
ec3d575a UW |
585 | if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */ |
586 | return 1; | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2 | |
592 | might change control flow, 0 otherwise. */ | |
593 | ||
594 | static int | |
595 | thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2) | |
596 | { | |
597 | if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) | |
598 | { | |
599 | /* Branches and miscellaneous control instructions. */ | |
600 | ||
601 | if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) | |
602 | { | |
603 | /* B, BL, BLX. */ | |
604 | return 1; | |
605 | } | |
606 | else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) | |
607 | { | |
608 | /* SUBS PC, LR, #imm8. */ | |
609 | return 1; | |
610 | } | |
611 | else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) | |
612 | { | |
613 | /* Conditional branch. */ | |
614 | return 1; | |
615 | } | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | if ((inst1 & 0xfe50) == 0xe810) | |
621 | { | |
622 | /* Load multiple or RFE. */ | |
623 | ||
624 | if (bit (inst1, 7) && !bit (inst1, 8)) | |
625 | { | |
626 | /* LDMIA or POP */ | |
627 | if (bit (inst2, 15)) | |
628 | return 1; | |
629 | } | |
630 | else if (!bit (inst1, 7) && bit (inst1, 8)) | |
631 | { | |
632 | /* LDMDB */ | |
633 | if (bit (inst2, 15)) | |
634 | return 1; | |
635 | } | |
636 | else if (bit (inst1, 7) && bit (inst1, 8)) | |
637 | { | |
638 | /* RFEIA */ | |
639 | return 1; | |
640 | } | |
641 | else if (!bit (inst1, 7) && !bit (inst1, 8)) | |
642 | { | |
643 | /* RFEDB */ | |
644 | return 1; | |
645 | } | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) | |
651 | { | |
652 | /* MOV PC or MOVS PC. */ | |
653 | return 1; | |
654 | } | |
655 | ||
656 | if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) | |
657 | { | |
658 | /* LDR PC. */ | |
659 | if (bits (inst1, 0, 3) == 15) | |
660 | return 1; | |
661 | if (bit (inst1, 7)) | |
662 | return 1; | |
663 | if (bit (inst2, 11)) | |
664 | return 1; | |
665 | if ((inst2 & 0x0fc0) == 0x0000) | |
666 | return 1; | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) | |
672 | { | |
673 | /* TBB. */ | |
674 | return 1; | |
675 | } | |
676 | ||
677 | if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) | |
678 | { | |
679 | /* TBH. */ | |
680 | return 1; | |
681 | } | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
540314bd YQ |
686 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
687 | epilogue, 0 otherwise. */ | |
688 | ||
689 | static int | |
690 | thumb_instruction_restores_sp (unsigned short insn) | |
691 | { | |
692 | return (insn == 0x46bd /* mov sp, r7 */ | |
693 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
694 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
695 | } | |
696 | ||
29d73ae4 DJ |
697 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
698 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
699 | clobber the stack frame unexpectedly, or an unknown instruction. |
700 | Return the last address which is definitely safe to skip for an | |
701 | initial breakpoint. */ | |
c906108c SS |
702 | |
703 | static CORE_ADDR | |
29d73ae4 DJ |
704 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
705 | CORE_ADDR start, CORE_ADDR limit, | |
706 | struct arm_prologue_cache *cache) | |
c906108c | 707 | { |
0d39a070 | 708 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 709 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
710 | int i; |
711 | pv_t regs[16]; | |
712 | struct pv_area *stack; | |
713 | struct cleanup *back_to; | |
714 | CORE_ADDR offset; | |
ec3d575a | 715 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 716 | |
29d73ae4 DJ |
717 | for (i = 0; i < 16; i++) |
718 | regs[i] = pv_register (i, 0); | |
55f960e1 | 719 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 DJ |
720 | back_to = make_cleanup_free_pv_area (stack); |
721 | ||
29d73ae4 | 722 | while (start < limit) |
c906108c | 723 | { |
29d73ae4 DJ |
724 | unsigned short insn; |
725 | ||
e17a4113 | 726 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 727 | |
94c30b78 | 728 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 729 | { |
29d73ae4 DJ |
730 | int regno; |
731 | int mask; | |
4be43953 DJ |
732 | |
733 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
734 | break; | |
29d73ae4 DJ |
735 | |
736 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
737 | whether to save LR (R14). */ | |
738 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
739 | ||
740 | /* Calculate offsets of saved R0-R7 and LR. */ | |
741 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
742 | if (mask & (1 << regno)) | |
743 | { | |
29d73ae4 DJ |
744 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
745 | -4); | |
746 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
747 | } | |
da59e081 | 748 | } |
1db01f22 | 749 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 750 | { |
29d73ae4 | 751 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
752 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
753 | -offset); | |
da59e081 | 754 | } |
808f7ab1 YQ |
755 | else if (thumb_instruction_restores_sp (insn)) |
756 | { | |
757 | /* Don't scan past the epilogue. */ | |
758 | break; | |
759 | } | |
0d39a070 DJ |
760 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
761 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
762 | (insn & 0xff) << 2); | |
763 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
764 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
765 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
766 | bits (insn, 6, 8)); | |
767 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
768 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
769 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
770 | bits (insn, 0, 7)); | |
771 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
772 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
773 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
774 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
775 | regs[bits (insn, 6, 8)]); | |
776 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
777 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
778 | { | |
779 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
780 | int rm = bits (insn, 3, 6); | |
781 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
782 | } | |
29d73ae4 | 783 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 784 | { |
29d73ae4 DJ |
785 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
786 | int src_reg = (insn & 0x78) >> 3; | |
787 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 788 | } |
29d73ae4 | 789 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 790 | { |
29d73ae4 DJ |
791 | /* Handle stores to the stack. Normally pushes are used, |
792 | but with GCC -mtpcs-frame, there may be other stores | |
793 | in the prologue to create the frame. */ | |
794 | int regno = (insn >> 8) & 0x7; | |
795 | pv_t addr; | |
796 | ||
797 | offset = (insn & 0xff) << 2; | |
798 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
799 | ||
800 | if (pv_area_store_would_trash (stack, addr)) | |
801 | break; | |
802 | ||
803 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 804 | } |
0d39a070 DJ |
805 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
806 | { | |
807 | int rd = bits (insn, 0, 2); | |
808 | int rn = bits (insn, 3, 5); | |
809 | pv_t addr; | |
810 | ||
811 | offset = bits (insn, 6, 10) << 2; | |
812 | addr = pv_add_constant (regs[rn], offset); | |
813 | ||
814 | if (pv_area_store_would_trash (stack, addr)) | |
815 | break; | |
816 | ||
817 | pv_area_store (stack, addr, 4, regs[rd]); | |
818 | } | |
819 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
820 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
821 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
822 | /* Ignore stores of argument registers to the stack. */ | |
823 | ; | |
824 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
825 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
826 | /* Ignore block loads from the stack, potentially copying | |
827 | parameters from memory. */ | |
828 | ; | |
829 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
830 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
831 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
832 | /* Similarly ignore single loads from the stack. */ | |
833 | ; | |
834 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
835 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
836 | /* Skip register copies, i.e. saves to another register | |
837 | instead of the stack. */ | |
838 | ; | |
839 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
840 | /* Recognize constant loads; even with small stacks these are necessary | |
841 | on Thumb. */ | |
842 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
843 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
844 | { | |
845 | /* Constant pool loads, for the same reason. */ | |
846 | unsigned int constant; | |
847 | CORE_ADDR loc; | |
848 | ||
849 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
850 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
851 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
852 | } | |
db24da6d | 853 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 854 | { |
0d39a070 DJ |
855 | unsigned short inst2; |
856 | ||
857 | inst2 = read_memory_unsigned_integer (start + 2, 2, | |
858 | byte_order_for_code); | |
859 | ||
860 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
861 | { | |
862 | /* BL, BLX. Allow some special function calls when | |
863 | skipping the prologue; GCC generates these before | |
864 | storing arguments to the stack. */ | |
865 | CORE_ADDR nextpc; | |
866 | int j1, j2, imm1, imm2; | |
867 | ||
868 | imm1 = sbits (insn, 0, 10); | |
869 | imm2 = bits (inst2, 0, 10); | |
870 | j1 = bit (inst2, 13); | |
871 | j2 = bit (inst2, 11); | |
872 | ||
873 | offset = ((imm1 << 12) + (imm2 << 1)); | |
874 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
875 | ||
876 | nextpc = start + 4 + offset; | |
877 | /* For BLX make sure to clear the low bits. */ | |
878 | if (bit (inst2, 12) == 0) | |
879 | nextpc = nextpc & 0xfffffffc; | |
880 | ||
e0634ccf UW |
881 | if (!skip_prologue_function (gdbarch, nextpc, |
882 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
883 | break; |
884 | } | |
ec3d575a | 885 | |
0963b4bd MS |
886 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
887 | { registers } */ | |
ec3d575a UW |
888 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
889 | { | |
890 | pv_t addr = regs[bits (insn, 0, 3)]; | |
891 | int regno; | |
892 | ||
893 | if (pv_area_store_would_trash (stack, addr)) | |
894 | break; | |
895 | ||
896 | /* Calculate offsets of saved registers. */ | |
897 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
898 | if (inst2 & (1 << regno)) | |
899 | { | |
900 | addr = pv_add_constant (addr, -4); | |
901 | pv_area_store (stack, addr, 4, regs[regno]); | |
902 | } | |
903 | ||
904 | if (insn & 0x0020) | |
905 | regs[bits (insn, 0, 3)] = addr; | |
906 | } | |
907 | ||
0963b4bd MS |
908 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
909 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
910 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
911 | { | |
912 | int regno1 = bits (inst2, 12, 15); | |
913 | int regno2 = bits (inst2, 8, 11); | |
914 | pv_t addr = regs[bits (insn, 0, 3)]; | |
915 | ||
916 | offset = inst2 & 0xff; | |
917 | if (insn & 0x0080) | |
918 | addr = pv_add_constant (addr, offset); | |
919 | else | |
920 | addr = pv_add_constant (addr, -offset); | |
921 | ||
922 | if (pv_area_store_would_trash (stack, addr)) | |
923 | break; | |
924 | ||
925 | pv_area_store (stack, addr, 4, regs[regno1]); | |
926 | pv_area_store (stack, pv_add_constant (addr, 4), | |
927 | 4, regs[regno2]); | |
928 | ||
929 | if (insn & 0x0020) | |
930 | regs[bits (insn, 0, 3)] = addr; | |
931 | } | |
932 | ||
933 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
934 | && (inst2 & 0x0c00) == 0x0c00 | |
935 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
936 | { | |
937 | int regno = bits (inst2, 12, 15); | |
938 | pv_t addr = regs[bits (insn, 0, 3)]; | |
939 | ||
940 | offset = inst2 & 0xff; | |
941 | if (inst2 & 0x0200) | |
942 | addr = pv_add_constant (addr, offset); | |
943 | else | |
944 | addr = pv_add_constant (addr, -offset); | |
945 | ||
946 | if (pv_area_store_would_trash (stack, addr)) | |
947 | break; | |
948 | ||
949 | pv_area_store (stack, addr, 4, regs[regno]); | |
950 | ||
951 | if (inst2 & 0x0100) | |
952 | regs[bits (insn, 0, 3)] = addr; | |
953 | } | |
954 | ||
955 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
956 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
957 | { | |
958 | int regno = bits (inst2, 12, 15); | |
959 | pv_t addr; | |
960 | ||
961 | offset = inst2 & 0xfff; | |
962 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
963 | ||
964 | if (pv_area_store_would_trash (stack, addr)) | |
965 | break; | |
966 | ||
967 | pv_area_store (stack, addr, 4, regs[regno]); | |
968 | } | |
969 | ||
970 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 971 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 972 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 973 | ; |
ec3d575a UW |
974 | |
975 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
976 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 977 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 978 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 979 | ; |
ec3d575a | 980 | |
0963b4bd MS |
981 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
982 | { registers } */ | |
ec3d575a UW |
983 | && (inst2 & 0x8000) == 0x0000 |
984 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
985 | /* Ignore block loads from the stack, potentially copying | |
986 | parameters from memory. */ | |
0d39a070 | 987 | ; |
ec3d575a | 988 | |
0963b4bd MS |
989 | else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, |
990 | [Rn, #+/-imm] */ | |
0d39a070 | 991 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 992 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 993 | ; |
ec3d575a UW |
994 | |
995 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
996 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 997 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 998 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 999 | ; |
ec3d575a UW |
1000 | |
1001 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 1002 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1003 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1004 | ; |
ec3d575a UW |
1005 | |
1006 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
1007 | && (inst2 & 0x8000) == 0x0000) | |
1008 | { | |
1009 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1010 | | (bits (inst2, 12, 14) << 8) | |
1011 | | bits (inst2, 0, 7)); | |
1012 | ||
1013 | regs[bits (inst2, 8, 11)] | |
1014 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1015 | thumb_expand_immediate (imm)); | |
1016 | } | |
1017 | ||
1018 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1019 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1020 | { |
ec3d575a UW |
1021 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1022 | | (bits (inst2, 12, 14) << 8) | |
1023 | | bits (inst2, 0, 7)); | |
1024 | ||
1025 | regs[bits (inst2, 8, 11)] | |
1026 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1027 | } | |
1028 | ||
1029 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1030 | && (inst2 & 0x8000) == 0x0000) | |
1031 | { | |
1032 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1033 | | (bits (inst2, 12, 14) << 8) | |
1034 | | bits (inst2, 0, 7)); | |
1035 | ||
1036 | regs[bits (inst2, 8, 11)] | |
1037 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1038 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1039 | } | |
1040 | ||
1041 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1042 | && (inst2 & 0x8000) == 0x0000) | |
1043 | { | |
1044 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1045 | | (bits (inst2, 12, 14) << 8) | |
1046 | | bits (inst2, 0, 7)); | |
1047 | ||
1048 | regs[bits (inst2, 8, 11)] | |
1049 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1050 | } | |
1051 | ||
1052 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1053 | { | |
1054 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1055 | | (bits (inst2, 12, 14) << 8) | |
1056 | | bits (inst2, 0, 7)); | |
1057 | ||
1058 | regs[bits (inst2, 8, 11)] | |
1059 | = pv_constant (thumb_expand_immediate (imm)); | |
1060 | } | |
1061 | ||
1062 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1063 | { | |
621c6d5b YQ |
1064 | unsigned int imm |
1065 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1066 | |
1067 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1068 | } | |
1069 | ||
1070 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1071 | && (inst2 & 0xf0f0) == 0) | |
1072 | { | |
1073 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1074 | int src_reg = inst2 & 0xf; | |
1075 | regs[dst_reg] = regs[src_reg]; | |
1076 | } | |
1077 | ||
1078 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1079 | { | |
1080 | /* Constant pool loads. */ | |
1081 | unsigned int constant; | |
1082 | CORE_ADDR loc; | |
1083 | ||
cac395ea | 1084 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1085 | if (insn & 0x0080) |
1086 | loc = start + 4 + offset; | |
1087 | else | |
1088 | loc = start + 4 - offset; | |
1089 | ||
1090 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1091 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1092 | } | |
1093 | ||
1094 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1095 | { | |
1096 | /* Constant pool loads. */ | |
1097 | unsigned int constant; | |
1098 | CORE_ADDR loc; | |
1099 | ||
cac395ea | 1100 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1101 | if (insn & 0x0080) |
1102 | loc = start + 4 + offset; | |
1103 | else | |
1104 | loc = start + 4 - offset; | |
1105 | ||
1106 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1107 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1108 | ||
1109 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1110 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1111 | } | |
1112 | ||
1113 | else if (thumb2_instruction_changes_pc (insn, inst2)) | |
1114 | { | |
1115 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1116 | break; |
1117 | } | |
ec3d575a UW |
1118 | else |
1119 | { | |
1120 | /* The optimizer might shove anything into the prologue, | |
1121 | so we just skip what we don't recognize. */ | |
1122 | unrecognized_pc = start; | |
1123 | } | |
0d39a070 DJ |
1124 | |
1125 | start += 2; | |
1126 | } | |
ec3d575a | 1127 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1128 | { |
ec3d575a | 1129 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1130 | break; |
3d74b771 | 1131 | } |
ec3d575a UW |
1132 | else |
1133 | { | |
1134 | /* The optimizer might shove anything into the prologue, | |
1135 | so we just skip what we don't recognize. */ | |
1136 | unrecognized_pc = start; | |
1137 | } | |
29d73ae4 DJ |
1138 | |
1139 | start += 2; | |
c906108c SS |
1140 | } |
1141 | ||
0d39a070 DJ |
1142 | if (arm_debug) |
1143 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1144 | paddress (gdbarch, start)); | |
1145 | ||
ec3d575a UW |
1146 | if (unrecognized_pc == 0) |
1147 | unrecognized_pc = start; | |
1148 | ||
29d73ae4 DJ |
1149 | if (cache == NULL) |
1150 | { | |
1151 | do_cleanups (back_to); | |
ec3d575a | 1152 | return unrecognized_pc; |
29d73ae4 DJ |
1153 | } |
1154 | ||
29d73ae4 DJ |
1155 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1156 | { | |
1157 | /* Frame pointer is fp. Frame size is constant. */ | |
1158 | cache->framereg = ARM_FP_REGNUM; | |
1159 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1160 | } | |
1161 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1162 | { | |
1163 | /* Frame pointer is r7. Frame size is constant. */ | |
1164 | cache->framereg = THUMB_FP_REGNUM; | |
1165 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1166 | } | |
72a2e3dc | 1167 | else |
29d73ae4 DJ |
1168 | { |
1169 | /* Try the stack pointer... this is a bit desperate. */ | |
1170 | cache->framereg = ARM_SP_REGNUM; | |
1171 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1172 | } | |
29d73ae4 DJ |
1173 | |
1174 | for (i = 0; i < 16; i++) | |
1175 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
1176 | cache->saved_regs[i].addr = offset; | |
1177 | ||
1178 | do_cleanups (back_to); | |
ec3d575a | 1179 | return unrecognized_pc; |
c906108c SS |
1180 | } |
1181 | ||
621c6d5b YQ |
1182 | |
1183 | /* Try to analyze the instructions starting from PC, which load symbol | |
1184 | __stack_chk_guard. Return the address of instruction after loading this | |
1185 | symbol, set the dest register number to *BASEREG, and set the size of | |
1186 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1187 | not recognized. */ | |
1188 | ||
1189 | static CORE_ADDR | |
1190 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1191 | unsigned int *destreg, int *offset) | |
1192 | { | |
1193 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1194 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1195 | unsigned int low, high, address; | |
1196 | ||
1197 | address = 0; | |
1198 | if (is_thumb) | |
1199 | { | |
1200 | unsigned short insn1 | |
1201 | = read_memory_unsigned_integer (pc, 2, byte_order_for_code); | |
1202 | ||
1203 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1204 | { | |
1205 | *destreg = bits (insn1, 8, 10); | |
1206 | *offset = 2; | |
6ae274b7 YQ |
1207 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1208 | address = read_memory_unsigned_integer (address, 4, | |
1209 | byte_order_for_code); | |
621c6d5b YQ |
1210 | } |
1211 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1212 | { | |
1213 | unsigned short insn2 | |
1214 | = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
1215 | ||
1216 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1217 | ||
1218 | insn1 | |
1219 | = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code); | |
1220 | insn2 | |
1221 | = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code); | |
1222 | ||
1223 | /* movt Rd, #const */ | |
1224 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1225 | { | |
1226 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1227 | *destreg = bits (insn2, 8, 11); | |
1228 | *offset = 8; | |
1229 | address = (high << 16 | low); | |
1230 | } | |
1231 | } | |
1232 | } | |
1233 | else | |
1234 | { | |
2e9e421f UW |
1235 | unsigned int insn |
1236 | = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
1237 | ||
6ae274b7 | 1238 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1239 | { |
6ae274b7 YQ |
1240 | address = bits (insn, 0, 11) + pc + 8; |
1241 | address = read_memory_unsigned_integer (address, 4, | |
1242 | byte_order_for_code); | |
1243 | ||
2e9e421f UW |
1244 | *destreg = bits (insn, 12, 15); |
1245 | *offset = 4; | |
1246 | } | |
1247 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1248 | { | |
1249 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1250 | ||
1251 | insn | |
1252 | = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code); | |
1253 | ||
1254 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1255 | { | |
1256 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1257 | *destreg = bits (insn, 12, 15); | |
1258 | *offset = 8; | |
1259 | address = (high << 16 | low); | |
1260 | } | |
1261 | } | |
621c6d5b YQ |
1262 | } |
1263 | ||
1264 | return address; | |
1265 | } | |
1266 | ||
1267 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1268 | points to the first instruction of this sequence, return the address of |
1269 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1270 | |
1271 | On arm, this sequence of instructions is composed of mainly three steps, | |
1272 | Step 1: load symbol __stack_chk_guard, | |
1273 | Step 2: load from address of __stack_chk_guard, | |
1274 | Step 3: store it to somewhere else. | |
1275 | ||
1276 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1277 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1278 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1279 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1280 | they are, | |
1281 | ||
1282 | movw Rn, #:lower16:__stack_chk_guard | |
1283 | movt Rn, #:upper16:__stack_chk_guard | |
1284 | ||
1285 | On ARMv5t, it is, | |
1286 | ||
1287 | ldr Rn, .Label | |
1288 | .... | |
1289 | .Lable: | |
1290 | .word __stack_chk_guard | |
1291 | ||
1292 | Since ldr/str is a very popular instruction, we can't use them as | |
1293 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1294 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1295 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1296 | ||
1297 | static CORE_ADDR | |
1298 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1299 | { | |
1300 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1301 | unsigned int basereg; |
7cbd4a93 | 1302 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1303 | int offset; |
1304 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1305 | CORE_ADDR addr; | |
1306 | ||
1307 | /* Try to parse the instructions in Step 1. */ | |
1308 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1309 | &basereg, &offset); | |
1310 | if (!addr) | |
1311 | return pc; | |
1312 | ||
1313 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1314 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1315 | Otherwise, this sequence cannot be for stack protector. */ | |
1316 | if (stack_chk_guard.minsym == NULL | |
61012eef | 1317 | || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard")) |
621c6d5b YQ |
1318 | return pc; |
1319 | ||
1320 | if (is_thumb) | |
1321 | { | |
1322 | unsigned int destreg; | |
1323 | unsigned short insn | |
1324 | = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code); | |
1325 | ||
1326 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1327 | if ((insn & 0xf800) != 0x6800) | |
1328 | return pc; | |
1329 | if (bits (insn, 3, 5) != basereg) | |
1330 | return pc; | |
1331 | destreg = bits (insn, 0, 2); | |
1332 | ||
1333 | insn = read_memory_unsigned_integer (pc + offset + 2, 2, | |
1334 | byte_order_for_code); | |
1335 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ | |
1336 | if ((insn & 0xf800) != 0x6000) | |
1337 | return pc; | |
1338 | if (destreg != bits (insn, 0, 2)) | |
1339 | return pc; | |
1340 | } | |
1341 | else | |
1342 | { | |
1343 | unsigned int destreg; | |
1344 | unsigned int insn | |
1345 | = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code); | |
1346 | ||
1347 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1348 | if ((insn & 0x0e500000) != 0x04100000) | |
1349 | return pc; | |
1350 | if (bits (insn, 16, 19) != basereg) | |
1351 | return pc; | |
1352 | destreg = bits (insn, 12, 15); | |
1353 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
1354 | insn = read_memory_unsigned_integer (pc + offset + 4, | |
1355 | 4, byte_order_for_code); | |
1356 | if ((insn & 0x0e500000) != 0x04000000) | |
1357 | return pc; | |
1358 | if (bits (insn, 12, 15) != destreg) | |
1359 | return pc; | |
1360 | } | |
1361 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1362 | on arm. */ | |
1363 | if (is_thumb) | |
1364 | return pc + offset + 4; | |
1365 | else | |
1366 | return pc + offset + 8; | |
1367 | } | |
1368 | ||
da3c6d4a MS |
1369 | /* Advance the PC across any function entry prologue instructions to |
1370 | reach some "real" code. | |
34e8f22d RE |
1371 | |
1372 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1373 | prologue: |
c906108c | 1374 | |
c5aa993b JM |
1375 | mov ip, sp |
1376 | [stmfd sp!, {a1,a2,a3,a4}] | |
1377 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1378 | [stfe f7, [sp, #-12]!] |
1379 | [stfe f6, [sp, #-12]!] | |
1380 | [stfe f5, [sp, #-12]!] | |
1381 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1382 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1383 | |
34e8f22d | 1384 | static CORE_ADDR |
6093d2eb | 1385 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1386 | { |
e17a4113 | 1387 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
c906108c | 1388 | unsigned long inst; |
a89fea3c | 1389 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1390 | |
a89fea3c JL |
1391 | /* See if we can determine the end of the prologue via the symbol table. |
1392 | If so, then return either PC, or the PC after the prologue, whichever | |
1393 | is greater. */ | |
1394 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1395 | { |
d80b854b UW |
1396 | CORE_ADDR post_prologue_pc |
1397 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1398 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1399 | |
621c6d5b YQ |
1400 | if (post_prologue_pc) |
1401 | post_prologue_pc | |
1402 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1403 | ||
1404 | ||
0d39a070 DJ |
1405 | /* GCC always emits a line note before the prologue and another |
1406 | one after, even if the two are at the same address or on the | |
1407 | same line. Take advantage of this so that we do not need to | |
1408 | know every instruction that might appear in the prologue. We | |
1409 | will have producer information for most binaries; if it is | |
1410 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1411 | if (post_prologue_pc | |
43f3e411 DE |
1412 | && (cust == NULL |
1413 | || COMPUNIT_PRODUCER (cust) == NULL | |
61012eef GB |
1414 | || startswith (COMPUNIT_PRODUCER (cust), "GNU ") |
1415 | || startswith (COMPUNIT_PRODUCER (cust), "clang "))) | |
0d39a070 DJ |
1416 | return post_prologue_pc; |
1417 | ||
a89fea3c | 1418 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1419 | { |
1420 | CORE_ADDR analyzed_limit; | |
1421 | ||
1422 | /* For non-GCC compilers, make sure the entire line is an | |
1423 | acceptable prologue; GDB will round this function's | |
1424 | return value up to the end of the following line so we | |
1425 | can not skip just part of a line (and we do not want to). | |
1426 | ||
1427 | RealView does not treat the prologue specially, but does | |
1428 | associate prologue code with the opening brace; so this | |
1429 | lets us skip the first line if we think it is the opening | |
1430 | brace. */ | |
9779414d | 1431 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1432 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1433 | post_prologue_pc, NULL); | |
1434 | else | |
1435 | analyzed_limit = arm_analyze_prologue (gdbarch, func_addr, | |
1436 | post_prologue_pc, NULL); | |
1437 | ||
1438 | if (analyzed_limit != post_prologue_pc) | |
1439 | return func_addr; | |
1440 | ||
1441 | return post_prologue_pc; | |
1442 | } | |
c906108c SS |
1443 | } |
1444 | ||
a89fea3c JL |
1445 | /* Can't determine prologue from the symbol table, need to examine |
1446 | instructions. */ | |
c906108c | 1447 | |
a89fea3c JL |
1448 | /* Find an upper limit on the function prologue using the debug |
1449 | information. If the debug information could not be used to provide | |
1450 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1451 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1452 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1453 | if (limit_pc == 0) |
1454 | limit_pc = pc + 64; /* Magic. */ | |
1455 | ||
c906108c | 1456 | |
29d73ae4 | 1457 | /* Check if this is Thumb code. */ |
9779414d | 1458 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1459 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf YQ |
1460 | else |
1461 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
c906108c | 1462 | } |
94c30b78 | 1463 | |
c5aa993b | 1464 | /* *INDENT-OFF* */ |
c906108c SS |
1465 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1466 | This function decodes a Thumb function prologue to determine: | |
1467 | 1) the size of the stack frame | |
1468 | 2) which registers are saved on it | |
1469 | 3) the offsets of saved regs | |
1470 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1471 | |
da59e081 JM |
1472 | A typical Thumb function prologue would create this stack frame |
1473 | (offsets relative to FP) | |
c906108c SS |
1474 | old SP -> 24 stack parameters |
1475 | 20 LR | |
1476 | 16 R7 | |
1477 | R7 -> 0 local variables (16 bytes) | |
1478 | SP -> -12 additional stack space (12 bytes) | |
1479 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1480 | 12 bytes. The frame register is R7. |
da59e081 | 1481 | |
da3c6d4a MS |
1482 | The comments for thumb_skip_prolog() describe the algorithm we use |
1483 | to detect the end of the prolog. */ | |
c5aa993b JM |
1484 | /* *INDENT-ON* */ |
1485 | ||
c906108c | 1486 | static void |
be8626e0 | 1487 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1488 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1489 | { |
1490 | CORE_ADDR prologue_start; | |
1491 | CORE_ADDR prologue_end; | |
c906108c | 1492 | |
b39cc962 DJ |
1493 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1494 | &prologue_end)) | |
c906108c | 1495 | { |
ec3d575a UW |
1496 | /* See comment in arm_scan_prologue for an explanation of |
1497 | this heuristics. */ | |
1498 | if (prologue_end > prologue_start + 64) | |
1499 | { | |
1500 | prologue_end = prologue_start + 64; | |
1501 | } | |
c906108c SS |
1502 | } |
1503 | else | |
f7060f85 DJ |
1504 | /* We're in the boondocks: we have no idea where the start of the |
1505 | function is. */ | |
1506 | return; | |
c906108c | 1507 | |
eb5492fa | 1508 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 1509 | |
be8626e0 | 1510 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1511 | } |
1512 | ||
0d39a070 | 1513 | /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */ |
c906108c | 1514 | |
0d39a070 DJ |
1515 | static int |
1516 | arm_instruction_changes_pc (uint32_t this_instr) | |
c906108c | 1517 | { |
0d39a070 DJ |
1518 | if (bits (this_instr, 28, 31) == INST_NV) |
1519 | /* Unconditional instructions. */ | |
1520 | switch (bits (this_instr, 24, 27)) | |
1521 | { | |
1522 | case 0xa: | |
1523 | case 0xb: | |
1524 | /* Branch with Link and change to Thumb. */ | |
1525 | return 1; | |
1526 | case 0xc: | |
1527 | case 0xd: | |
1528 | case 0xe: | |
1529 | /* Coprocessor register transfer. */ | |
1530 | if (bits (this_instr, 12, 15) == 15) | |
1531 | error (_("Invalid update to pc in instruction")); | |
1532 | return 0; | |
1533 | default: | |
1534 | return 0; | |
1535 | } | |
1536 | else | |
1537 | switch (bits (this_instr, 25, 27)) | |
1538 | { | |
1539 | case 0x0: | |
1540 | if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0) | |
1541 | { | |
1542 | /* Multiplies and extra load/stores. */ | |
1543 | if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1) | |
1544 | /* Neither multiplies nor extension load/stores are allowed | |
1545 | to modify PC. */ | |
1546 | return 0; | |
1547 | ||
1548 | /* Otherwise, miscellaneous instructions. */ | |
1549 | ||
1550 | /* BX <reg>, BXJ <reg>, BLX <reg> */ | |
1551 | if (bits (this_instr, 4, 27) == 0x12fff1 | |
1552 | || bits (this_instr, 4, 27) == 0x12fff2 | |
1553 | || bits (this_instr, 4, 27) == 0x12fff3) | |
1554 | return 1; | |
1555 | ||
1556 | /* Other miscellaneous instructions are unpredictable if they | |
1557 | modify PC. */ | |
1558 | return 0; | |
1559 | } | |
1560 | /* Data processing instruction. Fall through. */ | |
c906108c | 1561 | |
0d39a070 DJ |
1562 | case 0x1: |
1563 | if (bits (this_instr, 12, 15) == 15) | |
1564 | return 1; | |
1565 | else | |
1566 | return 0; | |
c906108c | 1567 | |
0d39a070 DJ |
1568 | case 0x2: |
1569 | case 0x3: | |
1570 | /* Media instructions and architecturally undefined instructions. */ | |
1571 | if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1) | |
1572 | return 0; | |
c906108c | 1573 | |
0d39a070 DJ |
1574 | /* Stores. */ |
1575 | if (bit (this_instr, 20) == 0) | |
1576 | return 0; | |
2a451106 | 1577 | |
0d39a070 DJ |
1578 | /* Loads. */ |
1579 | if (bits (this_instr, 12, 15) == ARM_PC_REGNUM) | |
1580 | return 1; | |
1581 | else | |
1582 | return 0; | |
2a451106 | 1583 | |
0d39a070 DJ |
1584 | case 0x4: |
1585 | /* Load/store multiple. */ | |
1586 | if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1) | |
1587 | return 1; | |
1588 | else | |
1589 | return 0; | |
2a451106 | 1590 | |
0d39a070 DJ |
1591 | case 0x5: |
1592 | /* Branch and branch with link. */ | |
1593 | return 1; | |
2a451106 | 1594 | |
0d39a070 DJ |
1595 | case 0x6: |
1596 | case 0x7: | |
1597 | /* Coprocessor transfers or SWIs can not affect PC. */ | |
1598 | return 0; | |
eb5492fa | 1599 | |
0d39a070 | 1600 | default: |
9b20d036 | 1601 | internal_error (__FILE__, __LINE__, _("bad value in switch")); |
0d39a070 DJ |
1602 | } |
1603 | } | |
c906108c | 1604 | |
f303bc3e YQ |
1605 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1606 | otherwise. */ | |
1607 | ||
1608 | static int | |
1609 | arm_instruction_restores_sp (unsigned int insn) | |
1610 | { | |
1611 | if (bits (insn, 28, 31) != INST_NV) | |
1612 | { | |
1613 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1614 | /* ADD SP (register or immediate). */ | |
1615 | || (insn & 0x0df0f000) == 0x0040d000 | |
1616 | /* SUB SP (register or immediate). */ | |
1617 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1618 | /* MOV SP. */ | |
1619 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1620 | /* POP (LDMIA). */ | |
1621 | || (insn & 0x0fff0000) == 0x049d0000) | |
1622 | /* POP of a single register. */ | |
1623 | return 1; | |
1624 | } | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | ||
0d39a070 DJ |
1629 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1630 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1631 | fill it in. Return the first address not recognized as a prologue | |
1632 | instruction. | |
eb5492fa | 1633 | |
0d39a070 DJ |
1634 | We recognize all the instructions typically found in ARM prologues, |
1635 | plus harmless instructions which can be skipped (either for analysis | |
1636 | purposes, or a more restrictive set that can be skipped when finding | |
1637 | the end of the prologue). */ | |
1638 | ||
1639 | static CORE_ADDR | |
1640 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1641 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
1642 | struct arm_prologue_cache *cache) | |
1643 | { | |
1644 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1645 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1646 | int regno; | |
1647 | CORE_ADDR offset, current_pc; | |
1648 | pv_t regs[ARM_FPS_REGNUM]; | |
1649 | struct pv_area *stack; | |
1650 | struct cleanup *back_to; | |
0d39a070 DJ |
1651 | CORE_ADDR unrecognized_pc = 0; |
1652 | ||
1653 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1654 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1655 | |
96baa820 JM |
1656 | Be careful, however, and if it doesn't look like a prologue, |
1657 | don't try to scan it. If, for instance, a frameless function | |
1658 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1659 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1660 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1661 | traceback. */ |
d4473757 | 1662 | |
4be43953 DJ |
1663 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1664 | regs[regno] = pv_register (regno, 0); | |
55f960e1 | 1665 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 DJ |
1666 | back_to = make_cleanup_free_pv_area (stack); |
1667 | ||
94c30b78 MS |
1668 | for (current_pc = prologue_start; |
1669 | current_pc < prologue_end; | |
f43845b3 | 1670 | current_pc += 4) |
96baa820 | 1671 | { |
e17a4113 UW |
1672 | unsigned int insn |
1673 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); | |
9d4fde75 | 1674 | |
94c30b78 | 1675 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1676 | { |
4be43953 | 1677 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1678 | continue; |
1679 | } | |
0d39a070 DJ |
1680 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1681 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 JG |
1682 | { |
1683 | unsigned imm = insn & 0xff; /* immediate value */ | |
1684 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
0d39a070 | 1685 | int rd = bits (insn, 12, 15); |
28cd8767 | 1686 | imm = (imm >> rot) | (imm << (32 - rot)); |
0d39a070 | 1687 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1688 | continue; |
1689 | } | |
0d39a070 DJ |
1690 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1691 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 JG |
1692 | { |
1693 | unsigned imm = insn & 0xff; /* immediate value */ | |
1694 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
0d39a070 | 1695 | int rd = bits (insn, 12, 15); |
28cd8767 | 1696 | imm = (imm >> rot) | (imm << (32 - rot)); |
0d39a070 | 1697 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1698 | continue; |
1699 | } | |
0963b4bd MS |
1700 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1701 | [sp, #-4]! */ | |
f43845b3 | 1702 | { |
4be43953 DJ |
1703 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1704 | break; | |
1705 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
0d39a070 DJ |
1706 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, |
1707 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1708 | continue; |
1709 | } | |
1710 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1711 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1712 | or | |
1713 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1714 | { |
d4473757 | 1715 | int mask = insn & 0xffff; |
ed9a39eb | 1716 | |
4be43953 DJ |
1717 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1718 | break; | |
1719 | ||
94c30b78 | 1720 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1721 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1722 | if (mask & (1 << regno)) |
1723 | { | |
0963b4bd MS |
1724 | regs[ARM_SP_REGNUM] |
1725 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
4be43953 | 1726 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1727 | } |
1728 | } | |
0d39a070 DJ |
1729 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1730 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1731 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1732 | { |
1733 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1734 | continue; | |
1735 | } | |
0d39a070 DJ |
1736 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1737 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1738 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1739 | { |
1740 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1741 | continue; | |
1742 | } | |
0963b4bd MS |
1743 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1744 | { registers } */ | |
0d39a070 DJ |
1745 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1746 | { | |
1747 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1748 | continue; | |
1749 | } | |
d4473757 KB |
1750 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1751 | { | |
94c30b78 MS |
1752 | unsigned imm = insn & 0xff; /* immediate value */ |
1753 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 1754 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 1755 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1756 | } |
1757 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1758 | { | |
94c30b78 MS |
1759 | unsigned imm = insn & 0xff; /* immediate value */ |
1760 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 1761 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 1762 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1763 | } |
0963b4bd MS |
1764 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1765 | [sp, -#c]! */ | |
2af46ca0 | 1766 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 1767 | { |
4be43953 DJ |
1768 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1769 | break; | |
1770 | ||
1771 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1772 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 1773 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1774 | } |
0963b4bd MS |
1775 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1776 | [sp!] */ | |
2af46ca0 | 1777 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
1778 | { |
1779 | int n_saved_fp_regs; | |
1780 | unsigned int fp_start_reg, fp_bound_reg; | |
1781 | ||
4be43953 DJ |
1782 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1783 | break; | |
1784 | ||
94c30b78 | 1785 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1786 | { |
d4473757 KB |
1787 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1788 | n_saved_fp_regs = 3; | |
1789 | else | |
1790 | n_saved_fp_regs = 1; | |
96baa820 | 1791 | } |
d4473757 | 1792 | else |
96baa820 | 1793 | { |
d4473757 KB |
1794 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1795 | n_saved_fp_regs = 2; | |
1796 | else | |
1797 | n_saved_fp_regs = 4; | |
96baa820 | 1798 | } |
d4473757 | 1799 | |
34e8f22d | 1800 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1801 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1802 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1803 | { |
4be43953 DJ |
1804 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
1805 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
1806 | regs[fp_start_reg++]); | |
96baa820 | 1807 | } |
c906108c | 1808 | } |
0d39a070 DJ |
1809 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
1810 | { | |
1811 | /* Allow some special function calls when skipping the | |
1812 | prologue; GCC generates these before storing arguments to | |
1813 | the stack. */ | |
1814 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
1815 | ||
e0634ccf | 1816 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
1817 | continue; |
1818 | else | |
1819 | break; | |
1820 | } | |
d4473757 | 1821 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 1822 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
1823 | else if (arm_instruction_changes_pc (insn)) |
1824 | /* Don't scan past anything that might change control flow. */ | |
1825 | break; | |
f303bc3e YQ |
1826 | else if (arm_instruction_restores_sp (insn)) |
1827 | { | |
1828 | /* Don't scan past the epilogue. */ | |
1829 | break; | |
1830 | } | |
d19f7eee UW |
1831 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
1832 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1833 | /* Ignore block loads from the stack, potentially copying | |
1834 | parameters from memory. */ | |
1835 | continue; | |
1836 | else if ((insn & 0xfc500000) == 0xe4100000 | |
1837 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1838 | /* Similarly ignore single loads from the stack. */ | |
1839 | continue; | |
0d39a070 DJ |
1840 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
1841 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
1842 | register instead of the stack. */ | |
d4473757 | 1843 | continue; |
0d39a070 DJ |
1844 | else |
1845 | { | |
21daaaaf YQ |
1846 | /* The optimizer might shove anything into the prologue, if |
1847 | we build up cache (cache != NULL) from scanning prologue, | |
1848 | we just skip what we don't recognize and scan further to | |
1849 | make cache as complete as possible. However, if we skip | |
1850 | prologue, we'll stop immediately on unrecognized | |
1851 | instruction. */ | |
0d39a070 | 1852 | unrecognized_pc = current_pc; |
21daaaaf YQ |
1853 | if (cache != NULL) |
1854 | continue; | |
1855 | else | |
1856 | break; | |
0d39a070 | 1857 | } |
c906108c SS |
1858 | } |
1859 | ||
0d39a070 DJ |
1860 | if (unrecognized_pc == 0) |
1861 | unrecognized_pc = current_pc; | |
1862 | ||
0d39a070 DJ |
1863 | if (cache) |
1864 | { | |
4072f920 YQ |
1865 | int framereg, framesize; |
1866 | ||
1867 | /* The frame size is just the distance from the frame register | |
1868 | to the original stack pointer. */ | |
1869 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1870 | { | |
1871 | /* Frame pointer is fp. */ | |
1872 | framereg = ARM_FP_REGNUM; | |
1873 | framesize = -regs[ARM_FP_REGNUM].k; | |
1874 | } | |
1875 | else | |
1876 | { | |
1877 | /* Try the stack pointer... this is a bit desperate. */ | |
1878 | framereg = ARM_SP_REGNUM; | |
1879 | framesize = -regs[ARM_SP_REGNUM].k; | |
1880 | } | |
1881 | ||
0d39a070 DJ |
1882 | cache->framereg = framereg; |
1883 | cache->framesize = framesize; | |
1884 | ||
1885 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
1886 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
1887 | cache->saved_regs[regno].addr = offset; | |
1888 | } | |
1889 | ||
1890 | if (arm_debug) | |
1891 | fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", | |
1892 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 DJ |
1893 | |
1894 | do_cleanups (back_to); | |
0d39a070 DJ |
1895 | return unrecognized_pc; |
1896 | } | |
1897 | ||
1898 | static void | |
1899 | arm_scan_prologue (struct frame_info *this_frame, | |
1900 | struct arm_prologue_cache *cache) | |
1901 | { | |
1902 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1903 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1904 | int regno; | |
1905 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
1906 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
1907 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
1908 | pv_t regs[ARM_FPS_REGNUM]; | |
1909 | struct pv_area *stack; | |
1910 | struct cleanup *back_to; | |
1911 | CORE_ADDR offset; | |
1912 | ||
1913 | /* Assume there is no frame until proven otherwise. */ | |
1914 | cache->framereg = ARM_SP_REGNUM; | |
1915 | cache->framesize = 0; | |
1916 | ||
1917 | /* Check for Thumb prologue. */ | |
1918 | if (arm_frame_is_thumb (this_frame)) | |
1919 | { | |
1920 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
1921 | return; | |
1922 | } | |
1923 | ||
1924 | /* Find the function prologue. If we can't find the function in | |
1925 | the symbol table, peek in the stack frame to find the PC. */ | |
1926 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
1927 | &prologue_end)) | |
1928 | { | |
1929 | /* One way to find the end of the prologue (which works well | |
1930 | for unoptimized code) is to do the following: | |
1931 | ||
1932 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
1933 | ||
1934 | if (sal.line == 0) | |
1935 | prologue_end = prev_pc; | |
1936 | else if (sal.end < prologue_end) | |
1937 | prologue_end = sal.end; | |
1938 | ||
1939 | This mechanism is very accurate so long as the optimizer | |
1940 | doesn't move any instructions from the function body into the | |
1941 | prologue. If this happens, sal.end will be the last | |
1942 | instruction in the first hunk of prologue code just before | |
1943 | the first instruction that the scheduler has moved from | |
1944 | the body to the prologue. | |
1945 | ||
1946 | In order to make sure that we scan all of the prologue | |
1947 | instructions, we use a slightly less accurate mechanism which | |
1948 | may scan more than necessary. To help compensate for this | |
1949 | lack of accuracy, the prologue scanning loop below contains | |
1950 | several clauses which'll cause the loop to terminate early if | |
1951 | an implausible prologue instruction is encountered. | |
1952 | ||
1953 | The expression | |
1954 | ||
1955 | prologue_start + 64 | |
1956 | ||
1957 | is a suitable endpoint since it accounts for the largest | |
1958 | possible prologue plus up to five instructions inserted by | |
1959 | the scheduler. */ | |
1960 | ||
1961 | if (prologue_end > prologue_start + 64) | |
1962 | { | |
1963 | prologue_end = prologue_start + 64; /* See above. */ | |
1964 | } | |
1965 | } | |
1966 | else | |
1967 | { | |
1968 | /* We have no symbol information. Our only option is to assume this | |
1969 | function has a standard stack frame and the normal frame register. | |
1970 | Then, we can find the value of our frame pointer on entrance to | |
1971 | the callee (or at the present moment if this is the innermost frame). | |
1972 | The value stored there should be the address of the stmfd + 8. */ | |
1973 | CORE_ADDR frame_loc; | |
1974 | LONGEST return_value; | |
1975 | ||
1976 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); | |
1977 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) | |
1978 | return; | |
1979 | else | |
1980 | { | |
1981 | prologue_start = gdbarch_addr_bits_remove | |
1982 | (gdbarch, return_value) - 8; | |
1983 | prologue_end = prologue_start + 64; /* See above. */ | |
1984 | } | |
1985 | } | |
1986 | ||
1987 | if (prev_pc < prologue_end) | |
1988 | prologue_end = prev_pc; | |
1989 | ||
1990 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); | |
c906108c SS |
1991 | } |
1992 | ||
eb5492fa | 1993 | static struct arm_prologue_cache * |
a262aec2 | 1994 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1995 | { |
eb5492fa DJ |
1996 | int reg; |
1997 | struct arm_prologue_cache *cache; | |
1998 | CORE_ADDR unwound_fp; | |
c5aa993b | 1999 | |
35d5d4ee | 2000 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 2001 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 2002 | |
a262aec2 | 2003 | arm_scan_prologue (this_frame, cache); |
848cfffb | 2004 | |
a262aec2 | 2005 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
2006 | if (unwound_fp == 0) |
2007 | return cache; | |
c906108c | 2008 | |
4be43953 | 2009 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 2010 | |
eb5492fa DJ |
2011 | /* Calculate actual addresses of saved registers using offsets |
2012 | determined by arm_scan_prologue. */ | |
a262aec2 | 2013 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 2014 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
2015 | cache->saved_regs[reg].addr += cache->prev_sp; |
2016 | ||
2017 | return cache; | |
c906108c SS |
2018 | } |
2019 | ||
c1ee9414 LM |
2020 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
2021 | ||
2022 | static enum unwind_stop_reason | |
2023 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
2024 | void **this_cache) | |
2025 | { | |
2026 | struct arm_prologue_cache *cache; | |
2027 | CORE_ADDR pc; | |
2028 | ||
2029 | if (*this_cache == NULL) | |
2030 | *this_cache = arm_make_prologue_cache (this_frame); | |
2031 | cache = *this_cache; | |
2032 | ||
2033 | /* This is meant to halt the backtrace at "_start". */ | |
2034 | pc = get_frame_pc (this_frame); | |
2035 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
2036 | return UNWIND_OUTERMOST; | |
2037 | ||
2038 | /* If we've hit a wall, stop. */ | |
2039 | if (cache->prev_sp == 0) | |
2040 | return UNWIND_OUTERMOST; | |
2041 | ||
2042 | return UNWIND_NO_REASON; | |
2043 | } | |
2044 | ||
eb5492fa DJ |
2045 | /* Our frame ID for a normal frame is the current function's starting PC |
2046 | and the caller's SP when we were called. */ | |
c906108c | 2047 | |
148754e5 | 2048 | static void |
a262aec2 | 2049 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
2050 | void **this_cache, |
2051 | struct frame_id *this_id) | |
c906108c | 2052 | { |
eb5492fa DJ |
2053 | struct arm_prologue_cache *cache; |
2054 | struct frame_id id; | |
2c404490 | 2055 | CORE_ADDR pc, func; |
f079148d | 2056 | |
eb5492fa | 2057 | if (*this_cache == NULL) |
a262aec2 | 2058 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 2059 | cache = *this_cache; |
2a451106 | 2060 | |
0e9e9abd UW |
2061 | /* Use function start address as part of the frame ID. If we cannot |
2062 | identify the start address (due to missing symbol information), | |
2063 | fall back to just using the current PC. */ | |
c1ee9414 | 2064 | pc = get_frame_pc (this_frame); |
2c404490 | 2065 | func = get_frame_func (this_frame); |
0e9e9abd UW |
2066 | if (!func) |
2067 | func = pc; | |
2068 | ||
eb5492fa | 2069 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 2070 | *this_id = id; |
c906108c SS |
2071 | } |
2072 | ||
a262aec2 DJ |
2073 | static struct value * |
2074 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 2075 | void **this_cache, |
a262aec2 | 2076 | int prev_regnum) |
24de872b | 2077 | { |
24568a2c | 2078 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
2079 | struct arm_prologue_cache *cache; |
2080 | ||
eb5492fa | 2081 | if (*this_cache == NULL) |
a262aec2 | 2082 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 2083 | cache = *this_cache; |
24de872b | 2084 | |
eb5492fa | 2085 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
2086 | instead. The prologue may save PC, but it will point into this |
2087 | frame's prologue, not the next frame's resume location. Also | |
2088 | strip the saved T bit. A valid LR may have the low bit set, but | |
2089 | a valid PC never does. */ | |
eb5492fa | 2090 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
2091 | { |
2092 | CORE_ADDR lr; | |
2093 | ||
2094 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2095 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 2096 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 2097 | } |
24de872b | 2098 | |
eb5492fa | 2099 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 2100 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2101 | The value was already reconstructed into PREV_SP. */ |
2102 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 2103 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 2104 | |
b39cc962 DJ |
2105 | /* The CPSR may have been changed by the call instruction and by the |
2106 | called function. The only bit we can reconstruct is the T bit, | |
2107 | by checking the low bit of LR as of the call. This is a reliable | |
2108 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2109 | Thumb code, which could get away with a clear low bit as long as | |
2110 | the called function did not use bx. Guess that all other | |
2111 | bits are unchanged; the condition flags are presumably lost, | |
2112 | but the processor status is likely valid. */ | |
2113 | if (prev_regnum == ARM_PS_REGNUM) | |
2114 | { | |
2115 | CORE_ADDR lr, cpsr; | |
9779414d | 2116 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
2117 | |
2118 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
2119 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2120 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 2121 | cpsr |= t_bit; |
b39cc962 | 2122 | else |
9779414d | 2123 | cpsr &= ~t_bit; |
b39cc962 DJ |
2124 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2125 | } | |
2126 | ||
a262aec2 DJ |
2127 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2128 | prev_regnum); | |
eb5492fa DJ |
2129 | } |
2130 | ||
2131 | struct frame_unwind arm_prologue_unwind = { | |
2132 | NORMAL_FRAME, | |
c1ee9414 | 2133 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2134 | arm_prologue_this_id, |
a262aec2 DJ |
2135 | arm_prologue_prev_register, |
2136 | NULL, | |
2137 | default_frame_sniffer | |
eb5492fa DJ |
2138 | }; |
2139 | ||
0e9e9abd UW |
2140 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2141 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2142 | personality routines; the cache will contain only the frame unwinding | |
2143 | instructions associated with the entry (not the descriptors). */ | |
2144 | ||
2145 | static const struct objfile_data *arm_exidx_data_key; | |
2146 | ||
2147 | struct arm_exidx_entry | |
2148 | { | |
2149 | bfd_vma addr; | |
2150 | gdb_byte *entry; | |
2151 | }; | |
2152 | typedef struct arm_exidx_entry arm_exidx_entry_s; | |
2153 | DEF_VEC_O(arm_exidx_entry_s); | |
2154 | ||
2155 | struct arm_exidx_data | |
2156 | { | |
2157 | VEC(arm_exidx_entry_s) **section_maps; | |
2158 | }; | |
2159 | ||
2160 | static void | |
2161 | arm_exidx_data_free (struct objfile *objfile, void *arg) | |
2162 | { | |
2163 | struct arm_exidx_data *data = arg; | |
2164 | unsigned int i; | |
2165 | ||
2166 | for (i = 0; i < objfile->obfd->section_count; i++) | |
2167 | VEC_free (arm_exidx_entry_s, data->section_maps[i]); | |
2168 | } | |
2169 | ||
2170 | static inline int | |
2171 | arm_compare_exidx_entries (const struct arm_exidx_entry *lhs, | |
2172 | const struct arm_exidx_entry *rhs) | |
2173 | { | |
2174 | return lhs->addr < rhs->addr; | |
2175 | } | |
2176 | ||
2177 | static struct obj_section * | |
2178 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2179 | { | |
2180 | struct obj_section *osect; | |
2181 | ||
2182 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
2183 | if (bfd_get_section_flags (objfile->obfd, | |
2184 | osect->the_bfd_section) & SEC_ALLOC) | |
2185 | { | |
2186 | bfd_vma start, size; | |
2187 | start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section); | |
2188 | size = bfd_get_section_size (osect->the_bfd_section); | |
2189 | ||
2190 | if (start <= vma && vma < start + size) | |
2191 | return osect; | |
2192 | } | |
2193 | ||
2194 | return NULL; | |
2195 | } | |
2196 | ||
2197 | /* Parse contents of exception table and exception index sections | |
2198 | of OBJFILE, and fill in the exception table entry cache. | |
2199 | ||
2200 | For each entry that refers to a standard ARM-defined personality | |
2201 | routine, extract the frame unwinding instructions (from either | |
2202 | the index or the table section). The unwinding instructions | |
2203 | are normalized by: | |
2204 | - extracting them from the rest of the table data | |
2205 | - converting to host endianness | |
2206 | - appending the implicit 0xb0 ("Finish") code | |
2207 | ||
2208 | The extracted and normalized instructions are stored for later | |
2209 | retrieval by the arm_find_exidx_entry routine. */ | |
2210 | ||
2211 | static void | |
2212 | arm_exidx_new_objfile (struct objfile *objfile) | |
2213 | { | |
3bb47e8b | 2214 | struct cleanup *cleanups; |
0e9e9abd UW |
2215 | struct arm_exidx_data *data; |
2216 | asection *exidx, *extab; | |
2217 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
2218 | bfd_size_type exidx_size = 0, extab_size = 0; | |
2219 | gdb_byte *exidx_data = NULL, *extab_data = NULL; | |
2220 | LONGEST i; | |
2221 | ||
2222 | /* If we've already touched this file, do nothing. */ | |
2223 | if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL) | |
2224 | return; | |
3bb47e8b | 2225 | cleanups = make_cleanup (null_cleanup, NULL); |
0e9e9abd UW |
2226 | |
2227 | /* Read contents of exception table and index. */ | |
2228 | exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx"); | |
2229 | if (exidx) | |
2230 | { | |
2231 | exidx_vma = bfd_section_vma (objfile->obfd, exidx); | |
2232 | exidx_size = bfd_get_section_size (exidx); | |
2233 | exidx_data = xmalloc (exidx_size); | |
2234 | make_cleanup (xfree, exidx_data); | |
2235 | ||
2236 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
2237 | exidx_data, 0, exidx_size)) | |
2238 | { | |
2239 | do_cleanups (cleanups); | |
2240 | return; | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
2245 | if (extab) | |
2246 | { | |
2247 | extab_vma = bfd_section_vma (objfile->obfd, extab); | |
2248 | extab_size = bfd_get_section_size (extab); | |
2249 | extab_data = xmalloc (extab_size); | |
2250 | make_cleanup (xfree, extab_data); | |
2251 | ||
2252 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
2253 | extab_data, 0, extab_size)) | |
2254 | { | |
2255 | do_cleanups (cleanups); | |
2256 | return; | |
2257 | } | |
2258 | } | |
2259 | ||
2260 | /* Allocate exception table data structure. */ | |
2261 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data); | |
2262 | set_objfile_data (objfile, arm_exidx_data_key, data); | |
2263 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
2264 | objfile->obfd->section_count, | |
2265 | VEC(arm_exidx_entry_s) *); | |
2266 | ||
2267 | /* Fill in exception table. */ | |
2268 | for (i = 0; i < exidx_size / 8; i++) | |
2269 | { | |
2270 | struct arm_exidx_entry new_exidx_entry; | |
2271 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8); | |
2272 | bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4); | |
2273 | bfd_vma addr = 0, word = 0; | |
2274 | int n_bytes = 0, n_words = 0; | |
2275 | struct obj_section *sec; | |
2276 | gdb_byte *entry = NULL; | |
2277 | ||
2278 | /* Extract address of start of function. */ | |
2279 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2280 | idx += exidx_vma + i * 8; | |
2281 | ||
2282 | /* Find section containing function and compute section offset. */ | |
2283 | sec = arm_obj_section_from_vma (objfile, idx); | |
2284 | if (sec == NULL) | |
2285 | continue; | |
2286 | idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section); | |
2287 | ||
2288 | /* Determine address of exception table entry. */ | |
2289 | if (val == 1) | |
2290 | { | |
2291 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2292 | } | |
2293 | else if ((val & 0xff000000) == 0x80000000) | |
2294 | { | |
2295 | /* Exception table entry embedded in .ARM.exidx | |
2296 | -- must be short form. */ | |
2297 | word = val; | |
2298 | n_bytes = 3; | |
2299 | } | |
2300 | else if (!(val & 0x80000000)) | |
2301 | { | |
2302 | /* Exception table entry in .ARM.extab. */ | |
2303 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2304 | addr += exidx_vma + i * 8 + 4; | |
2305 | ||
2306 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size) | |
2307 | { | |
2308 | word = bfd_h_get_32 (objfile->obfd, | |
2309 | extab_data + addr - extab_vma); | |
2310 | addr += 4; | |
2311 | ||
2312 | if ((word & 0xff000000) == 0x80000000) | |
2313 | { | |
2314 | /* Short form. */ | |
2315 | n_bytes = 3; | |
2316 | } | |
2317 | else if ((word & 0xff000000) == 0x81000000 | |
2318 | || (word & 0xff000000) == 0x82000000) | |
2319 | { | |
2320 | /* Long form. */ | |
2321 | n_bytes = 2; | |
2322 | n_words = ((word >> 16) & 0xff); | |
2323 | } | |
2324 | else if (!(word & 0x80000000)) | |
2325 | { | |
2326 | bfd_vma pers; | |
2327 | struct obj_section *pers_sec; | |
2328 | int gnu_personality = 0; | |
2329 | ||
2330 | /* Custom personality routine. */ | |
2331 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2332 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2333 | ||
2334 | /* Check whether we've got one of the variants of the | |
2335 | GNU personality routines. */ | |
2336 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2337 | if (pers_sec) | |
2338 | { | |
2339 | static const char *personality[] = | |
2340 | { | |
2341 | "__gcc_personality_v0", | |
2342 | "__gxx_personality_v0", | |
2343 | "__gcj_personality_v0", | |
2344 | "__gnu_objc_personality_v0", | |
2345 | NULL | |
2346 | }; | |
2347 | ||
2348 | CORE_ADDR pc = pers + obj_section_offset (pers_sec); | |
2349 | int k; | |
2350 | ||
2351 | for (k = 0; personality[k]; k++) | |
2352 | if (lookup_minimal_symbol_by_pc_name | |
2353 | (pc, personality[k], objfile)) | |
2354 | { | |
2355 | gnu_personality = 1; | |
2356 | break; | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | /* If so, the next word contains a word count in the high | |
2361 | byte, followed by the same unwind instructions as the | |
2362 | pre-defined forms. */ | |
2363 | if (gnu_personality | |
2364 | && addr + 4 <= extab_vma + extab_size) | |
2365 | { | |
2366 | word = bfd_h_get_32 (objfile->obfd, | |
2367 | extab_data + addr - extab_vma); | |
2368 | addr += 4; | |
2369 | n_bytes = 3; | |
2370 | n_words = ((word >> 24) & 0xff); | |
2371 | } | |
2372 | } | |
2373 | } | |
2374 | } | |
2375 | ||
2376 | /* Sanity check address. */ | |
2377 | if (n_words) | |
2378 | if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size) | |
2379 | n_words = n_bytes = 0; | |
2380 | ||
2381 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2382 | significant bytes are valid), followed by N_WORDS words in the | |
2383 | extab section starting at ADDR. */ | |
2384 | if (n_bytes || n_words) | |
2385 | { | |
2386 | gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack, | |
2387 | n_bytes + n_words * 4 + 1); | |
2388 | ||
2389 | while (n_bytes--) | |
2390 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2391 | ||
2392 | while (n_words--) | |
2393 | { | |
2394 | word = bfd_h_get_32 (objfile->obfd, | |
2395 | extab_data + addr - extab_vma); | |
2396 | addr += 4; | |
2397 | ||
2398 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2399 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2400 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2401 | *p++ = (gdb_byte) (word & 0xff); | |
2402 | } | |
2403 | ||
2404 | /* Implied "Finish" to terminate the list. */ | |
2405 | *p++ = 0xb0; | |
2406 | } | |
2407 | ||
2408 | /* Push entry onto vector. They are guaranteed to always | |
2409 | appear in order of increasing addresses. */ | |
2410 | new_exidx_entry.addr = idx; | |
2411 | new_exidx_entry.entry = entry; | |
2412 | VEC_safe_push (arm_exidx_entry_s, | |
2413 | data->section_maps[sec->the_bfd_section->index], | |
2414 | &new_exidx_entry); | |
2415 | } | |
2416 | ||
2417 | do_cleanups (cleanups); | |
2418 | } | |
2419 | ||
2420 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2421 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2422 | set *START to the start of the region covered by this entry. */ | |
2423 | ||
2424 | static gdb_byte * | |
2425 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2426 | { | |
2427 | struct obj_section *sec; | |
2428 | ||
2429 | sec = find_pc_section (memaddr); | |
2430 | if (sec != NULL) | |
2431 | { | |
2432 | struct arm_exidx_data *data; | |
2433 | VEC(arm_exidx_entry_s) *map; | |
2434 | struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 }; | |
2435 | unsigned int idx; | |
2436 | ||
2437 | data = objfile_data (sec->objfile, arm_exidx_data_key); | |
2438 | if (data != NULL) | |
2439 | { | |
2440 | map = data->section_maps[sec->the_bfd_section->index]; | |
2441 | if (!VEC_empty (arm_exidx_entry_s, map)) | |
2442 | { | |
2443 | struct arm_exidx_entry *map_sym; | |
2444 | ||
2445 | idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key, | |
2446 | arm_compare_exidx_entries); | |
2447 | ||
2448 | /* VEC_lower_bound finds the earliest ordered insertion | |
2449 | point. If the following symbol starts at this exact | |
2450 | address, we use that; otherwise, the preceding | |
2451 | exception table entry covers this address. */ | |
2452 | if (idx < VEC_length (arm_exidx_entry_s, map)) | |
2453 | { | |
2454 | map_sym = VEC_index (arm_exidx_entry_s, map, idx); | |
2455 | if (map_sym->addr == map_key.addr) | |
2456 | { | |
2457 | if (start) | |
2458 | *start = map_sym->addr + obj_section_addr (sec); | |
2459 | return map_sym->entry; | |
2460 | } | |
2461 | } | |
2462 | ||
2463 | if (idx > 0) | |
2464 | { | |
2465 | map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1); | |
2466 | if (start) | |
2467 | *start = map_sym->addr + obj_section_addr (sec); | |
2468 | return map_sym->entry; | |
2469 | } | |
2470 | } | |
2471 | } | |
2472 | } | |
2473 | ||
2474 | return NULL; | |
2475 | } | |
2476 | ||
2477 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2478 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2479 | return a prologue cache structure describing how to unwind this frame. | |
2480 | ||
2481 | Return NULL if the unwinding instruction list contains a "spare", | |
2482 | "reserved" or "refuse to unwind" instruction as defined in section | |
2483 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2484 | for the ARM Architecture" document. */ | |
2485 | ||
2486 | static struct arm_prologue_cache * | |
2487 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2488 | { | |
2489 | CORE_ADDR vsp = 0; | |
2490 | int vsp_valid = 0; | |
2491 | ||
2492 | struct arm_prologue_cache *cache; | |
2493 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2494 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2495 | ||
2496 | for (;;) | |
2497 | { | |
2498 | gdb_byte insn; | |
2499 | ||
2500 | /* Whenever we reload SP, we actually have to retrieve its | |
2501 | actual value in the current frame. */ | |
2502 | if (!vsp_valid) | |
2503 | { | |
2504 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2505 | { | |
2506 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2507 | vsp = get_frame_register_unsigned (this_frame, reg); | |
2508 | } | |
2509 | else | |
2510 | { | |
2511 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr; | |
2512 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); | |
2513 | } | |
2514 | ||
2515 | vsp_valid = 1; | |
2516 | } | |
2517 | ||
2518 | /* Decode next unwind instruction. */ | |
2519 | insn = *entry++; | |
2520 | ||
2521 | if ((insn & 0xc0) == 0) | |
2522 | { | |
2523 | int offset = insn & 0x3f; | |
2524 | vsp += (offset << 2) + 4; | |
2525 | } | |
2526 | else if ((insn & 0xc0) == 0x40) | |
2527 | { | |
2528 | int offset = insn & 0x3f; | |
2529 | vsp -= (offset << 2) + 4; | |
2530 | } | |
2531 | else if ((insn & 0xf0) == 0x80) | |
2532 | { | |
2533 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2534 | int i; | |
2535 | ||
2536 | /* The special case of an all-zero mask identifies | |
2537 | "Refuse to unwind". We return NULL to fall back | |
2538 | to the prologue analyzer. */ | |
2539 | if (mask == 0) | |
2540 | return NULL; | |
2541 | ||
2542 | /* Pop registers r4..r15 under mask. */ | |
2543 | for (i = 0; i < 12; i++) | |
2544 | if (mask & (1 << i)) | |
2545 | { | |
2546 | cache->saved_regs[4 + i].addr = vsp; | |
2547 | vsp += 4; | |
2548 | } | |
2549 | ||
2550 | /* Special-case popping SP -- we need to reload vsp. */ | |
2551 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2552 | vsp_valid = 0; | |
2553 | } | |
2554 | else if ((insn & 0xf0) == 0x90) | |
2555 | { | |
2556 | int reg = insn & 0xf; | |
2557 | ||
2558 | /* Reserved cases. */ | |
2559 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2560 | return NULL; | |
2561 | ||
2562 | /* Set SP from another register and mark VSP for reload. */ | |
2563 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2564 | vsp_valid = 0; | |
2565 | } | |
2566 | else if ((insn & 0xf0) == 0xa0) | |
2567 | { | |
2568 | int count = insn & 0x7; | |
2569 | int pop_lr = (insn & 0x8) != 0; | |
2570 | int i; | |
2571 | ||
2572 | /* Pop r4..r[4+count]. */ | |
2573 | for (i = 0; i <= count; i++) | |
2574 | { | |
2575 | cache->saved_regs[4 + i].addr = vsp; | |
2576 | vsp += 4; | |
2577 | } | |
2578 | ||
2579 | /* If indicated by flag, pop LR as well. */ | |
2580 | if (pop_lr) | |
2581 | { | |
2582 | cache->saved_regs[ARM_LR_REGNUM].addr = vsp; | |
2583 | vsp += 4; | |
2584 | } | |
2585 | } | |
2586 | else if (insn == 0xb0) | |
2587 | { | |
2588 | /* We could only have updated PC by popping into it; if so, it | |
2589 | will show up as address. Otherwise, copy LR into PC. */ | |
2590 | if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM)) | |
2591 | cache->saved_regs[ARM_PC_REGNUM] | |
2592 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2593 | ||
2594 | /* We're done. */ | |
2595 | break; | |
2596 | } | |
2597 | else if (insn == 0xb1) | |
2598 | { | |
2599 | int mask = *entry++; | |
2600 | int i; | |
2601 | ||
2602 | /* All-zero mask and mask >= 16 is "spare". */ | |
2603 | if (mask == 0 || mask >= 16) | |
2604 | return NULL; | |
2605 | ||
2606 | /* Pop r0..r3 under mask. */ | |
2607 | for (i = 0; i < 4; i++) | |
2608 | if (mask & (1 << i)) | |
2609 | { | |
2610 | cache->saved_regs[i].addr = vsp; | |
2611 | vsp += 4; | |
2612 | } | |
2613 | } | |
2614 | else if (insn == 0xb2) | |
2615 | { | |
2616 | ULONGEST offset = 0; | |
2617 | unsigned shift = 0; | |
2618 | ||
2619 | do | |
2620 | { | |
2621 | offset |= (*entry & 0x7f) << shift; | |
2622 | shift += 7; | |
2623 | } | |
2624 | while (*entry++ & 0x80); | |
2625 | ||
2626 | vsp += 0x204 + (offset << 2); | |
2627 | } | |
2628 | else if (insn == 0xb3) | |
2629 | { | |
2630 | int start = *entry >> 4; | |
2631 | int count = (*entry++) & 0xf; | |
2632 | int i; | |
2633 | ||
2634 | /* Only registers D0..D15 are valid here. */ | |
2635 | if (start + count >= 16) | |
2636 | return NULL; | |
2637 | ||
2638 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2639 | for (i = 0; i <= count; i++) | |
2640 | { | |
2641 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2642 | vsp += 8; | |
2643 | } | |
2644 | ||
2645 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2646 | vsp += 4; | |
2647 | } | |
2648 | else if ((insn & 0xf8) == 0xb8) | |
2649 | { | |
2650 | int count = insn & 0x7; | |
2651 | int i; | |
2652 | ||
2653 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2654 | for (i = 0; i <= count; i++) | |
2655 | { | |
2656 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2657 | vsp += 8; | |
2658 | } | |
2659 | ||
2660 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2661 | vsp += 4; | |
2662 | } | |
2663 | else if (insn == 0xc6) | |
2664 | { | |
2665 | int start = *entry >> 4; | |
2666 | int count = (*entry++) & 0xf; | |
2667 | int i; | |
2668 | ||
2669 | /* Only registers WR0..WR15 are valid. */ | |
2670 | if (start + count >= 16) | |
2671 | return NULL; | |
2672 | ||
2673 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2674 | for (i = 0; i <= count; i++) | |
2675 | { | |
2676 | cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp; | |
2677 | vsp += 8; | |
2678 | } | |
2679 | } | |
2680 | else if (insn == 0xc7) | |
2681 | { | |
2682 | int mask = *entry++; | |
2683 | int i; | |
2684 | ||
2685 | /* All-zero mask and mask >= 16 is "spare". */ | |
2686 | if (mask == 0 || mask >= 16) | |
2687 | return NULL; | |
2688 | ||
2689 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2690 | for (i = 0; i < 4; i++) | |
2691 | if (mask & (1 << i)) | |
2692 | { | |
2693 | cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp; | |
2694 | vsp += 4; | |
2695 | } | |
2696 | } | |
2697 | else if ((insn & 0xf8) == 0xc0) | |
2698 | { | |
2699 | int count = insn & 0x7; | |
2700 | int i; | |
2701 | ||
2702 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2703 | for (i = 0; i <= count; i++) | |
2704 | { | |
2705 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp; | |
2706 | vsp += 8; | |
2707 | } | |
2708 | } | |
2709 | else if (insn == 0xc8) | |
2710 | { | |
2711 | int start = *entry >> 4; | |
2712 | int count = (*entry++) & 0xf; | |
2713 | int i; | |
2714 | ||
2715 | /* Only registers D0..D31 are valid. */ | |
2716 | if (start + count >= 16) | |
2717 | return NULL; | |
2718 | ||
2719 | /* Pop VFP double-precision registers | |
2720 | D[16+start]..D[16+start+count]. */ | |
2721 | for (i = 0; i <= count; i++) | |
2722 | { | |
2723 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp; | |
2724 | vsp += 8; | |
2725 | } | |
2726 | } | |
2727 | else if (insn == 0xc9) | |
2728 | { | |
2729 | int start = *entry >> 4; | |
2730 | int count = (*entry++) & 0xf; | |
2731 | int i; | |
2732 | ||
2733 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2734 | for (i = 0; i <= count; i++) | |
2735 | { | |
2736 | cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp; | |
2737 | vsp += 8; | |
2738 | } | |
2739 | } | |
2740 | else if ((insn & 0xf8) == 0xd0) | |
2741 | { | |
2742 | int count = insn & 0x7; | |
2743 | int i; | |
2744 | ||
2745 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2746 | for (i = 0; i <= count; i++) | |
2747 | { | |
2748 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp; | |
2749 | vsp += 8; | |
2750 | } | |
2751 | } | |
2752 | else | |
2753 | { | |
2754 | /* Everything else is "spare". */ | |
2755 | return NULL; | |
2756 | } | |
2757 | } | |
2758 | ||
2759 | /* If we restore SP from a register, assume this was the frame register. | |
2760 | Otherwise just fall back to SP as frame register. */ | |
2761 | if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM)) | |
2762 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg; | |
2763 | else | |
2764 | cache->framereg = ARM_SP_REGNUM; | |
2765 | ||
2766 | /* Determine offset to previous frame. */ | |
2767 | cache->framesize | |
2768 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2769 | ||
2770 | /* We already got the previous SP. */ | |
2771 | cache->prev_sp = vsp; | |
2772 | ||
2773 | return cache; | |
2774 | } | |
2775 | ||
2776 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2777 | already computes a filled-in prologue cache, which is then used | |
2778 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2779 | routines also used for prologue-parsing based unwinding. */ | |
2780 | ||
2781 | static int | |
2782 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
2783 | struct frame_info *this_frame, | |
2784 | void **this_prologue_cache) | |
2785 | { | |
2786 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2787 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2788 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
2789 | struct arm_prologue_cache *cache; | |
2790 | gdb_byte *entry; | |
2791 | ||
2792 | /* See if we have an ARM exception table entry covering this address. */ | |
2793 | addr_in_block = get_frame_address_in_block (this_frame); | |
2794 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
2795 | if (!entry) | |
2796 | return 0; | |
2797 | ||
2798 | /* The ARM exception table does not describe unwind information | |
2799 | for arbitrary PC values, but is guaranteed to be correct only | |
2800 | at call sites. We have to decide here whether we want to use | |
2801 | ARM exception table information for this frame, or fall back | |
2802 | to using prologue parsing. (Note that if we have DWARF CFI, | |
2803 | this sniffer isn't even called -- CFI is always preferred.) | |
2804 | ||
2805 | Before we make this decision, however, we check whether we | |
2806 | actually have *symbol* information for the current frame. | |
2807 | If not, prologue parsing would not work anyway, so we might | |
2808 | as well use the exception table and hope for the best. */ | |
2809 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
2810 | { | |
2811 | int exc_valid = 0; | |
2812 | ||
2813 | /* If the next frame is "normal", we are at a call site in this | |
2814 | frame, so exception information is guaranteed to be valid. */ | |
2815 | if (get_next_frame (this_frame) | |
2816 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
2817 | exc_valid = 1; | |
2818 | ||
2819 | /* We also assume exception information is valid if we're currently | |
2820 | blocked in a system call. The system library is supposed to | |
2821 | ensure this, so that e.g. pthread cancellation works. */ | |
2822 | if (arm_frame_is_thumb (this_frame)) | |
2823 | { | |
2824 | LONGEST insn; | |
2825 | ||
2826 | if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2, | |
2827 | byte_order_for_code, &insn) | |
2828 | && (insn & 0xff00) == 0xdf00 /* svc */) | |
2829 | exc_valid = 1; | |
2830 | } | |
2831 | else | |
2832 | { | |
2833 | LONGEST insn; | |
2834 | ||
2835 | if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4, | |
2836 | byte_order_for_code, &insn) | |
2837 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) | |
2838 | exc_valid = 1; | |
2839 | } | |
2840 | ||
2841 | /* Bail out if we don't know that exception information is valid. */ | |
2842 | if (!exc_valid) | |
2843 | return 0; | |
2844 | ||
2845 | /* The ARM exception index does not mark the *end* of the region | |
2846 | covered by the entry, and some functions will not have any entry. | |
2847 | To correctly recognize the end of the covered region, the linker | |
2848 | should have inserted dummy records with a CANTUNWIND marker. | |
2849 | ||
2850 | Unfortunately, current versions of GNU ld do not reliably do | |
2851 | this, and thus we may have found an incorrect entry above. | |
2852 | As a (temporary) sanity check, we only use the entry if it | |
2853 | lies *within* the bounds of the function. Note that this check | |
2854 | might reject perfectly valid entries that just happen to cover | |
2855 | multiple functions; therefore this check ought to be removed | |
2856 | once the linker is fixed. */ | |
2857 | if (func_start > exidx_region) | |
2858 | return 0; | |
2859 | } | |
2860 | ||
2861 | /* Decode the list of unwinding instructions into a prologue cache. | |
2862 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
2863 | cache = arm_exidx_fill_cache (this_frame, entry); | |
2864 | if (!cache) | |
2865 | return 0; | |
2866 | ||
2867 | *this_prologue_cache = cache; | |
2868 | return 1; | |
2869 | } | |
2870 | ||
2871 | struct frame_unwind arm_exidx_unwind = { | |
2872 | NORMAL_FRAME, | |
8fbca658 | 2873 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
2874 | arm_prologue_this_id, |
2875 | arm_prologue_prev_register, | |
2876 | NULL, | |
2877 | arm_exidx_unwind_sniffer | |
2878 | }; | |
2879 | ||
80d8d390 YQ |
2880 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
2881 | trampoline, return the target PC. Otherwise return 0. | |
2882 | ||
2883 | void call0a (char c, short s, int i, long l) {} | |
2884 | ||
2885 | int main (void) | |
2886 | { | |
2887 | (*pointer_to_call0a) (c, s, i, l); | |
2888 | } | |
2889 | ||
2890 | Instead of calling a stub library function _call_via_xx (xx is | |
2891 | the register name), GCC may inline the trampoline in the object | |
2892 | file as below (register r2 has the address of call0a). | |
2893 | ||
2894 | .global main | |
2895 | .type main, %function | |
2896 | ... | |
2897 | bl .L1 | |
2898 | ... | |
2899 | .size main, .-main | |
2900 | ||
2901 | .L1: | |
2902 | bx r2 | |
2903 | ||
2904 | The trampoline 'bx r2' doesn't belong to main. */ | |
2905 | ||
2906 | static CORE_ADDR | |
2907 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
2908 | { | |
2909 | /* The heuristics of recognizing such trampoline is that FRAME is | |
2910 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
2911 | if (arm_frame_is_thumb (frame)) | |
2912 | { | |
2913 | gdb_byte buf[2]; | |
2914 | ||
2915 | if (target_read_memory (pc, buf, 2) == 0) | |
2916 | { | |
2917 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2918 | enum bfd_endian byte_order_for_code | |
2919 | = gdbarch_byte_order_for_code (gdbarch); | |
2920 | uint16_t insn | |
2921 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
2922 | ||
2923 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
2924 | { | |
2925 | CORE_ADDR dest | |
2926 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
2927 | ||
2928 | /* Clear the LSB so that gdb core sets step-resume | |
2929 | breakpoint at the right address. */ | |
2930 | return UNMAKE_THUMB_ADDR (dest); | |
2931 | } | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
909cf6ea | 2938 | static struct arm_prologue_cache * |
a262aec2 | 2939 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 2940 | { |
909cf6ea | 2941 | struct arm_prologue_cache *cache; |
909cf6ea | 2942 | |
35d5d4ee | 2943 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 2944 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 2945 | |
a262aec2 | 2946 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
2947 | |
2948 | return cache; | |
2949 | } | |
2950 | ||
2951 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
2952 | ||
2953 | static void | |
a262aec2 | 2954 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
2955 | void **this_cache, |
2956 | struct frame_id *this_id) | |
2957 | { | |
2958 | struct arm_prologue_cache *cache; | |
2959 | ||
2960 | if (*this_cache == NULL) | |
a262aec2 | 2961 | *this_cache = arm_make_stub_cache (this_frame); |
909cf6ea DJ |
2962 | cache = *this_cache; |
2963 | ||
a262aec2 | 2964 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
2965 | } |
2966 | ||
a262aec2 DJ |
2967 | static int |
2968 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
2969 | struct frame_info *this_frame, | |
2970 | void **this_prologue_cache) | |
909cf6ea | 2971 | { |
93d42b30 | 2972 | CORE_ADDR addr_in_block; |
948f8e3d | 2973 | gdb_byte dummy[4]; |
18d18ac8 YQ |
2974 | CORE_ADDR pc, start_addr; |
2975 | const char *name; | |
909cf6ea | 2976 | |
a262aec2 | 2977 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 2978 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 2979 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
2980 | /* We also use the stub winder if the target memory is unreadable |
2981 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
2982 | || target_read_memory (pc, dummy, 4) != 0) |
2983 | return 1; | |
2984 | ||
2985 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
2986 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 2987 | return 1; |
909cf6ea | 2988 | |
a262aec2 | 2989 | return 0; |
909cf6ea DJ |
2990 | } |
2991 | ||
a262aec2 DJ |
2992 | struct frame_unwind arm_stub_unwind = { |
2993 | NORMAL_FRAME, | |
8fbca658 | 2994 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
2995 | arm_stub_this_id, |
2996 | arm_prologue_prev_register, | |
2997 | NULL, | |
2998 | arm_stub_unwind_sniffer | |
2999 | }; | |
3000 | ||
2ae28aa9 YQ |
3001 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
3002 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
3003 | returned. */ | |
3004 | ||
3005 | static struct arm_prologue_cache * | |
3006 | arm_m_exception_cache (struct frame_info *this_frame) | |
3007 | { | |
3008 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3009 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3010 | struct arm_prologue_cache *cache; | |
3011 | CORE_ADDR unwound_sp; | |
3012 | LONGEST xpsr; | |
3013 | ||
3014 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
3015 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
3016 | ||
3017 | unwound_sp = get_frame_register_unsigned (this_frame, | |
3018 | ARM_SP_REGNUM); | |
3019 | ||
3020 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3021 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3022 | "B1.5.6 Exception entry behavior" in | |
3023 | "ARMv7-M Architecture Reference Manual". */ | |
3024 | cache->saved_regs[0].addr = unwound_sp; | |
3025 | cache->saved_regs[1].addr = unwound_sp + 4; | |
3026 | cache->saved_regs[2].addr = unwound_sp + 8; | |
3027 | cache->saved_regs[3].addr = unwound_sp + 12; | |
3028 | cache->saved_regs[12].addr = unwound_sp + 16; | |
3029 | cache->saved_regs[14].addr = unwound_sp + 20; | |
3030 | cache->saved_regs[15].addr = unwound_sp + 24; | |
3031 | cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28; | |
3032 | ||
3033 | /* If bit 9 of the saved xPSR is set, then there is a four-byte | |
3034 | aligner between the top of the 32-byte stack frame and the | |
3035 | previous context's stack pointer. */ | |
3036 | cache->prev_sp = unwound_sp + 32; | |
3037 | if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) | |
3038 | && (xpsr & (1 << 9)) != 0) | |
3039 | cache->prev_sp += 4; | |
3040 | ||
3041 | return cache; | |
3042 | } | |
3043 | ||
3044 | /* Implementation of function hook 'this_id' in | |
3045 | 'struct frame_uwnind'. */ | |
3046 | ||
3047 | static void | |
3048 | arm_m_exception_this_id (struct frame_info *this_frame, | |
3049 | void **this_cache, | |
3050 | struct frame_id *this_id) | |
3051 | { | |
3052 | struct arm_prologue_cache *cache; | |
3053 | ||
3054 | if (*this_cache == NULL) | |
3055 | *this_cache = arm_m_exception_cache (this_frame); | |
3056 | cache = *this_cache; | |
3057 | ||
3058 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3059 | *this_id = frame_id_build (cache->prev_sp, | |
3060 | get_frame_pc (this_frame)); | |
3061 | } | |
3062 | ||
3063 | /* Implementation of function hook 'prev_register' in | |
3064 | 'struct frame_uwnind'. */ | |
3065 | ||
3066 | static struct value * | |
3067 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
3068 | void **this_cache, | |
3069 | int prev_regnum) | |
3070 | { | |
3071 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3072 | struct arm_prologue_cache *cache; | |
3073 | ||
3074 | if (*this_cache == NULL) | |
3075 | *this_cache = arm_m_exception_cache (this_frame); | |
3076 | cache = *this_cache; | |
3077 | ||
3078 | /* The value was already reconstructed into PREV_SP. */ | |
3079 | if (prev_regnum == ARM_SP_REGNUM) | |
3080 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3081 | cache->prev_sp); | |
3082 | ||
3083 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3084 | prev_regnum); | |
3085 | } | |
3086 | ||
3087 | /* Implementation of function hook 'sniffer' in | |
3088 | 'struct frame_uwnind'. */ | |
3089 | ||
3090 | static int | |
3091 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
3092 | struct frame_info *this_frame, | |
3093 | void **this_prologue_cache) | |
3094 | { | |
3095 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
3096 | ||
3097 | /* No need to check is_m; this sniffer is only registered for | |
3098 | M-profile architectures. */ | |
3099 | ||
3100 | /* Exception frames return to one of these magic PCs. Other values | |
3101 | are not defined as of v7-M. See details in "B1.5.8 Exception | |
3102 | return behavior" in "ARMv7-M Architecture Reference Manual". */ | |
3103 | if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9 | |
3104 | || this_pc == 0xfffffffd) | |
3105 | return 1; | |
3106 | ||
3107 | return 0; | |
3108 | } | |
3109 | ||
3110 | /* Frame unwinder for M-profile exceptions. */ | |
3111 | ||
3112 | struct frame_unwind arm_m_exception_unwind = | |
3113 | { | |
3114 | SIGTRAMP_FRAME, | |
3115 | default_frame_unwind_stop_reason, | |
3116 | arm_m_exception_this_id, | |
3117 | arm_m_exception_prev_register, | |
3118 | NULL, | |
3119 | arm_m_exception_unwind_sniffer | |
3120 | }; | |
3121 | ||
24de872b | 3122 | static CORE_ADDR |
a262aec2 | 3123 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
3124 | { |
3125 | struct arm_prologue_cache *cache; | |
3126 | ||
eb5492fa | 3127 | if (*this_cache == NULL) |
a262aec2 | 3128 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa DJ |
3129 | cache = *this_cache; |
3130 | ||
4be43953 | 3131 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
3132 | } |
3133 | ||
eb5492fa DJ |
3134 | struct frame_base arm_normal_base = { |
3135 | &arm_prologue_unwind, | |
3136 | arm_normal_frame_base, | |
3137 | arm_normal_frame_base, | |
3138 | arm_normal_frame_base | |
3139 | }; | |
3140 | ||
a262aec2 | 3141 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
3142 | dummy frame. The frame ID's base needs to match the TOS value |
3143 | saved by save_dummy_frame_tos() and returned from | |
3144 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
3145 | breakpoint. */ | |
c906108c | 3146 | |
eb5492fa | 3147 | static struct frame_id |
a262aec2 | 3148 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 3149 | { |
0963b4bd MS |
3150 | return frame_id_build (get_frame_register_unsigned (this_frame, |
3151 | ARM_SP_REGNUM), | |
a262aec2 | 3152 | get_frame_pc (this_frame)); |
eb5492fa | 3153 | } |
c3b4394c | 3154 | |
eb5492fa DJ |
3155 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
3156 | be used to construct the previous frame's ID, after looking up the | |
3157 | containing function). */ | |
c3b4394c | 3158 | |
eb5492fa DJ |
3159 | static CORE_ADDR |
3160 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
3161 | { | |
3162 | CORE_ADDR pc; | |
3163 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
24568a2c | 3164 | return arm_addr_bits_remove (gdbarch, pc); |
eb5492fa DJ |
3165 | } |
3166 | ||
3167 | static CORE_ADDR | |
3168 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
3169 | { | |
3170 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
3171 | } |
3172 | ||
b39cc962 DJ |
3173 | static struct value * |
3174 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
3175 | int regnum) | |
3176 | { | |
24568a2c | 3177 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 | 3178 | CORE_ADDR lr, cpsr; |
9779414d | 3179 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
3180 | |
3181 | switch (regnum) | |
3182 | { | |
3183 | case ARM_PC_REGNUM: | |
3184 | /* The PC is normally copied from the return column, which | |
3185 | describes saves of LR. However, that version may have an | |
3186 | extra bit set to indicate Thumb state. The bit is not | |
3187 | part of the PC. */ | |
3188 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
3189 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3190 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
3191 | |
3192 | case ARM_PS_REGNUM: | |
3193 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 3194 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
3195 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3196 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 3197 | cpsr |= t_bit; |
b39cc962 | 3198 | else |
9779414d | 3199 | cpsr &= ~t_bit; |
ca38c58e | 3200 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3201 | |
3202 | default: | |
3203 | internal_error (__FILE__, __LINE__, | |
3204 | _("Unexpected register %d"), regnum); | |
3205 | } | |
3206 | } | |
3207 | ||
3208 | static void | |
3209 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3210 | struct dwarf2_frame_state_reg *reg, | |
3211 | struct frame_info *this_frame) | |
3212 | { | |
3213 | switch (regnum) | |
3214 | { | |
3215 | case ARM_PC_REGNUM: | |
3216 | case ARM_PS_REGNUM: | |
3217 | reg->how = DWARF2_FRAME_REG_FN; | |
3218 | reg->loc.fn = arm_dwarf2_prev_register; | |
3219 | break; | |
3220 | case ARM_SP_REGNUM: | |
3221 | reg->how = DWARF2_FRAME_REG_CFA; | |
3222 | break; | |
3223 | } | |
3224 | } | |
3225 | ||
4024ca99 UW |
3226 | /* Return true if we are in the function's epilogue, i.e. after the |
3227 | instruction that destroyed the function's stack frame. */ | |
3228 | ||
3229 | static int | |
3230 | thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3231 | { | |
3232 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3233 | unsigned int insn, insn2; | |
3234 | int found_return = 0, found_stack_adjust = 0; | |
3235 | CORE_ADDR func_start, func_end; | |
3236 | CORE_ADDR scan_pc; | |
3237 | gdb_byte buf[4]; | |
3238 | ||
3239 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3240 | return 0; | |
3241 | ||
3242 | /* The epilogue is a sequence of instructions along the following lines: | |
3243 | ||
3244 | - add stack frame size to SP or FP | |
3245 | - [if frame pointer used] restore SP from FP | |
3246 | - restore registers from SP [may include PC] | |
3247 | - a return-type instruction [if PC wasn't already restored] | |
3248 | ||
3249 | In a first pass, we scan forward from the current PC and verify the | |
3250 | instructions we find as compatible with this sequence, ending in a | |
3251 | return instruction. | |
3252 | ||
3253 | However, this is not sufficient to distinguish indirect function calls | |
3254 | within a function from indirect tail calls in the epilogue in some cases. | |
3255 | Therefore, if we didn't already find any SP-changing instruction during | |
3256 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3257 | are in the epilogue. */ | |
3258 | ||
3259 | scan_pc = pc; | |
3260 | while (scan_pc < func_end && !found_return) | |
3261 | { | |
3262 | if (target_read_memory (scan_pc, buf, 2)) | |
3263 | break; | |
3264 | ||
3265 | scan_pc += 2; | |
3266 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3267 | ||
3268 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3269 | found_return = 1; | |
3270 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3271 | found_return = 1; | |
540314bd | 3272 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3273 | { |
b7576e5c | 3274 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3275 | found_return = 1; |
3276 | } | |
db24da6d | 3277 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3278 | { |
3279 | if (target_read_memory (scan_pc, buf, 2)) | |
3280 | break; | |
3281 | ||
3282 | scan_pc += 2; | |
3283 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3284 | ||
3285 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3286 | { | |
4024ca99 UW |
3287 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3288 | found_return = 1; | |
3289 | } | |
3290 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3291 | && (insn2 & 0x0fff) == 0x0b04) | |
3292 | { | |
4024ca99 UW |
3293 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3294 | found_return = 1; | |
3295 | } | |
3296 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3297 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3298 | ; |
4024ca99 UW |
3299 | else |
3300 | break; | |
3301 | } | |
3302 | else | |
3303 | break; | |
3304 | } | |
3305 | ||
3306 | if (!found_return) | |
3307 | return 0; | |
3308 | ||
3309 | /* Since any instruction in the epilogue sequence, with the possible | |
3310 | exception of return itself, updates the stack pointer, we need to | |
3311 | scan backwards for at most one instruction. Try either a 16-bit or | |
3312 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3313 | too much about false positives. */ |
4024ca99 | 3314 | |
6b65d1b6 YQ |
3315 | if (pc - 4 < func_start) |
3316 | return 0; | |
3317 | if (target_read_memory (pc - 4, buf, 4)) | |
3318 | return 0; | |
4024ca99 | 3319 | |
6b65d1b6 YQ |
3320 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3321 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3322 | ||
3323 | if (thumb_instruction_restores_sp (insn2)) | |
3324 | found_stack_adjust = 1; | |
3325 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3326 | found_stack_adjust = 1; | |
3327 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3328 | && (insn2 & 0x0fff) == 0x0b04) | |
3329 | found_stack_adjust = 1; | |
3330 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3331 | && (insn2 & 0x0e00) == 0x0a00) | |
3332 | found_stack_adjust = 1; | |
4024ca99 UW |
3333 | |
3334 | return found_stack_adjust; | |
3335 | } | |
3336 | ||
3337 | /* Return true if we are in the function's epilogue, i.e. after the | |
3338 | instruction that destroyed the function's stack frame. */ | |
3339 | ||
3340 | static int | |
3341 | arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3342 | { | |
3343 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3344 | unsigned int insn; | |
f303bc3e | 3345 | int found_return; |
4024ca99 UW |
3346 | CORE_ADDR func_start, func_end; |
3347 | ||
3348 | if (arm_pc_is_thumb (gdbarch, pc)) | |
3349 | return thumb_in_function_epilogue_p (gdbarch, pc); | |
3350 | ||
3351 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3352 | return 0; | |
3353 | ||
3354 | /* We are in the epilogue if the previous instruction was a stack | |
3355 | adjustment and the next instruction is a possible return (bx, mov | |
3356 | pc, or pop). We could have to scan backwards to find the stack | |
3357 | adjustment, or forwards to find the return, but this is a decent | |
3358 | approximation. First scan forwards. */ | |
3359 | ||
3360 | found_return = 0; | |
3361 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3362 | if (bits (insn, 28, 31) != INST_NV) | |
3363 | { | |
3364 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3365 | /* BX. */ | |
3366 | found_return = 1; | |
3367 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3368 | /* MOV PC. */ | |
3369 | found_return = 1; | |
3370 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3371 | && (insn & 0x0000c000) != 0) | |
3372 | /* POP (LDMIA), including PC or LR. */ | |
3373 | found_return = 1; | |
3374 | } | |
3375 | ||
3376 | if (!found_return) | |
3377 | return 0; | |
3378 | ||
3379 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3380 | false positives from mode changes. */ | |
3381 | ||
3382 | if (pc < func_start + 4) | |
3383 | return 0; | |
3384 | ||
3385 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3386 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3387 | return 1; |
3388 | ||
3389 | return 0; | |
3390 | } | |
3391 | ||
3392 | ||
2dd604e7 RE |
3393 | /* When arguments must be pushed onto the stack, they go on in reverse |
3394 | order. The code below implements a FILO (stack) to do this. */ | |
3395 | ||
3396 | struct stack_item | |
3397 | { | |
3398 | int len; | |
3399 | struct stack_item *prev; | |
3400 | void *data; | |
3401 | }; | |
3402 | ||
3403 | static struct stack_item * | |
8c6363cf | 3404 | push_stack_item (struct stack_item *prev, const void *contents, int len) |
2dd604e7 RE |
3405 | { |
3406 | struct stack_item *si; | |
3407 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 3408 | si->data = xmalloc (len); |
2dd604e7 RE |
3409 | si->len = len; |
3410 | si->prev = prev; | |
3411 | memcpy (si->data, contents, len); | |
3412 | return si; | |
3413 | } | |
3414 | ||
3415 | static struct stack_item * | |
3416 | pop_stack_item (struct stack_item *si) | |
3417 | { | |
3418 | struct stack_item *dead = si; | |
3419 | si = si->prev; | |
3420 | xfree (dead->data); | |
3421 | xfree (dead); | |
3422 | return si; | |
3423 | } | |
3424 | ||
2af48f68 PB |
3425 | |
3426 | /* Return the alignment (in bytes) of the given type. */ | |
3427 | ||
3428 | static int | |
3429 | arm_type_align (struct type *t) | |
3430 | { | |
3431 | int n; | |
3432 | int align; | |
3433 | int falign; | |
3434 | ||
3435 | t = check_typedef (t); | |
3436 | switch (TYPE_CODE (t)) | |
3437 | { | |
3438 | default: | |
3439 | /* Should never happen. */ | |
3440 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
3441 | return 4; | |
3442 | ||
3443 | case TYPE_CODE_PTR: | |
3444 | case TYPE_CODE_ENUM: | |
3445 | case TYPE_CODE_INT: | |
3446 | case TYPE_CODE_FLT: | |
3447 | case TYPE_CODE_SET: | |
3448 | case TYPE_CODE_RANGE: | |
2af48f68 PB |
3449 | case TYPE_CODE_REF: |
3450 | case TYPE_CODE_CHAR: | |
3451 | case TYPE_CODE_BOOL: | |
3452 | return TYPE_LENGTH (t); | |
3453 | ||
3454 | case TYPE_CODE_ARRAY: | |
3455 | case TYPE_CODE_COMPLEX: | |
3456 | /* TODO: What about vector types? */ | |
3457 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
3458 | ||
3459 | case TYPE_CODE_STRUCT: | |
3460 | case TYPE_CODE_UNION: | |
3461 | align = 1; | |
3462 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
3463 | { | |
3464 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
3465 | if (falign > align) | |
3466 | align = falign; | |
3467 | } | |
3468 | return align; | |
3469 | } | |
3470 | } | |
3471 | ||
90445bd3 DJ |
3472 | /* Possible base types for a candidate for passing and returning in |
3473 | VFP registers. */ | |
3474 | ||
3475 | enum arm_vfp_cprc_base_type | |
3476 | { | |
3477 | VFP_CPRC_UNKNOWN, | |
3478 | VFP_CPRC_SINGLE, | |
3479 | VFP_CPRC_DOUBLE, | |
3480 | VFP_CPRC_VEC64, | |
3481 | VFP_CPRC_VEC128 | |
3482 | }; | |
3483 | ||
3484 | /* The length of one element of base type B. */ | |
3485 | ||
3486 | static unsigned | |
3487 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
3488 | { | |
3489 | switch (b) | |
3490 | { | |
3491 | case VFP_CPRC_SINGLE: | |
3492 | return 4; | |
3493 | case VFP_CPRC_DOUBLE: | |
3494 | return 8; | |
3495 | case VFP_CPRC_VEC64: | |
3496 | return 8; | |
3497 | case VFP_CPRC_VEC128: | |
3498 | return 16; | |
3499 | default: | |
3500 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3501 | (int) b); | |
3502 | } | |
3503 | } | |
3504 | ||
3505 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
3506 | for passing base type B. */ | |
3507 | ||
3508 | static int | |
3509 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
3510 | { | |
3511 | switch (b) | |
3512 | { | |
3513 | case VFP_CPRC_SINGLE: | |
3514 | return 's'; | |
3515 | case VFP_CPRC_DOUBLE: | |
3516 | return 'd'; | |
3517 | case VFP_CPRC_VEC64: | |
3518 | return 'd'; | |
3519 | case VFP_CPRC_VEC128: | |
3520 | return 'q'; | |
3521 | default: | |
3522 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3523 | (int) b); | |
3524 | } | |
3525 | } | |
3526 | ||
3527 | /* Determine whether T may be part of a candidate for passing and | |
3528 | returning in VFP registers, ignoring the limit on the total number | |
3529 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
3530 | classification of the first valid component found; if it is not | |
3531 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
3532 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
3533 | for passing and returning in VFP registers, a type differently | |
3534 | classified from *BASE_TYPE, or two types differently classified | |
3535 | from each other, return -1, otherwise return the total number of | |
3536 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
3537 | array). Vector types are not currently supported, matching the |
3538 | generic AAPCS support. */ | |
90445bd3 DJ |
3539 | |
3540 | static int | |
3541 | arm_vfp_cprc_sub_candidate (struct type *t, | |
3542 | enum arm_vfp_cprc_base_type *base_type) | |
3543 | { | |
3544 | t = check_typedef (t); | |
3545 | switch (TYPE_CODE (t)) | |
3546 | { | |
3547 | case TYPE_CODE_FLT: | |
3548 | switch (TYPE_LENGTH (t)) | |
3549 | { | |
3550 | case 4: | |
3551 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3552 | *base_type = VFP_CPRC_SINGLE; | |
3553 | else if (*base_type != VFP_CPRC_SINGLE) | |
3554 | return -1; | |
3555 | return 1; | |
3556 | ||
3557 | case 8: | |
3558 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3559 | *base_type = VFP_CPRC_DOUBLE; | |
3560 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3561 | return -1; | |
3562 | return 1; | |
3563 | ||
3564 | default: | |
3565 | return -1; | |
3566 | } | |
3567 | break; | |
3568 | ||
817e0957 YQ |
3569 | case TYPE_CODE_COMPLEX: |
3570 | /* Arguments of complex T where T is one of the types float or | |
3571 | double get treated as if they are implemented as: | |
3572 | ||
3573 | struct complexT | |
3574 | { | |
3575 | T real; | |
3576 | T imag; | |
5f52445b YQ |
3577 | }; |
3578 | ||
3579 | */ | |
817e0957 YQ |
3580 | switch (TYPE_LENGTH (t)) |
3581 | { | |
3582 | case 8: | |
3583 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3584 | *base_type = VFP_CPRC_SINGLE; | |
3585 | else if (*base_type != VFP_CPRC_SINGLE) | |
3586 | return -1; | |
3587 | return 2; | |
3588 | ||
3589 | case 16: | |
3590 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3591 | *base_type = VFP_CPRC_DOUBLE; | |
3592 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3593 | return -1; | |
3594 | return 2; | |
3595 | ||
3596 | default: | |
3597 | return -1; | |
3598 | } | |
3599 | break; | |
3600 | ||
90445bd3 DJ |
3601 | case TYPE_CODE_ARRAY: |
3602 | { | |
3603 | int count; | |
3604 | unsigned unitlen; | |
3605 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); | |
3606 | if (count == -1) | |
3607 | return -1; | |
3608 | if (TYPE_LENGTH (t) == 0) | |
3609 | { | |
3610 | gdb_assert (count == 0); | |
3611 | return 0; | |
3612 | } | |
3613 | else if (count == 0) | |
3614 | return -1; | |
3615 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3616 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
3617 | return TYPE_LENGTH (t) / unitlen; | |
3618 | } | |
3619 | break; | |
3620 | ||
3621 | case TYPE_CODE_STRUCT: | |
3622 | { | |
3623 | int count = 0; | |
3624 | unsigned unitlen; | |
3625 | int i; | |
3626 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
3627 | { | |
3628 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
3629 | base_type); | |
3630 | if (sub_count == -1) | |
3631 | return -1; | |
3632 | count += sub_count; | |
3633 | } | |
3634 | if (TYPE_LENGTH (t) == 0) | |
3635 | { | |
3636 | gdb_assert (count == 0); | |
3637 | return 0; | |
3638 | } | |
3639 | else if (count == 0) | |
3640 | return -1; | |
3641 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3642 | if (TYPE_LENGTH (t) != unitlen * count) | |
3643 | return -1; | |
3644 | return count; | |
3645 | } | |
3646 | ||
3647 | case TYPE_CODE_UNION: | |
3648 | { | |
3649 | int count = 0; | |
3650 | unsigned unitlen; | |
3651 | int i; | |
3652 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
3653 | { | |
3654 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
3655 | base_type); | |
3656 | if (sub_count == -1) | |
3657 | return -1; | |
3658 | count = (count > sub_count ? count : sub_count); | |
3659 | } | |
3660 | if (TYPE_LENGTH (t) == 0) | |
3661 | { | |
3662 | gdb_assert (count == 0); | |
3663 | return 0; | |
3664 | } | |
3665 | else if (count == 0) | |
3666 | return -1; | |
3667 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3668 | if (TYPE_LENGTH (t) != unitlen * count) | |
3669 | return -1; | |
3670 | return count; | |
3671 | } | |
3672 | ||
3673 | default: | |
3674 | break; | |
3675 | } | |
3676 | ||
3677 | return -1; | |
3678 | } | |
3679 | ||
3680 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
3681 | if passed to or returned from a non-variadic function with the VFP | |
3682 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
3683 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
3684 | elements of that base type before returning. */ | |
3685 | ||
3686 | static int | |
3687 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
3688 | int *count) | |
3689 | { | |
3690 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
3691 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
3692 | if (c <= 0 || c > 4) | |
3693 | return 0; | |
3694 | *base_type = b; | |
3695 | *count = c; | |
3696 | return 1; | |
3697 | } | |
3698 | ||
3699 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
3700 | returning values from a function of type FUNC_TYPE, 0 | |
3701 | otherwise. */ | |
3702 | ||
3703 | static int | |
3704 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
3705 | { | |
3706 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3707 | /* Variadic functions always use the base ABI. Assume that functions | |
3708 | without debug info are not variadic. */ | |
3709 | if (func_type && TYPE_VARARGS (check_typedef (func_type))) | |
3710 | return 0; | |
3711 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
3712 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
3713 | return 0; | |
3714 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
3715 | } | |
3716 | ||
3717 | /* We currently only support passing parameters in integer registers, which | |
3718 | conforms with GCC's default model, and VFP argument passing following | |
3719 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
3720 | we should probably support some of them based on the selected ABI. */ |
3721 | ||
3722 | static CORE_ADDR | |
7d9b040b | 3723 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
3724 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
3725 | struct value **args, CORE_ADDR sp, int struct_return, | |
3726 | CORE_ADDR struct_addr) | |
2dd604e7 | 3727 | { |
e17a4113 | 3728 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
3729 | int argnum; |
3730 | int argreg; | |
3731 | int nstack; | |
3732 | struct stack_item *si = NULL; | |
90445bd3 DJ |
3733 | int use_vfp_abi; |
3734 | struct type *ftype; | |
3735 | unsigned vfp_regs_free = (1 << 16) - 1; | |
3736 | ||
3737 | /* Determine the type of this function and whether the VFP ABI | |
3738 | applies. */ | |
3739 | ftype = check_typedef (value_type (function)); | |
3740 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) | |
3741 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); | |
3742 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 3743 | |
6a65450a AC |
3744 | /* Set the return address. For the ARM, the return breakpoint is |
3745 | always at BP_ADDR. */ | |
9779414d | 3746 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 3747 | bp_addr |= 1; |
6a65450a | 3748 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
3749 | |
3750 | /* Walk through the list of args and determine how large a temporary | |
3751 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 3752 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
3753 | nstack = 0; |
3754 | ||
3755 | argreg = ARM_A1_REGNUM; | |
3756 | nstack = 0; | |
3757 | ||
2dd604e7 RE |
3758 | /* The struct_return pointer occupies the first parameter |
3759 | passing register. */ | |
3760 | if (struct_return) | |
3761 | { | |
3762 | if (arm_debug) | |
5af949e3 | 3763 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 3764 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 3765 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
3766 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
3767 | argreg++; | |
3768 | } | |
3769 | ||
3770 | for (argnum = 0; argnum < nargs; argnum++) | |
3771 | { | |
3772 | int len; | |
3773 | struct type *arg_type; | |
3774 | struct type *target_type; | |
3775 | enum type_code typecode; | |
8c6363cf | 3776 | const bfd_byte *val; |
2af48f68 | 3777 | int align; |
90445bd3 DJ |
3778 | enum arm_vfp_cprc_base_type vfp_base_type; |
3779 | int vfp_base_count; | |
3780 | int may_use_core_reg = 1; | |
2dd604e7 | 3781 | |
df407dfe | 3782 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
3783 | len = TYPE_LENGTH (arg_type); |
3784 | target_type = TYPE_TARGET_TYPE (arg_type); | |
3785 | typecode = TYPE_CODE (arg_type); | |
8c6363cf | 3786 | val = value_contents (args[argnum]); |
2dd604e7 | 3787 | |
2af48f68 PB |
3788 | align = arm_type_align (arg_type); |
3789 | /* Round alignment up to a whole number of words. */ | |
3790 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
3791 | /* Different ABIs have different maximum alignments. */ | |
3792 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
3793 | { | |
3794 | /* The APCS ABI only requires word alignment. */ | |
3795 | align = INT_REGISTER_SIZE; | |
3796 | } | |
3797 | else | |
3798 | { | |
3799 | /* The AAPCS requires at most doubleword alignment. */ | |
3800 | if (align > INT_REGISTER_SIZE * 2) | |
3801 | align = INT_REGISTER_SIZE * 2; | |
3802 | } | |
3803 | ||
90445bd3 DJ |
3804 | if (use_vfp_abi |
3805 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
3806 | &vfp_base_count)) | |
3807 | { | |
3808 | int regno; | |
3809 | int unit_length; | |
3810 | int shift; | |
3811 | unsigned mask; | |
3812 | ||
3813 | /* Because this is a CPRC it cannot go in a core register or | |
3814 | cause a core register to be skipped for alignment. | |
3815 | Either it goes in VFP registers and the rest of this loop | |
3816 | iteration is skipped for this argument, or it goes on the | |
3817 | stack (and the stack alignment code is correct for this | |
3818 | case). */ | |
3819 | may_use_core_reg = 0; | |
3820 | ||
3821 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3822 | shift = unit_length / 4; | |
3823 | mask = (1 << (shift * vfp_base_count)) - 1; | |
3824 | for (regno = 0; regno < 16; regno += shift) | |
3825 | if (((vfp_regs_free >> regno) & mask) == mask) | |
3826 | break; | |
3827 | ||
3828 | if (regno < 16) | |
3829 | { | |
3830 | int reg_char; | |
3831 | int reg_scaled; | |
3832 | int i; | |
3833 | ||
3834 | vfp_regs_free &= ~(mask << regno); | |
3835 | reg_scaled = regno / shift; | |
3836 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3837 | for (i = 0; i < vfp_base_count; i++) | |
3838 | { | |
3839 | char name_buf[4]; | |
3840 | int regnum; | |
58d6951d DJ |
3841 | if (reg_char == 'q') |
3842 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 3843 | val + i * unit_length); |
58d6951d DJ |
3844 | else |
3845 | { | |
8c042590 PM |
3846 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
3847 | reg_char, reg_scaled + i); | |
58d6951d DJ |
3848 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
3849 | strlen (name_buf)); | |
3850 | regcache_cooked_write (regcache, regnum, | |
3851 | val + i * unit_length); | |
3852 | } | |
90445bd3 DJ |
3853 | } |
3854 | continue; | |
3855 | } | |
3856 | else | |
3857 | { | |
3858 | /* This CPRC could not go in VFP registers, so all VFP | |
3859 | registers are now marked as used. */ | |
3860 | vfp_regs_free = 0; | |
3861 | } | |
3862 | } | |
3863 | ||
2af48f68 PB |
3864 | /* Push stack padding for dowubleword alignment. */ |
3865 | if (nstack & (align - 1)) | |
3866 | { | |
3867 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
3868 | nstack += INT_REGISTER_SIZE; | |
3869 | } | |
3870 | ||
3871 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
3872 | if (may_use_core_reg |
3873 | && argreg <= ARM_LAST_ARG_REGNUM | |
2af48f68 PB |
3874 | && align > INT_REGISTER_SIZE |
3875 | && argreg & 1) | |
3876 | argreg++; | |
3877 | ||
2dd604e7 RE |
3878 | /* If the argument is a pointer to a function, and it is a |
3879 | Thumb function, create a LOCAL copy of the value and set | |
3880 | the THUMB bit in it. */ | |
3881 | if (TYPE_CODE_PTR == typecode | |
3882 | && target_type != NULL | |
f96b8fa0 | 3883 | && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type))) |
2dd604e7 | 3884 | { |
e17a4113 | 3885 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 3886 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 3887 | { |
8c6363cf TT |
3888 | bfd_byte *copy = alloca (len); |
3889 | store_unsigned_integer (copy, len, byte_order, | |
e17a4113 | 3890 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 3891 | val = copy; |
2dd604e7 RE |
3892 | } |
3893 | } | |
3894 | ||
3895 | /* Copy the argument to general registers or the stack in | |
3896 | register-sized pieces. Large arguments are split between | |
3897 | registers and stack. */ | |
3898 | while (len > 0) | |
3899 | { | |
f0c9063c | 3900 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 | 3901 | |
90445bd3 | 3902 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
3903 | { |
3904 | /* The argument is being passed in a general purpose | |
3905 | register. */ | |
e17a4113 UW |
3906 | CORE_ADDR regval |
3907 | = extract_unsigned_integer (val, partial_len, byte_order); | |
3908 | if (byte_order == BFD_ENDIAN_BIG) | |
8bf8793c | 3909 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
3910 | if (arm_debug) |
3911 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
3912 | argnum, |
3913 | gdbarch_register_name | |
2af46ca0 | 3914 | (gdbarch, argreg), |
f0c9063c | 3915 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
3916 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
3917 | argreg++; | |
3918 | } | |
3919 | else | |
3920 | { | |
3921 | /* Push the arguments onto the stack. */ | |
3922 | if (arm_debug) | |
3923 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
3924 | argnum, nstack); | |
f0c9063c UW |
3925 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
3926 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
3927 | } |
3928 | ||
3929 | len -= partial_len; | |
3930 | val += partial_len; | |
3931 | } | |
3932 | } | |
3933 | /* If we have an odd number of words to push, then decrement the stack | |
3934 | by one word now, so first stack argument will be dword aligned. */ | |
3935 | if (nstack & 4) | |
3936 | sp -= 4; | |
3937 | ||
3938 | while (si) | |
3939 | { | |
3940 | sp -= si->len; | |
3941 | write_memory (sp, si->data, si->len); | |
3942 | si = pop_stack_item (si); | |
3943 | } | |
3944 | ||
3945 | /* Finally, update teh SP register. */ | |
3946 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
3947 | ||
3948 | return sp; | |
3949 | } | |
3950 | ||
f53f0d0b PB |
3951 | |
3952 | /* Always align the frame to an 8-byte boundary. This is required on | |
3953 | some platforms and harmless on the rest. */ | |
3954 | ||
3955 | static CORE_ADDR | |
3956 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
3957 | { | |
3958 | /* Align the stack to eight bytes. */ | |
3959 | return sp & ~ (CORE_ADDR) 7; | |
3960 | } | |
3961 | ||
c906108c | 3962 | static void |
12b27276 | 3963 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 3964 | { |
c5aa993b | 3965 | if (flags & (1 << 0)) |
12b27276 | 3966 | fputs_filtered ("IVO ", file); |
c5aa993b | 3967 | if (flags & (1 << 1)) |
12b27276 | 3968 | fputs_filtered ("DVZ ", file); |
c5aa993b | 3969 | if (flags & (1 << 2)) |
12b27276 | 3970 | fputs_filtered ("OFL ", file); |
c5aa993b | 3971 | if (flags & (1 << 3)) |
12b27276 | 3972 | fputs_filtered ("UFL ", file); |
c5aa993b | 3973 | if (flags & (1 << 4)) |
12b27276 WN |
3974 | fputs_filtered ("INX ", file); |
3975 | fputc_filtered ('\n', file); | |
c906108c SS |
3976 | } |
3977 | ||
5e74b15c RE |
3978 | /* Print interesting information about the floating point processor |
3979 | (if present) or emulator. */ | |
34e8f22d | 3980 | static void |
d855c300 | 3981 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 3982 | struct frame_info *frame, const char *args) |
c906108c | 3983 | { |
9c9acae0 | 3984 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
3985 | int type; |
3986 | ||
3987 | type = (status >> 24) & 127; | |
edefbb7c | 3988 | if (status & (1 << 31)) |
12b27276 | 3989 | fprintf_filtered (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 3990 | else |
12b27276 | 3991 | fprintf_filtered (file, _("Software FPU type %d\n"), type); |
edefbb7c | 3992 | /* i18n: [floating point unit] mask */ |
12b27276 WN |
3993 | fputs_filtered (_("mask: "), file); |
3994 | print_fpu_flags (file, status >> 16); | |
edefbb7c | 3995 | /* i18n: [floating point unit] flags */ |
12b27276 WN |
3996 | fputs_filtered (_("flags: "), file); |
3997 | print_fpu_flags (file, status); | |
c906108c SS |
3998 | } |
3999 | ||
27067745 UW |
4000 | /* Construct the ARM extended floating point type. */ |
4001 | static struct type * | |
4002 | arm_ext_type (struct gdbarch *gdbarch) | |
4003 | { | |
4004 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4005 | ||
4006 | if (!tdep->arm_ext_type) | |
4007 | tdep->arm_ext_type | |
e9bb382b | 4008 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4009 | floatformats_arm_ext); |
4010 | ||
4011 | return tdep->arm_ext_type; | |
4012 | } | |
4013 | ||
58d6951d DJ |
4014 | static struct type * |
4015 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4016 | { | |
4017 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4018 | ||
4019 | if (tdep->neon_double_type == NULL) | |
4020 | { | |
4021 | struct type *t, *elem; | |
4022 | ||
4023 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4024 | TYPE_CODE_UNION); | |
4025 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4026 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4027 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4028 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4029 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4030 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4031 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4032 | append_composite_type_field (t, "u64", elem); | |
4033 | elem = builtin_type (gdbarch)->builtin_float; | |
4034 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4035 | elem = builtin_type (gdbarch)->builtin_double; | |
4036 | append_composite_type_field (t, "f64", elem); | |
4037 | ||
4038 | TYPE_VECTOR (t) = 1; | |
4039 | TYPE_NAME (t) = "neon_d"; | |
4040 | tdep->neon_double_type = t; | |
4041 | } | |
4042 | ||
4043 | return tdep->neon_double_type; | |
4044 | } | |
4045 | ||
4046 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4047 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4048 | bits of d0 - regardless of what unit size is being held in d0. So | |
4049 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4050 | first float is 4. This code works as-is for little-endian | |
4051 | targets. */ | |
4052 | ||
4053 | static struct type * | |
4054 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4055 | { | |
4056 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4057 | ||
4058 | if (tdep->neon_quad_type == NULL) | |
4059 | { | |
4060 | struct type *t, *elem; | |
4061 | ||
4062 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4063 | TYPE_CODE_UNION); | |
4064 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4065 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4066 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4067 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4068 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4069 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4070 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4071 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4072 | elem = builtin_type (gdbarch)->builtin_float; | |
4073 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4074 | elem = builtin_type (gdbarch)->builtin_double; | |
4075 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4076 | ||
4077 | TYPE_VECTOR (t) = 1; | |
4078 | TYPE_NAME (t) = "neon_q"; | |
4079 | tdep->neon_quad_type = t; | |
4080 | } | |
4081 | ||
4082 | return tdep->neon_quad_type; | |
4083 | } | |
4084 | ||
34e8f22d RE |
4085 | /* Return the GDB type object for the "standard" data type of data in |
4086 | register N. */ | |
4087 | ||
4088 | static struct type * | |
7a5ea0d4 | 4089 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4090 | { |
58d6951d DJ |
4091 | int num_regs = gdbarch_num_regs (gdbarch); |
4092 | ||
4093 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
4094 | && regnum >= num_regs && regnum < num_regs + 32) | |
4095 | return builtin_type (gdbarch)->builtin_float; | |
4096 | ||
4097 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
4098 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
4099 | return arm_neon_quad_type (gdbarch); | |
4100 | ||
4101 | /* If the target description has register information, we are only | |
4102 | in this function so that we can override the types of | |
4103 | double-precision registers for NEON. */ | |
4104 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4105 | { | |
4106 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4107 | ||
4108 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
4109 | && TYPE_CODE (t) == TYPE_CODE_FLT | |
4110 | && gdbarch_tdep (gdbarch)->have_neon) | |
4111 | return arm_neon_double_type (gdbarch); | |
4112 | else | |
4113 | return t; | |
4114 | } | |
4115 | ||
34e8f22d | 4116 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
4117 | { |
4118 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
4119 | return builtin_type (gdbarch)->builtin_void; | |
4120 | ||
4121 | return arm_ext_type (gdbarch); | |
4122 | } | |
e4c16157 | 4123 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4124 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4125 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4126 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4127 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4128 | /* These registers are only supported on targets which supply | |
4129 | an XML description. */ | |
df4df182 | 4130 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4131 | else |
df4df182 | 4132 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4133 | } |
4134 | ||
ff6f572f DJ |
4135 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4136 | number. */ | |
4137 | ||
4138 | static int | |
d3f73121 | 4139 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4140 | { |
4141 | /* Core integer regs. */ | |
4142 | if (reg >= 0 && reg <= 15) | |
4143 | return reg; | |
4144 | ||
4145 | /* Legacy FPA encoding. These were once used in a way which | |
4146 | overlapped with VFP register numbering, so their use is | |
4147 | discouraged, but GDB doesn't support the ARM toolchain | |
4148 | which used them for VFP. */ | |
4149 | if (reg >= 16 && reg <= 23) | |
4150 | return ARM_F0_REGNUM + reg - 16; | |
4151 | ||
4152 | /* New assignments for the FPA registers. */ | |
4153 | if (reg >= 96 && reg <= 103) | |
4154 | return ARM_F0_REGNUM + reg - 96; | |
4155 | ||
4156 | /* WMMX register assignments. */ | |
4157 | if (reg >= 104 && reg <= 111) | |
4158 | return ARM_WCGR0_REGNUM + reg - 104; | |
4159 | ||
4160 | if (reg >= 112 && reg <= 127) | |
4161 | return ARM_WR0_REGNUM + reg - 112; | |
4162 | ||
4163 | if (reg >= 192 && reg <= 199) | |
4164 | return ARM_WC0_REGNUM + reg - 192; | |
4165 | ||
58d6951d DJ |
4166 | /* VFP v2 registers. A double precision value is actually |
4167 | in d1 rather than s2, but the ABI only defines numbering | |
4168 | for the single precision registers. This will "just work" | |
4169 | in GDB for little endian targets (we'll read eight bytes, | |
4170 | starting in s0 and then progressing to s1), but will be | |
4171 | reversed on big endian targets with VFP. This won't | |
4172 | be a problem for the new Neon quad registers; you're supposed | |
4173 | to use DW_OP_piece for those. */ | |
4174 | if (reg >= 64 && reg <= 95) | |
4175 | { | |
4176 | char name_buf[4]; | |
4177 | ||
8c042590 | 4178 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4179 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4180 | strlen (name_buf)); | |
4181 | } | |
4182 | ||
4183 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4184 | registers, except that it now describes d0 instead of s0. */ | |
4185 | if (reg >= 256 && reg <= 287) | |
4186 | { | |
4187 | char name_buf[4]; | |
4188 | ||
8c042590 | 4189 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4190 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4191 | strlen (name_buf)); | |
4192 | } | |
4193 | ||
ff6f572f DJ |
4194 | return -1; |
4195 | } | |
4196 | ||
26216b98 AC |
4197 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4198 | static int | |
e7faf938 | 4199 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4200 | { |
4201 | int reg = regnum; | |
e7faf938 | 4202 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4203 | |
ff6f572f DJ |
4204 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4205 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4206 | ||
4207 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4208 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4209 | ||
4210 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4211 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4212 | ||
26216b98 AC |
4213 | if (reg < NUM_GREGS) |
4214 | return SIM_ARM_R0_REGNUM + reg; | |
4215 | reg -= NUM_GREGS; | |
4216 | ||
4217 | if (reg < NUM_FREGS) | |
4218 | return SIM_ARM_FP0_REGNUM + reg; | |
4219 | reg -= NUM_FREGS; | |
4220 | ||
4221 | if (reg < NUM_SREGS) | |
4222 | return SIM_ARM_FPS_REGNUM + reg; | |
4223 | reg -= NUM_SREGS; | |
4224 | ||
edefbb7c | 4225 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4226 | } |
34e8f22d | 4227 | |
a37b3cc0 AC |
4228 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
4229 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
4230 | It is thought that this is is the floating-point register format on | |
4231 | little-endian systems. */ | |
c906108c | 4232 | |
ed9a39eb | 4233 | static void |
b508a996 | 4234 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 4235 | void *dbl, int endianess) |
c906108c | 4236 | { |
a37b3cc0 | 4237 | DOUBLEST d; |
be8626e0 MD |
4238 | |
4239 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
4240 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
4241 | else | |
4242 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
4243 | ptr, &d); | |
b508a996 | 4244 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
4245 | } |
4246 | ||
34e8f22d | 4247 | static void |
be8626e0 MD |
4248 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
4249 | int endianess) | |
c906108c | 4250 | { |
a37b3cc0 | 4251 | DOUBLEST d; |
be8626e0 | 4252 | |
b508a996 | 4253 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 4254 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
4255 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
4256 | else | |
4257 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
4258 | &d, dbl); | |
c906108c | 4259 | } |
ed9a39eb | 4260 | |
c906108c | 4261 | static int |
ed9a39eb | 4262 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
4263 | { |
4264 | if (cond == INST_AL || cond == INST_NV) | |
4265 | return 1; | |
4266 | ||
4267 | switch (cond) | |
4268 | { | |
4269 | case INST_EQ: | |
4270 | return ((status_reg & FLAG_Z) != 0); | |
4271 | case INST_NE: | |
4272 | return ((status_reg & FLAG_Z) == 0); | |
4273 | case INST_CS: | |
4274 | return ((status_reg & FLAG_C) != 0); | |
4275 | case INST_CC: | |
4276 | return ((status_reg & FLAG_C) == 0); | |
4277 | case INST_MI: | |
4278 | return ((status_reg & FLAG_N) != 0); | |
4279 | case INST_PL: | |
4280 | return ((status_reg & FLAG_N) == 0); | |
4281 | case INST_VS: | |
4282 | return ((status_reg & FLAG_V) != 0); | |
4283 | case INST_VC: | |
4284 | return ((status_reg & FLAG_V) == 0); | |
4285 | case INST_HI: | |
4286 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
4287 | case INST_LS: | |
4288 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
4289 | case INST_GE: | |
4290 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
4291 | case INST_LT: | |
4292 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
4293 | case INST_GT: | |
f8bf5763 PM |
4294 | return (((status_reg & FLAG_Z) == 0) |
4295 | && (((status_reg & FLAG_N) == 0) | |
4296 | == ((status_reg & FLAG_V) == 0))); | |
c906108c | 4297 | case INST_LE: |
f8bf5763 PM |
4298 | return (((status_reg & FLAG_Z) != 0) |
4299 | || (((status_reg & FLAG_N) == 0) | |
4300 | != ((status_reg & FLAG_V) == 0))); | |
c906108c SS |
4301 | } |
4302 | return 1; | |
4303 | } | |
4304 | ||
c906108c | 4305 | static unsigned long |
0b1b3e42 UW |
4306 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
4307 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
4308 | { |
4309 | unsigned long res, shift; | |
4310 | int rm = bits (inst, 0, 3); | |
4311 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
4312 | |
4313 | if (bit (inst, 4)) | |
c906108c SS |
4314 | { |
4315 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
4316 | shift = (rs == 15 ? pc_val + 8 |
4317 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
4318 | } |
4319 | else | |
4320 | shift = bits (inst, 7, 11); | |
c5aa993b | 4321 | |
bf9f652a | 4322 | res = (rm == ARM_PC_REGNUM |
0d39a070 | 4323 | ? (pc_val + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 4324 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
4325 | |
4326 | switch (shifttype) | |
4327 | { | |
c5aa993b | 4328 | case 0: /* LSL */ |
c906108c SS |
4329 | res = shift >= 32 ? 0 : res << shift; |
4330 | break; | |
c5aa993b JM |
4331 | |
4332 | case 1: /* LSR */ | |
c906108c SS |
4333 | res = shift >= 32 ? 0 : res >> shift; |
4334 | break; | |
4335 | ||
c5aa993b JM |
4336 | case 2: /* ASR */ |
4337 | if (shift >= 32) | |
4338 | shift = 31; | |
c906108c SS |
4339 | res = ((res & 0x80000000L) |
4340 | ? ~((~res) >> shift) : res >> shift); | |
4341 | break; | |
4342 | ||
c5aa993b | 4343 | case 3: /* ROR/RRX */ |
c906108c SS |
4344 | shift &= 31; |
4345 | if (shift == 0) | |
4346 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
4347 | else | |
c5aa993b | 4348 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
4349 | break; |
4350 | } | |
4351 | ||
4352 | return res & 0xffffffff; | |
4353 | } | |
4354 | ||
c906108c SS |
4355 | /* Return number of 1-bits in VAL. */ |
4356 | ||
4357 | static int | |
ed9a39eb | 4358 | bitcount (unsigned long val) |
c906108c SS |
4359 | { |
4360 | int nbits; | |
4361 | for (nbits = 0; val != 0; nbits++) | |
0963b4bd | 4362 | val &= val - 1; /* Delete rightmost 1-bit in val. */ |
c906108c SS |
4363 | return nbits; |
4364 | } | |
4365 | ||
177321bd DJ |
4366 | /* Return the size in bytes of the complete Thumb instruction whose |
4367 | first halfword is INST1. */ | |
4368 | ||
4369 | static int | |
4370 | thumb_insn_size (unsigned short inst1) | |
4371 | { | |
4372 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) | |
4373 | return 4; | |
4374 | else | |
4375 | return 2; | |
4376 | } | |
4377 | ||
4378 | static int | |
4379 | thumb_advance_itstate (unsigned int itstate) | |
4380 | { | |
4381 | /* Preserve IT[7:5], the first three bits of the condition. Shift | |
4382 | the upcoming condition flags left by one bit. */ | |
4383 | itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f); | |
4384 | ||
4385 | /* If we have finished the IT block, clear the state. */ | |
4386 | if ((itstate & 0x0f) == 0) | |
4387 | itstate = 0; | |
4388 | ||
4389 | return itstate; | |
4390 | } | |
4391 | ||
4392 | /* Find the next PC after the current instruction executes. In some | |
4393 | cases we can not statically determine the answer (see the IT state | |
4394 | handling in this function); in that case, a breakpoint may be | |
4395 | inserted in addition to the returned PC, which will be used to set | |
4396 | another breakpoint by our caller. */ | |
4397 | ||
ad527d2e | 4398 | static CORE_ADDR |
18819fa6 | 4399 | thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 4400 | { |
2af46ca0 | 4401 | struct gdbarch *gdbarch = get_frame_arch (frame); |
177321bd | 4402 | struct address_space *aspace = get_frame_address_space (frame); |
e17a4113 UW |
4403 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4404 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c5aa993b | 4405 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
e17a4113 | 4406 | unsigned short inst1; |
0963b4bd | 4407 | CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */ |
c906108c | 4408 | unsigned long offset; |
177321bd | 4409 | ULONGEST status, itstate; |
c906108c | 4410 | |
50e98be4 DJ |
4411 | nextpc = MAKE_THUMB_ADDR (nextpc); |
4412 | pc_val = MAKE_THUMB_ADDR (pc_val); | |
4413 | ||
e17a4113 | 4414 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); |
9d4fde75 | 4415 | |
9dca5578 DJ |
4416 | /* Thumb-2 conditional execution support. There are eight bits in |
4417 | the CPSR which describe conditional execution state. Once | |
4418 | reconstructed (they're in a funny order), the low five bits | |
4419 | describe the low bit of the condition for each instruction and | |
4420 | how many instructions remain. The high three bits describe the | |
4421 | base condition. One of the low four bits will be set if an IT | |
4422 | block is active. These bits read as zero on earlier | |
4423 | processors. */ | |
4424 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
177321bd | 4425 | itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); |
9dca5578 | 4426 | |
177321bd DJ |
4427 | /* If-Then handling. On GNU/Linux, where this routine is used, we |
4428 | use an undefined instruction as a breakpoint. Unlike BKPT, IT | |
4429 | can disable execution of the undefined instruction. So we might | |
4430 | miss the breakpoint if we set it on a skipped conditional | |
4431 | instruction. Because conditional instructions can change the | |
4432 | flags, affecting the execution of further instructions, we may | |
4433 | need to set two breakpoints. */ | |
9dca5578 | 4434 | |
177321bd DJ |
4435 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL) |
4436 | { | |
4437 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
4438 | { | |
4439 | /* An IT instruction. Because this instruction does not | |
4440 | modify the flags, we can accurately predict the next | |
4441 | executed instruction. */ | |
4442 | itstate = inst1 & 0x00ff; | |
4443 | pc += thumb_insn_size (inst1); | |
4444 | ||
4445 | while (itstate != 0 && ! condition_true (itstate >> 4, status)) | |
4446 | { | |
0963b4bd MS |
4447 | inst1 = read_memory_unsigned_integer (pc, 2, |
4448 | byte_order_for_code); | |
177321bd DJ |
4449 | pc += thumb_insn_size (inst1); |
4450 | itstate = thumb_advance_itstate (itstate); | |
4451 | } | |
4452 | ||
50e98be4 | 4453 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
4454 | } |
4455 | else if (itstate != 0) | |
4456 | { | |
4457 | /* We are in a conditional block. Check the condition. */ | |
4458 | if (! condition_true (itstate >> 4, status)) | |
4459 | { | |
4460 | /* Advance to the next executed instruction. */ | |
4461 | pc += thumb_insn_size (inst1); | |
4462 | itstate = thumb_advance_itstate (itstate); | |
4463 | ||
4464 | while (itstate != 0 && ! condition_true (itstate >> 4, status)) | |
4465 | { | |
0963b4bd MS |
4466 | inst1 = read_memory_unsigned_integer (pc, 2, |
4467 | byte_order_for_code); | |
177321bd DJ |
4468 | pc += thumb_insn_size (inst1); |
4469 | itstate = thumb_advance_itstate (itstate); | |
4470 | } | |
4471 | ||
50e98be4 | 4472 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
4473 | } |
4474 | else if ((itstate & 0x0f) == 0x08) | |
4475 | { | |
4476 | /* This is the last instruction of the conditional | |
4477 | block, and it is executed. We can handle it normally | |
4478 | because the following instruction is not conditional, | |
4479 | and we must handle it normally because it is | |
4480 | permitted to branch. Fall through. */ | |
4481 | } | |
4482 | else | |
4483 | { | |
4484 | int cond_negated; | |
4485 | ||
4486 | /* There are conditional instructions after this one. | |
4487 | If this instruction modifies the flags, then we can | |
4488 | not predict what the next executed instruction will | |
4489 | be. Fortunately, this instruction is architecturally | |
4490 | forbidden to branch; we know it will fall through. | |
4491 | Start by skipping past it. */ | |
4492 | pc += thumb_insn_size (inst1); | |
4493 | itstate = thumb_advance_itstate (itstate); | |
4494 | ||
4495 | /* Set a breakpoint on the following instruction. */ | |
4496 | gdb_assert ((itstate & 0x0f) != 0); | |
18819fa6 UW |
4497 | arm_insert_single_step_breakpoint (gdbarch, aspace, |
4498 | MAKE_THUMB_ADDR (pc)); | |
177321bd DJ |
4499 | cond_negated = (itstate >> 4) & 1; |
4500 | ||
4501 | /* Skip all following instructions with the same | |
4502 | condition. If there is a later instruction in the IT | |
4503 | block with the opposite condition, set the other | |
4504 | breakpoint there. If not, then set a breakpoint on | |
4505 | the instruction after the IT block. */ | |
4506 | do | |
4507 | { | |
0963b4bd MS |
4508 | inst1 = read_memory_unsigned_integer (pc, 2, |
4509 | byte_order_for_code); | |
177321bd DJ |
4510 | pc += thumb_insn_size (inst1); |
4511 | itstate = thumb_advance_itstate (itstate); | |
4512 | } | |
4513 | while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated); | |
4514 | ||
50e98be4 | 4515 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
4516 | } |
4517 | } | |
4518 | } | |
4519 | else if (itstate & 0x0f) | |
9dca5578 DJ |
4520 | { |
4521 | /* We are in a conditional block. Check the condition. */ | |
177321bd | 4522 | int cond = itstate >> 4; |
9dca5578 DJ |
4523 | |
4524 | if (! condition_true (cond, status)) | |
db24da6d YQ |
4525 | /* Advance to the next instruction. All the 32-bit |
4526 | instructions share a common prefix. */ | |
4527 | return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1)); | |
177321bd DJ |
4528 | |
4529 | /* Otherwise, handle the instruction normally. */ | |
9dca5578 DJ |
4530 | } |
4531 | ||
c906108c SS |
4532 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
4533 | { | |
4534 | CORE_ADDR sp; | |
4535 | ||
4536 | /* Fetch the saved PC from the stack. It's stored above | |
4537 | all of the other registers. */ | |
f0c9063c | 4538 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 4539 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
e17a4113 | 4540 | nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); |
c906108c SS |
4541 | } |
4542 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
4543 | { | |
c5aa993b | 4544 | unsigned long cond = bits (inst1, 8, 11); |
25b41d01 YQ |
4545 | if (cond == 0x0f) /* 0x0f = SWI */ |
4546 | { | |
4547 | struct gdbarch_tdep *tdep; | |
4548 | tdep = gdbarch_tdep (gdbarch); | |
4549 | ||
4550 | if (tdep->syscall_next_pc != NULL) | |
4551 | nextpc = tdep->syscall_next_pc (frame); | |
4552 | ||
4553 | } | |
4554 | else if (cond != 0x0f && condition_true (cond, status)) | |
c906108c SS |
4555 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
4556 | } | |
4557 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
4558 | { | |
4559 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
4560 | } | |
db24da6d | 4561 | else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */ |
c906108c | 4562 | { |
e17a4113 UW |
4563 | unsigned short inst2; |
4564 | inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
9dca5578 DJ |
4565 | |
4566 | /* Default to the next instruction. */ | |
4567 | nextpc = pc + 4; | |
50e98be4 | 4568 | nextpc = MAKE_THUMB_ADDR (nextpc); |
9dca5578 DJ |
4569 | |
4570 | if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) | |
4571 | { | |
4572 | /* Branches and miscellaneous control instructions. */ | |
4573 | ||
4574 | if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) | |
4575 | { | |
4576 | /* B, BL, BLX. */ | |
4577 | int j1, j2, imm1, imm2; | |
4578 | ||
4579 | imm1 = sbits (inst1, 0, 10); | |
4580 | imm2 = bits (inst2, 0, 10); | |
4581 | j1 = bit (inst2, 13); | |
4582 | j2 = bit (inst2, 11); | |
4583 | ||
4584 | offset = ((imm1 << 12) + (imm2 << 1)); | |
4585 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
4586 | ||
4587 | nextpc = pc_val + offset; | |
4588 | /* For BLX make sure to clear the low bits. */ | |
4589 | if (bit (inst2, 12) == 0) | |
4590 | nextpc = nextpc & 0xfffffffc; | |
4591 | } | |
4592 | else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) | |
4593 | { | |
4594 | /* SUBS PC, LR, #imm8. */ | |
4595 | nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM); | |
4596 | nextpc -= inst2 & 0x00ff; | |
4597 | } | |
4069ebbe | 4598 | else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) |
9dca5578 DJ |
4599 | { |
4600 | /* Conditional branch. */ | |
4601 | if (condition_true (bits (inst1, 6, 9), status)) | |
4602 | { | |
4603 | int sign, j1, j2, imm1, imm2; | |
4604 | ||
4605 | sign = sbits (inst1, 10, 10); | |
4606 | imm1 = bits (inst1, 0, 5); | |
4607 | imm2 = bits (inst2, 0, 10); | |
4608 | j1 = bit (inst2, 13); | |
4609 | j2 = bit (inst2, 11); | |
4610 | ||
4611 | offset = (sign << 20) + (j2 << 19) + (j1 << 18); | |
4612 | offset += (imm1 << 12) + (imm2 << 1); | |
4613 | ||
4614 | nextpc = pc_val + offset; | |
4615 | } | |
4616 | } | |
4617 | } | |
4618 | else if ((inst1 & 0xfe50) == 0xe810) | |
4619 | { | |
4620 | /* Load multiple or RFE. */ | |
4621 | int rn, offset, load_pc = 1; | |
4622 | ||
4623 | rn = bits (inst1, 0, 3); | |
4624 | if (bit (inst1, 7) && !bit (inst1, 8)) | |
4625 | { | |
4626 | /* LDMIA or POP */ | |
4627 | if (!bit (inst2, 15)) | |
4628 | load_pc = 0; | |
4629 | offset = bitcount (inst2) * 4 - 4; | |
4630 | } | |
4631 | else if (!bit (inst1, 7) && bit (inst1, 8)) | |
4632 | { | |
4633 | /* LDMDB */ | |
4634 | if (!bit (inst2, 15)) | |
4635 | load_pc = 0; | |
4636 | offset = -4; | |
4637 | } | |
4638 | else if (bit (inst1, 7) && bit (inst1, 8)) | |
4639 | { | |
4640 | /* RFEIA */ | |
4641 | offset = 0; | |
4642 | } | |
4643 | else if (!bit (inst1, 7) && !bit (inst1, 8)) | |
4644 | { | |
4645 | /* RFEDB */ | |
4646 | offset = -8; | |
4647 | } | |
4648 | else | |
4649 | load_pc = 0; | |
4650 | ||
4651 | if (load_pc) | |
4652 | { | |
4653 | CORE_ADDR addr = get_frame_register_unsigned (frame, rn); | |
4654 | nextpc = get_frame_memory_unsigned (frame, addr + offset, 4); | |
4655 | } | |
4656 | } | |
4657 | else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) | |
4658 | { | |
4659 | /* MOV PC or MOVS PC. */ | |
4660 | nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); | |
50e98be4 | 4661 | nextpc = MAKE_THUMB_ADDR (nextpc); |
9dca5578 DJ |
4662 | } |
4663 | else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) | |
4664 | { | |
4665 | /* LDR PC. */ | |
4666 | CORE_ADDR base; | |
4667 | int rn, load_pc = 1; | |
4668 | ||
4669 | rn = bits (inst1, 0, 3); | |
4670 | base = get_frame_register_unsigned (frame, rn); | |
bf9f652a | 4671 | if (rn == ARM_PC_REGNUM) |
9dca5578 DJ |
4672 | { |
4673 | base = (base + 4) & ~(CORE_ADDR) 0x3; | |
4674 | if (bit (inst1, 7)) | |
4675 | base += bits (inst2, 0, 11); | |
4676 | else | |
4677 | base -= bits (inst2, 0, 11); | |
4678 | } | |
4679 | else if (bit (inst1, 7)) | |
4680 | base += bits (inst2, 0, 11); | |
4681 | else if (bit (inst2, 11)) | |
4682 | { | |
4683 | if (bit (inst2, 10)) | |
4684 | { | |
4685 | if (bit (inst2, 9)) | |
4686 | base += bits (inst2, 0, 7); | |
4687 | else | |
4688 | base -= bits (inst2, 0, 7); | |
4689 | } | |
4690 | } | |
4691 | else if ((inst2 & 0x0fc0) == 0x0000) | |
4692 | { | |
4693 | int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3); | |
4694 | base += get_frame_register_unsigned (frame, rm) << shift; | |
4695 | } | |
4696 | else | |
4697 | /* Reserved. */ | |
4698 | load_pc = 0; | |
4699 | ||
4700 | if (load_pc) | |
4701 | nextpc = get_frame_memory_unsigned (frame, base, 4); | |
4702 | } | |
4703 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) | |
4704 | { | |
4705 | /* TBB. */ | |
d476da0e RE |
4706 | CORE_ADDR tbl_reg, table, offset, length; |
4707 | ||
4708 | tbl_reg = bits (inst1, 0, 3); | |
4709 | if (tbl_reg == 0x0f) | |
4710 | table = pc + 4; /* Regcache copy of PC isn't right yet. */ | |
4711 | else | |
4712 | table = get_frame_register_unsigned (frame, tbl_reg); | |
9dca5578 | 4713 | |
9dca5578 DJ |
4714 | offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); |
4715 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 1); | |
4716 | nextpc = pc_val + length; | |
4717 | } | |
d476da0e | 4718 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) |
9dca5578 DJ |
4719 | { |
4720 | /* TBH. */ | |
d476da0e RE |
4721 | CORE_ADDR tbl_reg, table, offset, length; |
4722 | ||
4723 | tbl_reg = bits (inst1, 0, 3); | |
4724 | if (tbl_reg == 0x0f) | |
4725 | table = pc + 4; /* Regcache copy of PC isn't right yet. */ | |
4726 | else | |
4727 | table = get_frame_register_unsigned (frame, tbl_reg); | |
9dca5578 | 4728 | |
9dca5578 DJ |
4729 | offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3)); |
4730 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 2); | |
4731 | nextpc = pc_val + length; | |
4732 | } | |
c906108c | 4733 | } |
aa17d93e | 4734 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
4735 | { |
4736 | if (bits (inst1, 3, 6) == 0x0f) | |
6ca1b147 | 4737 | nextpc = UNMAKE_THUMB_ADDR (pc_val); |
9498281f | 4738 | else |
0b1b3e42 | 4739 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 4740 | } |
ad8b5167 UW |
4741 | else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */ |
4742 | { | |
4743 | if (bits (inst1, 3, 6) == 0x0f) | |
4744 | nextpc = pc_val; | |
4745 | else | |
4746 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); | |
4747 | ||
4748 | nextpc = MAKE_THUMB_ADDR (nextpc); | |
4749 | } | |
9dca5578 DJ |
4750 | else if ((inst1 & 0xf500) == 0xb100) |
4751 | { | |
4752 | /* CBNZ or CBZ. */ | |
4753 | int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1); | |
4754 | ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2)); | |
4755 | ||
4756 | if (bit (inst1, 11) && reg != 0) | |
4757 | nextpc = pc_val + imm; | |
4758 | else if (!bit (inst1, 11) && reg == 0) | |
4759 | nextpc = pc_val + imm; | |
4760 | } | |
c906108c SS |
4761 | return nextpc; |
4762 | } | |
4763 | ||
50e98be4 | 4764 | /* Get the raw next address. PC is the current program counter, in |
18819fa6 | 4765 | FRAME, which is assumed to be executing in ARM mode. |
50e98be4 DJ |
4766 | |
4767 | The value returned has the execution state of the next instruction | |
4768 | encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is | |
4769 | in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory | |
0963b4bd MS |
4770 | address. */ |
4771 | ||
50e98be4 | 4772 | static CORE_ADDR |
18819fa6 | 4773 | arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 4774 | { |
2af46ca0 | 4775 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
4776 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4777 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c906108c SS |
4778 | unsigned long pc_val; |
4779 | unsigned long this_instr; | |
4780 | unsigned long status; | |
4781 | CORE_ADDR nextpc; | |
4782 | ||
c906108c | 4783 | pc_val = (unsigned long) pc; |
e17a4113 | 4784 | this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); |
9d4fde75 | 4785 | |
0b1b3e42 | 4786 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 4787 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 4788 | |
daddc3c1 DJ |
4789 | if (bits (this_instr, 28, 31) == INST_NV) |
4790 | switch (bits (this_instr, 24, 27)) | |
4791 | { | |
4792 | case 0xa: | |
4793 | case 0xb: | |
4794 | { | |
4795 | /* Branch with Link and change to Thumb. */ | |
4796 | nextpc = BranchDest (pc, this_instr); | |
4797 | nextpc |= bit (this_instr, 24) << 1; | |
50e98be4 | 4798 | nextpc = MAKE_THUMB_ADDR (nextpc); |
daddc3c1 DJ |
4799 | break; |
4800 | } | |
4801 | case 0xc: | |
4802 | case 0xd: | |
4803 | case 0xe: | |
4804 | /* Coprocessor register transfer. */ | |
4805 | if (bits (this_instr, 12, 15) == 15) | |
4806 | error (_("Invalid update to pc in instruction")); | |
4807 | break; | |
4808 | } | |
4809 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
4810 | { |
4811 | switch (bits (this_instr, 24, 27)) | |
4812 | { | |
c5aa993b | 4813 | case 0x0: |
94c30b78 | 4814 | case 0x1: /* data processing */ |
c5aa993b JM |
4815 | case 0x2: |
4816 | case 0x3: | |
c906108c SS |
4817 | { |
4818 | unsigned long operand1, operand2, result = 0; | |
4819 | unsigned long rn; | |
4820 | int c; | |
c5aa993b | 4821 | |
c906108c SS |
4822 | if (bits (this_instr, 12, 15) != 15) |
4823 | break; | |
4824 | ||
4825 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 4826 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 4827 | error (_("Invalid update to pc in instruction")); |
c906108c | 4828 | |
9498281f | 4829 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
4830 | if (bits (this_instr, 4, 27) == 0x12fff1 |
4831 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
4832 | { |
4833 | rn = bits (this_instr, 0, 3); | |
bf9f652a YQ |
4834 | nextpc = ((rn == ARM_PC_REGNUM) |
4835 | ? (pc_val + 8) | |
4836 | : get_frame_register_unsigned (frame, rn)); | |
4837 | ||
9498281f DJ |
4838 | return nextpc; |
4839 | } | |
4840 | ||
0963b4bd | 4841 | /* Multiply into PC. */ |
c906108c SS |
4842 | c = (status & FLAG_C) ? 1 : 0; |
4843 | rn = bits (this_instr, 16, 19); | |
bf9f652a YQ |
4844 | operand1 = ((rn == ARM_PC_REGNUM) |
4845 | ? (pc_val + 8) | |
4846 | : get_frame_register_unsigned (frame, rn)); | |
c5aa993b | 4847 | |
c906108c SS |
4848 | if (bit (this_instr, 25)) |
4849 | { | |
4850 | unsigned long immval = bits (this_instr, 0, 7); | |
4851 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
4852 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
4853 | & 0xffffffff; | |
c906108c | 4854 | } |
0963b4bd MS |
4855 | else /* operand 2 is a shifted register. */ |
4856 | operand2 = shifted_reg_val (frame, this_instr, c, | |
4857 | pc_val, status); | |
c5aa993b | 4858 | |
c906108c SS |
4859 | switch (bits (this_instr, 21, 24)) |
4860 | { | |
c5aa993b | 4861 | case 0x0: /*and */ |
c906108c SS |
4862 | result = operand1 & operand2; |
4863 | break; | |
4864 | ||
c5aa993b | 4865 | case 0x1: /*eor */ |
c906108c SS |
4866 | result = operand1 ^ operand2; |
4867 | break; | |
4868 | ||
c5aa993b | 4869 | case 0x2: /*sub */ |
c906108c SS |
4870 | result = operand1 - operand2; |
4871 | break; | |
4872 | ||
c5aa993b | 4873 | case 0x3: /*rsb */ |
c906108c SS |
4874 | result = operand2 - operand1; |
4875 | break; | |
4876 | ||
c5aa993b | 4877 | case 0x4: /*add */ |
c906108c SS |
4878 | result = operand1 + operand2; |
4879 | break; | |
4880 | ||
c5aa993b | 4881 | case 0x5: /*adc */ |
c906108c SS |
4882 | result = operand1 + operand2 + c; |
4883 | break; | |
4884 | ||
c5aa993b | 4885 | case 0x6: /*sbc */ |
c906108c SS |
4886 | result = operand1 - operand2 + c; |
4887 | break; | |
4888 | ||
c5aa993b | 4889 | case 0x7: /*rsc */ |
c906108c SS |
4890 | result = operand2 - operand1 + c; |
4891 | break; | |
4892 | ||
c5aa993b JM |
4893 | case 0x8: |
4894 | case 0x9: | |
4895 | case 0xa: | |
4896 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
4897 | result = (unsigned long) nextpc; |
4898 | break; | |
4899 | ||
c5aa993b | 4900 | case 0xc: /*orr */ |
c906108c SS |
4901 | result = operand1 | operand2; |
4902 | break; | |
4903 | ||
c5aa993b | 4904 | case 0xd: /*mov */ |
c906108c SS |
4905 | /* Always step into a function. */ |
4906 | result = operand2; | |
c5aa993b | 4907 | break; |
c906108c | 4908 | |
c5aa993b | 4909 | case 0xe: /*bic */ |
c906108c SS |
4910 | result = operand1 & ~operand2; |
4911 | break; | |
4912 | ||
c5aa993b | 4913 | case 0xf: /*mvn */ |
c906108c SS |
4914 | result = ~operand2; |
4915 | break; | |
4916 | } | |
c906108c | 4917 | |
50e98be4 DJ |
4918 | /* In 26-bit APCS the bottom two bits of the result are |
4919 | ignored, and we always end up in ARM state. */ | |
4920 | if (!arm_apcs_32) | |
4921 | nextpc = arm_addr_bits_remove (gdbarch, result); | |
4922 | else | |
4923 | nextpc = result; | |
4924 | ||
c906108c SS |
4925 | break; |
4926 | } | |
c5aa993b JM |
4927 | |
4928 | case 0x4: | |
4929 | case 0x5: /* data transfer */ | |
4930 | case 0x6: | |
4931 | case 0x7: | |
c906108c SS |
4932 | if (bit (this_instr, 20)) |
4933 | { | |
4934 | /* load */ | |
4935 | if (bits (this_instr, 12, 15) == 15) | |
4936 | { | |
4937 | /* rd == pc */ | |
c5aa993b | 4938 | unsigned long rn; |
c906108c | 4939 | unsigned long base; |
c5aa993b | 4940 | |
c906108c | 4941 | if (bit (this_instr, 22)) |
edefbb7c | 4942 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
4943 | |
4944 | /* byte write to PC */ | |
4945 | rn = bits (this_instr, 16, 19); | |
bf9f652a YQ |
4946 | base = ((rn == ARM_PC_REGNUM) |
4947 | ? (pc_val + 8) | |
4948 | : get_frame_register_unsigned (frame, rn)); | |
4949 | ||
c906108c SS |
4950 | if (bit (this_instr, 24)) |
4951 | { | |
4952 | /* pre-indexed */ | |
4953 | int c = (status & FLAG_C) ? 1 : 0; | |
4954 | unsigned long offset = | |
c5aa993b | 4955 | (bit (this_instr, 25) |
0b1b3e42 | 4956 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 4957 | : bits (this_instr, 0, 11)); |
c906108c SS |
4958 | |
4959 | if (bit (this_instr, 23)) | |
4960 | base += offset; | |
4961 | else | |
4962 | base -= offset; | |
4963 | } | |
51370a33 YQ |
4964 | nextpc = |
4965 | (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base, | |
4966 | 4, byte_order); | |
c906108c SS |
4967 | } |
4968 | } | |
4969 | break; | |
c5aa993b JM |
4970 | |
4971 | case 0x8: | |
4972 | case 0x9: /* block transfer */ | |
c906108c SS |
4973 | if (bit (this_instr, 20)) |
4974 | { | |
4975 | /* LDM */ | |
4976 | if (bit (this_instr, 15)) | |
4977 | { | |
4978 | /* loading pc */ | |
4979 | int offset = 0; | |
51370a33 YQ |
4980 | unsigned long rn_val |
4981 | = get_frame_register_unsigned (frame, | |
4982 | bits (this_instr, 16, 19)); | |
c906108c SS |
4983 | |
4984 | if (bit (this_instr, 23)) | |
4985 | { | |
4986 | /* up */ | |
4987 | unsigned long reglist = bits (this_instr, 0, 14); | |
4988 | offset = bitcount (reglist) * 4; | |
c5aa993b | 4989 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
4990 | offset += 4; |
4991 | } | |
4992 | else if (bit (this_instr, 24)) | |
4993 | offset = -4; | |
c5aa993b | 4994 | |
51370a33 YQ |
4995 | nextpc = |
4996 | (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) | |
4997 | (rn_val + offset), | |
4998 | 4, byte_order); | |
c906108c SS |
4999 | } |
5000 | } | |
5001 | break; | |
c5aa993b JM |
5002 | |
5003 | case 0xb: /* branch & link */ | |
5004 | case 0xa: /* branch */ | |
c906108c SS |
5005 | { |
5006 | nextpc = BranchDest (pc, this_instr); | |
c906108c SS |
5007 | break; |
5008 | } | |
c5aa993b JM |
5009 | |
5010 | case 0xc: | |
5011 | case 0xd: | |
5012 | case 0xe: /* coproc ops */ | |
25b41d01 | 5013 | break; |
c5aa993b | 5014 | case 0xf: /* SWI */ |
25b41d01 YQ |
5015 | { |
5016 | struct gdbarch_tdep *tdep; | |
5017 | tdep = gdbarch_tdep (gdbarch); | |
5018 | ||
5019 | if (tdep->syscall_next_pc != NULL) | |
5020 | nextpc = tdep->syscall_next_pc (frame); | |
5021 | ||
5022 | } | |
c906108c SS |
5023 | break; |
5024 | ||
5025 | default: | |
edefbb7c | 5026 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
5027 | return (pc); |
5028 | } | |
5029 | } | |
5030 | ||
5031 | return nextpc; | |
5032 | } | |
5033 | ||
18819fa6 UW |
5034 | /* Determine next PC after current instruction executes. Will call either |
5035 | arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite | |
5036 | loop is detected. */ | |
5037 | ||
50e98be4 DJ |
5038 | CORE_ADDR |
5039 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
5040 | { | |
18819fa6 UW |
5041 | CORE_ADDR nextpc; |
5042 | ||
5043 | if (arm_frame_is_thumb (frame)) | |
2b59118e | 5044 | nextpc = thumb_get_next_pc_raw (frame, pc); |
18819fa6 | 5045 | else |
2b59118e | 5046 | nextpc = arm_get_next_pc_raw (frame, pc); |
18819fa6 | 5047 | |
50e98be4 DJ |
5048 | return nextpc; |
5049 | } | |
5050 | ||
18819fa6 UW |
5051 | /* Like insert_single_step_breakpoint, but make sure we use a breakpoint |
5052 | of the appropriate mode (as encoded in the PC value), even if this | |
5053 | differs from what would be expected according to the symbol tables. */ | |
5054 | ||
5055 | void | |
5056 | arm_insert_single_step_breakpoint (struct gdbarch *gdbarch, | |
5057 | struct address_space *aspace, | |
5058 | CORE_ADDR pc) | |
5059 | { | |
5060 | struct cleanup *old_chain | |
5061 | = make_cleanup_restore_integer (&arm_override_mode); | |
5062 | ||
5063 | arm_override_mode = IS_THUMB_ADDR (pc); | |
5064 | pc = gdbarch_addr_bits_remove (gdbarch, pc); | |
5065 | ||
5066 | insert_single_step_breakpoint (gdbarch, aspace, pc); | |
5067 | ||
5068 | do_cleanups (old_chain); | |
5069 | } | |
5070 | ||
35f73cfc UW |
5071 | /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D} |
5072 | instruction and ending with a STREX{,B,H,D} instruction. If such a sequence | |
5073 | is found, attempt to step through it. A breakpoint is placed at the end of | |
5074 | the sequence. */ | |
5075 | ||
5076 | static int | |
5077 | thumb_deal_with_atomic_sequence_raw (struct frame_info *frame) | |
5078 | { | |
5079 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
5080 | struct address_space *aspace = get_frame_address_space (frame); | |
5081 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
5082 | CORE_ADDR pc = get_frame_pc (frame); | |
5083 | CORE_ADDR breaks[2] = {-1, -1}; | |
5084 | CORE_ADDR loc = pc; | |
5085 | unsigned short insn1, insn2; | |
5086 | int insn_count; | |
5087 | int index; | |
5088 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
5089 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
5090 | ULONGEST status, itstate; | |
5091 | ||
5092 | /* We currently do not support atomic sequences within an IT block. */ | |
5093 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
5094 | itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); | |
5095 | if (itstate & 0x0f) | |
5096 | return 0; | |
5097 | ||
5098 | /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */ | |
5099 | insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); | |
5100 | loc += 2; | |
5101 | if (thumb_insn_size (insn1) != 4) | |
5102 | return 0; | |
5103 | ||
5104 | insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); | |
5105 | loc += 2; | |
5106 | if (!((insn1 & 0xfff0) == 0xe850 | |
5107 | || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040))) | |
5108 | return 0; | |
5109 | ||
5110 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
5111 | instructions. */ | |
5112 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
5113 | { | |
5114 | insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); | |
5115 | loc += 2; | |
5116 | ||
5117 | if (thumb_insn_size (insn1) != 4) | |
5118 | { | |
5119 | /* Assume that there is at most one conditional branch in the | |
5120 | atomic sequence. If a conditional branch is found, put a | |
5121 | breakpoint in its destination address. */ | |
5122 | if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f) | |
5123 | { | |
5124 | if (last_breakpoint > 0) | |
5125 | return 0; /* More than one conditional branch found, | |
5126 | fallback to the standard code. */ | |
5127 | ||
5128 | breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1); | |
5129 | last_breakpoint++; | |
5130 | } | |
5131 | ||
5132 | /* We do not support atomic sequences that use any *other* | |
5133 | instructions but conditional branches to change the PC. | |
5134 | Fall back to standard code to avoid losing control of | |
5135 | execution. */ | |
5136 | else if (thumb_instruction_changes_pc (insn1)) | |
5137 | return 0; | |
5138 | } | |
5139 | else | |
5140 | { | |
5141 | insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); | |
5142 | loc += 2; | |
5143 | ||
5144 | /* Assume that there is at most one conditional branch in the | |
5145 | atomic sequence. If a conditional branch is found, put a | |
5146 | breakpoint in its destination address. */ | |
5147 | if ((insn1 & 0xf800) == 0xf000 | |
5148 | && (insn2 & 0xd000) == 0x8000 | |
5149 | && (insn1 & 0x0380) != 0x0380) | |
5150 | { | |
5151 | int sign, j1, j2, imm1, imm2; | |
5152 | unsigned int offset; | |
5153 | ||
5154 | sign = sbits (insn1, 10, 10); | |
5155 | imm1 = bits (insn1, 0, 5); | |
5156 | imm2 = bits (insn2, 0, 10); | |
5157 | j1 = bit (insn2, 13); | |
5158 | j2 = bit (insn2, 11); | |
5159 | ||
5160 | offset = (sign << 20) + (j2 << 19) + (j1 << 18); | |
5161 | offset += (imm1 << 12) + (imm2 << 1); | |
5162 | ||
5163 | if (last_breakpoint > 0) | |
5164 | return 0; /* More than one conditional branch found, | |
5165 | fallback to the standard code. */ | |
5166 | ||
5167 | breaks[1] = loc + offset; | |
5168 | last_breakpoint++; | |
5169 | } | |
5170 | ||
5171 | /* We do not support atomic sequences that use any *other* | |
5172 | instructions but conditional branches to change the PC. | |
5173 | Fall back to standard code to avoid losing control of | |
5174 | execution. */ | |
5175 | else if (thumb2_instruction_changes_pc (insn1, insn2)) | |
5176 | return 0; | |
5177 | ||
5178 | /* If we find a strex{,b,h,d}, we're done. */ | |
5179 | if ((insn1 & 0xfff0) == 0xe840 | |
5180 | || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040)) | |
5181 | break; | |
5182 | } | |
5183 | } | |
5184 | ||
5185 | /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ | |
5186 | if (insn_count == atomic_sequence_length) | |
5187 | return 0; | |
5188 | ||
5189 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
5190 | breaks[0] = loc; | |
5191 | ||
5192 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
5193 | placed (branch instruction's destination) anywhere in sequence. */ | |
5194 | if (last_breakpoint | |
5195 | && (breaks[1] == breaks[0] | |
5196 | || (breaks[1] >= pc && breaks[1] < loc))) | |
5197 | last_breakpoint = 0; | |
5198 | ||
5199 | /* Effectively inserts the breakpoints. */ | |
5200 | for (index = 0; index <= last_breakpoint; index++) | |
5201 | arm_insert_single_step_breakpoint (gdbarch, aspace, | |
5202 | MAKE_THUMB_ADDR (breaks[index])); | |
5203 | ||
5204 | return 1; | |
5205 | } | |
5206 | ||
5207 | static int | |
5208 | arm_deal_with_atomic_sequence_raw (struct frame_info *frame) | |
5209 | { | |
5210 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
5211 | struct address_space *aspace = get_frame_address_space (frame); | |
5212 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
5213 | CORE_ADDR pc = get_frame_pc (frame); | |
5214 | CORE_ADDR breaks[2] = {-1, -1}; | |
5215 | CORE_ADDR loc = pc; | |
5216 | unsigned int insn; | |
5217 | int insn_count; | |
5218 | int index; | |
5219 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
5220 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
5221 | ||
5222 | /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. | |
5223 | Note that we do not currently support conditionally executed atomic | |
5224 | instructions. */ | |
5225 | insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code); | |
5226 | loc += 4; | |
5227 | if ((insn & 0xff9000f0) != 0xe1900090) | |
5228 | return 0; | |
5229 | ||
5230 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
5231 | instructions. */ | |
5232 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
5233 | { | |
5234 | insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code); | |
5235 | loc += 4; | |
5236 | ||
5237 | /* Assume that there is at most one conditional branch in the atomic | |
5238 | sequence. If a conditional branch is found, put a breakpoint in | |
5239 | its destination address. */ | |
5240 | if (bits (insn, 24, 27) == 0xa) | |
5241 | { | |
5242 | if (last_breakpoint > 0) | |
5243 | return 0; /* More than one conditional branch found, fallback | |
5244 | to the standard single-step code. */ | |
5245 | ||
5246 | breaks[1] = BranchDest (loc - 4, insn); | |
5247 | last_breakpoint++; | |
5248 | } | |
5249 | ||
5250 | /* We do not support atomic sequences that use any *other* instructions | |
5251 | but conditional branches to change the PC. Fall back to standard | |
5252 | code to avoid losing control of execution. */ | |
5253 | else if (arm_instruction_changes_pc (insn)) | |
5254 | return 0; | |
5255 | ||
5256 | /* If we find a strex{,b,h,d}, we're done. */ | |
5257 | if ((insn & 0xff9000f0) == 0xe1800090) | |
5258 | break; | |
5259 | } | |
5260 | ||
5261 | /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ | |
5262 | if (insn_count == atomic_sequence_length) | |
5263 | return 0; | |
5264 | ||
5265 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
5266 | breaks[0] = loc; | |
5267 | ||
5268 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
5269 | placed (branch instruction's destination) anywhere in sequence. */ | |
5270 | if (last_breakpoint | |
5271 | && (breaks[1] == breaks[0] | |
5272 | || (breaks[1] >= pc && breaks[1] < loc))) | |
5273 | last_breakpoint = 0; | |
5274 | ||
5275 | /* Effectively inserts the breakpoints. */ | |
5276 | for (index = 0; index <= last_breakpoint; index++) | |
5277 | arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
5278 | ||
5279 | return 1; | |
5280 | } | |
5281 | ||
5282 | int | |
5283 | arm_deal_with_atomic_sequence (struct frame_info *frame) | |
5284 | { | |
5285 | if (arm_frame_is_thumb (frame)) | |
5286 | return thumb_deal_with_atomic_sequence_raw (frame); | |
5287 | else | |
5288 | return arm_deal_with_atomic_sequence_raw (frame); | |
5289 | } | |
5290 | ||
9512d7fd FN |
5291 | /* single_step() is called just before we want to resume the inferior, |
5292 | if we want to single-step it but there is no hardware or kernel | |
5293 | single-step support. We find the target of the coming instruction | |
e0cd558a | 5294 | and breakpoint it. */ |
9512d7fd | 5295 | |
190dce09 | 5296 | int |
0b1b3e42 | 5297 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 5298 | { |
a6d9a66e | 5299 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 5300 | struct address_space *aspace = get_frame_address_space (frame); |
35f73cfc UW |
5301 | CORE_ADDR next_pc; |
5302 | ||
5303 | if (arm_deal_with_atomic_sequence (frame)) | |
5304 | return 1; | |
18819fa6 | 5305 | |
35f73cfc | 5306 | next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
18819fa6 | 5307 | arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b UW |
5308 | |
5309 | return 1; | |
9512d7fd | 5310 | } |
9512d7fd | 5311 | |
f9d67f43 DJ |
5312 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
5313 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
5314 | NULL if an error occurs. BUF is freed. */ | |
5315 | ||
5316 | static gdb_byte * | |
5317 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
5318 | int old_len, int new_len) | |
5319 | { | |
22e048c9 | 5320 | gdb_byte *new_buf; |
f9d67f43 DJ |
5321 | int bytes_to_read = new_len - old_len; |
5322 | ||
5323 | new_buf = xmalloc (new_len); | |
5324 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
5325 | xfree (buf); | |
5326 | if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0) | |
5327 | { | |
5328 | xfree (new_buf); | |
5329 | return NULL; | |
5330 | } | |
5331 | return new_buf; | |
5332 | } | |
5333 | ||
5334 | /* An IT block is at most the 2-byte IT instruction followed by | |
5335 | four 4-byte instructions. The furthest back we must search to | |
5336 | find an IT block that affects the current instruction is thus | |
5337 | 2 + 3 * 4 == 14 bytes. */ | |
5338 | #define MAX_IT_BLOCK_PREFIX 14 | |
5339 | ||
5340 | /* Use a quick scan if there are more than this many bytes of | |
5341 | code. */ | |
5342 | #define IT_SCAN_THRESHOLD 32 | |
5343 | ||
5344 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. | |
5345 | A breakpoint in an IT block may not be hit, depending on the | |
5346 | condition flags. */ | |
5347 | static CORE_ADDR | |
5348 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
5349 | { | |
5350 | gdb_byte *buf; | |
5351 | char map_type; | |
5352 | CORE_ADDR boundary, func_start; | |
22e048c9 | 5353 | int buf_len; |
f9d67f43 DJ |
5354 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); |
5355 | int i, any, last_it, last_it_count; | |
5356 | ||
5357 | /* If we are using BKPT breakpoints, none of this is necessary. */ | |
5358 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) | |
5359 | return bpaddr; | |
5360 | ||
5361 | /* ARM mode does not have this problem. */ | |
9779414d | 5362 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) |
f9d67f43 DJ |
5363 | return bpaddr; |
5364 | ||
5365 | /* We are setting a breakpoint in Thumb code that could potentially | |
5366 | contain an IT block. The first step is to find how much Thumb | |
5367 | code there is; we do not need to read outside of known Thumb | |
5368 | sequences. */ | |
5369 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
5370 | if (map_type == 0) | |
5371 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
5372 | return bpaddr; | |
5373 | ||
5374 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); | |
5375 | ||
5376 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) | |
5377 | && func_start > boundary) | |
5378 | boundary = func_start; | |
5379 | ||
5380 | /* Search for a candidate IT instruction. We have to do some fancy | |
5381 | footwork to distinguish a real IT instruction from the second | |
5382 | half of a 32-bit instruction, but there is no need for that if | |
5383 | there's no candidate. */ | |
5384 | buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX); | |
5385 | if (buf_len == 0) | |
5386 | /* No room for an IT instruction. */ | |
5387 | return bpaddr; | |
5388 | ||
5389 | buf = xmalloc (buf_len); | |
5390 | if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0) | |
5391 | return bpaddr; | |
5392 | any = 0; | |
5393 | for (i = 0; i < buf_len; i += 2) | |
5394 | { | |
5395 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5396 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
5397 | { | |
5398 | any = 1; | |
5399 | break; | |
5400 | } | |
5401 | } | |
5402 | if (any == 0) | |
5403 | { | |
5404 | xfree (buf); | |
5405 | return bpaddr; | |
5406 | } | |
5407 | ||
5408 | /* OK, the code bytes before this instruction contain at least one | |
5409 | halfword which resembles an IT instruction. We know that it's | |
5410 | Thumb code, but there are still two possibilities. Either the | |
5411 | halfword really is an IT instruction, or it is the second half of | |
5412 | a 32-bit Thumb instruction. The only way we can tell is to | |
5413 | scan forwards from a known instruction boundary. */ | |
5414 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
5415 | { | |
5416 | int definite; | |
5417 | ||
5418 | /* There's a lot of code before this instruction. Start with an | |
5419 | optimistic search; it's easy to recognize halfwords that can | |
5420 | not be the start of a 32-bit instruction, and use that to | |
5421 | lock on to the instruction boundaries. */ | |
5422 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
5423 | if (buf == NULL) | |
5424 | return bpaddr; | |
5425 | buf_len = IT_SCAN_THRESHOLD; | |
5426 | ||
5427 | definite = 0; | |
5428 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
5429 | { | |
5430 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5431 | if (thumb_insn_size (inst1) == 2) | |
5432 | { | |
5433 | definite = 1; | |
5434 | break; | |
5435 | } | |
5436 | } | |
5437 | ||
5438 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
5439 | are sure that we know the instruction boundaries, and it is far | |
5440 | enough from BPADDR that we could not miss an IT instruction | |
5441 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
5442 | known boundary. */ | |
5443 | if (! definite) | |
5444 | { | |
0963b4bd MS |
5445 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
5446 | bpaddr - boundary); | |
f9d67f43 DJ |
5447 | if (buf == NULL) |
5448 | return bpaddr; | |
5449 | buf_len = bpaddr - boundary; | |
5450 | i = 0; | |
5451 | } | |
5452 | } | |
5453 | else | |
5454 | { | |
5455 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
5456 | if (buf == NULL) | |
5457 | return bpaddr; | |
5458 | buf_len = bpaddr - boundary; | |
5459 | i = 0; | |
5460 | } | |
5461 | ||
5462 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
5463 | last_it = -1; | |
5464 | last_it_count = 0; | |
5465 | while (i < buf_len) | |
5466 | { | |
5467 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5468 | last_it_count--; | |
5469 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
5470 | { | |
5471 | last_it = i; | |
5472 | if (inst1 & 0x0001) | |
5473 | last_it_count = 4; | |
5474 | else if (inst1 & 0x0002) | |
5475 | last_it_count = 3; | |
5476 | else if (inst1 & 0x0004) | |
5477 | last_it_count = 2; | |
5478 | else | |
5479 | last_it_count = 1; | |
5480 | } | |
5481 | i += thumb_insn_size (inst1); | |
5482 | } | |
5483 | ||
5484 | xfree (buf); | |
5485 | ||
5486 | if (last_it == -1) | |
5487 | /* There wasn't really an IT instruction after all. */ | |
5488 | return bpaddr; | |
5489 | ||
5490 | if (last_it_count < 1) | |
5491 | /* It was too far away. */ | |
5492 | return bpaddr; | |
5493 | ||
5494 | /* This really is a trouble spot. Move the breakpoint to the IT | |
5495 | instruction. */ | |
5496 | return bpaddr - buf_len + last_it; | |
5497 | } | |
5498 | ||
cca44b1b | 5499 | /* ARM displaced stepping support. |
c906108c | 5500 | |
cca44b1b | 5501 | Generally ARM displaced stepping works as follows: |
c906108c | 5502 | |
cca44b1b JB |
5503 | 1. When an instruction is to be single-stepped, it is first decoded by |
5504 | arm_process_displaced_insn (called from arm_displaced_step_copy_insn). | |
5505 | Depending on the type of instruction, it is then copied to a scratch | |
5506 | location, possibly in a modified form. The copy_* set of functions | |
0963b4bd | 5507 | performs such modification, as necessary. A breakpoint is placed after |
cca44b1b JB |
5508 | the modified instruction in the scratch space to return control to GDB. |
5509 | Note in particular that instructions which modify the PC will no longer | |
5510 | do so after modification. | |
c5aa993b | 5511 | |
cca44b1b JB |
5512 | 2. The instruction is single-stepped, by setting the PC to the scratch |
5513 | location address, and resuming. Control returns to GDB when the | |
5514 | breakpoint is hit. | |
c5aa993b | 5515 | |
cca44b1b JB |
5516 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
5517 | function used for the current instruction. This function's job is to | |
5518 | put the CPU/memory state back to what it would have been if the | |
5519 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 5520 | |
cca44b1b JB |
5521 | /* NOP instruction (mov r0, r0). */ |
5522 | #define ARM_NOP 0xe1a00000 | |
34518530 | 5523 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
5524 | |
5525 | /* Helper for register reads for displaced stepping. In particular, this | |
5526 | returns the PC as it would be seen by the instruction at its original | |
5527 | location. */ | |
5528 | ||
5529 | ULONGEST | |
36073a92 YQ |
5530 | displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, |
5531 | int regno) | |
cca44b1b JB |
5532 | { |
5533 | ULONGEST ret; | |
36073a92 | 5534 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 5535 | |
bf9f652a | 5536 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 5537 | { |
4db71c0b YQ |
5538 | /* Compute pipeline offset: |
5539 | - When executing an ARM instruction, PC reads as the address of the | |
5540 | current instruction plus 8. | |
5541 | - When executing a Thumb instruction, PC reads as the address of the | |
5542 | current instruction plus 4. */ | |
5543 | ||
36073a92 | 5544 | if (!dsc->is_thumb) |
4db71c0b YQ |
5545 | from += 8; |
5546 | else | |
5547 | from += 4; | |
5548 | ||
cca44b1b JB |
5549 | if (debug_displaced) |
5550 | fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", | |
4db71c0b YQ |
5551 | (unsigned long) from); |
5552 | return (ULONGEST) from; | |
cca44b1b | 5553 | } |
c906108c | 5554 | else |
cca44b1b JB |
5555 | { |
5556 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
5557 | if (debug_displaced) | |
5558 | fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", | |
5559 | regno, (unsigned long) ret); | |
5560 | return ret; | |
5561 | } | |
c906108c SS |
5562 | } |
5563 | ||
cca44b1b JB |
5564 | static int |
5565 | displaced_in_arm_mode (struct regcache *regs) | |
5566 | { | |
5567 | ULONGEST ps; | |
9779414d | 5568 | ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); |
66e810cd | 5569 | |
cca44b1b | 5570 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 5571 | |
9779414d | 5572 | return (ps & t_bit) == 0; |
cca44b1b | 5573 | } |
66e810cd | 5574 | |
cca44b1b | 5575 | /* Write to the PC as from a branch instruction. */ |
c906108c | 5576 | |
cca44b1b | 5577 | static void |
36073a92 YQ |
5578 | branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
5579 | ULONGEST val) | |
c906108c | 5580 | { |
36073a92 | 5581 | if (!dsc->is_thumb) |
cca44b1b JB |
5582 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
5583 | architecture versions < 6. */ | |
0963b4bd MS |
5584 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5585 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 5586 | else |
0963b4bd MS |
5587 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5588 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 5589 | } |
66e810cd | 5590 | |
cca44b1b JB |
5591 | /* Write to the PC as from a branch-exchange instruction. */ |
5592 | ||
5593 | static void | |
5594 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
5595 | { | |
5596 | ULONGEST ps; | |
9779414d | 5597 | ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); |
cca44b1b JB |
5598 | |
5599 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
5600 | ||
5601 | if ((val & 1) == 1) | |
c906108c | 5602 | { |
9779414d | 5603 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
5604 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
5605 | } | |
5606 | else if ((val & 2) == 0) | |
5607 | { | |
9779414d | 5608 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5609 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
5610 | } |
5611 | else | |
5612 | { | |
cca44b1b JB |
5613 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
5614 | mode, align dest to 4 bytes). */ | |
5615 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 5616 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5617 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
5618 | } |
5619 | } | |
ed9a39eb | 5620 | |
cca44b1b | 5621 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 5622 | |
34e8f22d | 5623 | static void |
36073a92 YQ |
5624 | load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
5625 | ULONGEST val) | |
ed9a39eb | 5626 | { |
cca44b1b JB |
5627 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
5628 | bx_write_pc (regs, val); | |
5629 | else | |
36073a92 | 5630 | branch_write_pc (regs, dsc, val); |
cca44b1b | 5631 | } |
be8626e0 | 5632 | |
cca44b1b JB |
5633 | /* Write to the PC as if from an ALU instruction. */ |
5634 | ||
5635 | static void | |
36073a92 YQ |
5636 | alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, |
5637 | ULONGEST val) | |
cca44b1b | 5638 | { |
36073a92 | 5639 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
5640 | bx_write_pc (regs, val); |
5641 | else | |
36073a92 | 5642 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
5643 | } |
5644 | ||
5645 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
5646 | has a varying effects depending on the instruction which does the write: | |
5647 | this is controlled by the WRITE_PC argument. */ | |
5648 | ||
5649 | void | |
5650 | displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, | |
5651 | int regno, ULONGEST val, enum pc_write_style write_pc) | |
5652 | { | |
bf9f652a | 5653 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 5654 | { |
cca44b1b JB |
5655 | if (debug_displaced) |
5656 | fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", | |
5657 | (unsigned long) val); | |
5658 | switch (write_pc) | |
08216dd7 | 5659 | { |
cca44b1b | 5660 | case BRANCH_WRITE_PC: |
36073a92 | 5661 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
5662 | break; |
5663 | ||
cca44b1b JB |
5664 | case BX_WRITE_PC: |
5665 | bx_write_pc (regs, val); | |
5666 | break; | |
5667 | ||
5668 | case LOAD_WRITE_PC: | |
36073a92 | 5669 | load_write_pc (regs, dsc, val); |
cca44b1b JB |
5670 | break; |
5671 | ||
5672 | case ALU_WRITE_PC: | |
36073a92 | 5673 | alu_write_pc (regs, dsc, val); |
cca44b1b JB |
5674 | break; |
5675 | ||
5676 | case CANNOT_WRITE_PC: | |
5677 | warning (_("Instruction wrote to PC in an unexpected way when " | |
5678 | "single-stepping")); | |
08216dd7 RE |
5679 | break; |
5680 | ||
5681 | default: | |
97b9747c JB |
5682 | internal_error (__FILE__, __LINE__, |
5683 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 5684 | } |
b508a996 | 5685 | |
cca44b1b | 5686 | dsc->wrote_to_pc = 1; |
b508a996 | 5687 | } |
ed9a39eb | 5688 | else |
b508a996 | 5689 | { |
cca44b1b JB |
5690 | if (debug_displaced) |
5691 | fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", | |
5692 | regno, (unsigned long) val); | |
5693 | regcache_cooked_write_unsigned (regs, regno, val); | |
b508a996 | 5694 | } |
34e8f22d RE |
5695 | } |
5696 | ||
cca44b1b JB |
5697 | /* This function is used to concisely determine if an instruction INSN |
5698 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
5699 | corresponding fields of BITMASK set to 0b1111. The function |
5700 | returns return 1 if any of these fields in INSN reference the PC | |
5701 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
5702 | |
5703 | static int | |
cca44b1b | 5704 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 5705 | { |
cca44b1b | 5706 | uint32_t lowbit = 1; |
67255d04 | 5707 | |
cca44b1b JB |
5708 | while (bitmask != 0) |
5709 | { | |
5710 | uint32_t mask; | |
44e1a9eb | 5711 | |
cca44b1b JB |
5712 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
5713 | ; | |
67255d04 | 5714 | |
cca44b1b JB |
5715 | if (!lowbit) |
5716 | break; | |
67255d04 | 5717 | |
cca44b1b | 5718 | mask = lowbit * 0xf; |
67255d04 | 5719 | |
cca44b1b JB |
5720 | if ((insn & mask) == mask) |
5721 | return 1; | |
5722 | ||
5723 | bitmask &= ~mask; | |
67255d04 RE |
5724 | } |
5725 | ||
cca44b1b JB |
5726 | return 0; |
5727 | } | |
2af48f68 | 5728 | |
cca44b1b JB |
5729 | /* The simplest copy function. Many instructions have the same effect no |
5730 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 5731 | |
cca44b1b | 5732 | static int |
7ff120b4 YQ |
5733 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, |
5734 | const char *iname, struct displaced_step_closure *dsc) | |
cca44b1b JB |
5735 | { |
5736 | if (debug_displaced) | |
5737 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " | |
5738 | "opcode/class '%s' unmodified\n", (unsigned long) insn, | |
5739 | iname); | |
67255d04 | 5740 | |
cca44b1b | 5741 | dsc->modinsn[0] = insn; |
67255d04 | 5742 | |
cca44b1b JB |
5743 | return 0; |
5744 | } | |
5745 | ||
34518530 YQ |
5746 | static int |
5747 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
5748 | uint16_t insn2, const char *iname, | |
5749 | struct displaced_step_closure *dsc) | |
5750 | { | |
5751 | if (debug_displaced) | |
5752 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, " | |
5753 | "opcode/class '%s' unmodified\n", insn1, insn2, | |
5754 | iname); | |
5755 | ||
5756 | dsc->modinsn[0] = insn1; | |
5757 | dsc->modinsn[1] = insn2; | |
5758 | dsc->numinsns = 2; | |
5759 | ||
5760 | return 0; | |
5761 | } | |
5762 | ||
5763 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
5764 | modification. */ | |
5765 | static int | |
5766 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn, | |
5767 | const char *iname, | |
5768 | struct displaced_step_closure *dsc) | |
5769 | { | |
5770 | if (debug_displaced) | |
5771 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, " | |
5772 | "opcode/class '%s' unmodified\n", insn, | |
5773 | iname); | |
5774 | ||
5775 | dsc->modinsn[0] = insn; | |
5776 | ||
5777 | return 0; | |
5778 | } | |
5779 | ||
cca44b1b JB |
5780 | /* Preload instructions with immediate offset. */ |
5781 | ||
5782 | static void | |
6e39997a | 5783 | cleanup_preload (struct gdbarch *gdbarch, |
cca44b1b JB |
5784 | struct regcache *regs, struct displaced_step_closure *dsc) |
5785 | { | |
5786 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5787 | if (!dsc->u.preload.immed) | |
5788 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5789 | } | |
5790 | ||
7ff120b4 YQ |
5791 | static void |
5792 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
5793 | struct displaced_step_closure *dsc, unsigned int rn) | |
cca44b1b | 5794 | { |
cca44b1b | 5795 | ULONGEST rn_val; |
cca44b1b JB |
5796 | /* Preload instructions: |
5797 | ||
5798 | {pli/pld} [rn, #+/-imm] | |
5799 | -> | |
5800 | {pli/pld} [r0, #+/-imm]. */ | |
5801 | ||
36073a92 YQ |
5802 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5803 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5804 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
5805 | dsc->u.preload.immed = 1; |
5806 | ||
cca44b1b | 5807 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
5808 | } |
5809 | ||
cca44b1b | 5810 | static int |
7ff120b4 | 5811 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
cca44b1b JB |
5812 | struct displaced_step_closure *dsc) |
5813 | { | |
5814 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 5815 | |
7ff120b4 YQ |
5816 | if (!insn_references_pc (insn, 0x000f0000ul)) |
5817 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b JB |
5818 | |
5819 | if (debug_displaced) | |
5820 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
5821 | (unsigned long) insn); | |
5822 | ||
7ff120b4 YQ |
5823 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5824 | ||
5825 | install_preload (gdbarch, regs, dsc, rn); | |
5826 | ||
5827 | return 0; | |
5828 | } | |
5829 | ||
34518530 YQ |
5830 | static int |
5831 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
5832 | struct regcache *regs, struct displaced_step_closure *dsc) | |
5833 | { | |
5834 | unsigned int rn = bits (insn1, 0, 3); | |
5835 | unsigned int u_bit = bit (insn1, 7); | |
5836 | int imm12 = bits (insn2, 0, 11); | |
5837 | ULONGEST pc_val; | |
5838 | ||
5839 | if (rn != ARM_PC_REGNUM) | |
5840 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
5841 | ||
5842 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
5843 | PLD (literal) Encoding T1. */ | |
5844 | if (debug_displaced) | |
5845 | fprintf_unfiltered (gdb_stdlog, | |
5846 | "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n", | |
5847 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
5848 | imm12); | |
5849 | ||
5850 | if (!u_bit) | |
5851 | imm12 = -1 * imm12; | |
5852 | ||
5853 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
5854 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
5855 | ||
5856 | {pli/pld} [r0, r1] | |
5857 | ||
5858 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
5859 | ||
5860 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5861 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5862 | ||
5863 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5864 | ||
5865 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
5866 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
5867 | dsc->u.preload.immed = 0; | |
5868 | ||
5869 | /* {pli/pld} [r0, r1] */ | |
5870 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5871 | dsc->modinsn[1] = 0xf001; | |
5872 | dsc->numinsns = 2; | |
5873 | ||
5874 | dsc->cleanup = &cleanup_preload; | |
5875 | return 0; | |
5876 | } | |
5877 | ||
7ff120b4 YQ |
5878 | /* Preload instructions with register offset. */ |
5879 | ||
5880 | static void | |
5881 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
5882 | struct displaced_step_closure *dsc, unsigned int rn, | |
5883 | unsigned int rm) | |
5884 | { | |
5885 | ULONGEST rn_val, rm_val; | |
5886 | ||
cca44b1b JB |
5887 | /* Preload register-offset instructions: |
5888 | ||
5889 | {pli/pld} [rn, rm {, shift}] | |
5890 | -> | |
5891 | {pli/pld} [r0, r1 {, shift}]. */ | |
5892 | ||
36073a92 YQ |
5893 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5894 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5895 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5896 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5897 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5898 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
5899 | dsc->u.preload.immed = 0; |
5900 | ||
cca44b1b | 5901 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
5902 | } |
5903 | ||
5904 | static int | |
5905 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5906 | struct regcache *regs, | |
5907 | struct displaced_step_closure *dsc) | |
5908 | { | |
5909 | unsigned int rn = bits (insn, 16, 19); | |
5910 | unsigned int rm = bits (insn, 0, 3); | |
5911 | ||
5912 | ||
5913 | if (!insn_references_pc (insn, 0x000f000ful)) | |
5914 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
5915 | ||
5916 | if (debug_displaced) | |
5917 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
5918 | (unsigned long) insn); | |
5919 | ||
5920 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 5921 | |
7ff120b4 | 5922 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
5923 | return 0; |
5924 | } | |
5925 | ||
5926 | /* Copy/cleanup coprocessor load and store instructions. */ | |
5927 | ||
5928 | static void | |
6e39997a | 5929 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b JB |
5930 | struct regcache *regs, |
5931 | struct displaced_step_closure *dsc) | |
5932 | { | |
36073a92 | 5933 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5934 | |
5935 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5936 | ||
5937 | if (dsc->u.ldst.writeback) | |
5938 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
5939 | } | |
5940 | ||
7ff120b4 YQ |
5941 | static void |
5942 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
5943 | struct displaced_step_closure *dsc, | |
5944 | int writeback, unsigned int rn) | |
cca44b1b | 5945 | { |
cca44b1b | 5946 | ULONGEST rn_val; |
cca44b1b | 5947 | |
cca44b1b JB |
5948 | /* Coprocessor load/store instructions: |
5949 | ||
5950 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
5951 | -> | |
5952 | {stc/stc2} [r0, #+/-imm]. | |
5953 | ||
5954 | ldc/ldc2 are handled identically. */ | |
5955 | ||
36073a92 YQ |
5956 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5957 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
5958 | /* PC should be 4-byte aligned. */ |
5959 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
5960 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5961 | ||
7ff120b4 | 5962 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5963 | dsc->u.ldst.rn = rn; |
5964 | ||
7ff120b4 YQ |
5965 | dsc->cleanup = &cleanup_copro_load_store; |
5966 | } | |
5967 | ||
5968 | static int | |
5969 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
5970 | struct regcache *regs, | |
5971 | struct displaced_step_closure *dsc) | |
5972 | { | |
5973 | unsigned int rn = bits (insn, 16, 19); | |
5974 | ||
5975 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
5976 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
5977 | ||
5978 | if (debug_displaced) | |
5979 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " | |
5980 | "load/store insn %.8lx\n", (unsigned long) insn); | |
5981 | ||
cca44b1b JB |
5982 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5983 | ||
7ff120b4 | 5984 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
5985 | |
5986 | return 0; | |
5987 | } | |
5988 | ||
34518530 YQ |
5989 | static int |
5990 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
5991 | uint16_t insn2, struct regcache *regs, | |
5992 | struct displaced_step_closure *dsc) | |
5993 | { | |
5994 | unsigned int rn = bits (insn1, 0, 3); | |
5995 | ||
5996 | if (rn != ARM_PC_REGNUM) | |
5997 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
5998 | "copro load/store", dsc); | |
5999 | ||
6000 | if (debug_displaced) | |
6001 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " | |
6002 | "load/store insn %.4x%.4x\n", insn1, insn2); | |
6003 | ||
6004 | dsc->modinsn[0] = insn1 & 0xfff0; | |
6005 | dsc->modinsn[1] = insn2; | |
6006 | dsc->numinsns = 2; | |
6007 | ||
6008 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
6009 | doesn't support writeback, so pass 0. */ | |
6010 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
6011 | ||
6012 | return 0; | |
6013 | } | |
6014 | ||
cca44b1b JB |
6015 | /* Clean up branch instructions (actually perform the branch, by setting |
6016 | PC). */ | |
6017 | ||
6018 | static void | |
6e39997a | 6019 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
6020 | struct displaced_step_closure *dsc) |
6021 | { | |
36073a92 | 6022 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6023 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
6024 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
6025 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
6026 | ||
6027 | if (!branch_taken) | |
6028 | return; | |
6029 | ||
6030 | if (dsc->u.branch.link) | |
6031 | { | |
8c8dba6d YQ |
6032 | /* The value of LR should be the next insn of current one. In order |
6033 | not to confuse logic hanlding later insn `bx lr', if current insn mode | |
6034 | is Thumb, the bit 0 of LR value should be set to 1. */ | |
6035 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
6036 | ||
6037 | if (dsc->is_thumb) | |
6038 | next_insn_addr |= 0x1; | |
6039 | ||
6040 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
6041 | CANNOT_WRITE_PC); | |
cca44b1b JB |
6042 | } |
6043 | ||
bf9f652a | 6044 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
6045 | } |
6046 | ||
6047 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
6048 | ||
7ff120b4 YQ |
6049 | static void |
6050 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
6051 | struct displaced_step_closure *dsc, | |
6052 | unsigned int cond, int exchange, int link, long offset) | |
6053 | { | |
6054 | /* Implement "BL<cond> <label>" as: | |
6055 | ||
6056 | Preparation: cond <- instruction condition | |
6057 | Insn: mov r0, r0 (nop) | |
6058 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
6059 | ||
6060 | B<cond> similar, but don't set r14 in cleanup. */ | |
6061 | ||
6062 | dsc->u.branch.cond = cond; | |
6063 | dsc->u.branch.link = link; | |
6064 | dsc->u.branch.exchange = exchange; | |
6065 | ||
2b16b2e3 YQ |
6066 | dsc->u.branch.dest = dsc->insn_addr; |
6067 | if (link && exchange) | |
6068 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
6069 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
6070 | ||
7ff120b4 | 6071 | if (dsc->is_thumb) |
2b16b2e3 | 6072 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 6073 | else |
2b16b2e3 | 6074 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
6075 | |
6076 | dsc->cleanup = &cleanup_branch; | |
6077 | } | |
cca44b1b | 6078 | static int |
7ff120b4 YQ |
6079 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
6080 | struct regcache *regs, struct displaced_step_closure *dsc) | |
cca44b1b JB |
6081 | { |
6082 | unsigned int cond = bits (insn, 28, 31); | |
6083 | int exchange = (cond == 0xf); | |
6084 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
6085 | long offset; |
6086 | ||
6087 | if (debug_displaced) | |
6088 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " | |
6089 | "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", | |
6090 | (unsigned long) insn); | |
cca44b1b JB |
6091 | if (exchange) |
6092 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
6093 | then arrange the switch into Thumb mode. */ | |
6094 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
6095 | else | |
6096 | offset = bits (insn, 0, 23) << 2; | |
6097 | ||
6098 | if (bit (offset, 25)) | |
6099 | offset = offset | ~0x3ffffff; | |
6100 | ||
cca44b1b JB |
6101 | dsc->modinsn[0] = ARM_NOP; |
6102 | ||
7ff120b4 | 6103 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
6104 | return 0; |
6105 | } | |
6106 | ||
34518530 YQ |
6107 | static int |
6108 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
6109 | uint16_t insn2, struct regcache *regs, | |
6110 | struct displaced_step_closure *dsc) | |
6111 | { | |
6112 | int link = bit (insn2, 14); | |
6113 | int exchange = link && !bit (insn2, 12); | |
6114 | int cond = INST_AL; | |
6115 | long offset = 0; | |
6116 | int j1 = bit (insn2, 13); | |
6117 | int j2 = bit (insn2, 11); | |
6118 | int s = sbits (insn1, 10, 10); | |
6119 | int i1 = !(j1 ^ bit (insn1, 10)); | |
6120 | int i2 = !(j2 ^ bit (insn1, 10)); | |
6121 | ||
6122 | if (!link && !exchange) /* B */ | |
6123 | { | |
6124 | offset = (bits (insn2, 0, 10) << 1); | |
6125 | if (bit (insn2, 12)) /* Encoding T4 */ | |
6126 | { | |
6127 | offset |= (bits (insn1, 0, 9) << 12) | |
6128 | | (i2 << 22) | |
6129 | | (i1 << 23) | |
6130 | | (s << 24); | |
6131 | cond = INST_AL; | |
6132 | } | |
6133 | else /* Encoding T3 */ | |
6134 | { | |
6135 | offset |= (bits (insn1, 0, 5) << 12) | |
6136 | | (j1 << 18) | |
6137 | | (j2 << 19) | |
6138 | | (s << 20); | |
6139 | cond = bits (insn1, 6, 9); | |
6140 | } | |
6141 | } | |
6142 | else | |
6143 | { | |
6144 | offset = (bits (insn1, 0, 9) << 12); | |
6145 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
6146 | offset |= exchange ? | |
6147 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
6148 | } | |
6149 | ||
6150 | if (debug_displaced) | |
6151 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s insn " | |
6152 | "%.4x %.4x with offset %.8lx\n", | |
6153 | link ? (exchange) ? "blx" : "bl" : "b", | |
6154 | insn1, insn2, offset); | |
6155 | ||
6156 | dsc->modinsn[0] = THUMB_NOP; | |
6157 | ||
6158 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
6159 | return 0; | |
6160 | } | |
6161 | ||
6162 | /* Copy B Thumb instructions. */ | |
6163 | static int | |
6164 | thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn, | |
6165 | struct displaced_step_closure *dsc) | |
6166 | { | |
6167 | unsigned int cond = 0; | |
6168 | int offset = 0; | |
6169 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
6170 | CORE_ADDR from = dsc->insn_addr; | |
6171 | ||
6172 | if (bit_12_15 == 0xd) | |
6173 | { | |
6174 | /* offset = SignExtend (imm8:0, 32) */ | |
6175 | offset = sbits ((insn << 1), 0, 8); | |
6176 | cond = bits (insn, 8, 11); | |
6177 | } | |
6178 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
6179 | { | |
6180 | offset = sbits ((insn << 1), 0, 11); | |
6181 | cond = INST_AL; | |
6182 | } | |
6183 | ||
6184 | if (debug_displaced) | |
6185 | fprintf_unfiltered (gdb_stdlog, | |
6186 | "displaced: copying b immediate insn %.4x " | |
6187 | "with offset %d\n", insn, offset); | |
6188 | ||
6189 | dsc->u.branch.cond = cond; | |
6190 | dsc->u.branch.link = 0; | |
6191 | dsc->u.branch.exchange = 0; | |
6192 | dsc->u.branch.dest = from + 4 + offset; | |
6193 | ||
6194 | dsc->modinsn[0] = THUMB_NOP; | |
6195 | ||
6196 | dsc->cleanup = &cleanup_branch; | |
6197 | ||
6198 | return 0; | |
6199 | } | |
6200 | ||
cca44b1b JB |
6201 | /* Copy BX/BLX with register-specified destinations. */ |
6202 | ||
7ff120b4 YQ |
6203 | static void |
6204 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
6205 | struct displaced_step_closure *dsc, int link, | |
6206 | unsigned int cond, unsigned int rm) | |
cca44b1b | 6207 | { |
cca44b1b JB |
6208 | /* Implement {BX,BLX}<cond> <reg>" as: |
6209 | ||
6210 | Preparation: cond <- instruction condition | |
6211 | Insn: mov r0, r0 (nop) | |
6212 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
6213 | ||
6214 | Don't set r14 in cleanup for BX. */ | |
6215 | ||
36073a92 | 6216 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6217 | |
6218 | dsc->u.branch.cond = cond; | |
6219 | dsc->u.branch.link = link; | |
cca44b1b | 6220 | |
7ff120b4 | 6221 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
6222 | |
6223 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 6224 | } |
cca44b1b | 6225 | |
7ff120b4 YQ |
6226 | static int |
6227 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
6228 | struct regcache *regs, struct displaced_step_closure *dsc) | |
6229 | { | |
6230 | unsigned int cond = bits (insn, 28, 31); | |
6231 | /* BX: x12xxx1x | |
6232 | BLX: x12xxx3x. */ | |
6233 | int link = bit (insn, 5); | |
6234 | unsigned int rm = bits (insn, 0, 3); | |
6235 | ||
6236 | if (debug_displaced) | |
6237 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx", | |
6238 | (unsigned long) insn); | |
6239 | ||
6240 | dsc->modinsn[0] = ARM_NOP; | |
6241 | ||
6242 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
6243 | return 0; |
6244 | } | |
6245 | ||
34518530 YQ |
6246 | static int |
6247 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6248 | struct regcache *regs, | |
6249 | struct displaced_step_closure *dsc) | |
6250 | { | |
6251 | int link = bit (insn, 7); | |
6252 | unsigned int rm = bits (insn, 3, 6); | |
6253 | ||
6254 | if (debug_displaced) | |
6255 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x", | |
6256 | (unsigned short) insn); | |
6257 | ||
6258 | dsc->modinsn[0] = THUMB_NOP; | |
6259 | ||
6260 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
6261 | ||
6262 | return 0; | |
6263 | } | |
6264 | ||
6265 | ||
0963b4bd | 6266 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
6267 | |
6268 | static void | |
6e39997a | 6269 | cleanup_alu_imm (struct gdbarch *gdbarch, |
cca44b1b JB |
6270 | struct regcache *regs, struct displaced_step_closure *dsc) |
6271 | { | |
36073a92 | 6272 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6273 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
6274 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6275 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6276 | } | |
6277 | ||
6278 | static int | |
7ff120b4 YQ |
6279 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
6280 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
6281 | { |
6282 | unsigned int rn = bits (insn, 16, 19); | |
6283 | unsigned int rd = bits (insn, 12, 15); | |
6284 | unsigned int op = bits (insn, 21, 24); | |
6285 | int is_mov = (op == 0xd); | |
6286 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
6287 | |
6288 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 6289 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b JB |
6290 | |
6291 | if (debug_displaced) | |
6292 | fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn " | |
6293 | "%.8lx\n", is_mov ? "move" : "ALU", | |
6294 | (unsigned long) insn); | |
6295 | ||
6296 | /* Instruction is of form: | |
6297 | ||
6298 | <op><cond> rd, [rn,] #imm | |
6299 | ||
6300 | Rewrite as: | |
6301 | ||
6302 | Preparation: tmp1, tmp2 <- r0, r1; | |
6303 | r0, r1 <- rd, rn | |
6304 | Insn: <op><cond> r0, r1, #imm | |
6305 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6306 | */ | |
6307 | ||
36073a92 YQ |
6308 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6309 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6310 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6311 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
6312 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6313 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6314 | dsc->rd = rd; | |
6315 | ||
6316 | if (is_mov) | |
6317 | dsc->modinsn[0] = insn & 0xfff00fff; | |
6318 | else | |
6319 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
6320 | ||
6321 | dsc->cleanup = &cleanup_alu_imm; | |
6322 | ||
6323 | return 0; | |
6324 | } | |
6325 | ||
34518530 YQ |
6326 | static int |
6327 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6328 | uint16_t insn2, struct regcache *regs, | |
6329 | struct displaced_step_closure *dsc) | |
6330 | { | |
6331 | unsigned int op = bits (insn1, 5, 8); | |
6332 | unsigned int rn, rm, rd; | |
6333 | ULONGEST rd_val, rn_val; | |
6334 | ||
6335 | rn = bits (insn1, 0, 3); /* Rn */ | |
6336 | rm = bits (insn2, 0, 3); /* Rm */ | |
6337 | rd = bits (insn2, 8, 11); /* Rd */ | |
6338 | ||
6339 | /* This routine is only called for instruction MOV. */ | |
6340 | gdb_assert (op == 0x2 && rn == 0xf); | |
6341 | ||
6342 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
6343 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
6344 | ||
6345 | if (debug_displaced) | |
6346 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x%.4x\n", | |
6347 | "ALU", insn1, insn2); | |
6348 | ||
6349 | /* Instruction is of form: | |
6350 | ||
6351 | <op><cond> rd, [rn,] #imm | |
6352 | ||
6353 | Rewrite as: | |
6354 | ||
6355 | Preparation: tmp1, tmp2 <- r0, r1; | |
6356 | r0, r1 <- rd, rn | |
6357 | Insn: <op><cond> r0, r1, #imm | |
6358 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6359 | */ | |
6360 | ||
6361 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6362 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6363 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6364 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6365 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
6366 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6367 | dsc->rd = rd; | |
6368 | ||
6369 | dsc->modinsn[0] = insn1; | |
6370 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
6371 | dsc->numinsns = 2; | |
6372 | ||
6373 | dsc->cleanup = &cleanup_alu_imm; | |
6374 | ||
6375 | return 0; | |
6376 | } | |
6377 | ||
cca44b1b JB |
6378 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
6379 | ||
6380 | static void | |
6e39997a | 6381 | cleanup_alu_reg (struct gdbarch *gdbarch, |
cca44b1b JB |
6382 | struct regcache *regs, struct displaced_step_closure *dsc) |
6383 | { | |
6384 | ULONGEST rd_val; | |
6385 | int i; | |
6386 | ||
36073a92 | 6387 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6388 | |
6389 | for (i = 0; i < 3; i++) | |
6390 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6391 | ||
6392 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6393 | } | |
6394 | ||
7ff120b4 YQ |
6395 | static void |
6396 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
6397 | struct displaced_step_closure *dsc, | |
6398 | unsigned int rd, unsigned int rn, unsigned int rm) | |
cca44b1b | 6399 | { |
cca44b1b | 6400 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 6401 | |
cca44b1b JB |
6402 | /* Instruction is of form: |
6403 | ||
6404 | <op><cond> rd, [rn,] rm [, <shift>] | |
6405 | ||
6406 | Rewrite as: | |
6407 | ||
6408 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
6409 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 6410 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
6411 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
6412 | */ | |
6413 | ||
36073a92 YQ |
6414 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6415 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6416 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6417 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6418 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6419 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
6420 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6421 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6422 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6423 | dsc->rd = rd; | |
6424 | ||
7ff120b4 YQ |
6425 | dsc->cleanup = &cleanup_alu_reg; |
6426 | } | |
6427 | ||
6428 | static int | |
6429 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
6430 | struct displaced_step_closure *dsc) | |
6431 | { | |
6432 | unsigned int op = bits (insn, 21, 24); | |
6433 | int is_mov = (op == 0xd); | |
6434 | ||
6435 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6436 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
6437 | ||
6438 | if (debug_displaced) | |
6439 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n", | |
6440 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
6441 | ||
cca44b1b JB |
6442 | if (is_mov) |
6443 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
6444 | else | |
6445 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
6446 | ||
7ff120b4 YQ |
6447 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
6448 | bits (insn, 0, 3)); | |
cca44b1b JB |
6449 | return 0; |
6450 | } | |
6451 | ||
34518530 YQ |
6452 | static int |
6453 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6454 | struct regcache *regs, | |
6455 | struct displaced_step_closure *dsc) | |
6456 | { | |
ef713951 | 6457 | unsigned rm, rd; |
34518530 | 6458 | |
ef713951 YQ |
6459 | rm = bits (insn, 3, 6); |
6460 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 6461 | |
ef713951 | 6462 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
6463 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
6464 | ||
6465 | if (debug_displaced) | |
ef713951 YQ |
6466 | fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n", |
6467 | (unsigned short) insn); | |
34518530 | 6468 | |
ef713951 | 6469 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 6470 | |
ef713951 | 6471 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
6472 | |
6473 | return 0; | |
6474 | } | |
6475 | ||
cca44b1b JB |
6476 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
6477 | ||
6478 | static void | |
6e39997a | 6479 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b JB |
6480 | struct regcache *regs, |
6481 | struct displaced_step_closure *dsc) | |
6482 | { | |
36073a92 | 6483 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6484 | int i; |
6485 | ||
6486 | for (i = 0; i < 4; i++) | |
6487 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6488 | ||
6489 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6490 | } | |
6491 | ||
7ff120b4 YQ |
6492 | static void |
6493 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
6494 | struct displaced_step_closure *dsc, | |
6495 | unsigned int rd, unsigned int rn, unsigned int rm, | |
6496 | unsigned rs) | |
cca44b1b | 6497 | { |
7ff120b4 | 6498 | int i; |
cca44b1b | 6499 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 6500 | |
cca44b1b JB |
6501 | /* Instruction is of form: |
6502 | ||
6503 | <op><cond> rd, [rn,] rm, <shift> rs | |
6504 | ||
6505 | Rewrite as: | |
6506 | ||
6507 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
6508 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
6509 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
6510 | Cleanup: tmp5 <- r0 | |
6511 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
6512 | rd <- tmp5 | |
6513 | */ | |
6514 | ||
6515 | for (i = 0; i < 4; i++) | |
36073a92 | 6516 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 6517 | |
36073a92 YQ |
6518 | rd_val = displaced_read_reg (regs, dsc, rd); |
6519 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6520 | rm_val = displaced_read_reg (regs, dsc, rm); | |
6521 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
6522 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6523 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6524 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6525 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
6526 | dsc->rd = rd; | |
7ff120b4 YQ |
6527 | dsc->cleanup = &cleanup_alu_shifted_reg; |
6528 | } | |
6529 | ||
6530 | static int | |
6531 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
6532 | struct regcache *regs, | |
6533 | struct displaced_step_closure *dsc) | |
6534 | { | |
6535 | unsigned int op = bits (insn, 21, 24); | |
6536 | int is_mov = (op == 0xd); | |
6537 | unsigned int rd, rn, rm, rs; | |
6538 | ||
6539 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
6540 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
6541 | ||
6542 | if (debug_displaced) | |
6543 | fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn " | |
6544 | "%.8lx\n", is_mov ? "move" : "ALU", | |
6545 | (unsigned long) insn); | |
6546 | ||
6547 | rn = bits (insn, 16, 19); | |
6548 | rm = bits (insn, 0, 3); | |
6549 | rs = bits (insn, 8, 11); | |
6550 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
6551 | |
6552 | if (is_mov) | |
6553 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
6554 | else | |
6555 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
6556 | ||
7ff120b4 | 6557 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
6558 | |
6559 | return 0; | |
6560 | } | |
6561 | ||
6562 | /* Clean up load instructions. */ | |
6563 | ||
6564 | static void | |
6e39997a | 6565 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
6566 | struct displaced_step_closure *dsc) |
6567 | { | |
6568 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 6569 | |
36073a92 | 6570 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 6571 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
6572 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
6573 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
6574 | |
6575 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6576 | if (dsc->u.ldst.xfersize > 4) | |
6577 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6578 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6579 | if (!dsc->u.ldst.immed) | |
6580 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6581 | ||
6582 | /* Handle register writeback. */ | |
6583 | if (dsc->u.ldst.writeback) | |
6584 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6585 | /* Put result in right place. */ | |
6586 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
6587 | if (dsc->u.ldst.xfersize == 8) | |
6588 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
6589 | } | |
6590 | ||
6591 | /* Clean up store instructions. */ | |
6592 | ||
6593 | static void | |
6e39997a | 6594 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
6595 | struct displaced_step_closure *dsc) |
6596 | { | |
36073a92 | 6597 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
6598 | |
6599 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6600 | if (dsc->u.ldst.xfersize > 4) | |
6601 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6602 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6603 | if (!dsc->u.ldst.immed) | |
6604 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6605 | if (!dsc->u.ldst.restore_r4) | |
6606 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
6607 | ||
6608 | /* Writeback. */ | |
6609 | if (dsc->u.ldst.writeback) | |
6610 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6611 | } | |
6612 | ||
6613 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
6614 | transfers, which have a different encoding to byte/word transfers. */ | |
6615 | ||
6616 | static int | |
7ff120b4 YQ |
6617 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, |
6618 | struct regcache *regs, struct displaced_step_closure *dsc) | |
cca44b1b JB |
6619 | { |
6620 | unsigned int op1 = bits (insn, 20, 24); | |
6621 | unsigned int op2 = bits (insn, 5, 6); | |
6622 | unsigned int rt = bits (insn, 12, 15); | |
6623 | unsigned int rn = bits (insn, 16, 19); | |
6624 | unsigned int rm = bits (insn, 0, 3); | |
6625 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
6626 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
6627 | int immed = (op1 & 0x4) != 0; | |
6628 | int opcode; | |
6629 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
6630 | |
6631 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 6632 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b JB |
6633 | |
6634 | if (debug_displaced) | |
6635 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " | |
6636 | "insn %.8lx\n", unpriveleged ? "unpriveleged " : "", | |
6637 | (unsigned long) insn); | |
6638 | ||
6639 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
6640 | ||
6641 | if (opcode < 0) | |
6642 | internal_error (__FILE__, __LINE__, | |
6643 | _("copy_extra_ld_st: instruction decode error")); | |
6644 | ||
36073a92 YQ |
6645 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6646 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6647 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6648 | if (!immed) |
36073a92 | 6649 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6650 | |
36073a92 | 6651 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 6652 | if (bytesize[opcode] == 8) |
36073a92 YQ |
6653 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
6654 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6655 | if (!immed) |
36073a92 | 6656 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6657 | |
6658 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6659 | if (bytesize[opcode] == 8) | |
6660 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
6661 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6662 | if (!immed) | |
6663 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
6664 | ||
6665 | dsc->rd = rt; | |
6666 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
6667 | dsc->u.ldst.rn = rn; | |
6668 | dsc->u.ldst.immed = immed; | |
6669 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
6670 | dsc->u.ldst.restore_r4 = 0; | |
6671 | ||
6672 | if (immed) | |
6673 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
6674 | -> | |
6675 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
6676 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6677 | else | |
6678 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
6679 | -> | |
6680 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
6681 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6682 | ||
6683 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
6684 | ||
6685 | return 0; | |
6686 | } | |
6687 | ||
0f6f04ba | 6688 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 6689 | |
7ff120b4 | 6690 | static void |
0f6f04ba YQ |
6691 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
6692 | struct displaced_step_closure *dsc, int load, | |
6693 | int immed, int writeback, int size, int usermode, | |
6694 | int rt, int rm, int rn) | |
cca44b1b | 6695 | { |
cca44b1b | 6696 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 6697 | |
36073a92 YQ |
6698 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6699 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6700 | if (!immed) |
36073a92 | 6701 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6702 | if (!load) |
36073a92 | 6703 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 6704 | |
36073a92 YQ |
6705 | rt_val = displaced_read_reg (regs, dsc, rt); |
6706 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6707 | if (!immed) |
36073a92 | 6708 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6709 | |
6710 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6711 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6712 | if (!immed) | |
6713 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 6714 | dsc->rd = rt; |
0f6f04ba | 6715 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
6716 | dsc->u.ldst.rn = rn; |
6717 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 6718 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
6719 | |
6720 | /* To write PC we can do: | |
6721 | ||
494e194e YQ |
6722 | Before this sequence of instructions: |
6723 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
6724 | r2 is the Rn value got from dispalced_read_reg. | |
6725 | ||
6726 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
6727 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
6728 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
6729 | = addr(Insn1) + offset - addr(Insn3) - 8 | |
6730 | = offset - 16 | |
6731 | Insn4: add r4, r4, #8 r4 = offset - 8 | |
6732 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
6733 | = from + offset | |
6734 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) | |
cca44b1b JB |
6735 | |
6736 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
6737 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
6738 | of this can be found in Section "Saving from r15" in | |
6739 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 6740 | |
7ff120b4 YQ |
6741 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
6742 | } | |
6743 | ||
34518530 YQ |
6744 | |
6745 | static int | |
6746 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
6747 | uint16_t insn2, struct regcache *regs, | |
6748 | struct displaced_step_closure *dsc, int size) | |
6749 | { | |
6750 | unsigned int u_bit = bit (insn1, 7); | |
6751 | unsigned int rt = bits (insn2, 12, 15); | |
6752 | int imm12 = bits (insn2, 0, 11); | |
6753 | ULONGEST pc_val; | |
6754 | ||
6755 | if (debug_displaced) | |
6756 | fprintf_unfiltered (gdb_stdlog, | |
6757 | "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n", | |
6758 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
6759 | imm12); | |
6760 | ||
6761 | if (!u_bit) | |
6762 | imm12 = -1 * imm12; | |
6763 | ||
6764 | /* Rewrite instruction LDR Rt imm12 into: | |
6765 | ||
6766 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
6767 | ||
6768 | LDR R0, R2, R3, | |
6769 | ||
6770 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
6771 | ||
6772 | ||
6773 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6774 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6775 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
6776 | ||
6777 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6778 | ||
6779 | pc_val = pc_val & 0xfffffffc; | |
6780 | ||
6781 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
6782 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
6783 | ||
6784 | dsc->rd = rt; | |
6785 | ||
6786 | dsc->u.ldst.xfersize = size; | |
6787 | dsc->u.ldst.immed = 0; | |
6788 | dsc->u.ldst.writeback = 0; | |
6789 | dsc->u.ldst.restore_r4 = 0; | |
6790 | ||
6791 | /* LDR R0, R2, R3 */ | |
6792 | dsc->modinsn[0] = 0xf852; | |
6793 | dsc->modinsn[1] = 0x3; | |
6794 | dsc->numinsns = 2; | |
6795 | ||
6796 | dsc->cleanup = &cleanup_load; | |
6797 | ||
6798 | return 0; | |
6799 | } | |
6800 | ||
6801 | static int | |
6802 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6803 | uint16_t insn2, struct regcache *regs, | |
6804 | struct displaced_step_closure *dsc, | |
6805 | int writeback, int immed) | |
6806 | { | |
6807 | unsigned int rt = bits (insn2, 12, 15); | |
6808 | unsigned int rn = bits (insn1, 0, 3); | |
6809 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
6810 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
6811 | be PC, so we don't have to check it. */ | |
6812 | ||
6813 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
6814 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
6815 | dsc); | |
6816 | ||
6817 | if (debug_displaced) | |
6818 | fprintf_unfiltered (gdb_stdlog, | |
6819 | "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n", | |
6820 | rt, rn, insn1, insn2); | |
6821 | ||
6822 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
6823 | 0, rt, rm, rn); | |
6824 | ||
6825 | dsc->u.ldst.restore_r4 = 0; | |
6826 | ||
6827 | if (immed) | |
6828 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
6829 | -> | |
6830 | ldr[b]<cond> r0, [r2, #imm]. */ | |
6831 | { | |
6832 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6833 | dsc->modinsn[1] = insn2 & 0x0fff; | |
6834 | } | |
6835 | else | |
6836 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
6837 | -> | |
6838 | ldr[b]<cond> r0, [r2, r3]. */ | |
6839 | { | |
6840 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6841 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
6842 | } | |
6843 | ||
6844 | dsc->numinsns = 2; | |
6845 | ||
6846 | return 0; | |
6847 | } | |
6848 | ||
6849 | ||
7ff120b4 YQ |
6850 | static int |
6851 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
6852 | struct regcache *regs, | |
6853 | struct displaced_step_closure *dsc, | |
0f6f04ba | 6854 | int load, int size, int usermode) |
7ff120b4 YQ |
6855 | { |
6856 | int immed = !bit (insn, 25); | |
6857 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
6858 | unsigned int rt = bits (insn, 12, 15); | |
6859 | unsigned int rn = bits (insn, 16, 19); | |
6860 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
6861 | ||
6862 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6863 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
6864 | ||
6865 | if (debug_displaced) | |
6866 | fprintf_unfiltered (gdb_stdlog, | |
6867 | "displaced: copying %s%s r%d [r%d] insn %.8lx\n", | |
0f6f04ba YQ |
6868 | load ? (size == 1 ? "ldrb" : "ldr") |
6869 | : (size == 1 ? "strb" : "str"), usermode ? "t" : "", | |
7ff120b4 YQ |
6870 | rt, rn, |
6871 | (unsigned long) insn); | |
6872 | ||
0f6f04ba YQ |
6873 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
6874 | usermode, rt, rm, rn); | |
7ff120b4 | 6875 | |
bf9f652a | 6876 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
6877 | { |
6878 | dsc->u.ldst.restore_r4 = 0; | |
6879 | ||
6880 | if (immed) | |
6881 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
6882 | -> | |
6883 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
6884 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6885 | else | |
6886 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
6887 | -> | |
6888 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
6889 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6890 | } | |
6891 | else | |
6892 | { | |
6893 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
6894 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
6895 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
6896 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
6897 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
6898 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
6899 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
6900 | ||
6901 | /* As above. */ | |
6902 | if (immed) | |
6903 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
6904 | else | |
6905 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
6906 | ||
cca44b1b JB |
6907 | dsc->numinsns = 6; |
6908 | } | |
6909 | ||
6910 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
6911 | ||
6912 | return 0; | |
6913 | } | |
6914 | ||
6915 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
6916 | unfortunate corner case: it's impossible to implement correctly by modifying | |
6917 | the instruction. The issue is as follows: we have an instruction, | |
6918 | ||
6919 | ldm rN, {r0-r15} | |
6920 | ||
6921 | which we must rewrite to avoid loading PC. A possible solution would be to | |
6922 | do the load in two halves, something like (with suitable cleanup | |
6923 | afterwards): | |
6924 | ||
6925 | mov r8, rN | |
6926 | ldm[id][ab] r8!, {r0-r7} | |
6927 | str r7, <temp> | |
6928 | ldm[id][ab] r8, {r7-r14} | |
6929 | <bkpt> | |
6930 | ||
6931 | but at present there's no suitable place for <temp>, since the scratch space | |
6932 | is overwritten before the cleanup routine is called. For now, we simply | |
6933 | emulate the instruction. */ | |
6934 | ||
6935 | static void | |
6936 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
6937 | struct displaced_step_closure *dsc) | |
6938 | { | |
cca44b1b JB |
6939 | int inc = dsc->u.block.increment; |
6940 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
6941 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
6942 | uint32_t regmask = dsc->u.block.regmask; | |
6943 | int regno = inc ? 0 : 15; | |
6944 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
6945 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
6946 | && (regmask & 0x8000) != 0; | |
36073a92 | 6947 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6948 | int do_transfer = condition_true (dsc->u.block.cond, status); |
6949 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6950 | ||
6951 | if (!do_transfer) | |
6952 | return; | |
6953 | ||
6954 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
6955 | sensible we can do here. Complain loudly. */ | |
6956 | if (exception_return) | |
6957 | error (_("Cannot single-step exception return")); | |
6958 | ||
6959 | /* We don't handle any stores here for now. */ | |
6960 | gdb_assert (dsc->u.block.load != 0); | |
6961 | ||
6962 | if (debug_displaced) | |
6963 | fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: " | |
6964 | "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm", | |
6965 | dsc->u.block.increment ? "inc" : "dec", | |
6966 | dsc->u.block.before ? "before" : "after"); | |
6967 | ||
6968 | while (regmask) | |
6969 | { | |
6970 | uint32_t memword; | |
6971 | ||
6972 | if (inc) | |
bf9f652a | 6973 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
6974 | regno++; |
6975 | else | |
6976 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
6977 | regno--; | |
6978 | ||
6979 | xfer_addr += bump_before; | |
6980 | ||
6981 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
6982 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
6983 | ||
6984 | xfer_addr += bump_after; | |
6985 | ||
6986 | regmask &= ~(1 << regno); | |
6987 | } | |
6988 | ||
6989 | if (dsc->u.block.writeback) | |
6990 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
6991 | CANNOT_WRITE_PC); | |
6992 | } | |
6993 | ||
6994 | /* Clean up an STM which included the PC in the register list. */ | |
6995 | ||
6996 | static void | |
6997 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
6998 | struct displaced_step_closure *dsc) | |
6999 | { | |
36073a92 | 7000 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
7001 | int store_executed = condition_true (dsc->u.block.cond, status); |
7002 | CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask); | |
7003 | CORE_ADDR stm_insn_addr; | |
7004 | uint32_t pc_val; | |
7005 | long offset; | |
7006 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7007 | ||
7008 | /* If condition code fails, there's nothing else to do. */ | |
7009 | if (!store_executed) | |
7010 | return; | |
7011 | ||
7012 | if (dsc->u.block.increment) | |
7013 | { | |
7014 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
7015 | ||
7016 | if (dsc->u.block.before) | |
7017 | pc_stored_at += 4; | |
7018 | } | |
7019 | else | |
7020 | { | |
7021 | pc_stored_at = dsc->u.block.xfer_addr; | |
7022 | ||
7023 | if (dsc->u.block.before) | |
7024 | pc_stored_at -= 4; | |
7025 | } | |
7026 | ||
7027 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
7028 | stm_insn_addr = dsc->scratch_base; | |
7029 | offset = pc_val - stm_insn_addr; | |
7030 | ||
7031 | if (debug_displaced) | |
7032 | fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for " | |
7033 | "STM instruction\n", offset); | |
7034 | ||
7035 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
7036 | instruction. */ | |
7037 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
7038 | dsc->insn_addr + offset); | |
7039 | } | |
7040 | ||
7041 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
7042 | the registers in the transferred list into a contiguous range r0...rX (to | |
7043 | avoid loading PC directly and losing control of the debugged program), so we | |
7044 | must undo that here. */ | |
7045 | ||
7046 | static void | |
6e39997a | 7047 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b JB |
7048 | struct regcache *regs, |
7049 | struct displaced_step_closure *dsc) | |
7050 | { | |
36073a92 | 7051 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 7052 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 7053 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
cca44b1b JB |
7054 | unsigned int regs_loaded = bitcount (mask); |
7055 | unsigned int num_to_shuffle = regs_loaded, clobbered; | |
7056 | ||
7057 | /* The method employed here will fail if the register list is fully populated | |
7058 | (we need to avoid loading PC directly). */ | |
7059 | gdb_assert (num_to_shuffle < 16); | |
7060 | ||
7061 | if (!load_executed) | |
7062 | return; | |
7063 | ||
7064 | clobbered = (1 << num_to_shuffle) - 1; | |
7065 | ||
7066 | while (num_to_shuffle > 0) | |
7067 | { | |
7068 | if ((mask & (1 << write_reg)) != 0) | |
7069 | { | |
7070 | unsigned int read_reg = num_to_shuffle - 1; | |
7071 | ||
7072 | if (read_reg != write_reg) | |
7073 | { | |
36073a92 | 7074 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b JB |
7075 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
7076 | if (debug_displaced) | |
7077 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move " | |
7078 | "loaded register r%d to r%d\n"), read_reg, | |
7079 | write_reg); | |
7080 | } | |
7081 | else if (debug_displaced) | |
7082 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register " | |
7083 | "r%d already in the right place\n"), | |
7084 | write_reg); | |
7085 | ||
7086 | clobbered &= ~(1 << write_reg); | |
7087 | ||
7088 | num_to_shuffle--; | |
7089 | } | |
7090 | ||
7091 | write_reg--; | |
7092 | } | |
7093 | ||
7094 | /* Restore any registers we scribbled over. */ | |
7095 | for (write_reg = 0; clobbered != 0; write_reg++) | |
7096 | { | |
7097 | if ((clobbered & (1 << write_reg)) != 0) | |
7098 | { | |
7099 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
7100 | CANNOT_WRITE_PC); | |
7101 | if (debug_displaced) | |
7102 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored " | |
7103 | "clobbered register r%d\n"), write_reg); | |
7104 | clobbered &= ~(1 << write_reg); | |
7105 | } | |
7106 | } | |
7107 | ||
7108 | /* Perform register writeback manually. */ | |
7109 | if (dsc->u.block.writeback) | |
7110 | { | |
7111 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
7112 | ||
7113 | if (dsc->u.block.increment) | |
7114 | new_rn_val += regs_loaded * 4; | |
7115 | else | |
7116 | new_rn_val -= regs_loaded * 4; | |
7117 | ||
7118 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
7119 | CANNOT_WRITE_PC); | |
7120 | } | |
7121 | } | |
7122 | ||
7123 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
7124 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
7125 | ||
7126 | static int | |
7ff120b4 YQ |
7127 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
7128 | struct regcache *regs, | |
7129 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7130 | { |
7131 | int load = bit (insn, 20); | |
7132 | int user = bit (insn, 22); | |
7133 | int increment = bit (insn, 23); | |
7134 | int before = bit (insn, 24); | |
7135 | int writeback = bit (insn, 21); | |
7136 | int rn = bits (insn, 16, 19); | |
cca44b1b | 7137 | |
0963b4bd MS |
7138 | /* Block transfers which don't mention PC can be run directly |
7139 | out-of-line. */ | |
bf9f652a | 7140 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 7141 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 7142 | |
bf9f652a | 7143 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 7144 | { |
0963b4bd MS |
7145 | warning (_("displaced: Unpredictable LDM or STM with " |
7146 | "base register r15")); | |
7ff120b4 | 7147 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
7148 | } |
7149 | ||
7150 | if (debug_displaced) | |
7151 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " | |
7152 | "%.8lx\n", (unsigned long) insn); | |
7153 | ||
36073a92 | 7154 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
7155 | dsc->u.block.rn = rn; |
7156 | ||
7157 | dsc->u.block.load = load; | |
7158 | dsc->u.block.user = user; | |
7159 | dsc->u.block.increment = increment; | |
7160 | dsc->u.block.before = before; | |
7161 | dsc->u.block.writeback = writeback; | |
7162 | dsc->u.block.cond = bits (insn, 28, 31); | |
7163 | ||
7164 | dsc->u.block.regmask = insn & 0xffff; | |
7165 | ||
7166 | if (load) | |
7167 | { | |
7168 | if ((insn & 0xffff) == 0xffff) | |
7169 | { | |
7170 | /* LDM with a fully-populated register list. This case is | |
7171 | particularly tricky. Implement for now by fully emulating the | |
7172 | instruction (which might not behave perfectly in all cases, but | |
7173 | these instructions should be rare enough for that not to matter | |
7174 | too much). */ | |
7175 | dsc->modinsn[0] = ARM_NOP; | |
7176 | ||
7177 | dsc->cleanup = &cleanup_block_load_all; | |
7178 | } | |
7179 | else | |
7180 | { | |
7181 | /* LDM of a list of registers which includes PC. Implement by | |
7182 | rewriting the list of registers to be transferred into a | |
7183 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
7184 | registers into the correct places in the cleanup routine. */ | |
7185 | unsigned int regmask = insn & 0xffff; | |
7186 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; | |
7187 | unsigned int to = 0, from = 0, i, new_rn; | |
7188 | ||
7189 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 7190 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
7191 | |
7192 | /* Writeback makes things complicated. We need to avoid clobbering | |
7193 | the base register with one of the registers in our modified | |
7194 | register list, but just using a different register can't work in | |
7195 | all cases, e.g.: | |
7196 | ||
7197 | ldm r14!, {r0-r13,pc} | |
7198 | ||
7199 | which would need to be rewritten as: | |
7200 | ||
7201 | ldm rN!, {r0-r14} | |
7202 | ||
7203 | but that can't work, because there's no free register for N. | |
7204 | ||
7205 | Solve this by turning off the writeback bit, and emulating | |
7206 | writeback manually in the cleanup routine. */ | |
7207 | ||
7208 | if (writeback) | |
7209 | insn &= ~(1 << 21); | |
7210 | ||
7211 | new_regmask = (1 << num_in_list) - 1; | |
7212 | ||
7213 | if (debug_displaced) | |
7214 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " | |
7215 | "{..., pc}: original reg list %.4x, modified " | |
7216 | "list %.4x\n"), rn, writeback ? "!" : "", | |
7217 | (int) insn & 0xffff, new_regmask); | |
7218 | ||
7219 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
7220 | ||
7221 | dsc->cleanup = &cleanup_block_load_pc; | |
7222 | } | |
7223 | } | |
7224 | else | |
7225 | { | |
7226 | /* STM of a list of registers which includes PC. Run the instruction | |
7227 | as-is, but out of line: this will store the wrong value for the PC, | |
7228 | so we must manually fix up the memory in the cleanup routine. | |
7229 | Doing things this way has the advantage that we can auto-detect | |
7230 | the offset of the PC write (which is architecture-dependent) in | |
7231 | the cleanup routine. */ | |
7232 | dsc->modinsn[0] = insn; | |
7233 | ||
7234 | dsc->cleanup = &cleanup_block_store_pc; | |
7235 | } | |
7236 | ||
7237 | return 0; | |
7238 | } | |
7239 | ||
34518530 YQ |
7240 | static int |
7241 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
7242 | struct regcache *regs, | |
7243 | struct displaced_step_closure *dsc) | |
cca44b1b | 7244 | { |
34518530 YQ |
7245 | int rn = bits (insn1, 0, 3); |
7246 | int load = bit (insn1, 4); | |
7247 | int writeback = bit (insn1, 5); | |
cca44b1b | 7248 | |
34518530 YQ |
7249 | /* Block transfers which don't mention PC can be run directly |
7250 | out-of-line. */ | |
7251 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
7252 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 7253 | |
34518530 YQ |
7254 | if (rn == ARM_PC_REGNUM) |
7255 | { | |
7256 | warning (_("displaced: Unpredictable LDM or STM with " | |
7257 | "base register r15")); | |
7258 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7259 | "unpredictable ldm/stm", dsc); | |
7260 | } | |
cca44b1b JB |
7261 | |
7262 | if (debug_displaced) | |
34518530 YQ |
7263 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " |
7264 | "%.4x%.4x\n", insn1, insn2); | |
cca44b1b | 7265 | |
34518530 YQ |
7266 | /* Clear bit 13, since it should be always zero. */ |
7267 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
7268 | dsc->u.block.rn = rn; | |
cca44b1b | 7269 | |
34518530 YQ |
7270 | dsc->u.block.load = load; |
7271 | dsc->u.block.user = 0; | |
7272 | dsc->u.block.increment = bit (insn1, 7); | |
7273 | dsc->u.block.before = bit (insn1, 8); | |
7274 | dsc->u.block.writeback = writeback; | |
7275 | dsc->u.block.cond = INST_AL; | |
7276 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 7277 | |
34518530 YQ |
7278 | if (load) |
7279 | { | |
7280 | if (dsc->u.block.regmask == 0xffff) | |
7281 | { | |
7282 | /* This branch is impossible to happen. */ | |
7283 | gdb_assert (0); | |
7284 | } | |
7285 | else | |
7286 | { | |
7287 | unsigned int regmask = dsc->u.block.regmask; | |
7288 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; | |
7289 | unsigned int to = 0, from = 0, i, new_rn; | |
7290 | ||
7291 | for (i = 0; i < num_in_list; i++) | |
7292 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7293 | ||
7294 | if (writeback) | |
7295 | insn1 &= ~(1 << 5); | |
7296 | ||
7297 | new_regmask = (1 << num_in_list) - 1; | |
7298 | ||
7299 | if (debug_displaced) | |
7300 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " | |
7301 | "{..., pc}: original reg list %.4x, modified " | |
7302 | "list %.4x\n"), rn, writeback ? "!" : "", | |
7303 | (int) dsc->u.block.regmask, new_regmask); | |
7304 | ||
7305 | dsc->modinsn[0] = insn1; | |
7306 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
7307 | dsc->numinsns = 2; | |
7308 | ||
7309 | dsc->cleanup = &cleanup_block_load_pc; | |
7310 | } | |
7311 | } | |
7312 | else | |
7313 | { | |
7314 | dsc->modinsn[0] = insn1; | |
7315 | dsc->modinsn[1] = insn2; | |
7316 | dsc->numinsns = 2; | |
7317 | dsc->cleanup = &cleanup_block_store_pc; | |
7318 | } | |
7319 | return 0; | |
7320 | } | |
7321 | ||
7322 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden | |
7323 | for Linux, where some SVC instructions must be treated specially. */ | |
7324 | ||
7325 | static void | |
7326 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
7327 | struct displaced_step_closure *dsc) | |
7328 | { | |
7329 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
7330 | ||
7331 | if (debug_displaced) | |
7332 | fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at " | |
7333 | "%.8lx\n", (unsigned long) resume_addr); | |
7334 | ||
7335 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
7336 | } | |
7337 | ||
7338 | ||
7339 | /* Common copy routine for svc instruciton. */ | |
7340 | ||
7341 | static int | |
7342 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
7343 | struct displaced_step_closure *dsc) | |
7344 | { | |
7345 | /* Preparation: none. | |
7346 | Insn: unmodified svc. | |
7347 | Cleanup: pc <- insn_addr + insn_size. */ | |
7348 | ||
7349 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
7350 | instruction. */ | |
7351 | dsc->wrote_to_pc = 1; | |
7352 | ||
7353 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
7354 | if (dsc->u.svc.copy_svc_os) |
7355 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
7356 | else | |
7357 | { | |
7358 | dsc->cleanup = &cleanup_svc; | |
7359 | return 0; | |
7360 | } | |
34518530 YQ |
7361 | } |
7362 | ||
7363 | static int | |
7364 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
7365 | struct regcache *regs, struct displaced_step_closure *dsc) | |
7366 | { | |
7367 | ||
7368 | if (debug_displaced) | |
7369 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n", | |
7370 | (unsigned long) insn); | |
7371 | ||
7372 | dsc->modinsn[0] = insn; | |
7373 | ||
7374 | return install_svc (gdbarch, regs, dsc); | |
7375 | } | |
7376 | ||
7377 | static int | |
7378 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
7379 | struct regcache *regs, struct displaced_step_closure *dsc) | |
7380 | { | |
7381 | ||
7382 | if (debug_displaced) | |
7383 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.4x\n", | |
7384 | insn); | |
bd18283a | 7385 | |
34518530 YQ |
7386 | dsc->modinsn[0] = insn; |
7387 | ||
7388 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
7389 | } |
7390 | ||
7391 | /* Copy undefined instructions. */ | |
7392 | ||
7393 | static int | |
7ff120b4 YQ |
7394 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
7395 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7396 | { |
7397 | if (debug_displaced) | |
0963b4bd MS |
7398 | fprintf_unfiltered (gdb_stdlog, |
7399 | "displaced: copying undefined insn %.8lx\n", | |
cca44b1b JB |
7400 | (unsigned long) insn); |
7401 | ||
7402 | dsc->modinsn[0] = insn; | |
7403 | ||
7404 | return 0; | |
7405 | } | |
7406 | ||
34518530 YQ |
7407 | static int |
7408 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
7409 | struct displaced_step_closure *dsc) | |
7410 | { | |
7411 | ||
7412 | if (debug_displaced) | |
7413 | fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn " | |
7414 | "%.4x %.4x\n", (unsigned short) insn1, | |
7415 | (unsigned short) insn2); | |
7416 | ||
7417 | dsc->modinsn[0] = insn1; | |
7418 | dsc->modinsn[1] = insn2; | |
7419 | dsc->numinsns = 2; | |
7420 | ||
7421 | return 0; | |
7422 | } | |
7423 | ||
cca44b1b JB |
7424 | /* Copy unpredictable instructions. */ |
7425 | ||
7426 | static int | |
7ff120b4 YQ |
7427 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
7428 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7429 | { |
7430 | if (debug_displaced) | |
7431 | fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn " | |
7432 | "%.8lx\n", (unsigned long) insn); | |
7433 | ||
7434 | dsc->modinsn[0] = insn; | |
7435 | ||
7436 | return 0; | |
7437 | } | |
7438 | ||
7439 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
7440 | the presentation in the ARM ARM. */ | |
7441 | ||
7442 | static int | |
7ff120b4 YQ |
7443 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
7444 | struct regcache *regs, | |
7445 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7446 | { |
7447 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
7448 | unsigned int rn = bits (insn, 16, 19); | |
7449 | ||
7450 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0) | |
7ff120b4 | 7451 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
cca44b1b | 7452 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1) |
7ff120b4 | 7453 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 7454 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 7455 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 7456 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
7457 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
7458 | dsc); | |
cca44b1b | 7459 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 7460 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7461 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 7462 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
7463 | else if ((op1 & 0x77) == 0x51) |
7464 | { | |
7465 | if (rn != 0xf) | |
7ff120b4 | 7466 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 7467 | else |
7ff120b4 | 7468 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7469 | } |
7470 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 7471 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
7472 | else if (op1 == 0x57) |
7473 | switch (op2) | |
7474 | { | |
7ff120b4 YQ |
7475 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
7476 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
7477 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
7478 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
7479 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
7480 | } |
7481 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 7482 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7483 | else if ((op2 & 0x1) == 0x0) |
7484 | switch (op1 & ~0x80) | |
7485 | { | |
7486 | case 0x61: | |
7ff120b4 | 7487 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7488 | case 0x65: |
7ff120b4 | 7489 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b JB |
7490 | case 0x71: case 0x75: |
7491 | /* pld/pldw reg. */ | |
7ff120b4 | 7492 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7493 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 7494 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 7495 | default: |
7ff120b4 | 7496 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7497 | } |
7498 | else | |
7ff120b4 | 7499 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
7500 | } |
7501 | ||
7502 | static int | |
7ff120b4 YQ |
7503 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
7504 | struct regcache *regs, | |
7505 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7506 | { |
7507 | if (bit (insn, 27) == 0) | |
7ff120b4 | 7508 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7509 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
7510 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
7511 | { | |
7512 | case 0x0: case 0x2: | |
7ff120b4 | 7513 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
7514 | |
7515 | case 0x1: case 0x3: | |
7ff120b4 | 7516 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
7517 | |
7518 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 7519 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7520 | |
7521 | case 0x8: | |
7522 | switch ((insn & 0xe00000) >> 21) | |
7523 | { | |
7524 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
7525 | /* stc/stc2. */ | |
7ff120b4 | 7526 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7527 | |
7528 | case 0x2: | |
7ff120b4 | 7529 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
7530 | |
7531 | default: | |
7ff120b4 | 7532 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7533 | } |
7534 | ||
7535 | case 0x9: | |
7536 | { | |
7537 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
7538 | switch ((insn & 0xe00000) >> 21) | |
7539 | { | |
7540 | case 0x1: case 0x3: | |
7541 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
7542 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
7543 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
7544 | |
7545 | case 0x2: | |
7ff120b4 | 7546 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7547 | |
7548 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7549 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
7550 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
7551 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
7552 | |
7553 | default: | |
7ff120b4 | 7554 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7555 | } |
7556 | } | |
7557 | ||
7558 | case 0xa: | |
7ff120b4 | 7559 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
7560 | |
7561 | case 0xb: | |
7562 | if (bits (insn, 16, 19) == 0xf) | |
7563 | /* ldc/ldc2 lit. */ | |
7ff120b4 | 7564 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7565 | else |
7ff120b4 | 7566 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7567 | |
7568 | case 0xc: | |
7569 | if (bit (insn, 4)) | |
7ff120b4 | 7570 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7571 | else |
7ff120b4 | 7572 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7573 | |
7574 | case 0xd: | |
7575 | if (bit (insn, 4)) | |
7ff120b4 | 7576 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7577 | else |
7ff120b4 | 7578 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7579 | |
7580 | default: | |
7ff120b4 | 7581 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7582 | } |
7583 | } | |
7584 | ||
7585 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
7586 | ||
7587 | static int | |
7ff120b4 YQ |
7588 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
7589 | struct regcache *regs, | |
7590 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7591 | { |
7592 | unsigned int op2 = bits (insn, 4, 6); | |
7593 | unsigned int op = bits (insn, 21, 22); | |
7594 | unsigned int op1 = bits (insn, 16, 19); | |
7595 | ||
7596 | switch (op2) | |
7597 | { | |
7598 | case 0x0: | |
7ff120b4 | 7599 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
7600 | |
7601 | case 0x1: | |
7602 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 7603 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7604 | else if (op == 0x3) |
7ff120b4 | 7605 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 7606 | else |
7ff120b4 | 7607 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7608 | |
7609 | case 0x2: | |
7610 | if (op == 0x1) | |
7611 | /* Not really supported. */ | |
7ff120b4 | 7612 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 7613 | else |
7ff120b4 | 7614 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7615 | |
7616 | case 0x3: | |
7617 | if (op == 0x1) | |
7ff120b4 | 7618 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 7619 | regs, dsc); /* blx register. */ |
cca44b1b | 7620 | else |
7ff120b4 | 7621 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7622 | |
7623 | case 0x5: | |
7ff120b4 | 7624 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
7625 | |
7626 | case 0x7: | |
7627 | if (op == 0x1) | |
7ff120b4 | 7628 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b JB |
7629 | else if (op == 0x3) |
7630 | /* Not really supported. */ | |
7ff120b4 | 7631 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
cca44b1b JB |
7632 | |
7633 | default: | |
7ff120b4 | 7634 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7635 | } |
7636 | } | |
7637 | ||
7638 | static int | |
7ff120b4 YQ |
7639 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
7640 | struct regcache *regs, | |
7641 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7642 | { |
7643 | if (bit (insn, 25)) | |
7644 | switch (bits (insn, 20, 24)) | |
7645 | { | |
7646 | case 0x10: | |
7ff120b4 | 7647 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
7648 | |
7649 | case 0x14: | |
7ff120b4 | 7650 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
7651 | |
7652 | case 0x12: case 0x16: | |
7ff120b4 | 7653 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
7654 | |
7655 | default: | |
7ff120b4 | 7656 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7657 | } |
7658 | else | |
7659 | { | |
7660 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
7661 | ||
7662 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 7663 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7664 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 7665 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7666 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 7667 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 7668 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 7669 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 7670 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 7671 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 7672 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 7673 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b JB |
7674 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
7675 | /* 2nd arg means "unpriveleged". */ | |
7ff120b4 YQ |
7676 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
7677 | dsc); | |
cca44b1b JB |
7678 | } |
7679 | ||
7680 | /* Should be unreachable. */ | |
7681 | return 1; | |
7682 | } | |
7683 | ||
7684 | static int | |
7ff120b4 YQ |
7685 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
7686 | struct regcache *regs, | |
7687 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7688 | { |
7689 | int a = bit (insn, 25), b = bit (insn, 4); | |
7690 | uint32_t op1 = bits (insn, 20, 24); | |
7691 | int rn_f = bits (insn, 16, 19) == 0xf; | |
7692 | ||
7693 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
7694 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 7695 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
7696 | else if ((!a && (op1 & 0x17) == 0x02) |
7697 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 7698 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
7699 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
7700 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 7701 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
7702 | else if ((!a && (op1 & 0x17) == 0x03) |
7703 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 7704 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
7705 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
7706 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 7707 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
7708 | else if ((!a && (op1 & 0x17) == 0x06) |
7709 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 7710 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
7711 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
7712 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 7713 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
7714 | else if ((!a && (op1 & 0x17) == 0x07) |
7715 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 7716 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
7717 | |
7718 | /* Should be unreachable. */ | |
7719 | return 1; | |
7720 | } | |
7721 | ||
7722 | static int | |
7ff120b4 YQ |
7723 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
7724 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7725 | { |
7726 | switch (bits (insn, 20, 24)) | |
7727 | { | |
7728 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 7729 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
7730 | |
7731 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 7732 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
7733 | |
7734 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
7735 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 7736 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
7737 | "decode/pack/unpack/saturate/reverse", dsc); |
7738 | ||
7739 | case 0x18: | |
7740 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
7741 | { | |
7742 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 7743 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 7744 | else |
7ff120b4 | 7745 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
7746 | } |
7747 | else | |
7ff120b4 | 7748 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7749 | |
7750 | case 0x1a: case 0x1b: | |
7751 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7752 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 7753 | else |
7ff120b4 | 7754 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7755 | |
7756 | case 0x1c: case 0x1d: | |
7757 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
7758 | { | |
7759 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 7760 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 7761 | else |
7ff120b4 | 7762 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
7763 | } |
7764 | else | |
7ff120b4 | 7765 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7766 | |
7767 | case 0x1e: case 0x1f: | |
7768 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7769 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 7770 | else |
7ff120b4 | 7771 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7772 | } |
7773 | ||
7774 | /* Should be unreachable. */ | |
7775 | return 1; | |
7776 | } | |
7777 | ||
7778 | static int | |
7ff120b4 YQ |
7779 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn, |
7780 | struct regcache *regs, | |
7781 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7782 | { |
7783 | if (bit (insn, 25)) | |
7ff120b4 | 7784 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 7785 | else |
7ff120b4 | 7786 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7787 | } |
7788 | ||
7789 | static int | |
7ff120b4 YQ |
7790 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
7791 | struct regcache *regs, | |
7792 | struct displaced_step_closure *dsc) | |
cca44b1b JB |
7793 | { |
7794 | unsigned int opcode = bits (insn, 20, 24); | |
7795 | ||
7796 | switch (opcode) | |
7797 | { | |
7798 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 7799 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
7800 | |
7801 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
7802 | case 0x12: case 0x16: | |
7ff120b4 | 7803 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
7804 | |
7805 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
7806 | case 0x13: case 0x17: | |
7ff120b4 | 7807 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
7808 | |
7809 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7810 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7811 | /* Note: no writeback for these instructions. Bit 25 will always be | |
7812 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 7813 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7814 | } |
7815 | ||
7816 | /* Should be unreachable. */ | |
7817 | return 1; | |
7818 | } | |
7819 | ||
34518530 YQ |
7820 | /* Decode shifted register instructions. */ |
7821 | ||
7822 | static int | |
7823 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
7824 | uint16_t insn2, struct regcache *regs, | |
7825 | struct displaced_step_closure *dsc) | |
7826 | { | |
7827 | /* PC is only allowed to be used in instruction MOV. */ | |
7828 | ||
7829 | unsigned int op = bits (insn1, 5, 8); | |
7830 | unsigned int rn = bits (insn1, 0, 3); | |
7831 | ||
7832 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
7833 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
7834 | else | |
7835 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7836 | "dp (shift reg)", dsc); | |
7837 | } | |
7838 | ||
7839 | ||
7840 | /* Decode extension register load/store. Exactly the same as | |
7841 | arm_decode_ext_reg_ld_st. */ | |
7842 | ||
7843 | static int | |
7844 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
7845 | uint16_t insn2, struct regcache *regs, | |
7846 | struct displaced_step_closure *dsc) | |
7847 | { | |
7848 | unsigned int opcode = bits (insn1, 4, 8); | |
7849 | ||
7850 | switch (opcode) | |
7851 | { | |
7852 | case 0x04: case 0x05: | |
7853 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7854 | "vfp/neon vmov", dsc); | |
7855 | ||
7856 | case 0x08: case 0x0c: /* 01x00 */ | |
7857 | case 0x0a: case 0x0e: /* 01x10 */ | |
7858 | case 0x12: case 0x16: /* 10x10 */ | |
7859 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7860 | "vfp/neon vstm/vpush", dsc); | |
7861 | ||
7862 | case 0x09: case 0x0d: /* 01x01 */ | |
7863 | case 0x0b: case 0x0f: /* 01x11 */ | |
7864 | case 0x13: case 0x17: /* 10x11 */ | |
7865 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7866 | "vfp/neon vldm/vpop", dsc); | |
7867 | ||
7868 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7869 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7870 | "vstr", dsc); | |
7871 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7872 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
7873 | } | |
7874 | ||
7875 | /* Should be unreachable. */ | |
7876 | return 1; | |
7877 | } | |
7878 | ||
cca44b1b | 7879 | static int |
7ff120b4 YQ |
7880 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, |
7881 | struct regcache *regs, struct displaced_step_closure *dsc) | |
cca44b1b JB |
7882 | { |
7883 | unsigned int op1 = bits (insn, 20, 25); | |
7884 | int op = bit (insn, 4); | |
7885 | unsigned int coproc = bits (insn, 8, 11); | |
7886 | unsigned int rn = bits (insn, 16, 19); | |
7887 | ||
7888 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 7889 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7890 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
7891 | && (coproc & 0xe) != 0xa) | |
7892 | /* stc/stc2. */ | |
7ff120b4 | 7893 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7894 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
7895 | && (coproc & 0xe) != 0xa) | |
7896 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 7897 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7898 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 7899 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 7900 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 7901 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 7902 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7903 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 7904 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7905 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7906 | else if ((op1 & 0x30) == 0x20 && !op) |
7907 | { | |
7908 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 7909 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 7910 | else |
7ff120b4 | 7911 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7912 | } |
7913 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 7914 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 7915 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7916 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7917 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7918 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7919 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 7920 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 7921 | else |
7ff120b4 | 7922 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
7923 | } |
7924 | ||
34518530 YQ |
7925 | static int |
7926 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
7927 | uint16_t insn2, struct regcache *regs, | |
7928 | struct displaced_step_closure *dsc) | |
7929 | { | |
7930 | unsigned int coproc = bits (insn2, 8, 11); | |
7931 | unsigned int op1 = bits (insn1, 4, 9); | |
7932 | unsigned int bit_5_8 = bits (insn1, 5, 8); | |
7933 | unsigned int bit_9 = bit (insn1, 9); | |
7934 | unsigned int bit_4 = bit (insn1, 4); | |
7935 | unsigned int rn = bits (insn1, 0, 3); | |
7936 | ||
7937 | if (bit_9 == 0) | |
7938 | { | |
7939 | if (bit_5_8 == 2) | |
7940 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7941 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
7942 | dsc); | |
7943 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
7944 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7945 | else | |
7946 | { | |
7947 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
7948 | if ((coproc & 0xe) == 0xa) | |
7949 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
7950 | dsc); | |
7951 | else /* coproc is not 101x. */ | |
7952 | { | |
7953 | if (bit_4 == 0) /* STC/STC2. */ | |
7954 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7955 | "stc/stc2", dsc); | |
7956 | else /* LDC/LDC2 {literal, immeidate}. */ | |
7957 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, | |
7958 | regs, dsc); | |
7959 | } | |
7960 | } | |
7961 | } | |
7962 | else | |
7963 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
7964 | ||
7965 | return 0; | |
7966 | } | |
7967 | ||
7968 | static void | |
7969 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
7970 | struct displaced_step_closure *dsc, int rd) | |
7971 | { | |
7972 | /* ADR Rd, #imm | |
7973 | ||
7974 | Rewrite as: | |
7975 | ||
7976 | Preparation: Rd <- PC | |
7977 | Insn: ADD Rd, #imm | |
7978 | Cleanup: Null. | |
7979 | */ | |
7980 | ||
7981 | /* Rd <- PC */ | |
7982 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7983 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
7984 | } | |
7985 | ||
7986 | static int | |
7987 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
7988 | struct displaced_step_closure *dsc, | |
7989 | int rd, unsigned int imm) | |
7990 | { | |
7991 | ||
7992 | /* Encoding T2: ADDS Rd, #imm */ | |
7993 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
7994 | ||
7995 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7996 | ||
7997 | return 0; | |
7998 | } | |
7999 | ||
8000 | static int | |
8001 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
8002 | struct regcache *regs, | |
8003 | struct displaced_step_closure *dsc) | |
8004 | { | |
8005 | unsigned int rd = bits (insn, 8, 10); | |
8006 | unsigned int imm8 = bits (insn, 0, 7); | |
8007 | ||
8008 | if (debug_displaced) | |
8009 | fprintf_unfiltered (gdb_stdlog, | |
8010 | "displaced: copying thumb adr r%d, #%d insn %.4x\n", | |
8011 | rd, imm8, insn); | |
8012 | ||
8013 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
8014 | } | |
8015 | ||
8016 | static int | |
8017 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
8018 | uint16_t insn2, struct regcache *regs, | |
8019 | struct displaced_step_closure *dsc) | |
8020 | { | |
8021 | unsigned int rd = bits (insn2, 8, 11); | |
8022 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
8023 | extract raw immediate encoding rather than computing immediate. When | |
8024 | generating ADD or SUB instruction, we can simply perform OR operation to | |
8025 | set immediate into ADD. */ | |
8026 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
8027 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
8028 | ||
8029 | if (debug_displaced) | |
8030 | fprintf_unfiltered (gdb_stdlog, | |
8031 | "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n", | |
8032 | rd, imm_i, imm_3_8, insn1, insn2); | |
8033 | ||
8034 | if (bit (insn1, 7)) /* Encoding T2 */ | |
8035 | { | |
8036 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
8037 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
8038 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
8039 | } | |
8040 | else /* Encoding T3 */ | |
8041 | { | |
8042 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
8043 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
8044 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
8045 | } | |
8046 | dsc->numinsns = 2; | |
8047 | ||
8048 | install_pc_relative (gdbarch, regs, dsc, rd); | |
8049 | ||
8050 | return 0; | |
8051 | } | |
8052 | ||
8053 | static int | |
8054 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1, | |
8055 | struct regcache *regs, | |
8056 | struct displaced_step_closure *dsc) | |
8057 | { | |
8058 | unsigned int rt = bits (insn1, 8, 10); | |
8059 | unsigned int pc; | |
8060 | int imm8 = (bits (insn1, 0, 7) << 2); | |
8061 | CORE_ADDR from = dsc->insn_addr; | |
8062 | ||
8063 | /* LDR Rd, #imm8 | |
8064 | ||
8065 | Rwrite as: | |
8066 | ||
8067 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
8068 | ||
8069 | Insn: LDR R0, [R2, R3]; | |
8070 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
8071 | ||
8072 | if (debug_displaced) | |
8073 | fprintf_unfiltered (gdb_stdlog, | |
8074 | "displaced: copying thumb ldr r%d [pc #%d]\n" | |
8075 | , rt, imm8); | |
8076 | ||
8077 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
8078 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
8079 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
8080 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
8081 | /* The assembler calculates the required value of the offset from the | |
8082 | Align(PC,4) value of this instruction to the label. */ | |
8083 | pc = pc & 0xfffffffc; | |
8084 | ||
8085 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
8086 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
8087 | ||
8088 | dsc->rd = rt; | |
8089 | dsc->u.ldst.xfersize = 4; | |
8090 | dsc->u.ldst.rn = 0; | |
8091 | dsc->u.ldst.immed = 0; | |
8092 | dsc->u.ldst.writeback = 0; | |
8093 | dsc->u.ldst.restore_r4 = 0; | |
8094 | ||
8095 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
8096 | ||
8097 | dsc->cleanup = &cleanup_load; | |
8098 | ||
8099 | return 0; | |
8100 | } | |
8101 | ||
8102 | /* Copy Thumb cbnz/cbz insruction. */ | |
8103 | ||
8104 | static int | |
8105 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
8106 | struct regcache *regs, | |
8107 | struct displaced_step_closure *dsc) | |
8108 | { | |
8109 | int non_zero = bit (insn1, 11); | |
8110 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
8111 | CORE_ADDR from = dsc->insn_addr; | |
8112 | int rn = bits (insn1, 0, 2); | |
8113 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
8114 | ||
8115 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
8116 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
8117 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
8118 | condition is false, let it be, cleanup_branch will do nothing. */ | |
8119 | if (dsc->u.branch.cond) | |
8120 | { | |
8121 | dsc->u.branch.cond = INST_AL; | |
8122 | dsc->u.branch.dest = from + 4 + imm5; | |
8123 | } | |
8124 | else | |
8125 | dsc->u.branch.dest = from + 2; | |
8126 | ||
8127 | dsc->u.branch.link = 0; | |
8128 | dsc->u.branch.exchange = 0; | |
8129 | ||
8130 | if (debug_displaced) | |
8131 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s [r%d = 0x%x]" | |
8132 | " insn %.4x to %.8lx\n", non_zero ? "cbnz" : "cbz", | |
8133 | rn, rn_val, insn1, dsc->u.branch.dest); | |
8134 | ||
8135 | dsc->modinsn[0] = THUMB_NOP; | |
8136 | ||
8137 | dsc->cleanup = &cleanup_branch; | |
8138 | return 0; | |
8139 | } | |
8140 | ||
8141 | /* Copy Table Branch Byte/Halfword */ | |
8142 | static int | |
8143 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
8144 | uint16_t insn2, struct regcache *regs, | |
8145 | struct displaced_step_closure *dsc) | |
8146 | { | |
8147 | ULONGEST rn_val, rm_val; | |
8148 | int is_tbh = bit (insn2, 4); | |
8149 | CORE_ADDR halfwords = 0; | |
8150 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8151 | ||
8152 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
8153 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
8154 | ||
8155 | if (is_tbh) | |
8156 | { | |
8157 | gdb_byte buf[2]; | |
8158 | ||
8159 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
8160 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
8161 | } | |
8162 | else | |
8163 | { | |
8164 | gdb_byte buf[1]; | |
8165 | ||
8166 | target_read_memory (rn_val + rm_val, buf, 1); | |
8167 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
8168 | } | |
8169 | ||
8170 | if (debug_displaced) | |
8171 | fprintf_unfiltered (gdb_stdlog, "displaced: %s base 0x%x offset 0x%x" | |
8172 | " offset 0x%x\n", is_tbh ? "tbh" : "tbb", | |
8173 | (unsigned int) rn_val, (unsigned int) rm_val, | |
8174 | (unsigned int) halfwords); | |
8175 | ||
8176 | dsc->u.branch.cond = INST_AL; | |
8177 | dsc->u.branch.link = 0; | |
8178 | dsc->u.branch.exchange = 0; | |
8179 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
8180 | ||
8181 | dsc->cleanup = &cleanup_branch; | |
8182 | ||
8183 | return 0; | |
8184 | } | |
8185 | ||
8186 | static void | |
8187 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
8188 | struct displaced_step_closure *dsc) | |
8189 | { | |
8190 | /* PC <- r7 */ | |
8191 | int val = displaced_read_reg (regs, dsc, 7); | |
8192 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
8193 | ||
8194 | /* r7 <- r8 */ | |
8195 | val = displaced_read_reg (regs, dsc, 8); | |
8196 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
8197 | ||
8198 | /* r8 <- tmp[0] */ | |
8199 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
8200 | ||
8201 | } | |
8202 | ||
8203 | static int | |
8204 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1, | |
8205 | struct regcache *regs, | |
8206 | struct displaced_step_closure *dsc) | |
8207 | { | |
8208 | dsc->u.block.regmask = insn1 & 0x00ff; | |
8209 | ||
8210 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
8211 | to : | |
8212 | ||
8213 | (1) register list is full, that is, r0-r7 are used. | |
8214 | Prepare: tmp[0] <- r8 | |
8215 | ||
8216 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
8217 | MOV r8, r7; Move value of r7 to r8; | |
8218 | POP {r7}; Store PC value into r7. | |
8219 | ||
8220 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
8221 | ||
8222 | (2) register list is not full, supposing there are N registers in | |
8223 | register list (except PC, 0 <= N <= 7). | |
8224 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
8225 | ||
8226 | POP {r0, r1, ...., rN}; | |
8227 | ||
8228 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
8229 | from tmp[] properly. | |
8230 | */ | |
8231 | if (debug_displaced) | |
8232 | fprintf_unfiltered (gdb_stdlog, | |
8233 | "displaced: copying thumb pop {%.8x, pc} insn %.4x\n", | |
8234 | dsc->u.block.regmask, insn1); | |
8235 | ||
8236 | if (dsc->u.block.regmask == 0xff) | |
8237 | { | |
8238 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
8239 | ||
8240 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
8241 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
8242 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
8243 | ||
8244 | dsc->numinsns = 3; | |
8245 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
8246 | } | |
8247 | else | |
8248 | { | |
8249 | unsigned int num_in_list = bitcount (dsc->u.block.regmask); | |
8250 | unsigned int new_regmask, bit = 1; | |
8251 | unsigned int to = 0, from = 0, i, new_rn; | |
8252 | ||
8253 | for (i = 0; i < num_in_list + 1; i++) | |
8254 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
8255 | ||
8256 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
8257 | ||
8258 | if (debug_displaced) | |
8259 | fprintf_unfiltered (gdb_stdlog, _("displaced: POP " | |
8260 | "{..., pc}: original reg list %.4x," | |
8261 | " modified list %.4x\n"), | |
8262 | (int) dsc->u.block.regmask, new_regmask); | |
8263 | ||
8264 | dsc->u.block.regmask |= 0x8000; | |
8265 | dsc->u.block.writeback = 0; | |
8266 | dsc->u.block.cond = INST_AL; | |
8267 | ||
8268 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
8269 | ||
8270 | dsc->cleanup = &cleanup_block_load_pc; | |
8271 | } | |
8272 | ||
8273 | return 0; | |
8274 | } | |
8275 | ||
8276 | static void | |
8277 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8278 | struct regcache *regs, | |
8279 | struct displaced_step_closure *dsc) | |
8280 | { | |
8281 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
8282 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
8283 | int err = 0; | |
8284 | ||
8285 | /* 16-bit thumb instructions. */ | |
8286 | switch (op_bit_12_15) | |
8287 | { | |
8288 | /* Shift (imme), add, subtract, move and compare. */ | |
8289 | case 0: case 1: case 2: case 3: | |
8290 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8291 | "shift/add/sub/mov/cmp", | |
8292 | dsc); | |
8293 | break; | |
8294 | case 4: | |
8295 | switch (op_bit_10_11) | |
8296 | { | |
8297 | case 0: /* Data-processing */ | |
8298 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8299 | "data-processing", | |
8300 | dsc); | |
8301 | break; | |
8302 | case 1: /* Special data instructions and branch and exchange. */ | |
8303 | { | |
8304 | unsigned short op = bits (insn1, 7, 9); | |
8305 | if (op == 6 || op == 7) /* BX or BLX */ | |
8306 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
8307 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
8308 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
8309 | else | |
8310 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
8311 | dsc); | |
8312 | } | |
8313 | break; | |
8314 | default: /* LDR (literal) */ | |
8315 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
8316 | } | |
8317 | break; | |
8318 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
8319 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
8320 | break; | |
8321 | case 10: | |
8322 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
8323 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
8324 | else /* Generate SP-relative address */ | |
8325 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
8326 | break; | |
8327 | case 11: /* Misc 16-bit instructions */ | |
8328 | { | |
8329 | switch (bits (insn1, 8, 11)) | |
8330 | { | |
8331 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
8332 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
8333 | break; | |
8334 | case 12: case 13: /* POP */ | |
8335 | if (bit (insn1, 8)) /* PC is in register list. */ | |
8336 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
8337 | else | |
8338 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
8339 | break; | |
8340 | case 15: /* If-Then, and hints */ | |
8341 | if (bits (insn1, 0, 3)) | |
8342 | /* If-Then makes up to four following instructions conditional. | |
8343 | IT instruction itself is not conditional, so handle it as a | |
8344 | common unmodified instruction. */ | |
8345 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
8346 | dsc); | |
8347 | else | |
8348 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
8349 | break; | |
8350 | default: | |
8351 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
8352 | } | |
8353 | } | |
8354 | break; | |
8355 | case 12: | |
8356 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
8357 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
8358 | else /* Load multiple registers */ | |
8359 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
8360 | break; | |
8361 | case 13: /* Conditional branch and supervisor call */ | |
8362 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
8363 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8364 | else | |
8365 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
8366 | break; | |
8367 | case 14: /* Unconditional branch */ | |
8368 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8369 | break; | |
8370 | default: | |
8371 | err = 1; | |
8372 | } | |
8373 | ||
8374 | if (err) | |
8375 | internal_error (__FILE__, __LINE__, | |
8376 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
8377 | } | |
8378 | ||
8379 | static int | |
8380 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
8381 | uint16_t insn1, uint16_t insn2, | |
8382 | struct regcache *regs, | |
8383 | struct displaced_step_closure *dsc) | |
8384 | { | |
8385 | int rt = bits (insn2, 12, 15); | |
8386 | int rn = bits (insn1, 0, 3); | |
8387 | int op1 = bits (insn1, 7, 8); | |
8388 | int err = 0; | |
8389 | ||
8390 | switch (bits (insn1, 5, 6)) | |
8391 | { | |
8392 | case 0: /* Load byte and memory hints */ | |
8393 | if (rt == 0xf) /* PLD/PLI */ | |
8394 | { | |
8395 | if (rn == 0xf) | |
8396 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
8397 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
8398 | else | |
8399 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8400 | "pli/pld", dsc); | |
8401 | } | |
8402 | else | |
8403 | { | |
8404 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
8405 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8406 | 1); | |
8407 | else | |
8408 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8409 | "ldrb{reg, immediate}/ldrbt", | |
8410 | dsc); | |
8411 | } | |
8412 | ||
8413 | break; | |
8414 | case 1: /* Load halfword and memory hints. */ | |
8415 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
8416 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8417 | "pld/unalloc memhint", dsc); | |
8418 | else | |
8419 | { | |
8420 | if (rn == 0xf) | |
8421 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8422 | 2); | |
8423 | else | |
8424 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8425 | "ldrh/ldrht", dsc); | |
8426 | } | |
8427 | break; | |
8428 | case 2: /* Load word */ | |
8429 | { | |
8430 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
8431 | ||
8432 | if (rn == 0xf) | |
8433 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
8434 | else if (op1 == 0x1) /* Encoding T3 */ | |
8435 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
8436 | 0, 1); | |
8437 | else /* op1 == 0x0 */ | |
8438 | { | |
8439 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
8440 | /* LDR (immediate) */ | |
8441 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8442 | dsc, bit (insn2, 8), 1); | |
8443 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
8444 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8445 | "ldrt", dsc); | |
8446 | else | |
8447 | /* LDR (register) */ | |
8448 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8449 | dsc, 0, 0); | |
8450 | } | |
8451 | break; | |
8452 | } | |
8453 | default: | |
8454 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
8455 | break; | |
8456 | } | |
8457 | return 0; | |
8458 | } | |
8459 | ||
8460 | static void | |
8461 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8462 | uint16_t insn2, struct regcache *regs, | |
8463 | struct displaced_step_closure *dsc) | |
8464 | { | |
8465 | int err = 0; | |
8466 | unsigned short op = bit (insn2, 15); | |
8467 | unsigned int op1 = bits (insn1, 11, 12); | |
8468 | ||
8469 | switch (op1) | |
8470 | { | |
8471 | case 1: | |
8472 | { | |
8473 | switch (bits (insn1, 9, 10)) | |
8474 | { | |
8475 | case 0: | |
8476 | if (bit (insn1, 6)) | |
8477 | { | |
8478 | /* Load/store {dual, execlusive}, table branch. */ | |
8479 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 | |
8480 | && bits (insn2, 5, 7) == 0) | |
8481 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
8482 | dsc); | |
8483 | else | |
8484 | /* PC is not allowed to use in load/store {dual, exclusive} | |
8485 | instructions. */ | |
8486 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8487 | "load/store dual/ex", dsc); | |
8488 | } | |
8489 | else /* load/store multiple */ | |
8490 | { | |
8491 | switch (bits (insn1, 7, 8)) | |
8492 | { | |
8493 | case 0: case 3: /* SRS, RFE */ | |
8494 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8495 | "srs/rfe", dsc); | |
8496 | break; | |
8497 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
8498 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
8499 | break; | |
8500 | } | |
8501 | } | |
8502 | break; | |
8503 | ||
8504 | case 1: | |
8505 | /* Data-processing (shift register). */ | |
8506 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
8507 | dsc); | |
8508 | break; | |
8509 | default: /* Coprocessor instructions. */ | |
8510 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8511 | break; | |
8512 | } | |
8513 | break; | |
8514 | } | |
8515 | case 2: /* op1 = 2 */ | |
8516 | if (op) /* Branch and misc control. */ | |
8517 | { | |
8518 | if (bit (insn2, 14) /* BLX/BL */ | |
8519 | || bit (insn2, 12) /* Unconditional branch */ | |
8520 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
8521 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
8522 | else | |
8523 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8524 | "misc ctrl", dsc); | |
8525 | } | |
8526 | else | |
8527 | { | |
8528 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
8529 | { | |
8530 | int op = bits (insn1, 4, 8); | |
8531 | int rn = bits (insn1, 0, 3); | |
8532 | if ((op == 0 || op == 0xa) && rn == 0xf) | |
8533 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, | |
8534 | regs, dsc); | |
8535 | else | |
8536 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8537 | "dp/pb", dsc); | |
8538 | } | |
8539 | else /* Data processing (modified immeidate) */ | |
8540 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8541 | "dp/mi", dsc); | |
8542 | } | |
8543 | break; | |
8544 | case 3: /* op1 = 3 */ | |
8545 | switch (bits (insn1, 9, 10)) | |
8546 | { | |
8547 | case 0: | |
8548 | if (bit (insn1, 4)) | |
8549 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
8550 | regs, dsc); | |
8551 | else /* NEON Load/Store and Store single data item */ | |
8552 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8553 | "neon elt/struct load/store", | |
8554 | dsc); | |
8555 | break; | |
8556 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
8557 | switch (bits (insn1, 7, 8)) | |
8558 | { | |
8559 | case 0: case 1: /* Data processing (register) */ | |
8560 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8561 | "dp(reg)", dsc); | |
8562 | break; | |
8563 | case 2: /* Multiply and absolute difference */ | |
8564 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8565 | "mul/mua/diff", dsc); | |
8566 | break; | |
8567 | case 3: /* Long multiply and divide */ | |
8568 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8569 | "lmul/lmua", dsc); | |
8570 | break; | |
8571 | } | |
8572 | break; | |
8573 | default: /* Coprocessor instructions */ | |
8574 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8575 | break; | |
8576 | } | |
8577 | break; | |
8578 | default: | |
8579 | err = 1; | |
8580 | } | |
8581 | ||
8582 | if (err) | |
8583 | internal_error (__FILE__, __LINE__, | |
8584 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
8585 | ||
8586 | } | |
8587 | ||
b434a28f YQ |
8588 | static void |
8589 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
8590 | CORE_ADDR to, struct regcache *regs, | |
8591 | struct displaced_step_closure *dsc) | |
8592 | { | |
34518530 YQ |
8593 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8594 | uint16_t insn1 | |
8595 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
8596 | ||
8597 | if (debug_displaced) | |
8598 | fprintf_unfiltered (gdb_stdlog, "displaced: process thumb insn %.4x " | |
8599 | "at %.8lx\n", insn1, (unsigned long) from); | |
8600 | ||
8601 | dsc->is_thumb = 1; | |
8602 | dsc->insn_size = thumb_insn_size (insn1); | |
8603 | if (thumb_insn_size (insn1) == 4) | |
8604 | { | |
8605 | uint16_t insn2 | |
8606 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
8607 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
8608 | } | |
8609 | else | |
8610 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
8611 | } |
8612 | ||
cca44b1b | 8613 | void |
b434a28f YQ |
8614 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
8615 | CORE_ADDR to, struct regcache *regs, | |
cca44b1b JB |
8616 | struct displaced_step_closure *dsc) |
8617 | { | |
8618 | int err = 0; | |
b434a28f YQ |
8619 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8620 | uint32_t insn; | |
cca44b1b JB |
8621 | |
8622 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
8623 | here and override below if/when necessary. */ | |
8624 | dsc->numinsns = 1; | |
8625 | dsc->insn_addr = from; | |
8626 | dsc->scratch_base = to; | |
8627 | dsc->cleanup = NULL; | |
8628 | dsc->wrote_to_pc = 0; | |
8629 | ||
b434a28f YQ |
8630 | if (!displaced_in_arm_mode (regs)) |
8631 | return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc); | |
8632 | ||
4db71c0b YQ |
8633 | dsc->is_thumb = 0; |
8634 | dsc->insn_size = 4; | |
b434a28f YQ |
8635 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
8636 | if (debug_displaced) | |
8637 | fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " | |
8638 | "at %.8lx\n", (unsigned long) insn, | |
8639 | (unsigned long) from); | |
8640 | ||
cca44b1b | 8641 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 8642 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8643 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
8644 | { | |
8645 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 8646 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8647 | break; |
8648 | ||
8649 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 8650 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8651 | break; |
8652 | ||
8653 | case 0x7: | |
7ff120b4 | 8654 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
8655 | break; |
8656 | ||
8657 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 8658 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8659 | break; |
8660 | ||
8661 | case 0xc: case 0xd: case 0xe: case 0xf: | |
7ff120b4 | 8662 | err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc); |
cca44b1b JB |
8663 | break; |
8664 | } | |
8665 | ||
8666 | if (err) | |
8667 | internal_error (__FILE__, __LINE__, | |
8668 | _("arm_process_displaced_insn: Instruction decode error")); | |
8669 | } | |
8670 | ||
8671 | /* Actually set up the scratch space for a displaced instruction. */ | |
8672 | ||
8673 | void | |
8674 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
8675 | CORE_ADDR to, struct displaced_step_closure *dsc) | |
8676 | { | |
8677 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4db71c0b | 8678 | unsigned int i, len, offset; |
cca44b1b | 8679 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 8680 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 8681 | const gdb_byte *bkp_insn; |
cca44b1b | 8682 | |
4db71c0b | 8683 | offset = 0; |
cca44b1b JB |
8684 | /* Poke modified instruction(s). */ |
8685 | for (i = 0; i < dsc->numinsns; i++) | |
8686 | { | |
8687 | if (debug_displaced) | |
4db71c0b YQ |
8688 | { |
8689 | fprintf_unfiltered (gdb_stdlog, "displaced: writing insn "); | |
8690 | if (size == 4) | |
8691 | fprintf_unfiltered (gdb_stdlog, "%.8lx", | |
8692 | dsc->modinsn[i]); | |
8693 | else if (size == 2) | |
8694 | fprintf_unfiltered (gdb_stdlog, "%.4x", | |
8695 | (unsigned short)dsc->modinsn[i]); | |
8696 | ||
8697 | fprintf_unfiltered (gdb_stdlog, " at %.8lx\n", | |
8698 | (unsigned long) to + offset); | |
8699 | ||
8700 | } | |
8701 | write_memory_unsigned_integer (to + offset, size, | |
8702 | byte_order_for_code, | |
cca44b1b | 8703 | dsc->modinsn[i]); |
4db71c0b YQ |
8704 | offset += size; |
8705 | } | |
8706 | ||
8707 | /* Choose the correct breakpoint instruction. */ | |
8708 | if (dsc->is_thumb) | |
8709 | { | |
8710 | bkp_insn = tdep->thumb_breakpoint; | |
8711 | len = tdep->thumb_breakpoint_size; | |
8712 | } | |
8713 | else | |
8714 | { | |
8715 | bkp_insn = tdep->arm_breakpoint; | |
8716 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
8717 | } |
8718 | ||
8719 | /* Put breakpoint afterwards. */ | |
4db71c0b | 8720 | write_memory (to + offset, bkp_insn, len); |
cca44b1b JB |
8721 | |
8722 | if (debug_displaced) | |
8723 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
8724 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
8725 | } | |
8726 | ||
8727 | /* Entry point for copying an instruction into scratch space for displaced | |
8728 | stepping. */ | |
8729 | ||
8730 | struct displaced_step_closure * | |
8731 | arm_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
8732 | CORE_ADDR from, CORE_ADDR to, | |
8733 | struct regcache *regs) | |
8734 | { | |
8735 | struct displaced_step_closure *dsc | |
8736 | = xmalloc (sizeof (struct displaced_step_closure)); | |
b434a28f | 8737 | arm_process_displaced_insn (gdbarch, from, to, regs, dsc); |
cca44b1b JB |
8738 | arm_displaced_init_closure (gdbarch, from, to, dsc); |
8739 | ||
8740 | return dsc; | |
8741 | } | |
8742 | ||
8743 | /* Entry point for cleaning things up after a displaced instruction has been | |
8744 | single-stepped. */ | |
8745 | ||
8746 | void | |
8747 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
8748 | struct displaced_step_closure *dsc, | |
8749 | CORE_ADDR from, CORE_ADDR to, | |
8750 | struct regcache *regs) | |
8751 | { | |
8752 | if (dsc->cleanup) | |
8753 | dsc->cleanup (gdbarch, regs, dsc); | |
8754 | ||
8755 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
8756 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
8757 | dsc->insn_addr + dsc->insn_size); | |
8758 | ||
cca44b1b JB |
8759 | } |
8760 | ||
8761 | #include "bfd-in2.h" | |
8762 | #include "libcoff.h" | |
8763 | ||
8764 | static int | |
8765 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
8766 | { | |
9779414d DJ |
8767 | struct gdbarch *gdbarch = info->application_data; |
8768 | ||
8769 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
8770 | { |
8771 | static asymbol *asym; | |
8772 | static combined_entry_type ce; | |
8773 | static struct coff_symbol_struct csym; | |
8774 | static struct bfd fake_bfd; | |
8775 | static bfd_target fake_target; | |
8776 | ||
8777 | if (csym.native == NULL) | |
8778 | { | |
8779 | /* Create a fake symbol vector containing a Thumb symbol. | |
8780 | This is solely so that the code in print_insn_little_arm() | |
8781 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
8782 | the presence of a Thumb symbol and switch to decoding | |
8783 | Thumb instructions. */ | |
8784 | ||
8785 | fake_target.flavour = bfd_target_coff_flavour; | |
8786 | fake_bfd.xvec = &fake_target; | |
8787 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
8788 | csym.native = &ce; | |
8789 | csym.symbol.the_bfd = &fake_bfd; | |
8790 | csym.symbol.name = "fake"; | |
8791 | asym = (asymbol *) & csym; | |
8792 | } | |
8793 | ||
8794 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
8795 | info->symbols = &asym; | |
8796 | } | |
8797 | else | |
8798 | info->symbols = NULL; | |
8799 | ||
8800 | if (info->endian == BFD_ENDIAN_BIG) | |
8801 | return print_insn_big_arm (memaddr, info); | |
8802 | else | |
8803 | return print_insn_little_arm (memaddr, info); | |
8804 | } | |
8805 | ||
8806 | /* The following define instruction sequences that will cause ARM | |
8807 | cpu's to take an undefined instruction trap. These are used to | |
8808 | signal a breakpoint to GDB. | |
8809 | ||
8810 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
8811 | modes. A different instruction is required for each mode. The ARM | |
8812 | cpu's can also be big or little endian. Thus four different | |
8813 | instructions are needed to support all cases. | |
8814 | ||
8815 | Note: ARMv4 defines several new instructions that will take the | |
8816 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
8817 | not in fact add the new instructions. The new undefined | |
8818 | instructions in ARMv4 are all instructions that had no defined | |
8819 | behaviour in earlier chips. There is no guarantee that they will | |
8820 | raise an exception, but may be treated as NOP's. In practice, it | |
8821 | may only safe to rely on instructions matching: | |
8822 | ||
8823 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
8824 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
8825 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
8826 | ||
0963b4bd | 8827 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
8828 | following use a condition predicate of ALWAYS so it is always TRUE. |
8829 | ||
8830 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
8831 | and NetBSD all use a software interrupt rather than an undefined | |
8832 | instruction to force a trap. This can be handled by by the | |
8833 | abi-specific code during establishment of the gdbarch vector. */ | |
8834 | ||
8835 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
8836 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
8837 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
8838 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
8839 | ||
948f8e3d PA |
8840 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
8841 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
8842 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
8843 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b JB |
8844 | |
8845 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses | |
8846 | the program counter value to determine whether a 16-bit or 32-bit | |
8847 | breakpoint should be used. It returns a pointer to a string of | |
8848 | bytes that encode a breakpoint instruction, stores the length of | |
8849 | the string to *lenptr, and adjusts the program counter (if | |
8850 | necessary) to point to the actual memory location where the | |
8851 | breakpoint should be inserted. */ | |
8852 | ||
8853 | static const unsigned char * | |
8854 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) | |
8855 | { | |
8856 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
177321bd | 8857 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 8858 | |
9779414d | 8859 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
8860 | { |
8861 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
8862 | |
8863 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
8864 | check whether we are replacing a 32-bit instruction. */ | |
8865 | if (tdep->thumb2_breakpoint != NULL) | |
8866 | { | |
8867 | gdb_byte buf[2]; | |
8868 | if (target_read_memory (*pcptr, buf, 2) == 0) | |
8869 | { | |
8870 | unsigned short inst1; | |
8871 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
db24da6d | 8872 | if (thumb_insn_size (inst1) == 4) |
177321bd DJ |
8873 | { |
8874 | *lenptr = tdep->thumb2_breakpoint_size; | |
8875 | return tdep->thumb2_breakpoint; | |
8876 | } | |
8877 | } | |
8878 | } | |
8879 | ||
cca44b1b JB |
8880 | *lenptr = tdep->thumb_breakpoint_size; |
8881 | return tdep->thumb_breakpoint; | |
8882 | } | |
8883 | else | |
8884 | { | |
8885 | *lenptr = tdep->arm_breakpoint_size; | |
8886 | return tdep->arm_breakpoint; | |
8887 | } | |
8888 | } | |
8889 | ||
177321bd DJ |
8890 | static void |
8891 | arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
8892 | int *kindptr) | |
8893 | { | |
177321bd DJ |
8894 | arm_breakpoint_from_pc (gdbarch, pcptr, kindptr); |
8895 | ||
9779414d | 8896 | if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4) |
177321bd DJ |
8897 | /* The documented magic value for a 32-bit Thumb-2 breakpoint, so |
8898 | that this is not confused with a 32-bit ARM breakpoint. */ | |
8899 | *kindptr = 3; | |
8900 | } | |
8901 | ||
cca44b1b JB |
8902 | /* Extract from an array REGBUF containing the (raw) register state a |
8903 | function return value of type TYPE, and copy that, in virtual | |
8904 | format, into VALBUF. */ | |
8905 | ||
8906 | static void | |
8907 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
8908 | gdb_byte *valbuf) | |
8909 | { | |
8910 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
8911 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8912 | ||
8913 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
8914 | { | |
8915 | switch (gdbarch_tdep (gdbarch)->fp_model) | |
8916 | { | |
8917 | case ARM_FLOAT_FPA: | |
8918 | { | |
8919 | /* The value is in register F0 in internal format. We need to | |
8920 | extract the raw value and then convert it to the desired | |
8921 | internal type. */ | |
8922 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; | |
8923 | ||
8924 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
8925 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
8926 | valbuf, gdbarch_byte_order (gdbarch)); | |
8927 | } | |
8928 | break; | |
8929 | ||
8930 | case ARM_FLOAT_SOFT_FPA: | |
8931 | case ARM_FLOAT_SOFT_VFP: | |
8932 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
8933 | not using the VFP ABI code. */ | |
8934 | case ARM_FLOAT_VFP: | |
8935 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); | |
8936 | if (TYPE_LENGTH (type) > 4) | |
8937 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
8938 | valbuf + INT_REGISTER_SIZE); | |
8939 | break; | |
8940 | ||
8941 | default: | |
0963b4bd MS |
8942 | internal_error (__FILE__, __LINE__, |
8943 | _("arm_extract_return_value: " | |
8944 | "Floating point model not supported")); | |
cca44b1b JB |
8945 | break; |
8946 | } | |
8947 | } | |
8948 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
8949 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
8950 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
8951 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
8952 | || TYPE_CODE (type) == TYPE_CODE_REF | |
8953 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
8954 | { | |
b021a221 MS |
8955 | /* If the type is a plain integer, then the access is |
8956 | straight-forward. Otherwise we have to play around a bit | |
8957 | more. */ | |
cca44b1b JB |
8958 | int len = TYPE_LENGTH (type); |
8959 | int regno = ARM_A1_REGNUM; | |
8960 | ULONGEST tmp; | |
8961 | ||
8962 | while (len > 0) | |
8963 | { | |
8964 | /* By using store_unsigned_integer we avoid having to do | |
8965 | anything special for small big-endian values. */ | |
8966 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
8967 | store_unsigned_integer (valbuf, | |
8968 | (len > INT_REGISTER_SIZE | |
8969 | ? INT_REGISTER_SIZE : len), | |
8970 | byte_order, tmp); | |
8971 | len -= INT_REGISTER_SIZE; | |
8972 | valbuf += INT_REGISTER_SIZE; | |
8973 | } | |
8974 | } | |
8975 | else | |
8976 | { | |
8977 | /* For a structure or union the behaviour is as if the value had | |
8978 | been stored to word-aligned memory and then loaded into | |
8979 | registers with 32-bit load instruction(s). */ | |
8980 | int len = TYPE_LENGTH (type); | |
8981 | int regno = ARM_A1_REGNUM; | |
8982 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; | |
8983 | ||
8984 | while (len > 0) | |
8985 | { | |
8986 | regcache_cooked_read (regs, regno++, tmpbuf); | |
8987 | memcpy (valbuf, tmpbuf, | |
8988 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); | |
8989 | len -= INT_REGISTER_SIZE; | |
8990 | valbuf += INT_REGISTER_SIZE; | |
8991 | } | |
8992 | } | |
8993 | } | |
8994 | ||
8995 | ||
8996 | /* Will a function return an aggregate type in memory or in a | |
8997 | register? Return 0 if an aggregate type can be returned in a | |
8998 | register, 1 if it must be returned in memory. */ | |
8999 | ||
9000 | static int | |
9001 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
9002 | { | |
9003 | int nRc; | |
9004 | enum type_code code; | |
9005 | ||
9006 | CHECK_TYPEDEF (type); | |
9007 | ||
9008 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
9009 | registers. For an aggregate type to be integer like, its size | |
9010 | must be less than or equal to INT_REGISTER_SIZE and the | |
9011 | offset of each addressable subfield must be zero. Note that bit | |
9012 | fields are not addressable, and all addressable subfields of | |
9013 | unions always start at offset zero. | |
9014 | ||
9015 | This function is based on the behaviour of GCC 2.95.1. | |
9016 | See: gcc/arm.c: arm_return_in_memory() for details. | |
9017 | ||
9018 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
9019 | parameters correctly for a function returning the following | |
9020 | structure: struct { float f;}; This should be returned in memory, | |
9021 | not a register. Richard Earnshaw sent me a patch, but I do not | |
9022 | know of any way to detect if a function like the above has been | |
9023 | compiled with the correct calling convention. */ | |
9024 | ||
9025 | /* All aggregate types that won't fit in a register must be returned | |
9026 | in memory. */ | |
9027 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) | |
9028 | { | |
9029 | return 1; | |
9030 | } | |
9031 | ||
9032 | /* The AAPCS says all aggregates not larger than a word are returned | |
9033 | in a register. */ | |
9034 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
9035 | return 0; | |
9036 | ||
9037 | /* The only aggregate types that can be returned in a register are | |
9038 | structs and unions. Arrays must be returned in memory. */ | |
9039 | code = TYPE_CODE (type); | |
9040 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
9041 | { | |
9042 | return 1; | |
9043 | } | |
9044 | ||
9045 | /* Assume all other aggregate types can be returned in a register. | |
9046 | Run a check for structures, unions and arrays. */ | |
9047 | nRc = 0; | |
9048 | ||
9049 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
9050 | { | |
9051 | int i; | |
9052 | /* Need to check if this struct/union is "integer" like. For | |
9053 | this to be true, its size must be less than or equal to | |
9054 | INT_REGISTER_SIZE and the offset of each addressable | |
9055 | subfield must be zero. Note that bit fields are not | |
9056 | addressable, and unions always start at offset zero. If any | |
9057 | of the subfields is a floating point type, the struct/union | |
9058 | cannot be an integer type. */ | |
9059 | ||
9060 | /* For each field in the object, check: | |
9061 | 1) Is it FP? --> yes, nRc = 1; | |
67255d04 RE |
9062 | 2) Is it addressable (bitpos != 0) and |
9063 | not packed (bitsize == 0)? | |
9064 | --> yes, nRc = 1 | |
9065 | */ | |
9066 | ||
9067 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
9068 | { | |
9069 | enum type_code field_type_code; | |
0963b4bd MS |
9070 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, |
9071 | i))); | |
67255d04 RE |
9072 | |
9073 | /* Is it a floating point type field? */ | |
9074 | if (field_type_code == TYPE_CODE_FLT) | |
9075 | { | |
9076 | nRc = 1; | |
9077 | break; | |
9078 | } | |
9079 | ||
9080 | /* If bitpos != 0, then we have to care about it. */ | |
9081 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
9082 | { | |
9083 | /* Bitfields are not addressable. If the field bitsize is | |
9084 | zero, then the field is not packed. Hence it cannot be | |
9085 | a bitfield or any other packed type. */ | |
9086 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
9087 | { | |
9088 | nRc = 1; | |
9089 | break; | |
9090 | } | |
9091 | } | |
9092 | } | |
9093 | } | |
9094 | ||
9095 | return nRc; | |
9096 | } | |
9097 | ||
34e8f22d RE |
9098 | /* Write into appropriate registers a function return value of type |
9099 | TYPE, given in virtual format. */ | |
9100 | ||
9101 | static void | |
b508a996 | 9102 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 9103 | const gdb_byte *valbuf) |
34e8f22d | 9104 | { |
be8626e0 | 9105 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 9106 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 9107 | |
34e8f22d RE |
9108 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
9109 | { | |
e362b510 | 9110 | gdb_byte buf[MAX_REGISTER_SIZE]; |
34e8f22d | 9111 | |
be8626e0 | 9112 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
9113 | { |
9114 | case ARM_FLOAT_FPA: | |
9115 | ||
be8626e0 MD |
9116 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
9117 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 9118 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
9119 | break; |
9120 | ||
fd50bc42 | 9121 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 9122 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
9123 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
9124 | not using the VFP ABI code. */ | |
9125 | case ARM_FLOAT_VFP: | |
b508a996 RE |
9126 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
9127 | if (TYPE_LENGTH (type) > 4) | |
9128 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 9129 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
9130 | break; |
9131 | ||
9132 | default: | |
9b20d036 MS |
9133 | internal_error (__FILE__, __LINE__, |
9134 | _("arm_store_return_value: Floating " | |
9135 | "point model not supported")); | |
08216dd7 RE |
9136 | break; |
9137 | } | |
34e8f22d | 9138 | } |
b508a996 RE |
9139 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
9140 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
9141 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
9142 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
9143 | || TYPE_CODE (type) == TYPE_CODE_REF | |
9144 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
9145 | { | |
9146 | if (TYPE_LENGTH (type) <= 4) | |
9147 | { | |
9148 | /* Values of one word or less are zero/sign-extended and | |
9149 | returned in r0. */ | |
7a5ea0d4 | 9150 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
9151 | LONGEST val = unpack_long (type, valbuf); |
9152 | ||
e17a4113 | 9153 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
b508a996 RE |
9154 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
9155 | } | |
9156 | else | |
9157 | { | |
9158 | /* Integral values greater than one word are stored in consecutive | |
9159 | registers starting with r0. This will always be a multiple of | |
9160 | the regiser size. */ | |
9161 | int len = TYPE_LENGTH (type); | |
9162 | int regno = ARM_A1_REGNUM; | |
9163 | ||
9164 | while (len > 0) | |
9165 | { | |
9166 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
9167 | len -= INT_REGISTER_SIZE; |
9168 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
9169 | } |
9170 | } | |
9171 | } | |
34e8f22d | 9172 | else |
b508a996 RE |
9173 | { |
9174 | /* For a structure or union the behaviour is as if the value had | |
9175 | been stored to word-aligned memory and then loaded into | |
9176 | registers with 32-bit load instruction(s). */ | |
9177 | int len = TYPE_LENGTH (type); | |
9178 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 9179 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
9180 | |
9181 | while (len > 0) | |
9182 | { | |
9183 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 9184 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 9185 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
9186 | len -= INT_REGISTER_SIZE; |
9187 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
9188 | } |
9189 | } | |
34e8f22d RE |
9190 | } |
9191 | ||
2af48f68 PB |
9192 | |
9193 | /* Handle function return values. */ | |
9194 | ||
9195 | static enum return_value_convention | |
6a3a010b | 9196 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
9197 | struct type *valtype, struct regcache *regcache, |
9198 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 9199 | { |
7c00367c | 9200 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 9201 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
9202 | enum arm_vfp_cprc_base_type vfp_base_type; |
9203 | int vfp_base_count; | |
9204 | ||
9205 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
9206 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
9207 | { | |
9208 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
9209 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
9210 | int i; | |
9211 | for (i = 0; i < vfp_base_count; i++) | |
9212 | { | |
58d6951d DJ |
9213 | if (reg_char == 'q') |
9214 | { | |
9215 | if (writebuf) | |
9216 | arm_neon_quad_write (gdbarch, regcache, i, | |
9217 | writebuf + i * unit_length); | |
9218 | ||
9219 | if (readbuf) | |
9220 | arm_neon_quad_read (gdbarch, regcache, i, | |
9221 | readbuf + i * unit_length); | |
9222 | } | |
9223 | else | |
9224 | { | |
9225 | char name_buf[4]; | |
9226 | int regnum; | |
9227 | ||
8c042590 | 9228 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
9229 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9230 | strlen (name_buf)); | |
9231 | if (writebuf) | |
9232 | regcache_cooked_write (regcache, regnum, | |
9233 | writebuf + i * unit_length); | |
9234 | if (readbuf) | |
9235 | regcache_cooked_read (regcache, regnum, | |
9236 | readbuf + i * unit_length); | |
9237 | } | |
90445bd3 DJ |
9238 | } |
9239 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9240 | } | |
7c00367c | 9241 | |
2af48f68 PB |
9242 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
9243 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
9244 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
9245 | { | |
7c00367c MK |
9246 | if (tdep->struct_return == pcc_struct_return |
9247 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
9248 | return RETURN_VALUE_STRUCT_CONVENTION; |
9249 | } | |
9250 | ||
7052e42c UW |
9251 | /* AAPCS returns complex types longer than a register in memory. */ |
9252 | if (tdep->arm_abi != ARM_ABI_APCS | |
9253 | && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX | |
9254 | && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE) | |
9255 | return RETURN_VALUE_STRUCT_CONVENTION; | |
9256 | ||
2af48f68 PB |
9257 | if (writebuf) |
9258 | arm_store_return_value (valtype, regcache, writebuf); | |
9259 | ||
9260 | if (readbuf) | |
9261 | arm_extract_return_value (valtype, regcache, readbuf); | |
9262 | ||
9263 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9264 | } | |
9265 | ||
9266 | ||
9df628e0 | 9267 | static int |
60ade65d | 9268 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 9269 | { |
e17a4113 UW |
9270 | struct gdbarch *gdbarch = get_frame_arch (frame); |
9271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9272 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 9273 | CORE_ADDR jb_addr; |
e362b510 | 9274 | gdb_byte buf[INT_REGISTER_SIZE]; |
9df628e0 | 9275 | |
60ade65d | 9276 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
9277 | |
9278 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 9279 | INT_REGISTER_SIZE)) |
9df628e0 RE |
9280 | return 0; |
9281 | ||
e17a4113 | 9282 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
9283 | return 1; |
9284 | } | |
9285 | ||
faa95490 DJ |
9286 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
9287 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
9288 | |
9289 | CORE_ADDR | |
52f729a7 | 9290 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 9291 | { |
2c02bd72 | 9292 | const char *name; |
faa95490 | 9293 | int namelen; |
c906108c SS |
9294 | CORE_ADDR start_addr; |
9295 | ||
9296 | /* Find the starting address and name of the function containing the PC. */ | |
9297 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
9298 | { |
9299 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
9300 | check here. */ | |
9301 | start_addr = arm_skip_bx_reg (frame, pc); | |
9302 | if (start_addr != 0) | |
9303 | return start_addr; | |
9304 | ||
9305 | return 0; | |
9306 | } | |
c906108c | 9307 | |
faa95490 DJ |
9308 | /* If PC is in a Thumb call or return stub, return the address of the |
9309 | target PC, which is in a register. The thunk functions are called | |
9310 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
9311 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
9312 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
9313 | if (startswith (name, "_call_via_") |
9314 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 9315 | { |
ed9a39eb JM |
9316 | /* Use the name suffix to determine which register contains the |
9317 | target PC. */ | |
c5aa993b JM |
9318 | static char *table[15] = |
9319 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
9320 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
9321 | }; | |
c906108c | 9322 | int regno; |
faa95490 | 9323 | int offset = strlen (name) - 2; |
c906108c SS |
9324 | |
9325 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 9326 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 9327 | return get_frame_register_unsigned (frame, regno); |
c906108c | 9328 | } |
ed9a39eb | 9329 | |
faa95490 DJ |
9330 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
9331 | non-interworking calls to foo. We could decode the stubs | |
9332 | to find the target but it's easier to use the symbol table. */ | |
9333 | namelen = strlen (name); | |
9334 | if (name[0] == '_' && name[1] == '_' | |
9335 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 9336 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 9337 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 9338 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
9339 | { |
9340 | char *target_name; | |
9341 | int target_len = namelen - 2; | |
3b7344d5 | 9342 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
9343 | struct objfile *objfile; |
9344 | struct obj_section *sec; | |
9345 | ||
9346 | if (name[namelen - 1] == 'b') | |
9347 | target_len -= strlen ("_from_thumb"); | |
9348 | else | |
9349 | target_len -= strlen ("_from_arm"); | |
9350 | ||
9351 | target_name = alloca (target_len + 1); | |
9352 | memcpy (target_name, name + 2, target_len); | |
9353 | target_name[target_len] = '\0'; | |
9354 | ||
9355 | sec = find_pc_section (pc); | |
9356 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
9357 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 9358 | if (minsym.minsym != NULL) |
77e371c0 | 9359 | return BMSYMBOL_VALUE_ADDRESS (minsym); |
faa95490 DJ |
9360 | else |
9361 | return 0; | |
9362 | } | |
9363 | ||
c5aa993b | 9364 | return 0; /* not a stub */ |
c906108c SS |
9365 | } |
9366 | ||
afd7eef0 RE |
9367 | static void |
9368 | set_arm_command (char *args, int from_tty) | |
9369 | { | |
edefbb7c AC |
9370 | printf_unfiltered (_("\ |
9371 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
9372 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
9373 | } | |
9374 | ||
9375 | static void | |
9376 | show_arm_command (char *args, int from_tty) | |
9377 | { | |
26304000 | 9378 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
9379 | } |
9380 | ||
28e97307 DJ |
9381 | static void |
9382 | arm_update_current_architecture (void) | |
fd50bc42 | 9383 | { |
28e97307 | 9384 | struct gdbarch_info info; |
fd50bc42 | 9385 | |
28e97307 | 9386 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 9387 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 9388 | return; |
fd50bc42 | 9389 | |
28e97307 DJ |
9390 | /* Update the architecture. */ |
9391 | gdbarch_info_init (&info); | |
fd50bc42 | 9392 | |
28e97307 | 9393 | if (!gdbarch_update_p (info)) |
9b20d036 | 9394 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
9395 | } |
9396 | ||
9397 | static void | |
9398 | set_fp_model_sfunc (char *args, int from_tty, | |
9399 | struct cmd_list_element *c) | |
9400 | { | |
570dc176 | 9401 | int fp_model; |
fd50bc42 RE |
9402 | |
9403 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
9404 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
9405 | { | |
9406 | arm_fp_model = fp_model; | |
9407 | break; | |
9408 | } | |
9409 | ||
9410 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 9411 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
9412 | current_fp_model); |
9413 | ||
28e97307 | 9414 | arm_update_current_architecture (); |
fd50bc42 RE |
9415 | } |
9416 | ||
9417 | static void | |
08546159 AC |
9418 | show_fp_model (struct ui_file *file, int from_tty, |
9419 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 9420 | { |
f5656ead | 9421 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
fd50bc42 | 9422 | |
28e97307 | 9423 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 9424 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
9425 | fprintf_filtered (file, _("\ |
9426 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
9427 | fp_model_strings[tdep->fp_model]); | |
9428 | else | |
9429 | fprintf_filtered (file, _("\ | |
9430 | The current ARM floating point model is \"%s\".\n"), | |
9431 | fp_model_strings[arm_fp_model]); | |
9432 | } | |
9433 | ||
9434 | static void | |
9435 | arm_set_abi (char *args, int from_tty, | |
9436 | struct cmd_list_element *c) | |
9437 | { | |
570dc176 | 9438 | int arm_abi; |
28e97307 DJ |
9439 | |
9440 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
9441 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
9442 | { | |
9443 | arm_abi_global = arm_abi; | |
9444 | break; | |
9445 | } | |
9446 | ||
9447 | if (arm_abi == ARM_ABI_LAST) | |
9448 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
9449 | arm_abi_string); | |
9450 | ||
9451 | arm_update_current_architecture (); | |
9452 | } | |
9453 | ||
9454 | static void | |
9455 | arm_show_abi (struct ui_file *file, int from_tty, | |
9456 | struct cmd_list_element *c, const char *value) | |
9457 | { | |
f5656ead | 9458 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
28e97307 DJ |
9459 | |
9460 | if (arm_abi_global == ARM_ABI_AUTO | |
f5656ead | 9461 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
9462 | fprintf_filtered (file, _("\ |
9463 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
9464 | arm_abi_strings[tdep->arm_abi]); | |
9465 | else | |
9466 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
9467 | arm_abi_string); | |
fd50bc42 RE |
9468 | } |
9469 | ||
0428b8f5 DJ |
9470 | static void |
9471 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
9472 | struct cmd_list_element *c, const char *value) | |
9473 | { | |
0963b4bd MS |
9474 | fprintf_filtered (file, |
9475 | _("The current execution mode assumed " | |
9476 | "(when symbols are unavailable) is \"%s\".\n"), | |
0428b8f5 DJ |
9477 | arm_fallback_mode_string); |
9478 | } | |
9479 | ||
9480 | static void | |
9481 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
9482 | struct cmd_list_element *c, const char *value) | |
9483 | { | |
f5656ead | 9484 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
0428b8f5 | 9485 | |
0963b4bd MS |
9486 | fprintf_filtered (file, |
9487 | _("The current execution mode assumed " | |
9488 | "(even when symbols are available) is \"%s\".\n"), | |
0428b8f5 DJ |
9489 | arm_force_mode_string); |
9490 | } | |
9491 | ||
afd7eef0 RE |
9492 | /* If the user changes the register disassembly style used for info |
9493 | register and other commands, we have to also switch the style used | |
9494 | in opcodes for disassembly output. This function is run in the "set | |
9495 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
9496 | |
9497 | static void | |
afd7eef0 | 9498 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
9499 | struct cmd_list_element *c) |
9500 | { | |
afd7eef0 | 9501 | set_disassembly_style (); |
bc90b915 FN |
9502 | } |
9503 | \f | |
966fbf70 | 9504 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 9505 | static const char * |
d93859e2 | 9506 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 9507 | { |
58d6951d DJ |
9508 | const int num_regs = gdbarch_num_regs (gdbarch); |
9509 | ||
9510 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
9511 | && i >= num_regs && i < num_regs + 32) | |
9512 | { | |
9513 | static const char *const vfp_pseudo_names[] = { | |
9514 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
9515 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
9516 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
9517 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
9518 | }; | |
9519 | ||
9520 | return vfp_pseudo_names[i - num_regs]; | |
9521 | } | |
9522 | ||
9523 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
9524 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
9525 | { | |
9526 | static const char *const neon_pseudo_names[] = { | |
9527 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
9528 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
9529 | }; | |
9530 | ||
9531 | return neon_pseudo_names[i - num_regs - 32]; | |
9532 | } | |
9533 | ||
ff6f572f DJ |
9534 | if (i >= ARRAY_SIZE (arm_register_names)) |
9535 | /* These registers are only supported on targets which supply | |
9536 | an XML description. */ | |
9537 | return ""; | |
9538 | ||
966fbf70 RE |
9539 | return arm_register_names[i]; |
9540 | } | |
9541 | ||
bc90b915 | 9542 | static void |
afd7eef0 | 9543 | set_disassembly_style (void) |
bc90b915 | 9544 | { |
123dc839 | 9545 | int current; |
bc90b915 | 9546 | |
123dc839 DJ |
9547 | /* Find the style that the user wants. */ |
9548 | for (current = 0; current < num_disassembly_options; current++) | |
9549 | if (disassembly_style == valid_disassembly_styles[current]) | |
9550 | break; | |
9551 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 9552 | |
94c30b78 | 9553 | /* Synchronize the disassembler. */ |
bc90b915 FN |
9554 | set_arm_regname_option (current); |
9555 | } | |
9556 | ||
082fc60d RE |
9557 | /* Test whether the coff symbol specific value corresponds to a Thumb |
9558 | function. */ | |
9559 | ||
9560 | static int | |
9561 | coff_sym_is_thumb (int val) | |
9562 | { | |
f8bf5763 PM |
9563 | return (val == C_THUMBEXT |
9564 | || val == C_THUMBSTAT | |
9565 | || val == C_THUMBEXTFUNC | |
9566 | || val == C_THUMBSTATFUNC | |
9567 | || val == C_THUMBLABEL); | |
082fc60d RE |
9568 | } |
9569 | ||
9570 | /* arm_coff_make_msymbol_special() | |
9571 | arm_elf_make_msymbol_special() | |
9572 | ||
9573 | These functions test whether the COFF or ELF symbol corresponds to | |
9574 | an address in thumb code, and set a "special" bit in a minimal | |
9575 | symbol to indicate that it does. */ | |
9576 | ||
34e8f22d | 9577 | static void |
082fc60d RE |
9578 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
9579 | { | |
467d42c4 UW |
9580 | if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym) |
9581 | == ST_BRANCH_TO_THUMB) | |
082fc60d RE |
9582 | MSYMBOL_SET_SPECIAL (msym); |
9583 | } | |
9584 | ||
34e8f22d | 9585 | static void |
082fc60d RE |
9586 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
9587 | { | |
9588 | if (coff_sym_is_thumb (val)) | |
9589 | MSYMBOL_SET_SPECIAL (msym); | |
9590 | } | |
9591 | ||
60c5725c | 9592 | static void |
c1bd65d0 | 9593 | arm_objfile_data_free (struct objfile *objfile, void *arg) |
60c5725c DJ |
9594 | { |
9595 | struct arm_per_objfile *data = arg; | |
9596 | unsigned int i; | |
9597 | ||
9598 | for (i = 0; i < objfile->obfd->section_count; i++) | |
9599 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); | |
9600 | } | |
9601 | ||
9602 | static void | |
9603 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
9604 | asymbol *sym) | |
9605 | { | |
9606 | const char *name = bfd_asymbol_name (sym); | |
9607 | struct arm_per_objfile *data; | |
9608 | VEC(arm_mapping_symbol_s) **map_p; | |
9609 | struct arm_mapping_symbol new_map_sym; | |
9610 | ||
9611 | gdb_assert (name[0] == '$'); | |
9612 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
9613 | return; | |
9614 | ||
9615 | data = objfile_data (objfile, arm_objfile_data_key); | |
9616 | if (data == NULL) | |
9617 | { | |
9618 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, | |
9619 | struct arm_per_objfile); | |
9620 | set_objfile_data (objfile, arm_objfile_data_key, data); | |
9621 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
9622 | objfile->obfd->section_count, | |
9623 | VEC(arm_mapping_symbol_s) *); | |
9624 | } | |
9625 | map_p = &data->section_maps[bfd_get_section (sym)->index]; | |
9626 | ||
9627 | new_map_sym.value = sym->value; | |
9628 | new_map_sym.type = name[1]; | |
9629 | ||
9630 | /* Assume that most mapping symbols appear in order of increasing | |
9631 | value. If they were randomly distributed, it would be faster to | |
9632 | always push here and then sort at first use. */ | |
9633 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) | |
9634 | { | |
9635 | struct arm_mapping_symbol *prev_map_sym; | |
9636 | ||
9637 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); | |
9638 | if (prev_map_sym->value >= sym->value) | |
9639 | { | |
9640 | unsigned int idx; | |
9641 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, | |
9642 | arm_compare_mapping_symbols); | |
9643 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); | |
9644 | return; | |
9645 | } | |
9646 | } | |
9647 | ||
9648 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); | |
9649 | } | |
9650 | ||
756fe439 | 9651 | static void |
61a1198a | 9652 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 9653 | { |
9779414d | 9654 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
61a1198a | 9655 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
9656 | |
9657 | /* If necessary, set the T bit. */ | |
9658 | if (arm_apcs_32) | |
9659 | { | |
9779414d | 9660 | ULONGEST val, t_bit; |
61a1198a | 9661 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
9662 | t_bit = arm_psr_thumb_bit (gdbarch); |
9663 | if (arm_pc_is_thumb (gdbarch, pc)) | |
9664 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
9665 | val | t_bit); | |
756fe439 | 9666 | else |
61a1198a | 9667 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 9668 | val & ~t_bit); |
756fe439 DJ |
9669 | } |
9670 | } | |
123dc839 | 9671 | |
58d6951d DJ |
9672 | /* Read the contents of a NEON quad register, by reading from two |
9673 | double registers. This is used to implement the quad pseudo | |
9674 | registers, and for argument passing in case the quad registers are | |
9675 | missing; vectors are passed in quad registers when using the VFP | |
9676 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
9677 | the quad register, in [0, 15]. */ | |
9678 | ||
05d1431c | 9679 | static enum register_status |
58d6951d DJ |
9680 | arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, |
9681 | int regnum, gdb_byte *buf) | |
9682 | { | |
9683 | char name_buf[4]; | |
9684 | gdb_byte reg_buf[8]; | |
9685 | int offset, double_regnum; | |
05d1431c | 9686 | enum register_status status; |
58d6951d | 9687 | |
8c042590 | 9688 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9689 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9690 | strlen (name_buf)); | |
9691 | ||
9692 | /* d0 is always the least significant half of q0. */ | |
9693 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9694 | offset = 8; | |
9695 | else | |
9696 | offset = 0; | |
9697 | ||
05d1431c PA |
9698 | status = regcache_raw_read (regcache, double_regnum, reg_buf); |
9699 | if (status != REG_VALID) | |
9700 | return status; | |
58d6951d DJ |
9701 | memcpy (buf + offset, reg_buf, 8); |
9702 | ||
9703 | offset = 8 - offset; | |
05d1431c PA |
9704 | status = regcache_raw_read (regcache, double_regnum + 1, reg_buf); |
9705 | if (status != REG_VALID) | |
9706 | return status; | |
58d6951d | 9707 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
9708 | |
9709 | return REG_VALID; | |
58d6951d DJ |
9710 | } |
9711 | ||
05d1431c | 9712 | static enum register_status |
58d6951d DJ |
9713 | arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache, |
9714 | int regnum, gdb_byte *buf) | |
9715 | { | |
9716 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9717 | char name_buf[4]; | |
9718 | gdb_byte reg_buf[8]; | |
9719 | int offset, double_regnum; | |
9720 | ||
9721 | gdb_assert (regnum >= num_regs); | |
9722 | regnum -= num_regs; | |
9723 | ||
9724 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
9725 | /* Quad-precision register. */ | |
05d1431c | 9726 | return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); |
58d6951d DJ |
9727 | else |
9728 | { | |
05d1431c PA |
9729 | enum register_status status; |
9730 | ||
58d6951d DJ |
9731 | /* Single-precision register. */ |
9732 | gdb_assert (regnum < 32); | |
9733 | ||
9734 | /* s0 is always the least significant half of d0. */ | |
9735 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9736 | offset = (regnum & 1) ? 0 : 4; | |
9737 | else | |
9738 | offset = (regnum & 1) ? 4 : 0; | |
9739 | ||
8c042590 | 9740 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9741 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9742 | strlen (name_buf)); | |
9743 | ||
05d1431c PA |
9744 | status = regcache_raw_read (regcache, double_regnum, reg_buf); |
9745 | if (status == REG_VALID) | |
9746 | memcpy (buf, reg_buf + offset, 4); | |
9747 | return status; | |
58d6951d DJ |
9748 | } |
9749 | } | |
9750 | ||
9751 | /* Store the contents of BUF to a NEON quad register, by writing to | |
9752 | two double registers. This is used to implement the quad pseudo | |
9753 | registers, and for argument passing in case the quad registers are | |
9754 | missing; vectors are passed in quad registers when using the VFP | |
9755 | ABI, even if a NEON unit is not present. REGNUM is the index | |
9756 | of the quad register, in [0, 15]. */ | |
9757 | ||
9758 | static void | |
9759 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9760 | int regnum, const gdb_byte *buf) | |
9761 | { | |
9762 | char name_buf[4]; | |
58d6951d DJ |
9763 | int offset, double_regnum; |
9764 | ||
8c042590 | 9765 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9766 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9767 | strlen (name_buf)); | |
9768 | ||
9769 | /* d0 is always the least significant half of q0. */ | |
9770 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9771 | offset = 8; | |
9772 | else | |
9773 | offset = 0; | |
9774 | ||
9775 | regcache_raw_write (regcache, double_regnum, buf + offset); | |
9776 | offset = 8 - offset; | |
9777 | regcache_raw_write (regcache, double_regnum + 1, buf + offset); | |
9778 | } | |
9779 | ||
9780 | static void | |
9781 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9782 | int regnum, const gdb_byte *buf) | |
9783 | { | |
9784 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9785 | char name_buf[4]; | |
9786 | gdb_byte reg_buf[8]; | |
9787 | int offset, double_regnum; | |
9788 | ||
9789 | gdb_assert (regnum >= num_regs); | |
9790 | regnum -= num_regs; | |
9791 | ||
9792 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
9793 | /* Quad-precision register. */ | |
9794 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
9795 | else | |
9796 | { | |
9797 | /* Single-precision register. */ | |
9798 | gdb_assert (regnum < 32); | |
9799 | ||
9800 | /* s0 is always the least significant half of d0. */ | |
9801 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9802 | offset = (regnum & 1) ? 0 : 4; | |
9803 | else | |
9804 | offset = (regnum & 1) ? 4 : 0; | |
9805 | ||
8c042590 | 9806 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9807 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9808 | strlen (name_buf)); | |
9809 | ||
9810 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
9811 | memcpy (reg_buf + offset, buf, 4); | |
9812 | regcache_raw_write (regcache, double_regnum, reg_buf); | |
9813 | } | |
9814 | } | |
9815 | ||
123dc839 DJ |
9816 | static struct value * |
9817 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
9818 | { | |
9819 | const int *reg_p = baton; | |
9820 | return value_of_register (*reg_p, frame); | |
9821 | } | |
97e03143 | 9822 | \f |
70f80edf JT |
9823 | static enum gdb_osabi |
9824 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 9825 | { |
2af48f68 | 9826 | unsigned int elfosabi; |
70f80edf | 9827 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 9828 | |
70f80edf | 9829 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 9830 | |
28e97307 DJ |
9831 | if (elfosabi == ELFOSABI_ARM) |
9832 | /* GNU tools use this value. Check note sections in this case, | |
9833 | as well. */ | |
9834 | bfd_map_over_sections (abfd, | |
9835 | generic_elf_osabi_sniff_abi_tag_sections, | |
9836 | &osabi); | |
97e03143 | 9837 | |
28e97307 | 9838 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 9839 | return osabi; |
97e03143 RE |
9840 | } |
9841 | ||
54483882 YQ |
9842 | static int |
9843 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
9844 | struct reggroup *group) | |
9845 | { | |
2c291032 YQ |
9846 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
9847 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
9848 | all_reggroup, of course. */ | |
54483882 | 9849 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
9850 | return (group == float_reggroup |
9851 | || group == save_reggroup | |
9852 | || group == restore_reggroup | |
9853 | || group == all_reggroup); | |
54483882 YQ |
9854 | else |
9855 | return default_register_reggroup_p (gdbarch, regnum, group); | |
9856 | } | |
9857 | ||
25f8c692 JL |
9858 | \f |
9859 | /* For backward-compatibility we allow two 'g' packet lengths with | |
9860 | the remote protocol depending on whether FPA registers are | |
9861 | supplied. M-profile targets do not have FPA registers, but some | |
9862 | stubs already exist in the wild which use a 'g' packet which | |
9863 | supplies them albeit with dummy values. The packet format which | |
9864 | includes FPA registers should be considered deprecated for | |
9865 | M-profile targets. */ | |
9866 | ||
9867 | static void | |
9868 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
9869 | { | |
9870 | if (gdbarch_tdep (gdbarch)->is_m) | |
9871 | { | |
9872 | /* If we know from the executable this is an M-profile target, | |
9873 | cater for remote targets whose register set layout is the | |
9874 | same as the FPA layout. */ | |
9875 | register_remote_g_packet_guess (gdbarch, | |
03145bf4 | 9876 | /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */ |
25f8c692 JL |
9877 | (16 * INT_REGISTER_SIZE) |
9878 | + (8 * FP_REGISTER_SIZE) | |
9879 | + (2 * INT_REGISTER_SIZE), | |
9880 | tdesc_arm_with_m_fpa_layout); | |
9881 | ||
9882 | /* The regular M-profile layout. */ | |
9883 | register_remote_g_packet_guess (gdbarch, | |
9884 | /* r0-r12,sp,lr,pc; xpsr */ | |
9885 | (16 * INT_REGISTER_SIZE) | |
9886 | + INT_REGISTER_SIZE, | |
9887 | tdesc_arm_with_m); | |
3184d3f9 JL |
9888 | |
9889 | /* M-profile plus M4F VFP. */ | |
9890 | register_remote_g_packet_guess (gdbarch, | |
9891 | /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */ | |
9892 | (16 * INT_REGISTER_SIZE) | |
9893 | + (16 * VFP_REGISTER_SIZE) | |
9894 | + (2 * INT_REGISTER_SIZE), | |
9895 | tdesc_arm_with_m_vfp_d16); | |
25f8c692 JL |
9896 | } |
9897 | ||
9898 | /* Otherwise we don't have a useful guess. */ | |
9899 | } | |
9900 | ||
70f80edf | 9901 | \f |
da3c6d4a MS |
9902 | /* Initialize the current architecture based on INFO. If possible, |
9903 | re-use an architecture from ARCHES, which is a list of | |
9904 | architectures already created during this debugging session. | |
97e03143 | 9905 | |
da3c6d4a MS |
9906 | Called e.g. at program startup, when reading a core file, and when |
9907 | reading a binary file. */ | |
97e03143 | 9908 | |
39bbf761 RE |
9909 | static struct gdbarch * |
9910 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
9911 | { | |
97e03143 | 9912 | struct gdbarch_tdep *tdep; |
39bbf761 | 9913 | struct gdbarch *gdbarch; |
28e97307 DJ |
9914 | struct gdbarch_list *best_arch; |
9915 | enum arm_abi_kind arm_abi = arm_abi_global; | |
9916 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 | 9917 | struct tdesc_arch_data *tdesc_data = NULL; |
9779414d | 9918 | int i, is_m = 0; |
58d6951d DJ |
9919 | int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; |
9920 | int have_neon = 0; | |
ff6f572f | 9921 | int have_fpa_registers = 1; |
9779414d DJ |
9922 | const struct target_desc *tdesc = info.target_desc; |
9923 | ||
9924 | /* If we have an object to base this architecture on, try to determine | |
9925 | its ABI. */ | |
9926 | ||
9927 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
9928 | { | |
9929 | int ei_osabi, e_flags; | |
9930 | ||
9931 | switch (bfd_get_flavour (info.abfd)) | |
9932 | { | |
9933 | case bfd_target_aout_flavour: | |
9934 | /* Assume it's an old APCS-style ABI. */ | |
9935 | arm_abi = ARM_ABI_APCS; | |
9936 | break; | |
9937 | ||
9938 | case bfd_target_coff_flavour: | |
9939 | /* Assume it's an old APCS-style ABI. */ | |
9940 | /* XXX WinCE? */ | |
9941 | arm_abi = ARM_ABI_APCS; | |
9942 | break; | |
9943 | ||
9944 | case bfd_target_elf_flavour: | |
9945 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
9946 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
9947 | ||
9948 | if (ei_osabi == ELFOSABI_ARM) | |
9949 | { | |
9950 | /* GNU tools used to use this value, but do not for EABI | |
9951 | objects. There's nowhere to tag an EABI version | |
9952 | anyway, so assume APCS. */ | |
9953 | arm_abi = ARM_ABI_APCS; | |
9954 | } | |
9955 | else if (ei_osabi == ELFOSABI_NONE) | |
9956 | { | |
9957 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9958 | int attr_arch, attr_profile; | |
9959 | ||
9960 | switch (eabi_ver) | |
9961 | { | |
9962 | case EF_ARM_EABI_UNKNOWN: | |
9963 | /* Assume GNU tools. */ | |
9964 | arm_abi = ARM_ABI_APCS; | |
9965 | break; | |
9966 | ||
9967 | case EF_ARM_EABI_VER4: | |
9968 | case EF_ARM_EABI_VER5: | |
9969 | arm_abi = ARM_ABI_AAPCS; | |
9970 | /* EABI binaries default to VFP float ordering. | |
9971 | They may also contain build attributes that can | |
9972 | be used to identify if the VFP argument-passing | |
9973 | ABI is in use. */ | |
9974 | if (fp_model == ARM_FLOAT_AUTO) | |
9975 | { | |
9976 | #ifdef HAVE_ELF | |
9977 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
9978 | OBJ_ATTR_PROC, | |
9979 | Tag_ABI_VFP_args)) | |
9980 | { | |
b35b0298 | 9981 | case AEABI_VFP_args_base: |
9779414d DJ |
9982 | /* "The user intended FP parameter/result |
9983 | passing to conform to AAPCS, base | |
9984 | variant". */ | |
9985 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9986 | break; | |
b35b0298 | 9987 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9988 | /* "The user intended FP parameter/result |
9989 | passing to conform to AAPCS, VFP | |
9990 | variant". */ | |
9991 | fp_model = ARM_FLOAT_VFP; | |
9992 | break; | |
b35b0298 | 9993 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9994 | /* "The user intended FP parameter/result |
9995 | passing to conform to tool chain-specific | |
9996 | conventions" - we don't know any such | |
9997 | conventions, so leave it as "auto". */ | |
9998 | break; | |
b35b0298 | 9999 | case AEABI_VFP_args_compatible: |
5c294fee TG |
10000 | /* "Code is compatible with both the base |
10001 | and VFP variants; the user did not permit | |
10002 | non-variadic functions to pass FP | |
10003 | parameters/results" - leave it as | |
10004 | "auto". */ | |
10005 | break; | |
9779414d DJ |
10006 | default: |
10007 | /* Attribute value not mentioned in the | |
5c294fee | 10008 | November 2012 ABI, so leave it as |
9779414d DJ |
10009 | "auto". */ |
10010 | break; | |
10011 | } | |
10012 | #else | |
10013 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10014 | #endif | |
10015 | } | |
10016 | break; | |
10017 | ||
10018 | default: | |
10019 | /* Leave it as "auto". */ | |
10020 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
10021 | break; | |
10022 | } | |
10023 | ||
10024 | #ifdef HAVE_ELF | |
10025 | /* Detect M-profile programs. This only works if the | |
10026 | executable file includes build attributes; GCC does | |
10027 | copy them to the executable, but e.g. RealView does | |
10028 | not. */ | |
10029 | attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10030 | Tag_CPU_arch); | |
0963b4bd MS |
10031 | attr_profile = bfd_elf_get_obj_attr_int (info.abfd, |
10032 | OBJ_ATTR_PROC, | |
9779414d DJ |
10033 | Tag_CPU_arch_profile); |
10034 | /* GCC specifies the profile for v6-M; RealView only | |
10035 | specifies the profile for architectures starting with | |
10036 | V7 (as opposed to architectures with a tag | |
10037 | numerically greater than TAG_CPU_ARCH_V7). */ | |
10038 | if (!tdesc_has_registers (tdesc) | |
10039 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
10040 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
10041 | || attr_profile == 'M')) | |
25f8c692 | 10042 | is_m = 1; |
9779414d DJ |
10043 | #endif |
10044 | } | |
10045 | ||
10046 | if (fp_model == ARM_FLOAT_AUTO) | |
10047 | { | |
10048 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
10049 | ||
10050 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
10051 | { | |
10052 | case 0: | |
10053 | /* Leave it as "auto". Strictly speaking this case | |
10054 | means FPA, but almost nobody uses that now, and | |
10055 | many toolchains fail to set the appropriate bits | |
10056 | for the floating-point model they use. */ | |
10057 | break; | |
10058 | case EF_ARM_SOFT_FLOAT: | |
10059 | fp_model = ARM_FLOAT_SOFT_FPA; | |
10060 | break; | |
10061 | case EF_ARM_VFP_FLOAT: | |
10062 | fp_model = ARM_FLOAT_VFP; | |
10063 | break; | |
10064 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
10065 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10066 | break; | |
10067 | } | |
10068 | } | |
10069 | ||
10070 | if (e_flags & EF_ARM_BE8) | |
10071 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
10072 | ||
10073 | break; | |
10074 | ||
10075 | default: | |
10076 | /* Leave it as "auto". */ | |
10077 | break; | |
10078 | } | |
10079 | } | |
123dc839 DJ |
10080 | |
10081 | /* Check any target description for validity. */ | |
9779414d | 10082 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
10083 | { |
10084 | /* For most registers we require GDB's default names; but also allow | |
10085 | the numeric names for sp / lr / pc, as a convenience. */ | |
10086 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
10087 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
10088 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
10089 | ||
10090 | const struct tdesc_feature *feature; | |
58d6951d | 10091 | int valid_p; |
123dc839 | 10092 | |
9779414d | 10093 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10094 | "org.gnu.gdb.arm.core"); |
10095 | if (feature == NULL) | |
9779414d DJ |
10096 | { |
10097 | feature = tdesc_find_feature (tdesc, | |
10098 | "org.gnu.gdb.arm.m-profile"); | |
10099 | if (feature == NULL) | |
10100 | return NULL; | |
10101 | else | |
10102 | is_m = 1; | |
10103 | } | |
123dc839 DJ |
10104 | |
10105 | tdesc_data = tdesc_data_alloc (); | |
10106 | ||
10107 | valid_p = 1; | |
10108 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
10109 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
10110 | arm_register_names[i]); | |
10111 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
10112 | ARM_SP_REGNUM, | |
10113 | arm_sp_names); | |
10114 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
10115 | ARM_LR_REGNUM, | |
10116 | arm_lr_names); | |
10117 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
10118 | ARM_PC_REGNUM, | |
10119 | arm_pc_names); | |
9779414d DJ |
10120 | if (is_m) |
10121 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
10122 | ARM_PS_REGNUM, "xpsr"); | |
10123 | else | |
10124 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
10125 | ARM_PS_REGNUM, "cpsr"); | |
123dc839 DJ |
10126 | |
10127 | if (!valid_p) | |
10128 | { | |
10129 | tdesc_data_cleanup (tdesc_data); | |
10130 | return NULL; | |
10131 | } | |
10132 | ||
9779414d | 10133 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10134 | "org.gnu.gdb.arm.fpa"); |
10135 | if (feature != NULL) | |
10136 | { | |
10137 | valid_p = 1; | |
10138 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
10139 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
10140 | arm_register_names[i]); | |
10141 | if (!valid_p) | |
10142 | { | |
10143 | tdesc_data_cleanup (tdesc_data); | |
10144 | return NULL; | |
10145 | } | |
10146 | } | |
ff6f572f DJ |
10147 | else |
10148 | have_fpa_registers = 0; | |
10149 | ||
9779414d | 10150 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
10151 | "org.gnu.gdb.xscale.iwmmxt"); |
10152 | if (feature != NULL) | |
10153 | { | |
10154 | static const char *const iwmmxt_names[] = { | |
10155 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
10156 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
10157 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
10158 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
10159 | }; | |
10160 | ||
10161 | valid_p = 1; | |
10162 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
10163 | valid_p | |
10164 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
10165 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
10166 | ||
10167 | /* Check for the control registers, but do not fail if they | |
10168 | are missing. */ | |
10169 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
10170 | tdesc_numbered_register (feature, tdesc_data, i, | |
10171 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
10172 | ||
10173 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
10174 | valid_p | |
10175 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
10176 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
10177 | ||
10178 | if (!valid_p) | |
10179 | { | |
10180 | tdesc_data_cleanup (tdesc_data); | |
10181 | return NULL; | |
10182 | } | |
10183 | } | |
58d6951d DJ |
10184 | |
10185 | /* If we have a VFP unit, check whether the single precision registers | |
10186 | are present. If not, then we will synthesize them as pseudo | |
10187 | registers. */ | |
9779414d | 10188 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10189 | "org.gnu.gdb.arm.vfp"); |
10190 | if (feature != NULL) | |
10191 | { | |
10192 | static const char *const vfp_double_names[] = { | |
10193 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
10194 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
10195 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
10196 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
10197 | }; | |
10198 | ||
10199 | /* Require the double precision registers. There must be either | |
10200 | 16 or 32. */ | |
10201 | valid_p = 1; | |
10202 | for (i = 0; i < 32; i++) | |
10203 | { | |
10204 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
10205 | ARM_D0_REGNUM + i, | |
10206 | vfp_double_names[i]); | |
10207 | if (!valid_p) | |
10208 | break; | |
10209 | } | |
2b9e5ea6 UW |
10210 | if (!valid_p && i == 16) |
10211 | valid_p = 1; | |
58d6951d | 10212 | |
2b9e5ea6 UW |
10213 | /* Also require FPSCR. */ |
10214 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
10215 | ARM_FPSCR_REGNUM, "fpscr"); | |
10216 | if (!valid_p) | |
58d6951d DJ |
10217 | { |
10218 | tdesc_data_cleanup (tdesc_data); | |
10219 | return NULL; | |
10220 | } | |
10221 | ||
10222 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
10223 | have_vfp_pseudos = 1; | |
10224 | ||
10225 | have_vfp_registers = 1; | |
10226 | ||
10227 | /* If we have VFP, also check for NEON. The architecture allows | |
10228 | NEON without VFP (integer vector operations only), but GDB | |
10229 | does not support that. */ | |
9779414d | 10230 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10231 | "org.gnu.gdb.arm.neon"); |
10232 | if (feature != NULL) | |
10233 | { | |
10234 | /* NEON requires 32 double-precision registers. */ | |
10235 | if (i != 32) | |
10236 | { | |
10237 | tdesc_data_cleanup (tdesc_data); | |
10238 | return NULL; | |
10239 | } | |
10240 | ||
10241 | /* If there are quad registers defined by the stub, use | |
10242 | their type; otherwise (normally) provide them with | |
10243 | the default type. */ | |
10244 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
10245 | have_neon_pseudos = 1; | |
10246 | ||
10247 | have_neon = 1; | |
10248 | } | |
10249 | } | |
123dc839 | 10250 | } |
39bbf761 | 10251 | |
28e97307 DJ |
10252 | /* If there is already a candidate, use it. */ |
10253 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
10254 | best_arch != NULL; | |
10255 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
10256 | { | |
b8926edc DJ |
10257 | if (arm_abi != ARM_ABI_AUTO |
10258 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
10259 | continue; |
10260 | ||
b8926edc DJ |
10261 | if (fp_model != ARM_FLOAT_AUTO |
10262 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
10263 | continue; |
10264 | ||
58d6951d DJ |
10265 | /* There are various other properties in tdep that we do not |
10266 | need to check here: those derived from a target description, | |
10267 | since gdbarches with a different target description are | |
10268 | automatically disqualified. */ | |
10269 | ||
9779414d DJ |
10270 | /* Do check is_m, though, since it might come from the binary. */ |
10271 | if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m) | |
10272 | continue; | |
10273 | ||
28e97307 DJ |
10274 | /* Found a match. */ |
10275 | break; | |
10276 | } | |
97e03143 | 10277 | |
28e97307 | 10278 | if (best_arch != NULL) |
123dc839 DJ |
10279 | { |
10280 | if (tdesc_data != NULL) | |
10281 | tdesc_data_cleanup (tdesc_data); | |
10282 | return best_arch->gdbarch; | |
10283 | } | |
28e97307 DJ |
10284 | |
10285 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
10286 | gdbarch = gdbarch_alloc (&info, tdep); |
10287 | ||
28e97307 DJ |
10288 | /* Record additional information about the architecture we are defining. |
10289 | These are gdbarch discriminators, like the OSABI. */ | |
10290 | tdep->arm_abi = arm_abi; | |
10291 | tdep->fp_model = fp_model; | |
9779414d | 10292 | tdep->is_m = is_m; |
ff6f572f | 10293 | tdep->have_fpa_registers = have_fpa_registers; |
58d6951d DJ |
10294 | tdep->have_vfp_registers = have_vfp_registers; |
10295 | tdep->have_vfp_pseudos = have_vfp_pseudos; | |
10296 | tdep->have_neon_pseudos = have_neon_pseudos; | |
10297 | tdep->have_neon = have_neon; | |
08216dd7 | 10298 | |
25f8c692 JL |
10299 | arm_register_g_packet_guesses (gdbarch); |
10300 | ||
08216dd7 | 10301 | /* Breakpoints. */ |
9d4fde75 | 10302 | switch (info.byte_order_for_code) |
67255d04 RE |
10303 | { |
10304 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
10305 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
10306 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
10307 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
10308 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
10309 | ||
67255d04 RE |
10310 | break; |
10311 | ||
10312 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
10313 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
10314 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
10315 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
10316 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
10317 | ||
67255d04 RE |
10318 | break; |
10319 | ||
10320 | default: | |
10321 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 10322 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
10323 | } |
10324 | ||
d7b486e7 RE |
10325 | /* On ARM targets char defaults to unsigned. */ |
10326 | set_gdbarch_char_signed (gdbarch, 0); | |
10327 | ||
cca44b1b JB |
10328 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
10329 | of additional scratch space. This setting isn't used for anything beside | |
10330 | displaced stepping at present. */ | |
10331 | set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS); | |
10332 | ||
9df628e0 | 10333 | /* This should be low enough for everything. */ |
97e03143 | 10334 | tdep->lowest_pc = 0x20; |
94c30b78 | 10335 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 10336 | |
7c00367c MK |
10337 | /* The default, for both APCS and AAPCS, is to return small |
10338 | structures in registers. */ | |
10339 | tdep->struct_return = reg_struct_return; | |
10340 | ||
2dd604e7 | 10341 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 10342 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 10343 | |
756fe439 DJ |
10344 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
10345 | ||
148754e5 | 10346 | /* Frame handling. */ |
a262aec2 | 10347 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
10348 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
10349 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
10350 | ||
eb5492fa | 10351 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 10352 | |
34e8f22d | 10353 | /* Address manipulation. */ |
34e8f22d RE |
10354 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
10355 | ||
34e8f22d RE |
10356 | /* Advance PC across function entry code. */ |
10357 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
10358 | ||
4024ca99 UW |
10359 | /* Detect whether PC is in function epilogue. */ |
10360 | set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p); | |
10361 | ||
190dce09 UW |
10362 | /* Skip trampolines. */ |
10363 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
10364 | ||
34e8f22d RE |
10365 | /* The stack grows downward. */ |
10366 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
10367 | ||
10368 | /* Breakpoint manipulation. */ | |
10369 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
177321bd DJ |
10370 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
10371 | arm_remote_breakpoint_from_pc); | |
34e8f22d RE |
10372 | |
10373 | /* Information about registers, etc. */ | |
34e8f22d RE |
10374 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
10375 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 10376 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 10377 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 10378 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 10379 | |
ff6f572f DJ |
10380 | /* This "info float" is FPA-specific. Use the generic version if we |
10381 | do not have FPA. */ | |
10382 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
10383 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
10384 | ||
26216b98 | 10385 | /* Internal <-> external register number maps. */ |
ff6f572f | 10386 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
10387 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
10388 | ||
34e8f22d RE |
10389 | set_gdbarch_register_name (gdbarch, arm_register_name); |
10390 | ||
10391 | /* Returning results. */ | |
2af48f68 | 10392 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 10393 | |
03d48a7d RE |
10394 | /* Disassembly. */ |
10395 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
10396 | ||
34e8f22d RE |
10397 | /* Minsymbol frobbing. */ |
10398 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
10399 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
10400 | arm_coff_make_msymbol_special); | |
60c5725c | 10401 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 10402 | |
f9d67f43 DJ |
10403 | /* Thumb-2 IT block support. */ |
10404 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
10405 | arm_adjust_breakpoint_address); | |
10406 | ||
0d5de010 DJ |
10407 | /* Virtual tables. */ |
10408 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
10409 | ||
97e03143 | 10410 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 10411 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 10412 | |
b39cc962 DJ |
10413 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
10414 | ||
eb5492fa | 10415 | /* Add some default predicates. */ |
2ae28aa9 YQ |
10416 | if (is_m) |
10417 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
10418 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
10419 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 10420 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
a262aec2 | 10421 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 10422 | |
97e03143 RE |
10423 | /* Now we have tuned the configuration, set a few final things, |
10424 | based on what the OS ABI has told us. */ | |
10425 | ||
b8926edc DJ |
10426 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
10427 | binaries are always marked. */ | |
10428 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
10429 | tdep->arm_abi = ARM_ABI_APCS; | |
10430 | ||
e3039479 UW |
10431 | /* Watchpoints are not steppable. */ |
10432 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
10433 | ||
b8926edc DJ |
10434 | /* We used to default to FPA for generic ARM, but almost nobody |
10435 | uses that now, and we now provide a way for the user to force | |
10436 | the model. So default to the most useful variant. */ | |
10437 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
10438 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
10439 | ||
9df628e0 RE |
10440 | if (tdep->jb_pc >= 0) |
10441 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
10442 | ||
08216dd7 | 10443 | /* Floating point sizes and format. */ |
8da61cc4 | 10444 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 10445 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 10446 | { |
8da61cc4 DJ |
10447 | set_gdbarch_double_format |
10448 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10449 | set_gdbarch_long_double_format | |
10450 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10451 | } | |
10452 | else | |
10453 | { | |
10454 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
10455 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
10456 | } |
10457 | ||
58d6951d DJ |
10458 | if (have_vfp_pseudos) |
10459 | { | |
10460 | /* NOTE: These are the only pseudo registers used by | |
10461 | the ARM target at the moment. If more are added, a | |
10462 | little more care in numbering will be needed. */ | |
10463 | ||
10464 | int num_pseudos = 32; | |
10465 | if (have_neon_pseudos) | |
10466 | num_pseudos += 16; | |
10467 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
10468 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
10469 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
10470 | } | |
10471 | ||
123dc839 | 10472 | if (tdesc_data) |
58d6951d DJ |
10473 | { |
10474 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
10475 | ||
9779414d | 10476 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
58d6951d DJ |
10477 | |
10478 | /* Override tdesc_register_type to adjust the types of VFP | |
10479 | registers for NEON. */ | |
10480 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
10481 | } | |
123dc839 DJ |
10482 | |
10483 | /* Add standard register aliases. We add aliases even for those | |
10484 | nanes which are used by the current architecture - it's simpler, | |
10485 | and does no harm, since nothing ever lists user registers. */ | |
10486 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
10487 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
10488 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
10489 | ||
39bbf761 RE |
10490 | return gdbarch; |
10491 | } | |
10492 | ||
97e03143 | 10493 | static void |
2af46ca0 | 10494 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 10495 | { |
2af46ca0 | 10496 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
10497 | |
10498 | if (tdep == NULL) | |
10499 | return; | |
10500 | ||
edefbb7c | 10501 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
10502 | (unsigned long) tdep->lowest_pc); |
10503 | } | |
10504 | ||
a78f21af AC |
10505 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
10506 | ||
c906108c | 10507 | void |
ed9a39eb | 10508 | _initialize_arm_tdep (void) |
c906108c | 10509 | { |
bc90b915 FN |
10510 | struct ui_file *stb; |
10511 | long length; | |
26304000 | 10512 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
10513 | const char *setname; |
10514 | const char *setdesc; | |
4bd7b427 | 10515 | const char *const *regnames; |
bc90b915 FN |
10516 | int numregs, i, j; |
10517 | static char *helptext; | |
edefbb7c AC |
10518 | char regdesc[1024], *rdptr = regdesc; |
10519 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 10520 | |
42cf1509 | 10521 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 10522 | |
60c5725c | 10523 | arm_objfile_data_key |
c1bd65d0 | 10524 | = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free); |
60c5725c | 10525 | |
0e9e9abd UW |
10526 | /* Add ourselves to objfile event chain. */ |
10527 | observer_attach_new_objfile (arm_exidx_new_objfile); | |
10528 | arm_exidx_data_key | |
10529 | = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free); | |
10530 | ||
70f80edf JT |
10531 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
10532 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
10533 | bfd_target_elf_flavour, | |
10534 | arm_elf_osabi_sniffer); | |
10535 | ||
9779414d DJ |
10536 | /* Initialize the standard target descriptions. */ |
10537 | initialize_tdesc_arm_with_m (); | |
25f8c692 | 10538 | initialize_tdesc_arm_with_m_fpa_layout (); |
3184d3f9 | 10539 | initialize_tdesc_arm_with_m_vfp_d16 (); |
ef7e8358 UW |
10540 | initialize_tdesc_arm_with_iwmmxt (); |
10541 | initialize_tdesc_arm_with_vfpv2 (); | |
10542 | initialize_tdesc_arm_with_vfpv3 (); | |
10543 | initialize_tdesc_arm_with_neon (); | |
9779414d | 10544 | |
94c30b78 | 10545 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
10546 | num_disassembly_options = get_arm_regname_num_options (); |
10547 | ||
10548 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
10549 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 10550 | _("Various ARM-specific commands."), |
afd7eef0 RE |
10551 | &setarmcmdlist, "set arm ", 0, &setlist); |
10552 | ||
10553 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 10554 | _("Various ARM-specific commands."), |
afd7eef0 | 10555 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 10556 | |
94c30b78 | 10557 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 10558 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 10559 | |
eefe576e AC |
10560 | /* Initialize the array that will be passed to |
10561 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
10562 | valid_disassembly_styles |
10563 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
10564 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
10565 | { |
10566 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 10567 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
10568 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
10569 | rdptr += length; | |
10570 | rest -= length; | |
123dc839 DJ |
10571 | /* When we find the default names, tell the disassembler to use |
10572 | them. */ | |
bc90b915 FN |
10573 | if (!strcmp (setname, "std")) |
10574 | { | |
afd7eef0 | 10575 | disassembly_style = setname; |
bc90b915 FN |
10576 | set_arm_regname_option (i); |
10577 | } | |
10578 | } | |
94c30b78 | 10579 | /* Mark the end of valid options. */ |
afd7eef0 | 10580 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 10581 | |
edefbb7c AC |
10582 | /* Create the help text. */ |
10583 | stb = mem_fileopen (); | |
10584 | fprintf_unfiltered (stb, "%s%s%s", | |
10585 | _("The valid values are:\n"), | |
10586 | regdesc, | |
10587 | _("The default is \"std\".")); | |
759ef836 | 10588 | helptext = ui_file_xstrdup (stb, NULL); |
bc90b915 | 10589 | ui_file_delete (stb); |
ed9a39eb | 10590 | |
edefbb7c AC |
10591 | add_setshow_enum_cmd("disassembler", no_class, |
10592 | valid_disassembly_styles, &disassembly_style, | |
10593 | _("Set the disassembly style."), | |
10594 | _("Show the disassembly style."), | |
10595 | helptext, | |
2c5b56ce | 10596 | set_disassembly_style_sfunc, |
0963b4bd MS |
10597 | NULL, /* FIXME: i18n: The disassembly style is |
10598 | \"%s\". */ | |
7376b4c2 | 10599 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
10600 | |
10601 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
10602 | _("Set usage of ARM 32-bit mode."), | |
10603 | _("Show usage of ARM 32-bit mode."), | |
10604 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 10605 | NULL, |
0963b4bd MS |
10606 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
10607 | mode is %s. */ | |
26304000 | 10608 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 10609 | |
fd50bc42 | 10610 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
10611 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
10612 | _("Set the floating point type."), | |
10613 | _("Show the floating point type."), | |
10614 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
10615 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
10616 | fpa - FPA co-processor (GCC compiled).\n\ | |
10617 | softvfp - Software FP with pure-endian doubles.\n\ | |
10618 | vfp - VFP co-processor."), | |
edefbb7c | 10619 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 10620 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 10621 | |
28e97307 DJ |
10622 | /* Add a command to allow the user to force the ABI. */ |
10623 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
10624 | _("Set the ABI."), | |
10625 | _("Show the ABI."), | |
10626 | NULL, arm_set_abi, arm_show_abi, | |
10627 | &setarmcmdlist, &showarmcmdlist); | |
10628 | ||
0428b8f5 DJ |
10629 | /* Add two commands to allow the user to force the assumed |
10630 | execution mode. */ | |
10631 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
10632 | arm_mode_strings, &arm_fallback_mode_string, | |
10633 | _("Set the mode assumed when symbols are unavailable."), | |
10634 | _("Show the mode assumed when symbols are unavailable."), | |
10635 | NULL, NULL, arm_show_fallback_mode, | |
10636 | &setarmcmdlist, &showarmcmdlist); | |
10637 | add_setshow_enum_cmd ("force-mode", class_support, | |
10638 | arm_mode_strings, &arm_force_mode_string, | |
10639 | _("Set the mode assumed even when symbols are available."), | |
10640 | _("Show the mode assumed even when symbols are available."), | |
10641 | NULL, NULL, arm_show_force_mode, | |
10642 | &setarmcmdlist, &showarmcmdlist); | |
10643 | ||
6529d2dd | 10644 | /* Debugging flag. */ |
edefbb7c AC |
10645 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
10646 | _("Set ARM debugging."), | |
10647 | _("Show ARM debugging."), | |
10648 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 10649 | NULL, |
7915a72c | 10650 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 10651 | &setdebuglist, &showdebuglist); |
c906108c | 10652 | } |
72508ac0 PO |
10653 | |
10654 | /* ARM-reversible process record data structures. */ | |
10655 | ||
10656 | #define ARM_INSN_SIZE_BYTES 4 | |
10657 | #define THUMB_INSN_SIZE_BYTES 2 | |
10658 | #define THUMB2_INSN_SIZE_BYTES 4 | |
10659 | ||
10660 | ||
71e396f9 LM |
10661 | /* Position of the bit within a 32-bit ARM instruction |
10662 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
10663 | #define INSN_S_L_BIT_NUM 20 |
10664 | ||
10665 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
10666 | do \ | |
10667 | { \ | |
10668 | unsigned int reg_len = LENGTH; \ | |
10669 | if (reg_len) \ | |
10670 | { \ | |
10671 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
10672 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
10673 | } \ | |
10674 | } \ | |
10675 | while (0) | |
10676 | ||
10677 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
10678 | do \ | |
10679 | { \ | |
10680 | unsigned int mem_len = LENGTH; \ | |
10681 | if (mem_len) \ | |
10682 | { \ | |
10683 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
10684 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
10685 | sizeof(struct arm_mem_r) * LENGTH); \ | |
10686 | } \ | |
10687 | } \ | |
10688 | while (0) | |
10689 | ||
10690 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
10691 | #define INSN_RECORDED(ARM_RECORD) \ | |
10692 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) | |
10693 | ||
10694 | /* ARM memory record structure. */ | |
10695 | struct arm_mem_r | |
10696 | { | |
10697 | uint32_t len; /* Record length. */ | |
bfbbec00 | 10698 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
10699 | }; |
10700 | ||
10701 | /* ARM instruction record contains opcode of current insn | |
10702 | and execution state (before entry to decode_insn()), | |
10703 | contains list of to-be-modified registers and | |
10704 | memory blocks (on return from decode_insn()). */ | |
10705 | ||
10706 | typedef struct insn_decode_record_t | |
10707 | { | |
10708 | struct gdbarch *gdbarch; | |
10709 | struct regcache *regcache; | |
10710 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
10711 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
10712 | uint32_t cond; /* Condition code. */ | |
10713 | uint32_t opcode; /* Insn opcode. */ | |
10714 | uint32_t decode; /* Insn decode bits. */ | |
10715 | uint32_t mem_rec_count; /* No of mem records. */ | |
10716 | uint32_t reg_rec_count; /* No of reg records. */ | |
10717 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
10718 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
10719 | } insn_decode_record; | |
10720 | ||
10721 | ||
10722 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
10723 | ||
10724 | static int | |
10725 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
10726 | { | |
10727 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
10728 | ||
10729 | if (!len) | |
10730 | return 1; | |
10731 | ||
10732 | if (!sbo) | |
10733 | ones = ~ones; | |
10734 | ||
10735 | while (ones) | |
10736 | { | |
10737 | if (!(ones & sbo)) | |
10738 | { | |
10739 | return 0; | |
10740 | } | |
10741 | ones = ones >> 1; | |
10742 | } | |
10743 | return 1; | |
10744 | } | |
10745 | ||
c6ec2b30 OJ |
10746 | enum arm_record_result |
10747 | { | |
10748 | ARM_RECORD_SUCCESS = 0, | |
10749 | ARM_RECORD_FAILURE = 1 | |
10750 | }; | |
10751 | ||
72508ac0 PO |
10752 | typedef enum |
10753 | { | |
10754 | ARM_RECORD_STRH=1, | |
10755 | ARM_RECORD_STRD | |
10756 | } arm_record_strx_t; | |
10757 | ||
10758 | typedef enum | |
10759 | { | |
10760 | ARM_RECORD=1, | |
10761 | THUMB_RECORD, | |
10762 | THUMB2_RECORD | |
10763 | } record_type_t; | |
10764 | ||
10765 | ||
10766 | static int | |
10767 | arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, | |
10768 | uint32_t *record_buf_mem, arm_record_strx_t str_type) | |
10769 | { | |
10770 | ||
10771 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10772 | ULONGEST u_regval[2]= {0}; | |
10773 | ||
10774 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
10775 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
10776 | uint32_t opcode1 = 0; | |
10777 | ||
10778 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10779 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10780 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
10781 | ||
10782 | ||
10783 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10784 | { | |
10785 | /* 1) Handle misc store, immediate offset. */ | |
10786 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10787 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10788 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10789 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
10790 | &u_regval[0]); | |
10791 | if (ARM_PC_REGNUM == reg_src1) | |
10792 | { | |
10793 | /* If R15 was used as Rn, hence current PC+8. */ | |
10794 | u_regval[0] = u_regval[0] + 8; | |
10795 | } | |
10796 | offset_8 = (immed_high << 4) | immed_low; | |
10797 | /* Calculate target store address. */ | |
10798 | if (14 == arm_insn_r->opcode) | |
10799 | { | |
10800 | tgt_mem_addr = u_regval[0] + offset_8; | |
10801 | } | |
10802 | else | |
10803 | { | |
10804 | tgt_mem_addr = u_regval[0] - offset_8; | |
10805 | } | |
10806 | if (ARM_RECORD_STRH == str_type) | |
10807 | { | |
10808 | record_buf_mem[0] = 2; | |
10809 | record_buf_mem[1] = tgt_mem_addr; | |
10810 | arm_insn_r->mem_rec_count = 1; | |
10811 | } | |
10812 | else if (ARM_RECORD_STRD == str_type) | |
10813 | { | |
10814 | record_buf_mem[0] = 4; | |
10815 | record_buf_mem[1] = tgt_mem_addr; | |
10816 | record_buf_mem[2] = 4; | |
10817 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10818 | arm_insn_r->mem_rec_count = 2; | |
10819 | } | |
10820 | } | |
10821 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
10822 | { | |
10823 | /* 2) Store, register offset. */ | |
10824 | /* Get Rm. */ | |
10825 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10826 | /* Get Rn. */ | |
10827 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10828 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10829 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10830 | if (15 == reg_src2) | |
10831 | { | |
10832 | /* If R15 was used as Rn, hence current PC+8. */ | |
10833 | u_regval[0] = u_regval[0] + 8; | |
10834 | } | |
10835 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10836 | if (12 == arm_insn_r->opcode) | |
10837 | { | |
10838 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10839 | } | |
10840 | else | |
10841 | { | |
10842 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10843 | } | |
10844 | if (ARM_RECORD_STRH == str_type) | |
10845 | { | |
10846 | record_buf_mem[0] = 2; | |
10847 | record_buf_mem[1] = tgt_mem_addr; | |
10848 | arm_insn_r->mem_rec_count = 1; | |
10849 | } | |
10850 | else if (ARM_RECORD_STRD == str_type) | |
10851 | { | |
10852 | record_buf_mem[0] = 4; | |
10853 | record_buf_mem[1] = tgt_mem_addr; | |
10854 | record_buf_mem[2] = 4; | |
10855 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10856 | arm_insn_r->mem_rec_count = 2; | |
10857 | } | |
10858 | } | |
10859 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10860 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
10861 | { | |
10862 | /* 3) Store, immediate pre-indexed. */ | |
10863 | /* 5) Store, immediate post-indexed. */ | |
10864 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10865 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10866 | offset_8 = (immed_high << 4) | immed_low; | |
10867 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10868 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10869 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10870 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
10871 | { | |
10872 | tgt_mem_addr = u_regval[0] + offset_8; | |
10873 | } | |
10874 | else | |
10875 | { | |
10876 | tgt_mem_addr = u_regval[0] - offset_8; | |
10877 | } | |
10878 | if (ARM_RECORD_STRH == str_type) | |
10879 | { | |
10880 | record_buf_mem[0] = 2; | |
10881 | record_buf_mem[1] = tgt_mem_addr; | |
10882 | arm_insn_r->mem_rec_count = 1; | |
10883 | } | |
10884 | else if (ARM_RECORD_STRD == str_type) | |
10885 | { | |
10886 | record_buf_mem[0] = 4; | |
10887 | record_buf_mem[1] = tgt_mem_addr; | |
10888 | record_buf_mem[2] = 4; | |
10889 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10890 | arm_insn_r->mem_rec_count = 2; | |
10891 | } | |
10892 | /* Record Rn also as it changes. */ | |
10893 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
10894 | arm_insn_r->reg_rec_count = 1; | |
10895 | } | |
10896 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
10897 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
10898 | { | |
10899 | /* 4) Store, register pre-indexed. */ | |
10900 | /* 6) Store, register post -indexed. */ | |
10901 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10902 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10903 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10904 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10905 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10906 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
10907 | { | |
10908 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10909 | } | |
10910 | else | |
10911 | { | |
10912 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10913 | } | |
10914 | if (ARM_RECORD_STRH == str_type) | |
10915 | { | |
10916 | record_buf_mem[0] = 2; | |
10917 | record_buf_mem[1] = tgt_mem_addr; | |
10918 | arm_insn_r->mem_rec_count = 1; | |
10919 | } | |
10920 | else if (ARM_RECORD_STRD == str_type) | |
10921 | { | |
10922 | record_buf_mem[0] = 4; | |
10923 | record_buf_mem[1] = tgt_mem_addr; | |
10924 | record_buf_mem[2] = 4; | |
10925 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10926 | arm_insn_r->mem_rec_count = 2; | |
10927 | } | |
10928 | /* Record Rn also as it changes. */ | |
10929 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
10930 | arm_insn_r->reg_rec_count = 1; | |
10931 | } | |
10932 | return 0; | |
10933 | } | |
10934 | ||
10935 | /* Handling ARM extension space insns. */ | |
10936 | ||
10937 | static int | |
10938 | arm_record_extension_space (insn_decode_record *arm_insn_r) | |
10939 | { | |
10940 | uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */ | |
10941 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; | |
10942 | uint32_t record_buf[8], record_buf_mem[8]; | |
10943 | uint32_t reg_src1 = 0; | |
10944 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
10945 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10946 | ULONGEST u_regval = 0; | |
10947 | ||
10948 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
10949 | /* Handle unconditional insn extension space. */ | |
10950 | ||
10951 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
10952 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
10953 | if (arm_insn_r->cond) | |
10954 | { | |
10955 | /* PLD has no affect on architectural state, it just affects | |
10956 | the caches. */ | |
10957 | if (5 == ((opcode1 & 0xE0) >> 5)) | |
10958 | { | |
10959 | /* BLX(1) */ | |
10960 | record_buf[0] = ARM_PS_REGNUM; | |
10961 | record_buf[1] = ARM_LR_REGNUM; | |
10962 | arm_insn_r->reg_rec_count = 2; | |
10963 | } | |
10964 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ | |
10965 | } | |
10966 | ||
10967 | ||
10968 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10969 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
10970 | { | |
10971 | ret = -1; | |
10972 | /* Undefined instruction on ARM V5; need to handle if later | |
10973 | versions define it. */ | |
10974 | } | |
10975 | ||
10976 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
10977 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
10978 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
10979 | ||
10980 | /* Handle arithmetic insn extension space. */ | |
10981 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
10982 | && !INSN_RECORDED(arm_insn_r)) | |
10983 | { | |
10984 | /* Handle MLA(S) and MUL(S). */ | |
10985 | if (0 <= insn_op1 && 3 >= insn_op1) | |
10986 | { | |
10987 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10988 | record_buf[1] = ARM_PS_REGNUM; | |
10989 | arm_insn_r->reg_rec_count = 2; | |
10990 | } | |
10991 | else if (4 <= insn_op1 && 15 >= insn_op1) | |
10992 | { | |
10993 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
10994 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10995 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10996 | record_buf[2] = ARM_PS_REGNUM; | |
10997 | arm_insn_r->reg_rec_count = 3; | |
10998 | } | |
10999 | } | |
11000 | ||
11001 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
11002 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
11003 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
11004 | ||
11005 | /* Handle control insn extension space. */ | |
11006 | ||
11007 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
11008 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
11009 | { | |
11010 | if (!bit (arm_insn_r->arm_insn,25)) | |
11011 | { | |
11012 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
11013 | { | |
11014 | if ((0 == insn_op1) || (2 == insn_op1)) | |
11015 | { | |
11016 | /* MRS. */ | |
11017 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11018 | arm_insn_r->reg_rec_count = 1; | |
11019 | } | |
11020 | else if (1 == insn_op1) | |
11021 | { | |
11022 | /* CSPR is going to be changed. */ | |
11023 | record_buf[0] = ARM_PS_REGNUM; | |
11024 | arm_insn_r->reg_rec_count = 1; | |
11025 | } | |
11026 | else if (3 == insn_op1) | |
11027 | { | |
11028 | /* SPSR is going to be changed. */ | |
11029 | /* We need to get SPSR value, which is yet to be done. */ | |
11030 | printf_unfiltered (_("Process record does not support " | |
11031 | "instruction 0x%0x at address %s.\n"), | |
11032 | arm_insn_r->arm_insn, | |
11033 | paddress (arm_insn_r->gdbarch, | |
11034 | arm_insn_r->this_addr)); | |
11035 | return -1; | |
11036 | } | |
11037 | } | |
11038 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11039 | { | |
11040 | if (1 == insn_op1) | |
11041 | { | |
11042 | /* BX. */ | |
11043 | record_buf[0] = ARM_PS_REGNUM; | |
11044 | arm_insn_r->reg_rec_count = 1; | |
11045 | } | |
11046 | else if (3 == insn_op1) | |
11047 | { | |
11048 | /* CLZ. */ | |
11049 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11050 | arm_insn_r->reg_rec_count = 1; | |
11051 | } | |
11052 | } | |
11053 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11054 | { | |
11055 | /* BLX. */ | |
11056 | record_buf[0] = ARM_PS_REGNUM; | |
11057 | record_buf[1] = ARM_LR_REGNUM; | |
11058 | arm_insn_r->reg_rec_count = 2; | |
11059 | } | |
11060 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11061 | { | |
11062 | /* QADD, QSUB, QDADD, QDSUB */ | |
11063 | record_buf[0] = ARM_PS_REGNUM; | |
11064 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11065 | arm_insn_r->reg_rec_count = 2; | |
11066 | } | |
11067 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11068 | { | |
11069 | /* BKPT. */ | |
11070 | record_buf[0] = ARM_PS_REGNUM; | |
11071 | record_buf[1] = ARM_LR_REGNUM; | |
11072 | arm_insn_r->reg_rec_count = 2; | |
11073 | ||
11074 | /* Save SPSR also;how? */ | |
11075 | printf_unfiltered (_("Process record does not support " | |
11076 | "instruction 0x%0x at address %s.\n"), | |
11077 | arm_insn_r->arm_insn, | |
11078 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
11079 | return -1; | |
11080 | } | |
11081 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
11082 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
11083 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
11084 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
11085 | ) | |
11086 | { | |
11087 | if (0 == insn_op1 || 1 == insn_op1) | |
11088 | { | |
11089 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
11090 | /* We dont do optimization for SMULW<y> where we | |
11091 | need only Rd. */ | |
11092 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11093 | record_buf[1] = ARM_PS_REGNUM; | |
11094 | arm_insn_r->reg_rec_count = 2; | |
11095 | } | |
11096 | else if (2 == insn_op1) | |
11097 | { | |
11098 | /* SMLAL<x><y>. */ | |
11099 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11100 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11101 | arm_insn_r->reg_rec_count = 2; | |
11102 | } | |
11103 | else if (3 == insn_op1) | |
11104 | { | |
11105 | /* SMUL<x><y>. */ | |
11106 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11107 | arm_insn_r->reg_rec_count = 1; | |
11108 | } | |
11109 | } | |
11110 | } | |
11111 | else | |
11112 | { | |
11113 | /* MSR : immediate form. */ | |
11114 | if (1 == insn_op1) | |
11115 | { | |
11116 | /* CSPR is going to be changed. */ | |
11117 | record_buf[0] = ARM_PS_REGNUM; | |
11118 | arm_insn_r->reg_rec_count = 1; | |
11119 | } | |
11120 | else if (3 == insn_op1) | |
11121 | { | |
11122 | /* SPSR is going to be changed. */ | |
11123 | /* we need to get SPSR value, which is yet to be done */ | |
11124 | printf_unfiltered (_("Process record does not support " | |
11125 | "instruction 0x%0x at address %s.\n"), | |
11126 | arm_insn_r->arm_insn, | |
11127 | paddress (arm_insn_r->gdbarch, | |
11128 | arm_insn_r->this_addr)); | |
11129 | return -1; | |
11130 | } | |
11131 | } | |
11132 | } | |
11133 | ||
11134 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11135 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
11136 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
11137 | ||
11138 | /* Handle load/store insn extension space. */ | |
11139 | ||
11140 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
11141 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
11142 | && !INSN_RECORDED(arm_insn_r)) | |
11143 | { | |
11144 | /* SWP/SWPB. */ | |
11145 | if (0 == insn_op1) | |
11146 | { | |
11147 | /* These insn, changes register and memory as well. */ | |
11148 | /* SWP or SWPB insn. */ | |
11149 | /* Get memory address given by Rn. */ | |
11150 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11151 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11152 | /* SWP insn ?, swaps word. */ | |
11153 | if (8 == arm_insn_r->opcode) | |
11154 | { | |
11155 | record_buf_mem[0] = 4; | |
11156 | } | |
11157 | else | |
11158 | { | |
11159 | /* SWPB insn, swaps only byte. */ | |
11160 | record_buf_mem[0] = 1; | |
11161 | } | |
11162 | record_buf_mem[1] = u_regval; | |
11163 | arm_insn_r->mem_rec_count = 1; | |
11164 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11165 | arm_insn_r->reg_rec_count = 1; | |
11166 | } | |
11167 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
11168 | { | |
11169 | /* STRH. */ | |
11170 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11171 | ARM_RECORD_STRH); | |
11172 | } | |
11173 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
11174 | { | |
11175 | /* LDRD. */ | |
11176 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11177 | record_buf[1] = record_buf[0] + 1; | |
11178 | arm_insn_r->reg_rec_count = 2; | |
11179 | } | |
11180 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) | |
11181 | { | |
11182 | /* STRD. */ | |
11183 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11184 | ARM_RECORD_STRD); | |
11185 | } | |
11186 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) | |
11187 | { | |
11188 | /* LDRH, LDRSB, LDRSH. */ | |
11189 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11190 | arm_insn_r->reg_rec_count = 1; | |
11191 | } | |
11192 | ||
11193 | } | |
11194 | ||
11195 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
11196 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
11197 | && !INSN_RECORDED(arm_insn_r)) | |
11198 | { | |
11199 | ret = -1; | |
11200 | /* Handle coprocessor insn extension space. */ | |
11201 | } | |
11202 | ||
11203 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
11204 | if (-1 == ret) | |
11205 | printf_unfiltered (_("Process record does not support instruction x%0x " | |
11206 | "at address %s.\n"),arm_insn_r->arm_insn, | |
11207 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
11208 | ||
11209 | ||
11210 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11211 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11212 | ||
11213 | return ret; | |
11214 | } | |
11215 | ||
11216 | /* Handling opcode 000 insns. */ | |
11217 | ||
11218 | static int | |
11219 | arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) | |
11220 | { | |
11221 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11222 | uint32_t record_buf[8], record_buf_mem[8]; | |
11223 | ULONGEST u_regval[2] = {0}; | |
11224 | ||
11225 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
11226 | uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0; | |
11227 | uint32_t opcode1 = 0; | |
11228 | ||
11229 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11230 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11231 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
11232 | ||
11233 | /* Data processing insn /multiply insn. */ | |
11234 | if (9 == arm_insn_r->decode | |
11235 | && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
11236 | || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode))) | |
11237 | { | |
11238 | /* Handle multiply instructions. */ | |
11239 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
11240 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
11241 | { | |
11242 | /* Handle MLA and MUL. */ | |
11243 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11244 | record_buf[1] = ARM_PS_REGNUM; | |
11245 | arm_insn_r->reg_rec_count = 2; | |
11246 | } | |
11247 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
11248 | { | |
11249 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
11250 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11251 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11252 | record_buf[2] = ARM_PS_REGNUM; | |
11253 | arm_insn_r->reg_rec_count = 3; | |
11254 | } | |
11255 | } | |
11256 | else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
11257 | && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode)) | |
11258 | { | |
11259 | /* Handle misc load insns, as 20th bit (L = 1). */ | |
11260 | /* LDR insn has a capability to do branching, if | |
11261 | MOV LR, PC is precceded by LDR insn having Rn as R15 | |
11262 | in that case, it emulates branch and link insn, and hence we | |
11263 | need to save CSPR and PC as well. I am not sure this is right | |
11264 | place; as opcode = 010 LDR insn make this happen, if R15 was | |
11265 | used. */ | |
11266 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
11267 | if (15 != reg_dest) | |
11268 | { | |
11269 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11270 | arm_insn_r->reg_rec_count = 1; | |
11271 | } | |
11272 | else | |
11273 | { | |
11274 | record_buf[0] = reg_dest; | |
11275 | record_buf[1] = ARM_PS_REGNUM; | |
11276 | arm_insn_r->reg_rec_count = 2; | |
11277 | } | |
11278 | } | |
11279 | else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
11280 | && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0) | |
11281 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
11282 | && 2 == bits (arm_insn_r->arm_insn, 20, 21)) | |
11283 | { | |
11284 | /* Handle MSR insn. */ | |
11285 | if (9 == arm_insn_r->opcode) | |
11286 | { | |
11287 | /* CSPR is going to be changed. */ | |
11288 | record_buf[0] = ARM_PS_REGNUM; | |
11289 | arm_insn_r->reg_rec_count = 1; | |
11290 | } | |
11291 | else | |
11292 | { | |
11293 | /* SPSR is going to be changed. */ | |
11294 | /* How to read SPSR value? */ | |
11295 | printf_unfiltered (_("Process record does not support instruction " | |
11296 | "0x%0x at address %s.\n"), | |
11297 | arm_insn_r->arm_insn, | |
11298 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
11299 | return -1; | |
11300 | } | |
11301 | } | |
11302 | else if (9 == arm_insn_r->decode | |
11303 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11304 | && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11305 | { | |
11306 | /* Handling SWP, SWPB. */ | |
11307 | /* These insn, changes register and memory as well. */ | |
11308 | /* SWP or SWPB insn. */ | |
11309 | ||
11310 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11311 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11312 | /* SWP insn ?, swaps word. */ | |
11313 | if (8 == arm_insn_r->opcode) | |
11314 | { | |
11315 | record_buf_mem[0] = 4; | |
11316 | } | |
11317 | else | |
11318 | { | |
11319 | /* SWPB insn, swaps only byte. */ | |
11320 | record_buf_mem[0] = 1; | |
11321 | } | |
11322 | record_buf_mem[1] = u_regval[0]; | |
11323 | arm_insn_r->mem_rec_count = 1; | |
11324 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11325 | arm_insn_r->reg_rec_count = 1; | |
11326 | } | |
11327 | else if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
11328 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11329 | { | |
11330 | /* Handle BLX, branch and link/exchange. */ | |
11331 | if (9 == arm_insn_r->opcode) | |
11332 | { | |
11333 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
11334 | and R14 stores the return address. */ | |
11335 | record_buf[0] = ARM_PS_REGNUM; | |
11336 | record_buf[1] = ARM_LR_REGNUM; | |
11337 | arm_insn_r->reg_rec_count = 2; | |
11338 | } | |
11339 | } | |
11340 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
11341 | { | |
11342 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
11343 | /* CPSR is changed to be executed in ARM state, disabling normal | |
11344 | interrupts, entering abort mode. */ | |
11345 | /* According to high vector configuration PC is set. */ | |
11346 | /* user hit breakpoint and type reverse, in | |
11347 | that case, we need to go back with previous CPSR and | |
11348 | Program Counter. */ | |
11349 | record_buf[0] = ARM_PS_REGNUM; | |
11350 | record_buf[1] = ARM_LR_REGNUM; | |
11351 | arm_insn_r->reg_rec_count = 2; | |
11352 | ||
11353 | /* Save SPSR also; how? */ | |
11354 | printf_unfiltered (_("Process record does not support instruction " | |
11355 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
11356 | paddress (arm_insn_r->gdbarch, | |
11357 | arm_insn_r->this_addr)); | |
11358 | return -1; | |
11359 | } | |
11360 | else if (11 == arm_insn_r->decode | |
11361 | && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11362 | { | |
11363 | /* Handle enhanced store insns and DSP insns (e.g. LDRD). */ | |
11364 | ||
11365 | /* Handle str(x) insn */ | |
11366 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11367 | ARM_RECORD_STRH); | |
11368 | } | |
11369 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
11370 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11371 | { | |
11372 | /* Handle BX, branch and link/exchange. */ | |
11373 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
11374 | record_buf[0] = ARM_PS_REGNUM; | |
11375 | arm_insn_r->reg_rec_count = 1; | |
11376 | } | |
11377 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
11378 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
11379 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
11380 | { | |
11381 | /* Count leading zeros: CLZ. */ | |
11382 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11383 | arm_insn_r->reg_rec_count = 1; | |
11384 | } | |
11385 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
11386 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11387 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
11388 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0) | |
11389 | ) | |
11390 | { | |
11391 | /* Handle MRS insn. */ | |
11392 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11393 | arm_insn_r->reg_rec_count = 1; | |
11394 | } | |
11395 | else if (arm_insn_r->opcode <= 15) | |
11396 | { | |
11397 | /* Normal data processing insns. */ | |
11398 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
11399 | register, which is specified by 13-16 decode. */ | |
11400 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11401 | record_buf[1] = ARM_PS_REGNUM; | |
11402 | arm_insn_r->reg_rec_count = 2; | |
11403 | } | |
11404 | else | |
11405 | { | |
11406 | return -1; | |
11407 | } | |
11408 | ||
11409 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11410 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11411 | return 0; | |
11412 | } | |
11413 | ||
11414 | /* Handling opcode 001 insns. */ | |
11415 | ||
11416 | static int | |
11417 | arm_record_data_proc_imm (insn_decode_record *arm_insn_r) | |
11418 | { | |
11419 | uint32_t record_buf[8], record_buf_mem[8]; | |
11420 | ||
11421 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11422 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11423 | ||
11424 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
11425 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
11426 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
11427 | ) | |
11428 | { | |
11429 | /* Handle MSR insn. */ | |
11430 | if (9 == arm_insn_r->opcode) | |
11431 | { | |
11432 | /* CSPR is going to be changed. */ | |
11433 | record_buf[0] = ARM_PS_REGNUM; | |
11434 | arm_insn_r->reg_rec_count = 1; | |
11435 | } | |
11436 | else | |
11437 | { | |
11438 | /* SPSR is going to be changed. */ | |
11439 | } | |
11440 | } | |
11441 | else if (arm_insn_r->opcode <= 15) | |
11442 | { | |
11443 | /* Normal data processing insns. */ | |
11444 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
11445 | register, which is specified by 13-16 decode. */ | |
11446 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11447 | record_buf[1] = ARM_PS_REGNUM; | |
11448 | arm_insn_r->reg_rec_count = 2; | |
11449 | } | |
11450 | else | |
11451 | { | |
11452 | return -1; | |
11453 | } | |
11454 | ||
11455 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11456 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11457 | return 0; | |
11458 | } | |
11459 | ||
71e396f9 | 11460 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
11461 | |
11462 | static int | |
11463 | arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) | |
11464 | { | |
11465 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11466 | ||
71e396f9 LM |
11467 | uint32_t reg_base , reg_dest; |
11468 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 11469 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
11470 | unsigned char wback; |
11471 | ULONGEST u_regval; | |
72508ac0 | 11472 | |
71e396f9 LM |
11473 | /* Calculate wback. */ |
11474 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
11475 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 11476 | |
71e396f9 LM |
11477 | arm_insn_r->reg_rec_count = 0; |
11478 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
11479 | |
11480 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11481 | { | |
71e396f9 LM |
11482 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
11483 | and LDRT. */ | |
11484 | ||
72508ac0 | 11485 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
11486 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
11487 | ||
11488 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
11489 | preceeds a LDR instruction having R15 as reg_base, it | |
11490 | emulates a branch and link instruction, and hence we need to save | |
11491 | CPSR and PC as well. */ | |
11492 | if (ARM_PC_REGNUM == reg_dest) | |
11493 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11494 | ||
11495 | /* If wback is true, also save the base register, which is going to be | |
11496 | written to. */ | |
11497 | if (wback) | |
11498 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11499 | } |
11500 | else | |
11501 | { | |
71e396f9 LM |
11502 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
11503 | ||
72508ac0 | 11504 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
11505 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
11506 | ||
11507 | /* Handle bit U. */ | |
72508ac0 | 11508 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
11509 | { |
11510 | /* U == 1: Add the offset. */ | |
11511 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
11512 | } | |
72508ac0 | 11513 | else |
71e396f9 LM |
11514 | { |
11515 | /* U == 0: subtract the offset. */ | |
11516 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
11517 | } | |
11518 | ||
11519 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
11520 | bytes. */ | |
11521 | if (bit (arm_insn_r->arm_insn, 22)) | |
11522 | { | |
11523 | /* STRB and STRBT: 1 byte. */ | |
11524 | record_buf_mem[0] = 1; | |
11525 | } | |
11526 | else | |
11527 | { | |
11528 | /* STR and STRT: 4 bytes. */ | |
11529 | record_buf_mem[0] = 4; | |
11530 | } | |
11531 | ||
11532 | /* Handle bit P. */ | |
11533 | if (bit (arm_insn_r->arm_insn, 24)) | |
11534 | record_buf_mem[1] = tgt_mem_addr; | |
11535 | else | |
11536 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 11537 | |
72508ac0 PO |
11538 | arm_insn_r->mem_rec_count = 1; |
11539 | ||
71e396f9 LM |
11540 | /* If wback is true, also save the base register, which is going to be |
11541 | written to. */ | |
11542 | if (wback) | |
11543 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11544 | } |
11545 | ||
11546 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11547 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11548 | return 0; | |
11549 | } | |
11550 | ||
11551 | /* Handling opcode 011 insns. */ | |
11552 | ||
11553 | static int | |
11554 | arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) | |
11555 | { | |
11556 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11557 | ||
11558 | uint32_t shift_imm = 0; | |
11559 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
11560 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
11561 | uint32_t record_buf[8], record_buf_mem[8]; | |
11562 | ||
11563 | LONGEST s_word; | |
11564 | ULONGEST u_regval[2]; | |
11565 | ||
11566 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11567 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11568 | ||
11569 | /* Handle enhanced store insns and LDRD DSP insn, | |
11570 | order begins according to addressing modes for store insns | |
11571 | STRH insn. */ | |
11572 | ||
11573 | /* LDR or STR? */ | |
11574 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11575 | { | |
11576 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
11577 | /* LDR insn has a capability to do branching, if | |
11578 | MOV LR, PC is precedded by LDR insn having Rn as R15 | |
11579 | in that case, it emulates branch and link insn, and hence we | |
11580 | need to save CSPR and PC as well. */ | |
11581 | if (15 != reg_dest) | |
11582 | { | |
11583 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11584 | arm_insn_r->reg_rec_count = 1; | |
11585 | } | |
11586 | else | |
11587 | { | |
11588 | record_buf[0] = reg_dest; | |
11589 | record_buf[1] = ARM_PS_REGNUM; | |
11590 | arm_insn_r->reg_rec_count = 2; | |
11591 | } | |
11592 | } | |
11593 | else | |
11594 | { | |
11595 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
11596 | { | |
11597 | /* Store insn, register offset and register pre-indexed, | |
11598 | register post-indexed. */ | |
11599 | /* Get Rm. */ | |
11600 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11601 | /* Get Rn. */ | |
11602 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11603 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
11604 | , &u_regval[0]); | |
11605 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
11606 | , &u_regval[1]); | |
11607 | if (15 == reg_src2) | |
11608 | { | |
11609 | /* If R15 was used as Rn, hence current PC+8. */ | |
11610 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
11611 | u_regval[0] = u_regval[0] + 8; | |
11612 | } | |
11613 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11614 | /* U == 1. */ | |
11615 | if (bit (arm_insn_r->arm_insn, 23)) | |
11616 | { | |
11617 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11618 | } | |
11619 | else | |
11620 | { | |
11621 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11622 | } | |
11623 | ||
11624 | switch (arm_insn_r->opcode) | |
11625 | { | |
11626 | /* STR. */ | |
11627 | case 8: | |
11628 | case 12: | |
11629 | /* STR. */ | |
11630 | case 9: | |
11631 | case 13: | |
11632 | /* STRT. */ | |
11633 | case 1: | |
11634 | case 5: | |
11635 | /* STR. */ | |
11636 | case 0: | |
11637 | case 4: | |
11638 | record_buf_mem[0] = 4; | |
11639 | break; | |
11640 | ||
11641 | /* STRB. */ | |
11642 | case 10: | |
11643 | case 14: | |
11644 | /* STRB. */ | |
11645 | case 11: | |
11646 | case 15: | |
11647 | /* STRBT. */ | |
11648 | case 3: | |
11649 | case 7: | |
11650 | /* STRB. */ | |
11651 | case 2: | |
11652 | case 6: | |
11653 | record_buf_mem[0] = 1; | |
11654 | break; | |
11655 | ||
11656 | default: | |
11657 | gdb_assert_not_reached ("no decoding pattern found"); | |
11658 | break; | |
11659 | } | |
11660 | record_buf_mem[1] = tgt_mem_addr; | |
11661 | arm_insn_r->mem_rec_count = 1; | |
11662 | ||
11663 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
11664 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
11665 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
11666 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
11667 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
11668 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
11669 | ) | |
11670 | { | |
11671 | /* Rn is going to be changed in pre-indexed mode and | |
11672 | post-indexed mode as well. */ | |
11673 | record_buf[0] = reg_src2; | |
11674 | arm_insn_r->reg_rec_count = 1; | |
11675 | } | |
11676 | } | |
11677 | else | |
11678 | { | |
11679 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
11680 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
11681 | /* Get Rm. */ | |
11682 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11683 | /* Get Rn. */ | |
11684 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11685 | /* Get shift_imm. */ | |
11686 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
11687 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11688 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
11689 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11690 | /* Offset_12 used as shift. */ | |
11691 | switch (offset_12) | |
11692 | { | |
11693 | case 0: | |
11694 | /* Offset_12 used as index. */ | |
11695 | offset_12 = u_regval[0] << shift_imm; | |
11696 | break; | |
11697 | ||
11698 | case 1: | |
11699 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
11700 | break; | |
11701 | ||
11702 | case 2: | |
11703 | if (!shift_imm) | |
11704 | { | |
11705 | if (bit (u_regval[0], 31)) | |
11706 | { | |
11707 | offset_12 = 0xFFFFFFFF; | |
11708 | } | |
11709 | else | |
11710 | { | |
11711 | offset_12 = 0; | |
11712 | } | |
11713 | } | |
11714 | else | |
11715 | { | |
11716 | /* This is arithmetic shift. */ | |
11717 | offset_12 = s_word >> shift_imm; | |
11718 | } | |
11719 | break; | |
11720 | ||
11721 | case 3: | |
11722 | if (!shift_imm) | |
11723 | { | |
11724 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
11725 | &u_regval[1]); | |
11726 | /* Get C flag value and shift it by 31. */ | |
11727 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
11728 | | (u_regval[0]) >> 1); | |
11729 | } | |
11730 | else | |
11731 | { | |
11732 | offset_12 = (u_regval[0] >> shift_imm) \ | |
11733 | | (u_regval[0] << | |
11734 | (sizeof(uint32_t) - shift_imm)); | |
11735 | } | |
11736 | break; | |
11737 | ||
11738 | default: | |
11739 | gdb_assert_not_reached ("no decoding pattern found"); | |
11740 | break; | |
11741 | } | |
11742 | ||
11743 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11744 | /* bit U set. */ | |
11745 | if (bit (arm_insn_r->arm_insn, 23)) | |
11746 | { | |
11747 | tgt_mem_addr = u_regval[1] + offset_12; | |
11748 | } | |
11749 | else | |
11750 | { | |
11751 | tgt_mem_addr = u_regval[1] - offset_12; | |
11752 | } | |
11753 | ||
11754 | switch (arm_insn_r->opcode) | |
11755 | { | |
11756 | /* STR. */ | |
11757 | case 8: | |
11758 | case 12: | |
11759 | /* STR. */ | |
11760 | case 9: | |
11761 | case 13: | |
11762 | /* STRT. */ | |
11763 | case 1: | |
11764 | case 5: | |
11765 | /* STR. */ | |
11766 | case 0: | |
11767 | case 4: | |
11768 | record_buf_mem[0] = 4; | |
11769 | break; | |
11770 | ||
11771 | /* STRB. */ | |
11772 | case 10: | |
11773 | case 14: | |
11774 | /* STRB. */ | |
11775 | case 11: | |
11776 | case 15: | |
11777 | /* STRBT. */ | |
11778 | case 3: | |
11779 | case 7: | |
11780 | /* STRB. */ | |
11781 | case 2: | |
11782 | case 6: | |
11783 | record_buf_mem[0] = 1; | |
11784 | break; | |
11785 | ||
11786 | default: | |
11787 | gdb_assert_not_reached ("no decoding pattern found"); | |
11788 | break; | |
11789 | } | |
11790 | record_buf_mem[1] = tgt_mem_addr; | |
11791 | arm_insn_r->mem_rec_count = 1; | |
11792 | ||
11793 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
11794 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
11795 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
11796 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
11797 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
11798 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
11799 | ) | |
11800 | { | |
11801 | /* Rn is going to be changed in register scaled pre-indexed | |
11802 | mode,and scaled post indexed mode. */ | |
11803 | record_buf[0] = reg_src2; | |
11804 | arm_insn_r->reg_rec_count = 1; | |
11805 | } | |
11806 | } | |
11807 | } | |
11808 | ||
11809 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11810 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11811 | return 0; | |
11812 | } | |
11813 | ||
71e396f9 | 11814 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
11815 | |
11816 | static int | |
11817 | arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) | |
11818 | { | |
11819 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
11820 | uint32_t register_count = 0, register_bits; |
11821 | uint32_t reg_base, addr_mode; | |
72508ac0 | 11822 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
11823 | uint32_t wback; |
11824 | ULONGEST u_regval; | |
72508ac0 | 11825 | |
71e396f9 LM |
11826 | /* Fetch the list of registers. */ |
11827 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
11828 | arm_insn_r->reg_rec_count = 0; | |
11829 | ||
11830 | /* Fetch the base register that contains the address we are loading data | |
11831 | to. */ | |
11832 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11833 | |
71e396f9 LM |
11834 | /* Calculate wback. */ |
11835 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
11836 | |
11837 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11838 | { | |
71e396f9 | 11839 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 11840 | |
71e396f9 | 11841 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 11842 | while (register_bits) |
71e396f9 LM |
11843 | { |
11844 | if (register_bits & 0x00000001) | |
11845 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
11846 | register_bits = register_bits >> 1; | |
11847 | register_count++; | |
11848 | } | |
72508ac0 | 11849 | |
71e396f9 LM |
11850 | |
11851 | /* If wback is true, also save the base register, which is going to be | |
11852 | written to. */ | |
11853 | if (wback) | |
11854 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
11855 | ||
11856 | /* Save the CPSR register. */ | |
11857 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
11858 | } |
11859 | else | |
11860 | { | |
71e396f9 | 11861 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 11862 | |
71e396f9 LM |
11863 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
11864 | ||
11865 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
11866 | ||
11867 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 11868 | while (register_bits) |
71e396f9 LM |
11869 | { |
11870 | if (register_bits & 0x00000001) | |
11871 | register_count++; | |
11872 | register_bits = register_bits >> 1; | |
11873 | } | |
72508ac0 PO |
11874 | |
11875 | switch (addr_mode) | |
71e396f9 LM |
11876 | { |
11877 | /* STMDA (STMED): Decrement after. */ | |
11878 | case 0: | |
11879 | record_buf_mem[1] = (uint32_t) u_regval | |
11880 | - register_count * INT_REGISTER_SIZE + 4; | |
11881 | break; | |
11882 | /* STM (STMIA, STMEA): Increment after. */ | |
11883 | case 1: | |
11884 | record_buf_mem[1] = (uint32_t) u_regval; | |
11885 | break; | |
11886 | /* STMDB (STMFD): Decrement before. */ | |
11887 | case 2: | |
11888 | record_buf_mem[1] = (uint32_t) u_regval | |
11889 | - register_count * INT_REGISTER_SIZE; | |
11890 | break; | |
11891 | /* STMIB (STMFA): Increment before. */ | |
11892 | case 3: | |
11893 | record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE; | |
11894 | break; | |
11895 | default: | |
11896 | gdb_assert_not_reached ("no decoding pattern found"); | |
11897 | break; | |
11898 | } | |
72508ac0 | 11899 | |
71e396f9 LM |
11900 | record_buf_mem[0] = register_count * INT_REGISTER_SIZE; |
11901 | arm_insn_r->mem_rec_count = 1; | |
11902 | ||
11903 | /* If wback is true, also save the base register, which is going to be | |
11904 | written to. */ | |
11905 | if (wback) | |
11906 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11907 | } |
11908 | ||
11909 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11910 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11911 | return 0; | |
11912 | } | |
11913 | ||
11914 | /* Handling opcode 101 insns. */ | |
11915 | ||
11916 | static int | |
11917 | arm_record_b_bl (insn_decode_record *arm_insn_r) | |
11918 | { | |
11919 | uint32_t record_buf[8]; | |
11920 | ||
11921 | /* Handle B, BL, BLX(1) insns. */ | |
11922 | /* B simply branches so we do nothing here. */ | |
11923 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
11924 | extension space. */ | |
11925 | if (bit (arm_insn_r->arm_insn, 24)) | |
11926 | { | |
11927 | record_buf[0] = ARM_LR_REGNUM; | |
11928 | arm_insn_r->reg_rec_count = 1; | |
11929 | } | |
11930 | ||
11931 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11932 | ||
11933 | return 0; | |
11934 | } | |
11935 | ||
11936 | /* Handling opcode 110 insns. */ | |
11937 | ||
11938 | static int | |
c6ec2b30 | 11939 | arm_record_unsupported_insn (insn_decode_record *arm_insn_r) |
72508ac0 PO |
11940 | { |
11941 | printf_unfiltered (_("Process record does not support instruction " | |
11942 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
11943 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
11944 | ||
11945 | return -1; | |
11946 | } | |
11947 | ||
5a578da5 OJ |
11948 | /* Record handler for vector data transfer instructions. */ |
11949 | ||
11950 | static int | |
11951 | arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) | |
11952 | { | |
11953 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
11954 | uint32_t record_buf[4]; | |
11955 | ||
11956 | const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); | |
11957 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); | |
11958 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
11959 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
11960 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
11961 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
11962 | ||
11963 | /* Handle VMOV instruction. */ | |
11964 | if (bit_l && bit_c) | |
11965 | { | |
11966 | record_buf[0] = reg_t; | |
11967 | arm_insn_r->reg_rec_count = 1; | |
11968 | } | |
11969 | else if (bit_l && !bit_c) | |
11970 | { | |
11971 | /* Handle VMOV instruction. */ | |
11972 | if (bits_a == 0x00) | |
11973 | { | |
11974 | if (bit (arm_insn_r->arm_insn, 20)) | |
11975 | record_buf[0] = reg_t; | |
11976 | else | |
11977 | record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | | |
11978 | (reg_v << 1)); | |
11979 | ||
11980 | arm_insn_r->reg_rec_count = 1; | |
11981 | } | |
11982 | /* Handle VMRS instruction. */ | |
11983 | else if (bits_a == 0x07) | |
11984 | { | |
11985 | if (reg_t == 15) | |
11986 | reg_t = ARM_PS_REGNUM; | |
11987 | ||
11988 | record_buf[0] = reg_t; | |
11989 | arm_insn_r->reg_rec_count = 1; | |
11990 | } | |
11991 | } | |
11992 | else if (!bit_l && !bit_c) | |
11993 | { | |
11994 | /* Handle VMOV instruction. */ | |
11995 | if (bits_a == 0x00) | |
11996 | { | |
11997 | if (bit (arm_insn_r->arm_insn, 20)) | |
11998 | record_buf[0] = reg_t; | |
11999 | else | |
12000 | record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | | |
12001 | (reg_v << 1)); | |
12002 | ||
12003 | arm_insn_r->reg_rec_count = 1; | |
12004 | } | |
12005 | /* Handle VMSR instruction. */ | |
12006 | else if (bits_a == 0x07) | |
12007 | { | |
12008 | record_buf[0] = ARM_FPSCR_REGNUM; | |
12009 | arm_insn_r->reg_rec_count = 1; | |
12010 | } | |
12011 | } | |
12012 | else if (!bit_l && bit_c) | |
12013 | { | |
12014 | /* Handle VMOV instruction. */ | |
12015 | if (!(bits_a & 0x04)) | |
12016 | { | |
12017 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
12018 | + ARM_D0_REGNUM; | |
12019 | arm_insn_r->reg_rec_count = 1; | |
12020 | } | |
12021 | /* Handle VDUP instruction. */ | |
12022 | else | |
12023 | { | |
12024 | if (bit (arm_insn_r->arm_insn, 21)) | |
12025 | { | |
12026 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12027 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12028 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
12029 | arm_insn_r->reg_rec_count = 2; | |
12030 | } | |
12031 | else | |
12032 | { | |
12033 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12034 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12035 | arm_insn_r->reg_rec_count = 1; | |
12036 | } | |
12037 | } | |
12038 | } | |
12039 | ||
12040 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12041 | return 0; | |
12042 | } | |
12043 | ||
f20f80dd OJ |
12044 | /* Record handler for extension register load/store instructions. */ |
12045 | ||
12046 | static int | |
12047 | arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) | |
12048 | { | |
12049 | uint32_t opcode, single_reg; | |
12050 | uint8_t op_vldm_vstm; | |
12051 | uint32_t record_buf[8], record_buf_mem[128]; | |
12052 | ULONGEST u_regval = 0; | |
12053 | ||
12054 | struct regcache *reg_cache = arm_insn_r->regcache; | |
12055 | const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); | |
12056 | ||
12057 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
12058 | single_reg = bit (arm_insn_r->arm_insn, 8); | |
12059 | op_vldm_vstm = opcode & 0x1b; | |
12060 | ||
12061 | /* Handle VMOV instructions. */ | |
12062 | if ((opcode & 0x1e) == 0x04) | |
12063 | { | |
12064 | if (bit (arm_insn_r->arm_insn, 4)) | |
12065 | { | |
12066 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12067 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12068 | arm_insn_r->reg_rec_count = 2; | |
12069 | } | |
12070 | else | |
12071 | { | |
12072 | uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) | |
12073 | | bit (arm_insn_r->arm_insn, 5); | |
12074 | ||
12075 | if (!single_reg) | |
12076 | { | |
12077 | record_buf[0] = num_regs + reg_m; | |
12078 | record_buf[1] = num_regs + reg_m + 1; | |
12079 | arm_insn_r->reg_rec_count = 2; | |
12080 | } | |
12081 | else | |
12082 | { | |
12083 | record_buf[0] = reg_m + ARM_D0_REGNUM; | |
12084 | arm_insn_r->reg_rec_count = 1; | |
12085 | } | |
12086 | } | |
12087 | } | |
12088 | /* Handle VSTM and VPUSH instructions. */ | |
12089 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
12090 | || op_vldm_vstm == 0x12) | |
12091 | { | |
12092 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
12093 | uint32_t memory_index = 0; | |
12094 | ||
12095 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12096 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12097 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
12098 | imm_off32 = imm_off8 << 24; | |
12099 | memory_count = imm_off8; | |
12100 | ||
12101 | if (bit (arm_insn_r->arm_insn, 23)) | |
12102 | start_address = u_regval; | |
12103 | else | |
12104 | start_address = u_regval - imm_off32; | |
12105 | ||
12106 | if (bit (arm_insn_r->arm_insn, 21)) | |
12107 | { | |
12108 | record_buf[0] = reg_rn; | |
12109 | arm_insn_r->reg_rec_count = 1; | |
12110 | } | |
12111 | ||
12112 | while (memory_count > 0) | |
12113 | { | |
12114 | if (!single_reg) | |
12115 | { | |
12116 | record_buf_mem[memory_index] = start_address; | |
12117 | record_buf_mem[memory_index + 1] = 4; | |
12118 | start_address = start_address + 4; | |
12119 | memory_index = memory_index + 2; | |
12120 | } | |
12121 | else | |
12122 | { | |
12123 | record_buf_mem[memory_index] = start_address; | |
12124 | record_buf_mem[memory_index + 1] = 4; | |
12125 | record_buf_mem[memory_index + 2] = start_address + 4; | |
12126 | record_buf_mem[memory_index + 3] = 4; | |
12127 | start_address = start_address + 8; | |
12128 | memory_index = memory_index + 4; | |
12129 | } | |
12130 | memory_count--; | |
12131 | } | |
12132 | arm_insn_r->mem_rec_count = (memory_index >> 1); | |
12133 | } | |
12134 | /* Handle VLDM instructions. */ | |
12135 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
12136 | || op_vldm_vstm == 0x13) | |
12137 | { | |
12138 | uint32_t reg_count, reg_vd; | |
12139 | uint32_t reg_index = 0; | |
12140 | ||
12141 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12142 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
12143 | ||
12144 | if (single_reg) | |
12145 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
12146 | else | |
12147 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
12148 | ||
12149 | if (bit (arm_insn_r->arm_insn, 21)) | |
12150 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); | |
12151 | ||
12152 | while (reg_count > 0) | |
12153 | { | |
12154 | if (single_reg) | |
12155 | record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; | |
12156 | else | |
12157 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
12158 | ||
12159 | reg_count--; | |
12160 | } | |
12161 | arm_insn_r->reg_rec_count = reg_index; | |
12162 | } | |
12163 | /* VSTR Vector store register. */ | |
12164 | else if ((opcode & 0x13) == 0x10) | |
12165 | { | |
12166 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
12167 | uint32_t memory_index = 0; | |
12168 | ||
12169 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12170 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12171 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
12172 | imm_off32 = imm_off8 << 24; | |
12173 | memory_count = imm_off8; | |
12174 | ||
12175 | if (bit (arm_insn_r->arm_insn, 23)) | |
12176 | start_address = u_regval + imm_off32; | |
12177 | else | |
12178 | start_address = u_regval - imm_off32; | |
12179 | ||
12180 | if (single_reg) | |
12181 | { | |
12182 | record_buf_mem[memory_index] = start_address; | |
12183 | record_buf_mem[memory_index + 1] = 4; | |
12184 | arm_insn_r->mem_rec_count = 1; | |
12185 | } | |
12186 | else | |
12187 | { | |
12188 | record_buf_mem[memory_index] = start_address; | |
12189 | record_buf_mem[memory_index + 1] = 4; | |
12190 | record_buf_mem[memory_index + 2] = start_address + 4; | |
12191 | record_buf_mem[memory_index + 3] = 4; | |
12192 | arm_insn_r->mem_rec_count = 2; | |
12193 | } | |
12194 | } | |
12195 | /* VLDR Vector load register. */ | |
12196 | else if ((opcode & 0x13) == 0x11) | |
12197 | { | |
12198 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12199 | ||
12200 | if (!single_reg) | |
12201 | { | |
12202 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
12203 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
12204 | } | |
12205 | else | |
12206 | { | |
12207 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
12208 | record_buf[0] = num_regs + reg_vd; | |
12209 | } | |
12210 | arm_insn_r->reg_rec_count = 1; | |
12211 | } | |
12212 | ||
12213 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12214 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12215 | return 0; | |
12216 | } | |
12217 | ||
851f26ae OJ |
12218 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
12219 | ||
12220 | static int | |
12221 | arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) | |
12222 | { | |
12223 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
12224 | uint32_t record_buf[4]; | |
12225 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
12226 | enum insn_types curr_insn_type = INSN_INV; | |
12227 | ||
12228 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12229 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
12230 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12231 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
12232 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
12233 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
12234 | opc1 = opc1 & 0x04; | |
12235 | ||
12236 | /* Handle VMLA, VMLS. */ | |
12237 | if (opc1 == 0x00) | |
12238 | { | |
12239 | if (bit (arm_insn_r->arm_insn, 10)) | |
12240 | { | |
12241 | if (bit (arm_insn_r->arm_insn, 6)) | |
12242 | curr_insn_type = INSN_T0; | |
12243 | else | |
12244 | curr_insn_type = INSN_T1; | |
12245 | } | |
12246 | else | |
12247 | { | |
12248 | if (dp_op_sz) | |
12249 | curr_insn_type = INSN_T1; | |
12250 | else | |
12251 | curr_insn_type = INSN_T2; | |
12252 | } | |
12253 | } | |
12254 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
12255 | else if (opc1 == 0x01) | |
12256 | { | |
12257 | if (dp_op_sz) | |
12258 | curr_insn_type = INSN_T1; | |
12259 | else | |
12260 | curr_insn_type = INSN_T2; | |
12261 | } | |
12262 | /* Handle VMUL. */ | |
12263 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
12264 | { | |
12265 | if (bit (arm_insn_r->arm_insn, 10)) | |
12266 | { | |
12267 | if (bit (arm_insn_r->arm_insn, 6)) | |
12268 | curr_insn_type = INSN_T0; | |
12269 | else | |
12270 | curr_insn_type = INSN_T1; | |
12271 | } | |
12272 | else | |
12273 | { | |
12274 | if (dp_op_sz) | |
12275 | curr_insn_type = INSN_T1; | |
12276 | else | |
12277 | curr_insn_type = INSN_T2; | |
12278 | } | |
12279 | } | |
12280 | /* Handle VADD, VSUB. */ | |
12281 | else if (opc1 == 0x03) | |
12282 | { | |
12283 | if (!bit (arm_insn_r->arm_insn, 9)) | |
12284 | { | |
12285 | if (bit (arm_insn_r->arm_insn, 6)) | |
12286 | curr_insn_type = INSN_T0; | |
12287 | else | |
12288 | curr_insn_type = INSN_T1; | |
12289 | } | |
12290 | else | |
12291 | { | |
12292 | if (dp_op_sz) | |
12293 | curr_insn_type = INSN_T1; | |
12294 | else | |
12295 | curr_insn_type = INSN_T2; | |
12296 | } | |
12297 | } | |
12298 | /* Handle VDIV. */ | |
12299 | else if (opc1 == 0x0b) | |
12300 | { | |
12301 | if (dp_op_sz) | |
12302 | curr_insn_type = INSN_T1; | |
12303 | else | |
12304 | curr_insn_type = INSN_T2; | |
12305 | } | |
12306 | /* Handle all other vfp data processing instructions. */ | |
12307 | else if (opc1 == 0x0b) | |
12308 | { | |
12309 | /* Handle VMOV. */ | |
12310 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
12311 | { | |
12312 | if (bit (arm_insn_r->arm_insn, 4)) | |
12313 | { | |
12314 | if (bit (arm_insn_r->arm_insn, 6)) | |
12315 | curr_insn_type = INSN_T0; | |
12316 | else | |
12317 | curr_insn_type = INSN_T1; | |
12318 | } | |
12319 | else | |
12320 | { | |
12321 | if (dp_op_sz) | |
12322 | curr_insn_type = INSN_T1; | |
12323 | else | |
12324 | curr_insn_type = INSN_T2; | |
12325 | } | |
12326 | } | |
12327 | /* Handle VNEG and VABS. */ | |
12328 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
12329 | || (opc2 == 0x00 && opc3 == 0x03)) | |
12330 | { | |
12331 | if (!bit (arm_insn_r->arm_insn, 11)) | |
12332 | { | |
12333 | if (bit (arm_insn_r->arm_insn, 6)) | |
12334 | curr_insn_type = INSN_T0; | |
12335 | else | |
12336 | curr_insn_type = INSN_T1; | |
12337 | } | |
12338 | else | |
12339 | { | |
12340 | if (dp_op_sz) | |
12341 | curr_insn_type = INSN_T1; | |
12342 | else | |
12343 | curr_insn_type = INSN_T2; | |
12344 | } | |
12345 | } | |
12346 | /* Handle VSQRT. */ | |
12347 | else if (opc2 == 0x01 && opc3 == 0x03) | |
12348 | { | |
12349 | if (dp_op_sz) | |
12350 | curr_insn_type = INSN_T1; | |
12351 | else | |
12352 | curr_insn_type = INSN_T2; | |
12353 | } | |
12354 | /* Handle VCVT. */ | |
12355 | else if (opc2 == 0x07 && opc3 == 0x03) | |
12356 | { | |
12357 | if (!dp_op_sz) | |
12358 | curr_insn_type = INSN_T1; | |
12359 | else | |
12360 | curr_insn_type = INSN_T2; | |
12361 | } | |
12362 | else if (opc3 & 0x01) | |
12363 | { | |
12364 | /* Handle VCVT. */ | |
12365 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
12366 | { | |
12367 | if (!bit (arm_insn_r->arm_insn, 18)) | |
12368 | curr_insn_type = INSN_T2; | |
12369 | else | |
12370 | { | |
12371 | if (dp_op_sz) | |
12372 | curr_insn_type = INSN_T1; | |
12373 | else | |
12374 | curr_insn_type = INSN_T2; | |
12375 | } | |
12376 | } | |
12377 | /* Handle VCVT. */ | |
12378 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
12379 | { | |
12380 | if (dp_op_sz) | |
12381 | curr_insn_type = INSN_T1; | |
12382 | else | |
12383 | curr_insn_type = INSN_T2; | |
12384 | } | |
12385 | /* Handle VCVTB, VCVTT. */ | |
12386 | else if ((opc2 & 0x0e) == 0x02) | |
12387 | curr_insn_type = INSN_T2; | |
12388 | /* Handle VCMP, VCMPE. */ | |
12389 | else if ((opc2 & 0x0e) == 0x04) | |
12390 | curr_insn_type = INSN_T3; | |
12391 | } | |
12392 | } | |
12393 | ||
12394 | switch (curr_insn_type) | |
12395 | { | |
12396 | case INSN_T0: | |
12397 | reg_vd = reg_vd | (bit_d << 4); | |
12398 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12399 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
12400 | arm_insn_r->reg_rec_count = 2; | |
12401 | break; | |
12402 | ||
12403 | case INSN_T1: | |
12404 | reg_vd = reg_vd | (bit_d << 4); | |
12405 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12406 | arm_insn_r->reg_rec_count = 1; | |
12407 | break; | |
12408 | ||
12409 | case INSN_T2: | |
12410 | reg_vd = (reg_vd << 1) | bit_d; | |
12411 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12412 | arm_insn_r->reg_rec_count = 1; | |
12413 | break; | |
12414 | ||
12415 | case INSN_T3: | |
12416 | record_buf[0] = ARM_FPSCR_REGNUM; | |
12417 | arm_insn_r->reg_rec_count = 1; | |
12418 | break; | |
12419 | ||
12420 | default: | |
12421 | gdb_assert_not_reached ("no decoding pattern found"); | |
12422 | break; | |
12423 | } | |
12424 | ||
12425 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12426 | return 0; | |
12427 | } | |
12428 | ||
60cc5e93 OJ |
12429 | /* Handling opcode 110 insns. */ |
12430 | ||
12431 | static int | |
12432 | arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) | |
12433 | { | |
12434 | uint32_t op, op1, op1_sbit, op1_ebit, coproc; | |
12435 | ||
12436 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
12437 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
12438 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12439 | ||
12440 | if ((coproc & 0x0e) == 0x0a) | |
12441 | { | |
12442 | /* Handle extension register ld/st instructions. */ | |
12443 | if (!(op1 & 0x20)) | |
f20f80dd | 12444 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12445 | |
12446 | /* 64-bit transfers between arm core and extension registers. */ | |
12447 | if ((op1 & 0x3e) == 0x04) | |
f20f80dd | 12448 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12449 | } |
12450 | else | |
12451 | { | |
12452 | /* Handle coprocessor ld/st instructions. */ | |
12453 | if (!(op1 & 0x3a)) | |
12454 | { | |
12455 | /* Store. */ | |
12456 | if (!op1_ebit) | |
12457 | return arm_record_unsupported_insn (arm_insn_r); | |
12458 | else | |
12459 | /* Load. */ | |
12460 | return arm_record_unsupported_insn (arm_insn_r); | |
12461 | } | |
12462 | ||
12463 | /* Move to coprocessor from two arm core registers. */ | |
12464 | if (op1 == 0x4) | |
12465 | return arm_record_unsupported_insn (arm_insn_r); | |
12466 | ||
12467 | /* Move to two arm core registers from coprocessor. */ | |
12468 | if (op1 == 0x5) | |
12469 | { | |
12470 | uint32_t reg_t[2]; | |
12471 | ||
12472 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12473 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12474 | arm_insn_r->reg_rec_count = 2; | |
12475 | ||
12476 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); | |
12477 | return 0; | |
12478 | } | |
12479 | } | |
12480 | return arm_record_unsupported_insn (arm_insn_r); | |
12481 | } | |
12482 | ||
72508ac0 PO |
12483 | /* Handling opcode 111 insns. */ |
12484 | ||
12485 | static int | |
12486 | arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) | |
12487 | { | |
60cc5e93 | 12488 | uint32_t op, op1_sbit, op1_ebit, coproc; |
72508ac0 PO |
12489 | struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); |
12490 | struct regcache *reg_cache = arm_insn_r->regcache; | |
97dfe206 | 12491 | ULONGEST u_regval = 0; |
72508ac0 PO |
12492 | |
12493 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 OJ |
12494 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
12495 | op1_sbit = bit (arm_insn_r->arm_insn, 24); | |
12496 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12497 | op = bit (arm_insn_r->arm_insn, 4); | |
97dfe206 OJ |
12498 | |
12499 | /* Handle arm SWI/SVC system call instructions. */ | |
60cc5e93 | 12500 | if (op1_sbit) |
97dfe206 OJ |
12501 | { |
12502 | if (tdep->arm_syscall_record != NULL) | |
12503 | { | |
12504 | ULONGEST svc_operand, svc_number; | |
12505 | ||
12506 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); | |
12507 | ||
12508 | if (svc_operand) /* OABI. */ | |
12509 | svc_number = svc_operand - 0x900000; | |
12510 | else /* EABI. */ | |
12511 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
12512 | ||
60cc5e93 | 12513 | return tdep->arm_syscall_record (reg_cache, svc_number); |
97dfe206 OJ |
12514 | } |
12515 | else | |
12516 | { | |
12517 | printf_unfiltered (_("no syscall record support\n")); | |
60cc5e93 | 12518 | return -1; |
97dfe206 OJ |
12519 | } |
12520 | } | |
60cc5e93 OJ |
12521 | |
12522 | if ((coproc & 0x0e) == 0x0a) | |
12523 | { | |
12524 | /* VFP data-processing instructions. */ | |
12525 | if (!op1_sbit && !op) | |
851f26ae | 12526 | return arm_record_vfp_data_proc_insn (arm_insn_r); |
60cc5e93 OJ |
12527 | |
12528 | /* Advanced SIMD, VFP instructions. */ | |
12529 | if (!op1_sbit && op) | |
5a578da5 | 12530 | return arm_record_vdata_transfer_insn (arm_insn_r); |
60cc5e93 | 12531 | } |
97dfe206 OJ |
12532 | else |
12533 | { | |
60cc5e93 OJ |
12534 | /* Coprocessor data operations. */ |
12535 | if (!op1_sbit && !op) | |
12536 | return arm_record_unsupported_insn (arm_insn_r); | |
12537 | ||
12538 | /* Move to Coprocessor from ARM core register. */ | |
12539 | if (!op1_sbit && !op1_ebit && op) | |
12540 | return arm_record_unsupported_insn (arm_insn_r); | |
12541 | ||
12542 | /* Move to arm core register from coprocessor. */ | |
12543 | if (!op1_sbit && op1_ebit && op) | |
12544 | { | |
12545 | uint32_t record_buf[1]; | |
12546 | ||
12547 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12548 | if (record_buf[0] == 15) | |
12549 | record_buf[0] = ARM_PS_REGNUM; | |
12550 | ||
12551 | arm_insn_r->reg_rec_count = 1; | |
12552 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
12553 | record_buf); | |
12554 | return 0; | |
12555 | } | |
97dfe206 | 12556 | } |
72508ac0 | 12557 | |
60cc5e93 | 12558 | return arm_record_unsupported_insn (arm_insn_r); |
72508ac0 PO |
12559 | } |
12560 | ||
12561 | /* Handling opcode 000 insns. */ | |
12562 | ||
12563 | static int | |
12564 | thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) | |
12565 | { | |
12566 | uint32_t record_buf[8]; | |
12567 | uint32_t reg_src1 = 0; | |
12568 | ||
12569 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12570 | ||
12571 | record_buf[0] = ARM_PS_REGNUM; | |
12572 | record_buf[1] = reg_src1; | |
12573 | thumb_insn_r->reg_rec_count = 2; | |
12574 | ||
12575 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12576 | ||
12577 | return 0; | |
12578 | } | |
12579 | ||
12580 | ||
12581 | /* Handling opcode 001 insns. */ | |
12582 | ||
12583 | static int | |
12584 | thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) | |
12585 | { | |
12586 | uint32_t record_buf[8]; | |
12587 | uint32_t reg_src1 = 0; | |
12588 | ||
12589 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12590 | ||
12591 | record_buf[0] = ARM_PS_REGNUM; | |
12592 | record_buf[1] = reg_src1; | |
12593 | thumb_insn_r->reg_rec_count = 2; | |
12594 | ||
12595 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12596 | ||
12597 | return 0; | |
12598 | } | |
12599 | ||
12600 | /* Handling opcode 010 insns. */ | |
12601 | ||
12602 | static int | |
12603 | thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) | |
12604 | { | |
12605 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12606 | uint32_t record_buf[8], record_buf_mem[8]; | |
12607 | ||
12608 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
12609 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
12610 | ||
12611 | ULONGEST u_regval[2] = {0}; | |
12612 | ||
12613 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
12614 | ||
12615 | if (bit (thumb_insn_r->arm_insn, 12)) | |
12616 | { | |
12617 | /* Handle load/store register offset. */ | |
12618 | opcode2 = bits (thumb_insn_r->arm_insn, 9, 10); | |
12619 | if (opcode2 >= 12 && opcode2 <= 15) | |
12620 | { | |
12621 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
12622 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
12623 | record_buf[0] = reg_src1; | |
12624 | thumb_insn_r->reg_rec_count = 1; | |
12625 | } | |
12626 | else if (opcode2 >= 8 && opcode2 <= 10) | |
12627 | { | |
12628 | /* STR(2), STRB(2), STRH(2) . */ | |
12629 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12630 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
12631 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
12632 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12633 | if (8 == opcode2) | |
12634 | record_buf_mem[0] = 4; /* STR (2). */ | |
12635 | else if (10 == opcode2) | |
12636 | record_buf_mem[0] = 1; /* STRB (2). */ | |
12637 | else if (9 == opcode2) | |
12638 | record_buf_mem[0] = 2; /* STRH (2). */ | |
12639 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
12640 | thumb_insn_r->mem_rec_count = 1; | |
12641 | } | |
12642 | } | |
12643 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
12644 | { | |
12645 | /* Handle load from literal pool. */ | |
12646 | /* LDR(3). */ | |
12647 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12648 | record_buf[0] = reg_src1; | |
12649 | thumb_insn_r->reg_rec_count = 1; | |
12650 | } | |
12651 | else if (opcode1) | |
12652 | { | |
12653 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); | |
12654 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12655 | if ((3 == opcode2) && (!opcode3)) | |
12656 | { | |
12657 | /* Branch with exchange. */ | |
12658 | record_buf[0] = ARM_PS_REGNUM; | |
12659 | thumb_insn_r->reg_rec_count = 1; | |
12660 | } | |
12661 | else | |
12662 | { | |
12663 | /* Format 8; special data processing insns. */ | |
12664 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12665 | record_buf[0] = ARM_PS_REGNUM; | |
12666 | record_buf[1] = reg_src1; | |
12667 | thumb_insn_r->reg_rec_count = 2; | |
12668 | } | |
12669 | } | |
12670 | else | |
12671 | { | |
12672 | /* Format 5; data processing insns. */ | |
12673 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12674 | if (bit (thumb_insn_r->arm_insn, 7)) | |
12675 | { | |
12676 | reg_src1 = reg_src1 + 8; | |
12677 | } | |
12678 | record_buf[0] = ARM_PS_REGNUM; | |
12679 | record_buf[1] = reg_src1; | |
12680 | thumb_insn_r->reg_rec_count = 2; | |
12681 | } | |
12682 | ||
12683 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12684 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
12685 | record_buf_mem); | |
12686 | ||
12687 | return 0; | |
12688 | } | |
12689 | ||
12690 | /* Handling opcode 001 insns. */ | |
12691 | ||
12692 | static int | |
12693 | thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) | |
12694 | { | |
12695 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12696 | uint32_t record_buf[8], record_buf_mem[8]; | |
12697 | ||
12698 | uint32_t reg_src1 = 0; | |
12699 | uint32_t opcode = 0, immed_5 = 0; | |
12700 | ||
12701 | ULONGEST u_regval = 0; | |
12702 | ||
12703 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
12704 | ||
12705 | if (opcode) | |
12706 | { | |
12707 | /* LDR(1). */ | |
12708 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12709 | record_buf[0] = reg_src1; | |
12710 | thumb_insn_r->reg_rec_count = 1; | |
12711 | } | |
12712 | else | |
12713 | { | |
12714 | /* STR(1). */ | |
12715 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12716 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12717 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12718 | record_buf_mem[0] = 4; | |
12719 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
12720 | thumb_insn_r->mem_rec_count = 1; | |
12721 | } | |
12722 | ||
12723 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12724 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
12725 | record_buf_mem); | |
12726 | ||
12727 | return 0; | |
12728 | } | |
12729 | ||
12730 | /* Handling opcode 100 insns. */ | |
12731 | ||
12732 | static int | |
12733 | thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) | |
12734 | { | |
12735 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12736 | uint32_t record_buf[8], record_buf_mem[8]; | |
12737 | ||
12738 | uint32_t reg_src1 = 0; | |
12739 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
12740 | ||
12741 | ULONGEST u_regval = 0; | |
12742 | ||
12743 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
12744 | ||
12745 | if (3 == opcode) | |
12746 | { | |
12747 | /* LDR(4). */ | |
12748 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12749 | record_buf[0] = reg_src1; | |
12750 | thumb_insn_r->reg_rec_count = 1; | |
12751 | } | |
12752 | else if (1 == opcode) | |
12753 | { | |
12754 | /* LDRH(1). */ | |
12755 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12756 | record_buf[0] = reg_src1; | |
12757 | thumb_insn_r->reg_rec_count = 1; | |
12758 | } | |
12759 | else if (2 == opcode) | |
12760 | { | |
12761 | /* STR(3). */ | |
12762 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
12763 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12764 | record_buf_mem[0] = 4; | |
12765 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
12766 | thumb_insn_r->mem_rec_count = 1; | |
12767 | } | |
12768 | else if (0 == opcode) | |
12769 | { | |
12770 | /* STRH(1). */ | |
12771 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12772 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12773 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12774 | record_buf_mem[0] = 2; | |
12775 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
12776 | thumb_insn_r->mem_rec_count = 1; | |
12777 | } | |
12778 | ||
12779 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12780 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
12781 | record_buf_mem); | |
12782 | ||
12783 | return 0; | |
12784 | } | |
12785 | ||
12786 | /* Handling opcode 101 insns. */ | |
12787 | ||
12788 | static int | |
12789 | thumb_record_misc (insn_decode_record *thumb_insn_r) | |
12790 | { | |
12791 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12792 | ||
12793 | uint32_t opcode = 0, opcode1 = 0, opcode2 = 0; | |
12794 | uint32_t register_bits = 0, register_count = 0; | |
12795 | uint32_t register_list[8] = {0}, index = 0, start_address = 0; | |
12796 | uint32_t record_buf[24], record_buf_mem[48]; | |
12797 | uint32_t reg_src1; | |
12798 | ||
12799 | ULONGEST u_regval = 0; | |
12800 | ||
12801 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
12802 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
12803 | opcode2 = bits (thumb_insn_r->arm_insn, 9, 12); | |
12804 | ||
12805 | if (14 == opcode2) | |
12806 | { | |
12807 | /* POP. */ | |
12808 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12809 | while (register_bits) | |
f969241e OJ |
12810 | { |
12811 | if (register_bits & 0x00000001) | |
12812 | record_buf[index++] = register_count; | |
12813 | register_bits = register_bits >> 1; | |
12814 | register_count++; | |
12815 | } | |
12816 | record_buf[index++] = ARM_PS_REGNUM; | |
12817 | record_buf[index++] = ARM_SP_REGNUM; | |
12818 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
12819 | } |
12820 | else if (10 == opcode2) | |
12821 | { | |
12822 | /* PUSH. */ | |
12823 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
9904a494 | 12824 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); |
72508ac0 PO |
12825 | while (register_bits) |
12826 | { | |
12827 | if (register_bits & 0x00000001) | |
12828 | register_count++; | |
12829 | register_bits = register_bits >> 1; | |
12830 | } | |
12831 | start_address = u_regval - \ | |
12832 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
12833 | thumb_insn_r->mem_rec_count = register_count; | |
12834 | while (register_count) | |
12835 | { | |
12836 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12837 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12838 | start_address = start_address + 4; | |
12839 | register_count--; | |
12840 | } | |
12841 | record_buf[0] = ARM_SP_REGNUM; | |
12842 | thumb_insn_r->reg_rec_count = 1; | |
12843 | } | |
12844 | else if (0x1E == opcode1) | |
12845 | { | |
12846 | /* BKPT insn. */ | |
12847 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
12848 | /* CPSR is changed to be executed in ARM state, disabling normal | |
12849 | interrupts, entering abort mode. */ | |
12850 | /* According to high vector configuration PC is set. */ | |
12851 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
12852 | previous CPSR and Program Counter. */ | |
12853 | record_buf[0] = ARM_PS_REGNUM; | |
12854 | record_buf[1] = ARM_LR_REGNUM; | |
12855 | thumb_insn_r->reg_rec_count = 2; | |
12856 | /* We need to save SPSR value, which is not yet done. */ | |
12857 | printf_unfiltered (_("Process record does not support instruction " | |
12858 | "0x%0x at address %s.\n"), | |
12859 | thumb_insn_r->arm_insn, | |
12860 | paddress (thumb_insn_r->gdbarch, | |
12861 | thumb_insn_r->this_addr)); | |
12862 | return -1; | |
12863 | } | |
12864 | else if ((0 == opcode) || (1 == opcode)) | |
12865 | { | |
12866 | /* ADD(5), ADD(6). */ | |
12867 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12868 | record_buf[0] = reg_src1; | |
12869 | thumb_insn_r->reg_rec_count = 1; | |
12870 | } | |
12871 | else if (2 == opcode) | |
12872 | { | |
12873 | /* ADD(7), SUB(4). */ | |
12874 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12875 | record_buf[0] = ARM_SP_REGNUM; | |
12876 | thumb_insn_r->reg_rec_count = 1; | |
12877 | } | |
12878 | ||
12879 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12880 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
12881 | record_buf_mem); | |
12882 | ||
12883 | return 0; | |
12884 | } | |
12885 | ||
12886 | /* Handling opcode 110 insns. */ | |
12887 | ||
12888 | static int | |
12889 | thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) | |
12890 | { | |
12891 | struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch); | |
12892 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12893 | ||
12894 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
12895 | uint32_t reg_src1 = 0; | |
12896 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
12897 | uint32_t register_list[8] = {0}, index = 0, start_address = 0; | |
12898 | uint32_t record_buf[24], record_buf_mem[48]; | |
12899 | ||
12900 | ULONGEST u_regval = 0; | |
12901 | ||
12902 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
12903 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
12904 | ||
12905 | if (1 == opcode2) | |
12906 | { | |
12907 | ||
12908 | /* LDMIA. */ | |
12909 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12910 | /* Get Rn. */ | |
12911 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12912 | while (register_bits) | |
12913 | { | |
12914 | if (register_bits & 0x00000001) | |
f969241e | 12915 | record_buf[index++] = register_count; |
72508ac0 | 12916 | register_bits = register_bits >> 1; |
f969241e | 12917 | register_count++; |
72508ac0 | 12918 | } |
f969241e OJ |
12919 | record_buf[index++] = reg_src1; |
12920 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
12921 | } |
12922 | else if (0 == opcode2) | |
12923 | { | |
12924 | /* It handles both STMIA. */ | |
12925 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12926 | /* Get Rn. */ | |
12927 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12928 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12929 | while (register_bits) | |
12930 | { | |
12931 | if (register_bits & 0x00000001) | |
12932 | register_count++; | |
12933 | register_bits = register_bits >> 1; | |
12934 | } | |
12935 | start_address = u_regval; | |
12936 | thumb_insn_r->mem_rec_count = register_count; | |
12937 | while (register_count) | |
12938 | { | |
12939 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12940 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12941 | start_address = start_address + 4; | |
12942 | register_count--; | |
12943 | } | |
12944 | } | |
12945 | else if (0x1F == opcode1) | |
12946 | { | |
12947 | /* Handle arm syscall insn. */ | |
97dfe206 | 12948 | if (tdep->arm_syscall_record != NULL) |
72508ac0 | 12949 | { |
97dfe206 OJ |
12950 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); |
12951 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
72508ac0 PO |
12952 | } |
12953 | else | |
12954 | { | |
12955 | printf_unfiltered (_("no syscall record support\n")); | |
12956 | return -1; | |
12957 | } | |
12958 | } | |
12959 | ||
12960 | /* B (1), conditional branch is automatically taken care in process_record, | |
12961 | as PC is saved there. */ | |
12962 | ||
12963 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12964 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
12965 | record_buf_mem); | |
12966 | ||
12967 | return ret; | |
12968 | } | |
12969 | ||
12970 | /* Handling opcode 111 insns. */ | |
12971 | ||
12972 | static int | |
12973 | thumb_record_branch (insn_decode_record *thumb_insn_r) | |
12974 | { | |
12975 | uint32_t record_buf[8]; | |
12976 | uint32_t bits_h = 0; | |
12977 | ||
12978 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
12979 | ||
12980 | if (2 == bits_h || 3 == bits_h) | |
12981 | { | |
12982 | /* BL */ | |
12983 | record_buf[0] = ARM_LR_REGNUM; | |
12984 | thumb_insn_r->reg_rec_count = 1; | |
12985 | } | |
12986 | else if (1 == bits_h) | |
12987 | { | |
12988 | /* BLX(1). */ | |
12989 | record_buf[0] = ARM_PS_REGNUM; | |
12990 | record_buf[1] = ARM_LR_REGNUM; | |
12991 | thumb_insn_r->reg_rec_count = 2; | |
12992 | } | |
12993 | ||
12994 | /* B(2) is automatically taken care in process_record, as PC is | |
12995 | saved there. */ | |
12996 | ||
12997 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12998 | ||
12999 | return 0; | |
13000 | } | |
13001 | ||
c6ec2b30 OJ |
13002 | /* Handler for thumb2 load/store multiple instructions. */ |
13003 | ||
13004 | static int | |
13005 | thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) | |
13006 | { | |
13007 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13008 | ||
13009 | uint32_t reg_rn, op; | |
13010 | uint32_t register_bits = 0, register_count = 0; | |
13011 | uint32_t index = 0, start_address = 0; | |
13012 | uint32_t record_buf[24], record_buf_mem[48]; | |
13013 | ||
13014 | ULONGEST u_regval = 0; | |
13015 | ||
13016 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13017 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13018 | ||
13019 | if (0 == op || 3 == op) | |
13020 | { | |
13021 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13022 | { | |
13023 | /* Handle RFE instruction. */ | |
13024 | record_buf[0] = ARM_PS_REGNUM; | |
13025 | thumb2_insn_r->reg_rec_count = 1; | |
13026 | } | |
13027 | else | |
13028 | { | |
13029 | /* Handle SRS instruction after reading banked SP. */ | |
13030 | return arm_record_unsupported_insn (thumb2_insn_r); | |
13031 | } | |
13032 | } | |
13033 | else if (1 == op || 2 == op) | |
13034 | { | |
13035 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13036 | { | |
13037 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
13038 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13039 | while (register_bits) | |
13040 | { | |
13041 | if (register_bits & 0x00000001) | |
13042 | record_buf[index++] = register_count; | |
13043 | ||
13044 | register_count++; | |
13045 | register_bits = register_bits >> 1; | |
13046 | } | |
13047 | record_buf[index++] = reg_rn; | |
13048 | record_buf[index++] = ARM_PS_REGNUM; | |
13049 | thumb2_insn_r->reg_rec_count = index; | |
13050 | } | |
13051 | else | |
13052 | { | |
13053 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
13054 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13055 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13056 | while (register_bits) | |
13057 | { | |
13058 | if (register_bits & 0x00000001) | |
13059 | register_count++; | |
13060 | ||
13061 | register_bits = register_bits >> 1; | |
13062 | } | |
13063 | ||
13064 | if (1 == op) | |
13065 | { | |
13066 | /* Start address calculation for LDMDB/LDMEA. */ | |
13067 | start_address = u_regval; | |
13068 | } | |
13069 | else if (2 == op) | |
13070 | { | |
13071 | /* Start address calculation for LDMDB/LDMEA. */ | |
13072 | start_address = u_regval - register_count * 4; | |
13073 | } | |
13074 | ||
13075 | thumb2_insn_r->mem_rec_count = register_count; | |
13076 | while (register_count) | |
13077 | { | |
13078 | record_buf_mem[register_count * 2 - 1] = start_address; | |
13079 | record_buf_mem[register_count * 2 - 2] = 4; | |
13080 | start_address = start_address + 4; | |
13081 | register_count--; | |
13082 | } | |
13083 | record_buf[0] = reg_rn; | |
13084 | record_buf[1] = ARM_PS_REGNUM; | |
13085 | thumb2_insn_r->reg_rec_count = 2; | |
13086 | } | |
13087 | } | |
13088 | ||
13089 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
13090 | record_buf_mem); | |
13091 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13092 | record_buf); | |
13093 | return ARM_RECORD_SUCCESS; | |
13094 | } | |
13095 | ||
13096 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
13097 | instructions. */ | |
13098 | ||
13099 | static int | |
13100 | thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) | |
13101 | { | |
13102 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13103 | ||
13104 | uint32_t reg_rd, reg_rn, offset_imm; | |
13105 | uint32_t reg_dest1, reg_dest2; | |
13106 | uint32_t address, offset_addr; | |
13107 | uint32_t record_buf[8], record_buf_mem[8]; | |
13108 | uint32_t op1, op2, op3; | |
13109 | LONGEST s_word; | |
13110 | ||
13111 | ULONGEST u_regval[2]; | |
13112 | ||
13113 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13114 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
13115 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13116 | ||
13117 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13118 | { | |
13119 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
13120 | { | |
13121 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13122 | record_buf[0] = reg_dest1; | |
13123 | record_buf[1] = ARM_PS_REGNUM; | |
13124 | thumb2_insn_r->reg_rec_count = 2; | |
13125 | } | |
13126 | ||
13127 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
13128 | { | |
13129 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13130 | record_buf[2] = reg_dest2; | |
13131 | thumb2_insn_r->reg_rec_count = 3; | |
13132 | } | |
13133 | } | |
13134 | else | |
13135 | { | |
13136 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13137 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13138 | ||
13139 | if (0 == op1 && 0 == op2) | |
13140 | { | |
13141 | /* Handle STREX. */ | |
13142 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13143 | address = u_regval[0] + (offset_imm * 4); | |
13144 | record_buf_mem[0] = 4; | |
13145 | record_buf_mem[1] = address; | |
13146 | thumb2_insn_r->mem_rec_count = 1; | |
13147 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13148 | record_buf[0] = reg_rd; | |
13149 | thumb2_insn_r->reg_rec_count = 1; | |
13150 | } | |
13151 | else if (1 == op1 && 0 == op2) | |
13152 | { | |
13153 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13154 | record_buf[0] = reg_rd; | |
13155 | thumb2_insn_r->reg_rec_count = 1; | |
13156 | address = u_regval[0]; | |
13157 | record_buf_mem[1] = address; | |
13158 | ||
13159 | if (4 == op3) | |
13160 | { | |
13161 | /* Handle STREXB. */ | |
13162 | record_buf_mem[0] = 1; | |
13163 | thumb2_insn_r->mem_rec_count = 1; | |
13164 | } | |
13165 | else if (5 == op3) | |
13166 | { | |
13167 | /* Handle STREXH. */ | |
13168 | record_buf_mem[0] = 2 ; | |
13169 | thumb2_insn_r->mem_rec_count = 1; | |
13170 | } | |
13171 | else if (7 == op3) | |
13172 | { | |
13173 | /* Handle STREXD. */ | |
13174 | address = u_regval[0]; | |
13175 | record_buf_mem[0] = 4; | |
13176 | record_buf_mem[2] = 4; | |
13177 | record_buf_mem[3] = address + 4; | |
13178 | thumb2_insn_r->mem_rec_count = 2; | |
13179 | } | |
13180 | } | |
13181 | else | |
13182 | { | |
13183 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13184 | ||
13185 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
13186 | { | |
13187 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13188 | offset_addr = u_regval[0] + (offset_imm * 4); | |
13189 | else | |
13190 | offset_addr = u_regval[0] - (offset_imm * 4); | |
13191 | ||
13192 | address = offset_addr; | |
13193 | } | |
13194 | else | |
13195 | address = u_regval[0]; | |
13196 | ||
13197 | record_buf_mem[0] = 4; | |
13198 | record_buf_mem[1] = address; | |
13199 | record_buf_mem[2] = 4; | |
13200 | record_buf_mem[3] = address + 4; | |
13201 | thumb2_insn_r->mem_rec_count = 2; | |
13202 | record_buf[0] = reg_rn; | |
13203 | thumb2_insn_r->reg_rec_count = 1; | |
13204 | } | |
13205 | } | |
13206 | ||
13207 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13208 | record_buf); | |
13209 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
13210 | record_buf_mem); | |
13211 | return ARM_RECORD_SUCCESS; | |
13212 | } | |
13213 | ||
13214 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
13215 | instructions. */ | |
13216 | ||
13217 | static int | |
13218 | thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) | |
13219 | { | |
13220 | uint32_t reg_rd, op; | |
13221 | uint32_t record_buf[8]; | |
13222 | ||
13223 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
13224 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13225 | ||
13226 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
13227 | { | |
13228 | record_buf[0] = ARM_PS_REGNUM; | |
13229 | thumb2_insn_r->reg_rec_count = 1; | |
13230 | } | |
13231 | else | |
13232 | { | |
13233 | record_buf[0] = reg_rd; | |
13234 | record_buf[1] = ARM_PS_REGNUM; | |
13235 | thumb2_insn_r->reg_rec_count = 2; | |
13236 | } | |
13237 | ||
13238 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13239 | record_buf); | |
13240 | return ARM_RECORD_SUCCESS; | |
13241 | } | |
13242 | ||
13243 | /* Generic handler for thumb2 instructions which effect destination and PS | |
13244 | registers. */ | |
13245 | ||
13246 | static int | |
13247 | thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) | |
13248 | { | |
13249 | uint32_t reg_rd; | |
13250 | uint32_t record_buf[8]; | |
13251 | ||
13252 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13253 | ||
13254 | record_buf[0] = reg_rd; | |
13255 | record_buf[1] = ARM_PS_REGNUM; | |
13256 | thumb2_insn_r->reg_rec_count = 2; | |
13257 | ||
13258 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13259 | record_buf); | |
13260 | return ARM_RECORD_SUCCESS; | |
13261 | } | |
13262 | ||
13263 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
13264 | ||
13265 | static int | |
13266 | thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) | |
13267 | { | |
13268 | uint32_t op, op1, op2; | |
13269 | uint32_t record_buf[8]; | |
13270 | ||
13271 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13272 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
13273 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13274 | ||
13275 | /* Handle MSR insn. */ | |
13276 | if (!(op1 & 0x2) && 0x38 == op) | |
13277 | { | |
13278 | if (!(op2 & 0x3)) | |
13279 | { | |
13280 | /* CPSR is going to be changed. */ | |
13281 | record_buf[0] = ARM_PS_REGNUM; | |
13282 | thumb2_insn_r->reg_rec_count = 1; | |
13283 | } | |
13284 | else | |
13285 | { | |
13286 | arm_record_unsupported_insn(thumb2_insn_r); | |
13287 | return -1; | |
13288 | } | |
13289 | } | |
13290 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
13291 | { | |
13292 | /* BLX. */ | |
13293 | record_buf[0] = ARM_PS_REGNUM; | |
13294 | record_buf[1] = ARM_LR_REGNUM; | |
13295 | thumb2_insn_r->reg_rec_count = 2; | |
13296 | } | |
13297 | ||
13298 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13299 | record_buf); | |
13300 | return ARM_RECORD_SUCCESS; | |
13301 | } | |
13302 | ||
13303 | /* Handler for thumb2 store single data item instructions. */ | |
13304 | ||
13305 | static int | |
13306 | thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) | |
13307 | { | |
13308 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13309 | ||
13310 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
13311 | uint32_t address, offset_addr; | |
13312 | uint32_t record_buf[8], record_buf_mem[8]; | |
13313 | uint32_t op1, op2; | |
13314 | ||
13315 | ULONGEST u_regval[2]; | |
13316 | ||
13317 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
13318 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
13319 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13320 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13321 | ||
13322 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13323 | { | |
13324 | /* T2 encoding. */ | |
13325 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
13326 | offset_addr = u_regval[0] + offset_imm; | |
13327 | address = offset_addr; | |
13328 | } | |
13329 | else | |
13330 | { | |
13331 | /* T3 encoding. */ | |
13332 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
13333 | { | |
13334 | /* Handle STRB (register). */ | |
13335 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13336 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
13337 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
13338 | offset_addr = u_regval[1] << shift_imm; | |
13339 | address = u_regval[0] + offset_addr; | |
13340 | } | |
13341 | else | |
13342 | { | |
13343 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13344 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
13345 | { | |
13346 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
13347 | offset_addr = u_regval[0] + offset_imm; | |
13348 | else | |
13349 | offset_addr = u_regval[0] - offset_imm; | |
13350 | ||
13351 | address = offset_addr; | |
13352 | } | |
13353 | else | |
13354 | address = u_regval[0]; | |
13355 | } | |
13356 | } | |
13357 | ||
13358 | switch (op1) | |
13359 | { | |
13360 | /* Store byte instructions. */ | |
13361 | case 4: | |
13362 | case 0: | |
13363 | record_buf_mem[0] = 1; | |
13364 | break; | |
13365 | /* Store half word instructions. */ | |
13366 | case 1: | |
13367 | case 5: | |
13368 | record_buf_mem[0] = 2; | |
13369 | break; | |
13370 | /* Store word instructions. */ | |
13371 | case 2: | |
13372 | case 6: | |
13373 | record_buf_mem[0] = 4; | |
13374 | break; | |
13375 | ||
13376 | default: | |
13377 | gdb_assert_not_reached ("no decoding pattern found"); | |
13378 | break; | |
13379 | } | |
13380 | ||
13381 | record_buf_mem[1] = address; | |
13382 | thumb2_insn_r->mem_rec_count = 1; | |
13383 | record_buf[0] = reg_rn; | |
13384 | thumb2_insn_r->reg_rec_count = 1; | |
13385 | ||
13386 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13387 | record_buf); | |
13388 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
13389 | record_buf_mem); | |
13390 | return ARM_RECORD_SUCCESS; | |
13391 | } | |
13392 | ||
13393 | /* Handler for thumb2 load memory hints instructions. */ | |
13394 | ||
13395 | static int | |
13396 | thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) | |
13397 | { | |
13398 | uint32_t record_buf[8]; | |
13399 | uint32_t reg_rt, reg_rn; | |
13400 | ||
13401 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13402 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13403 | ||
13404 | if (ARM_PC_REGNUM != reg_rt) | |
13405 | { | |
13406 | record_buf[0] = reg_rt; | |
13407 | record_buf[1] = reg_rn; | |
13408 | record_buf[2] = ARM_PS_REGNUM; | |
13409 | thumb2_insn_r->reg_rec_count = 3; | |
13410 | ||
13411 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13412 | record_buf); | |
13413 | return ARM_RECORD_SUCCESS; | |
13414 | } | |
13415 | ||
13416 | return ARM_RECORD_FAILURE; | |
13417 | } | |
13418 | ||
13419 | /* Handler for thumb2 load word instructions. */ | |
13420 | ||
13421 | static int | |
13422 | thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) | |
13423 | { | |
13424 | uint32_t opcode1 = 0, opcode2 = 0; | |
13425 | uint32_t record_buf[8]; | |
13426 | ||
13427 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13428 | record_buf[1] = ARM_PS_REGNUM; | |
13429 | thumb2_insn_r->reg_rec_count = 2; | |
13430 | ||
13431 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13432 | record_buf); | |
13433 | return ARM_RECORD_SUCCESS; | |
13434 | } | |
13435 | ||
13436 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
13437 | divide instructions. */ | |
13438 | ||
13439 | static int | |
13440 | thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) | |
13441 | { | |
13442 | uint32_t opcode1 = 0, opcode2 = 0; | |
13443 | uint32_t record_buf[8]; | |
13444 | uint32_t reg_src1 = 0; | |
13445 | ||
13446 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
13447 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13448 | ||
13449 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
13450 | { | |
13451 | /* Handle SMULL, UMULL, SMULAL. */ | |
13452 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
13453 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13454 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13455 | record_buf[2] = ARM_PS_REGNUM; | |
13456 | thumb2_insn_r->reg_rec_count = 3; | |
13457 | } | |
13458 | else if (1 == opcode1 || 3 == opcode2) | |
13459 | { | |
13460 | /* Handle SDIV and UDIV. */ | |
13461 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13462 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13463 | record_buf[2] = ARM_PS_REGNUM; | |
13464 | thumb2_insn_r->reg_rec_count = 3; | |
13465 | } | |
13466 | else | |
13467 | return ARM_RECORD_FAILURE; | |
13468 | ||
13469 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13470 | record_buf); | |
13471 | return ARM_RECORD_SUCCESS; | |
13472 | } | |
13473 | ||
60cc5e93 OJ |
13474 | /* Record handler for thumb32 coprocessor instructions. */ |
13475 | ||
13476 | static int | |
13477 | thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) | |
13478 | { | |
13479 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
13480 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
13481 | else | |
13482 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
13483 | } | |
13484 | ||
1e1b6563 OJ |
13485 | /* Record handler for advance SIMD structure load/store instructions. */ |
13486 | ||
13487 | static int | |
13488 | thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) | |
13489 | { | |
13490 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13491 | uint32_t l_bit, a_bit, b_bits; | |
13492 | uint32_t record_buf[128], record_buf_mem[128]; | |
13493 | uint32_t reg_rn, reg_vd, address, f_esize, f_elem; | |
13494 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; | |
13495 | uint8_t f_ebytes; | |
13496 | ||
13497 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
13498 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
13499 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13500 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13501 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13502 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
13503 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
13504 | f_esize = 8 * f_ebytes; | |
13505 | f_elem = 8 / f_ebytes; | |
13506 | ||
13507 | if (!l_bit) | |
13508 | { | |
13509 | ULONGEST u_regval = 0; | |
13510 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13511 | address = u_regval; | |
13512 | ||
13513 | if (!a_bit) | |
13514 | { | |
13515 | /* Handle VST1. */ | |
13516 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
13517 | { | |
13518 | if (b_bits == 0x07) | |
13519 | bf_regs = 1; | |
13520 | else if (b_bits == 0x0a) | |
13521 | bf_regs = 2; | |
13522 | else if (b_bits == 0x06) | |
13523 | bf_regs = 3; | |
13524 | else if (b_bits == 0x02) | |
13525 | bf_regs = 4; | |
13526 | else | |
13527 | bf_regs = 0; | |
13528 | ||
13529 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13530 | { | |
13531 | for (index_e = 0; index_e < f_elem; index_e++) | |
13532 | { | |
13533 | record_buf_mem[index_m++] = f_ebytes; | |
13534 | record_buf_mem[index_m++] = address; | |
13535 | address = address + f_ebytes; | |
13536 | thumb2_insn_r->mem_rec_count += 1; | |
13537 | } | |
13538 | } | |
13539 | } | |
13540 | /* Handle VST2. */ | |
13541 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
13542 | { | |
13543 | if (b_bits == 0x09 || b_bits == 0x08) | |
13544 | bf_regs = 1; | |
13545 | else if (b_bits == 0x03) | |
13546 | bf_regs = 2; | |
13547 | else | |
13548 | bf_regs = 0; | |
13549 | ||
13550 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13551 | for (index_e = 0; index_e < f_elem; index_e++) | |
13552 | { | |
13553 | for (loop_t = 0; loop_t < 2; loop_t++) | |
13554 | { | |
13555 | record_buf_mem[index_m++] = f_ebytes; | |
13556 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13557 | thumb2_insn_r->mem_rec_count += 1; | |
13558 | } | |
13559 | address = address + (2 * f_ebytes); | |
13560 | } | |
13561 | } | |
13562 | /* Handle VST3. */ | |
13563 | else if ((b_bits & 0x0e) == 0x04) | |
13564 | { | |
13565 | for (index_e = 0; index_e < f_elem; index_e++) | |
13566 | { | |
13567 | for (loop_t = 0; loop_t < 3; loop_t++) | |
13568 | { | |
13569 | record_buf_mem[index_m++] = f_ebytes; | |
13570 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13571 | thumb2_insn_r->mem_rec_count += 1; | |
13572 | } | |
13573 | address = address + (3 * f_ebytes); | |
13574 | } | |
13575 | } | |
13576 | /* Handle VST4. */ | |
13577 | else if (!(b_bits & 0x0e)) | |
13578 | { | |
13579 | for (index_e = 0; index_e < f_elem; index_e++) | |
13580 | { | |
13581 | for (loop_t = 0; loop_t < 4; loop_t++) | |
13582 | { | |
13583 | record_buf_mem[index_m++] = f_ebytes; | |
13584 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13585 | thumb2_insn_r->mem_rec_count += 1; | |
13586 | } | |
13587 | address = address + (4 * f_ebytes); | |
13588 | } | |
13589 | } | |
13590 | } | |
13591 | else | |
13592 | { | |
13593 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
13594 | ||
13595 | if (bft_size == 0x00) | |
13596 | f_ebytes = 1; | |
13597 | else if (bft_size == 0x01) | |
13598 | f_ebytes = 2; | |
13599 | else if (bft_size == 0x02) | |
13600 | f_ebytes = 4; | |
13601 | else | |
13602 | f_ebytes = 0; | |
13603 | ||
13604 | /* Handle VST1. */ | |
13605 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
13606 | thumb2_insn_r->mem_rec_count = 1; | |
13607 | /* Handle VST2. */ | |
13608 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
13609 | thumb2_insn_r->mem_rec_count = 2; | |
13610 | /* Handle VST3. */ | |
13611 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
13612 | thumb2_insn_r->mem_rec_count = 3; | |
13613 | /* Handle VST4. */ | |
13614 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
13615 | thumb2_insn_r->mem_rec_count = 4; | |
13616 | ||
13617 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
13618 | { | |
13619 | record_buf_mem[index_m] = f_ebytes; | |
13620 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
13621 | } | |
13622 | } | |
13623 | } | |
13624 | else | |
13625 | { | |
13626 | if (!a_bit) | |
13627 | { | |
13628 | /* Handle VLD1. */ | |
13629 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
13630 | thumb2_insn_r->reg_rec_count = 1; | |
13631 | /* Handle VLD2. */ | |
13632 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
13633 | thumb2_insn_r->reg_rec_count = 2; | |
13634 | /* Handle VLD3. */ | |
13635 | else if ((b_bits & 0x0e) == 0x04) | |
13636 | thumb2_insn_r->reg_rec_count = 3; | |
13637 | /* Handle VLD4. */ | |
13638 | else if (!(b_bits & 0x0e)) | |
13639 | thumb2_insn_r->reg_rec_count = 4; | |
13640 | } | |
13641 | else | |
13642 | { | |
13643 | /* Handle VLD1. */ | |
13644 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
13645 | thumb2_insn_r->reg_rec_count = 1; | |
13646 | /* Handle VLD2. */ | |
13647 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
13648 | thumb2_insn_r->reg_rec_count = 2; | |
13649 | /* Handle VLD3. */ | |
13650 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
13651 | thumb2_insn_r->reg_rec_count = 3; | |
13652 | /* Handle VLD4. */ | |
13653 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
13654 | thumb2_insn_r->reg_rec_count = 4; | |
13655 | ||
13656 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
13657 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
13658 | } | |
13659 | } | |
13660 | ||
13661 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
13662 | { | |
13663 | record_buf[index_r] = reg_rn; | |
13664 | thumb2_insn_r->reg_rec_count += 1; | |
13665 | } | |
13666 | ||
13667 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
13668 | record_buf); | |
13669 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
13670 | record_buf_mem); | |
13671 | return 0; | |
13672 | } | |
13673 | ||
c6ec2b30 OJ |
13674 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
13675 | ||
13676 | static unsigned int | |
13677 | thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) | |
13678 | { | |
13679 | uint32_t op, op1, op2; | |
13680 | ||
13681 | op = bit (thumb2_insn_r->arm_insn, 15); | |
13682 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
13683 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13684 | ||
13685 | if (op1 == 0x01) | |
13686 | { | |
13687 | if (!(op2 & 0x64 )) | |
13688 | { | |
13689 | /* Load/store multiple instruction. */ | |
13690 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
13691 | } | |
13692 | else if (!((op2 & 0x64) ^ 0x04)) | |
13693 | { | |
13694 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
13695 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
13696 | } | |
13697 | else if (!((op2 & 0x20) ^ 0x20)) | |
13698 | { | |
13699 | /* Data-processing (shifted register). */ | |
13700 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
13701 | } | |
13702 | else if (op2 & 0x40) | |
13703 | { | |
13704 | /* Co-processor instructions. */ | |
60cc5e93 | 13705 | return thumb2_record_coproc_insn (thumb2_insn_r); |
c6ec2b30 OJ |
13706 | } |
13707 | } | |
13708 | else if (op1 == 0x02) | |
13709 | { | |
13710 | if (op) | |
13711 | { | |
13712 | /* Branches and miscellaneous control instructions. */ | |
13713 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
13714 | } | |
13715 | else if (op2 & 0x20) | |
13716 | { | |
13717 | /* Data-processing (plain binary immediate) instruction. */ | |
13718 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13719 | } | |
13720 | else | |
13721 | { | |
13722 | /* Data-processing (modified immediate). */ | |
13723 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
13724 | } | |
13725 | } | |
13726 | else if (op1 == 0x03) | |
13727 | { | |
13728 | if (!(op2 & 0x71 )) | |
13729 | { | |
13730 | /* Store single data item. */ | |
13731 | return thumb2_record_str_single_data (thumb2_insn_r); | |
13732 | } | |
13733 | else if (!((op2 & 0x71) ^ 0x10)) | |
13734 | { | |
13735 | /* Advanced SIMD or structure load/store instructions. */ | |
1e1b6563 | 13736 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); |
c6ec2b30 OJ |
13737 | } |
13738 | else if (!((op2 & 0x67) ^ 0x01)) | |
13739 | { | |
13740 | /* Load byte, memory hints instruction. */ | |
13741 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13742 | } | |
13743 | else if (!((op2 & 0x67) ^ 0x03)) | |
13744 | { | |
13745 | /* Load halfword, memory hints instruction. */ | |
13746 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13747 | } | |
13748 | else if (!((op2 & 0x67) ^ 0x05)) | |
13749 | { | |
13750 | /* Load word instruction. */ | |
13751 | return thumb2_record_ld_word (thumb2_insn_r); | |
13752 | } | |
13753 | else if (!((op2 & 0x70) ^ 0x20)) | |
13754 | { | |
13755 | /* Data-processing (register) instruction. */ | |
13756 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13757 | } | |
13758 | else if (!((op2 & 0x78) ^ 0x30)) | |
13759 | { | |
13760 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
13761 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13762 | } | |
13763 | else if (!((op2 & 0x78) ^ 0x38)) | |
13764 | { | |
13765 | /* Long multiply, long multiply accumulate, and divide. */ | |
13766 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
13767 | } | |
13768 | else if (op2 & 0x40) | |
13769 | { | |
13770 | /* Co-processor instructions. */ | |
60cc5e93 | 13771 | return thumb2_record_coproc_insn (thumb2_insn_r); |
c6ec2b30 OJ |
13772 | } |
13773 | } | |
13774 | ||
13775 | return -1; | |
13776 | } | |
72508ac0 PO |
13777 | |
13778 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success | |
13779 | and positive val on fauilure. */ | |
13780 | ||
13781 | static int | |
13782 | extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size) | |
13783 | { | |
13784 | gdb_byte buf[insn_size]; | |
13785 | ||
13786 | memset (&buf[0], 0, insn_size); | |
13787 | ||
13788 | if (target_read_memory (insn_record->this_addr, &buf[0], insn_size)) | |
13789 | return 1; | |
13790 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
13791 | insn_size, | |
2959fed9 | 13792 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
13793 | return 0; |
13794 | } | |
13795 | ||
13796 | typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); | |
13797 | ||
13798 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
13799 | dispatch it. */ | |
13800 | ||
13801 | static int | |
13802 | decode_insn (insn_decode_record *arm_record, record_type_t record_type, | |
13803 | uint32_t insn_size) | |
13804 | { | |
13805 | ||
13806 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */ | |
0fa9c223 | 13807 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
13808 | { |
13809 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
13810 | arm_record_data_proc_imm, /* 001. */ | |
13811 | arm_record_ld_st_imm_offset, /* 010. */ | |
13812 | arm_record_ld_st_reg_offset, /* 011. */ | |
13813 | arm_record_ld_st_multiple, /* 100. */ | |
13814 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 13815 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
13816 | arm_record_coproc_data_proc /* 111. */ |
13817 | }; | |
13818 | ||
13819 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */ | |
0fa9c223 | 13820 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
13821 | { \ |
13822 | thumb_record_shift_add_sub, /* 000. */ | |
13823 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
13824 | thumb_record_ld_st_reg_offset, /* 010. */ | |
13825 | thumb_record_ld_st_imm_offset, /* 011. */ | |
13826 | thumb_record_ld_st_stack, /* 100. */ | |
13827 | thumb_record_misc, /* 101. */ | |
13828 | thumb_record_ldm_stm_swi, /* 110. */ | |
13829 | thumb_record_branch /* 111. */ | |
13830 | }; | |
13831 | ||
13832 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
13833 | uint32_t insn_id = 0; | |
13834 | ||
13835 | if (extract_arm_insn (arm_record, insn_size)) | |
13836 | { | |
13837 | if (record_debug) | |
13838 | { | |
13839 | printf_unfiltered (_("Process record: error reading memory at " | |
13840 | "addr %s len = %d.\n"), | |
13841 | paddress (arm_record->gdbarch, arm_record->this_addr), insn_size); | |
13842 | } | |
13843 | return -1; | |
13844 | } | |
13845 | else if (ARM_RECORD == record_type) | |
13846 | { | |
13847 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
13848 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
13849 | ret = arm_record_extension_space (arm_record); | |
13850 | /* If this insn has fallen into extension space | |
13851 | then we need not decode it anymore. */ | |
13852 | if (ret != -1 && !INSN_RECORDED(arm_record)) | |
13853 | { | |
13854 | ret = arm_handle_insn[insn_id] (arm_record); | |
13855 | } | |
13856 | } | |
13857 | else if (THUMB_RECORD == record_type) | |
13858 | { | |
13859 | /* As thumb does not have condition codes, we set negative. */ | |
13860 | arm_record->cond = -1; | |
13861 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
13862 | ret = thumb_handle_insn[insn_id] (arm_record); | |
13863 | } | |
13864 | else if (THUMB2_RECORD == record_type) | |
13865 | { | |
c6ec2b30 OJ |
13866 | /* As thumb does not have condition codes, we set negative. */ |
13867 | arm_record->cond = -1; | |
13868 | ||
13869 | /* Swap first half of 32bit thumb instruction with second half. */ | |
13870 | arm_record->arm_insn | |
13871 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); | |
13872 | ||
13873 | insn_id = thumb2_record_decode_insn_handler (arm_record); | |
13874 | ||
13875 | if (insn_id != ARM_RECORD_SUCCESS) | |
13876 | { | |
13877 | arm_record_unsupported_insn (arm_record); | |
13878 | ret = -1; | |
13879 | } | |
72508ac0 PO |
13880 | } |
13881 | else | |
13882 | { | |
13883 | /* Throw assertion. */ | |
13884 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
13885 | } | |
13886 | ||
13887 | return ret; | |
13888 | } | |
13889 | ||
13890 | ||
13891 | /* Cleans up local record registers and memory allocations. */ | |
13892 | ||
13893 | static void | |
13894 | deallocate_reg_mem (insn_decode_record *record) | |
13895 | { | |
13896 | xfree (record->arm_regs); | |
13897 | xfree (record->arm_mems); | |
13898 | } | |
13899 | ||
13900 | ||
13901 | /* Parse the current instruction and record the values of the registers and | |
13902 | memory that will be changed in current instruction to record_arch_list". | |
13903 | Return -1 if something is wrong. */ | |
13904 | ||
13905 | int | |
13906 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
13907 | CORE_ADDR insn_addr) | |
13908 | { | |
13909 | ||
13910 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
13911 | uint32_t no_of_rec = 0; | |
13912 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
13913 | ULONGEST t_bit = 0, insn_id = 0; | |
13914 | ||
13915 | ULONGEST u_regval = 0; | |
13916 | ||
13917 | insn_decode_record arm_record; | |
13918 | ||
13919 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13920 | arm_record.regcache = regcache; | |
13921 | arm_record.this_addr = insn_addr; | |
13922 | arm_record.gdbarch = gdbarch; | |
13923 | ||
13924 | ||
13925 | if (record_debug > 1) | |
13926 | { | |
13927 | fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " | |
13928 | "addr = %s\n", | |
13929 | paddress (gdbarch, arm_record.this_addr)); | |
13930 | } | |
13931 | ||
13932 | if (extract_arm_insn (&arm_record, 2)) | |
13933 | { | |
13934 | if (record_debug) | |
13935 | { | |
13936 | printf_unfiltered (_("Process record: error reading memory at " | |
13937 | "addr %s len = %d.\n"), | |
13938 | paddress (arm_record.gdbarch, | |
13939 | arm_record.this_addr), 2); | |
13940 | } | |
13941 | return -1; | |
13942 | } | |
13943 | ||
13944 | /* Check the insn, whether it is thumb or arm one. */ | |
13945 | ||
13946 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
13947 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
13948 | ||
13949 | ||
13950 | if (!(u_regval & t_bit)) | |
13951 | { | |
13952 | /* We are decoding arm insn. */ | |
13953 | ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); | |
13954 | } | |
13955 | else | |
13956 | { | |
13957 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
13958 | /* is it thumb2 insn? */ | |
13959 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
13960 | { | |
13961 | ret = decode_insn (&arm_record, THUMB2_RECORD, | |
13962 | THUMB2_INSN_SIZE_BYTES); | |
13963 | } | |
13964 | else | |
13965 | { | |
13966 | /* We are decoding thumb insn. */ | |
13967 | ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES); | |
13968 | } | |
13969 | } | |
13970 | ||
13971 | if (0 == ret) | |
13972 | { | |
13973 | /* Record registers. */ | |
25ea693b | 13974 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 PO |
13975 | if (arm_record.arm_regs) |
13976 | { | |
13977 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
13978 | { | |
25ea693b MM |
13979 | if (record_full_arch_list_add_reg |
13980 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) | |
72508ac0 PO |
13981 | ret = -1; |
13982 | } | |
13983 | } | |
13984 | /* Record memories. */ | |
13985 | if (arm_record.arm_mems) | |
13986 | { | |
13987 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
13988 | { | |
25ea693b | 13989 | if (record_full_arch_list_add_mem |
72508ac0 | 13990 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, |
25ea693b | 13991 | arm_record.arm_mems[no_of_rec].len)) |
72508ac0 PO |
13992 | ret = -1; |
13993 | } | |
13994 | } | |
13995 | ||
25ea693b | 13996 | if (record_full_arch_list_add_end ()) |
72508ac0 PO |
13997 | ret = -1; |
13998 | } | |
13999 | ||
14000 | ||
14001 | deallocate_reg_mem (&arm_record); | |
14002 | ||
14003 | return ret; | |
14004 | } | |
14005 |