Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
1e698235 | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
4be87837 | 36 | #include "osabi.h" |
eb5492fa DJ |
37 | #include "frame-unwind.h" |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
34e8f22d RE |
40 | |
41 | #include "arm-tdep.h" | |
26216b98 | 42 | #include "gdb/sim-arm.h" |
34e8f22d | 43 | |
082fc60d RE |
44 | #include "elf-bfd.h" |
45 | #include "coff/internal.h" | |
97e03143 | 46 | #include "elf/arm.h" |
c906108c | 47 | |
26216b98 AC |
48 | #include "gdb_assert.h" |
49 | ||
6529d2dd AC |
50 | static int arm_debug; |
51 | ||
2a451106 KB |
52 | /* Each OS has a different mechanism for accessing the various |
53 | registers stored in the sigcontext structure. | |
54 | ||
55 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
56 | function pointer) which may be used to determine the addresses | |
57 | of the various saved registers in the sigcontext structure. | |
58 | ||
59 | For the ARM target, there are three parameters to this function. | |
60 | The first is the pc value of the frame under consideration, the | |
61 | second the stack pointer of this frame, and the last is the | |
62 | register number to fetch. | |
63 | ||
64 | If the tm.h file does not define this macro, then it's assumed that | |
65 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
66 | be 0. | |
67 | ||
68 | When it comes time to multi-arching this code, see the identically | |
69 | named machinery in ia64-tdep.c for an example of how it could be | |
70 | done. It should not be necessary to modify the code below where | |
71 | this macro is used. */ | |
72 | ||
3bb04bdd AC |
73 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
74 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
75 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
76 | #endif | |
77 | #else | |
78 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
79 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
80 | #endif |
81 | ||
082fc60d RE |
82 | /* Macros for setting and testing a bit in a minimal symbol that marks |
83 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
84 | is used for this purpose. This field is already being used to store | |
85 | the symbol size, so the assumption is that the symbol size cannot | |
86 | exceed 2^31. | |
87 | ||
88 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
89 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
90 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
91 | i.e. the "info" field with the "special" bit | |
92 | masked out. */ | |
93 | ||
94 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
95 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
96 | | 0x80000000) | |
97 | ||
98 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
99 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
100 | ||
101 | #define MSYMBOL_SIZE(msym) \ | |
102 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 103 | |
afd7eef0 RE |
104 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
105 | static struct cmd_list_element *setarmcmdlist = NULL; | |
106 | static struct cmd_list_element *showarmcmdlist = NULL; | |
107 | ||
fd50bc42 RE |
108 | /* The type of floating-point to use. Keep this in sync with enum |
109 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
110 | static const char *fp_model_strings[] = | |
111 | { | |
112 | "auto", | |
113 | "softfpa", | |
114 | "fpa", | |
115 | "softvfp", | |
116 | "vfp" | |
117 | }; | |
118 | ||
119 | /* A variable that can be configured by the user. */ | |
120 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
121 | static const char *current_fp_model = "auto"; | |
122 | ||
94c30b78 | 123 | /* Number of different reg name sets (options). */ |
afd7eef0 | 124 | static int num_disassembly_options; |
bc90b915 FN |
125 | |
126 | /* We have more registers than the disassembler as gdb can print the value | |
127 | of special registers as well. | |
128 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 129 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 130 | |
94c30b78 | 131 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 132 | static char * arm_register_name_strings[] = |
da59e081 JM |
133 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
134 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
135 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
136 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
137 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
138 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 139 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 140 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 141 | |
afd7eef0 RE |
142 | /* Valid register name styles. */ |
143 | static const char **valid_disassembly_styles; | |
ed9a39eb | 144 | |
afd7eef0 RE |
145 | /* Disassembly style to use. Default to "std" register names. */ |
146 | static const char *disassembly_style; | |
94c30b78 | 147 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 148 | static int current_option; |
96baa820 | 149 | |
ed9a39eb | 150 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
151 | style. */ |
152 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 153 | struct cmd_list_element *); |
afd7eef0 | 154 | static void set_disassembly_style (void); |
ed9a39eb | 155 | |
b508a996 RE |
156 | static void convert_from_extended (const struct floatformat *, const void *, |
157 | void *); | |
158 | static void convert_to_extended (const struct floatformat *, void *, | |
159 | const void *); | |
ed9a39eb | 160 | |
9b8d791a | 161 | struct arm_prologue_cache |
c3b4394c | 162 | { |
eb5492fa DJ |
163 | /* The stack pointer at the time this frame was created; i.e. the |
164 | caller's stack pointer when this function was called. It is used | |
165 | to identify this frame. */ | |
166 | CORE_ADDR prev_sp; | |
167 | ||
168 | /* The frame base for this frame is just prev_sp + frame offset - | |
169 | frame size. FRAMESIZE is the size of this stack frame, and | |
170 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
171 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
172 | ||
c3b4394c RE |
173 | int framesize; |
174 | int frameoffset; | |
eb5492fa DJ |
175 | |
176 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 177 | int framereg; |
eb5492fa DJ |
178 | |
179 | /* Saved register offsets. */ | |
180 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 181 | }; |
ed9a39eb | 182 | |
bc90b915 FN |
183 | /* Addresses for calling Thumb functions have the bit 0 set. |
184 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
185 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
186 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
187 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
188 | ||
94c30b78 | 189 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
190 | |
191 | int arm_apcs_32 = 1; | |
192 | ||
ed9a39eb JM |
193 | /* Flag set by arm_fix_call_dummy that tells whether the target |
194 | function is a Thumb function. This flag is checked by | |
195 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
196 | its use in valops.c) to pass the function address as an additional | |
197 | parameter. */ | |
c906108c SS |
198 | |
199 | static int target_is_thumb; | |
200 | ||
ed9a39eb JM |
201 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
202 | function is a Thumb function. This flag is checked by | |
203 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
204 | |
205 | static int caller_is_thumb; | |
206 | ||
ed9a39eb JM |
207 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
208 | function. */ | |
c906108c | 209 | |
34e8f22d | 210 | int |
2a451106 | 211 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 212 | { |
c5aa993b | 213 | struct minimal_symbol *sym; |
c906108c | 214 | |
ed9a39eb | 215 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
216 | if (IS_THUMB_ADDR (memaddr)) |
217 | return 1; | |
218 | ||
ed9a39eb | 219 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
220 | sym = lookup_minimal_symbol_by_pc (memaddr); |
221 | if (sym) | |
222 | { | |
c5aa993b | 223 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
224 | } |
225 | else | |
ed9a39eb JM |
226 | { |
227 | return 0; | |
228 | } | |
c906108c SS |
229 | } |
230 | ||
ed9a39eb JM |
231 | /* Determine if the program counter specified in MEMADDR is in a call |
232 | dummy being called from a Thumb function. */ | |
c906108c | 233 | |
34e8f22d | 234 | int |
2a451106 | 235 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 236 | { |
c5aa993b | 237 | CORE_ADDR sp = read_sp (); |
c906108c | 238 | |
dfcd3bfb JM |
239 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
240 | is the best we can do. We are trying to determine if the pc is on | |
241 | the stack, which (hopefully) will only happen in a call dummy. | |
242 | We hope the current stack pointer is not so far alway from the dummy | |
243 | frame location (true if we have not pushed large data structures or | |
244 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 245 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 246 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
247 | return caller_is_thumb; |
248 | else | |
249 | return 0; | |
250 | } | |
251 | ||
181c1381 | 252 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 253 | static CORE_ADDR |
ed9a39eb | 254 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 255 | { |
a3a2ee65 JT |
256 | if (arm_apcs_32) |
257 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 258 | else |
a3a2ee65 | 259 | return (val & 0x03fffffc); |
c906108c SS |
260 | } |
261 | ||
181c1381 RE |
262 | /* When reading symbols, we need to zap the low bit of the address, |
263 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 264 | static CORE_ADDR |
181c1381 RE |
265 | arm_smash_text_address (CORE_ADDR val) |
266 | { | |
267 | return val & ~1; | |
268 | } | |
269 | ||
34e8f22d RE |
270 | /* Immediately after a function call, return the saved pc. Can't |
271 | always go through the frames for this because on some machines the | |
272 | new frame is not set up until the new function executes some | |
273 | instructions. */ | |
274 | ||
275 | static CORE_ADDR | |
ed9a39eb | 276 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 277 | { |
34e8f22d | 278 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
279 | } |
280 | ||
0defa245 RE |
281 | /* Determine whether the function invocation represented by FI has a |
282 | frame on the stack associated with it. If it does return zero, | |
283 | otherwise return 1. */ | |
284 | ||
148754e5 | 285 | static int |
ed9a39eb | 286 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 287 | { |
392a587b | 288 | CORE_ADDR func_start, after_prologue; |
96baa820 | 289 | int frameless; |
ed9a39eb | 290 | |
0defa245 RE |
291 | /* Sometimes we have functions that do a little setup (like saving the |
292 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
293 | The symbol table will report this as a prologue. However, it is | |
294 | important not to try to parse these partial frames as frames, or we | |
295 | will get really confused. | |
296 | ||
297 | So I will demand 3 instructions between the start & end of the | |
298 | prologue before I call it a real prologue, i.e. at least | |
299 | mov ip, sp, | |
300 | stmdb sp!, {} | |
301 | sub sp, ip, #4. */ | |
302 | ||
8cf71652 | 303 | func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET); |
7be570e7 | 304 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 305 | |
96baa820 | 306 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 307 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 308 | be func_start + 8. */ |
ed9a39eb | 309 | |
96baa820 | 310 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
311 | return frameless; |
312 | } | |
313 | ||
c906108c | 314 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
315 | push {r7, lr} |
316 | add sp, sp, #-28 | |
317 | add r7, sp, #12 | |
c906108c | 318 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
319 | mov r7, sp |
320 | ||
321 | or like this: | |
322 | push {r7, lr} | |
323 | mov r7, sp | |
324 | sub sp, #12 | |
325 | ||
326 | or, on tpcs, like this: | |
327 | sub sp,#16 | |
328 | push {r7, lr} | |
329 | (many instructions) | |
330 | mov r7, sp | |
331 | sub sp, #12 | |
332 | ||
333 | There is always one instruction of three classes: | |
334 | 1 - push | |
335 | 2 - setting of r7 | |
336 | 3 - adjusting of sp | |
337 | ||
338 | When we have found at least one of each class we are done with the prolog. | |
339 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 340 | */ |
c906108c SS |
341 | |
342 | static CORE_ADDR | |
c7885828 | 343 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
344 | { |
345 | CORE_ADDR current_pc; | |
da3c6d4a MS |
346 | /* findmask: |
347 | bit 0 - push { rlist } | |
348 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
349 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
350 | */ | |
351 | int findmask = 0; | |
352 | ||
94c30b78 MS |
353 | for (current_pc = pc; |
354 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 355 | current_pc += 2) |
c906108c SS |
356 | { |
357 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
358 | ||
94c30b78 | 359 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 360 | { |
94c30b78 | 361 | findmask |= 1; /* push found */ |
da59e081 | 362 | } |
da3c6d4a MS |
363 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
364 | sub sp, #simm */ | |
da59e081 | 365 | { |
94c30b78 | 366 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
367 | continue; |
368 | else | |
94c30b78 | 369 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
370 | } |
371 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
372 | { | |
94c30b78 | 373 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
374 | } |
375 | else if (insn == 0x466f) /* mov r7, sp */ | |
376 | { | |
94c30b78 | 377 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 378 | } |
3d74b771 FF |
379 | else if (findmask == (4+2+1)) |
380 | { | |
da3c6d4a MS |
381 | /* We have found one of each type of prologue instruction */ |
382 | break; | |
3d74b771 | 383 | } |
da59e081 | 384 | else |
94c30b78 | 385 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 386 | instruction from outside the prolog scheduled here for |
94c30b78 | 387 | optimization. */ |
da3c6d4a | 388 | continue; |
c906108c SS |
389 | } |
390 | ||
391 | return current_pc; | |
392 | } | |
393 | ||
da3c6d4a MS |
394 | /* Advance the PC across any function entry prologue instructions to |
395 | reach some "real" code. | |
34e8f22d RE |
396 | |
397 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 398 | prologue: |
c906108c | 399 | |
c5aa993b JM |
400 | mov ip, sp |
401 | [stmfd sp!, {a1,a2,a3,a4}] | |
402 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
403 | [stfe f7, [sp, #-12]!] |
404 | [stfe f6, [sp, #-12]!] | |
405 | [stfe f5, [sp, #-12]!] | |
406 | [stfe f4, [sp, #-12]!] | |
407 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 408 | |
34e8f22d | 409 | static CORE_ADDR |
ed9a39eb | 410 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
411 | { |
412 | unsigned long inst; | |
413 | CORE_ADDR skip_pc; | |
b8d5e71d | 414 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 415 | char *func_name; |
c906108c SS |
416 | struct symtab_and_line sal; |
417 | ||
848cfffb | 418 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 419 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
420 | return pc; |
421 | ||
96baa820 | 422 | /* See what the symbol table says. */ |
ed9a39eb | 423 | |
50f6fb4b | 424 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 425 | { |
50f6fb4b CV |
426 | struct symbol *sym; |
427 | ||
428 | /* Found a function. */ | |
176620f1 | 429 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
430 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
431 | { | |
94c30b78 | 432 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
433 | sal = find_pc_line (func_addr, 0); |
434 | if ((sal.line != 0) && (sal.end < func_end)) | |
435 | return sal.end; | |
436 | } | |
c906108c SS |
437 | } |
438 | ||
439 | /* Check if this is Thumb code. */ | |
440 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 441 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
442 | |
443 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 444 | by disassembling the instructions. */ |
c906108c | 445 | |
b8d5e71d MS |
446 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
447 | if (func_end == 0 || func_end > pc + 64) | |
448 | func_end = pc + 64; | |
c906108c | 449 | |
b8d5e71d | 450 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 451 | { |
f43845b3 | 452 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 453 | |
b8d5e71d MS |
454 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
455 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
456 | continue; | |
c906108c | 457 | |
b8d5e71d MS |
458 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
459 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
460 | continue; | |
c906108c | 461 | |
b8d5e71d MS |
462 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
463 | continue; | |
c906108c | 464 | |
b8d5e71d MS |
465 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
466 | continue; | |
11d3b27d | 467 | |
b8d5e71d MS |
468 | /* Any insns after this point may float into the code, if it makes |
469 | for better instruction scheduling, so we skip them only if we | |
470 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 471 | |
b8d5e71d MS |
472 | /* We may have either one sfmfd instruction here, or several stfe |
473 | insns, depending on the version of floating point code we | |
474 | support. */ | |
475 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
476 | continue; | |
477 | ||
478 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
479 | continue; | |
480 | ||
481 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
482 | continue; | |
483 | ||
484 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
485 | continue; | |
486 | ||
487 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
488 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
489 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
490 | continue; | |
491 | ||
492 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
493 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
494 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
495 | continue; | |
496 | ||
497 | /* Un-recognized instruction; stop scanning. */ | |
498 | break; | |
f43845b3 | 499 | } |
c906108c | 500 | |
b8d5e71d | 501 | return skip_pc; /* End of prologue */ |
c906108c | 502 | } |
94c30b78 | 503 | |
c5aa993b | 504 | /* *INDENT-OFF* */ |
c906108c SS |
505 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
506 | This function decodes a Thumb function prologue to determine: | |
507 | 1) the size of the stack frame | |
508 | 2) which registers are saved on it | |
509 | 3) the offsets of saved regs | |
510 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 511 | |
da59e081 JM |
512 | A typical Thumb function prologue would create this stack frame |
513 | (offsets relative to FP) | |
c906108c SS |
514 | old SP -> 24 stack parameters |
515 | 20 LR | |
516 | 16 R7 | |
517 | R7 -> 0 local variables (16 bytes) | |
518 | SP -> -12 additional stack space (12 bytes) | |
519 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
520 | 12 bytes. The frame register is R7. |
521 | ||
da3c6d4a MS |
522 | The comments for thumb_skip_prolog() describe the algorithm we use |
523 | to detect the end of the prolog. */ | |
c5aa993b JM |
524 | /* *INDENT-ON* */ |
525 | ||
c906108c | 526 | static void |
eb5492fa | 527 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
528 | { |
529 | CORE_ADDR prologue_start; | |
530 | CORE_ADDR prologue_end; | |
531 | CORE_ADDR current_pc; | |
94c30b78 | 532 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
533 | int saved_reg[16]; |
534 | /* findmask: | |
535 | bit 0 - push { rlist } | |
536 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
537 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
538 | */ | |
539 | int findmask = 0; | |
c5aa993b | 540 | int i; |
c906108c | 541 | |
eb5492fa | 542 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
543 | { |
544 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
545 | ||
94c30b78 | 546 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 547 | prologue_end = prev_pc; |
c906108c | 548 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 549 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
550 | } |
551 | else | |
da3c6d4a MS |
552 | /* We're in the boondocks: allow for |
553 | 16 pushes, an add, and "mv fp,sp". */ | |
554 | prologue_end = prologue_start + 40; | |
c906108c | 555 | |
eb5492fa | 556 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
557 | |
558 | /* Initialize the saved register map. When register H is copied to | |
559 | register L, we will put H in saved_reg[L]. */ | |
560 | for (i = 0; i < 16; i++) | |
561 | saved_reg[i] = i; | |
562 | ||
563 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
564 | frame pointer, adjust the stack pointer, and save registers. |
565 | Do this until all basic prolog instructions are found. */ | |
c906108c | 566 | |
9b8d791a | 567 | cache->framesize = 0; |
da59e081 JM |
568 | for (current_pc = prologue_start; |
569 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
570 | current_pc += 2) | |
c906108c SS |
571 | { |
572 | unsigned short insn; | |
573 | int regno; | |
574 | int offset; | |
575 | ||
576 | insn = read_memory_unsigned_integer (current_pc, 2); | |
577 | ||
c5aa993b | 578 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 579 | { |
da59e081 | 580 | int mask; |
94c30b78 | 581 | findmask |= 1; /* push found */ |
c906108c SS |
582 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
583 | whether to save LR (R14). */ | |
da59e081 | 584 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 585 | |
b8d5e71d | 586 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 587 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 588 | if (mask & (1 << regno)) |
c5aa993b | 589 | { |
9b8d791a | 590 | cache->framesize += 4; |
eb5492fa | 591 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
592 | /* Reset saved register map. */ |
593 | saved_reg[regno] = regno; | |
c906108c SS |
594 | } |
595 | } | |
da3c6d4a MS |
596 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
597 | sub sp, #simm */ | |
c906108c | 598 | { |
b8d5e71d | 599 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
600 | continue; |
601 | else | |
94c30b78 | 602 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 603 | |
94c30b78 MS |
604 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
605 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 606 | { |
9b8d791a | 607 | cache->frameoffset += offset; |
da59e081 JM |
608 | offset = -offset; |
609 | } | |
9b8d791a | 610 | cache->framesize -= offset; |
c906108c SS |
611 | } |
612 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
613 | { | |
94c30b78 | 614 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 615 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 616 | /* get scaled offset */ |
9b8d791a | 617 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 618 | } |
da59e081 | 619 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 620 | { |
94c30b78 | 621 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
622 | cache->framereg = THUMB_FP_REGNUM; |
623 | cache->frameoffset = 0; | |
34e8f22d | 624 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
625 | } |
626 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
627 | { | |
da3c6d4a | 628 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 629 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 630 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
631 | } |
632 | else | |
da3c6d4a MS |
633 | /* Something in the prolog that we don't care about or some |
634 | instruction from outside the prolog scheduled here for | |
635 | optimization. */ | |
636 | continue; | |
c906108c SS |
637 | } |
638 | } | |
639 | ||
ed9a39eb | 640 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
641 | 1) the size of the stack frame |
642 | 2) which registers are saved on it | |
643 | 3) the offsets of saved regs | |
644 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
645 | This information is stored in the "extra" fields of the frame_info. |
646 | ||
96baa820 JM |
647 | There are two basic forms for the ARM prologue. The fixed argument |
648 | function call will look like: | |
ed9a39eb JM |
649 | |
650 | mov ip, sp | |
651 | stmfd sp!, {fp, ip, lr, pc} | |
652 | sub fp, ip, #4 | |
653 | [sub sp, sp, #4] | |
96baa820 | 654 | |
c906108c | 655 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
656 | IP -> 4 (caller's stack) |
657 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
658 | -4 LR (return address in caller) | |
659 | -8 IP (copy of caller's SP) | |
660 | -12 FP (caller's FP) | |
661 | SP -> -28 Local variables | |
662 | ||
c906108c | 663 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
664 | 28 bytes. The stmfd call can also save any of the vN registers it |
665 | plans to use, which increases the frame size accordingly. | |
666 | ||
667 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
668 | because the ARM Store instructions always store PC + 8 when you read | |
669 | the PC register. | |
ed9a39eb | 670 | |
96baa820 JM |
671 | A variable argument function call will look like: |
672 | ||
ed9a39eb JM |
673 | mov ip, sp |
674 | stmfd sp!, {a1, a2, a3, a4} | |
675 | stmfd sp!, {fp, ip, lr, pc} | |
676 | sub fp, ip, #20 | |
677 | ||
96baa820 | 678 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
679 | IP -> 20 (caller's stack) |
680 | 16 A4 | |
681 | 12 A3 | |
682 | 8 A2 | |
683 | 4 A1 | |
684 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
685 | -4 LR (return address in caller) | |
686 | -8 IP (copy of caller's SP) | |
687 | -12 FP (caller's FP) | |
688 | SP -> -28 Local variables | |
96baa820 JM |
689 | |
690 | The frame size would thus be 48 bytes, and the frame offset would be | |
691 | 28 bytes. | |
692 | ||
693 | There is another potential complication, which is that the optimizer | |
694 | will try to separate the store of fp in the "stmfd" instruction from | |
695 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
696 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
697 | ||
698 | Also, note, the original version of the ARM toolchain claimed that there | |
699 | should be an | |
700 | ||
701 | instruction at the end of the prologue. I have never seen GCC produce | |
702 | this, and the ARM docs don't mention it. We still test for it below in | |
703 | case it happens... | |
ed9a39eb JM |
704 | |
705 | */ | |
c906108c SS |
706 | |
707 | static void | |
eb5492fa | 708 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c SS |
709 | { |
710 | int regno, sp_offset, fp_offset; | |
711 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
eb5492fa | 712 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 713 | |
c906108c | 714 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
715 | cache->framereg = ARM_SP_REGNUM; |
716 | cache->framesize = 0; | |
717 | cache->frameoffset = 0; | |
c906108c SS |
718 | |
719 | /* Check for Thumb prologue. */ | |
eb5492fa | 720 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 721 | { |
eb5492fa | 722 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
723 | return; |
724 | } | |
725 | ||
726 | /* Find the function prologue. If we can't find the function in | |
727 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 728 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 729 | { |
2a451106 KB |
730 | /* One way to find the end of the prologue (which works well |
731 | for unoptimized code) is to do the following: | |
732 | ||
733 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
734 | ||
735 | if (sal.line == 0) | |
eb5492fa | 736 | prologue_end = prev_pc; |
2a451106 KB |
737 | else if (sal.end < prologue_end) |
738 | prologue_end = sal.end; | |
739 | ||
740 | This mechanism is very accurate so long as the optimizer | |
741 | doesn't move any instructions from the function body into the | |
742 | prologue. If this happens, sal.end will be the last | |
743 | instruction in the first hunk of prologue code just before | |
744 | the first instruction that the scheduler has moved from | |
745 | the body to the prologue. | |
746 | ||
747 | In order to make sure that we scan all of the prologue | |
748 | instructions, we use a slightly less accurate mechanism which | |
749 | may scan more than necessary. To help compensate for this | |
750 | lack of accuracy, the prologue scanning loop below contains | |
751 | several clauses which'll cause the loop to terminate early if | |
752 | an implausible prologue instruction is encountered. | |
753 | ||
754 | The expression | |
755 | ||
756 | prologue_start + 64 | |
757 | ||
758 | is a suitable endpoint since it accounts for the largest | |
759 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 760 | the scheduler. */ |
2a451106 KB |
761 | |
762 | if (prologue_end > prologue_start + 64) | |
763 | { | |
94c30b78 | 764 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 765 | } |
c906108c SS |
766 | } |
767 | else | |
768 | { | |
eb5492fa DJ |
769 | /* We have no symbol information. Our only option is to assume this |
770 | function has a standard stack frame and the normal frame register. | |
771 | Then, we can find the value of our frame pointer on entrance to | |
772 | the callee (or at the present moment if this is the innermost frame). | |
773 | The value stored there should be the address of the stmfd + 8. */ | |
774 | CORE_ADDR frame_loc; | |
775 | LONGEST return_value; | |
776 | ||
777 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
778 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
779 | return; |
780 | else | |
781 | { | |
782 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 783 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 784 | } |
c906108c SS |
785 | } |
786 | ||
eb5492fa DJ |
787 | if (prev_pc < prologue_end) |
788 | prologue_end = prev_pc; | |
789 | ||
c906108c | 790 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 791 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 792 | |
96baa820 JM |
793 | Be careful, however, and if it doesn't look like a prologue, |
794 | don't try to scan it. If, for instance, a frameless function | |
795 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 796 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
797 | and other operations that rely on a knowledge of the stack |
798 | traceback. | |
799 | ||
800 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 801 | if we don't see this as the first insn, we will stop. |
c906108c | 802 | |
f43845b3 MS |
803 | [Note: This doesn't seem to be true any longer, so it's now an |
804 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 805 | |
f43845b3 MS |
806 | [Note further: The "mov ip,sp" only seems to be missing in |
807 | frameless functions at optimization level "-O2" or above, | |
808 | in which case it is often (but not always) replaced by | |
b8d5e71d | 809 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 810 | |
f43845b3 MS |
811 | sp_offset = fp_offset = 0; |
812 | ||
94c30b78 MS |
813 | for (current_pc = prologue_start; |
814 | current_pc < prologue_end; | |
f43845b3 | 815 | current_pc += 4) |
96baa820 | 816 | { |
d4473757 KB |
817 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
818 | ||
94c30b78 | 819 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
820 | { |
821 | continue; | |
822 | } | |
94c30b78 | 823 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
824 | { |
825 | /* Function is frameless: extra_info defaults OK? */ | |
826 | continue; | |
827 | } | |
828 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
829 | /* stmfd sp!, {..., fp, ip, lr, pc} |
830 | or | |
831 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 832 | { |
d4473757 | 833 | int mask = insn & 0xffff; |
ed9a39eb | 834 | |
94c30b78 | 835 | /* Calculate offsets of saved registers. */ |
34e8f22d | 836 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
837 | if (mask & (1 << regno)) |
838 | { | |
839 | sp_offset -= 4; | |
eb5492fa | 840 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
841 | } |
842 | } | |
b8d5e71d MS |
843 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
844 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
845 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
846 | { | |
847 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
848 | continue; | |
849 | } | |
850 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
851 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
852 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
853 | { |
854 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
855 | continue; | |
856 | } | |
d4473757 KB |
857 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
858 | { | |
94c30b78 MS |
859 | unsigned imm = insn & 0xff; /* immediate value */ |
860 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
861 | imm = (imm >> rot) | (imm << (32 - rot)); |
862 | fp_offset = -imm; | |
9b8d791a | 863 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
864 | } |
865 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
866 | { | |
94c30b78 MS |
867 | unsigned imm = insn & 0xff; /* immediate value */ |
868 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
869 | imm = (imm >> rot) | (imm << (32 - rot)); |
870 | sp_offset -= imm; | |
871 | } | |
872 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
873 | { | |
874 | sp_offset -= 12; | |
34e8f22d | 875 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 876 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
877 | } |
878 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
879 | { | |
880 | int n_saved_fp_regs; | |
881 | unsigned int fp_start_reg, fp_bound_reg; | |
882 | ||
94c30b78 | 883 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 884 | { |
d4473757 KB |
885 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
886 | n_saved_fp_regs = 3; | |
887 | else | |
888 | n_saved_fp_regs = 1; | |
96baa820 | 889 | } |
d4473757 | 890 | else |
96baa820 | 891 | { |
d4473757 KB |
892 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
893 | n_saved_fp_regs = 2; | |
894 | else | |
895 | n_saved_fp_regs = 4; | |
96baa820 | 896 | } |
d4473757 | 897 | |
34e8f22d | 898 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
899 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
900 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
901 | { |
902 | sp_offset -= 12; | |
eb5492fa | 903 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 904 | } |
c906108c | 905 | } |
d4473757 | 906 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 907 | break; /* Condition not true, exit early */ |
b8d5e71d | 908 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 909 | break; /* Don't scan past a block load */ |
d4473757 KB |
910 | else |
911 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 912 | so we just skip what we don't recognize. */ |
d4473757 | 913 | continue; |
c906108c SS |
914 | } |
915 | ||
94c30b78 MS |
916 | /* The frame size is just the negative of the offset (from the |
917 | original SP) of the last thing thing we pushed on the stack. | |
918 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
919 | cache->framesize = -sp_offset; |
920 | if (cache->framereg == ARM_FP_REGNUM) | |
921 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 922 | else |
9b8d791a | 923 | cache->frameoffset = 0; |
c906108c SS |
924 | } |
925 | ||
eb5492fa DJ |
926 | static struct arm_prologue_cache * |
927 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 928 | { |
eb5492fa DJ |
929 | int reg; |
930 | struct arm_prologue_cache *cache; | |
931 | CORE_ADDR unwound_fp; | |
c5aa993b | 932 | |
eb5492fa DJ |
933 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
934 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 935 | |
eb5492fa | 936 | arm_scan_prologue (next_frame, cache); |
848cfffb | 937 | |
eb5492fa DJ |
938 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
939 | if (unwound_fp == 0) | |
940 | return cache; | |
c906108c | 941 | |
eb5492fa | 942 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 943 | |
eb5492fa DJ |
944 | /* Calculate actual addresses of saved registers using offsets |
945 | determined by arm_scan_prologue. */ | |
946 | for (reg = 0; reg < NUM_REGS; reg++) | |
947 | if (cache->saved_regs[reg].addr != 0) | |
948 | cache->saved_regs[reg].addr += cache->prev_sp; | |
949 | ||
950 | return cache; | |
c906108c SS |
951 | } |
952 | ||
eb5492fa DJ |
953 | /* Our frame ID for a normal frame is the current function's starting PC |
954 | and the caller's SP when we were called. */ | |
c906108c | 955 | |
148754e5 | 956 | static void |
eb5492fa DJ |
957 | arm_prologue_this_id (struct frame_info *next_frame, |
958 | void **this_cache, | |
959 | struct frame_id *this_id) | |
c906108c | 960 | { |
eb5492fa DJ |
961 | struct arm_prologue_cache *cache; |
962 | struct frame_id id; | |
963 | CORE_ADDR func; | |
f079148d | 964 | |
eb5492fa DJ |
965 | if (*this_cache == NULL) |
966 | *this_cache = arm_make_prologue_cache (next_frame); | |
967 | cache = *this_cache; | |
2a451106 | 968 | |
eb5492fa | 969 | func = frame_func_unwind (next_frame); |
2a451106 | 970 | |
eb5492fa DJ |
971 | /* This is meant to halt the backtrace at "_start". Make sure we |
972 | don't halt it at a generic dummy frame. */ | |
973 | if (func <= LOWEST_PC || inside_entry_file (func)) | |
974 | return; | |
5a203e44 | 975 | |
eb5492fa DJ |
976 | /* If we've hit a wall, stop. */ |
977 | if (cache->prev_sp == 0) | |
978 | return; | |
24de872b | 979 | |
eb5492fa | 980 | id = frame_id_build (cache->prev_sp, func); |
c906108c | 981 | |
eb5492fa DJ |
982 | /* Check that we're not going round in circles with the same frame |
983 | ID (but avoid applying the test to sentinel frames which do go | |
984 | round in circles). */ | |
985 | if (frame_relative_level (next_frame) >= 0 | |
986 | && get_frame_type (next_frame) == NORMAL_FRAME | |
987 | && frame_id_eq (get_frame_id (next_frame), id)) | |
988 | return; | |
989 | ||
990 | *this_id = id; | |
c906108c SS |
991 | } |
992 | ||
eb5492fa DJ |
993 | static void |
994 | arm_prologue_prev_register (struct frame_info *next_frame, | |
995 | void **this_cache, | |
996 | int prev_regnum, | |
997 | int *optimized, | |
998 | enum lval_type *lvalp, | |
999 | CORE_ADDR *addrp, | |
1000 | int *realnump, | |
1001 | void *valuep) | |
24de872b DJ |
1002 | { |
1003 | struct arm_prologue_cache *cache; | |
1004 | ||
eb5492fa DJ |
1005 | if (*this_cache == NULL) |
1006 | *this_cache = arm_make_prologue_cache (next_frame); | |
1007 | cache = *this_cache; | |
24de872b | 1008 | |
eb5492fa DJ |
1009 | /* If we are asked to unwind the PC, then we need to return the LR |
1010 | instead. The saved value of PC points into this frame's | |
1011 | prologue, not the next frame's resume location. */ | |
1012 | if (prev_regnum == ARM_PC_REGNUM) | |
1013 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 1014 | |
eb5492fa DJ |
1015 | /* SP is generally not saved to the stack, but this frame is |
1016 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
1017 | The value was already reconstructed into PREV_SP. */ | |
1018 | if (prev_regnum == ARM_SP_REGNUM) | |
1019 | { | |
1020 | *lvalp = not_lval; | |
1021 | if (valuep) | |
1022 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
1023 | return; | |
1024 | } | |
1025 | ||
1026 | trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, | |
1027 | optimized, lvalp, addrp, realnump, valuep); | |
1028 | } | |
1029 | ||
1030 | struct frame_unwind arm_prologue_unwind = { | |
1031 | NORMAL_FRAME, | |
1032 | arm_prologue_this_id, | |
1033 | arm_prologue_prev_register | |
1034 | }; | |
1035 | ||
1036 | static const struct frame_unwind * | |
1037 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
1038 | { | |
1039 | return &arm_prologue_unwind; | |
24de872b DJ |
1040 | } |
1041 | ||
1042 | static CORE_ADDR | |
eb5492fa | 1043 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1044 | { |
1045 | struct arm_prologue_cache *cache; | |
1046 | ||
eb5492fa DJ |
1047 | if (*this_cache == NULL) |
1048 | *this_cache = arm_make_prologue_cache (next_frame); | |
1049 | cache = *this_cache; | |
1050 | ||
1051 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1052 | } |
1053 | ||
eb5492fa DJ |
1054 | struct frame_base arm_normal_base = { |
1055 | &arm_prologue_unwind, | |
1056 | arm_normal_frame_base, | |
1057 | arm_normal_frame_base, | |
1058 | arm_normal_frame_base | |
1059 | }; | |
1060 | ||
1061 | static struct arm_prologue_cache * | |
1062 | arm_make_sigtramp_cache (struct frame_info *next_frame) | |
24de872b DJ |
1063 | { |
1064 | struct arm_prologue_cache *cache; | |
eb5492fa DJ |
1065 | int reg; |
1066 | ||
1067 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
24de872b | 1068 | |
eb5492fa | 1069 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
24de872b | 1070 | |
eb5492fa | 1071 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
24de872b | 1072 | |
eb5492fa DJ |
1073 | for (reg = 0; reg < NUM_REGS; reg++) |
1074 | cache->saved_regs[reg].addr | |
1075 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, | |
1076 | frame_pc_unwind (next_frame), reg); | |
24de872b | 1077 | |
eb5492fa DJ |
1078 | /* FIXME: What about thumb mode? */ |
1079 | cache->framereg = ARM_SP_REGNUM; | |
1080 | cache->prev_sp | |
1081 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, | |
1082 | REGISTER_RAW_SIZE (cache->framereg)); | |
1083 | ||
1084 | return cache; | |
24de872b | 1085 | } |
c906108c | 1086 | |
eb5492fa DJ |
1087 | static void |
1088 | arm_sigtramp_this_id (struct frame_info *next_frame, | |
1089 | void **this_cache, | |
1090 | struct frame_id *this_id) | |
1091 | { | |
1092 | struct arm_prologue_cache *cache; | |
c906108c | 1093 | |
eb5492fa DJ |
1094 | if (*this_cache == NULL) |
1095 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1096 | cache = *this_cache; | |
c906108c | 1097 | |
eb5492fa DJ |
1098 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
1099 | the sigtramp frame; the PC should be the beginning of the trampoline. */ | |
1100 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); | |
1101 | } | |
1102 | ||
1103 | static void | |
1104 | arm_sigtramp_prev_register (struct frame_info *next_frame, | |
1105 | void **this_cache, | |
1106 | int prev_regnum, | |
1107 | int *optimized, | |
1108 | enum lval_type *lvalp, | |
1109 | CORE_ADDR *addrp, | |
1110 | int *realnump, | |
1111 | void *valuep) | |
c906108c | 1112 | { |
eb5492fa | 1113 | struct arm_prologue_cache *cache; |
848cfffb | 1114 | |
eb5492fa DJ |
1115 | if (*this_cache == NULL) |
1116 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1117 | cache = *this_cache; | |
1118 | ||
1119 | trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, | |
1120 | optimized, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1121 | } |
1122 | ||
eb5492fa DJ |
1123 | struct frame_unwind arm_sigtramp_unwind = { |
1124 | SIGTRAMP_FRAME, | |
1125 | arm_sigtramp_this_id, | |
1126 | arm_sigtramp_prev_register | |
1127 | }; | |
c906108c | 1128 | |
eb5492fa DJ |
1129 | static const struct frame_unwind * |
1130 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) | |
c906108c | 1131 | { |
eb5492fa DJ |
1132 | /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1133 | against the name of the function, the code below will have to be | |
1134 | changed to first fetch the name of the function and then pass | |
1135 | this name to PC_IN_SIGTRAMP. */ | |
1136 | ||
1137 | if (SIGCONTEXT_REGISTER_ADDRESS_P () | |
1138 | && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame), (char *) 0)) | |
1139 | return &arm_sigtramp_unwind; | |
1140 | ||
1141 | return NULL; | |
c906108c SS |
1142 | } |
1143 | ||
eb5492fa DJ |
1144 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1145 | dummy frame. The frame ID's base needs to match the TOS value | |
1146 | saved by save_dummy_frame_tos() and returned from | |
1147 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1148 | breakpoint. */ | |
c906108c | 1149 | |
eb5492fa DJ |
1150 | static struct frame_id |
1151 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1152 | { |
eb5492fa DJ |
1153 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1154 | frame_pc_unwind (next_frame)); | |
1155 | } | |
c3b4394c | 1156 | |
eb5492fa DJ |
1157 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1158 | be used to construct the previous frame's ID, after looking up the | |
1159 | containing function). */ | |
c3b4394c | 1160 | |
eb5492fa DJ |
1161 | static CORE_ADDR |
1162 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1163 | { | |
1164 | CORE_ADDR pc; | |
1165 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1166 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1167 | } | |
1168 | ||
1169 | static CORE_ADDR | |
1170 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1171 | { | |
1172 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1173 | } |
1174 | ||
848cfffb AC |
1175 | /* Set the return address for a generic dummy frame. ARM uses the |
1176 | entry point. */ | |
1177 | ||
1178 | static CORE_ADDR | |
1179 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1180 | { | |
88a82a65 | 1181 | write_register (ARM_LR_REGNUM, entry_point_address ()); |
848cfffb AC |
1182 | return sp; |
1183 | } | |
1184 | ||
148754e5 RE |
1185 | /* Push an empty stack frame, to record the current PC, etc. */ |
1186 | ||
1187 | static void | |
ed9a39eb | 1188 | arm_push_dummy_frame (void) |
c906108c | 1189 | { |
34e8f22d | 1190 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1191 | CORE_ADDR sp = old_sp; |
1192 | CORE_ADDR fp, prologue_start; | |
1193 | int regnum; | |
1194 | ||
1195 | /* Push the two dummy prologue instructions in reverse order, | |
1196 | so that they'll be in the correct low-to-high order in memory. */ | |
1197 | /* sub fp, ip, #4 */ | |
1198 | sp = push_word (sp, 0xe24cb004); | |
1199 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1200 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1201 | ||
ed9a39eb JM |
1202 | /* Push a pointer to the dummy prologue + 12, because when stm |
1203 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1204 | instruction itself plus 12. */ |
1205 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1206 | |
f079148d | 1207 | /* Push the processor status. */ |
34e8f22d | 1208 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1209 | |
1210 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1211 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1212 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1213 | |
f079148d | 1214 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1215 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1216 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1217 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1218 | } |
1219 | ||
b1e29e33 | 1220 | /* DEPRECATED_CALL_DUMMY_WORDS: |
6eb69eab RE |
1221 | This sequence of words is the instructions |
1222 | ||
1223 | mov lr,pc | |
1224 | mov pc,r4 | |
1225 | illegal | |
1226 | ||
1227 | Note this is 12 bytes. */ | |
1228 | ||
34e8f22d | 1229 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1230 | { |
1231 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1232 | }; | |
1233 | ||
3fb4b924 RE |
1234 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1235 | breakpoint to the proper address in the call dummy, so that | |
1236 | `finish' after a stop in a call dummy works. | |
1237 | ||
d7b486e7 RE |
1238 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1239 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
04714b91 AC |
1240 | followed by a call to call_function_by_hand, which is the only |
1241 | function where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1242 | |
1243 | ||
1244 | static void | |
1245 | arm_set_call_dummy_breakpoint_offset (void) | |
1246 | { | |
1247 | if (caller_is_thumb) | |
b1e29e33 | 1248 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 4); |
3fb4b924 | 1249 | else |
b1e29e33 | 1250 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 8); |
3fb4b924 RE |
1251 | } |
1252 | ||
c906108c | 1253 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1254 | in Thumb or ARM mode, and whether the target function is Thumb or |
1255 | ARM. There are three different situations requiring three | |
c906108c SS |
1256 | different dummies: |
1257 | ||
1258 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1259 | been copied into the dummy parameter to this function. |
c906108c | 1260 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1261 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1262 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1263 | works for calling both ARM and Thumb functions. |
c906108c | 1264 | |
ed9a39eb JM |
1265 | All three call dummies expect to receive the target function |
1266 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1267 | |
34e8f22d | 1268 | static void |
ed9a39eb | 1269 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1270 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1271 | { |
1272 | static short thumb_dummy[4] = | |
1273 | { | |
c5aa993b JM |
1274 | 0xf000, 0xf801, /* bl label */ |
1275 | 0xdf18, /* swi 24 */ | |
1276 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1277 | }; |
1278 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1279 | ||
94c30b78 | 1280 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1281 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1282 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1283 | |
ed9a39eb JM |
1284 | /* If the target function is Thumb, set the low bit of the function |
1285 | address. And if the CPU is currently in ARM mode, patch the | |
1286 | second instruction of call dummy to use a BX instruction to | |
1287 | switch to Thumb mode. */ | |
c906108c SS |
1288 | target_is_thumb = arm_pc_is_thumb (fun); |
1289 | if (target_is_thumb) | |
1290 | { | |
1291 | fun |= 1; | |
1292 | if (!caller_is_thumb) | |
1293 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1294 | } | |
1295 | ||
1296 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1297 | instead of the ARM one that's already been copied. This will | |
1298 | work for both Thumb and ARM target functions. */ | |
1299 | if (caller_is_thumb) | |
1300 | { | |
1301 | int i; | |
1302 | char *p = dummy; | |
1303 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1304 | ||
1305 | for (i = 0; i < len; i++) | |
1306 | { | |
1307 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1308 | p += sizeof (thumb_dummy[0]); | |
1309 | } | |
1310 | } | |
1311 | ||
ed9a39eb | 1312 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1313 | the PC. */ |
c906108c SS |
1314 | write_register (4, fun); |
1315 | } | |
1316 | ||
2dd604e7 RE |
1317 | /* When arguments must be pushed onto the stack, they go on in reverse |
1318 | order. The code below implements a FILO (stack) to do this. */ | |
1319 | ||
1320 | struct stack_item | |
1321 | { | |
1322 | int len; | |
1323 | struct stack_item *prev; | |
1324 | void *data; | |
1325 | }; | |
1326 | ||
1327 | static struct stack_item * | |
1328 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1329 | { | |
1330 | struct stack_item *si; | |
1331 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1332 | si->data = xmalloc (len); |
2dd604e7 RE |
1333 | si->len = len; |
1334 | si->prev = prev; | |
1335 | memcpy (si->data, contents, len); | |
1336 | return si; | |
1337 | } | |
1338 | ||
1339 | static struct stack_item * | |
1340 | pop_stack_item (struct stack_item *si) | |
1341 | { | |
1342 | struct stack_item *dead = si; | |
1343 | si = si->prev; | |
1344 | xfree (dead->data); | |
1345 | xfree (dead); | |
1346 | return si; | |
1347 | } | |
1348 | ||
1349 | /* We currently only support passing parameters in integer registers. This | |
1350 | conforms with GCC's default model. Several other variants exist and | |
1351 | we should probably support some of them based on the selected ABI. */ | |
1352 | ||
1353 | static CORE_ADDR | |
6a65450a AC |
1354 | arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1355 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
1356 | struct value **args, CORE_ADDR sp, int struct_return, | |
1357 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1358 | { |
1359 | int argnum; | |
1360 | int argreg; | |
1361 | int nstack; | |
1362 | struct stack_item *si = NULL; | |
1363 | ||
6a65450a AC |
1364 | /* Set the return address. For the ARM, the return breakpoint is |
1365 | always at BP_ADDR. */ | |
2dd604e7 | 1366 | /* XXX Fix for Thumb. */ |
6a65450a | 1367 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1368 | |
1369 | /* Walk through the list of args and determine how large a temporary | |
1370 | stack is required. Need to take care here as structs may be | |
1371 | passed on the stack, and we have to to push them. */ | |
1372 | nstack = 0; | |
1373 | ||
1374 | argreg = ARM_A1_REGNUM; | |
1375 | nstack = 0; | |
1376 | ||
1377 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1378 | is correctly aligned before we start. We always do this even if | |
1379 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1380 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1381 | |
1382 | /* The struct_return pointer occupies the first parameter | |
1383 | passing register. */ | |
1384 | if (struct_return) | |
1385 | { | |
1386 | if (arm_debug) | |
1387 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1388 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1389 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1390 | argreg++; | |
1391 | } | |
1392 | ||
1393 | for (argnum = 0; argnum < nargs; argnum++) | |
1394 | { | |
1395 | int len; | |
1396 | struct type *arg_type; | |
1397 | struct type *target_type; | |
1398 | enum type_code typecode; | |
1399 | char *val; | |
1400 | ||
1401 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1402 | len = TYPE_LENGTH (arg_type); | |
1403 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1404 | typecode = TYPE_CODE (arg_type); | |
1405 | val = VALUE_CONTENTS (args[argnum]); | |
1406 | ||
1407 | /* If the argument is a pointer to a function, and it is a | |
1408 | Thumb function, create a LOCAL copy of the value and set | |
1409 | the THUMB bit in it. */ | |
1410 | if (TYPE_CODE_PTR == typecode | |
1411 | && target_type != NULL | |
1412 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1413 | { | |
7c0b4a20 | 1414 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1415 | if (arm_pc_is_thumb (regval)) |
1416 | { | |
1417 | val = alloca (len); | |
fbd9dcd3 | 1418 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1419 | } |
1420 | } | |
1421 | ||
1422 | /* Copy the argument to general registers or the stack in | |
1423 | register-sized pieces. Large arguments are split between | |
1424 | registers and stack. */ | |
1425 | while (len > 0) | |
1426 | { | |
b1e29e33 | 1427 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1428 | |
1429 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1430 | { | |
1431 | /* The argument is being passed in a general purpose | |
1432 | register. */ | |
7c0b4a20 | 1433 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1434 | if (arm_debug) |
1435 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1436 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1437 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1438 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1439 | argreg++; | |
1440 | } | |
1441 | else | |
1442 | { | |
1443 | /* Push the arguments onto the stack. */ | |
1444 | if (arm_debug) | |
1445 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1446 | argnum, nstack); | |
b1e29e33 AC |
1447 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1448 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1449 | } |
1450 | ||
1451 | len -= partial_len; | |
1452 | val += partial_len; | |
1453 | } | |
1454 | } | |
1455 | /* If we have an odd number of words to push, then decrement the stack | |
1456 | by one word now, so first stack argument will be dword aligned. */ | |
1457 | if (nstack & 4) | |
1458 | sp -= 4; | |
1459 | ||
1460 | while (si) | |
1461 | { | |
1462 | sp -= si->len; | |
1463 | write_memory (sp, si->data, si->len); | |
1464 | si = pop_stack_item (si); | |
1465 | } | |
1466 | ||
1467 | /* Finally, update teh SP register. */ | |
1468 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1469 | ||
1470 | return sp; | |
1471 | } | |
1472 | ||
c906108c | 1473 | static void |
ed9a39eb | 1474 | print_fpu_flags (int flags) |
c906108c | 1475 | { |
c5aa993b JM |
1476 | if (flags & (1 << 0)) |
1477 | fputs ("IVO ", stdout); | |
1478 | if (flags & (1 << 1)) | |
1479 | fputs ("DVZ ", stdout); | |
1480 | if (flags & (1 << 2)) | |
1481 | fputs ("OFL ", stdout); | |
1482 | if (flags & (1 << 3)) | |
1483 | fputs ("UFL ", stdout); | |
1484 | if (flags & (1 << 4)) | |
1485 | fputs ("INX ", stdout); | |
1486 | putchar ('\n'); | |
c906108c SS |
1487 | } |
1488 | ||
5e74b15c RE |
1489 | /* Print interesting information about the floating point processor |
1490 | (if present) or emulator. */ | |
34e8f22d | 1491 | static void |
d855c300 | 1492 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1493 | struct frame_info *frame, const char *args) |
c906108c | 1494 | { |
34e8f22d | 1495 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1496 | int type; |
1497 | ||
1498 | type = (status >> 24) & 127; | |
1499 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1500 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1501 | type); |
1502 | fputs ("mask: ", stdout); | |
1503 | print_fpu_flags (status >> 16); | |
1504 | fputs ("flags: ", stdout); | |
1505 | print_fpu_flags (status); | |
c906108c SS |
1506 | } |
1507 | ||
34e8f22d RE |
1508 | /* Return the GDB type object for the "standard" data type of data in |
1509 | register N. */ | |
1510 | ||
1511 | static struct type * | |
032758dc AC |
1512 | arm_register_type (int regnum) |
1513 | { | |
34e8f22d | 1514 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1515 | { |
d7449b42 | 1516 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1517 | return builtin_type_arm_ext_big; |
1518 | else | |
1519 | return builtin_type_arm_ext_littlebyte_bigword; | |
1520 | } | |
1521 | else | |
1522 | return builtin_type_int32; | |
1523 | } | |
1524 | ||
34e8f22d RE |
1525 | /* Index within `registers' of the first byte of the space for |
1526 | register N. */ | |
1527 | ||
1528 | static int | |
1529 | arm_register_byte (int regnum) | |
1530 | { | |
1531 | if (regnum < ARM_F0_REGNUM) | |
1532 | return regnum * INT_REGISTER_RAW_SIZE; | |
1533 | else if (regnum < ARM_PS_REGNUM) | |
1534 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1535 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1536 | else | |
1537 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1538 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1539 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1540 | } | |
1541 | ||
1542 | /* Number of bytes of storage in the actual machine representation for | |
1543 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1544 | 12 bytes in length. */ | |
1545 | ||
1546 | static int | |
1547 | arm_register_raw_size (int regnum) | |
1548 | { | |
1549 | if (regnum < ARM_F0_REGNUM) | |
1550 | return INT_REGISTER_RAW_SIZE; | |
1551 | else if (regnum < ARM_FPS_REGNUM) | |
1552 | return FP_REGISTER_RAW_SIZE; | |
1553 | else | |
1554 | return STATUS_REGISTER_SIZE; | |
1555 | } | |
1556 | ||
1557 | /* Number of bytes of storage in a program's representation | |
1558 | for register N. */ | |
1559 | static int | |
1560 | arm_register_virtual_size (int regnum) | |
1561 | { | |
1562 | if (regnum < ARM_F0_REGNUM) | |
1563 | return INT_REGISTER_VIRTUAL_SIZE; | |
1564 | else if (regnum < ARM_FPS_REGNUM) | |
1565 | return FP_REGISTER_VIRTUAL_SIZE; | |
1566 | else | |
1567 | return STATUS_REGISTER_SIZE; | |
1568 | } | |
1569 | ||
26216b98 AC |
1570 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1571 | static int | |
1572 | arm_register_sim_regno (int regnum) | |
1573 | { | |
1574 | int reg = regnum; | |
1575 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1576 | ||
1577 | if (reg < NUM_GREGS) | |
1578 | return SIM_ARM_R0_REGNUM + reg; | |
1579 | reg -= NUM_GREGS; | |
1580 | ||
1581 | if (reg < NUM_FREGS) | |
1582 | return SIM_ARM_FP0_REGNUM + reg; | |
1583 | reg -= NUM_FREGS; | |
1584 | ||
1585 | if (reg < NUM_SREGS) | |
1586 | return SIM_ARM_FPS_REGNUM + reg; | |
1587 | reg -= NUM_SREGS; | |
1588 | ||
1589 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1590 | } | |
34e8f22d | 1591 | |
a37b3cc0 AC |
1592 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1593 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1594 | It is thought that this is is the floating-point register format on | |
1595 | little-endian systems. */ | |
c906108c | 1596 | |
ed9a39eb | 1597 | static void |
b508a996 RE |
1598 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1599 | void *dbl) | |
c906108c | 1600 | { |
a37b3cc0 | 1601 | DOUBLEST d; |
d7449b42 | 1602 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1603 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1604 | else | |
1605 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1606 | ptr, &d); | |
b508a996 | 1607 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1608 | } |
1609 | ||
34e8f22d | 1610 | static void |
b508a996 | 1611 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1612 | { |
a37b3cc0 | 1613 | DOUBLEST d; |
b508a996 | 1614 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1615 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1616 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1617 | else | |
1618 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1619 | &d, dbl); | |
c906108c | 1620 | } |
ed9a39eb | 1621 | |
c906108c | 1622 | static int |
ed9a39eb | 1623 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1624 | { |
1625 | if (cond == INST_AL || cond == INST_NV) | |
1626 | return 1; | |
1627 | ||
1628 | switch (cond) | |
1629 | { | |
1630 | case INST_EQ: | |
1631 | return ((status_reg & FLAG_Z) != 0); | |
1632 | case INST_NE: | |
1633 | return ((status_reg & FLAG_Z) == 0); | |
1634 | case INST_CS: | |
1635 | return ((status_reg & FLAG_C) != 0); | |
1636 | case INST_CC: | |
1637 | return ((status_reg & FLAG_C) == 0); | |
1638 | case INST_MI: | |
1639 | return ((status_reg & FLAG_N) != 0); | |
1640 | case INST_PL: | |
1641 | return ((status_reg & FLAG_N) == 0); | |
1642 | case INST_VS: | |
1643 | return ((status_reg & FLAG_V) != 0); | |
1644 | case INST_VC: | |
1645 | return ((status_reg & FLAG_V) == 0); | |
1646 | case INST_HI: | |
1647 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1648 | case INST_LS: | |
1649 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1650 | case INST_GE: | |
1651 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1652 | case INST_LT: | |
1653 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1654 | case INST_GT: | |
1655 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1656 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1657 | case INST_LE: |
1658 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1659 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1660 | } |
1661 | return 1; | |
1662 | } | |
1663 | ||
9512d7fd | 1664 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1665 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1666 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1667 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1668 | #define sbits(obj,st,fn) \ | |
1669 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1670 | #define BranchDest(addr,instr) \ | |
1671 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1672 | #define ARM_PC_32 1 | |
1673 | ||
1674 | static unsigned long | |
ed9a39eb JM |
1675 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1676 | unsigned long status_reg) | |
c906108c SS |
1677 | { |
1678 | unsigned long res, shift; | |
1679 | int rm = bits (inst, 0, 3); | |
1680 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1681 | |
1682 | if (bit (inst, 4)) | |
c906108c SS |
1683 | { |
1684 | int rs = bits (inst, 8, 11); | |
1685 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1686 | } | |
1687 | else | |
1688 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1689 | |
1690 | res = (rm == 15 | |
c906108c | 1691 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1692 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1693 | : read_register (rm)); |
1694 | ||
1695 | switch (shifttype) | |
1696 | { | |
c5aa993b | 1697 | case 0: /* LSL */ |
c906108c SS |
1698 | res = shift >= 32 ? 0 : res << shift; |
1699 | break; | |
c5aa993b JM |
1700 | |
1701 | case 1: /* LSR */ | |
c906108c SS |
1702 | res = shift >= 32 ? 0 : res >> shift; |
1703 | break; | |
1704 | ||
c5aa993b JM |
1705 | case 2: /* ASR */ |
1706 | if (shift >= 32) | |
1707 | shift = 31; | |
c906108c SS |
1708 | res = ((res & 0x80000000L) |
1709 | ? ~((~res) >> shift) : res >> shift); | |
1710 | break; | |
1711 | ||
c5aa993b | 1712 | case 3: /* ROR/RRX */ |
c906108c SS |
1713 | shift &= 31; |
1714 | if (shift == 0) | |
1715 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1716 | else | |
c5aa993b | 1717 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1718 | break; |
1719 | } | |
1720 | ||
1721 | return res & 0xffffffff; | |
1722 | } | |
1723 | ||
c906108c SS |
1724 | /* Return number of 1-bits in VAL. */ |
1725 | ||
1726 | static int | |
ed9a39eb | 1727 | bitcount (unsigned long val) |
c906108c SS |
1728 | { |
1729 | int nbits; | |
1730 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1731 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1732 | return nbits; |
1733 | } | |
1734 | ||
34e8f22d | 1735 | CORE_ADDR |
ed9a39eb | 1736 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1737 | { |
c5aa993b | 1738 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1739 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1740 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1741 | unsigned long offset; |
1742 | ||
1743 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1744 | { | |
1745 | CORE_ADDR sp; | |
1746 | ||
1747 | /* Fetch the saved PC from the stack. It's stored above | |
1748 | all of the other registers. */ | |
b1e29e33 | 1749 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1750 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1751 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1752 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1753 | if (nextpc == pc) | |
1754 | error ("Infinite loop detected"); | |
1755 | } | |
1756 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1757 | { | |
34e8f22d | 1758 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1759 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1760 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1761 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1762 | } | |
1763 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1764 | { | |
1765 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1766 | } | |
1767 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1768 | { | |
1769 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1770 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1771 | nextpc = pc_val + offset; |
1772 | } | |
1773 | ||
1774 | return nextpc; | |
1775 | } | |
1776 | ||
34e8f22d | 1777 | CORE_ADDR |
ed9a39eb | 1778 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1779 | { |
1780 | unsigned long pc_val; | |
1781 | unsigned long this_instr; | |
1782 | unsigned long status; | |
1783 | CORE_ADDR nextpc; | |
1784 | ||
1785 | if (arm_pc_is_thumb (pc)) | |
1786 | return thumb_get_next_pc (pc); | |
1787 | ||
1788 | pc_val = (unsigned long) pc; | |
1789 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1790 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1791 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1792 | |
1793 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1794 | { | |
1795 | switch (bits (this_instr, 24, 27)) | |
1796 | { | |
c5aa993b | 1797 | case 0x0: |
94c30b78 | 1798 | case 0x1: /* data processing */ |
c5aa993b JM |
1799 | case 0x2: |
1800 | case 0x3: | |
c906108c SS |
1801 | { |
1802 | unsigned long operand1, operand2, result = 0; | |
1803 | unsigned long rn; | |
1804 | int c; | |
c5aa993b | 1805 | |
c906108c SS |
1806 | if (bits (this_instr, 12, 15) != 15) |
1807 | break; | |
1808 | ||
1809 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1810 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1811 | error ("Illegal update to pc in instruction"); |
1812 | ||
1813 | /* Multiply into PC */ | |
1814 | c = (status & FLAG_C) ? 1 : 0; | |
1815 | rn = bits (this_instr, 16, 19); | |
1816 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1817 | |
c906108c SS |
1818 | if (bit (this_instr, 25)) |
1819 | { | |
1820 | unsigned long immval = bits (this_instr, 0, 7); | |
1821 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1822 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1823 | & 0xffffffff; | |
c906108c | 1824 | } |
c5aa993b | 1825 | else /* operand 2 is a shifted register */ |
c906108c | 1826 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1827 | |
c906108c SS |
1828 | switch (bits (this_instr, 21, 24)) |
1829 | { | |
c5aa993b | 1830 | case 0x0: /*and */ |
c906108c SS |
1831 | result = operand1 & operand2; |
1832 | break; | |
1833 | ||
c5aa993b | 1834 | case 0x1: /*eor */ |
c906108c SS |
1835 | result = operand1 ^ operand2; |
1836 | break; | |
1837 | ||
c5aa993b | 1838 | case 0x2: /*sub */ |
c906108c SS |
1839 | result = operand1 - operand2; |
1840 | break; | |
1841 | ||
c5aa993b | 1842 | case 0x3: /*rsb */ |
c906108c SS |
1843 | result = operand2 - operand1; |
1844 | break; | |
1845 | ||
c5aa993b | 1846 | case 0x4: /*add */ |
c906108c SS |
1847 | result = operand1 + operand2; |
1848 | break; | |
1849 | ||
c5aa993b | 1850 | case 0x5: /*adc */ |
c906108c SS |
1851 | result = operand1 + operand2 + c; |
1852 | break; | |
1853 | ||
c5aa993b | 1854 | case 0x6: /*sbc */ |
c906108c SS |
1855 | result = operand1 - operand2 + c; |
1856 | break; | |
1857 | ||
c5aa993b | 1858 | case 0x7: /*rsc */ |
c906108c SS |
1859 | result = operand2 - operand1 + c; |
1860 | break; | |
1861 | ||
c5aa993b JM |
1862 | case 0x8: |
1863 | case 0x9: | |
1864 | case 0xa: | |
1865 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1866 | result = (unsigned long) nextpc; |
1867 | break; | |
1868 | ||
c5aa993b | 1869 | case 0xc: /*orr */ |
c906108c SS |
1870 | result = operand1 | operand2; |
1871 | break; | |
1872 | ||
c5aa993b | 1873 | case 0xd: /*mov */ |
c906108c SS |
1874 | /* Always step into a function. */ |
1875 | result = operand2; | |
c5aa993b | 1876 | break; |
c906108c | 1877 | |
c5aa993b | 1878 | case 0xe: /*bic */ |
c906108c SS |
1879 | result = operand1 & ~operand2; |
1880 | break; | |
1881 | ||
c5aa993b | 1882 | case 0xf: /*mvn */ |
c906108c SS |
1883 | result = ~operand2; |
1884 | break; | |
1885 | } | |
1886 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1887 | ||
1888 | if (nextpc == pc) | |
1889 | error ("Infinite loop detected"); | |
1890 | break; | |
1891 | } | |
c5aa993b JM |
1892 | |
1893 | case 0x4: | |
1894 | case 0x5: /* data transfer */ | |
1895 | case 0x6: | |
1896 | case 0x7: | |
c906108c SS |
1897 | if (bit (this_instr, 20)) |
1898 | { | |
1899 | /* load */ | |
1900 | if (bits (this_instr, 12, 15) == 15) | |
1901 | { | |
1902 | /* rd == pc */ | |
c5aa993b | 1903 | unsigned long rn; |
c906108c | 1904 | unsigned long base; |
c5aa993b | 1905 | |
c906108c SS |
1906 | if (bit (this_instr, 22)) |
1907 | error ("Illegal update to pc in instruction"); | |
1908 | ||
1909 | /* byte write to PC */ | |
1910 | rn = bits (this_instr, 16, 19); | |
1911 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1912 | if (bit (this_instr, 24)) | |
1913 | { | |
1914 | /* pre-indexed */ | |
1915 | int c = (status & FLAG_C) ? 1 : 0; | |
1916 | unsigned long offset = | |
c5aa993b | 1917 | (bit (this_instr, 25) |
ed9a39eb | 1918 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1919 | : bits (this_instr, 0, 11)); |
c906108c SS |
1920 | |
1921 | if (bit (this_instr, 23)) | |
1922 | base += offset; | |
1923 | else | |
1924 | base -= offset; | |
1925 | } | |
c5aa993b | 1926 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1927 | 4); |
c5aa993b | 1928 | |
c906108c SS |
1929 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1930 | ||
1931 | if (nextpc == pc) | |
1932 | error ("Infinite loop detected"); | |
1933 | } | |
1934 | } | |
1935 | break; | |
c5aa993b JM |
1936 | |
1937 | case 0x8: | |
1938 | case 0x9: /* block transfer */ | |
c906108c SS |
1939 | if (bit (this_instr, 20)) |
1940 | { | |
1941 | /* LDM */ | |
1942 | if (bit (this_instr, 15)) | |
1943 | { | |
1944 | /* loading pc */ | |
1945 | int offset = 0; | |
1946 | ||
1947 | if (bit (this_instr, 23)) | |
1948 | { | |
1949 | /* up */ | |
1950 | unsigned long reglist = bits (this_instr, 0, 14); | |
1951 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1952 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1953 | offset += 4; |
1954 | } | |
1955 | else if (bit (this_instr, 24)) | |
1956 | offset = -4; | |
c5aa993b | 1957 | |
c906108c | 1958 | { |
c5aa993b JM |
1959 | unsigned long rn_val = |
1960 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1961 | nextpc = |
1962 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1963 | + offset), |
c906108c SS |
1964 | 4); |
1965 | } | |
1966 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1967 | if (nextpc == pc) | |
1968 | error ("Infinite loop detected"); | |
1969 | } | |
1970 | } | |
1971 | break; | |
c5aa993b JM |
1972 | |
1973 | case 0xb: /* branch & link */ | |
1974 | case 0xa: /* branch */ | |
c906108c SS |
1975 | { |
1976 | nextpc = BranchDest (pc, this_instr); | |
1977 | ||
1978 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1979 | if (nextpc == pc) | |
1980 | error ("Infinite loop detected"); | |
1981 | break; | |
1982 | } | |
c5aa993b JM |
1983 | |
1984 | case 0xc: | |
1985 | case 0xd: | |
1986 | case 0xe: /* coproc ops */ | |
1987 | case 0xf: /* SWI */ | |
c906108c SS |
1988 | break; |
1989 | ||
1990 | default: | |
97e03143 | 1991 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
1992 | return (pc); |
1993 | } | |
1994 | } | |
1995 | ||
1996 | return nextpc; | |
1997 | } | |
1998 | ||
9512d7fd FN |
1999 | /* single_step() is called just before we want to resume the inferior, |
2000 | if we want to single-step it but there is no hardware or kernel | |
2001 | single-step support. We find the target of the coming instruction | |
2002 | and breakpoint it. | |
2003 | ||
94c30b78 MS |
2004 | single_step() is also called just after the inferior stops. If we |
2005 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2006 | |
34e8f22d RE |
2007 | static void |
2008 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2009 | { |
b8d5e71d | 2010 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2011 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2012 | ||
2013 | if (insert_bpt) | |
2014 | { | |
34e8f22d | 2015 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2016 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2017 | } |
2018 | else | |
80fcf3f0 | 2019 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2020 | } |
9512d7fd | 2021 | |
c906108c SS |
2022 | #include "bfd-in2.h" |
2023 | #include "libcoff.h" | |
2024 | ||
2025 | static int | |
ed9a39eb | 2026 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2027 | { |
2028 | if (arm_pc_is_thumb (memaddr)) | |
2029 | { | |
c5aa993b JM |
2030 | static asymbol *asym; |
2031 | static combined_entry_type ce; | |
2032 | static struct coff_symbol_struct csym; | |
27cddce2 | 2033 | static struct bfd fake_bfd; |
c5aa993b | 2034 | static bfd_target fake_target; |
c906108c SS |
2035 | |
2036 | if (csym.native == NULL) | |
2037 | { | |
da3c6d4a MS |
2038 | /* Create a fake symbol vector containing a Thumb symbol. |
2039 | This is solely so that the code in print_insn_little_arm() | |
2040 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2041 | the presence of a Thumb symbol and switch to decoding | |
2042 | Thumb instructions. */ | |
c5aa993b JM |
2043 | |
2044 | fake_target.flavour = bfd_target_coff_flavour; | |
2045 | fake_bfd.xvec = &fake_target; | |
c906108c | 2046 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2047 | csym.native = &ce; |
2048 | csym.symbol.the_bfd = &fake_bfd; | |
2049 | csym.symbol.name = "fake"; | |
2050 | asym = (asymbol *) & csym; | |
c906108c | 2051 | } |
c5aa993b | 2052 | |
c906108c | 2053 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2054 | info->symbols = &asym; |
c906108c SS |
2055 | } |
2056 | else | |
2057 | info->symbols = NULL; | |
c5aa993b | 2058 | |
d7449b42 | 2059 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2060 | return print_insn_big_arm (memaddr, info); |
2061 | else | |
2062 | return print_insn_little_arm (memaddr, info); | |
2063 | } | |
2064 | ||
66e810cd RE |
2065 | /* The following define instruction sequences that will cause ARM |
2066 | cpu's to take an undefined instruction trap. These are used to | |
2067 | signal a breakpoint to GDB. | |
2068 | ||
2069 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2070 | modes. A different instruction is required for each mode. The ARM | |
2071 | cpu's can also be big or little endian. Thus four different | |
2072 | instructions are needed to support all cases. | |
2073 | ||
2074 | Note: ARMv4 defines several new instructions that will take the | |
2075 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2076 | not in fact add the new instructions. The new undefined | |
2077 | instructions in ARMv4 are all instructions that had no defined | |
2078 | behaviour in earlier chips. There is no guarantee that they will | |
2079 | raise an exception, but may be treated as NOP's. In practice, it | |
2080 | may only safe to rely on instructions matching: | |
2081 | ||
2082 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2083 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2084 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2085 | ||
2086 | Even this may only true if the condition predicate is true. The | |
2087 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2088 | ||
2089 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2090 | and NetBSD all use a software interrupt rather than an undefined | |
2091 | instruction to force a trap. This can be handled by by the | |
2092 | abi-specific code during establishment of the gdbarch vector. */ | |
2093 | ||
2094 | ||
d7b486e7 RE |
2095 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2096 | override these definitions. */ | |
66e810cd RE |
2097 | #ifndef ARM_LE_BREAKPOINT |
2098 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2099 | #endif | |
2100 | #ifndef ARM_BE_BREAKPOINT | |
2101 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2102 | #endif | |
2103 | #ifndef THUMB_LE_BREAKPOINT | |
2104 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2105 | #endif | |
2106 | #ifndef THUMB_BE_BREAKPOINT | |
2107 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2108 | #endif | |
2109 | ||
2110 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2111 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2112 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2113 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2114 | ||
34e8f22d RE |
2115 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2116 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2117 | breakpoint should be used. It returns a pointer to a string of |
2118 | bytes that encode a breakpoint instruction, stores the length of | |
2119 | the string to *lenptr, and adjusts the program counter (if | |
2120 | necessary) to point to the actual memory location where the | |
c906108c SS |
2121 | breakpoint should be inserted. */ |
2122 | ||
34e8f22d RE |
2123 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2124 | breakpoints and storing their handles instread of what was in | |
2125 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2126 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2127 | |
ab89facf | 2128 | static const unsigned char * |
ed9a39eb | 2129 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2130 | { |
66e810cd RE |
2131 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2132 | ||
c906108c SS |
2133 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2134 | { | |
66e810cd RE |
2135 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2136 | *lenptr = tdep->thumb_breakpoint_size; | |
2137 | return tdep->thumb_breakpoint; | |
c906108c SS |
2138 | } |
2139 | else | |
2140 | { | |
66e810cd RE |
2141 | *lenptr = tdep->arm_breakpoint_size; |
2142 | return tdep->arm_breakpoint; | |
c906108c SS |
2143 | } |
2144 | } | |
ed9a39eb JM |
2145 | |
2146 | /* Extract from an array REGBUF containing the (raw) register state a | |
2147 | function return value of type TYPE, and copy that, in virtual | |
2148 | format, into VALBUF. */ | |
2149 | ||
34e8f22d | 2150 | static void |
ed9a39eb | 2151 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2152 | struct regcache *regs, |
2153 | void *dst) | |
ed9a39eb | 2154 | { |
b508a996 RE |
2155 | bfd_byte *valbuf = dst; |
2156 | ||
ed9a39eb | 2157 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2158 | { |
fd50bc42 | 2159 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2160 | { |
2161 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2162 | { |
2163 | /* The value is in register F0 in internal format. We need to | |
2164 | extract the raw value and then convert it to the desired | |
2165 | internal type. */ | |
2166 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; | |
2167 | ||
2168 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2169 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2170 | valbuf); | |
2171 | } | |
08216dd7 RE |
2172 | break; |
2173 | ||
fd50bc42 | 2174 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2175 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2176 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2177 | if (TYPE_LENGTH (type) > 4) | |
2178 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
2179 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2180 | break; |
2181 | ||
2182 | default: | |
2183 | internal_error | |
2184 | (__FILE__, __LINE__, | |
2185 | "arm_extract_return_value: Floating point model not supported"); | |
2186 | break; | |
2187 | } | |
2188 | } | |
b508a996 RE |
2189 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2190 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2191 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2192 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2193 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2194 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2195 | { | |
2196 | /* If the the type is a plain integer, then the access is | |
2197 | straight-forward. Otherwise we have to play around a bit more. */ | |
2198 | int len = TYPE_LENGTH (type); | |
2199 | int regno = ARM_A1_REGNUM; | |
2200 | ULONGEST tmp; | |
2201 | ||
2202 | while (len > 0) | |
2203 | { | |
2204 | /* By using store_unsigned_integer we avoid having to do | |
2205 | anything special for small big-endian values. */ | |
2206 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2207 | store_unsigned_integer (valbuf, | |
2208 | (len > INT_REGISTER_RAW_SIZE | |
2209 | ? INT_REGISTER_RAW_SIZE : len), | |
2210 | tmp); | |
2211 | len -= INT_REGISTER_RAW_SIZE; | |
2212 | valbuf += INT_REGISTER_RAW_SIZE; | |
2213 | } | |
2214 | } | |
ed9a39eb | 2215 | else |
b508a996 RE |
2216 | { |
2217 | /* For a structure or union the behaviour is as if the value had | |
2218 | been stored to word-aligned memory and then loaded into | |
2219 | registers with 32-bit load instruction(s). */ | |
2220 | int len = TYPE_LENGTH (type); | |
2221 | int regno = ARM_A1_REGNUM; | |
2222 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2223 | ||
2224 | while (len > 0) | |
2225 | { | |
2226 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2227 | memcpy (valbuf, tmpbuf, | |
2228 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2229 | len -= INT_REGISTER_RAW_SIZE; | |
2230 | valbuf += INT_REGISTER_RAW_SIZE; | |
2231 | } | |
2232 | } | |
34e8f22d RE |
2233 | } |
2234 | ||
67255d04 RE |
2235 | /* Extract from an array REGBUF containing the (raw) register state |
2236 | the address in which a function should return its structure value. */ | |
2237 | ||
2238 | static CORE_ADDR | |
95f95911 | 2239 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2240 | { |
95f95911 MS |
2241 | ULONGEST ret; |
2242 | ||
2243 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2244 | return ret; | |
67255d04 RE |
2245 | } |
2246 | ||
2247 | /* Will a function return an aggregate type in memory or in a | |
2248 | register? Return 0 if an aggregate type can be returned in a | |
2249 | register, 1 if it must be returned in memory. */ | |
2250 | ||
2251 | static int | |
2252 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2253 | { | |
2254 | int nRc; | |
2255 | register enum type_code code; | |
2256 | ||
2257 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2258 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2259 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2260 | offset of each addressable subfield must be zero. Note that bit | |
2261 | fields are not addressable, and all addressable subfields of | |
2262 | unions always start at offset zero. | |
67255d04 RE |
2263 | |
2264 | This function is based on the behaviour of GCC 2.95.1. | |
2265 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2266 | ||
2267 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2268 | parameters correctly for a function returning the following | |
2269 | structure: struct { float f;}; This should be returned in memory, | |
2270 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2271 | know of any way to detect if a function like the above has been | |
2272 | compiled with the correct calling convention. */ | |
2273 | ||
2274 | /* All aggregate types that won't fit in a register must be returned | |
2275 | in memory. */ | |
b1e29e33 | 2276 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2277 | { |
2278 | return 1; | |
2279 | } | |
2280 | ||
2281 | /* The only aggregate types that can be returned in a register are | |
2282 | structs and unions. Arrays must be returned in memory. */ | |
2283 | code = TYPE_CODE (type); | |
2284 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2285 | { | |
2286 | return 1; | |
2287 | } | |
2288 | ||
2289 | /* Assume all other aggregate types can be returned in a register. | |
2290 | Run a check for structures, unions and arrays. */ | |
2291 | nRc = 0; | |
2292 | ||
2293 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2294 | { | |
2295 | int i; | |
2296 | /* Need to check if this struct/union is "integer" like. For | |
2297 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2298 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2299 | subfield must be zero. Note that bit fields are not | |
2300 | addressable, and unions always start at offset zero. If any | |
2301 | of the subfields is a floating point type, the struct/union | |
2302 | cannot be an integer type. */ | |
67255d04 RE |
2303 | |
2304 | /* For each field in the object, check: | |
2305 | 1) Is it FP? --> yes, nRc = 1; | |
2306 | 2) Is it addressable (bitpos != 0) and | |
2307 | not packed (bitsize == 0)? | |
2308 | --> yes, nRc = 1 | |
2309 | */ | |
2310 | ||
2311 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2312 | { | |
2313 | enum type_code field_type_code; | |
2314 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2315 | ||
2316 | /* Is it a floating point type field? */ | |
2317 | if (field_type_code == TYPE_CODE_FLT) | |
2318 | { | |
2319 | nRc = 1; | |
2320 | break; | |
2321 | } | |
2322 | ||
2323 | /* If bitpos != 0, then we have to care about it. */ | |
2324 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2325 | { | |
2326 | /* Bitfields are not addressable. If the field bitsize is | |
2327 | zero, then the field is not packed. Hence it cannot be | |
2328 | a bitfield or any other packed type. */ | |
2329 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2330 | { | |
2331 | nRc = 1; | |
2332 | break; | |
2333 | } | |
2334 | } | |
2335 | } | |
2336 | } | |
2337 | ||
2338 | return nRc; | |
2339 | } | |
2340 | ||
34e8f22d RE |
2341 | /* Write into appropriate registers a function return value of type |
2342 | TYPE, given in virtual format. */ | |
2343 | ||
2344 | static void | |
b508a996 RE |
2345 | arm_store_return_value (struct type *type, struct regcache *regs, |
2346 | const void *src) | |
34e8f22d | 2347 | { |
b508a996 RE |
2348 | const bfd_byte *valbuf = src; |
2349 | ||
34e8f22d RE |
2350 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2351 | { | |
7bbcf283 | 2352 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2353 | |
fd50bc42 | 2354 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2355 | { |
2356 | case ARM_FLOAT_FPA: | |
2357 | ||
b508a996 RE |
2358 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2359 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2360 | break; |
2361 | ||
fd50bc42 | 2362 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2363 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2364 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2365 | if (TYPE_LENGTH (type) > 4) | |
2366 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
2367 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2368 | break; |
2369 | ||
2370 | default: | |
2371 | internal_error | |
2372 | (__FILE__, __LINE__, | |
2373 | "arm_store_return_value: Floating point model not supported"); | |
2374 | break; | |
2375 | } | |
34e8f22d | 2376 | } |
b508a996 RE |
2377 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2378 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2379 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2380 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2381 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2382 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2383 | { | |
2384 | if (TYPE_LENGTH (type) <= 4) | |
2385 | { | |
2386 | /* Values of one word or less are zero/sign-extended and | |
2387 | returned in r0. */ | |
2388 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2389 | LONGEST val = unpack_long (type, valbuf); | |
2390 | ||
2391 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); | |
2392 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); | |
2393 | } | |
2394 | else | |
2395 | { | |
2396 | /* Integral values greater than one word are stored in consecutive | |
2397 | registers starting with r0. This will always be a multiple of | |
2398 | the regiser size. */ | |
2399 | int len = TYPE_LENGTH (type); | |
2400 | int regno = ARM_A1_REGNUM; | |
2401 | ||
2402 | while (len > 0) | |
2403 | { | |
2404 | regcache_cooked_write (regs, regno++, valbuf); | |
2405 | len -= INT_REGISTER_RAW_SIZE; | |
2406 | valbuf += INT_REGISTER_RAW_SIZE; | |
2407 | } | |
2408 | } | |
2409 | } | |
34e8f22d | 2410 | else |
b508a996 RE |
2411 | { |
2412 | /* For a structure or union the behaviour is as if the value had | |
2413 | been stored to word-aligned memory and then loaded into | |
2414 | registers with 32-bit load instruction(s). */ | |
2415 | int len = TYPE_LENGTH (type); | |
2416 | int regno = ARM_A1_REGNUM; | |
2417 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2418 | ||
2419 | while (len > 0) | |
2420 | { | |
2421 | memcpy (tmpbuf, valbuf, | |
2422 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2423 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2424 | len -= INT_REGISTER_RAW_SIZE; | |
2425 | valbuf += INT_REGISTER_RAW_SIZE; | |
2426 | } | |
2427 | } | |
34e8f22d RE |
2428 | } |
2429 | ||
9df628e0 RE |
2430 | static int |
2431 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2432 | { | |
2433 | CORE_ADDR jb_addr; | |
2434 | char buf[INT_REGISTER_RAW_SIZE]; | |
2435 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2436 | ||
2437 | jb_addr = read_register (ARM_A1_REGNUM); | |
2438 | ||
2439 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2440 | INT_REGISTER_RAW_SIZE)) | |
2441 | return 0; | |
2442 | ||
7c0b4a20 | 2443 | *pc = extract_unsigned_integer (buf, INT_REGISTER_RAW_SIZE); |
9df628e0 RE |
2444 | return 1; |
2445 | } | |
2446 | ||
ed9a39eb | 2447 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2448 | |
2449 | int | |
ed9a39eb | 2450 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2451 | { |
2452 | CORE_ADDR start_addr; | |
2453 | ||
ed9a39eb JM |
2454 | /* Find the starting address of the function containing the PC. If |
2455 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2456 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2457 | &start_addr, NULL)) | |
c906108c SS |
2458 | return 0; |
2459 | ||
2460 | return strncmp (name, "_call_via_r", 11) == 0; | |
2461 | } | |
2462 | ||
ed9a39eb JM |
2463 | /* If PC is in a Thumb call or return stub, return the address of the |
2464 | target PC, which is in a register. The thunk functions are called | |
2465 | _called_via_xx, where x is the register name. The possible names | |
2466 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2467 | |
2468 | CORE_ADDR | |
ed9a39eb | 2469 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2470 | { |
c5aa993b | 2471 | char *name; |
c906108c SS |
2472 | CORE_ADDR start_addr; |
2473 | ||
2474 | /* Find the starting address and name of the function containing the PC. */ | |
2475 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2476 | return 0; | |
2477 | ||
2478 | /* Call thunks always start with "_call_via_". */ | |
2479 | if (strncmp (name, "_call_via_", 10) == 0) | |
2480 | { | |
ed9a39eb JM |
2481 | /* Use the name suffix to determine which register contains the |
2482 | target PC. */ | |
c5aa993b JM |
2483 | static char *table[15] = |
2484 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2485 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2486 | }; | |
c906108c SS |
2487 | int regno; |
2488 | ||
2489 | for (regno = 0; regno <= 14; regno++) | |
2490 | if (strcmp (&name[10], table[regno]) == 0) | |
2491 | return read_register (regno); | |
2492 | } | |
ed9a39eb | 2493 | |
c5aa993b | 2494 | return 0; /* not a stub */ |
c906108c SS |
2495 | } |
2496 | ||
afd7eef0 RE |
2497 | static void |
2498 | set_arm_command (char *args, int from_tty) | |
2499 | { | |
2500 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); | |
2501 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); | |
2502 | } | |
2503 | ||
2504 | static void | |
2505 | show_arm_command (char *args, int from_tty) | |
2506 | { | |
26304000 | 2507 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2508 | } |
2509 | ||
fd50bc42 RE |
2510 | enum arm_float_model |
2511 | arm_get_fp_model (struct gdbarch *gdbarch) | |
2512 | { | |
2513 | if (arm_fp_model == ARM_FLOAT_AUTO) | |
2514 | return gdbarch_tdep (gdbarch)->fp_model; | |
2515 | ||
2516 | return arm_fp_model; | |
2517 | } | |
2518 | ||
2519 | static void | |
2520 | arm_set_fp (struct gdbarch *gdbarch) | |
2521 | { | |
2522 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); | |
2523 | ||
2524 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE | |
2525 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) | |
2526 | { | |
2527 | set_gdbarch_double_format (gdbarch, | |
2528 | &floatformat_ieee_double_littlebyte_bigword); | |
2529 | set_gdbarch_long_double_format | |
2530 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2535 | set_gdbarch_long_double_format (gdbarch, | |
2536 | &floatformat_ieee_double_little); | |
2537 | } | |
2538 | } | |
2539 | ||
2540 | static void | |
2541 | set_fp_model_sfunc (char *args, int from_tty, | |
2542 | struct cmd_list_element *c) | |
2543 | { | |
2544 | enum arm_float_model fp_model; | |
2545 | ||
2546 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2547 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2548 | { | |
2549 | arm_fp_model = fp_model; | |
2550 | break; | |
2551 | } | |
2552 | ||
2553 | if (fp_model == ARM_FLOAT_LAST) | |
2554 | internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", | |
2555 | current_fp_model); | |
2556 | ||
2557 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2558 | arm_set_fp (current_gdbarch); | |
2559 | } | |
2560 | ||
2561 | static void | |
2562 | show_fp_model (char *args, int from_tty, | |
2563 | struct cmd_list_element *c) | |
2564 | { | |
2565 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2566 | ||
2567 | if (arm_fp_model == ARM_FLOAT_AUTO | |
2568 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2569 | printf_filtered (" - the default for the current ABI is \"%s\".\n", | |
2570 | fp_model_strings[tdep->fp_model]); | |
2571 | } | |
2572 | ||
afd7eef0 RE |
2573 | /* If the user changes the register disassembly style used for info |
2574 | register and other commands, we have to also switch the style used | |
2575 | in opcodes for disassembly output. This function is run in the "set | |
2576 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2577 | |
2578 | static void | |
afd7eef0 | 2579 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2580 | struct cmd_list_element *c) |
2581 | { | |
afd7eef0 | 2582 | set_disassembly_style (); |
bc90b915 FN |
2583 | } |
2584 | \f | |
966fbf70 | 2585 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2586 | static const char * |
34e8f22d | 2587 | arm_register_name (int i) |
966fbf70 RE |
2588 | { |
2589 | return arm_register_names[i]; | |
2590 | } | |
2591 | ||
bc90b915 | 2592 | static void |
afd7eef0 | 2593 | set_disassembly_style (void) |
bc90b915 FN |
2594 | { |
2595 | const char *setname, *setdesc, **regnames; | |
2596 | int numregs, j; | |
2597 | ||
afd7eef0 | 2598 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2599 | int current = 0; |
2600 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2601 | while ((disassembly_style != setname) |
2602 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2603 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2604 | current_option = current; | |
2605 | ||
94c30b78 | 2606 | /* Fill our copy. */ |
bc90b915 FN |
2607 | for (j = 0; j < numregs; j++) |
2608 | arm_register_names[j] = (char *) regnames[j]; | |
2609 | ||
94c30b78 | 2610 | /* Adjust case. */ |
34e8f22d | 2611 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2612 | { |
34e8f22d RE |
2613 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2614 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2615 | } |
2616 | else | |
2617 | { | |
34e8f22d RE |
2618 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2619 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2620 | } |
2621 | ||
94c30b78 | 2622 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2623 | set_arm_regname_option (current); |
2624 | } | |
2625 | ||
afd7eef0 RE |
2626 | /* arm_othernames implements the "othernames" command. This is deprecated |
2627 | by the "set arm disassembly" command. */ | |
bc90b915 FN |
2628 | |
2629 | static void | |
2630 | arm_othernames (char *names, int n) | |
2631 | { | |
94c30b78 | 2632 | /* Circle through the various flavors. */ |
afd7eef0 | 2633 | current_option = (current_option + 1) % num_disassembly_options; |
bc90b915 | 2634 | |
afd7eef0 RE |
2635 | disassembly_style = valid_disassembly_styles[current_option]; |
2636 | set_disassembly_style (); | |
bc90b915 FN |
2637 | } |
2638 | ||
082fc60d RE |
2639 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2640 | function. */ | |
2641 | ||
2642 | static int | |
2643 | coff_sym_is_thumb (int val) | |
2644 | { | |
2645 | return (val == C_THUMBEXT || | |
2646 | val == C_THUMBSTAT || | |
2647 | val == C_THUMBEXTFUNC || | |
2648 | val == C_THUMBSTATFUNC || | |
2649 | val == C_THUMBLABEL); | |
2650 | } | |
2651 | ||
2652 | /* arm_coff_make_msymbol_special() | |
2653 | arm_elf_make_msymbol_special() | |
2654 | ||
2655 | These functions test whether the COFF or ELF symbol corresponds to | |
2656 | an address in thumb code, and set a "special" bit in a minimal | |
2657 | symbol to indicate that it does. */ | |
2658 | ||
34e8f22d | 2659 | static void |
082fc60d RE |
2660 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2661 | { | |
2662 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2663 | STT_ARM_TFUNC). */ | |
2664 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2665 | == STT_LOPROC) | |
2666 | MSYMBOL_SET_SPECIAL (msym); | |
2667 | } | |
2668 | ||
34e8f22d | 2669 | static void |
082fc60d RE |
2670 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2671 | { | |
2672 | if (coff_sym_is_thumb (val)) | |
2673 | MSYMBOL_SET_SPECIAL (msym); | |
2674 | } | |
2675 | ||
97e03143 | 2676 | \f |
70f80edf JT |
2677 | static enum gdb_osabi |
2678 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2679 | { |
70f80edf JT |
2680 | unsigned int elfosabi, eflags; |
2681 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2682 | |
70f80edf | 2683 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2684 | |
70f80edf | 2685 | switch (elfosabi) |
97e03143 | 2686 | { |
70f80edf JT |
2687 | case ELFOSABI_NONE: |
2688 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2689 | file are conforming to the base specification for that machine | |
2690 | (there are no OS-specific extensions). In order to determine the | |
2691 | real OS in use we must look for OS notes that have been added. */ | |
2692 | bfd_map_over_sections (abfd, | |
2693 | generic_elf_osabi_sniff_abi_tag_sections, | |
2694 | &osabi); | |
2695 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2696 | { |
70f80edf JT |
2697 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2698 | field for more information. */ | |
2699 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2700 | switch (eflags) | |
97e03143 | 2701 | { |
70f80edf JT |
2702 | case EF_ARM_EABI_VER1: |
2703 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2704 | break; |
2705 | ||
70f80edf JT |
2706 | case EF_ARM_EABI_VER2: |
2707 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2708 | break; |
2709 | ||
70f80edf JT |
2710 | case EF_ARM_EABI_UNKNOWN: |
2711 | /* Assume GNU tools. */ | |
2712 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2713 | break; |
2714 | ||
70f80edf JT |
2715 | default: |
2716 | internal_error (__FILE__, __LINE__, | |
2717 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2718 | "version 0x%x", eflags); | |
97e03143 RE |
2719 | } |
2720 | } | |
70f80edf | 2721 | break; |
97e03143 | 2722 | |
70f80edf JT |
2723 | case ELFOSABI_ARM: |
2724 | /* GNU tools use this value. Check note sections in this case, | |
2725 | as well. */ | |
97e03143 | 2726 | bfd_map_over_sections (abfd, |
70f80edf JT |
2727 | generic_elf_osabi_sniff_abi_tag_sections, |
2728 | &osabi); | |
2729 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2730 | { |
70f80edf JT |
2731 | /* Assume APCS ABI. */ |
2732 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2733 | } |
2734 | break; | |
2735 | ||
97e03143 | 2736 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2737 | osabi = GDB_OSABI_FREEBSD_ELF; |
2738 | break; | |
97e03143 | 2739 | |
70f80edf JT |
2740 | case ELFOSABI_NETBSD: |
2741 | osabi = GDB_OSABI_NETBSD_ELF; | |
2742 | break; | |
97e03143 | 2743 | |
70f80edf JT |
2744 | case ELFOSABI_LINUX: |
2745 | osabi = GDB_OSABI_LINUX; | |
2746 | break; | |
97e03143 RE |
2747 | } |
2748 | ||
70f80edf | 2749 | return osabi; |
97e03143 RE |
2750 | } |
2751 | ||
70f80edf | 2752 | \f |
da3c6d4a MS |
2753 | /* Initialize the current architecture based on INFO. If possible, |
2754 | re-use an architecture from ARCHES, which is a list of | |
2755 | architectures already created during this debugging session. | |
97e03143 | 2756 | |
da3c6d4a MS |
2757 | Called e.g. at program startup, when reading a core file, and when |
2758 | reading a binary file. */ | |
97e03143 | 2759 | |
39bbf761 RE |
2760 | static struct gdbarch * |
2761 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2762 | { | |
97e03143 | 2763 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2764 | struct gdbarch *gdbarch; |
2765 | ||
97e03143 | 2766 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2767 | |
4be87837 | 2768 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2769 | { |
4be87837 | 2770 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2771 | { |
4be87837 DJ |
2772 | case bfd_target_aout_flavour: |
2773 | /* Assume it's an old APCS-style ABI. */ | |
2774 | info.osabi = GDB_OSABI_ARM_APCS; | |
2775 | break; | |
97e03143 | 2776 | |
4be87837 DJ |
2777 | case bfd_target_coff_flavour: |
2778 | /* Assume it's an old APCS-style ABI. */ | |
2779 | /* XXX WinCE? */ | |
2780 | info.osabi = GDB_OSABI_ARM_APCS; | |
2781 | break; | |
97e03143 | 2782 | |
4be87837 DJ |
2783 | default: |
2784 | /* Leave it as "unknown". */ | |
50ceaba5 | 2785 | break; |
97e03143 RE |
2786 | } |
2787 | } | |
2788 | ||
4be87837 DJ |
2789 | /* If there is already a candidate, use it. */ |
2790 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2791 | if (arches != NULL) | |
2792 | return arches->gdbarch; | |
97e03143 RE |
2793 | |
2794 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2795 | gdbarch = gdbarch_alloc (&info, tdep); | |
2796 | ||
fd50bc42 RE |
2797 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
2798 | now, and we now provide a way for the user to force the model. So | |
2799 | default to the most useful variant. */ | |
2800 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
08216dd7 RE |
2801 | |
2802 | /* Breakpoints. */ | |
67255d04 RE |
2803 | switch (info.byte_order) |
2804 | { | |
2805 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2806 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2807 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2808 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2809 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2810 | ||
67255d04 RE |
2811 | break; |
2812 | ||
2813 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2814 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2815 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2816 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2817 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2818 | ||
67255d04 RE |
2819 | break; |
2820 | ||
2821 | default: | |
2822 | internal_error (__FILE__, __LINE__, | |
2823 | "arm_gdbarch_init: bad byte order for float format"); | |
2824 | } | |
2825 | ||
d7b486e7 RE |
2826 | /* On ARM targets char defaults to unsigned. */ |
2827 | set_gdbarch_char_signed (gdbarch, 0); | |
2828 | ||
9df628e0 | 2829 | /* This should be low enough for everything. */ |
97e03143 | 2830 | tdep->lowest_pc = 0x20; |
94c30b78 | 2831 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2832 | |
b1e29e33 AC |
2833 | set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words); |
2834 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); | |
848cfffb | 2835 | |
2dd604e7 | 2836 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2837 | |
148754e5 | 2838 | /* Frame handling. */ |
eb5492fa DJ |
2839 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2840 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2841 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2842 | ||
148754e5 RE |
2843 | set_gdbarch_frameless_function_invocation |
2844 | (gdbarch, arm_frameless_function_invocation); | |
148754e5 | 2845 | set_gdbarch_frame_args_skip (gdbarch, 0); |
eb5492fa DJ |
2846 | |
2847 | frame_base_set_default (gdbarch, &arm_normal_base); | |
148754e5 | 2848 | |
34e8f22d RE |
2849 | /* Address manipulation. */ |
2850 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2851 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2852 | ||
2853 | /* Offset from address of function to start of its code. */ | |
2854 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2855 | ||
2856 | /* Advance PC across function entry code. */ | |
2857 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2858 | ||
2859 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2860 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2861 | |
2862 | /* The stack grows downward. */ | |
2863 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2864 | ||
2865 | /* Breakpoint manipulation. */ | |
2866 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2867 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2868 | ||
2869 | /* Information about registers, etc. */ | |
2870 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2871 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2872 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2873 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2874 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
b8b527c5 AC |
2875 | set_gdbarch_deprecated_register_bytes (gdbarch, |
2876 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2877 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2878 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
34e8f22d | 2879 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
9c04cab7 AC |
2880 | set_gdbarch_deprecated_register_raw_size (gdbarch, arm_register_raw_size); |
2881 | set_gdbarch_deprecated_register_virtual_size (gdbarch, arm_register_virtual_size); | |
a0ed5532 AC |
2882 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); |
2883 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
9c04cab7 | 2884 | set_gdbarch_deprecated_register_virtual_type (gdbarch, arm_register_type); |
34e8f22d | 2885 | |
26216b98 AC |
2886 | /* Internal <-> external register number maps. */ |
2887 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2888 | ||
34e8f22d | 2889 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2890 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2891 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2892 | ||
2893 | /* Returning results. */ | |
b508a996 RE |
2894 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2895 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
67255d04 | 2896 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2897 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2898 | arm_extract_struct_value_address); |
34e8f22d RE |
2899 | |
2900 | /* Single stepping. */ | |
2901 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2902 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2903 | ||
03d48a7d RE |
2904 | /* Disassembly. */ |
2905 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2906 | ||
34e8f22d RE |
2907 | /* Minsymbol frobbing. */ |
2908 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2909 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2910 | arm_coff_make_msymbol_special); | |
2911 | ||
97e03143 | 2912 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2913 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2914 | |
eb5492fa DJ |
2915 | /* Add some default predicates. */ |
2916 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); | |
2917 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); | |
2918 | ||
97e03143 RE |
2919 | /* Now we have tuned the configuration, set a few final things, |
2920 | based on what the OS ABI has told us. */ | |
2921 | ||
9df628e0 RE |
2922 | if (tdep->jb_pc >= 0) |
2923 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2924 | ||
08216dd7 RE |
2925 | /* Floating point sizes and format. */ |
2926 | switch (info.byte_order) | |
2927 | { | |
2928 | case BFD_ENDIAN_BIG: | |
2929 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2930 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2931 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2932 | ||
2933 | break; | |
2934 | ||
2935 | case BFD_ENDIAN_LITTLE: | |
2936 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
fd50bc42 | 2937 | arm_set_fp (gdbarch); |
08216dd7 RE |
2938 | break; |
2939 | ||
2940 | default: | |
2941 | internal_error (__FILE__, __LINE__, | |
2942 | "arm_gdbarch_init: bad byte order for float format"); | |
2943 | } | |
2944 | ||
39bbf761 RE |
2945 | return gdbarch; |
2946 | } | |
2947 | ||
97e03143 RE |
2948 | static void |
2949 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2950 | { | |
2951 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2952 | ||
2953 | if (tdep == NULL) | |
2954 | return; | |
2955 | ||
97e03143 RE |
2956 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
2957 | (unsigned long) tdep->lowest_pc); | |
2958 | } | |
2959 | ||
2960 | static void | |
2961 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2962 | struct gdbarch *gdbarch) | |
2963 | { | |
2964 | /* Place-holder. */ | |
2965 | } | |
2966 | ||
2967 | static void | |
2968 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2969 | struct gdbarch *gdbarch) | |
2970 | { | |
2971 | /* Place-holder. */ | |
2972 | } | |
2973 | ||
2974 | static void | |
2975 | arm_init_abi_apcs (struct gdbarch_info info, | |
2976 | struct gdbarch *gdbarch) | |
2977 | { | |
2978 | /* Place-holder. */ | |
2979 | } | |
2980 | ||
a78f21af AC |
2981 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2982 | ||
c906108c | 2983 | void |
ed9a39eb | 2984 | _initialize_arm_tdep (void) |
c906108c | 2985 | { |
bc90b915 FN |
2986 | struct ui_file *stb; |
2987 | long length; | |
26304000 | 2988 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2989 | const char *setname; |
2990 | const char *setdesc; | |
2991 | const char **regnames; | |
bc90b915 FN |
2992 | int numregs, i, j; |
2993 | static char *helptext; | |
085dd6e6 | 2994 | |
42cf1509 | 2995 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2996 | |
70f80edf JT |
2997 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2998 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2999 | bfd_target_elf_flavour, | |
3000 | arm_elf_osabi_sniffer); | |
3001 | ||
97e03143 | 3002 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 3003 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 3004 | arm_init_abi_eabi_v1); |
05816f70 | 3005 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 3006 | arm_init_abi_eabi_v2); |
05816f70 | 3007 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 3008 | arm_init_abi_apcs); |
39bbf761 | 3009 | |
94c30b78 | 3010 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3011 | num_disassembly_options = get_arm_regname_num_options (); |
3012 | ||
3013 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3014 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
3015 | "Various ARM-specific commands.", | |
3016 | &setarmcmdlist, "set arm ", 0, &setlist); | |
3017 | ||
3018 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
3019 | "Various ARM-specific commands.", | |
3020 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 3021 | |
94c30b78 | 3022 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3023 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3024 | |
94c30b78 | 3025 | /* Begin creating the help text. */ |
bc90b915 | 3026 | stb = mem_fileopen (); |
afd7eef0 RE |
3027 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
3028 | "The valid values are:\n"); | |
ed9a39eb | 3029 | |
94c30b78 | 3030 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
afd7eef0 RE |
3031 | valid_disassembly_styles |
3032 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3033 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3034 | { |
3035 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3036 | valid_disassembly_styles[i] = setname; |
bc90b915 FN |
3037 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3038 | setdesc); | |
94c30b78 | 3039 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3040 | if (!strcmp (setname, "std")) |
3041 | { | |
afd7eef0 | 3042 | disassembly_style = setname; |
bc90b915 FN |
3043 | current_option = i; |
3044 | for (j = 0; j < numregs; j++) | |
3045 | arm_register_names[j] = (char *) regnames[j]; | |
3046 | set_arm_regname_option (i); | |
3047 | } | |
3048 | } | |
94c30b78 | 3049 | /* Mark the end of valid options. */ |
afd7eef0 | 3050 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3051 | |
94c30b78 | 3052 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3053 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3054 | helptext = ui_file_xstrdup (stb, &length); | |
3055 | ui_file_delete (stb); | |
ed9a39eb | 3056 | |
afd7eef0 | 3057 | /* Add the deprecated disassembly-flavor command. */ |
26304000 | 3058 | new_set = add_set_enum_cmd ("disassembly-flavor", no_class, |
afd7eef0 RE |
3059 | valid_disassembly_styles, |
3060 | &disassembly_style, | |
bc90b915 | 3061 | helptext, |
ed9a39eb | 3062 | &setlist); |
26304000 RE |
3063 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
3064 | deprecate_cmd (new_set, "set arm disassembly"); | |
3065 | deprecate_cmd (add_show_from_set (new_set, &showlist), | |
afd7eef0 RE |
3066 | "show arm disassembly"); |
3067 | ||
3068 | /* And now add the new interface. */ | |
30757f90 | 3069 | new_set = add_set_enum_cmd ("disassembler", no_class, |
26304000 RE |
3070 | valid_disassembly_styles, &disassembly_style, |
3071 | helptext, &setarmcmdlist); | |
3072 | ||
fd50bc42 | 3073 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
26304000 RE |
3074 | add_show_from_set (new_set, &showarmcmdlist); |
3075 | ||
3076 | add_setshow_cmd_full ("apcs32", no_class, | |
3077 | var_boolean, (char *) &arm_apcs_32, | |
3078 | "Set usage of ARM 32-bit mode.", | |
3079 | "Show usage of ARM 32-bit mode.", | |
3080 | NULL, NULL, | |
3081 | &setlist, &showlist, &new_set, &new_show); | |
3082 | deprecate_cmd (new_set, "set arm apcs32"); | |
3083 | deprecate_cmd (new_show, "show arm apcs32"); | |
3084 | ||
3085 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3086 | "Set usage of ARM 32-bit mode. " | |
3087 | "When off, a 26-bit PC will be used.", | |
3088 | "Show usage of ARM 32-bit mode. " | |
3089 | "When off, a 26-bit PC will be used.", | |
3090 | NULL, NULL, | |
3091 | &setarmcmdlist, &showarmcmdlist); | |
c906108c | 3092 | |
fd50bc42 RE |
3093 | /* Add a command to allow the user to force the FPU model. */ |
3094 | new_set = add_set_enum_cmd | |
3095 | ("fpu", no_class, fp_model_strings, ¤t_fp_model, | |
3096 | "Set the floating point type.\n" | |
3097 | "auto - Determine the FP typefrom the OS-ABI.\n" | |
3098 | "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" | |
3099 | "fpa - FPA co-processor (GCC compiled).\n" | |
3100 | "softvfp - Software FP with pure-endian doubles.\n" | |
3101 | "vfp - VFP co-processor.", | |
3102 | &setarmcmdlist); | |
3103 | set_cmd_sfunc (new_set, set_fp_model_sfunc); | |
3104 | set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model); | |
3105 | ||
94c30b78 | 3106 | /* Add the deprecated "othernames" command. */ |
afd7eef0 RE |
3107 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
3108 | "Switch to the next set of register names."), | |
3109 | "set arm disassembly"); | |
c3b4394c | 3110 | |
6529d2dd | 3111 | /* Debugging flag. */ |
26304000 RE |
3112 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3113 | "Set ARM debugging. " | |
3114 | "When on, arm-specific debugging is enabled.", | |
3115 | "Show ARM debugging. " | |
3116 | "When on, arm-specific debugging is enabled.", | |
3117 | NULL, NULL, | |
3118 | &setdebuglist, &showdebuglist); | |
c906108c | 3119 | } |