Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
756fe439 | 3 | 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
34e8f22d RE |
39 | |
40 | #include "arm-tdep.h" | |
26216b98 | 41 | #include "gdb/sim-arm.h" |
34e8f22d | 42 | |
082fc60d RE |
43 | #include "elf-bfd.h" |
44 | #include "coff/internal.h" | |
97e03143 | 45 | #include "elf/arm.h" |
c906108c | 46 | |
26216b98 AC |
47 | #include "gdb_assert.h" |
48 | ||
6529d2dd AC |
49 | static int arm_debug; |
50 | ||
2a451106 KB |
51 | /* Each OS has a different mechanism for accessing the various |
52 | registers stored in the sigcontext structure. | |
53 | ||
54 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
55 | function pointer) which may be used to determine the addresses | |
56 | of the various saved registers in the sigcontext structure. | |
57 | ||
58 | For the ARM target, there are three parameters to this function. | |
59 | The first is the pc value of the frame under consideration, the | |
60 | second the stack pointer of this frame, and the last is the | |
61 | register number to fetch. | |
62 | ||
63 | If the tm.h file does not define this macro, then it's assumed that | |
64 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
65 | be 0. | |
66 | ||
67 | When it comes time to multi-arching this code, see the identically | |
68 | named machinery in ia64-tdep.c for an example of how it could be | |
69 | done. It should not be necessary to modify the code below where | |
70 | this macro is used. */ | |
71 | ||
3bb04bdd AC |
72 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
73 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
74 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
75 | #endif | |
76 | #else | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
78 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
79 | #endif |
80 | ||
082fc60d RE |
81 | /* Macros for setting and testing a bit in a minimal symbol that marks |
82 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 83 | is used for this purpose. |
082fc60d RE |
84 | |
85 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 86 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
87 | |
88 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
89 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
90 | | 0x80000000) | |
91 | ||
92 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
93 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
94 | ||
afd7eef0 RE |
95 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
96 | static struct cmd_list_element *setarmcmdlist = NULL; | |
97 | static struct cmd_list_element *showarmcmdlist = NULL; | |
98 | ||
fd50bc42 RE |
99 | /* The type of floating-point to use. Keep this in sync with enum |
100 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
101 | static const char *fp_model_strings[] = | |
102 | { | |
103 | "auto", | |
104 | "softfpa", | |
105 | "fpa", | |
106 | "softvfp", | |
107 | "vfp" | |
108 | }; | |
109 | ||
110 | /* A variable that can be configured by the user. */ | |
111 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
112 | static const char *current_fp_model = "auto"; | |
113 | ||
94c30b78 | 114 | /* Number of different reg name sets (options). */ |
afd7eef0 | 115 | static int num_disassembly_options; |
bc90b915 FN |
116 | |
117 | /* We have more registers than the disassembler as gdb can print the value | |
118 | of special registers as well. | |
119 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 120 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 121 | |
94c30b78 | 122 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 123 | static char * arm_register_name_strings[] = |
da59e081 JM |
124 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
125 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
126 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
127 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
128 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
129 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 130 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 131 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 132 | |
afd7eef0 RE |
133 | /* Valid register name styles. */ |
134 | static const char **valid_disassembly_styles; | |
ed9a39eb | 135 | |
afd7eef0 RE |
136 | /* Disassembly style to use. Default to "std" register names. */ |
137 | static const char *disassembly_style; | |
94c30b78 | 138 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 139 | static int current_option; |
96baa820 | 140 | |
ed9a39eb | 141 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
142 | style. */ |
143 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 144 | struct cmd_list_element *); |
afd7eef0 | 145 | static void set_disassembly_style (void); |
ed9a39eb | 146 | |
b508a996 RE |
147 | static void convert_from_extended (const struct floatformat *, const void *, |
148 | void *); | |
149 | static void convert_to_extended (const struct floatformat *, void *, | |
150 | const void *); | |
ed9a39eb | 151 | |
9b8d791a | 152 | struct arm_prologue_cache |
c3b4394c | 153 | { |
eb5492fa DJ |
154 | /* The stack pointer at the time this frame was created; i.e. the |
155 | caller's stack pointer when this function was called. It is used | |
156 | to identify this frame. */ | |
157 | CORE_ADDR prev_sp; | |
158 | ||
159 | /* The frame base for this frame is just prev_sp + frame offset - | |
160 | frame size. FRAMESIZE is the size of this stack frame, and | |
161 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
162 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
163 | ||
c3b4394c RE |
164 | int framesize; |
165 | int frameoffset; | |
eb5492fa DJ |
166 | |
167 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 168 | int framereg; |
eb5492fa DJ |
169 | |
170 | /* Saved register offsets. */ | |
171 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 172 | }; |
ed9a39eb | 173 | |
bc90b915 FN |
174 | /* Addresses for calling Thumb functions have the bit 0 set. |
175 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
176 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
177 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
178 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
179 | ||
94c30b78 | 180 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
181 | |
182 | int arm_apcs_32 = 1; | |
183 | ||
ed9a39eb JM |
184 | /* Flag set by arm_fix_call_dummy that tells whether the target |
185 | function is a Thumb function. This flag is checked by | |
186 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
187 | its use in valops.c) to pass the function address as an additional | |
188 | parameter. */ | |
c906108c SS |
189 | |
190 | static int target_is_thumb; | |
191 | ||
ed9a39eb JM |
192 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
193 | function is a Thumb function. This flag is checked by | |
e4a2df64 | 194 | arm_pc_is_thumb. */ |
c906108c SS |
195 | |
196 | static int caller_is_thumb; | |
197 | ||
ed9a39eb JM |
198 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
199 | function. */ | |
c906108c | 200 | |
34e8f22d | 201 | int |
2a451106 | 202 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 203 | { |
c5aa993b | 204 | struct minimal_symbol *sym; |
c906108c | 205 | |
ed9a39eb | 206 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
207 | if (IS_THUMB_ADDR (memaddr)) |
208 | return 1; | |
209 | ||
ed9a39eb | 210 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
211 | sym = lookup_minimal_symbol_by_pc (memaddr); |
212 | if (sym) | |
213 | { | |
c5aa993b | 214 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
215 | } |
216 | else | |
ed9a39eb JM |
217 | { |
218 | return 0; | |
219 | } | |
c906108c SS |
220 | } |
221 | ||
ed9a39eb JM |
222 | /* Determine if the program counter specified in MEMADDR is in a call |
223 | dummy being called from a Thumb function. */ | |
c906108c | 224 | |
34e8f22d | 225 | int |
2a451106 | 226 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 227 | { |
c5aa993b | 228 | CORE_ADDR sp = read_sp (); |
c906108c | 229 | |
dfcd3bfb JM |
230 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
231 | is the best we can do. We are trying to determine if the pc is on | |
232 | the stack, which (hopefully) will only happen in a call dummy. | |
233 | We hope the current stack pointer is not so far alway from the dummy | |
234 | frame location (true if we have not pushed large data structures or | |
235 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 236 | code regions as part of the stack (true for most practical purposes). */ |
30a4a8e0 | 237 | if (deprecated_pc_in_call_dummy (memaddr)) |
c906108c SS |
238 | return caller_is_thumb; |
239 | else | |
240 | return 0; | |
241 | } | |
242 | ||
181c1381 | 243 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 244 | static CORE_ADDR |
ed9a39eb | 245 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 246 | { |
a3a2ee65 JT |
247 | if (arm_apcs_32) |
248 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 249 | else |
a3a2ee65 | 250 | return (val & 0x03fffffc); |
c906108c SS |
251 | } |
252 | ||
181c1381 RE |
253 | /* When reading symbols, we need to zap the low bit of the address, |
254 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 255 | static CORE_ADDR |
181c1381 RE |
256 | arm_smash_text_address (CORE_ADDR val) |
257 | { | |
258 | return val & ~1; | |
259 | } | |
260 | ||
34e8f22d RE |
261 | /* Immediately after a function call, return the saved pc. Can't |
262 | always go through the frames for this because on some machines the | |
263 | new frame is not set up until the new function executes some | |
264 | instructions. */ | |
265 | ||
266 | static CORE_ADDR | |
ed9a39eb | 267 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 268 | { |
34e8f22d | 269 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
270 | } |
271 | ||
0defa245 RE |
272 | /* Determine whether the function invocation represented by FI has a |
273 | frame on the stack associated with it. If it does return zero, | |
274 | otherwise return 1. */ | |
275 | ||
148754e5 | 276 | static int |
ed9a39eb | 277 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 278 | { |
392a587b | 279 | CORE_ADDR func_start, after_prologue; |
96baa820 | 280 | int frameless; |
ed9a39eb | 281 | |
0defa245 RE |
282 | /* Sometimes we have functions that do a little setup (like saving the |
283 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
284 | The symbol table will report this as a prologue. However, it is | |
285 | important not to try to parse these partial frames as frames, or we | |
286 | will get really confused. | |
287 | ||
288 | So I will demand 3 instructions between the start & end of the | |
289 | prologue before I call it a real prologue, i.e. at least | |
290 | mov ip, sp, | |
291 | stmdb sp!, {} | |
292 | sub sp, ip, #4. */ | |
293 | ||
782263ab | 294 | func_start = (get_frame_func (fi) + DEPRECATED_FUNCTION_START_OFFSET); |
7be570e7 | 295 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 296 | |
96baa820 | 297 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 298 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 299 | be func_start + 8. */ |
ed9a39eb | 300 | |
96baa820 | 301 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
302 | return frameless; |
303 | } | |
304 | ||
c906108c | 305 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
306 | push {r7, lr} |
307 | add sp, sp, #-28 | |
308 | add r7, sp, #12 | |
c906108c | 309 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
310 | mov r7, sp |
311 | ||
312 | or like this: | |
313 | push {r7, lr} | |
314 | mov r7, sp | |
315 | sub sp, #12 | |
316 | ||
317 | or, on tpcs, like this: | |
318 | sub sp,#16 | |
319 | push {r7, lr} | |
320 | (many instructions) | |
321 | mov r7, sp | |
322 | sub sp, #12 | |
323 | ||
324 | There is always one instruction of three classes: | |
325 | 1 - push | |
326 | 2 - setting of r7 | |
327 | 3 - adjusting of sp | |
328 | ||
329 | When we have found at least one of each class we are done with the prolog. | |
330 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 331 | */ |
c906108c SS |
332 | |
333 | static CORE_ADDR | |
c7885828 | 334 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
335 | { |
336 | CORE_ADDR current_pc; | |
da3c6d4a MS |
337 | /* findmask: |
338 | bit 0 - push { rlist } | |
339 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
340 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
341 | */ | |
342 | int findmask = 0; | |
343 | ||
94c30b78 MS |
344 | for (current_pc = pc; |
345 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 346 | current_pc += 2) |
c906108c SS |
347 | { |
348 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
349 | ||
94c30b78 | 350 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 351 | { |
94c30b78 | 352 | findmask |= 1; /* push found */ |
da59e081 | 353 | } |
da3c6d4a MS |
354 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
355 | sub sp, #simm */ | |
da59e081 | 356 | { |
94c30b78 | 357 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
358 | continue; |
359 | else | |
94c30b78 | 360 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
361 | } |
362 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
363 | { | |
94c30b78 | 364 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
365 | } |
366 | else if (insn == 0x466f) /* mov r7, sp */ | |
367 | { | |
94c30b78 | 368 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 369 | } |
3d74b771 FF |
370 | else if (findmask == (4+2+1)) |
371 | { | |
da3c6d4a MS |
372 | /* We have found one of each type of prologue instruction */ |
373 | break; | |
3d74b771 | 374 | } |
da59e081 | 375 | else |
94c30b78 | 376 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 377 | instruction from outside the prolog scheduled here for |
94c30b78 | 378 | optimization. */ |
da3c6d4a | 379 | continue; |
c906108c SS |
380 | } |
381 | ||
382 | return current_pc; | |
383 | } | |
384 | ||
da3c6d4a MS |
385 | /* Advance the PC across any function entry prologue instructions to |
386 | reach some "real" code. | |
34e8f22d RE |
387 | |
388 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 389 | prologue: |
c906108c | 390 | |
c5aa993b JM |
391 | mov ip, sp |
392 | [stmfd sp!, {a1,a2,a3,a4}] | |
393 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
394 | [stfe f7, [sp, #-12]!] |
395 | [stfe f6, [sp, #-12]!] | |
396 | [stfe f5, [sp, #-12]!] | |
397 | [stfe f4, [sp, #-12]!] | |
398 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 399 | |
34e8f22d | 400 | static CORE_ADDR |
ed9a39eb | 401 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
402 | { |
403 | unsigned long inst; | |
404 | CORE_ADDR skip_pc; | |
b8d5e71d | 405 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 406 | char *func_name; |
c906108c SS |
407 | struct symtab_and_line sal; |
408 | ||
848cfffb | 409 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 410 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
411 | return pc; |
412 | ||
96baa820 | 413 | /* See what the symbol table says. */ |
ed9a39eb | 414 | |
50f6fb4b | 415 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 416 | { |
50f6fb4b CV |
417 | struct symbol *sym; |
418 | ||
419 | /* Found a function. */ | |
176620f1 | 420 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
421 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
422 | { | |
94c30b78 | 423 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
424 | sal = find_pc_line (func_addr, 0); |
425 | if ((sal.line != 0) && (sal.end < func_end)) | |
426 | return sal.end; | |
427 | } | |
c906108c SS |
428 | } |
429 | ||
430 | /* Check if this is Thumb code. */ | |
431 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 432 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
433 | |
434 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 435 | by disassembling the instructions. */ |
c906108c | 436 | |
b8d5e71d MS |
437 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
438 | if (func_end == 0 || func_end > pc + 64) | |
439 | func_end = pc + 64; | |
c906108c | 440 | |
b8d5e71d | 441 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 442 | { |
f43845b3 | 443 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 444 | |
b8d5e71d MS |
445 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
446 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
447 | continue; | |
c906108c | 448 | |
28cd8767 JG |
449 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
450 | continue; | |
451 | ||
452 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
453 | continue; | |
454 | ||
b8d5e71d MS |
455 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
456 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
457 | continue; | |
c906108c | 458 | |
b8d5e71d MS |
459 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
460 | continue; | |
c906108c | 461 | |
b8d5e71d MS |
462 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
463 | continue; | |
11d3b27d | 464 | |
b8d5e71d MS |
465 | /* Any insns after this point may float into the code, if it makes |
466 | for better instruction scheduling, so we skip them only if we | |
467 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 468 | |
b8d5e71d MS |
469 | /* We may have either one sfmfd instruction here, or several stfe |
470 | insns, depending on the version of floating point code we | |
471 | support. */ | |
472 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
473 | continue; | |
474 | ||
475 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
476 | continue; | |
477 | ||
478 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
479 | continue; | |
480 | ||
481 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
482 | continue; | |
483 | ||
484 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
485 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
486 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
487 | continue; | |
488 | ||
489 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
490 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
491 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
492 | continue; | |
493 | ||
494 | /* Un-recognized instruction; stop scanning. */ | |
495 | break; | |
f43845b3 | 496 | } |
c906108c | 497 | |
b8d5e71d | 498 | return skip_pc; /* End of prologue */ |
c906108c | 499 | } |
94c30b78 | 500 | |
c5aa993b | 501 | /* *INDENT-OFF* */ |
c906108c SS |
502 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
503 | This function decodes a Thumb function prologue to determine: | |
504 | 1) the size of the stack frame | |
505 | 2) which registers are saved on it | |
506 | 3) the offsets of saved regs | |
507 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 508 | |
da59e081 JM |
509 | A typical Thumb function prologue would create this stack frame |
510 | (offsets relative to FP) | |
c906108c SS |
511 | old SP -> 24 stack parameters |
512 | 20 LR | |
513 | 16 R7 | |
514 | R7 -> 0 local variables (16 bytes) | |
515 | SP -> -12 additional stack space (12 bytes) | |
516 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
517 | 12 bytes. The frame register is R7. |
518 | ||
da3c6d4a MS |
519 | The comments for thumb_skip_prolog() describe the algorithm we use |
520 | to detect the end of the prolog. */ | |
c5aa993b JM |
521 | /* *INDENT-ON* */ |
522 | ||
c906108c | 523 | static void |
eb5492fa | 524 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
525 | { |
526 | CORE_ADDR prologue_start; | |
527 | CORE_ADDR prologue_end; | |
528 | CORE_ADDR current_pc; | |
94c30b78 | 529 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
530 | int saved_reg[16]; |
531 | /* findmask: | |
532 | bit 0 - push { rlist } | |
533 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
534 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
535 | */ | |
536 | int findmask = 0; | |
c5aa993b | 537 | int i; |
c906108c | 538 | |
eb5492fa | 539 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
540 | { |
541 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
542 | ||
94c30b78 | 543 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 544 | prologue_end = prev_pc; |
c906108c | 545 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 546 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
547 | } |
548 | else | |
da3c6d4a MS |
549 | /* We're in the boondocks: allow for |
550 | 16 pushes, an add, and "mv fp,sp". */ | |
551 | prologue_end = prologue_start + 40; | |
c906108c | 552 | |
eb5492fa | 553 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
554 | |
555 | /* Initialize the saved register map. When register H is copied to | |
556 | register L, we will put H in saved_reg[L]. */ | |
557 | for (i = 0; i < 16; i++) | |
558 | saved_reg[i] = i; | |
559 | ||
560 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
561 | frame pointer, adjust the stack pointer, and save registers. |
562 | Do this until all basic prolog instructions are found. */ | |
c906108c | 563 | |
9b8d791a | 564 | cache->framesize = 0; |
da59e081 JM |
565 | for (current_pc = prologue_start; |
566 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
567 | current_pc += 2) | |
c906108c SS |
568 | { |
569 | unsigned short insn; | |
570 | int regno; | |
571 | int offset; | |
572 | ||
573 | insn = read_memory_unsigned_integer (current_pc, 2); | |
574 | ||
c5aa993b | 575 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 576 | { |
da59e081 | 577 | int mask; |
94c30b78 | 578 | findmask |= 1; /* push found */ |
c906108c SS |
579 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
580 | whether to save LR (R14). */ | |
da59e081 | 581 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 582 | |
b8d5e71d | 583 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 584 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 585 | if (mask & (1 << regno)) |
c5aa993b | 586 | { |
9b8d791a | 587 | cache->framesize += 4; |
eb5492fa | 588 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
589 | /* Reset saved register map. */ |
590 | saved_reg[regno] = regno; | |
c906108c SS |
591 | } |
592 | } | |
da3c6d4a MS |
593 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
594 | sub sp, #simm */ | |
c906108c | 595 | { |
b8d5e71d | 596 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
597 | continue; |
598 | else | |
94c30b78 | 599 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 600 | |
94c30b78 MS |
601 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
602 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 603 | { |
9b8d791a | 604 | cache->frameoffset += offset; |
da59e081 JM |
605 | offset = -offset; |
606 | } | |
9b8d791a | 607 | cache->framesize -= offset; |
c906108c SS |
608 | } |
609 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
610 | { | |
94c30b78 | 611 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 612 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 613 | /* get scaled offset */ |
9b8d791a | 614 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 615 | } |
da59e081 | 616 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 617 | { |
94c30b78 | 618 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
619 | cache->framereg = THUMB_FP_REGNUM; |
620 | cache->frameoffset = 0; | |
34e8f22d | 621 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
622 | } |
623 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
624 | { | |
da3c6d4a | 625 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 626 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 627 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
628 | } |
629 | else | |
da3c6d4a MS |
630 | /* Something in the prolog that we don't care about or some |
631 | instruction from outside the prolog scheduled here for | |
632 | optimization. */ | |
633 | continue; | |
c906108c SS |
634 | } |
635 | } | |
636 | ||
ed9a39eb | 637 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
638 | 1) the size of the stack frame |
639 | 2) which registers are saved on it | |
640 | 3) the offsets of saved regs | |
641 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
642 | This information is stored in the "extra" fields of the frame_info. |
643 | ||
96baa820 JM |
644 | There are two basic forms for the ARM prologue. The fixed argument |
645 | function call will look like: | |
ed9a39eb JM |
646 | |
647 | mov ip, sp | |
648 | stmfd sp!, {fp, ip, lr, pc} | |
649 | sub fp, ip, #4 | |
650 | [sub sp, sp, #4] | |
96baa820 | 651 | |
c906108c | 652 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
653 | IP -> 4 (caller's stack) |
654 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
655 | -4 LR (return address in caller) | |
656 | -8 IP (copy of caller's SP) | |
657 | -12 FP (caller's FP) | |
658 | SP -> -28 Local variables | |
659 | ||
c906108c | 660 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
661 | 28 bytes. The stmfd call can also save any of the vN registers it |
662 | plans to use, which increases the frame size accordingly. | |
663 | ||
664 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
665 | because the ARM Store instructions always store PC + 8 when you read | |
666 | the PC register. | |
ed9a39eb | 667 | |
96baa820 JM |
668 | A variable argument function call will look like: |
669 | ||
ed9a39eb JM |
670 | mov ip, sp |
671 | stmfd sp!, {a1, a2, a3, a4} | |
672 | stmfd sp!, {fp, ip, lr, pc} | |
673 | sub fp, ip, #20 | |
674 | ||
96baa820 | 675 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
676 | IP -> 20 (caller's stack) |
677 | 16 A4 | |
678 | 12 A3 | |
679 | 8 A2 | |
680 | 4 A1 | |
681 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
682 | -4 LR (return address in caller) | |
683 | -8 IP (copy of caller's SP) | |
684 | -12 FP (caller's FP) | |
685 | SP -> -28 Local variables | |
96baa820 JM |
686 | |
687 | The frame size would thus be 48 bytes, and the frame offset would be | |
688 | 28 bytes. | |
689 | ||
690 | There is another potential complication, which is that the optimizer | |
691 | will try to separate the store of fp in the "stmfd" instruction from | |
692 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
693 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
694 | ||
695 | Also, note, the original version of the ARM toolchain claimed that there | |
696 | should be an | |
697 | ||
698 | instruction at the end of the prologue. I have never seen GCC produce | |
699 | this, and the ARM docs don't mention it. We still test for it below in | |
700 | case it happens... | |
ed9a39eb JM |
701 | |
702 | */ | |
c906108c SS |
703 | |
704 | static void | |
eb5492fa | 705 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 706 | { |
28cd8767 | 707 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 708 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 709 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 710 | |
c906108c | 711 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
712 | cache->framereg = ARM_SP_REGNUM; |
713 | cache->framesize = 0; | |
714 | cache->frameoffset = 0; | |
c906108c SS |
715 | |
716 | /* Check for Thumb prologue. */ | |
eb5492fa | 717 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 718 | { |
eb5492fa | 719 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
720 | return; |
721 | } | |
722 | ||
723 | /* Find the function prologue. If we can't find the function in | |
724 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 725 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 726 | { |
2a451106 KB |
727 | /* One way to find the end of the prologue (which works well |
728 | for unoptimized code) is to do the following: | |
729 | ||
730 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
731 | ||
732 | if (sal.line == 0) | |
eb5492fa | 733 | prologue_end = prev_pc; |
2a451106 KB |
734 | else if (sal.end < prologue_end) |
735 | prologue_end = sal.end; | |
736 | ||
737 | This mechanism is very accurate so long as the optimizer | |
738 | doesn't move any instructions from the function body into the | |
739 | prologue. If this happens, sal.end will be the last | |
740 | instruction in the first hunk of prologue code just before | |
741 | the first instruction that the scheduler has moved from | |
742 | the body to the prologue. | |
743 | ||
744 | In order to make sure that we scan all of the prologue | |
745 | instructions, we use a slightly less accurate mechanism which | |
746 | may scan more than necessary. To help compensate for this | |
747 | lack of accuracy, the prologue scanning loop below contains | |
748 | several clauses which'll cause the loop to terminate early if | |
749 | an implausible prologue instruction is encountered. | |
750 | ||
751 | The expression | |
752 | ||
753 | prologue_start + 64 | |
754 | ||
755 | is a suitable endpoint since it accounts for the largest | |
756 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 757 | the scheduler. */ |
2a451106 KB |
758 | |
759 | if (prologue_end > prologue_start + 64) | |
760 | { | |
94c30b78 | 761 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 762 | } |
c906108c SS |
763 | } |
764 | else | |
765 | { | |
eb5492fa DJ |
766 | /* We have no symbol information. Our only option is to assume this |
767 | function has a standard stack frame and the normal frame register. | |
768 | Then, we can find the value of our frame pointer on entrance to | |
769 | the callee (or at the present moment if this is the innermost frame). | |
770 | The value stored there should be the address of the stmfd + 8. */ | |
771 | CORE_ADDR frame_loc; | |
772 | LONGEST return_value; | |
773 | ||
774 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
775 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
776 | return; |
777 | else | |
778 | { | |
779 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 780 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 781 | } |
c906108c SS |
782 | } |
783 | ||
eb5492fa DJ |
784 | if (prev_pc < prologue_end) |
785 | prologue_end = prev_pc; | |
786 | ||
c906108c | 787 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 788 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 789 | |
96baa820 JM |
790 | Be careful, however, and if it doesn't look like a prologue, |
791 | don't try to scan it. If, for instance, a frameless function | |
792 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 793 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
794 | and other operations that rely on a knowledge of the stack |
795 | traceback. | |
796 | ||
797 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 798 | if we don't see this as the first insn, we will stop. |
c906108c | 799 | |
f43845b3 MS |
800 | [Note: This doesn't seem to be true any longer, so it's now an |
801 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 802 | |
f43845b3 MS |
803 | [Note further: The "mov ip,sp" only seems to be missing in |
804 | frameless functions at optimization level "-O2" or above, | |
805 | in which case it is often (but not always) replaced by | |
b8d5e71d | 806 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 807 | |
28cd8767 | 808 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 809 | |
94c30b78 MS |
810 | for (current_pc = prologue_start; |
811 | current_pc < prologue_end; | |
f43845b3 | 812 | current_pc += 4) |
96baa820 | 813 | { |
d4473757 KB |
814 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
815 | ||
94c30b78 | 816 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 817 | { |
28cd8767 JG |
818 | ip_offset = 0; |
819 | continue; | |
820 | } | |
821 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
822 | { | |
823 | unsigned imm = insn & 0xff; /* immediate value */ | |
824 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
825 | imm = (imm >> rot) | (imm << (32 - rot)); | |
826 | ip_offset = imm; | |
827 | continue; | |
828 | } | |
829 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
830 | { | |
831 | unsigned imm = insn & 0xff; /* immediate value */ | |
832 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
833 | imm = (imm >> rot) | (imm << (32 - rot)); | |
834 | ip_offset = -imm; | |
f43845b3 MS |
835 | continue; |
836 | } | |
94c30b78 | 837 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 838 | { |
e28a332c JG |
839 | sp_offset -= 4; |
840 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
841 | continue; |
842 | } | |
843 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
844 | /* stmfd sp!, {..., fp, ip, lr, pc} |
845 | or | |
846 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 847 | { |
d4473757 | 848 | int mask = insn & 0xffff; |
ed9a39eb | 849 | |
94c30b78 | 850 | /* Calculate offsets of saved registers. */ |
34e8f22d | 851 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
852 | if (mask & (1 << regno)) |
853 | { | |
854 | sp_offset -= 4; | |
eb5492fa | 855 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
856 | } |
857 | } | |
b8d5e71d MS |
858 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
859 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
860 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
861 | { | |
862 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
863 | continue; | |
864 | } | |
865 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
866 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
867 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
868 | { |
869 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
870 | continue; | |
871 | } | |
d4473757 KB |
872 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
873 | { | |
94c30b78 MS |
874 | unsigned imm = insn & 0xff; /* immediate value */ |
875 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 876 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 877 | fp_offset = -imm + ip_offset; |
9b8d791a | 878 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
879 | } |
880 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
881 | { | |
94c30b78 MS |
882 | unsigned imm = insn & 0xff; /* immediate value */ |
883 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
884 | imm = (imm >> rot) | (imm << (32 - rot)); |
885 | sp_offset -= imm; | |
886 | } | |
887 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
888 | { | |
889 | sp_offset -= 12; | |
34e8f22d | 890 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 891 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
892 | } |
893 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
894 | { | |
895 | int n_saved_fp_regs; | |
896 | unsigned int fp_start_reg, fp_bound_reg; | |
897 | ||
94c30b78 | 898 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 899 | { |
d4473757 KB |
900 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
901 | n_saved_fp_regs = 3; | |
902 | else | |
903 | n_saved_fp_regs = 1; | |
96baa820 | 904 | } |
d4473757 | 905 | else |
96baa820 | 906 | { |
d4473757 KB |
907 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
908 | n_saved_fp_regs = 2; | |
909 | else | |
910 | n_saved_fp_regs = 4; | |
96baa820 | 911 | } |
d4473757 | 912 | |
34e8f22d | 913 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
914 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
915 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
916 | { |
917 | sp_offset -= 12; | |
eb5492fa | 918 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 919 | } |
c906108c | 920 | } |
d4473757 | 921 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 922 | break; /* Condition not true, exit early */ |
b8d5e71d | 923 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 924 | break; /* Don't scan past a block load */ |
d4473757 KB |
925 | else |
926 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 927 | so we just skip what we don't recognize. */ |
d4473757 | 928 | continue; |
c906108c SS |
929 | } |
930 | ||
94c30b78 MS |
931 | /* The frame size is just the negative of the offset (from the |
932 | original SP) of the last thing thing we pushed on the stack. | |
933 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
934 | cache->framesize = -sp_offset; |
935 | if (cache->framereg == ARM_FP_REGNUM) | |
936 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 937 | else |
9b8d791a | 938 | cache->frameoffset = 0; |
c906108c SS |
939 | } |
940 | ||
eb5492fa DJ |
941 | static struct arm_prologue_cache * |
942 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 943 | { |
eb5492fa DJ |
944 | int reg; |
945 | struct arm_prologue_cache *cache; | |
946 | CORE_ADDR unwound_fp; | |
c5aa993b | 947 | |
eb5492fa DJ |
948 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
949 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 950 | |
eb5492fa | 951 | arm_scan_prologue (next_frame, cache); |
848cfffb | 952 | |
eb5492fa DJ |
953 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
954 | if (unwound_fp == 0) | |
955 | return cache; | |
c906108c | 956 | |
eb5492fa | 957 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 958 | |
eb5492fa DJ |
959 | /* Calculate actual addresses of saved registers using offsets |
960 | determined by arm_scan_prologue. */ | |
961 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 962 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
963 | cache->saved_regs[reg].addr += cache->prev_sp; |
964 | ||
965 | return cache; | |
c906108c SS |
966 | } |
967 | ||
eb5492fa DJ |
968 | /* Our frame ID for a normal frame is the current function's starting PC |
969 | and the caller's SP when we were called. */ | |
c906108c | 970 | |
148754e5 | 971 | static void |
eb5492fa DJ |
972 | arm_prologue_this_id (struct frame_info *next_frame, |
973 | void **this_cache, | |
974 | struct frame_id *this_id) | |
c906108c | 975 | { |
eb5492fa DJ |
976 | struct arm_prologue_cache *cache; |
977 | struct frame_id id; | |
978 | CORE_ADDR func; | |
f079148d | 979 | |
eb5492fa DJ |
980 | if (*this_cache == NULL) |
981 | *this_cache = arm_make_prologue_cache (next_frame); | |
982 | cache = *this_cache; | |
2a451106 | 983 | |
eb5492fa | 984 | func = frame_func_unwind (next_frame); |
2a451106 | 985 | |
eb5492fa DJ |
986 | /* This is meant to halt the backtrace at "_start". Make sure we |
987 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 988 | if (func <= LOWEST_PC) |
eb5492fa | 989 | return; |
5a203e44 | 990 | |
eb5492fa DJ |
991 | /* If we've hit a wall, stop. */ |
992 | if (cache->prev_sp == 0) | |
993 | return; | |
24de872b | 994 | |
eb5492fa | 995 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 996 | *this_id = id; |
c906108c SS |
997 | } |
998 | ||
eb5492fa DJ |
999 | static void |
1000 | arm_prologue_prev_register (struct frame_info *next_frame, | |
1001 | void **this_cache, | |
1002 | int prev_regnum, | |
1003 | int *optimized, | |
1004 | enum lval_type *lvalp, | |
1005 | CORE_ADDR *addrp, | |
1006 | int *realnump, | |
1007 | void *valuep) | |
24de872b DJ |
1008 | { |
1009 | struct arm_prologue_cache *cache; | |
1010 | ||
eb5492fa DJ |
1011 | if (*this_cache == NULL) |
1012 | *this_cache = arm_make_prologue_cache (next_frame); | |
1013 | cache = *this_cache; | |
24de872b | 1014 | |
eb5492fa DJ |
1015 | /* If we are asked to unwind the PC, then we need to return the LR |
1016 | instead. The saved value of PC points into this frame's | |
1017 | prologue, not the next frame's resume location. */ | |
1018 | if (prev_regnum == ARM_PC_REGNUM) | |
1019 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 1020 | |
eb5492fa DJ |
1021 | /* SP is generally not saved to the stack, but this frame is |
1022 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
1023 | The value was already reconstructed into PREV_SP. */ | |
1024 | if (prev_regnum == ARM_SP_REGNUM) | |
1025 | { | |
1026 | *lvalp = not_lval; | |
1027 | if (valuep) | |
1028 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
1029 | return; | |
1030 | } | |
1031 | ||
1032 | trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, | |
1033 | optimized, lvalp, addrp, realnump, valuep); | |
1034 | } | |
1035 | ||
1036 | struct frame_unwind arm_prologue_unwind = { | |
1037 | NORMAL_FRAME, | |
1038 | arm_prologue_this_id, | |
1039 | arm_prologue_prev_register | |
1040 | }; | |
1041 | ||
1042 | static const struct frame_unwind * | |
1043 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
1044 | { | |
1045 | return &arm_prologue_unwind; | |
24de872b DJ |
1046 | } |
1047 | ||
1048 | static CORE_ADDR | |
eb5492fa | 1049 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1050 | { |
1051 | struct arm_prologue_cache *cache; | |
1052 | ||
eb5492fa DJ |
1053 | if (*this_cache == NULL) |
1054 | *this_cache = arm_make_prologue_cache (next_frame); | |
1055 | cache = *this_cache; | |
1056 | ||
1057 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1058 | } |
1059 | ||
eb5492fa DJ |
1060 | struct frame_base arm_normal_base = { |
1061 | &arm_prologue_unwind, | |
1062 | arm_normal_frame_base, | |
1063 | arm_normal_frame_base, | |
1064 | arm_normal_frame_base | |
1065 | }; | |
1066 | ||
1067 | static struct arm_prologue_cache * | |
1068 | arm_make_sigtramp_cache (struct frame_info *next_frame) | |
24de872b DJ |
1069 | { |
1070 | struct arm_prologue_cache *cache; | |
eb5492fa DJ |
1071 | int reg; |
1072 | ||
1073 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
24de872b | 1074 | |
eb5492fa | 1075 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
24de872b | 1076 | |
eb5492fa | 1077 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
24de872b | 1078 | |
eb5492fa DJ |
1079 | for (reg = 0; reg < NUM_REGS; reg++) |
1080 | cache->saved_regs[reg].addr | |
1081 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, | |
1082 | frame_pc_unwind (next_frame), reg); | |
24de872b | 1083 | |
eb5492fa DJ |
1084 | /* FIXME: What about thumb mode? */ |
1085 | cache->framereg = ARM_SP_REGNUM; | |
1086 | cache->prev_sp | |
1087 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, | |
7a5ea0d4 | 1088 | register_size (current_gdbarch, cache->framereg)); |
eb5492fa DJ |
1089 | |
1090 | return cache; | |
24de872b | 1091 | } |
c906108c | 1092 | |
eb5492fa DJ |
1093 | static void |
1094 | arm_sigtramp_this_id (struct frame_info *next_frame, | |
1095 | void **this_cache, | |
1096 | struct frame_id *this_id) | |
1097 | { | |
1098 | struct arm_prologue_cache *cache; | |
c906108c | 1099 | |
eb5492fa DJ |
1100 | if (*this_cache == NULL) |
1101 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1102 | cache = *this_cache; | |
c906108c | 1103 | |
eb5492fa DJ |
1104 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
1105 | the sigtramp frame; the PC should be the beginning of the trampoline. */ | |
1106 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | arm_sigtramp_prev_register (struct frame_info *next_frame, | |
1111 | void **this_cache, | |
1112 | int prev_regnum, | |
1113 | int *optimized, | |
1114 | enum lval_type *lvalp, | |
1115 | CORE_ADDR *addrp, | |
1116 | int *realnump, | |
1117 | void *valuep) | |
c906108c | 1118 | { |
eb5492fa | 1119 | struct arm_prologue_cache *cache; |
848cfffb | 1120 | |
eb5492fa DJ |
1121 | if (*this_cache == NULL) |
1122 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1123 | cache = *this_cache; | |
1124 | ||
1125 | trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum, | |
1126 | optimized, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1127 | } |
1128 | ||
eb5492fa DJ |
1129 | struct frame_unwind arm_sigtramp_unwind = { |
1130 | SIGTRAMP_FRAME, | |
1131 | arm_sigtramp_this_id, | |
1132 | arm_sigtramp_prev_register | |
1133 | }; | |
c906108c | 1134 | |
eb5492fa DJ |
1135 | static const struct frame_unwind * |
1136 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) | |
c906108c | 1137 | { |
eb5492fa | 1138 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
0b281939 | 1139 | && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0)) |
eb5492fa DJ |
1140 | return &arm_sigtramp_unwind; |
1141 | ||
1142 | return NULL; | |
c906108c SS |
1143 | } |
1144 | ||
eb5492fa DJ |
1145 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1146 | dummy frame. The frame ID's base needs to match the TOS value | |
1147 | saved by save_dummy_frame_tos() and returned from | |
1148 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1149 | breakpoint. */ | |
c906108c | 1150 | |
eb5492fa DJ |
1151 | static struct frame_id |
1152 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1153 | { |
eb5492fa DJ |
1154 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1155 | frame_pc_unwind (next_frame)); | |
1156 | } | |
c3b4394c | 1157 | |
eb5492fa DJ |
1158 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1159 | be used to construct the previous frame's ID, after looking up the | |
1160 | containing function). */ | |
c3b4394c | 1161 | |
eb5492fa DJ |
1162 | static CORE_ADDR |
1163 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1164 | { | |
1165 | CORE_ADDR pc; | |
1166 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1167 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1168 | } | |
1169 | ||
1170 | static CORE_ADDR | |
1171 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1172 | { | |
1173 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1174 | } |
1175 | ||
2dd604e7 RE |
1176 | /* When arguments must be pushed onto the stack, they go on in reverse |
1177 | order. The code below implements a FILO (stack) to do this. */ | |
1178 | ||
1179 | struct stack_item | |
1180 | { | |
1181 | int len; | |
1182 | struct stack_item *prev; | |
1183 | void *data; | |
1184 | }; | |
1185 | ||
1186 | static struct stack_item * | |
1187 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1188 | { | |
1189 | struct stack_item *si; | |
1190 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1191 | si->data = xmalloc (len); |
2dd604e7 RE |
1192 | si->len = len; |
1193 | si->prev = prev; | |
1194 | memcpy (si->data, contents, len); | |
1195 | return si; | |
1196 | } | |
1197 | ||
1198 | static struct stack_item * | |
1199 | pop_stack_item (struct stack_item *si) | |
1200 | { | |
1201 | struct stack_item *dead = si; | |
1202 | si = si->prev; | |
1203 | xfree (dead->data); | |
1204 | xfree (dead); | |
1205 | return si; | |
1206 | } | |
1207 | ||
1208 | /* We currently only support passing parameters in integer registers. This | |
1209 | conforms with GCC's default model. Several other variants exist and | |
1210 | we should probably support some of them based on the selected ABI. */ | |
1211 | ||
1212 | static CORE_ADDR | |
7d9b040b | 1213 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1214 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1215 | struct value **args, CORE_ADDR sp, int struct_return, | |
1216 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1217 | { |
1218 | int argnum; | |
1219 | int argreg; | |
1220 | int nstack; | |
1221 | struct stack_item *si = NULL; | |
1222 | ||
6a65450a AC |
1223 | /* Set the return address. For the ARM, the return breakpoint is |
1224 | always at BP_ADDR. */ | |
2dd604e7 | 1225 | /* XXX Fix for Thumb. */ |
6a65450a | 1226 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1227 | |
1228 | /* Walk through the list of args and determine how large a temporary | |
1229 | stack is required. Need to take care here as structs may be | |
1230 | passed on the stack, and we have to to push them. */ | |
1231 | nstack = 0; | |
1232 | ||
1233 | argreg = ARM_A1_REGNUM; | |
1234 | nstack = 0; | |
1235 | ||
1236 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1237 | is correctly aligned before we start. We always do this even if | |
1238 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1239 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1240 | |
1241 | /* The struct_return pointer occupies the first parameter | |
1242 | passing register. */ | |
1243 | if (struct_return) | |
1244 | { | |
1245 | if (arm_debug) | |
1246 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1247 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1248 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1249 | argreg++; | |
1250 | } | |
1251 | ||
1252 | for (argnum = 0; argnum < nargs; argnum++) | |
1253 | { | |
1254 | int len; | |
1255 | struct type *arg_type; | |
1256 | struct type *target_type; | |
1257 | enum type_code typecode; | |
1258 | char *val; | |
1259 | ||
1260 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1261 | len = TYPE_LENGTH (arg_type); | |
1262 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1263 | typecode = TYPE_CODE (arg_type); | |
1264 | val = VALUE_CONTENTS (args[argnum]); | |
1265 | ||
1266 | /* If the argument is a pointer to a function, and it is a | |
1267 | Thumb function, create a LOCAL copy of the value and set | |
1268 | the THUMB bit in it. */ | |
1269 | if (TYPE_CODE_PTR == typecode | |
1270 | && target_type != NULL | |
1271 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1272 | { | |
7c0b4a20 | 1273 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1274 | if (arm_pc_is_thumb (regval)) |
1275 | { | |
1276 | val = alloca (len); | |
fbd9dcd3 | 1277 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1278 | } |
1279 | } | |
1280 | ||
1281 | /* Copy the argument to general registers or the stack in | |
1282 | register-sized pieces. Large arguments are split between | |
1283 | registers and stack. */ | |
1284 | while (len > 0) | |
1285 | { | |
b1e29e33 | 1286 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1287 | |
1288 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1289 | { | |
1290 | /* The argument is being passed in a general purpose | |
1291 | register. */ | |
7c0b4a20 | 1292 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1293 | if (arm_debug) |
1294 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1295 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1296 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1297 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1298 | argreg++; | |
1299 | } | |
1300 | else | |
1301 | { | |
1302 | /* Push the arguments onto the stack. */ | |
1303 | if (arm_debug) | |
1304 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1305 | argnum, nstack); | |
b1e29e33 AC |
1306 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1307 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1308 | } |
1309 | ||
1310 | len -= partial_len; | |
1311 | val += partial_len; | |
1312 | } | |
1313 | } | |
1314 | /* If we have an odd number of words to push, then decrement the stack | |
1315 | by one word now, so first stack argument will be dword aligned. */ | |
1316 | if (nstack & 4) | |
1317 | sp -= 4; | |
1318 | ||
1319 | while (si) | |
1320 | { | |
1321 | sp -= si->len; | |
1322 | write_memory (sp, si->data, si->len); | |
1323 | si = pop_stack_item (si); | |
1324 | } | |
1325 | ||
1326 | /* Finally, update teh SP register. */ | |
1327 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1328 | ||
1329 | return sp; | |
1330 | } | |
1331 | ||
c906108c | 1332 | static void |
ed9a39eb | 1333 | print_fpu_flags (int flags) |
c906108c | 1334 | { |
c5aa993b JM |
1335 | if (flags & (1 << 0)) |
1336 | fputs ("IVO ", stdout); | |
1337 | if (flags & (1 << 1)) | |
1338 | fputs ("DVZ ", stdout); | |
1339 | if (flags & (1 << 2)) | |
1340 | fputs ("OFL ", stdout); | |
1341 | if (flags & (1 << 3)) | |
1342 | fputs ("UFL ", stdout); | |
1343 | if (flags & (1 << 4)) | |
1344 | fputs ("INX ", stdout); | |
1345 | putchar ('\n'); | |
c906108c SS |
1346 | } |
1347 | ||
5e74b15c RE |
1348 | /* Print interesting information about the floating point processor |
1349 | (if present) or emulator. */ | |
34e8f22d | 1350 | static void |
d855c300 | 1351 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1352 | struct frame_info *frame, const char *args) |
c906108c | 1353 | { |
52f0bd74 | 1354 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1355 | int type; |
1356 | ||
1357 | type = (status >> 24) & 127; | |
1358 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1359 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1360 | type); |
1361 | fputs ("mask: ", stdout); | |
1362 | print_fpu_flags (status >> 16); | |
1363 | fputs ("flags: ", stdout); | |
1364 | print_fpu_flags (status); | |
c906108c SS |
1365 | } |
1366 | ||
34e8f22d RE |
1367 | /* Return the GDB type object for the "standard" data type of data in |
1368 | register N. */ | |
1369 | ||
1370 | static struct type * | |
7a5ea0d4 | 1371 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1372 | { |
34e8f22d | 1373 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1374 | { |
d7449b42 | 1375 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1376 | return builtin_type_arm_ext_big; |
1377 | else | |
1378 | return builtin_type_arm_ext_littlebyte_bigword; | |
1379 | } | |
1380 | else | |
1381 | return builtin_type_int32; | |
1382 | } | |
1383 | ||
34e8f22d RE |
1384 | /* Index within `registers' of the first byte of the space for |
1385 | register N. */ | |
1386 | ||
1387 | static int | |
1388 | arm_register_byte (int regnum) | |
1389 | { | |
1390 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1391 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1392 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1393 | return (NUM_GREGS * INT_REGISTER_SIZE |
1394 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1395 | else |
7a5ea0d4 DJ |
1396 | return (NUM_GREGS * INT_REGISTER_SIZE |
1397 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1398 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1399 | } | |
1400 | ||
26216b98 AC |
1401 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1402 | static int | |
1403 | arm_register_sim_regno (int regnum) | |
1404 | { | |
1405 | int reg = regnum; | |
1406 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1407 | ||
1408 | if (reg < NUM_GREGS) | |
1409 | return SIM_ARM_R0_REGNUM + reg; | |
1410 | reg -= NUM_GREGS; | |
1411 | ||
1412 | if (reg < NUM_FREGS) | |
1413 | return SIM_ARM_FP0_REGNUM + reg; | |
1414 | reg -= NUM_FREGS; | |
1415 | ||
1416 | if (reg < NUM_SREGS) | |
1417 | return SIM_ARM_FPS_REGNUM + reg; | |
1418 | reg -= NUM_SREGS; | |
1419 | ||
1420 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1421 | } | |
34e8f22d | 1422 | |
a37b3cc0 AC |
1423 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1424 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1425 | It is thought that this is is the floating-point register format on | |
1426 | little-endian systems. */ | |
c906108c | 1427 | |
ed9a39eb | 1428 | static void |
b508a996 RE |
1429 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1430 | void *dbl) | |
c906108c | 1431 | { |
a37b3cc0 | 1432 | DOUBLEST d; |
d7449b42 | 1433 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1434 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1435 | else | |
1436 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1437 | ptr, &d); | |
b508a996 | 1438 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1439 | } |
1440 | ||
34e8f22d | 1441 | static void |
b508a996 | 1442 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1443 | { |
a37b3cc0 | 1444 | DOUBLEST d; |
b508a996 | 1445 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1446 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1447 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1448 | else | |
1449 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1450 | &d, dbl); | |
c906108c | 1451 | } |
ed9a39eb | 1452 | |
c906108c | 1453 | static int |
ed9a39eb | 1454 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1455 | { |
1456 | if (cond == INST_AL || cond == INST_NV) | |
1457 | return 1; | |
1458 | ||
1459 | switch (cond) | |
1460 | { | |
1461 | case INST_EQ: | |
1462 | return ((status_reg & FLAG_Z) != 0); | |
1463 | case INST_NE: | |
1464 | return ((status_reg & FLAG_Z) == 0); | |
1465 | case INST_CS: | |
1466 | return ((status_reg & FLAG_C) != 0); | |
1467 | case INST_CC: | |
1468 | return ((status_reg & FLAG_C) == 0); | |
1469 | case INST_MI: | |
1470 | return ((status_reg & FLAG_N) != 0); | |
1471 | case INST_PL: | |
1472 | return ((status_reg & FLAG_N) == 0); | |
1473 | case INST_VS: | |
1474 | return ((status_reg & FLAG_V) != 0); | |
1475 | case INST_VC: | |
1476 | return ((status_reg & FLAG_V) == 0); | |
1477 | case INST_HI: | |
1478 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1479 | case INST_LS: | |
1480 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1481 | case INST_GE: | |
1482 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1483 | case INST_LT: | |
1484 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1485 | case INST_GT: | |
1486 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1487 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1488 | case INST_LE: |
1489 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1490 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1491 | } |
1492 | return 1; | |
1493 | } | |
1494 | ||
9512d7fd | 1495 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1496 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1497 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1498 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1499 | #define sbits(obj,st,fn) \ | |
1500 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1501 | #define BranchDest(addr,instr) \ | |
1502 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1503 | #define ARM_PC_32 1 | |
1504 | ||
1505 | static unsigned long | |
ed9a39eb JM |
1506 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1507 | unsigned long status_reg) | |
c906108c SS |
1508 | { |
1509 | unsigned long res, shift; | |
1510 | int rm = bits (inst, 0, 3); | |
1511 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1512 | |
1513 | if (bit (inst, 4)) | |
c906108c SS |
1514 | { |
1515 | int rs = bits (inst, 8, 11); | |
1516 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1517 | } | |
1518 | else | |
1519 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1520 | |
1521 | res = (rm == 15 | |
c906108c | 1522 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1523 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1524 | : read_register (rm)); |
1525 | ||
1526 | switch (shifttype) | |
1527 | { | |
c5aa993b | 1528 | case 0: /* LSL */ |
c906108c SS |
1529 | res = shift >= 32 ? 0 : res << shift; |
1530 | break; | |
c5aa993b JM |
1531 | |
1532 | case 1: /* LSR */ | |
c906108c SS |
1533 | res = shift >= 32 ? 0 : res >> shift; |
1534 | break; | |
1535 | ||
c5aa993b JM |
1536 | case 2: /* ASR */ |
1537 | if (shift >= 32) | |
1538 | shift = 31; | |
c906108c SS |
1539 | res = ((res & 0x80000000L) |
1540 | ? ~((~res) >> shift) : res >> shift); | |
1541 | break; | |
1542 | ||
c5aa993b | 1543 | case 3: /* ROR/RRX */ |
c906108c SS |
1544 | shift &= 31; |
1545 | if (shift == 0) | |
1546 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1547 | else | |
c5aa993b | 1548 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1549 | break; |
1550 | } | |
1551 | ||
1552 | return res & 0xffffffff; | |
1553 | } | |
1554 | ||
c906108c SS |
1555 | /* Return number of 1-bits in VAL. */ |
1556 | ||
1557 | static int | |
ed9a39eb | 1558 | bitcount (unsigned long val) |
c906108c SS |
1559 | { |
1560 | int nbits; | |
1561 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1562 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1563 | return nbits; |
1564 | } | |
1565 | ||
34e8f22d | 1566 | CORE_ADDR |
ed9a39eb | 1567 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1568 | { |
c5aa993b | 1569 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1570 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1571 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1572 | unsigned long offset; |
1573 | ||
1574 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1575 | { | |
1576 | CORE_ADDR sp; | |
1577 | ||
1578 | /* Fetch the saved PC from the stack. It's stored above | |
1579 | all of the other registers. */ | |
b1e29e33 | 1580 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1581 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1582 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1583 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1584 | if (nextpc == pc) | |
1585 | error ("Infinite loop detected"); | |
1586 | } | |
1587 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1588 | { | |
34e8f22d | 1589 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1590 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1591 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1592 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1593 | } | |
1594 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1595 | { | |
1596 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1597 | } | |
aa17d93e | 1598 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c SS |
1599 | { |
1600 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1601 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1602 | nextpc = pc_val + offset; |
aa17d93e DJ |
1603 | /* For BLX make sure to clear the low bits. */ |
1604 | if (bits (inst2, 11, 12) == 1) | |
1605 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1606 | } |
aa17d93e | 1607 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1608 | { |
1609 | if (bits (inst1, 3, 6) == 0x0f) | |
1610 | nextpc = pc_val; | |
1611 | else | |
1612 | nextpc = read_register (bits (inst1, 3, 6)); | |
1613 | ||
1614 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1615 | if (nextpc == pc) | |
1616 | error ("Infinite loop detected"); | |
1617 | } | |
c906108c SS |
1618 | |
1619 | return nextpc; | |
1620 | } | |
1621 | ||
34e8f22d | 1622 | CORE_ADDR |
ed9a39eb | 1623 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1624 | { |
1625 | unsigned long pc_val; | |
1626 | unsigned long this_instr; | |
1627 | unsigned long status; | |
1628 | CORE_ADDR nextpc; | |
1629 | ||
1630 | if (arm_pc_is_thumb (pc)) | |
1631 | return thumb_get_next_pc (pc); | |
1632 | ||
1633 | pc_val = (unsigned long) pc; | |
1634 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1635 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1636 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1637 | |
1638 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1639 | { | |
1640 | switch (bits (this_instr, 24, 27)) | |
1641 | { | |
c5aa993b | 1642 | case 0x0: |
94c30b78 | 1643 | case 0x1: /* data processing */ |
c5aa993b JM |
1644 | case 0x2: |
1645 | case 0x3: | |
c906108c SS |
1646 | { |
1647 | unsigned long operand1, operand2, result = 0; | |
1648 | unsigned long rn; | |
1649 | int c; | |
c5aa993b | 1650 | |
c906108c SS |
1651 | if (bits (this_instr, 12, 15) != 15) |
1652 | break; | |
1653 | ||
1654 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1655 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1656 | error ("Illegal update to pc in instruction"); |
1657 | ||
9498281f DJ |
1658 | /* BX <reg>, BLX <reg> */ |
1659 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1660 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1661 | { | |
1662 | rn = bits (this_instr, 0, 3); | |
1663 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1664 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1665 | ||
1666 | if (nextpc == pc) | |
1667 | error ("Infinite loop detected"); | |
1668 | ||
1669 | return nextpc; | |
1670 | } | |
1671 | ||
c906108c SS |
1672 | /* Multiply into PC */ |
1673 | c = (status & FLAG_C) ? 1 : 0; | |
1674 | rn = bits (this_instr, 16, 19); | |
1675 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1676 | |
c906108c SS |
1677 | if (bit (this_instr, 25)) |
1678 | { | |
1679 | unsigned long immval = bits (this_instr, 0, 7); | |
1680 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1681 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1682 | & 0xffffffff; | |
c906108c | 1683 | } |
c5aa993b | 1684 | else /* operand 2 is a shifted register */ |
c906108c | 1685 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1686 | |
c906108c SS |
1687 | switch (bits (this_instr, 21, 24)) |
1688 | { | |
c5aa993b | 1689 | case 0x0: /*and */ |
c906108c SS |
1690 | result = operand1 & operand2; |
1691 | break; | |
1692 | ||
c5aa993b | 1693 | case 0x1: /*eor */ |
c906108c SS |
1694 | result = operand1 ^ operand2; |
1695 | break; | |
1696 | ||
c5aa993b | 1697 | case 0x2: /*sub */ |
c906108c SS |
1698 | result = operand1 - operand2; |
1699 | break; | |
1700 | ||
c5aa993b | 1701 | case 0x3: /*rsb */ |
c906108c SS |
1702 | result = operand2 - operand1; |
1703 | break; | |
1704 | ||
c5aa993b | 1705 | case 0x4: /*add */ |
c906108c SS |
1706 | result = operand1 + operand2; |
1707 | break; | |
1708 | ||
c5aa993b | 1709 | case 0x5: /*adc */ |
c906108c SS |
1710 | result = operand1 + operand2 + c; |
1711 | break; | |
1712 | ||
c5aa993b | 1713 | case 0x6: /*sbc */ |
c906108c SS |
1714 | result = operand1 - operand2 + c; |
1715 | break; | |
1716 | ||
c5aa993b | 1717 | case 0x7: /*rsc */ |
c906108c SS |
1718 | result = operand2 - operand1 + c; |
1719 | break; | |
1720 | ||
c5aa993b JM |
1721 | case 0x8: |
1722 | case 0x9: | |
1723 | case 0xa: | |
1724 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1725 | result = (unsigned long) nextpc; |
1726 | break; | |
1727 | ||
c5aa993b | 1728 | case 0xc: /*orr */ |
c906108c SS |
1729 | result = operand1 | operand2; |
1730 | break; | |
1731 | ||
c5aa993b | 1732 | case 0xd: /*mov */ |
c906108c SS |
1733 | /* Always step into a function. */ |
1734 | result = operand2; | |
c5aa993b | 1735 | break; |
c906108c | 1736 | |
c5aa993b | 1737 | case 0xe: /*bic */ |
c906108c SS |
1738 | result = operand1 & ~operand2; |
1739 | break; | |
1740 | ||
c5aa993b | 1741 | case 0xf: /*mvn */ |
c906108c SS |
1742 | result = ~operand2; |
1743 | break; | |
1744 | } | |
1745 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1746 | ||
1747 | if (nextpc == pc) | |
1748 | error ("Infinite loop detected"); | |
1749 | break; | |
1750 | } | |
c5aa993b JM |
1751 | |
1752 | case 0x4: | |
1753 | case 0x5: /* data transfer */ | |
1754 | case 0x6: | |
1755 | case 0x7: | |
c906108c SS |
1756 | if (bit (this_instr, 20)) |
1757 | { | |
1758 | /* load */ | |
1759 | if (bits (this_instr, 12, 15) == 15) | |
1760 | { | |
1761 | /* rd == pc */ | |
c5aa993b | 1762 | unsigned long rn; |
c906108c | 1763 | unsigned long base; |
c5aa993b | 1764 | |
c906108c SS |
1765 | if (bit (this_instr, 22)) |
1766 | error ("Illegal update to pc in instruction"); | |
1767 | ||
1768 | /* byte write to PC */ | |
1769 | rn = bits (this_instr, 16, 19); | |
1770 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1771 | if (bit (this_instr, 24)) | |
1772 | { | |
1773 | /* pre-indexed */ | |
1774 | int c = (status & FLAG_C) ? 1 : 0; | |
1775 | unsigned long offset = | |
c5aa993b | 1776 | (bit (this_instr, 25) |
ed9a39eb | 1777 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1778 | : bits (this_instr, 0, 11)); |
c906108c SS |
1779 | |
1780 | if (bit (this_instr, 23)) | |
1781 | base += offset; | |
1782 | else | |
1783 | base -= offset; | |
1784 | } | |
c5aa993b | 1785 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1786 | 4); |
c5aa993b | 1787 | |
c906108c SS |
1788 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1789 | ||
1790 | if (nextpc == pc) | |
1791 | error ("Infinite loop detected"); | |
1792 | } | |
1793 | } | |
1794 | break; | |
c5aa993b JM |
1795 | |
1796 | case 0x8: | |
1797 | case 0x9: /* block transfer */ | |
c906108c SS |
1798 | if (bit (this_instr, 20)) |
1799 | { | |
1800 | /* LDM */ | |
1801 | if (bit (this_instr, 15)) | |
1802 | { | |
1803 | /* loading pc */ | |
1804 | int offset = 0; | |
1805 | ||
1806 | if (bit (this_instr, 23)) | |
1807 | { | |
1808 | /* up */ | |
1809 | unsigned long reglist = bits (this_instr, 0, 14); | |
1810 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1811 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1812 | offset += 4; |
1813 | } | |
1814 | else if (bit (this_instr, 24)) | |
1815 | offset = -4; | |
c5aa993b | 1816 | |
c906108c | 1817 | { |
c5aa993b JM |
1818 | unsigned long rn_val = |
1819 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1820 | nextpc = |
1821 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1822 | + offset), |
c906108c SS |
1823 | 4); |
1824 | } | |
1825 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1826 | if (nextpc == pc) | |
1827 | error ("Infinite loop detected"); | |
1828 | } | |
1829 | } | |
1830 | break; | |
c5aa993b JM |
1831 | |
1832 | case 0xb: /* branch & link */ | |
1833 | case 0xa: /* branch */ | |
c906108c SS |
1834 | { |
1835 | nextpc = BranchDest (pc, this_instr); | |
1836 | ||
9498281f DJ |
1837 | /* BLX */ |
1838 | if (bits (this_instr, 28, 31) == INST_NV) | |
1839 | nextpc |= bit (this_instr, 24) << 1; | |
1840 | ||
c906108c SS |
1841 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1842 | if (nextpc == pc) | |
1843 | error ("Infinite loop detected"); | |
1844 | break; | |
1845 | } | |
c5aa993b JM |
1846 | |
1847 | case 0xc: | |
1848 | case 0xd: | |
1849 | case 0xe: /* coproc ops */ | |
1850 | case 0xf: /* SWI */ | |
c906108c SS |
1851 | break; |
1852 | ||
1853 | default: | |
97e03143 | 1854 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
1855 | return (pc); |
1856 | } | |
1857 | } | |
1858 | ||
1859 | return nextpc; | |
1860 | } | |
1861 | ||
9512d7fd FN |
1862 | /* single_step() is called just before we want to resume the inferior, |
1863 | if we want to single-step it but there is no hardware or kernel | |
1864 | single-step support. We find the target of the coming instruction | |
1865 | and breakpoint it. | |
1866 | ||
94c30b78 MS |
1867 | single_step() is also called just after the inferior stops. If we |
1868 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1869 | |
34e8f22d RE |
1870 | static void |
1871 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1872 | { |
b8d5e71d | 1873 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
1874 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
1875 | ||
1876 | if (insert_bpt) | |
1877 | { | |
34e8f22d | 1878 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 1879 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1880 | } |
1881 | else | |
80fcf3f0 | 1882 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1883 | } |
9512d7fd | 1884 | |
c906108c SS |
1885 | #include "bfd-in2.h" |
1886 | #include "libcoff.h" | |
1887 | ||
1888 | static int | |
ed9a39eb | 1889 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1890 | { |
1891 | if (arm_pc_is_thumb (memaddr)) | |
1892 | { | |
c5aa993b JM |
1893 | static asymbol *asym; |
1894 | static combined_entry_type ce; | |
1895 | static struct coff_symbol_struct csym; | |
27cddce2 | 1896 | static struct bfd fake_bfd; |
c5aa993b | 1897 | static bfd_target fake_target; |
c906108c SS |
1898 | |
1899 | if (csym.native == NULL) | |
1900 | { | |
da3c6d4a MS |
1901 | /* Create a fake symbol vector containing a Thumb symbol. |
1902 | This is solely so that the code in print_insn_little_arm() | |
1903 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1904 | the presence of a Thumb symbol and switch to decoding | |
1905 | Thumb instructions. */ | |
c5aa993b JM |
1906 | |
1907 | fake_target.flavour = bfd_target_coff_flavour; | |
1908 | fake_bfd.xvec = &fake_target; | |
c906108c | 1909 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1910 | csym.native = &ce; |
1911 | csym.symbol.the_bfd = &fake_bfd; | |
1912 | csym.symbol.name = "fake"; | |
1913 | asym = (asymbol *) & csym; | |
c906108c | 1914 | } |
c5aa993b | 1915 | |
c906108c | 1916 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1917 | info->symbols = &asym; |
c906108c SS |
1918 | } |
1919 | else | |
1920 | info->symbols = NULL; | |
c5aa993b | 1921 | |
d7449b42 | 1922 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1923 | return print_insn_big_arm (memaddr, info); |
1924 | else | |
1925 | return print_insn_little_arm (memaddr, info); | |
1926 | } | |
1927 | ||
66e810cd RE |
1928 | /* The following define instruction sequences that will cause ARM |
1929 | cpu's to take an undefined instruction trap. These are used to | |
1930 | signal a breakpoint to GDB. | |
1931 | ||
1932 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1933 | modes. A different instruction is required for each mode. The ARM | |
1934 | cpu's can also be big or little endian. Thus four different | |
1935 | instructions are needed to support all cases. | |
1936 | ||
1937 | Note: ARMv4 defines several new instructions that will take the | |
1938 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1939 | not in fact add the new instructions. The new undefined | |
1940 | instructions in ARMv4 are all instructions that had no defined | |
1941 | behaviour in earlier chips. There is no guarantee that they will | |
1942 | raise an exception, but may be treated as NOP's. In practice, it | |
1943 | may only safe to rely on instructions matching: | |
1944 | ||
1945 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1946 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1947 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1948 | ||
1949 | Even this may only true if the condition predicate is true. The | |
1950 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1951 | ||
1952 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1953 | and NetBSD all use a software interrupt rather than an undefined | |
1954 | instruction to force a trap. This can be handled by by the | |
1955 | abi-specific code during establishment of the gdbarch vector. */ | |
1956 | ||
1957 | ||
d7b486e7 RE |
1958 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1959 | override these definitions. */ | |
66e810cd RE |
1960 | #ifndef ARM_LE_BREAKPOINT |
1961 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1962 | #endif | |
1963 | #ifndef ARM_BE_BREAKPOINT | |
1964 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1965 | #endif | |
1966 | #ifndef THUMB_LE_BREAKPOINT | |
1967 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1968 | #endif | |
1969 | #ifndef THUMB_BE_BREAKPOINT | |
1970 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1971 | #endif | |
1972 | ||
1973 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1974 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1975 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1976 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1977 | ||
34e8f22d RE |
1978 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1979 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1980 | breakpoint should be used. It returns a pointer to a string of |
1981 | bytes that encode a breakpoint instruction, stores the length of | |
1982 | the string to *lenptr, and adjusts the program counter (if | |
1983 | necessary) to point to the actual memory location where the | |
c906108c SS |
1984 | breakpoint should be inserted. */ |
1985 | ||
34e8f22d RE |
1986 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
1987 | breakpoints and storing their handles instread of what was in | |
1988 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 1989 | otherwise remote-rdp will have to change. */ |
34e8f22d | 1990 | |
ab89facf | 1991 | static const unsigned char * |
ed9a39eb | 1992 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1993 | { |
66e810cd RE |
1994 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1995 | ||
c906108c SS |
1996 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
1997 | { | |
66e810cd RE |
1998 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1999 | *lenptr = tdep->thumb_breakpoint_size; | |
2000 | return tdep->thumb_breakpoint; | |
c906108c SS |
2001 | } |
2002 | else | |
2003 | { | |
66e810cd RE |
2004 | *lenptr = tdep->arm_breakpoint_size; |
2005 | return tdep->arm_breakpoint; | |
c906108c SS |
2006 | } |
2007 | } | |
ed9a39eb JM |
2008 | |
2009 | /* Extract from an array REGBUF containing the (raw) register state a | |
2010 | function return value of type TYPE, and copy that, in virtual | |
2011 | format, into VALBUF. */ | |
2012 | ||
34e8f22d | 2013 | static void |
ed9a39eb | 2014 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2015 | struct regcache *regs, |
2016 | void *dst) | |
ed9a39eb | 2017 | { |
b508a996 RE |
2018 | bfd_byte *valbuf = dst; |
2019 | ||
ed9a39eb | 2020 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2021 | { |
fd50bc42 | 2022 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2023 | { |
2024 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2025 | { |
2026 | /* The value is in register F0 in internal format. We need to | |
2027 | extract the raw value and then convert it to the desired | |
2028 | internal type. */ | |
7a5ea0d4 | 2029 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2030 | |
2031 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2032 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2033 | valbuf); | |
2034 | } | |
08216dd7 RE |
2035 | break; |
2036 | ||
fd50bc42 | 2037 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2038 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2039 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2040 | if (TYPE_LENGTH (type) > 4) | |
2041 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2042 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2043 | break; |
2044 | ||
2045 | default: | |
2046 | internal_error | |
2047 | (__FILE__, __LINE__, | |
2048 | "arm_extract_return_value: Floating point model not supported"); | |
2049 | break; | |
2050 | } | |
2051 | } | |
b508a996 RE |
2052 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2053 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2054 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2055 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2056 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2057 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2058 | { | |
2059 | /* If the the type is a plain integer, then the access is | |
2060 | straight-forward. Otherwise we have to play around a bit more. */ | |
2061 | int len = TYPE_LENGTH (type); | |
2062 | int regno = ARM_A1_REGNUM; | |
2063 | ULONGEST tmp; | |
2064 | ||
2065 | while (len > 0) | |
2066 | { | |
2067 | /* By using store_unsigned_integer we avoid having to do | |
2068 | anything special for small big-endian values. */ | |
2069 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2070 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2071 | (len > INT_REGISTER_SIZE |
2072 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2073 | tmp); |
7a5ea0d4 DJ |
2074 | len -= INT_REGISTER_SIZE; |
2075 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2076 | } |
2077 | } | |
ed9a39eb | 2078 | else |
b508a996 RE |
2079 | { |
2080 | /* For a structure or union the behaviour is as if the value had | |
2081 | been stored to word-aligned memory and then loaded into | |
2082 | registers with 32-bit load instruction(s). */ | |
2083 | int len = TYPE_LENGTH (type); | |
2084 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2085 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2086 | |
2087 | while (len > 0) | |
2088 | { | |
2089 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2090 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2091 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2092 | len -= INT_REGISTER_SIZE; | |
2093 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2094 | } |
2095 | } | |
34e8f22d RE |
2096 | } |
2097 | ||
67255d04 RE |
2098 | /* Extract from an array REGBUF containing the (raw) register state |
2099 | the address in which a function should return its structure value. */ | |
2100 | ||
2101 | static CORE_ADDR | |
95f95911 | 2102 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2103 | { |
95f95911 MS |
2104 | ULONGEST ret; |
2105 | ||
2106 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2107 | return ret; | |
67255d04 RE |
2108 | } |
2109 | ||
2110 | /* Will a function return an aggregate type in memory or in a | |
2111 | register? Return 0 if an aggregate type can be returned in a | |
2112 | register, 1 if it must be returned in memory. */ | |
2113 | ||
2114 | static int | |
2115 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2116 | { | |
2117 | int nRc; | |
52f0bd74 | 2118 | enum type_code code; |
67255d04 | 2119 | |
44e1a9eb DJ |
2120 | CHECK_TYPEDEF (type); |
2121 | ||
67255d04 RE |
2122 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2123 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2124 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2125 | offset of each addressable subfield must be zero. Note that bit | |
2126 | fields are not addressable, and all addressable subfields of | |
2127 | unions always start at offset zero. | |
67255d04 RE |
2128 | |
2129 | This function is based on the behaviour of GCC 2.95.1. | |
2130 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2131 | ||
2132 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2133 | parameters correctly for a function returning the following | |
2134 | structure: struct { float f;}; This should be returned in memory, | |
2135 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2136 | know of any way to detect if a function like the above has been | |
2137 | compiled with the correct calling convention. */ | |
2138 | ||
2139 | /* All aggregate types that won't fit in a register must be returned | |
2140 | in memory. */ | |
b1e29e33 | 2141 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2142 | { |
2143 | return 1; | |
2144 | } | |
2145 | ||
2146 | /* The only aggregate types that can be returned in a register are | |
2147 | structs and unions. Arrays must be returned in memory. */ | |
2148 | code = TYPE_CODE (type); | |
2149 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2150 | { | |
2151 | return 1; | |
2152 | } | |
2153 | ||
2154 | /* Assume all other aggregate types can be returned in a register. | |
2155 | Run a check for structures, unions and arrays. */ | |
2156 | nRc = 0; | |
2157 | ||
2158 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2159 | { | |
2160 | int i; | |
2161 | /* Need to check if this struct/union is "integer" like. For | |
2162 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2163 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2164 | subfield must be zero. Note that bit fields are not | |
2165 | addressable, and unions always start at offset zero. If any | |
2166 | of the subfields is a floating point type, the struct/union | |
2167 | cannot be an integer type. */ | |
67255d04 RE |
2168 | |
2169 | /* For each field in the object, check: | |
2170 | 1) Is it FP? --> yes, nRc = 1; | |
2171 | 2) Is it addressable (bitpos != 0) and | |
2172 | not packed (bitsize == 0)? | |
2173 | --> yes, nRc = 1 | |
2174 | */ | |
2175 | ||
2176 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2177 | { | |
2178 | enum type_code field_type_code; | |
44e1a9eb | 2179 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2180 | |
2181 | /* Is it a floating point type field? */ | |
2182 | if (field_type_code == TYPE_CODE_FLT) | |
2183 | { | |
2184 | nRc = 1; | |
2185 | break; | |
2186 | } | |
2187 | ||
2188 | /* If bitpos != 0, then we have to care about it. */ | |
2189 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2190 | { | |
2191 | /* Bitfields are not addressable. If the field bitsize is | |
2192 | zero, then the field is not packed. Hence it cannot be | |
2193 | a bitfield or any other packed type. */ | |
2194 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2195 | { | |
2196 | nRc = 1; | |
2197 | break; | |
2198 | } | |
2199 | } | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | return nRc; | |
2204 | } | |
2205 | ||
34e8f22d RE |
2206 | /* Write into appropriate registers a function return value of type |
2207 | TYPE, given in virtual format. */ | |
2208 | ||
2209 | static void | |
b508a996 RE |
2210 | arm_store_return_value (struct type *type, struct regcache *regs, |
2211 | const void *src) | |
34e8f22d | 2212 | { |
b508a996 RE |
2213 | const bfd_byte *valbuf = src; |
2214 | ||
34e8f22d RE |
2215 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2216 | { | |
7a5ea0d4 | 2217 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2218 | |
fd50bc42 | 2219 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2220 | { |
2221 | case ARM_FLOAT_FPA: | |
2222 | ||
b508a996 RE |
2223 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2224 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2225 | break; |
2226 | ||
fd50bc42 | 2227 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2228 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2229 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2230 | if (TYPE_LENGTH (type) > 4) | |
2231 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2232 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2233 | break; |
2234 | ||
2235 | default: | |
2236 | internal_error | |
2237 | (__FILE__, __LINE__, | |
2238 | "arm_store_return_value: Floating point model not supported"); | |
2239 | break; | |
2240 | } | |
34e8f22d | 2241 | } |
b508a996 RE |
2242 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2243 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2244 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2245 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2246 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2247 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2248 | { | |
2249 | if (TYPE_LENGTH (type) <= 4) | |
2250 | { | |
2251 | /* Values of one word or less are zero/sign-extended and | |
2252 | returned in r0. */ | |
7a5ea0d4 | 2253 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2254 | LONGEST val = unpack_long (type, valbuf); |
2255 | ||
7a5ea0d4 | 2256 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2257 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2258 | } | |
2259 | else | |
2260 | { | |
2261 | /* Integral values greater than one word are stored in consecutive | |
2262 | registers starting with r0. This will always be a multiple of | |
2263 | the regiser size. */ | |
2264 | int len = TYPE_LENGTH (type); | |
2265 | int regno = ARM_A1_REGNUM; | |
2266 | ||
2267 | while (len > 0) | |
2268 | { | |
2269 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2270 | len -= INT_REGISTER_SIZE; |
2271 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2272 | } |
2273 | } | |
2274 | } | |
34e8f22d | 2275 | else |
b508a996 RE |
2276 | { |
2277 | /* For a structure or union the behaviour is as if the value had | |
2278 | been stored to word-aligned memory and then loaded into | |
2279 | registers with 32-bit load instruction(s). */ | |
2280 | int len = TYPE_LENGTH (type); | |
2281 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2282 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2283 | |
2284 | while (len > 0) | |
2285 | { | |
2286 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2287 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2288 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2289 | len -= INT_REGISTER_SIZE; |
2290 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2291 | } |
2292 | } | |
34e8f22d RE |
2293 | } |
2294 | ||
9df628e0 RE |
2295 | static int |
2296 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2297 | { | |
2298 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2299 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2300 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2301 | ||
2302 | jb_addr = read_register (ARM_A1_REGNUM); | |
2303 | ||
2304 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2305 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2306 | return 0; |
2307 | ||
7a5ea0d4 | 2308 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2309 | return 1; |
2310 | } | |
2311 | ||
ed9a39eb | 2312 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2313 | |
2314 | int | |
ed9a39eb | 2315 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2316 | { |
2317 | CORE_ADDR start_addr; | |
2318 | ||
ed9a39eb JM |
2319 | /* Find the starting address of the function containing the PC. If |
2320 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2321 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2322 | &start_addr, NULL)) | |
c906108c SS |
2323 | return 0; |
2324 | ||
2325 | return strncmp (name, "_call_via_r", 11) == 0; | |
2326 | } | |
2327 | ||
ed9a39eb JM |
2328 | /* If PC is in a Thumb call or return stub, return the address of the |
2329 | target PC, which is in a register. The thunk functions are called | |
2330 | _called_via_xx, where x is the register name. The possible names | |
2331 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2332 | |
2333 | CORE_ADDR | |
ed9a39eb | 2334 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2335 | { |
c5aa993b | 2336 | char *name; |
c906108c SS |
2337 | CORE_ADDR start_addr; |
2338 | ||
2339 | /* Find the starting address and name of the function containing the PC. */ | |
2340 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2341 | return 0; | |
2342 | ||
2343 | /* Call thunks always start with "_call_via_". */ | |
2344 | if (strncmp (name, "_call_via_", 10) == 0) | |
2345 | { | |
ed9a39eb JM |
2346 | /* Use the name suffix to determine which register contains the |
2347 | target PC. */ | |
c5aa993b JM |
2348 | static char *table[15] = |
2349 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2350 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2351 | }; | |
c906108c SS |
2352 | int regno; |
2353 | ||
2354 | for (regno = 0; regno <= 14; regno++) | |
2355 | if (strcmp (&name[10], table[regno]) == 0) | |
2356 | return read_register (regno); | |
2357 | } | |
ed9a39eb | 2358 | |
c5aa993b | 2359 | return 0; /* not a stub */ |
c906108c SS |
2360 | } |
2361 | ||
afd7eef0 RE |
2362 | static void |
2363 | set_arm_command (char *args, int from_tty) | |
2364 | { | |
2365 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); | |
2366 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); | |
2367 | } | |
2368 | ||
2369 | static void | |
2370 | show_arm_command (char *args, int from_tty) | |
2371 | { | |
26304000 | 2372 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2373 | } |
2374 | ||
fd50bc42 RE |
2375 | enum arm_float_model |
2376 | arm_get_fp_model (struct gdbarch *gdbarch) | |
2377 | { | |
2378 | if (arm_fp_model == ARM_FLOAT_AUTO) | |
2379 | return gdbarch_tdep (gdbarch)->fp_model; | |
2380 | ||
2381 | return arm_fp_model; | |
2382 | } | |
2383 | ||
2384 | static void | |
2385 | arm_set_fp (struct gdbarch *gdbarch) | |
2386 | { | |
2387 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); | |
2388 | ||
2389 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE | |
2390 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) | |
2391 | { | |
2392 | set_gdbarch_double_format (gdbarch, | |
2393 | &floatformat_ieee_double_littlebyte_bigword); | |
2394 | set_gdbarch_long_double_format | |
2395 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2396 | } | |
2397 | else | |
2398 | { | |
2399 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2400 | set_gdbarch_long_double_format (gdbarch, | |
2401 | &floatformat_ieee_double_little); | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | static void | |
2406 | set_fp_model_sfunc (char *args, int from_tty, | |
2407 | struct cmd_list_element *c) | |
2408 | { | |
2409 | enum arm_float_model fp_model; | |
2410 | ||
2411 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2412 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2413 | { | |
2414 | arm_fp_model = fp_model; | |
2415 | break; | |
2416 | } | |
2417 | ||
2418 | if (fp_model == ARM_FLOAT_LAST) | |
2419 | internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", | |
2420 | current_fp_model); | |
2421 | ||
2422 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2423 | arm_set_fp (current_gdbarch); | |
2424 | } | |
2425 | ||
2426 | static void | |
2427 | show_fp_model (char *args, int from_tty, | |
2428 | struct cmd_list_element *c) | |
2429 | { | |
2430 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2431 | ||
2432 | if (arm_fp_model == ARM_FLOAT_AUTO | |
2433 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2434 | printf_filtered (" - the default for the current ABI is \"%s\".\n", | |
2435 | fp_model_strings[tdep->fp_model]); | |
2436 | } | |
2437 | ||
afd7eef0 RE |
2438 | /* If the user changes the register disassembly style used for info |
2439 | register and other commands, we have to also switch the style used | |
2440 | in opcodes for disassembly output. This function is run in the "set | |
2441 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2442 | |
2443 | static void | |
afd7eef0 | 2444 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2445 | struct cmd_list_element *c) |
2446 | { | |
afd7eef0 | 2447 | set_disassembly_style (); |
bc90b915 FN |
2448 | } |
2449 | \f | |
966fbf70 | 2450 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2451 | static const char * |
34e8f22d | 2452 | arm_register_name (int i) |
966fbf70 RE |
2453 | { |
2454 | return arm_register_names[i]; | |
2455 | } | |
2456 | ||
bc90b915 | 2457 | static void |
afd7eef0 | 2458 | set_disassembly_style (void) |
bc90b915 FN |
2459 | { |
2460 | const char *setname, *setdesc, **regnames; | |
2461 | int numregs, j; | |
2462 | ||
afd7eef0 | 2463 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2464 | int current = 0; |
2465 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2466 | while ((disassembly_style != setname) |
2467 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2468 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2469 | current_option = current; | |
2470 | ||
94c30b78 | 2471 | /* Fill our copy. */ |
bc90b915 FN |
2472 | for (j = 0; j < numregs; j++) |
2473 | arm_register_names[j] = (char *) regnames[j]; | |
2474 | ||
94c30b78 | 2475 | /* Adjust case. */ |
34e8f22d | 2476 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2477 | { |
34e8f22d RE |
2478 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2479 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2480 | } |
2481 | else | |
2482 | { | |
34e8f22d RE |
2483 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2484 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2485 | } |
2486 | ||
94c30b78 | 2487 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2488 | set_arm_regname_option (current); |
2489 | } | |
2490 | ||
afd7eef0 RE |
2491 | /* arm_othernames implements the "othernames" command. This is deprecated |
2492 | by the "set arm disassembly" command. */ | |
bc90b915 FN |
2493 | |
2494 | static void | |
2495 | arm_othernames (char *names, int n) | |
2496 | { | |
94c30b78 | 2497 | /* Circle through the various flavors. */ |
afd7eef0 | 2498 | current_option = (current_option + 1) % num_disassembly_options; |
bc90b915 | 2499 | |
afd7eef0 RE |
2500 | disassembly_style = valid_disassembly_styles[current_option]; |
2501 | set_disassembly_style (); | |
bc90b915 FN |
2502 | } |
2503 | ||
082fc60d RE |
2504 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2505 | function. */ | |
2506 | ||
2507 | static int | |
2508 | coff_sym_is_thumb (int val) | |
2509 | { | |
2510 | return (val == C_THUMBEXT || | |
2511 | val == C_THUMBSTAT || | |
2512 | val == C_THUMBEXTFUNC || | |
2513 | val == C_THUMBSTATFUNC || | |
2514 | val == C_THUMBLABEL); | |
2515 | } | |
2516 | ||
2517 | /* arm_coff_make_msymbol_special() | |
2518 | arm_elf_make_msymbol_special() | |
2519 | ||
2520 | These functions test whether the COFF or ELF symbol corresponds to | |
2521 | an address in thumb code, and set a "special" bit in a minimal | |
2522 | symbol to indicate that it does. */ | |
2523 | ||
34e8f22d | 2524 | static void |
082fc60d RE |
2525 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2526 | { | |
2527 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2528 | STT_ARM_TFUNC). */ | |
2529 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2530 | == STT_LOPROC) | |
2531 | MSYMBOL_SET_SPECIAL (msym); | |
2532 | } | |
2533 | ||
34e8f22d | 2534 | static void |
082fc60d RE |
2535 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2536 | { | |
2537 | if (coff_sym_is_thumb (val)) | |
2538 | MSYMBOL_SET_SPECIAL (msym); | |
2539 | } | |
2540 | ||
756fe439 DJ |
2541 | static void |
2542 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2543 | { | |
2544 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2545 | ||
2546 | /* If necessary, set the T bit. */ | |
2547 | if (arm_apcs_32) | |
2548 | { | |
2549 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2550 | if (arm_pc_is_thumb (pc)) | |
2551 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2552 | else | |
2553 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2554 | } | |
2555 | } | |
97e03143 | 2556 | \f |
70f80edf JT |
2557 | static enum gdb_osabi |
2558 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2559 | { |
70f80edf JT |
2560 | unsigned int elfosabi, eflags; |
2561 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2562 | |
70f80edf | 2563 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2564 | |
70f80edf | 2565 | switch (elfosabi) |
97e03143 | 2566 | { |
70f80edf JT |
2567 | case ELFOSABI_NONE: |
2568 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2569 | file are conforming to the base specification for that machine | |
2570 | (there are no OS-specific extensions). In order to determine the | |
2571 | real OS in use we must look for OS notes that have been added. */ | |
2572 | bfd_map_over_sections (abfd, | |
2573 | generic_elf_osabi_sniff_abi_tag_sections, | |
2574 | &osabi); | |
2575 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2576 | { |
70f80edf JT |
2577 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2578 | field for more information. */ | |
2579 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2580 | switch (eflags) | |
97e03143 | 2581 | { |
70f80edf JT |
2582 | case EF_ARM_EABI_VER1: |
2583 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2584 | break; |
2585 | ||
70f80edf JT |
2586 | case EF_ARM_EABI_VER2: |
2587 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2588 | break; |
2589 | ||
70f80edf JT |
2590 | case EF_ARM_EABI_UNKNOWN: |
2591 | /* Assume GNU tools. */ | |
2592 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2593 | break; |
2594 | ||
70f80edf JT |
2595 | default: |
2596 | internal_error (__FILE__, __LINE__, | |
2597 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2598 | "version 0x%x", eflags); | |
97e03143 RE |
2599 | } |
2600 | } | |
70f80edf | 2601 | break; |
97e03143 | 2602 | |
70f80edf JT |
2603 | case ELFOSABI_ARM: |
2604 | /* GNU tools use this value. Check note sections in this case, | |
2605 | as well. */ | |
97e03143 | 2606 | bfd_map_over_sections (abfd, |
70f80edf JT |
2607 | generic_elf_osabi_sniff_abi_tag_sections, |
2608 | &osabi); | |
2609 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2610 | { |
70f80edf JT |
2611 | /* Assume APCS ABI. */ |
2612 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2613 | } |
2614 | break; | |
2615 | ||
97e03143 | 2616 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2617 | osabi = GDB_OSABI_FREEBSD_ELF; |
2618 | break; | |
97e03143 | 2619 | |
70f80edf JT |
2620 | case ELFOSABI_NETBSD: |
2621 | osabi = GDB_OSABI_NETBSD_ELF; | |
2622 | break; | |
97e03143 | 2623 | |
70f80edf JT |
2624 | case ELFOSABI_LINUX: |
2625 | osabi = GDB_OSABI_LINUX; | |
2626 | break; | |
97e03143 RE |
2627 | } |
2628 | ||
70f80edf | 2629 | return osabi; |
97e03143 RE |
2630 | } |
2631 | ||
70f80edf | 2632 | \f |
da3c6d4a MS |
2633 | /* Initialize the current architecture based on INFO. If possible, |
2634 | re-use an architecture from ARCHES, which is a list of | |
2635 | architectures already created during this debugging session. | |
97e03143 | 2636 | |
da3c6d4a MS |
2637 | Called e.g. at program startup, when reading a core file, and when |
2638 | reading a binary file. */ | |
97e03143 | 2639 | |
39bbf761 RE |
2640 | static struct gdbarch * |
2641 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2642 | { | |
97e03143 | 2643 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2644 | struct gdbarch *gdbarch; |
2645 | ||
97e03143 | 2646 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2647 | |
4be87837 | 2648 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2649 | { |
4be87837 | 2650 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2651 | { |
4be87837 DJ |
2652 | case bfd_target_aout_flavour: |
2653 | /* Assume it's an old APCS-style ABI. */ | |
2654 | info.osabi = GDB_OSABI_ARM_APCS; | |
2655 | break; | |
97e03143 | 2656 | |
4be87837 DJ |
2657 | case bfd_target_coff_flavour: |
2658 | /* Assume it's an old APCS-style ABI. */ | |
2659 | /* XXX WinCE? */ | |
2660 | info.osabi = GDB_OSABI_ARM_APCS; | |
2661 | break; | |
97e03143 | 2662 | |
4be87837 DJ |
2663 | default: |
2664 | /* Leave it as "unknown". */ | |
50ceaba5 | 2665 | break; |
97e03143 RE |
2666 | } |
2667 | } | |
2668 | ||
4be87837 DJ |
2669 | /* If there is already a candidate, use it. */ |
2670 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2671 | if (arches != NULL) | |
2672 | return arches->gdbarch; | |
97e03143 RE |
2673 | |
2674 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2675 | gdbarch = gdbarch_alloc (&info, tdep); | |
2676 | ||
fd50bc42 RE |
2677 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
2678 | now, and we now provide a way for the user to force the model. So | |
2679 | default to the most useful variant. */ | |
2680 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
08216dd7 RE |
2681 | |
2682 | /* Breakpoints. */ | |
67255d04 RE |
2683 | switch (info.byte_order) |
2684 | { | |
2685 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2686 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2687 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2688 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2689 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2690 | ||
67255d04 RE |
2691 | break; |
2692 | ||
2693 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2694 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2695 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2696 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2697 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2698 | ||
67255d04 RE |
2699 | break; |
2700 | ||
2701 | default: | |
2702 | internal_error (__FILE__, __LINE__, | |
2703 | "arm_gdbarch_init: bad byte order for float format"); | |
2704 | } | |
2705 | ||
d7b486e7 RE |
2706 | /* On ARM targets char defaults to unsigned. */ |
2707 | set_gdbarch_char_signed (gdbarch, 0); | |
2708 | ||
9df628e0 | 2709 | /* This should be low enough for everything. */ |
97e03143 | 2710 | tdep->lowest_pc = 0x20; |
94c30b78 | 2711 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2712 | |
2dd604e7 | 2713 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2714 | |
756fe439 DJ |
2715 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2716 | ||
148754e5 | 2717 | /* Frame handling. */ |
eb5492fa DJ |
2718 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2719 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2720 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2721 | ||
19772a2c | 2722 | set_gdbarch_deprecated_frameless_function_invocation (gdbarch, arm_frameless_function_invocation); |
eb5492fa DJ |
2723 | |
2724 | frame_base_set_default (gdbarch, &arm_normal_base); | |
148754e5 | 2725 | |
34e8f22d RE |
2726 | /* Address manipulation. */ |
2727 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2728 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2729 | ||
34e8f22d RE |
2730 | /* Advance PC across function entry code. */ |
2731 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2732 | ||
2733 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2734 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2735 | |
2736 | /* The stack grows downward. */ | |
2737 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2738 | ||
2739 | /* Breakpoint manipulation. */ | |
2740 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2741 | |
2742 | /* Information about registers, etc. */ | |
2743 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2744 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2745 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2746 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2747 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
b8b527c5 | 2748 | set_gdbarch_deprecated_register_bytes (gdbarch, |
7a5ea0d4 DJ |
2749 | (NUM_GREGS * INT_REGISTER_SIZE |
2750 | + NUM_FREGS * FP_REGISTER_SIZE | |
b8b527c5 | 2751 | + NUM_SREGS * STATUS_REGISTER_SIZE)); |
34e8f22d | 2752 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2753 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2754 | |
26216b98 AC |
2755 | /* Internal <-> external register number maps. */ |
2756 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2757 | ||
34e8f22d | 2758 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2759 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2760 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2761 | ||
2762 | /* Returning results. */ | |
b508a996 RE |
2763 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2764 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
b5622e8d | 2765 | set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention); |
74055713 | 2766 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); |
34e8f22d RE |
2767 | |
2768 | /* Single stepping. */ | |
2769 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2770 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2771 | ||
03d48a7d RE |
2772 | /* Disassembly. */ |
2773 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2774 | ||
34e8f22d RE |
2775 | /* Minsymbol frobbing. */ |
2776 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2777 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2778 | arm_coff_make_msymbol_special); | |
2779 | ||
97e03143 | 2780 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2781 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2782 | |
eb5492fa DJ |
2783 | /* Add some default predicates. */ |
2784 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); | |
2785 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); | |
2786 | ||
97e03143 RE |
2787 | /* Now we have tuned the configuration, set a few final things, |
2788 | based on what the OS ABI has told us. */ | |
2789 | ||
9df628e0 RE |
2790 | if (tdep->jb_pc >= 0) |
2791 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2792 | ||
08216dd7 RE |
2793 | /* Floating point sizes and format. */ |
2794 | switch (info.byte_order) | |
2795 | { | |
2796 | case BFD_ENDIAN_BIG: | |
2797 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2798 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2799 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2800 | ||
2801 | break; | |
2802 | ||
2803 | case BFD_ENDIAN_LITTLE: | |
2804 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
fd50bc42 | 2805 | arm_set_fp (gdbarch); |
08216dd7 RE |
2806 | break; |
2807 | ||
2808 | default: | |
2809 | internal_error (__FILE__, __LINE__, | |
2810 | "arm_gdbarch_init: bad byte order for float format"); | |
2811 | } | |
2812 | ||
39bbf761 RE |
2813 | return gdbarch; |
2814 | } | |
2815 | ||
97e03143 RE |
2816 | static void |
2817 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2818 | { | |
2819 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2820 | ||
2821 | if (tdep == NULL) | |
2822 | return; | |
2823 | ||
97e03143 RE |
2824 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
2825 | (unsigned long) tdep->lowest_pc); | |
2826 | } | |
2827 | ||
2828 | static void | |
2829 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2830 | struct gdbarch *gdbarch) | |
2831 | { | |
2832 | /* Place-holder. */ | |
2833 | } | |
2834 | ||
2835 | static void | |
2836 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2837 | struct gdbarch *gdbarch) | |
2838 | { | |
2839 | /* Place-holder. */ | |
2840 | } | |
2841 | ||
2842 | static void | |
2843 | arm_init_abi_apcs (struct gdbarch_info info, | |
2844 | struct gdbarch *gdbarch) | |
2845 | { | |
2846 | /* Place-holder. */ | |
2847 | } | |
2848 | ||
a78f21af AC |
2849 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2850 | ||
c906108c | 2851 | void |
ed9a39eb | 2852 | _initialize_arm_tdep (void) |
c906108c | 2853 | { |
bc90b915 FN |
2854 | struct ui_file *stb; |
2855 | long length; | |
26304000 | 2856 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2857 | const char *setname; |
2858 | const char *setdesc; | |
2859 | const char **regnames; | |
bc90b915 FN |
2860 | int numregs, i, j; |
2861 | static char *helptext; | |
085dd6e6 | 2862 | |
42cf1509 | 2863 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2864 | |
70f80edf JT |
2865 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2866 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2867 | bfd_target_elf_flavour, | |
2868 | arm_elf_osabi_sniffer); | |
2869 | ||
97e03143 | 2870 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 2871 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 2872 | arm_init_abi_eabi_v1); |
05816f70 | 2873 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 2874 | arm_init_abi_eabi_v2); |
05816f70 | 2875 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 2876 | arm_init_abi_apcs); |
39bbf761 | 2877 | |
94c30b78 | 2878 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2879 | num_disassembly_options = get_arm_regname_num_options (); |
2880 | ||
2881 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2882 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
2883 | "Various ARM-specific commands.", | |
2884 | &setarmcmdlist, "set arm ", 0, &setlist); | |
2885 | ||
2886 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
2887 | "Various ARM-specific commands.", | |
2888 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 2889 | |
94c30b78 | 2890 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2891 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2892 | |
94c30b78 | 2893 | /* Begin creating the help text. */ |
bc90b915 | 2894 | stb = mem_fileopen (); |
afd7eef0 RE |
2895 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
2896 | "The valid values are:\n"); | |
ed9a39eb | 2897 | |
94c30b78 | 2898 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
afd7eef0 RE |
2899 | valid_disassembly_styles |
2900 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2901 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2902 | { |
2903 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2904 | valid_disassembly_styles[i] = setname; |
bc90b915 FN |
2905 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
2906 | setdesc); | |
94c30b78 | 2907 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2908 | if (!strcmp (setname, "std")) |
2909 | { | |
afd7eef0 | 2910 | disassembly_style = setname; |
bc90b915 FN |
2911 | current_option = i; |
2912 | for (j = 0; j < numregs; j++) | |
2913 | arm_register_names[j] = (char *) regnames[j]; | |
2914 | set_arm_regname_option (i); | |
2915 | } | |
2916 | } | |
94c30b78 | 2917 | /* Mark the end of valid options. */ |
afd7eef0 | 2918 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2919 | |
94c30b78 | 2920 | /* Finish the creation of the help text. */ |
bc90b915 FN |
2921 | fprintf_unfiltered (stb, "The default is \"std\"."); |
2922 | helptext = ui_file_xstrdup (stb, &length); | |
2923 | ui_file_delete (stb); | |
ed9a39eb | 2924 | |
afd7eef0 | 2925 | /* Add the deprecated disassembly-flavor command. */ |
26304000 | 2926 | new_set = add_set_enum_cmd ("disassembly-flavor", no_class, |
afd7eef0 RE |
2927 | valid_disassembly_styles, |
2928 | &disassembly_style, | |
bc90b915 | 2929 | helptext, |
ed9a39eb | 2930 | &setlist); |
26304000 RE |
2931 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
2932 | deprecate_cmd (new_set, "set arm disassembly"); | |
2933 | deprecate_cmd (add_show_from_set (new_set, &showlist), | |
afd7eef0 RE |
2934 | "show arm disassembly"); |
2935 | ||
2936 | /* And now add the new interface. */ | |
30757f90 | 2937 | new_set = add_set_enum_cmd ("disassembler", no_class, |
26304000 RE |
2938 | valid_disassembly_styles, &disassembly_style, |
2939 | helptext, &setarmcmdlist); | |
2940 | ||
fd50bc42 | 2941 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
26304000 RE |
2942 | add_show_from_set (new_set, &showarmcmdlist); |
2943 | ||
2944 | add_setshow_cmd_full ("apcs32", no_class, | |
2945 | var_boolean, (char *) &arm_apcs_32, | |
2946 | "Set usage of ARM 32-bit mode.", | |
2947 | "Show usage of ARM 32-bit mode.", | |
2948 | NULL, NULL, | |
2949 | &setlist, &showlist, &new_set, &new_show); | |
2950 | deprecate_cmd (new_set, "set arm apcs32"); | |
2951 | deprecate_cmd (new_show, "show arm apcs32"); | |
2952 | ||
2953 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2954 | "Set usage of ARM 32-bit mode. " | |
2955 | "When off, a 26-bit PC will be used.", | |
2956 | "Show usage of ARM 32-bit mode. " | |
2957 | "When off, a 26-bit PC will be used.", | |
2958 | NULL, NULL, | |
2959 | &setarmcmdlist, &showarmcmdlist); | |
c906108c | 2960 | |
fd50bc42 RE |
2961 | /* Add a command to allow the user to force the FPU model. */ |
2962 | new_set = add_set_enum_cmd | |
2963 | ("fpu", no_class, fp_model_strings, ¤t_fp_model, | |
2964 | "Set the floating point type.\n" | |
2965 | "auto - Determine the FP typefrom the OS-ABI.\n" | |
2966 | "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" | |
2967 | "fpa - FPA co-processor (GCC compiled).\n" | |
2968 | "softvfp - Software FP with pure-endian doubles.\n" | |
2969 | "vfp - VFP co-processor.", | |
2970 | &setarmcmdlist); | |
2971 | set_cmd_sfunc (new_set, set_fp_model_sfunc); | |
2972 | set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model); | |
2973 | ||
94c30b78 | 2974 | /* Add the deprecated "othernames" command. */ |
afd7eef0 RE |
2975 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
2976 | "Switch to the next set of register names."), | |
2977 | "set arm disassembly"); | |
c3b4394c | 2978 | |
6529d2dd | 2979 | /* Debugging flag. */ |
26304000 RE |
2980 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2981 | "Set ARM debugging. " | |
2982 | "When on, arm-specific debugging is enabled.", | |
2983 | "Show ARM debugging. " | |
2984 | "When on, arm-specific debugging is enabled.", | |
2985 | NULL, NULL, | |
2986 | &setdebuglist, &showdebuglist); | |
c906108c | 2987 | } |