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54af8e6e | 1 | /* Target-dependent code for the Acorn Risc Machine, for GDB, the GNU Debugger. |
e01b4200 | 2 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998 |
72c9954b | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | |
5 | This file is part of GDB. | |
6 | ||
54af8e6e | 7 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 8 | it under the terms of the GNU General Public License as published by |
54af8e6e SC |
9 | the Free Software Foundation; either version 2 of the License, or |
10 | (at your option) any later version. | |
bd5635a1 | 11 | |
54af8e6e | 12 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
54af8e6e | 18 | along with this program; if not, write to the Free Software |
72c9954b | 19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 RP |
20 | |
21 | #include "defs.h" | |
bd5635a1 RP |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
72c9954b | 24 | #include "gdbcmd.h" |
e01b4200 ZR |
25 | #include "gdbcore.h" |
26 | #include "symfile.h" | |
27 | #include "gdb_string.h" | |
28 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
29 | ||
98760eab AC |
30 | /* |
31 | The following macros are actually wrong. Neither arm nor thumb can | |
32 | or should set the lsb on addr. | |
33 | The thumb addresses are mod 2, so (addr & 2) would be a good heuristic | |
34 | to use when checking for thumb (see arm_pc_is_thumb() below). | |
35 | Unfortunately, something else depends on these (incorrect) macros, so | |
36 | fixing them actually breaks gdb. I didn't have time to investigate. Z.R. | |
37 | */ | |
e01b4200 ZR |
38 | /* Thumb function addresses are odd (bit 0 is set). Here are some |
39 | macros to test, set, or clear bit 0 of addresses. */ | |
40 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
41 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
42 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
43 | ||
44 | /* Macros to round N up or down to the next A boundary; A must be | |
45 | a power of two. */ | |
46 | #define ROUND_DOWN(n,a) ((n) & ~((a) - 1)) | |
47 | #define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1)) | |
48 | ||
98760eab AC |
49 | /* Should call_function allocate stack space for a struct return? */ |
50 | /* The system C compiler uses a similar structure return convention to gcc */ | |
51 | int | |
52 | arm_use_struct_convention (gcc_p, type) | |
53 | int gcc_p; | |
54 | struct type *type; | |
55 | { | |
56 | return (TYPE_LENGTH (type) > 4); | |
57 | } | |
58 | ||
72c9954b | 59 | /* Set to true if the 32-bit mode is in use. */ |
bd5635a1 | 60 | |
72c9954b | 61 | int arm_apcs_32 = 1; |
bd5635a1 | 62 | |
e01b4200 ZR |
63 | /* Flag set by arm_fix_call_dummy that tells whether the target function |
64 | is a Thumb function. This flag is checked by arm_push_arguments. | |
65 | FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to | |
66 | pass the function address as an additional parameter. */ | |
67 | ||
68 | static int target_is_thumb; | |
69 | ||
70 | /* Flag set by arm_fix_call_dummy that tells whether the calling function | |
71 | is a Thumb function. This flag is checked by arm_pc_is_thumb | |
72 | and arm_call_dummy_breakpoint_offset. */ | |
73 | ||
74 | static int caller_is_thumb; | |
75 | ||
76 | /* Tell if the program counter value in MEMADDR is in a Thumb function. */ | |
77 | ||
78 | int | |
79 | arm_pc_is_thumb (memaddr) | |
80 | bfd_vma memaddr; | |
81 | { | |
82 | struct minimal_symbol * sym; | |
83 | CORE_ADDR sp; | |
84 | ||
85 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
86 | if (IS_THUMB_ADDR (memaddr)) | |
87 | return 1; | |
88 | ||
89 | /* Thumb function have a "special" bit set in minimal symbols */ | |
90 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
91 | if (sym) | |
92 | { | |
93 | return (MSYMBOL_IS_SPECIAL(sym)); | |
94 | } | |
95 | else | |
96 | return 0; | |
97 | } | |
98 | ||
99 | /* Tell if the program counter value in MEMADDR is in a call dummy that | |
100 | is being called from a Thumb function. */ | |
101 | ||
102 | int | |
103 | arm_pc_is_thumb_dummy (memaddr) | |
104 | bfd_vma memaddr; | |
105 | { | |
106 | CORE_ADDR sp = read_sp(); | |
107 | ||
108 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp+64)) | |
109 | return caller_is_thumb; | |
110 | else | |
111 | return 0; | |
112 | } | |
113 | ||
72c9954b SS |
114 | CORE_ADDR |
115 | arm_addr_bits_remove (val) | |
e01b4200 | 116 | CORE_ADDR val; |
bd5635a1 | 117 | { |
e01b4200 ZR |
118 | if (arm_pc_is_thumb (val)) |
119 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
120 | else | |
121 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
bd5635a1 | 122 | } |
bd5635a1 | 123 | |
72c9954b SS |
124 | CORE_ADDR |
125 | arm_saved_pc_after_call (frame) | |
126 | struct frame_info *frame; | |
bd5635a1 | 127 | { |
72c9954b | 128 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); |
bd5635a1 | 129 | } |
72c9954b | 130 | |
e01b4200 ZR |
131 | /* A typical Thumb prologue looks like this: |
132 | push {r7, lr} | |
133 | add sp, sp, #-28 | |
134 | add r7, sp, #12 | |
135 | Sometimes the latter instruction may be replaced by: | |
136 | mov r7, sp | |
137 | */ | |
138 | ||
139 | static CORE_ADDR | |
140 | thumb_skip_prologue (pc) | |
141 | CORE_ADDR pc; | |
142 | { | |
143 | CORE_ADDR current_pc; | |
144 | ||
145 | for (current_pc = pc; current_pc < pc + 20; current_pc += 2) | |
146 | { | |
147 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
148 | ||
149 | if ( (insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ | |
150 | && (insn & 0xff00) != 0xb000 /* add sp, #simm */ | |
151 | && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ | |
152 | && insn != 0x466f /* mov r7, sp */ | |
153 | && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ | |
154 | break; | |
155 | } | |
156 | ||
157 | return current_pc; | |
158 | } | |
159 | ||
bd5635a1 RP |
160 | /* APCS (ARM procedure call standard) defines the following prologue: |
161 | ||
162 | mov ip, sp | |
163 | [stmfd sp!, {a1,a2,a3,a4}] | |
164 | stmfd sp!, {...,fp,ip,lr,pc} | |
165 | [stfe f7, [sp, #-12]!] | |
166 | [stfe f6, [sp, #-12]!] | |
167 | [stfe f5, [sp, #-12]!] | |
168 | [stfe f4, [sp, #-12]!] | |
169 | sub fp, ip, #nn // nn == 20 or 4 depending on second ins | |
170 | */ | |
171 | ||
172 | CORE_ADDR | |
72c9954b | 173 | arm_skip_prologue (pc) |
e01b4200 | 174 | CORE_ADDR pc; |
bd5635a1 | 175 | { |
72c9954b | 176 | unsigned long inst; |
e01b4200 ZR |
177 | CORE_ADDR skip_pc; |
178 | CORE_ADDR func_addr, func_end; | |
179 | struct symtab_and_line sal; | |
180 | ||
181 | /* See what the symbol table says. */ | |
182 | if (find_pc_partial_function (pc, NULL, & func_addr, & func_end)) | |
183 | { | |
184 | sal = find_pc_line (func_addr, 0); | |
185 | if (sal.line != 0 && sal.end < func_end) | |
186 | return sal.end; | |
187 | } | |
188 | ||
189 | /* Check if this is Thumb code. */ | |
190 | if (arm_pc_is_thumb (pc)) | |
191 | return thumb_skip_prologue (pc); | |
72c9954b | 192 | |
e01b4200 ZR |
193 | /* Can't find the prologue end in the symbol table, try it the hard way |
194 | by disassembling the instructions. */ | |
195 | skip_pc = pc; | |
72c9954b SS |
196 | inst = read_memory_integer (skip_pc, 4); |
197 | if (inst != 0xe1a0c00d) /* mov ip, sp */ | |
198 | return pc; | |
199 | ||
200 | skip_pc += 4; | |
201 | inst = read_memory_integer (skip_pc, 4); | |
202 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ | |
203 | { | |
204 | skip_pc += 4; | |
205 | inst = read_memory_integer (skip_pc, 4); | |
206 | } | |
207 | ||
208 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ | |
209 | return pc; | |
210 | ||
211 | skip_pc += 4; | |
212 | inst = read_memory_integer (skip_pc, 4); | |
213 | ||
214 | /* Any insns after this point may float into the code, if it makes | |
215 | for better instruction scheduling, so we skip them only if | |
216 | we find them, but still consdier the function to be frame-ful */ | |
217 | ||
218 | /* We may have either one sfmfd instruction here, or several stfe insns, | |
219 | depending on the version of floating point code we support. */ | |
220 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
221 | { | |
222 | skip_pc += 4; | |
223 | inst = read_memory_integer (skip_pc, 4); | |
224 | } | |
225 | else | |
226 | { | |
227 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
228 | { | |
229 | skip_pc += 4; | |
230 | inst = read_memory_integer (skip_pc, 4); | |
231 | } | |
232 | } | |
233 | ||
234 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
bd5635a1 | 235 | skip_pc += 4; |
72c9954b SS |
236 | |
237 | return skip_pc; | |
bd5635a1 RP |
238 | } |
239 | ||
e01b4200 ZR |
240 | |
241 | ||
242 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) | |
243 | This function decodes a Thumb function prologue to determine: | |
244 | 1) the size of the stack frame | |
245 | 2) which registers are saved on it | |
246 | 3) the offsets of saved regs | |
247 | 4) the offset from the stack pointer to the frame pointer | |
248 | This information is stored in the "extra" fields of the frame_info. | |
249 | ||
250 | A typical Thumb function prologue might look like this: | |
251 | push {r7, lr} | |
252 | sub sp, #28, | |
253 | add r7, sp, #12 | |
254 | Which would create this stack frame (offsets relative to FP) | |
255 | old SP -> 24 stack parameters | |
256 | 20 LR | |
257 | 16 R7 | |
258 | R7 -> 0 local variables (16 bytes) | |
259 | SP -> -12 additional stack space (12 bytes) | |
260 | The frame size would thus be 36 bytes, and the frame offset would be | |
261 | 12 bytes. The frame register is R7. */ | |
262 | ||
263 | static void | |
264 | thumb_scan_prologue (fi) | |
265 | struct frame_info * fi; | |
54af8e6e | 266 | { |
e01b4200 ZR |
267 | CORE_ADDR prologue_start; |
268 | CORE_ADDR prologue_end; | |
269 | CORE_ADDR current_pc; | |
270 | int saved_reg[16]; /* which register has been copied to register n? */ | |
271 | int i; | |
54af8e6e | 272 | |
e01b4200 | 273 | if (find_pc_partial_function (fi->pc, NULL, & prologue_start, & prologue_end)) |
54af8e6e | 274 | { |
e01b4200 ZR |
275 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
276 | ||
277 | if (sal.line == 0) /* no line info, use current PC */ | |
278 | prologue_end = fi->pc; | |
279 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
280 | prologue_end = sal.end; /* (probably means no prologue) */ | |
54af8e6e | 281 | } |
e01b4200 ZR |
282 | else |
283 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ | |
284 | /* 16 pushes, an add, and "mv fp,sp" */ | |
285 | ||
286 | prologue_end = min (prologue_end, fi->pc); | |
287 | ||
288 | /* Initialize the saved register map. When register H is copied to | |
289 | register L, we will put H in saved_reg[L]. */ | |
290 | for (i = 0; i < 16; i++) | |
291 | saved_reg[i] = i; | |
292 | ||
293 | /* Search the prologue looking for instructions that set up the | |
294 | frame pointer, adjust the stack pointer, and save registers. */ | |
295 | ||
296 | fi->framesize = 0; | |
297 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 2) | |
54af8e6e | 298 | { |
e01b4200 ZR |
299 | unsigned short insn; |
300 | int regno; | |
301 | int offset; | |
302 | ||
303 | insn = read_memory_unsigned_integer (current_pc, 2); | |
304 | ||
305 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ | |
306 | { | |
307 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
308 | whether to save LR (R14). */ | |
309 | int mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
310 | ||
311 | /* Calculate offsets of saved R0-R7 and LR. */ | |
312 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
313 | if (mask & (1 << regno)) | |
314 | { | |
315 | fi->framesize += 4; | |
316 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); | |
317 | saved_reg[regno] = regno; /* reset saved register map */ | |
318 | } | |
319 | } | |
320 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm */ | |
321 | { | |
322 | offset = (insn & 0x7f) << 2; /* get scaled offset */ | |
323 | if (insn & 0x80) /* is it signed? */ | |
324 | offset = -offset; | |
325 | fi->framesize -= offset; | |
326 | } | |
327 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
328 | { | |
329 | fi->framereg = THUMB_FP_REGNUM; | |
330 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ | |
331 | } | |
332 | else if (insn == 0x466f) /* mov r7, sp */ | |
333 | { | |
334 | fi->framereg = THUMB_FP_REGNUM; | |
335 | fi->frameoffset = 0; | |
336 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; | |
337 | } | |
338 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
339 | { | |
340 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ | |
341 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ | |
342 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ | |
343 | } | |
344 | else | |
345 | break; /* anything else isn't prologue */ | |
54af8e6e | 346 | } |
e01b4200 ZR |
347 | } |
348 | ||
349 | /* Function: check_prologue_cache | |
350 | Check if prologue for this frame's PC has already been scanned. | |
351 | If it has, copy the relevant information about that prologue and | |
352 | return non-zero. Otherwise do not copy anything and return zero. | |
353 | ||
354 | The information saved in the cache includes: | |
355 | * the frame register number; | |
356 | * the size of the stack frame; | |
357 | * the offsets of saved regs (relative to the old SP); and | |
358 | * the offset from the stack pointer to the frame pointer | |
359 | ||
360 | The cache contains only one entry, since this is adequate | |
361 | for the typical sequence of prologue scan requests we get. | |
362 | When performing a backtrace, GDB will usually ask to scan | |
363 | the same function twice in a row (once to get the frame chain, | |
364 | and once to fill in the extra frame information). | |
365 | */ | |
366 | ||
367 | static struct frame_info prologue_cache; | |
368 | ||
369 | static int | |
370 | check_prologue_cache (fi) | |
371 | struct frame_info * fi; | |
372 | { | |
373 | int i; | |
374 | ||
375 | if (fi->pc == prologue_cache.pc) | |
54af8e6e | 376 | { |
e01b4200 ZR |
377 | fi->framereg = prologue_cache.framereg; |
378 | fi->framesize = prologue_cache.framesize; | |
379 | fi->frameoffset = prologue_cache.frameoffset; | |
380 | for (i = 0; i <= NUM_REGS; i++) | |
381 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; | |
382 | return 1; | |
54af8e6e | 383 | } |
e01b4200 ZR |
384 | else |
385 | return 0; | |
386 | } | |
387 | ||
388 | ||
389 | /* Function: save_prologue_cache | |
390 | Copy the prologue information from fi to the prologue cache. | |
391 | */ | |
392 | ||
393 | static void | |
394 | save_prologue_cache (fi) | |
395 | struct frame_info * fi; | |
396 | { | |
397 | int i; | |
398 | ||
399 | prologue_cache.pc = fi->pc; | |
400 | prologue_cache.framereg = fi->framereg; | |
401 | prologue_cache.framesize = fi->framesize; | |
402 | prologue_cache.frameoffset = fi->frameoffset; | |
403 | ||
404 | for (i = 0; i <= NUM_REGS; i++) | |
405 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; | |
406 | } | |
407 | ||
408 | ||
409 | /* Function: arm_scan_prologue | |
410 | This function decodes an ARM function prologue to determine: | |
411 | 1) the size of the stack frame | |
412 | 2) which registers are saved on it | |
413 | 3) the offsets of saved regs | |
414 | 4) the offset from the stack pointer to the frame pointer | |
415 | This information is stored in the "extra" fields of the frame_info. | |
416 | ||
417 | A typical Arm function prologue might look like this: | |
418 | mov ip, sp | |
419 | stmfd sp!, {fp, ip, lr, pc} | |
420 | sub fp, ip, #4 | |
421 | sub sp, sp, #16 | |
422 | Which would create this stack frame (offsets relative to FP): | |
423 | IP -> 4 (caller's stack) | |
424 | FP -> 0 PC (points to address of stmfd instruction + 12 in callee) | |
425 | -4 LR (return address in caller) | |
426 | -8 IP (copy of caller's SP) | |
427 | -12 FP (caller's FP) | |
428 | SP -> -28 Local variables | |
429 | The frame size would thus be 32 bytes, and the frame offset would be | |
430 | 28 bytes. */ | |
431 | ||
432 | static void | |
433 | arm_scan_prologue (fi) | |
434 | struct frame_info * fi; | |
435 | { | |
436 | int regno, sp_offset, fp_offset; | |
437 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
438 | ||
439 | /* Check if this function is already in the cache of frame information. */ | |
440 | if (check_prologue_cache (fi)) | |
441 | return; | |
442 | ||
443 | /* Assume there is no frame until proven otherwise. */ | |
444 | fi->framereg = SP_REGNUM; | |
445 | fi->framesize = 0; | |
446 | fi->frameoffset = 0; | |
447 | ||
448 | /* Check for Thumb prologue. */ | |
449 | if (arm_pc_is_thumb (fi->pc)) | |
450 | { | |
451 | thumb_scan_prologue (fi); | |
452 | save_prologue_cache (fi); | |
453 | return; | |
454 | } | |
455 | ||
456 | /* Find the function prologue. If we can't find the function in | |
457 | the symbol table, peek in the stack frame to find the PC. */ | |
458 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
459 | { | |
460 | /* Assume the prologue is everything between the first instruction | |
461 | in the function and the first source line. */ | |
462 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
463 | ||
464 | if (sal.line == 0) /* no line info, use current PC */ | |
465 | prologue_end = fi->pc; | |
466 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
467 | prologue_end = sal.end; /* (probably means no prologue) */ | |
468 | } | |
469 | else | |
470 | { | |
471 | /* Get address of the stmfd in the prologue of the callee; the saved | |
472 | PC is the address of the stmfd + 12. */ | |
473 | prologue_start = (read_memory_integer (fi->frame, 4) & 0x03fffffc) - 12; | |
474 | prologue_end = prologue_start + 40; /* FIXME: should be big enough */ | |
475 | } | |
476 | ||
477 | /* Now search the prologue looking for instructions that set up the | |
478 | frame pointer, adjust the stack pointer, and save registers. */ | |
479 | ||
480 | sp_offset = fp_offset = 0; | |
481 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 4) | |
482 | { | |
483 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); | |
484 | ||
485 | if ((insn & 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., r7, lr} */ | |
486 | { | |
487 | int mask = insn & 0xffff; | |
488 | ||
489 | /* Calculate offsets of saved registers. */ | |
490 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
491 | if (mask & (1 << regno)) | |
492 | { | |
493 | sp_offset -= 4; | |
494 | fi->fsr.regs[regno] = sp_offset; | |
495 | } | |
496 | } | |
497 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
498 | { | |
499 | unsigned imm = insn & 0xff; /* immediate value */ | |
500 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
501 | imm = (imm >> rot) | (imm << (32-rot)); | |
502 | fp_offset = -imm; | |
503 | fi->framereg = FP_REGNUM; | |
504 | } | |
505 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
506 | { | |
507 | unsigned imm = insn & 0xff; /* immediate value */ | |
508 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
509 | imm = (imm >> rot) | (imm << (32-rot)); | |
510 | sp_offset -= imm; | |
511 | } | |
512 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
513 | { | |
514 | sp_offset -= 12; | |
515 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
516 | fi->fsr.regs[regno] = sp_offset; | |
517 | } | |
518 | else if (insn == 0xe1a0c00d) /* mov ip, sp */ | |
519 | continue; | |
520 | else | |
521 | break; /* not a recognized prologue instruction */ | |
522 | } | |
523 | ||
524 | /* The frame size is just the negative of the offset (from the original SP) | |
525 | of the last thing thing we pushed on the stack. The frame offset is | |
526 | [new FP] - [new SP]. */ | |
527 | fi->framesize = -sp_offset; | |
528 | fi->frameoffset = fp_offset - sp_offset; | |
529 | ||
530 | save_prologue_cache (fi); | |
531 | } | |
532 | ||
533 | ||
534 | /* Function: find_callers_reg | |
535 | Find REGNUM on the stack. Otherwise, it's in an active register. One thing | |
536 | we might want to do here is to check REGNUM against the clobber mask, and | |
537 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
538 | would provide a graceful failure mode when trying to get the value of | |
539 | caller-saves registers for an inner frame. */ | |
540 | ||
541 | static CORE_ADDR | |
542 | arm_find_callers_reg (fi, regnum) | |
543 | struct frame_info * fi; | |
544 | int regnum; | |
545 | { | |
546 | for (; fi; fi = fi->next) | |
547 | ||
548 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
549 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
550 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
551 | else | |
552 | #endif | |
553 | if (fi->fsr.regs[regnum] != 0) | |
554 | return read_memory_integer (fi->fsr.regs[regnum], | |
555 | REGISTER_RAW_SIZE(regnum)); | |
556 | return read_register (regnum); | |
557 | } | |
558 | ||
559 | ||
560 | /* Function: frame_chain | |
561 | Given a GDB frame, determine the address of the calling function's frame. | |
562 | This will be used to create a new GDB frame struct, and then | |
563 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
564 | For ARM, we save the frame size when we initialize the frame_info. | |
565 | ||
566 | The original definition of this function was a macro in tm-arm.h: | |
567 | { In the case of the ARM, the frame's nominal address is the FP value, | |
568 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
569 | ||
570 | #define FRAME_CHAIN(thisframe) \ | |
571 | ((thisframe)->pc >= LOWEST_PC ? \ | |
572 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
573 | 0) | |
574 | */ | |
575 | ||
576 | CORE_ADDR | |
577 | arm_frame_chain (fi) | |
578 | struct frame_info * fi; | |
579 | { | |
580 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
581 | CORE_ADDR fn_start, callers_pc, fp; | |
582 | ||
583 | /* is this a dummy frame? */ | |
584 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
585 | return fi->frame; /* dummy frame same as caller's frame */ | |
586 | ||
587 | /* is caller-of-this a dummy frame? */ | |
588 | callers_pc = FRAME_SAVED_PC(fi); /* find out who called us: */ | |
589 | fp = arm_find_callers_reg (fi, FP_REGNUM); | |
590 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) | |
591 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
592 | ||
593 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
594 | if (fn_start == entry_point_address ()) | |
595 | return 0; /* in _start fn, don't chain further */ | |
596 | #endif | |
597 | CORE_ADDR caller_pc, fn_start; | |
598 | struct frame_info caller_fi; | |
599 | int framereg = fi->framereg; | |
600 | ||
601 | if (fi->pc < LOWEST_PC) | |
602 | return 0; | |
603 | ||
604 | /* If the caller is the startup code, we're at the end of the chain. */ | |
605 | caller_pc = FRAME_SAVED_PC (fi); | |
606 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
607 | if (fn_start == entry_point_address ()) | |
608 | return 0; | |
609 | ||
610 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
611 | the frame register of the caller is different from ours. | |
612 | So we must scan the prologue of the caller to determine its | |
613 | frame register number. */ | |
614 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) | |
54af8e6e | 615 | { |
e01b4200 ZR |
616 | memset (& caller_fi, 0, sizeof (caller_fi)); |
617 | caller_fi.pc = caller_pc; | |
618 | arm_scan_prologue (& caller_fi); | |
619 | framereg = caller_fi.framereg; | |
54af8e6e | 620 | } |
e01b4200 ZR |
621 | |
622 | /* If the caller used a frame register, return its value. | |
623 | Otherwise, return the caller's stack pointer. */ | |
624 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
625 | return arm_find_callers_reg (fi, framereg); | |
626 | else | |
627 | return fi->frame + fi->framesize; | |
54af8e6e SC |
628 | } |
629 | ||
e01b4200 ZR |
630 | /* Function: init_extra_frame_info |
631 | This function actually figures out the frame address for a given pc and | |
632 | sp. This is tricky because we sometimes don't use an explicit | |
633 | frame pointer, and the previous stack pointer isn't necessarily recorded | |
634 | on the stack. The only reliable way to get this info is to | |
635 | examine the prologue. */ | |
636 | ||
72c9954b | 637 | void |
e01b4200 ZR |
638 | arm_init_extra_frame_info (fi) |
639 | struct frame_info * fi; | |
72c9954b | 640 | { |
e01b4200 ZR |
641 | int reg; |
642 | ||
643 | if (fi->next) | |
644 | fi->pc = FRAME_SAVED_PC (fi->next); | |
645 | ||
646 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); | |
647 | ||
648 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
649 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
650 | { | |
651 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
652 | by assuming it's always FP. */ | |
653 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
654 | fi->framesize = 0; | |
655 | fi->frameoffset = 0; | |
656 | return; | |
657 | } | |
658 | else | |
659 | #endif | |
660 | { | |
661 | arm_scan_prologue (fi); | |
662 | ||
663 | if (!fi->next) /* this is the innermost frame? */ | |
664 | fi->frame = read_register (fi->framereg); | |
665 | else /* not the innermost frame */ | |
666 | /* If we have an FP, the callee saved it. */ | |
667 | if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) | |
668 | if (fi->next->fsr.regs[fi->framereg] != 0) | |
669 | fi->frame = read_memory_integer (fi->next->fsr.regs[fi->framereg], | |
670 | 4); | |
671 | ||
672 | /* Calculate actual addresses of saved registers using offsets determined | |
673 | by arm_scan_prologue. */ | |
674 | for (reg = 0; reg < NUM_REGS; reg++) | |
675 | if (fi->fsr.regs[reg] != 0) | |
676 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; | |
677 | } | |
678 | } | |
679 | ||
680 | ||
681 | /* Function: frame_saved_pc | |
682 | Find the caller of this frame. We do this by seeing if LR_REGNUM is saved | |
683 | in the stack anywhere, otherwise we get it from the registers. | |
72c9954b | 684 | |
e01b4200 ZR |
685 | The old definition of this function was a macro: |
686 | #define FRAME_SAVED_PC(FRAME) \ | |
687 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) | |
688 | */ | |
689 | ||
690 | CORE_ADDR | |
691 | arm_frame_saved_pc (fi) | |
692 | struct frame_info * fi; | |
693 | { | |
694 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
695 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
696 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
697 | else | |
698 | #endif | |
699 | { | |
700 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
701 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
702 | } | |
703 | } | |
704 | ||
705 | ||
706 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. | |
707 | Examine the Program Status Register to decide which state we're in. */ | |
708 | ||
709 | CORE_ADDR | |
710 | arm_target_read_fp () | |
711 | { | |
712 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
713 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
714 | else | |
715 | return read_register (FP_REGNUM); /* R11 if ARM */ | |
716 | } | |
717 | ||
718 | ||
719 | /* Calculate the frame offsets of the saved registers (ARM version). */ | |
720 | void | |
721 | arm_frame_find_saved_regs (fi, regaddr) | |
722 | struct frame_info *fi; | |
723 | struct frame_saved_regs *regaddr; | |
724 | { | |
725 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); | |
726 | } | |
727 | ||
728 | ||
729 | void | |
730 | arm_push_dummy_frame () | |
731 | { | |
732 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
733 | CORE_ADDR sp = old_sp; | |
734 | CORE_ADDR fp, prologue_start; | |
735 | int regnum; | |
736 | ||
737 | /* Push the two dummy prologue instructions in reverse order, | |
738 | so that they'll be in the correct low-to-high order in memory. */ | |
739 | /* sub fp, ip, #4 */ | |
740 | sp = push_word (sp, 0xe24cb004); | |
741 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
742 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
743 | ||
744 | /* push a pointer to the dummy prologue + 12, because when | |
745 | stm instruction stores the PC, it stores the address of the stm | |
746 | instruction itself plus 12. */ | |
747 | fp = sp = push_word (sp, prologue_start + 12); | |
748 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ | |
749 | sp = push_word (sp, old_sp); | |
72c9954b | 750 | sp = push_word (sp, read_register (FP_REGNUM)); |
e01b4200 ZR |
751 | |
752 | for (regnum = 10; regnum >= 0; regnum --) | |
72c9954b | 753 | sp = push_word (sp, read_register (regnum)); |
e01b4200 ZR |
754 | |
755 | write_register (FP_REGNUM, fp); | |
756 | write_register (THUMB_FP_REGNUM, fp); | |
72c9954b SS |
757 | write_register (SP_REGNUM, sp); |
758 | } | |
759 | ||
e01b4200 ZR |
760 | /* Fix up the call dummy, based on whether the processor is currently |
761 | in Thumb or ARM mode, and whether the target function is Thumb | |
762 | or ARM. There are three different situations requiring three | |
763 | different dummies: | |
764 | ||
765 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
766 | been copied into the dummy parameter to this function. | |
767 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the | |
768 | "mov pc,r4" instruction patched to be a "bx r4" instead. | |
769 | * Thumb calling anything: uses the Thumb dummy defined below, which | |
770 | works for calling both ARM and Thumb functions. | |
771 | ||
772 | All three call dummies expect to receive the target function address | |
773 | in R4, with the low bit set if it's a Thumb function. | |
774 | */ | |
775 | ||
72c9954b | 776 | void |
e01b4200 ZR |
777 | arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) |
778 | char * dummy; | |
779 | CORE_ADDR pc; | |
780 | CORE_ADDR fun; | |
781 | int nargs; | |
782 | value_ptr * args; | |
783 | struct type * type; | |
784 | int gcc_p; | |
72c9954b | 785 | { |
e01b4200 ZR |
786 | static short thumb_dummy[4] = |
787 | { | |
788 | 0xf000, 0xf801, /* bl label */ | |
789 | 0xdf18, /* swi 24 */ | |
790 | 0x4720, /* label: bx r4 */ | |
791 | }; | |
792 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
793 | ||
794 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
795 | caller_is_thumb = arm_pc_is_thumb (read_pc()); | |
796 | ||
797 | /* If the target function is Thumb, set the low bit of the function address. | |
798 | And if the CPU is currently in ARM mode, patch the second instruction | |
799 | of call dummy to use a BX instruction to switch to Thumb mode. */ | |
800 | target_is_thumb = arm_pc_is_thumb (fun); | |
801 | if (target_is_thumb) | |
802 | { | |
803 | fun |= 1; | |
804 | if (!caller_is_thumb) | |
805 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
806 | } | |
72c9954b | 807 | |
e01b4200 ZR |
808 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy |
809 | instead of the ARM one that's already been copied. This will | |
810 | work for both Thumb and ARM target functions. */ | |
811 | if (caller_is_thumb) | |
72c9954b | 812 | { |
e01b4200 ZR |
813 | int i; |
814 | char *p = dummy; | |
815 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
816 | ||
817 | for (i = 0; i < len; i++) | |
72c9954b | 818 | { |
e01b4200 ZR |
819 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); |
820 | p += sizeof (thumb_dummy[0]); | |
821 | } | |
822 | } | |
823 | ||
824 | /* Put the target address in r4; the call dummy will copy this to the PC. */ | |
825 | write_register (4, fun); | |
826 | } | |
827 | ||
828 | ||
829 | /* Return the offset in the call dummy of the instruction that needs | |
830 | to have a breakpoint placed on it. This is the offset of the 'swi 24' | |
831 | instruction, which is no longer actually used, but simply acts | |
832 | as a place-holder now. | |
833 | ||
834 | This implements the CALL_DUMMY_BREAK_OFFSET macro. | |
835 | */ | |
836 | ||
837 | int | |
838 | arm_call_dummy_breakpoint_offset () | |
839 | { | |
840 | if (caller_is_thumb) | |
841 | return 4; | |
842 | else | |
843 | return 8; | |
844 | } | |
845 | ||
846 | ||
847 | CORE_ADDR | |
848 | arm_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
849 | int nargs; | |
850 | value_ptr * args; | |
851 | CORE_ADDR sp; | |
852 | int struct_return; | |
853 | CORE_ADDR struct_addr; | |
854 | { | |
855 | int argreg; | |
856 | int float_argreg; | |
857 | int argnum; | |
858 | int stack_offset; | |
98760eab AC |
859 | struct stack_arg { |
860 | char *val; | |
861 | int len; | |
862 | int offset; | |
863 | }; | |
864 | struct stack_arg *stack_args = | |
865 | (struct stack_arg*)alloca (nargs * sizeof (struct stack_arg)); | |
866 | int nstack_args = 0; | |
867 | ||
e01b4200 ZR |
868 | |
869 | /* Initialize the integer and float register pointers. */ | |
870 | argreg = A1_REGNUM; | |
871 | float_argreg = F0_REGNUM; | |
872 | ||
873 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
874 | if (struct_return) | |
875 | write_register (argreg++, struct_addr); | |
876 | ||
877 | /* The offset onto the stack at which we will start copying parameters | |
878 | (after the registers are used up) begins at 16 in the old ABI. | |
879 | This leaves room for the "home" area for register parameters. */ | |
880 | stack_offset = REGISTER_SIZE * 4; | |
881 | ||
98760eab AC |
882 | /* Process args from left to right. Store as many as allowed in |
883 | registers, save the rest to be pushed on the stack */ | |
884 | for(argnum = 0; argnum < nargs; argnum++) | |
e01b4200 ZR |
885 | { |
886 | char * val; | |
887 | value_ptr arg = args[argnum]; | |
888 | struct type * arg_type = check_typedef (VALUE_TYPE (arg)); | |
889 | struct type * target_type = TYPE_TARGET_TYPE (arg_type); | |
890 | int len = TYPE_LENGTH (arg_type); | |
891 | enum type_code typecode = TYPE_CODE (arg_type); | |
892 | CORE_ADDR regval; | |
98760eab | 893 | int newarg; |
e01b4200 ZR |
894 | |
895 | val = (char *) VALUE_CONTENTS (arg); | |
896 | ||
897 | /* If the argument is a pointer to a function, and it's a Thumb | |
898 | function, set the low bit of the pointer. */ | |
899 | if (typecode == TYPE_CODE_PTR | |
900 | && target_type != NULL | |
901 | && TYPE_CODE (target_type) == TYPE_CODE_FUNC) | |
902 | { | |
903 | regval = extract_address (val, len); | |
904 | if (arm_pc_is_thumb (regval)) | |
905 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
906 | } | |
907 | ||
908 | #define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */ | |
909 | #if MAPCS_FLOAT | |
910 | /* Up to four floating point arguments can be passed in floating | |
911 | point registers on ARM (not on Thumb). */ | |
912 | if (typecode == TYPE_CODE_FLT | |
913 | && float_argreg <= ARM_LAST_FP_ARG_REGNUM | |
914 | && !target_is_thumb) | |
915 | { | |
916 | /* This is a floating point value that fits entirely | |
917 | in a single register. */ | |
918 | regval = extract_address (val, len); | |
919 | write_register (float_argreg++, regval); | |
920 | } | |
921 | else | |
922 | #endif | |
923 | { | |
924 | /* Copy the argument to general registers or the stack in | |
925 | register-sized pieces. Large arguments are split between | |
926 | registers and stack. */ | |
927 | while (len > 0) | |
928 | { | |
e01b4200 ZR |
929 | if (argreg <= ARM_LAST_ARG_REGNUM) |
930 | { | |
98760eab | 931 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
e01b4200 ZR |
932 | regval = extract_address (val, partial_len); |
933 | ||
934 | /* It's a simple argument being passed in a general | |
935 | register. */ | |
936 | write_register (argreg, regval); | |
937 | argreg++; | |
98760eab AC |
938 | len -= partial_len; |
939 | val += partial_len; | |
e01b4200 ZR |
940 | } |
941 | else | |
942 | { | |
98760eab AC |
943 | /* keep for later pushing */ |
944 | stack_args[nstack_args].val = val; | |
945 | stack_args[nstack_args++].len = len; | |
946 | break; | |
e01b4200 | 947 | } |
e01b4200 | 948 | } |
72c9954b SS |
949 | } |
950 | } | |
98760eab AC |
951 | /* now do the real stack pushing, process args right to left */ |
952 | while(nstack_args--) | |
953 | { | |
954 | sp -= stack_args[nstack_args].len; | |
955 | write_memory(sp, stack_args[nstack_args].val, | |
956 | stack_args[nstack_args].len); | |
957 | } | |
e01b4200 ZR |
958 | |
959 | /* Return adjusted stack pointer. */ | |
960 | return sp; | |
961 | } | |
962 | ||
963 | void | |
964 | arm_pop_frame () | |
965 | { | |
966 | struct frame_info *frame = get_current_frame(); | |
967 | int regnum; | |
968 | ||
969 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
970 | if (frame->fsr.regs[regnum] != 0) | |
971 | write_register (regnum, | |
972 | read_memory_integer (frame->fsr.regs[regnum], 4)); | |
973 | ||
974 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); | |
975 | write_register (SP_REGNUM, read_register (frame->framereg)); | |
976 | ||
72c9954b SS |
977 | flush_cached_frames (); |
978 | } | |
979 | ||
bd5635a1 | 980 | static void |
72c9954b | 981 | print_fpu_flags (flags) |
e01b4200 | 982 | int flags; |
bd5635a1 | 983 | { |
72c9954b SS |
984 | if (flags & (1 << 0)) fputs ("IVO ", stdout); |
985 | if (flags & (1 << 1)) fputs ("DVZ ", stdout); | |
986 | if (flags & (1 << 2)) fputs ("OFL ", stdout); | |
987 | if (flags & (1 << 3)) fputs ("UFL ", stdout); | |
988 | if (flags & (1 << 4)) fputs ("INX ", stdout); | |
989 | putchar ('\n'); | |
bd5635a1 RP |
990 | } |
991 | ||
992 | void | |
72c9954b | 993 | arm_float_info () |
bd5635a1 | 994 | { |
72c9954b | 995 | register unsigned long status = read_register (FPS_REGNUM); |
bd5635a1 RP |
996 | int type; |
997 | ||
998 | type = (status >> 24) & 127; | |
72c9954b SS |
999 | printf ("%s FPU type %d\n", |
1000 | (status & (1<<31)) ? "Hardware" : "Software", | |
1001 | type); | |
1002 | fputs ("mask: ", stdout); | |
1003 | print_fpu_flags (status >> 16); | |
1004 | fputs ("flags: ", stdout); | |
1005 | print_fpu_flags (status); | |
bd5635a1 | 1006 | } |
54af8e6e | 1007 | |
72c9954b SS |
1008 | static void |
1009 | arm_othernames () | |
54af8e6e | 1010 | { |
72c9954b SS |
1011 | static int toggle; |
1012 | static char *original[] = ORIGINAL_REGISTER_NAMES; | |
1013 | static char *extra_crispy[] = ADDITIONAL_REGISTER_NAMES; | |
54af8e6e | 1014 | |
72c9954b SS |
1015 | memcpy (reg_names, toggle ? extra_crispy : original, sizeof(original)); |
1016 | toggle = !toggle; | |
1017 | } | |
54af8e6e SC |
1018 | |
1019 | /* FIXME: Fill in with the 'right thing', see asm | |
1020 | template in arm-convert.s */ | |
1021 | ||
1022 | void | |
1023 | convert_from_extended (ptr, dbl) | |
e01b4200 ZR |
1024 | void * ptr; |
1025 | double * dbl; | |
54af8e6e SC |
1026 | { |
1027 | *dbl = *(double*)ptr; | |
1028 | } | |
1029 | ||
54af8e6e SC |
1030 | void |
1031 | convert_to_extended (dbl, ptr) | |
e01b4200 ZR |
1032 | void * ptr; |
1033 | double * dbl; | |
54af8e6e SC |
1034 | { |
1035 | *(double*)ptr = *dbl; | |
1036 | } | |
1037 | ||
e01b4200 ZR |
1038 | static int |
1039 | condition_true (cond, status_reg) | |
1040 | unsigned long cond; | |
1041 | unsigned long status_reg; | |
72c9954b | 1042 | { |
72c9954b | 1043 | if (cond == INST_AL || cond == INST_NV) |
e01b4200 | 1044 | return 1; |
72c9954b SS |
1045 | |
1046 | switch (cond) | |
1047 | { | |
1048 | case INST_EQ: | |
72c9954b | 1049 | return ((status_reg & FLAG_Z) != 0); |
e01b4200 ZR |
1050 | case INST_NE: |
1051 | return ((status_reg & FLAG_Z) == 0); | |
72c9954b | 1052 | case INST_CS: |
72c9954b | 1053 | return ((status_reg & FLAG_C) != 0); |
e01b4200 ZR |
1054 | case INST_CC: |
1055 | return ((status_reg & FLAG_C) == 0); | |
72c9954b | 1056 | case INST_MI: |
72c9954b | 1057 | return ((status_reg & FLAG_N) != 0); |
e01b4200 ZR |
1058 | case INST_PL: |
1059 | return ((status_reg & FLAG_N) == 0); | |
72c9954b | 1060 | case INST_VS: |
72c9954b | 1061 | return ((status_reg & FLAG_V) != 0); |
e01b4200 ZR |
1062 | case INST_VC: |
1063 | return ((status_reg & FLAG_V) == 0); | |
72c9954b | 1064 | case INST_HI: |
e01b4200 | 1065 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
72c9954b | 1066 | case INST_LS: |
e01b4200 | 1067 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
72c9954b | 1068 | case INST_GE: |
72c9954b | 1069 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
e01b4200 ZR |
1070 | case INST_LT: |
1071 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
72c9954b | 1072 | case INST_GT: |
72c9954b SS |
1073 | return (((status_reg & FLAG_Z) == 0) && |
1074 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); | |
e01b4200 ZR |
1075 | case INST_LE: |
1076 | return (((status_reg & FLAG_Z) != 0) || | |
1077 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); | |
72c9954b | 1078 | } |
e01b4200 | 1079 | return 1; |
72c9954b SS |
1080 | } |
1081 | ||
1082 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
e01b4200 ZR |
1083 | #define bit(obj,st) (((obj) >> (st)) & 1) |
1084 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
72c9954b SS |
1085 | #define sbits(obj,st,fn) \ |
1086 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1087 | #define BranchDest(addr,instr) \ | |
1088 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1089 | #define ARM_PC_32 1 | |
1090 | ||
1091 | static unsigned long | |
e01b4200 | 1092 | shifted_reg_val (inst, carry, pc_val, status_reg) |
72c9954b SS |
1093 | unsigned long inst; |
1094 | int carry; | |
1095 | unsigned long pc_val; | |
e01b4200 | 1096 | unsigned long status_reg; |
72c9954b SS |
1097 | { |
1098 | unsigned long res, shift; | |
1099 | int rm = bits (inst, 0, 3); | |
1100 | unsigned long shifttype = bits (inst, 5, 6); | |
1101 | ||
1102 | if (bit(inst, 4)) | |
1103 | { | |
1104 | int rs = bits (inst, 8, 11); | |
1105 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1106 | } | |
1107 | else | |
1108 | shift = bits (inst, 7, 11); | |
1109 | ||
1110 | res = (rm == 15 | |
e01b4200 | 1111 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
72c9954b SS |
1112 | + (bit (inst, 4) ? 12 : 8)) |
1113 | : read_register (rm)); | |
1114 | ||
1115 | switch (shifttype) | |
1116 | { | |
1117 | case 0: /* LSL */ | |
1118 | res = shift >= 32 ? 0 : res << shift; | |
1119 | break; | |
1120 | ||
1121 | case 1: /* LSR */ | |
1122 | res = shift >= 32 ? 0 : res >> shift; | |
1123 | break; | |
1124 | ||
1125 | case 2: /* ASR */ | |
1126 | if (shift >= 32) shift = 31; | |
1127 | res = ((res & 0x80000000L) | |
1128 | ? ~((~res) >> shift) : res >> shift); | |
1129 | break; | |
1130 | ||
1131 | case 3: /* ROR/RRX */ | |
1132 | shift &= 31; | |
1133 | if (shift == 0) | |
1134 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1135 | else | |
1136 | res = (res >> shift) | (res << (32-shift)); | |
1137 | break; | |
1138 | } | |
1139 | ||
1140 | return res & 0xffffffff; | |
1141 | } | |
1142 | ||
1143 | ||
e01b4200 ZR |
1144 | /* Return number of 1-bits in VAL. */ |
1145 | ||
1146 | static int | |
1147 | bitcount (val) | |
1148 | unsigned long val; | |
1149 | { | |
1150 | int nbits; | |
1151 | for (nbits = 0; val != 0; nbits++) | |
1152 | val &= val - 1; /* delete rightmost 1-bit in val */ | |
1153 | return nbits; | |
1154 | } | |
1155 | ||
1156 | ||
1157 | static CORE_ADDR | |
1158 | thumb_get_next_pc (pc) | |
1159 | CORE_ADDR pc; | |
1160 | { | |
1161 | unsigned long pc_val = ((unsigned long)pc) + 4; /* PC after prefetch */ | |
1162 | unsigned short inst1 = read_memory_integer (pc, 2); | |
1163 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ | |
1164 | unsigned long offset; | |
1165 | ||
1166 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1167 | { | |
1168 | CORE_ADDR sp; | |
1169 | ||
1170 | /* Fetch the saved PC from the stack. It's stored above | |
1171 | all of the other registers. */ | |
1172 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1173 | sp = read_register (SP_REGNUM); | |
1174 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1175 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1176 | if (nextpc == pc) | |
1177 | error ("Infinite loop detected"); | |
1178 | } | |
1179 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1180 | { | |
1181 | unsigned long status = read_register (PS_REGNUM); | |
1182 | unsigned long cond = bits (inst1, 8, 11); | |
1183 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ | |
1184 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1185 | } | |
1186 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1187 | { | |
1188 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1189 | } | |
1190 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1191 | { | |
1192 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
1193 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); | |
1194 | nextpc = pc_val + offset; | |
1195 | } | |
1196 | ||
1197 | return nextpc; | |
1198 | } | |
1199 | ||
1200 | ||
72c9954b SS |
1201 | CORE_ADDR |
1202 | arm_get_next_pc (pc) | |
1203 | CORE_ADDR pc; | |
1204 | { | |
e01b4200 ZR |
1205 | unsigned long pc_val; |
1206 | unsigned long this_instr; | |
1207 | unsigned long status; | |
1208 | CORE_ADDR nextpc; | |
1209 | ||
1210 | if (arm_pc_is_thumb (pc)) | |
1211 | return thumb_get_next_pc (pc); | |
1212 | ||
1213 | pc_val = (unsigned long) pc; | |
1214 | this_instr = read_memory_integer (pc, 4); | |
1215 | status = read_register (PS_REGNUM); | |
1216 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ | |
72c9954b | 1217 | |
e01b4200 | 1218 | if (condition_true (bits (this_instr, 28, 31), status)) |
72c9954b | 1219 | { |
e01b4200 | 1220 | switch (bits (this_instr, 24, 27)) |
72c9954b SS |
1221 | { |
1222 | case 0x0: case 0x1: /* data processing */ | |
1223 | case 0x2: case 0x3: | |
1224 | { | |
1225 | unsigned long operand1, operand2, result = 0; | |
1226 | unsigned long rn; | |
1227 | int c; | |
1228 | ||
e01b4200 | 1229 | if (bits (this_instr, 12, 15) != 15) |
72c9954b SS |
1230 | break; |
1231 | ||
1232 | if (bits (this_instr, 22, 25) == 0 | |
1233 | && bits (this_instr, 4, 7) == 9) /* multiply */ | |
1234 | error ("Illegal update to pc in instruction"); | |
1235 | ||
1236 | /* Multiply into PC */ | |
1237 | c = (status & FLAG_C) ? 1 : 0; | |
1238 | rn = bits (this_instr, 16, 19); | |
1239 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1240 | ||
1241 | if (bit (this_instr, 25)) | |
1242 | { | |
1243 | unsigned long immval = bits (this_instr, 0, 7); | |
1244 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
e01b4200 ZR |
1245 | operand2 = ((immval >> rotate) | (immval << (32-rotate))) |
1246 | & 0xffffffff; | |
72c9954b SS |
1247 | } |
1248 | else /* operand 2 is a shifted register */ | |
e01b4200 | 1249 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
72c9954b SS |
1250 | |
1251 | switch (bits (this_instr, 21, 24)) | |
1252 | { | |
1253 | case 0x0: /*and*/ | |
1254 | result = operand1 & operand2; | |
1255 | break; | |
1256 | ||
1257 | case 0x1: /*eor*/ | |
1258 | result = operand1 ^ operand2; | |
1259 | break; | |
1260 | ||
1261 | case 0x2: /*sub*/ | |
1262 | result = operand1 - operand2; | |
1263 | break; | |
1264 | ||
1265 | case 0x3: /*rsb*/ | |
1266 | result = operand2 - operand1; | |
1267 | break; | |
1268 | ||
1269 | case 0x4: /*add*/ | |
1270 | result = operand1 + operand2; | |
1271 | break; | |
1272 | ||
1273 | case 0x5: /*adc*/ | |
1274 | result = operand1 + operand2 + c; | |
1275 | break; | |
1276 | ||
1277 | case 0x6: /*sbc*/ | |
1278 | result = operand1 - operand2 + c; | |
1279 | break; | |
1280 | ||
1281 | case 0x7: /*rsc*/ | |
1282 | result = operand2 - operand1 + c; | |
1283 | break; | |
1284 | ||
1285 | case 0x8: case 0x9: case 0xa: case 0xb: /* tst, teq, cmp, cmn */ | |
1286 | result = (unsigned long) nextpc; | |
1287 | break; | |
1288 | ||
1289 | case 0xc: /*orr*/ | |
1290 | result = operand1 | operand2; | |
1291 | break; | |
1292 | ||
1293 | case 0xd: /*mov*/ | |
1294 | /* Always step into a function. */ | |
1295 | result = operand2; | |
1296 | break; | |
1297 | ||
1298 | case 0xe: /*bic*/ | |
1299 | result = operand1 & ~operand2; | |
1300 | break; | |
1301 | ||
1302 | case 0xf: /*mvn*/ | |
1303 | result = ~operand2; | |
1304 | break; | |
1305 | } | |
1306 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1307 | ||
1308 | if (nextpc == pc) | |
1309 | error ("Infinite loop detected"); | |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | case 0x4: case 0x5: /* data transfer */ | |
1314 | case 0x6: case 0x7: | |
1315 | if (bit (this_instr, 20)) | |
1316 | { | |
1317 | /* load */ | |
1318 | if (bits (this_instr, 12, 15) == 15) | |
1319 | { | |
1320 | /* rd == pc */ | |
1321 | unsigned long rn; | |
1322 | unsigned long base; | |
1323 | ||
1324 | if (bit (this_instr, 22)) | |
1325 | error ("Illegal update to pc in instruction"); | |
1326 | ||
1327 | /* byte write to PC */ | |
1328 | rn = bits (this_instr, 16, 19); | |
1329 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1330 | if (bit (this_instr, 24)) | |
1331 | { | |
1332 | /* pre-indexed */ | |
1333 | int c = (status & FLAG_C) ? 1 : 0; | |
1334 | unsigned long offset = | |
1335 | (bit (this_instr, 25) | |
1336 | ? shifted_reg_val (this_instr, c, pc_val) | |
1337 | : bits (this_instr, 0, 11)); | |
1338 | ||
1339 | if (bit (this_instr, 23)) | |
1340 | base += offset; | |
1341 | else | |
1342 | base -= offset; | |
1343 | } | |
1344 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, | |
1345 | 4); | |
1346 | ||
1347 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1348 | ||
1349 | if (nextpc == pc) | |
1350 | error ("Infinite loop detected"); | |
1351 | } | |
1352 | } | |
1353 | break; | |
1354 | ||
1355 | case 0x8: case 0x9: /* block transfer */ | |
1356 | if (bit (this_instr, 20)) | |
1357 | { | |
1358 | /* LDM */ | |
1359 | if (bit (this_instr, 15)) | |
1360 | { | |
1361 | /* loading pc */ | |
1362 | int offset = 0; | |
1363 | ||
1364 | if (bit (this_instr, 23)) | |
1365 | { | |
1366 | /* up */ | |
1367 | unsigned long reglist = bits (this_instr, 0, 14); | |
e01b4200 | 1368 | offset = bitcount (reglist) * 4; |
72c9954b SS |
1369 | if (bit (this_instr, 24)) /* pre */ |
1370 | offset += 4; | |
1371 | } | |
1372 | else if (bit (this_instr, 24)) | |
1373 | offset = -4; | |
1374 | ||
1375 | { | |
1376 | unsigned long rn_val = | |
1377 | read_register (bits (this_instr, 16, 19)); | |
1378 | nextpc = | |
1379 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
1380 | + offset), | |
1381 | 4); | |
1382 | } | |
1383 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1384 | if (nextpc == pc) | |
1385 | error ("Infinite loop detected"); | |
1386 | } | |
1387 | } | |
1388 | break; | |
1389 | ||
1390 | case 0xb: /* branch & link */ | |
1391 | case 0xa: /* branch */ | |
1392 | { | |
1393 | nextpc = BranchDest (pc, this_instr); | |
1394 | ||
1395 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1396 | if (nextpc == pc) | |
1397 | error ("Infinite loop detected"); | |
1398 | break; | |
1399 | } | |
1400 | ||
1401 | case 0xc: case 0xd: | |
1402 | case 0xe: /* coproc ops */ | |
1403 | case 0xf: /* SWI */ | |
1404 | break; | |
1405 | ||
1406 | default: | |
1407 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1408 | return (pc); | |
1409 | } | |
1410 | } | |
1411 | ||
1412 | return nextpc; | |
1413 | } | |
1414 | ||
e01b4200 ZR |
1415 | #include "bfd-in2.h" |
1416 | #include "libcoff.h" | |
1417 | ||
1418 | static int | |
1419 | gdb_print_insn_arm (memaddr, info) | |
1420 | bfd_vma memaddr; | |
1421 | disassemble_info * info; | |
1422 | { | |
1423 | if (arm_pc_is_thumb (memaddr)) | |
1424 | { | |
1425 | static asymbol * asym; | |
1426 | static combined_entry_type ce; | |
1427 | static struct coff_symbol_struct csym; | |
1428 | static struct _bfd fake_bfd; | |
1429 | static bfd_target fake_target; | |
1430 | ||
1431 | if (csym.native == NULL) | |
1432 | { | |
1433 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1434 | solely so that the code in print_insn_little_arm() and | |
1435 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1436 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
1437 | ||
1438 | fake_target.flavour = bfd_target_coff_flavour; | |
1439 | fake_bfd.xvec = & fake_target; | |
1440 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
1441 | csym.native = & ce; | |
1442 | csym.symbol.the_bfd = & fake_bfd; | |
1443 | csym.symbol.name = "fake"; | |
1444 | asym = (asymbol *) & csym; | |
1445 | } | |
1446 | ||
1447 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
1448 | info->symbols = & asym; | |
1449 | } | |
1450 | else | |
1451 | info->symbols = NULL; | |
1452 | ||
1453 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1454 | return print_insn_big_arm (memaddr, info); | |
1455 | else | |
1456 | return print_insn_little_arm (memaddr, info); | |
1457 | } | |
1458 | ||
1459 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
1460 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
1461 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
1462 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
1463 | (if necessary) to point to the actual memory location where the | |
1464 | breakpoint should be inserted. */ | |
1465 | ||
1466 | unsigned char * | |
1467 | arm_breakpoint_from_pc (pcptr, lenptr) | |
1468 | CORE_ADDR * pcptr; | |
1469 | int * lenptr; | |
1470 | { | |
e01b4200 ZR |
1471 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
1472 | { | |
98760eab AC |
1473 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1474 | { | |
1475 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1476 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1477 | *lenptr = sizeof (thumb_breakpoint); | |
1478 | return thumb_breakpoint; | |
1479 | } | |
1480 | else | |
1481 | { | |
1482 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1483 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1484 | *lenptr = sizeof (thumb_breakpoint); | |
1485 | return thumb_breakpoint; | |
1486 | } | |
e01b4200 ZR |
1487 | } |
1488 | else | |
1489 | { | |
98760eab AC |
1490 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1491 | { | |
1492 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
1493 | *lenptr = sizeof (arm_breakpoint); | |
1494 | return arm_breakpoint; | |
1495 | } | |
1496 | else | |
1497 | { | |
1498 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
1499 | *lenptr = sizeof (arm_breakpoint); | |
1500 | return arm_breakpoint; | |
1501 | } | |
e01b4200 ZR |
1502 | } |
1503 | } | |
e01b4200 ZR |
1504 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). |
1505 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
1506 | ||
1507 | int | |
1508 | arm_in_call_stub (pc, name) | |
1509 | CORE_ADDR pc; | |
1510 | char * name; | |
1511 | { | |
1512 | CORE_ADDR start_addr; | |
1513 | ||
1514 | /* Find the starting address of the function containing the PC. If the | |
1515 | caller didn't give us a name, look it up at the same time. */ | |
1516 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
1517 | return 0; | |
1518 | ||
1519 | return strncmp (name, "_call_via_r", 11) == 0; | |
1520 | } | |
1521 | ||
1522 | ||
1523 | /* If PC is in a Thumb call or return stub, return the address of the target | |
1524 | PC, which is in a register. The thunk functions are called _called_via_xx, | |
1525 | where x is the register name. The possible names are r0-r9, sl, fp, ip, | |
1526 | sp, and lr. */ | |
1527 | ||
1528 | CORE_ADDR | |
1529 | arm_skip_stub (pc) | |
1530 | CORE_ADDR pc; | |
1531 | { | |
1532 | char * name; | |
1533 | CORE_ADDR start_addr; | |
1534 | ||
1535 | /* Find the starting address and name of the function containing the PC. */ | |
1536 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1537 | return 0; | |
1538 | ||
1539 | /* Call thunks always start with "_call_via_". */ | |
1540 | if (strncmp (name, "_call_via_", 10) == 0) | |
1541 | { | |
1542 | /* Use the name suffix to determine which register contains | |
1543 | the target PC. */ | |
1544 | static char *table[15] = | |
1545 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1546 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
1547 | }; | |
1548 | int regno; | |
1549 | ||
1550 | for (regno = 0; regno <= 14; regno++) | |
1551 | if (strcmp (&name[10], table[regno]) == 0) | |
1552 | return read_register (regno); | |
1553 | } | |
1554 | return 0; /* not a stub */ | |
1555 | } | |
1556 | ||
1557 | ||
72c9954b SS |
1558 | void |
1559 | _initialize_arm_tdep () | |
1560 | { | |
e01b4200 | 1561 | tm_print_insn = gdb_print_insn_arm; |
72c9954b SS |
1562 | |
1563 | add_com ("othernames", class_obscure, arm_othernames, | |
1564 | "Switch to the other set of register names."); | |
1565 | ||
e01b4200 | 1566 | /* ??? Maybe this should be a boolean. */ |
72c9954b | 1567 | add_show_from_set (add_set_cmd ("apcs32", no_class, |
e01b4200 | 1568 | var_zinteger, (char *)&arm_apcs_32, |
72c9954b | 1569 | "Set usage of ARM 32-bit mode.\n", &setlist), |
e01b4200 ZR |
1570 | & showlist); |
1571 | ||
1572 | } | |
72c9954b | 1573 | |
e01b4200 ZR |
1574 | /* Test whether the coff symbol specific value corresponds to a Thumb function */ |
1575 | int | |
1576 | coff_sym_is_thumb(int val) | |
1577 | { | |
1578 | return (val == C_THUMBEXT || | |
1579 | val == C_THUMBSTAT || | |
1580 | val == C_THUMBEXTFUNC || | |
1581 | val == C_THUMBSTATFUNC || | |
1582 | val == C_THUMBLABEL); | |
72c9954b | 1583 | } |