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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 KB |
2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
3 | 2001 Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "gdb_string.h" | |
29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
e8b09175 | 30 | #include "dis-asm.h" /* For register flavors. */ |
30f6df08 | 31 | #include <ctype.h> /* for isupper () */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
c906108c | 35 | |
2a451106 KB |
36 | /* Each OS has a different mechanism for accessing the various |
37 | registers stored in the sigcontext structure. | |
38 | ||
39 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
40 | function pointer) which may be used to determine the addresses | |
41 | of the various saved registers in the sigcontext structure. | |
42 | ||
43 | For the ARM target, there are three parameters to this function. | |
44 | The first is the pc value of the frame under consideration, the | |
45 | second the stack pointer of this frame, and the last is the | |
46 | register number to fetch. | |
47 | ||
48 | If the tm.h file does not define this macro, then it's assumed that | |
49 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
50 | be 0. | |
51 | ||
52 | When it comes time to multi-arching this code, see the identically | |
53 | named machinery in ia64-tdep.c for an example of how it could be | |
54 | done. It should not be necessary to modify the code below where | |
55 | this macro is used. */ | |
56 | ||
3bb04bdd AC |
57 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
58 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
59 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
60 | #endif | |
61 | #else | |
62 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
63 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
64 | #endif |
65 | ||
ed9a39eb JM |
66 | extern void _initialize_arm_tdep (void); |
67 | ||
bc90b915 FN |
68 | /* Number of different reg name sets (options). */ |
69 | static int num_flavor_options; | |
70 | ||
71 | /* We have more registers than the disassembler as gdb can print the value | |
72 | of special registers as well. | |
73 | The general register names are overwritten by whatever is being used by | |
74 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ | |
75 | ||
76 | /* Initial value: Register names used in ARM's ISA documentation. */ | |
77 | static char * arm_register_name_strings[] = | |
da59e081 JM |
78 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
79 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
80 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
81 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
82 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
83 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
bc90b915 FN |
84 | "fps", "cpsr" }; /* 24 25 */ |
85 | char **arm_register_names = arm_register_name_strings; | |
ed9a39eb | 86 | |
bc90b915 | 87 | /* Valid register name flavors. */ |
53904c9e | 88 | static const char **valid_flavors; |
ed9a39eb | 89 | |
bc90b915 | 90 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 91 | static const char *disassembly_flavor; |
bc90b915 | 92 | static int current_option; /* Index to that option in the opcodes table. */ |
96baa820 | 93 | |
ed9a39eb JM |
94 | /* This is used to keep the bfd arch_info in sync with the disassembly |
95 | flavor. */ | |
96 | static void set_disassembly_flavor_sfunc(char *, int, | |
97 | struct cmd_list_element *); | |
98 | static void set_disassembly_flavor (void); | |
99 | ||
100 | static void convert_from_extended (void *ptr, void *dbl); | |
101 | ||
102 | /* Define other aspects of the stack frame. We keep the offsets of | |
103 | all saved registers, 'cause we need 'em a lot! We also keep the | |
104 | current size of the stack frame, and the offset of the frame | |
105 | pointer from the stack pointer (for frameless functions, and when | |
106 | we're still in the prologue of a function with a frame) */ | |
107 | ||
108 | struct frame_extra_info | |
109 | { | |
110 | struct frame_saved_regs fsr; | |
111 | int framesize; | |
112 | int frameoffset; | |
113 | int framereg; | |
114 | }; | |
115 | ||
bc90b915 FN |
116 | /* Addresses for calling Thumb functions have the bit 0 set. |
117 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
118 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
119 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
120 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
121 | ||
ed9a39eb JM |
122 | /* Will a function return an aggregate type in memory or in a |
123 | register? Return 0 if an aggregate type can be returned in a | |
124 | register, 1 if it must be returned in memory. */ | |
085dd6e6 | 125 | |
c906108c | 126 | int |
ed9a39eb | 127 | arm_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 128 | { |
ed9a39eb JM |
129 | int nRc; |
130 | register enum type_code code; | |
131 | ||
132 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
133 | registers. For an aggregate type to be integer like, its size | |
134 | must be less than or equal to REGISTER_SIZE and the offset of | |
135 | each addressable subfield must be zero. Note that bit fields are | |
136 | not addressable, and all addressable subfields of unions always | |
137 | start at offset zero. | |
138 | ||
139 | This function is based on the behaviour of GCC 2.95.1. | |
140 | See: gcc/arm.c: arm_return_in_memory() for details. | |
141 | ||
142 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
143 | parameters correctly for a function returning the following | |
144 | structure: struct { float f;}; This should be returned in memory, | |
145 | not a register. Richard Earnshaw sent me a patch, but I do not | |
146 | know of any way to detect if a function like the above has been | |
147 | compiled with the correct calling convention. */ | |
148 | ||
149 | /* All aggregate types that won't fit in a register must be returned | |
150 | in memory. */ | |
151 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
152 | { | |
153 | return 1; | |
154 | } | |
155 | ||
156 | /* The only aggregate types that can be returned in a register are | |
157 | structs and unions. Arrays must be returned in memory. */ | |
158 | code = TYPE_CODE (type); | |
159 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
160 | { | |
161 | return 1; | |
162 | } | |
163 | ||
164 | /* Assume all other aggregate types can be returned in a register. | |
165 | Run a check for structures, unions and arrays. */ | |
166 | nRc = 0; | |
167 | ||
168 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
169 | { | |
170 | int i; | |
171 | /* Need to check if this struct/union is "integer" like. For | |
172 | this to be true, its size must be less than or equal to | |
173 | REGISTER_SIZE and the offset of each addressable subfield | |
174 | must be zero. Note that bit fields are not addressable, and | |
175 | unions always start at offset zero. If any of the subfields | |
176 | is a floating point type, the struct/union cannot be an | |
177 | integer type. */ | |
178 | ||
179 | /* For each field in the object, check: | |
180 | 1) Is it FP? --> yes, nRc = 1; | |
181 | 2) Is it addressable (bitpos != 0) and | |
182 | not packed (bitsize == 0)? | |
183 | --> yes, nRc = 1 | |
184 | */ | |
185 | ||
186 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
187 | { | |
188 | enum type_code field_type_code; | |
189 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
190 | ||
191 | /* Is it a floating point type field? */ | |
192 | if (field_type_code == TYPE_CODE_FLT) | |
193 | { | |
194 | nRc = 1; | |
195 | break; | |
196 | } | |
197 | ||
198 | /* If bitpos != 0, then we have to care about it. */ | |
199 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
200 | { | |
201 | /* Bitfields are not addressable. If the field bitsize is | |
202 | zero, then the field is not packed. Hence it cannot be | |
203 | a bitfield or any other packed type. */ | |
204 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
205 | { | |
206 | nRc = 1; | |
207 | break; | |
208 | } | |
209 | } | |
210 | } | |
211 | } | |
212 | ||
213 | return nRc; | |
c906108c SS |
214 | } |
215 | ||
216 | int | |
ed9a39eb | 217 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 218 | { |
c906108c SS |
219 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
220 | } | |
221 | ||
222 | /* Set to true if the 32-bit mode is in use. */ | |
223 | ||
224 | int arm_apcs_32 = 1; | |
225 | ||
ed9a39eb JM |
226 | /* Flag set by arm_fix_call_dummy that tells whether the target |
227 | function is a Thumb function. This flag is checked by | |
228 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
229 | its use in valops.c) to pass the function address as an additional | |
230 | parameter. */ | |
c906108c SS |
231 | |
232 | static int target_is_thumb; | |
233 | ||
ed9a39eb JM |
234 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
235 | function is a Thumb function. This flag is checked by | |
236 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
237 | |
238 | static int caller_is_thumb; | |
239 | ||
ed9a39eb JM |
240 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
241 | function. */ | |
c906108c SS |
242 | |
243 | int | |
2a451106 | 244 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 245 | { |
c5aa993b | 246 | struct minimal_symbol *sym; |
c906108c | 247 | |
ed9a39eb | 248 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
249 | if (IS_THUMB_ADDR (memaddr)) |
250 | return 1; | |
251 | ||
ed9a39eb | 252 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
253 | sym = lookup_minimal_symbol_by_pc (memaddr); |
254 | if (sym) | |
255 | { | |
c5aa993b | 256 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
257 | } |
258 | else | |
ed9a39eb JM |
259 | { |
260 | return 0; | |
261 | } | |
c906108c SS |
262 | } |
263 | ||
ed9a39eb JM |
264 | /* Determine if the program counter specified in MEMADDR is in a call |
265 | dummy being called from a Thumb function. */ | |
c906108c SS |
266 | |
267 | int | |
2a451106 | 268 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 269 | { |
c5aa993b | 270 | CORE_ADDR sp = read_sp (); |
c906108c | 271 | |
dfcd3bfb JM |
272 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
273 | is the best we can do. We are trying to determine if the pc is on | |
274 | the stack, which (hopefully) will only happen in a call dummy. | |
275 | We hope the current stack pointer is not so far alway from the dummy | |
276 | frame location (true if we have not pushed large data structures or | |
277 | gone too many levels deep) and that our 1024 is not enough to consider | |
278 | code regions as part of the stack (true for most practical purposes) */ | |
279 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) | |
c906108c SS |
280 | return caller_is_thumb; |
281 | else | |
282 | return 0; | |
283 | } | |
284 | ||
285 | CORE_ADDR | |
ed9a39eb | 286 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
287 | { |
288 | if (arm_pc_is_thumb (val)) | |
289 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
290 | else | |
291 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
292 | } | |
293 | ||
294 | CORE_ADDR | |
ed9a39eb | 295 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
296 | { |
297 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
298 | } | |
299 | ||
392a587b | 300 | int |
ed9a39eb | 301 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 302 | { |
392a587b | 303 | CORE_ADDR func_start, after_prologue; |
96baa820 | 304 | int frameless; |
ed9a39eb | 305 | |
392a587b | 306 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 307 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 308 | |
96baa820 | 309 | /* There are some frameless functions whose first two instructions |
ed9a39eb JM |
310 | follow the standard APCS form, in which case after_prologue will |
311 | be func_start + 8. */ | |
312 | ||
96baa820 | 313 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
314 | return frameless; |
315 | } | |
316 | ||
c906108c | 317 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
318 | push {r7, lr} |
319 | add sp, sp, #-28 | |
320 | add r7, sp, #12 | |
c906108c | 321 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
322 | mov r7, sp |
323 | ||
324 | or like this: | |
325 | push {r7, lr} | |
326 | mov r7, sp | |
327 | sub sp, #12 | |
328 | ||
329 | or, on tpcs, like this: | |
330 | sub sp,#16 | |
331 | push {r7, lr} | |
332 | (many instructions) | |
333 | mov r7, sp | |
334 | sub sp, #12 | |
335 | ||
336 | There is always one instruction of three classes: | |
337 | 1 - push | |
338 | 2 - setting of r7 | |
339 | 3 - adjusting of sp | |
340 | ||
341 | When we have found at least one of each class we are done with the prolog. | |
342 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 343 | */ |
c906108c SS |
344 | |
345 | static CORE_ADDR | |
c7885828 | 346 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
347 | { |
348 | CORE_ADDR current_pc; | |
da59e081 JM |
349 | int findmask = 0; /* findmask: |
350 | bit 0 - push { rlist } | |
351 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
352 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
353 | */ | |
c906108c | 354 | |
c7885828 | 355 | for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2) |
c906108c SS |
356 | { |
357 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
358 | ||
da59e081 JM |
359 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
360 | { | |
361 | findmask |= 1; /* push found */ | |
362 | } | |
363 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ | |
364 | { | |
365 | if ((findmask & 1) == 0) /* before push ? */ | |
366 | continue; | |
367 | else | |
368 | findmask |= 4; /* add/sub sp found */ | |
369 | } | |
370 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
371 | { | |
372 | findmask |= 2; /* setting of r7 found */ | |
373 | } | |
374 | else if (insn == 0x466f) /* mov r7, sp */ | |
375 | { | |
376 | findmask |= 2; /* setting of r7 found */ | |
377 | } | |
378 | else | |
379 | continue; /* something in the prolog that we don't care about or some | |
380 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
381 | } |
382 | ||
383 | return current_pc; | |
384 | } | |
385 | ||
ed9a39eb JM |
386 | /* The APCS (ARM Procedure Call Standard) defines the following |
387 | prologue: | |
c906108c | 388 | |
c5aa993b JM |
389 | mov ip, sp |
390 | [stmfd sp!, {a1,a2,a3,a4}] | |
391 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
392 | [stfe f7, [sp, #-12]!] |
393 | [stfe f6, [sp, #-12]!] | |
394 | [stfe f5, [sp, #-12]!] | |
395 | [stfe f4, [sp, #-12]!] | |
396 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c SS |
397 | |
398 | CORE_ADDR | |
ed9a39eb | 399 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
400 | { |
401 | unsigned long inst; | |
402 | CORE_ADDR skip_pc; | |
403 | CORE_ADDR func_addr, func_end; | |
404 | struct symtab_and_line sal; | |
405 | ||
96baa820 | 406 | /* See what the symbol table says. */ |
ed9a39eb | 407 | |
c5aa993b | 408 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c906108c SS |
409 | { |
410 | sal = find_pc_line (func_addr, 0); | |
96baa820 | 411 | if ((sal.line != 0) && (sal.end < func_end)) |
c906108c SS |
412 | return sal.end; |
413 | } | |
414 | ||
415 | /* Check if this is Thumb code. */ | |
416 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 417 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
418 | |
419 | /* Can't find the prologue end in the symbol table, try it the hard way | |
420 | by disassembling the instructions. */ | |
421 | skip_pc = pc; | |
422 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 423 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
424 | return pc; |
425 | ||
426 | skip_pc += 4; | |
427 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 428 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
429 | { |
430 | skip_pc += 4; | |
431 | inst = read_memory_integer (skip_pc, 4); | |
432 | } | |
433 | ||
c5aa993b | 434 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
435 | return pc; |
436 | ||
437 | skip_pc += 4; | |
438 | inst = read_memory_integer (skip_pc, 4); | |
439 | ||
440 | /* Any insns after this point may float into the code, if it makes | |
ed9a39eb JM |
441 | for better instruction scheduling, so we skip them only if we |
442 | find them, but still consdier the function to be frame-ful. */ | |
c906108c | 443 | |
ed9a39eb JM |
444 | /* We may have either one sfmfd instruction here, or several stfe |
445 | insns, depending on the version of floating point code we | |
446 | support. */ | |
c5aa993b | 447 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
448 | { |
449 | skip_pc += 4; | |
450 | inst = read_memory_integer (skip_pc, 4); | |
451 | } | |
452 | else | |
453 | { | |
c5aa993b JM |
454 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
455 | { | |
456 | skip_pc += 4; | |
457 | inst = read_memory_integer (skip_pc, 4); | |
458 | } | |
c906108c SS |
459 | } |
460 | ||
c5aa993b | 461 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
462 | skip_pc += 4; |
463 | ||
464 | return skip_pc; | |
465 | } | |
c5aa993b | 466 | /* *INDENT-OFF* */ |
c906108c SS |
467 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
468 | This function decodes a Thumb function prologue to determine: | |
469 | 1) the size of the stack frame | |
470 | 2) which registers are saved on it | |
471 | 3) the offsets of saved regs | |
472 | 4) the offset from the stack pointer to the frame pointer | |
473 | This information is stored in the "extra" fields of the frame_info. | |
474 | ||
da59e081 JM |
475 | A typical Thumb function prologue would create this stack frame |
476 | (offsets relative to FP) | |
c906108c SS |
477 | old SP -> 24 stack parameters |
478 | 20 LR | |
479 | 16 R7 | |
480 | R7 -> 0 local variables (16 bytes) | |
481 | SP -> -12 additional stack space (12 bytes) | |
482 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
483 | 12 bytes. The frame register is R7. |
484 | ||
485 | The comments for thumb_skip_prolog() describe the algorithm we use to detect | |
486 | the end of the prolog */ | |
c5aa993b JM |
487 | /* *INDENT-ON* */ |
488 | ||
c906108c | 489 | static void |
ed9a39eb | 490 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
491 | { |
492 | CORE_ADDR prologue_start; | |
493 | CORE_ADDR prologue_end; | |
494 | CORE_ADDR current_pc; | |
c5aa993b | 495 | int saved_reg[16]; /* which register has been copied to register n? */ |
da59e081 JM |
496 | int findmask = 0; /* findmask: |
497 | bit 0 - push { rlist } | |
498 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
499 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
500 | */ | |
c5aa993b | 501 | int i; |
c906108c | 502 | |
c5aa993b | 503 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
504 | { |
505 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
506 | ||
c5aa993b | 507 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
508 | prologue_end = fi->pc; |
509 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 510 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
511 | } |
512 | else | |
c5aa993b JM |
513 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
514 | /* 16 pushes, an add, and "mv fp,sp" */ | |
c906108c SS |
515 | |
516 | prologue_end = min (prologue_end, fi->pc); | |
517 | ||
518 | /* Initialize the saved register map. When register H is copied to | |
519 | register L, we will put H in saved_reg[L]. */ | |
520 | for (i = 0; i < 16; i++) | |
521 | saved_reg[i] = i; | |
522 | ||
523 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
524 | frame pointer, adjust the stack pointer, and save registers. |
525 | Do this until all basic prolog instructions are found. */ | |
c906108c SS |
526 | |
527 | fi->framesize = 0; | |
da59e081 JM |
528 | for (current_pc = prologue_start; |
529 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
530 | current_pc += 2) | |
c906108c SS |
531 | { |
532 | unsigned short insn; | |
533 | int regno; | |
534 | int offset; | |
535 | ||
536 | insn = read_memory_unsigned_integer (current_pc, 2); | |
537 | ||
c5aa993b | 538 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 539 | { |
da59e081 JM |
540 | int mask; |
541 | findmask |= 1; /* push found */ | |
c906108c SS |
542 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
543 | whether to save LR (R14). */ | |
da59e081 | 544 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c SS |
545 | |
546 | /* Calculate offsets of saved R0-R7 and LR. */ | |
547 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
548 | if (mask & (1 << regno)) | |
c5aa993b | 549 | { |
c906108c SS |
550 | fi->framesize += 4; |
551 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); | |
552 | saved_reg[regno] = regno; /* reset saved register map */ | |
553 | } | |
554 | } | |
da59e081 | 555 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ |
c906108c | 556 | { |
da59e081 JM |
557 | if ((findmask & 1) == 0) /* before push ? */ |
558 | continue; | |
559 | else | |
560 | findmask |= 4; /* add/sub sp found */ | |
561 | ||
c5aa993b | 562 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
da59e081 JM |
563 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
564 | { | |
565 | fi->frameoffset += offset; | |
566 | offset = -offset; | |
567 | } | |
c906108c SS |
568 | fi->framesize -= offset; |
569 | } | |
570 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
571 | { | |
da59e081 | 572 | findmask |= 2; /* setting of r7 found */ |
c906108c | 573 | fi->framereg = THUMB_FP_REGNUM; |
c5aa993b | 574 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ |
c906108c | 575 | } |
da59e081 | 576 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 577 | { |
da59e081 | 578 | findmask |= 2; /* setting of r7 found */ |
c906108c SS |
579 | fi->framereg = THUMB_FP_REGNUM; |
580 | fi->frameoffset = 0; | |
581 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; | |
582 | } | |
583 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
584 | { | |
c5aa993b | 585 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 586 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 587 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
588 | } |
589 | else | |
da59e081 JM |
590 | continue; /* something in the prolog that we don't care about or some |
591 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
592 | } |
593 | } | |
594 | ||
ed9a39eb JM |
595 | /* Check if prologue for this frame's PC has already been scanned. If |
596 | it has, copy the relevant information about that prologue and | |
c906108c SS |
597 | return non-zero. Otherwise do not copy anything and return zero. |
598 | ||
599 | The information saved in the cache includes: | |
c5aa993b JM |
600 | * the frame register number; |
601 | * the size of the stack frame; | |
602 | * the offsets of saved regs (relative to the old SP); and | |
603 | * the offset from the stack pointer to the frame pointer | |
c906108c | 604 | |
ed9a39eb JM |
605 | The cache contains only one entry, since this is adequate for the |
606 | typical sequence of prologue scan requests we get. When performing | |
607 | a backtrace, GDB will usually ask to scan the same function twice | |
608 | in a row (once to get the frame chain, and once to fill in the | |
609 | extra frame information). */ | |
c906108c SS |
610 | |
611 | static struct frame_info prologue_cache; | |
612 | ||
613 | static int | |
ed9a39eb | 614 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
615 | { |
616 | int i; | |
617 | ||
618 | if (fi->pc == prologue_cache.pc) | |
619 | { | |
620 | fi->framereg = prologue_cache.framereg; | |
621 | fi->framesize = prologue_cache.framesize; | |
622 | fi->frameoffset = prologue_cache.frameoffset; | |
911413e6 | 623 | for (i = 0; i < NUM_REGS; i++) |
c906108c SS |
624 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; |
625 | return 1; | |
626 | } | |
627 | else | |
628 | return 0; | |
629 | } | |
630 | ||
631 | ||
ed9a39eb | 632 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
633 | |
634 | static void | |
ed9a39eb | 635 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
636 | { |
637 | int i; | |
638 | ||
c5aa993b JM |
639 | prologue_cache.pc = fi->pc; |
640 | prologue_cache.framereg = fi->framereg; | |
641 | prologue_cache.framesize = fi->framesize; | |
c906108c | 642 | prologue_cache.frameoffset = fi->frameoffset; |
c5aa993b | 643 | |
911413e6 | 644 | for (i = 0; i < NUM_REGS; i++) |
c906108c SS |
645 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; |
646 | } | |
647 | ||
648 | ||
ed9a39eb | 649 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
650 | 1) the size of the stack frame |
651 | 2) which registers are saved on it | |
652 | 3) the offsets of saved regs | |
653 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
654 | This information is stored in the "extra" fields of the frame_info. |
655 | ||
96baa820 JM |
656 | There are two basic forms for the ARM prologue. The fixed argument |
657 | function call will look like: | |
ed9a39eb JM |
658 | |
659 | mov ip, sp | |
660 | stmfd sp!, {fp, ip, lr, pc} | |
661 | sub fp, ip, #4 | |
662 | [sub sp, sp, #4] | |
96baa820 | 663 | |
c906108c | 664 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
665 | IP -> 4 (caller's stack) |
666 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
667 | -4 LR (return address in caller) | |
668 | -8 IP (copy of caller's SP) | |
669 | -12 FP (caller's FP) | |
670 | SP -> -28 Local variables | |
671 | ||
c906108c | 672 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
673 | 28 bytes. The stmfd call can also save any of the vN registers it |
674 | plans to use, which increases the frame size accordingly. | |
675 | ||
676 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
677 | because the ARM Store instructions always store PC + 8 when you read | |
678 | the PC register. | |
ed9a39eb | 679 | |
96baa820 JM |
680 | A variable argument function call will look like: |
681 | ||
ed9a39eb JM |
682 | mov ip, sp |
683 | stmfd sp!, {a1, a2, a3, a4} | |
684 | stmfd sp!, {fp, ip, lr, pc} | |
685 | sub fp, ip, #20 | |
686 | ||
96baa820 | 687 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
688 | IP -> 20 (caller's stack) |
689 | 16 A4 | |
690 | 12 A3 | |
691 | 8 A2 | |
692 | 4 A1 | |
693 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
694 | -4 LR (return address in caller) | |
695 | -8 IP (copy of caller's SP) | |
696 | -12 FP (caller's FP) | |
697 | SP -> -28 Local variables | |
96baa820 JM |
698 | |
699 | The frame size would thus be 48 bytes, and the frame offset would be | |
700 | 28 bytes. | |
701 | ||
702 | There is another potential complication, which is that the optimizer | |
703 | will try to separate the store of fp in the "stmfd" instruction from | |
704 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
705 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
706 | ||
707 | Also, note, the original version of the ARM toolchain claimed that there | |
708 | should be an | |
709 | ||
710 | instruction at the end of the prologue. I have never seen GCC produce | |
711 | this, and the ARM docs don't mention it. We still test for it below in | |
712 | case it happens... | |
ed9a39eb JM |
713 | |
714 | */ | |
c906108c SS |
715 | |
716 | static void | |
ed9a39eb | 717 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
718 | { |
719 | int regno, sp_offset, fp_offset; | |
720 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
721 | ||
722 | /* Check if this function is already in the cache of frame information. */ | |
723 | if (check_prologue_cache (fi)) | |
724 | return; | |
725 | ||
726 | /* Assume there is no frame until proven otherwise. */ | |
c5aa993b JM |
727 | fi->framereg = SP_REGNUM; |
728 | fi->framesize = 0; | |
c906108c SS |
729 | fi->frameoffset = 0; |
730 | ||
731 | /* Check for Thumb prologue. */ | |
732 | if (arm_pc_is_thumb (fi->pc)) | |
733 | { | |
734 | thumb_scan_prologue (fi); | |
735 | save_prologue_cache (fi); | |
736 | return; | |
737 | } | |
738 | ||
739 | /* Find the function prologue. If we can't find the function in | |
740 | the symbol table, peek in the stack frame to find the PC. */ | |
741 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
742 | { | |
2a451106 KB |
743 | /* One way to find the end of the prologue (which works well |
744 | for unoptimized code) is to do the following: | |
745 | ||
746 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
747 | ||
748 | if (sal.line == 0) | |
749 | prologue_end = fi->pc; | |
750 | else if (sal.end < prologue_end) | |
751 | prologue_end = sal.end; | |
752 | ||
753 | This mechanism is very accurate so long as the optimizer | |
754 | doesn't move any instructions from the function body into the | |
755 | prologue. If this happens, sal.end will be the last | |
756 | instruction in the first hunk of prologue code just before | |
757 | the first instruction that the scheduler has moved from | |
758 | the body to the prologue. | |
759 | ||
760 | In order to make sure that we scan all of the prologue | |
761 | instructions, we use a slightly less accurate mechanism which | |
762 | may scan more than necessary. To help compensate for this | |
763 | lack of accuracy, the prologue scanning loop below contains | |
764 | several clauses which'll cause the loop to terminate early if | |
765 | an implausible prologue instruction is encountered. | |
766 | ||
767 | The expression | |
768 | ||
769 | prologue_start + 64 | |
770 | ||
771 | is a suitable endpoint since it accounts for the largest | |
772 | possible prologue plus up to five instructions inserted by | |
773 | the scheduler. */ | |
774 | ||
775 | if (prologue_end > prologue_start + 64) | |
776 | { | |
777 | prologue_end = prologue_start + 64; /* See above. */ | |
778 | } | |
c906108c SS |
779 | } |
780 | else | |
781 | { | |
782 | /* Get address of the stmfd in the prologue of the callee; the saved | |
96baa820 | 783 | PC is the address of the stmfd + 8. */ |
ed9a39eb | 784 | prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4)) |
96baa820 | 785 | - 8; |
2a451106 | 786 | prologue_end = prologue_start + 64; /* See above. */ |
c906108c SS |
787 | } |
788 | ||
789 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 790 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 791 | |
96baa820 JM |
792 | Be careful, however, and if it doesn't look like a prologue, |
793 | don't try to scan it. If, for instance, a frameless function | |
794 | begins with stmfd sp!, then we will tell ourselves there is | |
795 | a frame, which will confuse stack traceback, as well ad"finish" | |
796 | and other operations that rely on a knowledge of the stack | |
797 | traceback. | |
798 | ||
799 | In the APCS, the prologue should start with "mov ip, sp" so | |
800 | if we don't see this as the first insn, we will stop. */ | |
c906108c SS |
801 | |
802 | sp_offset = fp_offset = 0; | |
c906108c | 803 | |
ed9a39eb JM |
804 | if (read_memory_unsigned_integer (prologue_start, 4) |
805 | == 0xe1a0c00d) /* mov ip, sp */ | |
96baa820 | 806 | { |
ed9a39eb | 807 | for (current_pc = prologue_start + 4; current_pc < prologue_end; |
96baa820 | 808 | current_pc += 4) |
c906108c | 809 | { |
96baa820 | 810 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
ed9a39eb | 811 | |
96baa820 JM |
812 | if ((insn & 0xffff0000) == 0xe92d0000) |
813 | /* stmfd sp!, {..., fp, ip, lr, pc} | |
814 | or | |
815 | stmfd sp!, {a1, a2, a3, a4} */ | |
816 | { | |
817 | int mask = insn & 0xffff; | |
ed9a39eb | 818 | |
96baa820 JM |
819 | /* Calculate offsets of saved registers. */ |
820 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
821 | if (mask & (1 << regno)) | |
822 | { | |
823 | sp_offset -= 4; | |
824 | fi->fsr.regs[regno] = sp_offset; | |
825 | } | |
826 | } | |
ed9a39eb | 827 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
96baa820 | 828 | { |
ed9a39eb JM |
829 | unsigned imm = insn & 0xff; /* immediate value */ |
830 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
831 | imm = (imm >> rot) | (imm << (32 - rot)); | |
96baa820 JM |
832 | fp_offset = -imm; |
833 | fi->framereg = FP_REGNUM; | |
834 | } | |
ed9a39eb | 835 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
96baa820 | 836 | { |
ed9a39eb JM |
837 | unsigned imm = insn & 0xff; /* immediate value */ |
838 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
839 | imm = (imm >> rot) | (imm << (32 - rot)); | |
96baa820 JM |
840 | sp_offset -= imm; |
841 | } | |
ed9a39eb | 842 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
96baa820 JM |
843 | { |
844 | sp_offset -= 12; | |
845 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
846 | fi->fsr.regs[regno] = sp_offset; | |
847 | } | |
ed9a39eb | 848 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
96baa820 | 849 | { |
ed9a39eb | 850 | int n_saved_fp_regs; |
96baa820 | 851 | unsigned int fp_start_reg, fp_bound_reg; |
ed9a39eb JM |
852 | |
853 | if ((insn & 0x800) == 0x800) /* N0 is set */ | |
854 | { | |
855 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ | |
96baa820 JM |
856 | n_saved_fp_regs = 3; |
857 | else | |
858 | n_saved_fp_regs = 1; | |
859 | } | |
860 | else | |
ed9a39eb JM |
861 | { |
862 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ | |
96baa820 JM |
863 | n_saved_fp_regs = 2; |
864 | else | |
865 | n_saved_fp_regs = 4; | |
866 | } | |
ed9a39eb | 867 | |
96baa820 JM |
868 | fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); |
869 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; | |
870 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
871 | { | |
872 | sp_offset -= 12; | |
873 | fi->fsr.regs[fp_start_reg++] = sp_offset; | |
874 | } | |
875 | } | |
2a451106 KB |
876 | else if ((insn & 0xf0000000) != 0xe0000000) |
877 | break; /* Condition not true, exit early */ | |
878 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ | |
879 | break; /* Don't scan past a block load */ | |
96baa820 | 880 | else |
ed9a39eb JM |
881 | /* The optimizer might shove anything into the prologue, |
882 | so we just skip what we don't recognize. */ | |
883 | continue; | |
c906108c | 884 | } |
c906108c SS |
885 | } |
886 | ||
887 | /* The frame size is just the negative of the offset (from the original SP) | |
888 | of the last thing thing we pushed on the stack. The frame offset is | |
889 | [new FP] - [new SP]. */ | |
890 | fi->framesize = -sp_offset; | |
891 | fi->frameoffset = fp_offset - sp_offset; | |
ed9a39eb | 892 | |
c906108c SS |
893 | save_prologue_cache (fi); |
894 | } | |
895 | ||
ed9a39eb JM |
896 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
897 | One thing we might want to do here is to check REGNUM against the | |
898 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
899 | the stack somewhere. This would provide a graceful failure mode | |
900 | when trying to get the value of caller-saves registers for an inner | |
901 | frame. */ | |
c906108c SS |
902 | |
903 | static CORE_ADDR | |
ed9a39eb | 904 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c SS |
905 | { |
906 | for (; fi; fi = fi->next) | |
c5aa993b JM |
907 | |
908 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
c906108c SS |
909 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
910 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
911 | else | |
912 | #endif | |
c5aa993b JM |
913 | if (fi->fsr.regs[regnum] != 0) |
914 | return read_memory_integer (fi->fsr.regs[regnum], | |
915 | REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
916 | return read_register (regnum); |
917 | } | |
c5aa993b | 918 | /* *INDENT-OFF* */ |
c906108c SS |
919 | /* Function: frame_chain |
920 | Given a GDB frame, determine the address of the calling function's frame. | |
921 | This will be used to create a new GDB frame struct, and then | |
922 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
923 | For ARM, we save the frame size when we initialize the frame_info. | |
924 | ||
925 | The original definition of this function was a macro in tm-arm.h: | |
926 | { In the case of the ARM, the frame's nominal address is the FP value, | |
927 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
928 | ||
929 | #define FRAME_CHAIN(thisframe) \ | |
930 | ((thisframe)->pc >= LOWEST_PC ? \ | |
931 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
932 | 0) | |
933 | */ | |
c5aa993b JM |
934 | /* *INDENT-ON* */ |
935 | ||
c906108c | 936 | CORE_ADDR |
ed9a39eb | 937 | arm_frame_chain (struct frame_info *fi) |
c906108c | 938 | { |
c5aa993b | 939 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
940 | CORE_ADDR fn_start, callers_pc, fp; |
941 | ||
942 | /* is this a dummy frame? */ | |
943 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 944 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
945 | |
946 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 947 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
c906108c | 948 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
c5aa993b JM |
949 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
950 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
951 | |
952 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
953 | if (fn_start == entry_point_address ()) | |
c5aa993b | 954 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
955 | #endif |
956 | CORE_ADDR caller_pc, fn_start; | |
957 | struct frame_info caller_fi; | |
958 | int framereg = fi->framereg; | |
959 | ||
960 | if (fi->pc < LOWEST_PC) | |
961 | return 0; | |
962 | ||
963 | /* If the caller is the startup code, we're at the end of the chain. */ | |
964 | caller_pc = FRAME_SAVED_PC (fi); | |
965 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
966 | if (fn_start == entry_point_address ()) | |
967 | return 0; | |
968 | ||
969 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
970 | the frame register of the caller is different from ours. | |
971 | So we must scan the prologue of the caller to determine its | |
972 | frame register number. */ | |
973 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) | |
974 | { | |
c5aa993b | 975 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c906108c | 976 | caller_fi.pc = caller_pc; |
c5aa993b | 977 | arm_scan_prologue (&caller_fi); |
c906108c SS |
978 | framereg = caller_fi.framereg; |
979 | } | |
980 | ||
981 | /* If the caller used a frame register, return its value. | |
982 | Otherwise, return the caller's stack pointer. */ | |
983 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
984 | return arm_find_callers_reg (fi, framereg); | |
985 | else | |
986 | return fi->frame + fi->framesize; | |
987 | } | |
988 | ||
ed9a39eb JM |
989 | /* This function actually figures out the frame address for a given pc |
990 | and sp. This is tricky because we sometimes don't use an explicit | |
991 | frame pointer, and the previous stack pointer isn't necessarily | |
992 | recorded on the stack. The only reliable way to get this info is | |
993 | to examine the prologue. FROMLEAF is a little confusing, it means | |
994 | this is the next frame up the chain AFTER a frameless function. If | |
995 | this is true, then the frame value for this frame is still in the | |
996 | fp register. */ | |
c906108c SS |
997 | |
998 | void | |
ed9a39eb | 999 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1000 | { |
1001 | int reg; | |
1002 | ||
1003 | if (fi->next) | |
1004 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1005 | ||
1006 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); | |
1007 | ||
c5aa993b | 1008 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1009 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1010 | { | |
1011 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
1012 | by assuming it's always FP. */ |
1013 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
1014 | fi->framesize = 0; | |
c906108c SS |
1015 | fi->frameoffset = 0; |
1016 | return; | |
1017 | } | |
c5aa993b | 1018 | else |
c906108c | 1019 | #endif |
2a451106 KB |
1020 | |
1021 | /* Determine whether or not we're in a sigtramp frame. | |
1022 | Unfortunately, it isn't sufficient to test | |
1023 | fi->signal_handler_caller because this value is sometimes set | |
1024 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1025 | fi->signal_handler_caller and IN_SIGTRAMP to determine if we need | |
1026 | to use the sigcontext addresses for the saved registers. | |
1027 | ||
1028 | Note: If an ARM IN_SIGTRAMP method ever needs to compare against | |
1029 | the name of the function, the code below will have to be changed | |
1030 | to first fetch the name of the function and then pass this name | |
1031 | to IN_SIGTRAMP. */ | |
1032 | ||
3bb04bdd | 1033 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
2a451106 KB |
1034 | && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, 0))) |
1035 | { | |
1036 | CORE_ADDR sp; | |
1037 | ||
1038 | if (!fi->next) | |
1039 | sp = read_sp(); | |
1040 | else | |
1041 | sp = fi->next->frame - fi->next->frameoffset + fi->next->framesize; | |
1042 | ||
1043 | for (reg = 0; reg < NUM_REGS; reg++) | |
1044 | fi->fsr.regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); | |
1045 | ||
1046 | /* FIXME: What about thumb mode? */ | |
1047 | fi->framereg = SP_REGNUM; | |
1048 | fi->frame = read_memory_integer (fi->fsr.regs[fi->framereg], 4); | |
1049 | fi->framesize = 0; | |
1050 | fi->frameoffset = 0; | |
1051 | ||
1052 | } | |
1053 | else | |
c906108c SS |
1054 | { |
1055 | arm_scan_prologue (fi); | |
1056 | ||
104c1213 JM |
1057 | if (!fi->next) |
1058 | /* this is the innermost frame? */ | |
c906108c | 1059 | fi->frame = read_register (fi->framereg); |
ed9a39eb JM |
1060 | else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) |
1061 | { | |
1062 | /* not the innermost frame */ | |
1063 | /* If we have an FP, the callee saved it. */ | |
1064 | if (fi->next->fsr.regs[fi->framereg] != 0) | |
1065 | fi->frame = | |
1066 | read_memory_integer (fi->next->fsr.regs[fi->framereg], 4); | |
1067 | else if (fromleaf) | |
1068 | /* If we were called by a frameless fn. then our frame is | |
1069 | still in the frame pointer register on the board... */ | |
1070 | fi->frame = read_fp (); | |
1071 | } | |
c906108c | 1072 | |
ed9a39eb JM |
1073 | /* Calculate actual addresses of saved registers using offsets |
1074 | determined by arm_scan_prologue. */ | |
c906108c SS |
1075 | for (reg = 0; reg < NUM_REGS; reg++) |
1076 | if (fi->fsr.regs[reg] != 0) | |
1077 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | ||
ed9a39eb JM |
1082 | /* Find the caller of this frame. We do this by seeing if LR_REGNUM |
1083 | is saved in the stack anywhere, otherwise we get it from the | |
1084 | registers. | |
c906108c SS |
1085 | |
1086 | The old definition of this function was a macro: | |
c5aa993b | 1087 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1088 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c SS |
1089 | |
1090 | CORE_ADDR | |
ed9a39eb | 1091 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1092 | { |
c5aa993b | 1093 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1094 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1095 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
1096 | else | |
1097 | #endif | |
1098 | { | |
1099 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
1100 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1101 | } | |
1102 | } | |
1103 | ||
c906108c SS |
1104 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1105 | Examine the Program Status Register to decide which state we're in. */ | |
1106 | ||
1107 | CORE_ADDR | |
ed9a39eb | 1108 | arm_target_read_fp (void) |
c906108c SS |
1109 | { |
1110 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
1111 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
1112 | else | |
c5aa993b | 1113 | return read_register (FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1114 | } |
1115 | ||
ed9a39eb | 1116 | /* Calculate the frame offsets of the saved registers (ARM version). */ |
c906108c | 1117 | |
c906108c | 1118 | void |
ed9a39eb JM |
1119 | arm_frame_find_saved_regs (struct frame_info *fi, |
1120 | struct frame_saved_regs *regaddr) | |
c906108c SS |
1121 | { |
1122 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); | |
1123 | } | |
1124 | ||
c906108c | 1125 | void |
ed9a39eb | 1126 | arm_push_dummy_frame (void) |
c906108c SS |
1127 | { |
1128 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
1129 | CORE_ADDR sp = old_sp; | |
1130 | CORE_ADDR fp, prologue_start; | |
1131 | int regnum; | |
1132 | ||
1133 | /* Push the two dummy prologue instructions in reverse order, | |
1134 | so that they'll be in the correct low-to-high order in memory. */ | |
1135 | /* sub fp, ip, #4 */ | |
1136 | sp = push_word (sp, 0xe24cb004); | |
1137 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1138 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1139 | ||
ed9a39eb JM |
1140 | /* Push a pointer to the dummy prologue + 12, because when stm |
1141 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1142 | instruction itself plus 12. */ |
1143 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1144 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ |
c906108c SS |
1145 | sp = push_word (sp, old_sp); |
1146 | sp = push_word (sp, read_register (FP_REGNUM)); | |
c5aa993b JM |
1147 | |
1148 | for (regnum = 10; regnum >= 0; regnum--) | |
c906108c | 1149 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1150 | |
c906108c SS |
1151 | write_register (FP_REGNUM, fp); |
1152 | write_register (THUMB_FP_REGNUM, fp); | |
1153 | write_register (SP_REGNUM, sp); | |
1154 | } | |
1155 | ||
1156 | /* Fix up the call dummy, based on whether the processor is currently | |
ed9a39eb JM |
1157 | in Thumb or ARM mode, and whether the target function is Thumb or |
1158 | ARM. There are three different situations requiring three | |
c906108c SS |
1159 | different dummies: |
1160 | ||
1161 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1162 | been copied into the dummy parameter to this function. |
c906108c | 1163 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1164 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1165 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1166 | works for calling both ARM and Thumb functions. |
c906108c | 1167 | |
ed9a39eb JM |
1168 | All three call dummies expect to receive the target function |
1169 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c SS |
1170 | |
1171 | void | |
ed9a39eb | 1172 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1173 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1174 | { |
1175 | static short thumb_dummy[4] = | |
1176 | { | |
c5aa993b JM |
1177 | 0xf000, 0xf801, /* bl label */ |
1178 | 0xdf18, /* swi 24 */ | |
1179 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1180 | }; |
1181 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1182 | ||
1183 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 1184 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
c906108c | 1185 | |
ed9a39eb JM |
1186 | /* If the target function is Thumb, set the low bit of the function |
1187 | address. And if the CPU is currently in ARM mode, patch the | |
1188 | second instruction of call dummy to use a BX instruction to | |
1189 | switch to Thumb mode. */ | |
c906108c SS |
1190 | target_is_thumb = arm_pc_is_thumb (fun); |
1191 | if (target_is_thumb) | |
1192 | { | |
1193 | fun |= 1; | |
1194 | if (!caller_is_thumb) | |
1195 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1196 | } | |
1197 | ||
1198 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1199 | instead of the ARM one that's already been copied. This will | |
1200 | work for both Thumb and ARM target functions. */ | |
1201 | if (caller_is_thumb) | |
1202 | { | |
1203 | int i; | |
1204 | char *p = dummy; | |
1205 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1206 | ||
1207 | for (i = 0; i < len; i++) | |
1208 | { | |
1209 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1210 | p += sizeof (thumb_dummy[0]); | |
1211 | } | |
1212 | } | |
1213 | ||
ed9a39eb JM |
1214 | /* Put the target address in r4; the call dummy will copy this to |
1215 | the PC. */ | |
c906108c SS |
1216 | write_register (4, fun); |
1217 | } | |
1218 | ||
c906108c | 1219 | /* Return the offset in the call dummy of the instruction that needs |
ed9a39eb JM |
1220 | to have a breakpoint placed on it. This is the offset of the 'swi |
1221 | 24' instruction, which is no longer actually used, but simply acts | |
c906108c SS |
1222 | as a place-holder now. |
1223 | ||
ed9a39eb | 1224 | This implements the CALL_DUMMY_BREAK_OFFSET macro. */ |
c906108c SS |
1225 | |
1226 | int | |
ed9a39eb | 1227 | arm_call_dummy_breakpoint_offset (void) |
c906108c SS |
1228 | { |
1229 | if (caller_is_thumb) | |
1230 | return 4; | |
1231 | else | |
1232 | return 8; | |
1233 | } | |
1234 | ||
ed9a39eb JM |
1235 | /* Note: ScottB |
1236 | ||
1237 | This function does not support passing parameters using the FPA | |
1238 | variant of the APCS. It passes any floating point arguments in the | |
1239 | general registers and/or on the stack. */ | |
c906108c SS |
1240 | |
1241 | CORE_ADDR | |
ea7c478f | 1242 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1243 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1244 | { |
ed9a39eb JM |
1245 | char *fp; |
1246 | int argnum, argreg, nstack_size; | |
1247 | ||
1248 | /* Walk through the list of args and determine how large a temporary | |
1249 | stack is required. Need to take care here as structs may be | |
1250 | passed on the stack, and we have to to push them. */ | |
1251 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
1252 | if (struct_return) /* The struct address goes in A1. */ | |
1253 | nstack_size += REGISTER_SIZE; | |
1254 | ||
1255 | /* Walk through the arguments and add their size to nstack_size. */ | |
1256 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1257 | { |
c906108c | 1258 | int len; |
ed9a39eb JM |
1259 | struct type *arg_type; |
1260 | ||
1261 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1262 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1263 | |
ed9a39eb JM |
1264 | /* ANSI C code passes float arguments as integers, K&R code |
1265 | passes float arguments as doubles. Correct for this here. */ | |
1266 | if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) | |
1267 | nstack_size += FP_REGISTER_VIRTUAL_SIZE; | |
1268 | else | |
1269 | nstack_size += len; | |
1270 | } | |
c906108c | 1271 | |
ed9a39eb JM |
1272 | /* Allocate room on the stack, and initialize our stack frame |
1273 | pointer. */ | |
1274 | fp = NULL; | |
1275 | if (nstack_size > 0) | |
1276 | { | |
1277 | sp -= nstack_size; | |
1278 | fp = (char *) sp; | |
1279 | } | |
1280 | ||
1281 | /* Initialize the integer argument register pointer. */ | |
c906108c | 1282 | argreg = A1_REGNUM; |
c906108c | 1283 | |
ed9a39eb JM |
1284 | /* The struct_return pointer occupies the first parameter passing |
1285 | register. */ | |
c906108c | 1286 | if (struct_return) |
c5aa993b | 1287 | write_register (argreg++, struct_addr); |
c906108c | 1288 | |
ed9a39eb JM |
1289 | /* Process arguments from left to right. Store as many as allowed |
1290 | in the parameter passing registers (A1-A4), and save the rest on | |
1291 | the temporary stack. */ | |
c5aa993b | 1292 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1293 | { |
ed9a39eb | 1294 | int len; |
c5aa993b | 1295 | char *val; |
c5aa993b | 1296 | CORE_ADDR regval; |
ed9a39eb JM |
1297 | enum type_code typecode; |
1298 | struct type *arg_type, *target_type; | |
1299 | ||
1300 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1301 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1302 | len = TYPE_LENGTH (arg_type); | |
1303 | typecode = TYPE_CODE (arg_type); | |
1304 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1305 | ||
1306 | /* ANSI C code passes float arguments as integers, K&R code | |
1307 | passes float arguments as doubles. The .stabs record for | |
1308 | for ANSI prototype floating point arguments records the | |
1309 | type as FP_INTEGER, while a K&R style (no prototype) | |
1310 | .stabs records the type as FP_FLOAT. In this latter case | |
1311 | the compiler converts the float arguments to double before | |
1312 | calling the function. */ | |
1313 | if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) | |
1314 | { | |
a37b3cc0 AC |
1315 | DOUBLEST dblval; |
1316 | dblval = extract_floating (val, len); | |
1317 | len = TARGET_DOUBLE_BIT / TARGET_CHAR_BIT; | |
1318 | val = alloca (len); | |
1319 | store_floating (val, len, dblval); | |
ed9a39eb | 1320 | } |
da59e081 JM |
1321 | #if 1 |
1322 | /* I don't know why this code was disable. The only logical use | |
1323 | for a function pointer is to call that function, so setting | |
1324 | the mode bit is perfectly fine. FN */ | |
ed9a39eb | 1325 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1326 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1327 | if (TYPE_CODE_PTR == typecode |
1328 | && NULL != target_type | |
1329 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1330 | { |
ed9a39eb | 1331 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1332 | if (arm_pc_is_thumb (regval)) |
1333 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1334 | } | |
c906108c | 1335 | #endif |
ed9a39eb JM |
1336 | /* Copy the argument to general registers or the stack in |
1337 | register-sized pieces. Large arguments are split between | |
1338 | registers and stack. */ | |
1339 | while (len > 0) | |
c906108c | 1340 | { |
ed9a39eb JM |
1341 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1342 | ||
1343 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1344 | { |
ed9a39eb JM |
1345 | /* It's an argument being passed in a general register. */ |
1346 | regval = extract_address (val, partial_len); | |
1347 | write_register (argreg++, regval); | |
c906108c | 1348 | } |
ed9a39eb JM |
1349 | else |
1350 | { | |
1351 | /* Push the arguments onto the stack. */ | |
1352 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1353 | fp += REGISTER_SIZE; | |
1354 | } | |
1355 | ||
1356 | len -= partial_len; | |
1357 | val += partial_len; | |
c906108c SS |
1358 | } |
1359 | } | |
c906108c SS |
1360 | |
1361 | /* Return adjusted stack pointer. */ | |
1362 | return sp; | |
1363 | } | |
1364 | ||
1365 | void | |
ed9a39eb | 1366 | arm_pop_frame (void) |
c906108c | 1367 | { |
c906108c | 1368 | int regnum; |
8b93c638 | 1369 | struct frame_info *frame = get_current_frame (); |
c906108c | 1370 | |
8b93c638 JM |
1371 | if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp())) |
1372 | { | |
1373 | CORE_ADDR old_SP; | |
1374 | ||
1375 | old_SP = read_register (frame->framereg); | |
1376 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
1377 | if (frame->fsr.regs[regnum] != 0) | |
1378 | write_register (regnum, | |
c906108c SS |
1379 | read_memory_integer (frame->fsr.regs[regnum], 4)); |
1380 | ||
8b93c638 JM |
1381 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
1382 | write_register (SP_REGNUM, old_SP); | |
1383 | } | |
1384 | else | |
1385 | { | |
1386 | CORE_ADDR sp; | |
1387 | ||
1388 | sp = read_register (FP_REGNUM); | |
1389 | sp -= sizeof(CORE_ADDR); /* we don't care about this first word */ | |
1390 | ||
1391 | write_register (PC_REGNUM, read_memory_integer (sp, 4)); | |
1392 | sp -= sizeof(CORE_ADDR); | |
1393 | write_register (SP_REGNUM, read_memory_integer (sp, 4)); | |
1394 | sp -= sizeof(CORE_ADDR); | |
1395 | write_register (FP_REGNUM, read_memory_integer (sp, 4)); | |
1396 | sp -= sizeof(CORE_ADDR); | |
1397 | ||
1398 | for (regnum = 10; regnum >= 0; regnum--) | |
1399 | { | |
1400 | write_register (regnum, read_memory_integer (sp, 4)); | |
1401 | sp -= sizeof(CORE_ADDR); | |
1402 | } | |
1403 | } | |
c906108c SS |
1404 | |
1405 | flush_cached_frames (); | |
1406 | } | |
1407 | ||
1408 | static void | |
ed9a39eb | 1409 | print_fpu_flags (int flags) |
c906108c | 1410 | { |
c5aa993b JM |
1411 | if (flags & (1 << 0)) |
1412 | fputs ("IVO ", stdout); | |
1413 | if (flags & (1 << 1)) | |
1414 | fputs ("DVZ ", stdout); | |
1415 | if (flags & (1 << 2)) | |
1416 | fputs ("OFL ", stdout); | |
1417 | if (flags & (1 << 3)) | |
1418 | fputs ("UFL ", stdout); | |
1419 | if (flags & (1 << 4)) | |
1420 | fputs ("INX ", stdout); | |
1421 | putchar ('\n'); | |
c906108c SS |
1422 | } |
1423 | ||
1424 | void | |
ed9a39eb | 1425 | arm_float_info (void) |
c906108c | 1426 | { |
c5aa993b JM |
1427 | register unsigned long status = read_register (FPS_REGNUM); |
1428 | int type; | |
1429 | ||
1430 | type = (status >> 24) & 127; | |
1431 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1432 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1433 | type); |
1434 | fputs ("mask: ", stdout); | |
1435 | print_fpu_flags (status >> 16); | |
1436 | fputs ("flags: ", stdout); | |
1437 | print_fpu_flags (status); | |
c906108c SS |
1438 | } |
1439 | ||
a37b3cc0 AC |
1440 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1441 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1442 | It is thought that this is is the floating-point register format on | |
1443 | little-endian systems. */ | |
c906108c | 1444 | |
ed9a39eb JM |
1445 | static void |
1446 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1447 | { |
a37b3cc0 AC |
1448 | DOUBLEST d; |
1449 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1450 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); | |
1451 | else | |
1452 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1453 | ptr, &d); | |
1454 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1455 | } |
1456 | ||
c5aa993b | 1457 | void |
ed9a39eb | 1458 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1459 | { |
a37b3cc0 AC |
1460 | DOUBLEST d; |
1461 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
1462 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1463 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); | |
1464 | else | |
1465 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1466 | &d, dbl); | |
c906108c | 1467 | } |
ed9a39eb JM |
1468 | |
1469 | /* Nonzero if register N requires conversion from raw format to | |
1470 | virtual format. */ | |
1471 | ||
1472 | int | |
1473 | arm_register_convertible (unsigned int regnum) | |
1474 | { | |
1475 | return ((regnum - F0_REGNUM) < 8); | |
1476 | } | |
1477 | ||
1478 | /* Convert data from raw format for register REGNUM in buffer FROM to | |
1479 | virtual format with type TYPE in buffer TO. */ | |
1480 | ||
1481 | void | |
1482 | arm_register_convert_to_virtual (unsigned int regnum, struct type *type, | |
1483 | void *from, void *to) | |
1484 | { | |
1485 | double val; | |
1486 | ||
1487 | convert_from_extended (from, &val); | |
1488 | store_floating (to, TYPE_LENGTH (type), val); | |
1489 | } | |
1490 | ||
1491 | /* Convert data from virtual format with type TYPE in buffer FROM to | |
1492 | raw format for register REGNUM in buffer TO. */ | |
1493 | ||
1494 | void | |
1495 | arm_register_convert_to_raw (unsigned int regnum, struct type *type, | |
1496 | void *from, void *to) | |
1497 | { | |
1498 | double val = extract_floating (from, TYPE_LENGTH (type)); | |
1499 | ||
1500 | convert_to_extended (&val, to); | |
1501 | } | |
c906108c SS |
1502 | |
1503 | static int | |
ed9a39eb | 1504 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1505 | { |
1506 | if (cond == INST_AL || cond == INST_NV) | |
1507 | return 1; | |
1508 | ||
1509 | switch (cond) | |
1510 | { | |
1511 | case INST_EQ: | |
1512 | return ((status_reg & FLAG_Z) != 0); | |
1513 | case INST_NE: | |
1514 | return ((status_reg & FLAG_Z) == 0); | |
1515 | case INST_CS: | |
1516 | return ((status_reg & FLAG_C) != 0); | |
1517 | case INST_CC: | |
1518 | return ((status_reg & FLAG_C) == 0); | |
1519 | case INST_MI: | |
1520 | return ((status_reg & FLAG_N) != 0); | |
1521 | case INST_PL: | |
1522 | return ((status_reg & FLAG_N) == 0); | |
1523 | case INST_VS: | |
1524 | return ((status_reg & FLAG_V) != 0); | |
1525 | case INST_VC: | |
1526 | return ((status_reg & FLAG_V) == 0); | |
1527 | case INST_HI: | |
1528 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1529 | case INST_LS: | |
1530 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1531 | case INST_GE: | |
1532 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1533 | case INST_LT: | |
1534 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1535 | case INST_GT: | |
1536 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1537 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1538 | case INST_LE: |
1539 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1540 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1541 | } |
1542 | return 1; | |
1543 | } | |
1544 | ||
1545 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
1546 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1547 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1548 | #define sbits(obj,st,fn) \ | |
1549 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1550 | #define BranchDest(addr,instr) \ | |
1551 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1552 | #define ARM_PC_32 1 | |
1553 | ||
1554 | static unsigned long | |
ed9a39eb JM |
1555 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1556 | unsigned long status_reg) | |
c906108c SS |
1557 | { |
1558 | unsigned long res, shift; | |
1559 | int rm = bits (inst, 0, 3); | |
1560 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1561 | |
1562 | if (bit (inst, 4)) | |
c906108c SS |
1563 | { |
1564 | int rs = bits (inst, 8, 11); | |
1565 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1566 | } | |
1567 | else | |
1568 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1569 | |
1570 | res = (rm == 15 | |
c906108c | 1571 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1572 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1573 | : read_register (rm)); |
1574 | ||
1575 | switch (shifttype) | |
1576 | { | |
c5aa993b | 1577 | case 0: /* LSL */ |
c906108c SS |
1578 | res = shift >= 32 ? 0 : res << shift; |
1579 | break; | |
c5aa993b JM |
1580 | |
1581 | case 1: /* LSR */ | |
c906108c SS |
1582 | res = shift >= 32 ? 0 : res >> shift; |
1583 | break; | |
1584 | ||
c5aa993b JM |
1585 | case 2: /* ASR */ |
1586 | if (shift >= 32) | |
1587 | shift = 31; | |
c906108c SS |
1588 | res = ((res & 0x80000000L) |
1589 | ? ~((~res) >> shift) : res >> shift); | |
1590 | break; | |
1591 | ||
c5aa993b | 1592 | case 3: /* ROR/RRX */ |
c906108c SS |
1593 | shift &= 31; |
1594 | if (shift == 0) | |
1595 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1596 | else | |
c5aa993b | 1597 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1598 | break; |
1599 | } | |
1600 | ||
1601 | return res & 0xffffffff; | |
1602 | } | |
1603 | ||
c906108c SS |
1604 | /* Return number of 1-bits in VAL. */ |
1605 | ||
1606 | static int | |
ed9a39eb | 1607 | bitcount (unsigned long val) |
c906108c SS |
1608 | { |
1609 | int nbits; | |
1610 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1611 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1612 | return nbits; |
1613 | } | |
1614 | ||
c906108c | 1615 | static CORE_ADDR |
ed9a39eb | 1616 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1617 | { |
c5aa993b | 1618 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1619 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1620 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1621 | unsigned long offset; |
1622 | ||
1623 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1624 | { | |
1625 | CORE_ADDR sp; | |
1626 | ||
1627 | /* Fetch the saved PC from the stack. It's stored above | |
1628 | all of the other registers. */ | |
1629 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1630 | sp = read_register (SP_REGNUM); | |
1631 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1632 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1633 | if (nextpc == pc) | |
1634 | error ("Infinite loop detected"); | |
1635 | } | |
1636 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1637 | { | |
1638 | unsigned long status = read_register (PS_REGNUM); | |
c5aa993b | 1639 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1640 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1641 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1642 | } | |
1643 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1644 | { | |
1645 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1646 | } | |
1647 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1648 | { | |
1649 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1650 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1651 | nextpc = pc_val + offset; |
1652 | } | |
1653 | ||
1654 | return nextpc; | |
1655 | } | |
1656 | ||
c906108c | 1657 | CORE_ADDR |
ed9a39eb | 1658 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1659 | { |
1660 | unsigned long pc_val; | |
1661 | unsigned long this_instr; | |
1662 | unsigned long status; | |
1663 | CORE_ADDR nextpc; | |
1664 | ||
1665 | if (arm_pc_is_thumb (pc)) | |
1666 | return thumb_get_next_pc (pc); | |
1667 | ||
1668 | pc_val = (unsigned long) pc; | |
1669 | this_instr = read_memory_integer (pc, 4); | |
1670 | status = read_register (PS_REGNUM); | |
c5aa993b | 1671 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1672 | |
1673 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1674 | { | |
1675 | switch (bits (this_instr, 24, 27)) | |
1676 | { | |
c5aa993b JM |
1677 | case 0x0: |
1678 | case 0x1: /* data processing */ | |
1679 | case 0x2: | |
1680 | case 0x3: | |
c906108c SS |
1681 | { |
1682 | unsigned long operand1, operand2, result = 0; | |
1683 | unsigned long rn; | |
1684 | int c; | |
c5aa993b | 1685 | |
c906108c SS |
1686 | if (bits (this_instr, 12, 15) != 15) |
1687 | break; | |
1688 | ||
1689 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1690 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1691 | error ("Illegal update to pc in instruction"); |
1692 | ||
1693 | /* Multiply into PC */ | |
1694 | c = (status & FLAG_C) ? 1 : 0; | |
1695 | rn = bits (this_instr, 16, 19); | |
1696 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1697 | |
c906108c SS |
1698 | if (bit (this_instr, 25)) |
1699 | { | |
1700 | unsigned long immval = bits (this_instr, 0, 7); | |
1701 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1702 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1703 | & 0xffffffff; | |
c906108c | 1704 | } |
c5aa993b | 1705 | else /* operand 2 is a shifted register */ |
c906108c | 1706 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1707 | |
c906108c SS |
1708 | switch (bits (this_instr, 21, 24)) |
1709 | { | |
c5aa993b | 1710 | case 0x0: /*and */ |
c906108c SS |
1711 | result = operand1 & operand2; |
1712 | break; | |
1713 | ||
c5aa993b | 1714 | case 0x1: /*eor */ |
c906108c SS |
1715 | result = operand1 ^ operand2; |
1716 | break; | |
1717 | ||
c5aa993b | 1718 | case 0x2: /*sub */ |
c906108c SS |
1719 | result = operand1 - operand2; |
1720 | break; | |
1721 | ||
c5aa993b | 1722 | case 0x3: /*rsb */ |
c906108c SS |
1723 | result = operand2 - operand1; |
1724 | break; | |
1725 | ||
c5aa993b | 1726 | case 0x4: /*add */ |
c906108c SS |
1727 | result = operand1 + operand2; |
1728 | break; | |
1729 | ||
c5aa993b | 1730 | case 0x5: /*adc */ |
c906108c SS |
1731 | result = operand1 + operand2 + c; |
1732 | break; | |
1733 | ||
c5aa993b | 1734 | case 0x6: /*sbc */ |
c906108c SS |
1735 | result = operand1 - operand2 + c; |
1736 | break; | |
1737 | ||
c5aa993b | 1738 | case 0x7: /*rsc */ |
c906108c SS |
1739 | result = operand2 - operand1 + c; |
1740 | break; | |
1741 | ||
c5aa993b JM |
1742 | case 0x8: |
1743 | case 0x9: | |
1744 | case 0xa: | |
1745 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1746 | result = (unsigned long) nextpc; |
1747 | break; | |
1748 | ||
c5aa993b | 1749 | case 0xc: /*orr */ |
c906108c SS |
1750 | result = operand1 | operand2; |
1751 | break; | |
1752 | ||
c5aa993b | 1753 | case 0xd: /*mov */ |
c906108c SS |
1754 | /* Always step into a function. */ |
1755 | result = operand2; | |
c5aa993b | 1756 | break; |
c906108c | 1757 | |
c5aa993b | 1758 | case 0xe: /*bic */ |
c906108c SS |
1759 | result = operand1 & ~operand2; |
1760 | break; | |
1761 | ||
c5aa993b | 1762 | case 0xf: /*mvn */ |
c906108c SS |
1763 | result = ~operand2; |
1764 | break; | |
1765 | } | |
1766 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1767 | ||
1768 | if (nextpc == pc) | |
1769 | error ("Infinite loop detected"); | |
1770 | break; | |
1771 | } | |
c5aa993b JM |
1772 | |
1773 | case 0x4: | |
1774 | case 0x5: /* data transfer */ | |
1775 | case 0x6: | |
1776 | case 0x7: | |
c906108c SS |
1777 | if (bit (this_instr, 20)) |
1778 | { | |
1779 | /* load */ | |
1780 | if (bits (this_instr, 12, 15) == 15) | |
1781 | { | |
1782 | /* rd == pc */ | |
c5aa993b | 1783 | unsigned long rn; |
c906108c | 1784 | unsigned long base; |
c5aa993b | 1785 | |
c906108c SS |
1786 | if (bit (this_instr, 22)) |
1787 | error ("Illegal update to pc in instruction"); | |
1788 | ||
1789 | /* byte write to PC */ | |
1790 | rn = bits (this_instr, 16, 19); | |
1791 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1792 | if (bit (this_instr, 24)) | |
1793 | { | |
1794 | /* pre-indexed */ | |
1795 | int c = (status & FLAG_C) ? 1 : 0; | |
1796 | unsigned long offset = | |
c5aa993b | 1797 | (bit (this_instr, 25) |
ed9a39eb | 1798 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1799 | : bits (this_instr, 0, 11)); |
c906108c SS |
1800 | |
1801 | if (bit (this_instr, 23)) | |
1802 | base += offset; | |
1803 | else | |
1804 | base -= offset; | |
1805 | } | |
c5aa993b | 1806 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1807 | 4); |
c5aa993b | 1808 | |
c906108c SS |
1809 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1810 | ||
1811 | if (nextpc == pc) | |
1812 | error ("Infinite loop detected"); | |
1813 | } | |
1814 | } | |
1815 | break; | |
c5aa993b JM |
1816 | |
1817 | case 0x8: | |
1818 | case 0x9: /* block transfer */ | |
c906108c SS |
1819 | if (bit (this_instr, 20)) |
1820 | { | |
1821 | /* LDM */ | |
1822 | if (bit (this_instr, 15)) | |
1823 | { | |
1824 | /* loading pc */ | |
1825 | int offset = 0; | |
1826 | ||
1827 | if (bit (this_instr, 23)) | |
1828 | { | |
1829 | /* up */ | |
1830 | unsigned long reglist = bits (this_instr, 0, 14); | |
1831 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1832 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1833 | offset += 4; |
1834 | } | |
1835 | else if (bit (this_instr, 24)) | |
1836 | offset = -4; | |
c5aa993b | 1837 | |
c906108c | 1838 | { |
c5aa993b JM |
1839 | unsigned long rn_val = |
1840 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1841 | nextpc = |
1842 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1843 | + offset), |
c906108c SS |
1844 | 4); |
1845 | } | |
1846 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1847 | if (nextpc == pc) | |
1848 | error ("Infinite loop detected"); | |
1849 | } | |
1850 | } | |
1851 | break; | |
c5aa993b JM |
1852 | |
1853 | case 0xb: /* branch & link */ | |
1854 | case 0xa: /* branch */ | |
c906108c SS |
1855 | { |
1856 | nextpc = BranchDest (pc, this_instr); | |
1857 | ||
1858 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1859 | if (nextpc == pc) | |
1860 | error ("Infinite loop detected"); | |
1861 | break; | |
1862 | } | |
c5aa993b JM |
1863 | |
1864 | case 0xc: | |
1865 | case 0xd: | |
1866 | case 0xe: /* coproc ops */ | |
1867 | case 0xf: /* SWI */ | |
c906108c SS |
1868 | break; |
1869 | ||
1870 | default: | |
1871 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1872 | return (pc); | |
1873 | } | |
1874 | } | |
1875 | ||
1876 | return nextpc; | |
1877 | } | |
1878 | ||
1879 | #include "bfd-in2.h" | |
1880 | #include "libcoff.h" | |
1881 | ||
1882 | static int | |
ed9a39eb | 1883 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1884 | { |
1885 | if (arm_pc_is_thumb (memaddr)) | |
1886 | { | |
c5aa993b JM |
1887 | static asymbol *asym; |
1888 | static combined_entry_type ce; | |
1889 | static struct coff_symbol_struct csym; | |
1890 | static struct _bfd fake_bfd; | |
1891 | static bfd_target fake_target; | |
c906108c SS |
1892 | |
1893 | if (csym.native == NULL) | |
1894 | { | |
1895 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1896 | solely so that the code in print_insn_little_arm() and | |
1897 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1898 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
c5aa993b JM |
1899 | |
1900 | fake_target.flavour = bfd_target_coff_flavour; | |
1901 | fake_bfd.xvec = &fake_target; | |
c906108c | 1902 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1903 | csym.native = &ce; |
1904 | csym.symbol.the_bfd = &fake_bfd; | |
1905 | csym.symbol.name = "fake"; | |
1906 | asym = (asymbol *) & csym; | |
c906108c | 1907 | } |
c5aa993b | 1908 | |
c906108c | 1909 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1910 | info->symbols = &asym; |
c906108c SS |
1911 | } |
1912 | else | |
1913 | info->symbols = NULL; | |
c5aa993b | 1914 | |
c906108c SS |
1915 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1916 | return print_insn_big_arm (memaddr, info); | |
1917 | else | |
1918 | return print_insn_little_arm (memaddr, info); | |
1919 | } | |
1920 | ||
ed9a39eb JM |
1921 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the |
1922 | program counter value to determine whether a 16-bit or 32-bit | |
1923 | breakpoint should be used. It returns a pointer to a string of | |
1924 | bytes that encode a breakpoint instruction, stores the length of | |
1925 | the string to *lenptr, and adjusts the program counter (if | |
1926 | necessary) to point to the actual memory location where the | |
c906108c SS |
1927 | breakpoint should be inserted. */ |
1928 | ||
1929 | unsigned char * | |
ed9a39eb | 1930 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c SS |
1931 | { |
1932 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
1933 | { | |
1934 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1935 | { |
1936 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1937 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1938 | *lenptr = sizeof (thumb_breakpoint); | |
1939 | return thumb_breakpoint; | |
1940 | } | |
c906108c | 1941 | else |
c5aa993b JM |
1942 | { |
1943 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1944 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1945 | *lenptr = sizeof (thumb_breakpoint); | |
1946 | return thumb_breakpoint; | |
1947 | } | |
c906108c SS |
1948 | } |
1949 | else | |
1950 | { | |
1951 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1952 | { |
1953 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
1954 | *lenptr = sizeof (arm_breakpoint); | |
1955 | return arm_breakpoint; | |
1956 | } | |
c906108c | 1957 | else |
c5aa993b JM |
1958 | { |
1959 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
1960 | *lenptr = sizeof (arm_breakpoint); | |
1961 | return arm_breakpoint; | |
1962 | } | |
c906108c SS |
1963 | } |
1964 | } | |
ed9a39eb JM |
1965 | |
1966 | /* Extract from an array REGBUF containing the (raw) register state a | |
1967 | function return value of type TYPE, and copy that, in virtual | |
1968 | format, into VALBUF. */ | |
1969 | ||
1970 | void | |
1971 | arm_extract_return_value (struct type *type, | |
1972 | char regbuf[REGISTER_BYTES], | |
1973 | char *valbuf) | |
1974 | { | |
1975 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
1976 | convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); | |
1977 | else | |
1978 | memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); | |
1979 | } | |
1980 | ||
1981 | /* Return non-zero if the PC is inside a thumb call thunk. */ | |
c906108c SS |
1982 | |
1983 | int | |
ed9a39eb | 1984 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
1985 | { |
1986 | CORE_ADDR start_addr; | |
1987 | ||
ed9a39eb JM |
1988 | /* Find the starting address of the function containing the PC. If |
1989 | the caller didn't give us a name, look it up at the same time. */ | |
c906108c SS |
1990 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
1991 | return 0; | |
1992 | ||
1993 | return strncmp (name, "_call_via_r", 11) == 0; | |
1994 | } | |
1995 | ||
ed9a39eb JM |
1996 | /* If PC is in a Thumb call or return stub, return the address of the |
1997 | target PC, which is in a register. The thunk functions are called | |
1998 | _called_via_xx, where x is the register name. The possible names | |
1999 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2000 | |
2001 | CORE_ADDR | |
ed9a39eb | 2002 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2003 | { |
c5aa993b | 2004 | char *name; |
c906108c SS |
2005 | CORE_ADDR start_addr; |
2006 | ||
2007 | /* Find the starting address and name of the function containing the PC. */ | |
2008 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2009 | return 0; | |
2010 | ||
2011 | /* Call thunks always start with "_call_via_". */ | |
2012 | if (strncmp (name, "_call_via_", 10) == 0) | |
2013 | { | |
ed9a39eb JM |
2014 | /* Use the name suffix to determine which register contains the |
2015 | target PC. */ | |
c5aa993b JM |
2016 | static char *table[15] = |
2017 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2018 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2019 | }; | |
c906108c SS |
2020 | int regno; |
2021 | ||
2022 | for (regno = 0; regno <= 14; regno++) | |
2023 | if (strcmp (&name[10], table[regno]) == 0) | |
2024 | return read_register (regno); | |
2025 | } | |
ed9a39eb | 2026 | |
c5aa993b | 2027 | return 0; /* not a stub */ |
c906108c SS |
2028 | } |
2029 | ||
bc90b915 FN |
2030 | /* If the user changes the register disassembly flavor used for info register |
2031 | and other commands, we have to also switch the flavor used in opcodes | |
2032 | for disassembly output. | |
2033 | This function is run in the set disassembly_flavor command, and does that. */ | |
2034 | ||
2035 | static void | |
2036 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2037 | struct cmd_list_element *c) | |
2038 | { | |
2039 | set_disassembly_flavor (); | |
2040 | } | |
2041 | \f | |
2042 | static void | |
2043 | set_disassembly_flavor (void) | |
2044 | { | |
2045 | const char *setname, *setdesc, **regnames; | |
2046 | int numregs, j; | |
2047 | ||
2048 | /* Find the flavor that the user wants in the opcodes table. */ | |
2049 | int current = 0; | |
2050 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2051 | while ((disassembly_flavor != setname) | |
2052 | && (current < num_flavor_options)) | |
2053 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2054 | current_option = current; | |
2055 | ||
2056 | /* Fill our copy. */ | |
2057 | for (j = 0; j < numregs; j++) | |
2058 | arm_register_names[j] = (char *) regnames[j]; | |
2059 | ||
2060 | /* Adjust case. */ | |
2061 | if (isupper (*regnames[PC_REGNUM])) | |
2062 | { | |
2063 | arm_register_names[FPS_REGNUM] = "FPS"; | |
2064 | arm_register_names[PS_REGNUM] = "CPSR"; | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | arm_register_names[FPS_REGNUM] = "fps"; | |
2069 | arm_register_names[PS_REGNUM] = "cpsr"; | |
2070 | } | |
2071 | ||
2072 | /* Synchronize the disassembler. */ | |
2073 | set_arm_regname_option (current); | |
2074 | } | |
2075 | ||
2076 | /* arm_othernames implements the "othernames" command. This is kind | |
2077 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2078 | also used for the x86 gdb. I will keep this around, however, in | |
2079 | case anyone is actually using it. */ | |
2080 | ||
2081 | static void | |
2082 | arm_othernames (char *names, int n) | |
2083 | { | |
2084 | /* Circle through the various flavors. */ | |
2085 | current_option = (current_option + 1) % num_flavor_options; | |
2086 | ||
2087 | disassembly_flavor = valid_flavors[current_option]; | |
2088 | set_disassembly_flavor (); | |
2089 | } | |
2090 | ||
c906108c | 2091 | void |
ed9a39eb | 2092 | _initialize_arm_tdep (void) |
c906108c | 2093 | { |
bc90b915 FN |
2094 | struct ui_file *stb; |
2095 | long length; | |
96baa820 | 2096 | struct cmd_list_element *new_cmd; |
53904c9e AC |
2097 | const char *setname; |
2098 | const char *setdesc; | |
2099 | const char **regnames; | |
bc90b915 FN |
2100 | int numregs, i, j; |
2101 | static char *helptext; | |
085dd6e6 | 2102 | |
c906108c | 2103 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 2104 | |
bc90b915 FN |
2105 | /* Get the number of possible sets of register names defined in opcodes. */ |
2106 | num_flavor_options = get_arm_regname_num_options (); | |
2107 | ||
085dd6e6 | 2108 | /* Sync the opcode insn printer with our register viewer: */ |
bc90b915 | 2109 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2110 | |
bc90b915 FN |
2111 | /* Begin creating the help text. */ |
2112 | stb = mem_fileopen (); | |
2113 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
2114 | The valid values are:\n"); | |
ed9a39eb | 2115 | |
bc90b915 FN |
2116 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
2117 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); | |
2118 | for (i = 0; i < num_flavor_options; i++) | |
2119 | { | |
2120 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 2121 | valid_flavors[i] = setname; |
bc90b915 FN |
2122 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
2123 | setdesc); | |
2124 | /* Copy the default names (if found) and synchronize disassembler. */ | |
2125 | if (!strcmp (setname, "std")) | |
2126 | { | |
53904c9e | 2127 | disassembly_flavor = setname; |
bc90b915 FN |
2128 | current_option = i; |
2129 | for (j = 0; j < numregs; j++) | |
2130 | arm_register_names[j] = (char *) regnames[j]; | |
2131 | set_arm_regname_option (i); | |
2132 | } | |
2133 | } | |
2134 | /* Mark the end of valid options. */ | |
2135 | valid_flavors[num_flavor_options] = NULL; | |
c906108c | 2136 | |
bc90b915 FN |
2137 | /* Finish the creation of the help text. */ |
2138 | fprintf_unfiltered (stb, "The default is \"std\"."); | |
2139 | helptext = ui_file_xstrdup (stb, &length); | |
2140 | ui_file_delete (stb); | |
ed9a39eb | 2141 | |
bc90b915 | 2142 | /* Add the disassembly-flavor command */ |
96baa820 | 2143 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 2144 | valid_flavors, |
1ed2a135 | 2145 | &disassembly_flavor, |
bc90b915 | 2146 | helptext, |
ed9a39eb | 2147 | &setlist); |
96baa820 | 2148 | new_cmd->function.sfunc = set_disassembly_flavor_sfunc; |
ed9a39eb JM |
2149 | add_show_from_set (new_cmd, &showlist); |
2150 | ||
c906108c SS |
2151 | /* ??? Maybe this should be a boolean. */ |
2152 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 2153 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 2154 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 2155 | &showlist); |
c906108c | 2156 | |
bc90b915 FN |
2157 | /* Add the deprecated "othernames" command */ |
2158 | ||
2159 | add_com ("othernames", class_obscure, arm_othernames, | |
2160 | "Switch to the next set of register names."); | |
c906108c SS |
2161 | } |
2162 | ||
ed9a39eb JM |
2163 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2164 | function. */ | |
2165 | ||
c906108c | 2166 | int |
c5aa993b | 2167 | coff_sym_is_thumb (int val) |
c906108c | 2168 | { |
c5aa993b JM |
2169 | return (val == C_THUMBEXT || |
2170 | val == C_THUMBSTAT || | |
2171 | val == C_THUMBEXTFUNC || | |
2172 | val == C_THUMBSTATFUNC || | |
2173 | val == C_THUMBLABEL); | |
c906108c | 2174 | } |