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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
756fe439 | 3 | 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
34e8f22d RE |
39 | |
40 | #include "arm-tdep.h" | |
26216b98 | 41 | #include "gdb/sim-arm.h" |
34e8f22d | 42 | |
082fc60d RE |
43 | #include "elf-bfd.h" |
44 | #include "coff/internal.h" | |
97e03143 | 45 | #include "elf/arm.h" |
c906108c | 46 | |
26216b98 AC |
47 | #include "gdb_assert.h" |
48 | ||
6529d2dd AC |
49 | static int arm_debug; |
50 | ||
2a451106 KB |
51 | /* Each OS has a different mechanism for accessing the various |
52 | registers stored in the sigcontext structure. | |
53 | ||
54 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
55 | function pointer) which may be used to determine the addresses | |
56 | of the various saved registers in the sigcontext structure. | |
57 | ||
58 | For the ARM target, there are three parameters to this function. | |
59 | The first is the pc value of the frame under consideration, the | |
60 | second the stack pointer of this frame, and the last is the | |
61 | register number to fetch. | |
62 | ||
63 | If the tm.h file does not define this macro, then it's assumed that | |
64 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
65 | be 0. | |
66 | ||
67 | When it comes time to multi-arching this code, see the identically | |
68 | named machinery in ia64-tdep.c for an example of how it could be | |
69 | done. It should not be necessary to modify the code below where | |
70 | this macro is used. */ | |
71 | ||
3bb04bdd AC |
72 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
73 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
74 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
75 | #endif | |
76 | #else | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
78 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
79 | #endif |
80 | ||
082fc60d RE |
81 | /* Macros for setting and testing a bit in a minimal symbol that marks |
82 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 83 | is used for this purpose. |
082fc60d RE |
84 | |
85 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 86 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
87 | |
88 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
89 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
90 | | 0x80000000) | |
91 | ||
92 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
93 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
94 | ||
afd7eef0 RE |
95 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
96 | static struct cmd_list_element *setarmcmdlist = NULL; | |
97 | static struct cmd_list_element *showarmcmdlist = NULL; | |
98 | ||
fd50bc42 RE |
99 | /* The type of floating-point to use. Keep this in sync with enum |
100 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
101 | static const char *fp_model_strings[] = | |
102 | { | |
103 | "auto", | |
104 | "softfpa", | |
105 | "fpa", | |
106 | "softvfp", | |
107 | "vfp" | |
108 | }; | |
109 | ||
110 | /* A variable that can be configured by the user. */ | |
111 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
112 | static const char *current_fp_model = "auto"; | |
113 | ||
94c30b78 | 114 | /* Number of different reg name sets (options). */ |
afd7eef0 | 115 | static int num_disassembly_options; |
bc90b915 FN |
116 | |
117 | /* We have more registers than the disassembler as gdb can print the value | |
118 | of special registers as well. | |
119 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 120 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 121 | |
94c30b78 | 122 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 123 | static char * arm_register_name_strings[] = |
da59e081 JM |
124 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
125 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
126 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
127 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
128 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
129 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 130 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 131 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 132 | |
afd7eef0 RE |
133 | /* Valid register name styles. */ |
134 | static const char **valid_disassembly_styles; | |
ed9a39eb | 135 | |
afd7eef0 RE |
136 | /* Disassembly style to use. Default to "std" register names. */ |
137 | static const char *disassembly_style; | |
94c30b78 | 138 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 139 | static int current_option; |
96baa820 | 140 | |
ed9a39eb | 141 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
142 | style. */ |
143 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 144 | struct cmd_list_element *); |
afd7eef0 | 145 | static void set_disassembly_style (void); |
ed9a39eb | 146 | |
b508a996 RE |
147 | static void convert_from_extended (const struct floatformat *, const void *, |
148 | void *); | |
149 | static void convert_to_extended (const struct floatformat *, void *, | |
150 | const void *); | |
ed9a39eb | 151 | |
9b8d791a | 152 | struct arm_prologue_cache |
c3b4394c | 153 | { |
eb5492fa DJ |
154 | /* The stack pointer at the time this frame was created; i.e. the |
155 | caller's stack pointer when this function was called. It is used | |
156 | to identify this frame. */ | |
157 | CORE_ADDR prev_sp; | |
158 | ||
159 | /* The frame base for this frame is just prev_sp + frame offset - | |
160 | frame size. FRAMESIZE is the size of this stack frame, and | |
161 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
162 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
163 | ||
c3b4394c RE |
164 | int framesize; |
165 | int frameoffset; | |
eb5492fa DJ |
166 | |
167 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 168 | int framereg; |
eb5492fa DJ |
169 | |
170 | /* Saved register offsets. */ | |
171 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 172 | }; |
ed9a39eb | 173 | |
bc90b915 FN |
174 | /* Addresses for calling Thumb functions have the bit 0 set. |
175 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
176 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
177 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
178 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
179 | ||
94c30b78 | 180 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
181 | |
182 | int arm_apcs_32 = 1; | |
183 | ||
ed9a39eb JM |
184 | /* Flag set by arm_fix_call_dummy that tells whether the target |
185 | function is a Thumb function. This flag is checked by | |
186 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
187 | its use in valops.c) to pass the function address as an additional | |
188 | parameter. */ | |
c906108c SS |
189 | |
190 | static int target_is_thumb; | |
191 | ||
ed9a39eb JM |
192 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
193 | function is a Thumb function. This flag is checked by | |
e4a2df64 | 194 | arm_pc_is_thumb. */ |
c906108c SS |
195 | |
196 | static int caller_is_thumb; | |
197 | ||
ed9a39eb JM |
198 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
199 | function. */ | |
c906108c | 200 | |
34e8f22d | 201 | int |
2a451106 | 202 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 203 | { |
c5aa993b | 204 | struct minimal_symbol *sym; |
c906108c | 205 | |
ed9a39eb | 206 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
207 | if (IS_THUMB_ADDR (memaddr)) |
208 | return 1; | |
209 | ||
ed9a39eb | 210 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
211 | sym = lookup_minimal_symbol_by_pc (memaddr); |
212 | if (sym) | |
213 | { | |
c5aa993b | 214 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
215 | } |
216 | else | |
ed9a39eb JM |
217 | { |
218 | return 0; | |
219 | } | |
c906108c SS |
220 | } |
221 | ||
ed9a39eb JM |
222 | /* Determine if the program counter specified in MEMADDR is in a call |
223 | dummy being called from a Thumb function. */ | |
c906108c | 224 | |
34e8f22d | 225 | int |
2a451106 | 226 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 227 | { |
c5aa993b | 228 | CORE_ADDR sp = read_sp (); |
c906108c | 229 | |
dfcd3bfb JM |
230 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
231 | is the best we can do. We are trying to determine if the pc is on | |
232 | the stack, which (hopefully) will only happen in a call dummy. | |
233 | We hope the current stack pointer is not so far alway from the dummy | |
234 | frame location (true if we have not pushed large data structures or | |
235 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 236 | code regions as part of the stack (true for most practical purposes). */ |
30a4a8e0 | 237 | if (deprecated_pc_in_call_dummy (memaddr)) |
c906108c SS |
238 | return caller_is_thumb; |
239 | else | |
240 | return 0; | |
241 | } | |
242 | ||
181c1381 | 243 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 244 | static CORE_ADDR |
ed9a39eb | 245 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 246 | { |
a3a2ee65 JT |
247 | if (arm_apcs_32) |
248 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 249 | else |
a3a2ee65 | 250 | return (val & 0x03fffffc); |
c906108c SS |
251 | } |
252 | ||
181c1381 RE |
253 | /* When reading symbols, we need to zap the low bit of the address, |
254 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 255 | static CORE_ADDR |
181c1381 RE |
256 | arm_smash_text_address (CORE_ADDR val) |
257 | { | |
258 | return val & ~1; | |
259 | } | |
260 | ||
34e8f22d RE |
261 | /* Immediately after a function call, return the saved pc. Can't |
262 | always go through the frames for this because on some machines the | |
263 | new frame is not set up until the new function executes some | |
264 | instructions. */ | |
265 | ||
266 | static CORE_ADDR | |
ed9a39eb | 267 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 268 | { |
34e8f22d | 269 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
270 | } |
271 | ||
272 | /* A typical Thumb prologue looks like this: | |
c5aa993b JM |
273 | push {r7, lr} |
274 | add sp, sp, #-28 | |
275 | add r7, sp, #12 | |
c906108c | 276 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
277 | mov r7, sp |
278 | ||
279 | or like this: | |
280 | push {r7, lr} | |
281 | mov r7, sp | |
282 | sub sp, #12 | |
283 | ||
284 | or, on tpcs, like this: | |
285 | sub sp,#16 | |
286 | push {r7, lr} | |
287 | (many instructions) | |
288 | mov r7, sp | |
289 | sub sp, #12 | |
290 | ||
291 | There is always one instruction of three classes: | |
292 | 1 - push | |
293 | 2 - setting of r7 | |
294 | 3 - adjusting of sp | |
295 | ||
296 | When we have found at least one of each class we are done with the prolog. | |
297 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 298 | */ |
c906108c SS |
299 | |
300 | static CORE_ADDR | |
c7885828 | 301 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
302 | { |
303 | CORE_ADDR current_pc; | |
da3c6d4a MS |
304 | /* findmask: |
305 | bit 0 - push { rlist } | |
306 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
307 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
308 | */ | |
309 | int findmask = 0; | |
310 | ||
94c30b78 MS |
311 | for (current_pc = pc; |
312 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 313 | current_pc += 2) |
c906108c SS |
314 | { |
315 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
316 | ||
94c30b78 | 317 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 318 | { |
94c30b78 | 319 | findmask |= 1; /* push found */ |
da59e081 | 320 | } |
da3c6d4a MS |
321 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
322 | sub sp, #simm */ | |
da59e081 | 323 | { |
94c30b78 | 324 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
325 | continue; |
326 | else | |
94c30b78 | 327 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
328 | } |
329 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
330 | { | |
94c30b78 | 331 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
332 | } |
333 | else if (insn == 0x466f) /* mov r7, sp */ | |
334 | { | |
94c30b78 | 335 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 336 | } |
3d74b771 FF |
337 | else if (findmask == (4+2+1)) |
338 | { | |
da3c6d4a MS |
339 | /* We have found one of each type of prologue instruction */ |
340 | break; | |
3d74b771 | 341 | } |
da59e081 | 342 | else |
94c30b78 | 343 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 344 | instruction from outside the prolog scheduled here for |
94c30b78 | 345 | optimization. */ |
da3c6d4a | 346 | continue; |
c906108c SS |
347 | } |
348 | ||
349 | return current_pc; | |
350 | } | |
351 | ||
da3c6d4a MS |
352 | /* Advance the PC across any function entry prologue instructions to |
353 | reach some "real" code. | |
34e8f22d RE |
354 | |
355 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 356 | prologue: |
c906108c | 357 | |
c5aa993b JM |
358 | mov ip, sp |
359 | [stmfd sp!, {a1,a2,a3,a4}] | |
360 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
361 | [stfe f7, [sp, #-12]!] |
362 | [stfe f6, [sp, #-12]!] | |
363 | [stfe f5, [sp, #-12]!] | |
364 | [stfe f4, [sp, #-12]!] | |
365 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 366 | |
34e8f22d | 367 | static CORE_ADDR |
ed9a39eb | 368 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
369 | { |
370 | unsigned long inst; | |
371 | CORE_ADDR skip_pc; | |
b8d5e71d | 372 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 373 | char *func_name; |
c906108c SS |
374 | struct symtab_and_line sal; |
375 | ||
848cfffb | 376 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 377 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
378 | return pc; |
379 | ||
96baa820 | 380 | /* See what the symbol table says. */ |
ed9a39eb | 381 | |
50f6fb4b | 382 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 383 | { |
50f6fb4b CV |
384 | struct symbol *sym; |
385 | ||
386 | /* Found a function. */ | |
176620f1 | 387 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
388 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
389 | { | |
94c30b78 | 390 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
391 | sal = find_pc_line (func_addr, 0); |
392 | if ((sal.line != 0) && (sal.end < func_end)) | |
393 | return sal.end; | |
394 | } | |
c906108c SS |
395 | } |
396 | ||
397 | /* Check if this is Thumb code. */ | |
398 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 399 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
400 | |
401 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 402 | by disassembling the instructions. */ |
c906108c | 403 | |
b8d5e71d MS |
404 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
405 | if (func_end == 0 || func_end > pc + 64) | |
406 | func_end = pc + 64; | |
c906108c | 407 | |
b8d5e71d | 408 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 409 | { |
f43845b3 | 410 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 411 | |
b8d5e71d MS |
412 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
413 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
414 | continue; | |
c906108c | 415 | |
28cd8767 JG |
416 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
417 | continue; | |
418 | ||
419 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
420 | continue; | |
421 | ||
b8d5e71d MS |
422 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
423 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
424 | continue; | |
c906108c | 425 | |
b8d5e71d MS |
426 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
427 | continue; | |
c906108c | 428 | |
b8d5e71d MS |
429 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
430 | continue; | |
11d3b27d | 431 | |
b8d5e71d MS |
432 | /* Any insns after this point may float into the code, if it makes |
433 | for better instruction scheduling, so we skip them only if we | |
434 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 435 | |
b8d5e71d MS |
436 | /* We may have either one sfmfd instruction here, or several stfe |
437 | insns, depending on the version of floating point code we | |
438 | support. */ | |
439 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
440 | continue; | |
441 | ||
442 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
443 | continue; | |
444 | ||
445 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
446 | continue; | |
447 | ||
448 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
449 | continue; | |
450 | ||
451 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
452 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
453 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
454 | continue; | |
455 | ||
456 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
457 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
458 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
459 | continue; | |
460 | ||
461 | /* Un-recognized instruction; stop scanning. */ | |
462 | break; | |
f43845b3 | 463 | } |
c906108c | 464 | |
b8d5e71d | 465 | return skip_pc; /* End of prologue */ |
c906108c | 466 | } |
94c30b78 | 467 | |
c5aa993b | 468 | /* *INDENT-OFF* */ |
c906108c SS |
469 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
470 | This function decodes a Thumb function prologue to determine: | |
471 | 1) the size of the stack frame | |
472 | 2) which registers are saved on it | |
473 | 3) the offsets of saved regs | |
474 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 475 | |
da59e081 JM |
476 | A typical Thumb function prologue would create this stack frame |
477 | (offsets relative to FP) | |
c906108c SS |
478 | old SP -> 24 stack parameters |
479 | 20 LR | |
480 | 16 R7 | |
481 | R7 -> 0 local variables (16 bytes) | |
482 | SP -> -12 additional stack space (12 bytes) | |
483 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
484 | 12 bytes. The frame register is R7. |
485 | ||
da3c6d4a MS |
486 | The comments for thumb_skip_prolog() describe the algorithm we use |
487 | to detect the end of the prolog. */ | |
c5aa993b JM |
488 | /* *INDENT-ON* */ |
489 | ||
c906108c | 490 | static void |
eb5492fa | 491 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
492 | { |
493 | CORE_ADDR prologue_start; | |
494 | CORE_ADDR prologue_end; | |
495 | CORE_ADDR current_pc; | |
94c30b78 | 496 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
497 | int saved_reg[16]; |
498 | /* findmask: | |
499 | bit 0 - push { rlist } | |
500 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
501 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
502 | */ | |
503 | int findmask = 0; | |
c5aa993b | 504 | int i; |
c906108c | 505 | |
eb5492fa | 506 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
507 | { |
508 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
509 | ||
94c30b78 | 510 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 511 | prologue_end = prev_pc; |
c906108c | 512 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 513 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
514 | } |
515 | else | |
da3c6d4a MS |
516 | /* We're in the boondocks: allow for |
517 | 16 pushes, an add, and "mv fp,sp". */ | |
518 | prologue_end = prologue_start + 40; | |
c906108c | 519 | |
eb5492fa | 520 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
521 | |
522 | /* Initialize the saved register map. When register H is copied to | |
523 | register L, we will put H in saved_reg[L]. */ | |
524 | for (i = 0; i < 16; i++) | |
525 | saved_reg[i] = i; | |
526 | ||
527 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
528 | frame pointer, adjust the stack pointer, and save registers. |
529 | Do this until all basic prolog instructions are found. */ | |
c906108c | 530 | |
9b8d791a | 531 | cache->framesize = 0; |
da59e081 JM |
532 | for (current_pc = prologue_start; |
533 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
534 | current_pc += 2) | |
c906108c SS |
535 | { |
536 | unsigned short insn; | |
537 | int regno; | |
538 | int offset; | |
539 | ||
540 | insn = read_memory_unsigned_integer (current_pc, 2); | |
541 | ||
c5aa993b | 542 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 543 | { |
da59e081 | 544 | int mask; |
94c30b78 | 545 | findmask |= 1; /* push found */ |
c906108c SS |
546 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
547 | whether to save LR (R14). */ | |
da59e081 | 548 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 549 | |
b8d5e71d | 550 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 551 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 552 | if (mask & (1 << regno)) |
c5aa993b | 553 | { |
9b8d791a | 554 | cache->framesize += 4; |
eb5492fa | 555 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
556 | /* Reset saved register map. */ |
557 | saved_reg[regno] = regno; | |
c906108c SS |
558 | } |
559 | } | |
da3c6d4a MS |
560 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
561 | sub sp, #simm */ | |
c906108c | 562 | { |
b8d5e71d | 563 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
564 | continue; |
565 | else | |
94c30b78 | 566 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 567 | |
94c30b78 MS |
568 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
569 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 570 | { |
9b8d791a | 571 | cache->frameoffset += offset; |
da59e081 JM |
572 | offset = -offset; |
573 | } | |
9b8d791a | 574 | cache->framesize -= offset; |
c906108c SS |
575 | } |
576 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
577 | { | |
94c30b78 | 578 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 579 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 580 | /* get scaled offset */ |
9b8d791a | 581 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 582 | } |
da59e081 | 583 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 584 | { |
94c30b78 | 585 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
586 | cache->framereg = THUMB_FP_REGNUM; |
587 | cache->frameoffset = 0; | |
34e8f22d | 588 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
589 | } |
590 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
591 | { | |
da3c6d4a | 592 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 593 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 594 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
595 | } |
596 | else | |
da3c6d4a MS |
597 | /* Something in the prolog that we don't care about or some |
598 | instruction from outside the prolog scheduled here for | |
599 | optimization. */ | |
600 | continue; | |
c906108c SS |
601 | } |
602 | } | |
603 | ||
ed9a39eb | 604 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
605 | 1) the size of the stack frame |
606 | 2) which registers are saved on it | |
607 | 3) the offsets of saved regs | |
608 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
609 | This information is stored in the "extra" fields of the frame_info. |
610 | ||
96baa820 JM |
611 | There are two basic forms for the ARM prologue. The fixed argument |
612 | function call will look like: | |
ed9a39eb JM |
613 | |
614 | mov ip, sp | |
615 | stmfd sp!, {fp, ip, lr, pc} | |
616 | sub fp, ip, #4 | |
617 | [sub sp, sp, #4] | |
96baa820 | 618 | |
c906108c | 619 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
620 | IP -> 4 (caller's stack) |
621 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
622 | -4 LR (return address in caller) | |
623 | -8 IP (copy of caller's SP) | |
624 | -12 FP (caller's FP) | |
625 | SP -> -28 Local variables | |
626 | ||
c906108c | 627 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
628 | 28 bytes. The stmfd call can also save any of the vN registers it |
629 | plans to use, which increases the frame size accordingly. | |
630 | ||
631 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
632 | because the ARM Store instructions always store PC + 8 when you read | |
633 | the PC register. | |
ed9a39eb | 634 | |
96baa820 JM |
635 | A variable argument function call will look like: |
636 | ||
ed9a39eb JM |
637 | mov ip, sp |
638 | stmfd sp!, {a1, a2, a3, a4} | |
639 | stmfd sp!, {fp, ip, lr, pc} | |
640 | sub fp, ip, #20 | |
641 | ||
96baa820 | 642 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
643 | IP -> 20 (caller's stack) |
644 | 16 A4 | |
645 | 12 A3 | |
646 | 8 A2 | |
647 | 4 A1 | |
648 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
649 | -4 LR (return address in caller) | |
650 | -8 IP (copy of caller's SP) | |
651 | -12 FP (caller's FP) | |
652 | SP -> -28 Local variables | |
96baa820 JM |
653 | |
654 | The frame size would thus be 48 bytes, and the frame offset would be | |
655 | 28 bytes. | |
656 | ||
657 | There is another potential complication, which is that the optimizer | |
658 | will try to separate the store of fp in the "stmfd" instruction from | |
659 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
660 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
661 | ||
662 | Also, note, the original version of the ARM toolchain claimed that there | |
663 | should be an | |
664 | ||
665 | instruction at the end of the prologue. I have never seen GCC produce | |
666 | this, and the ARM docs don't mention it. We still test for it below in | |
667 | case it happens... | |
ed9a39eb JM |
668 | |
669 | */ | |
c906108c SS |
670 | |
671 | static void | |
eb5492fa | 672 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 673 | { |
28cd8767 | 674 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 675 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 676 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 677 | |
c906108c | 678 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
679 | cache->framereg = ARM_SP_REGNUM; |
680 | cache->framesize = 0; | |
681 | cache->frameoffset = 0; | |
c906108c SS |
682 | |
683 | /* Check for Thumb prologue. */ | |
eb5492fa | 684 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 685 | { |
eb5492fa | 686 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
687 | return; |
688 | } | |
689 | ||
690 | /* Find the function prologue. If we can't find the function in | |
691 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 692 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 693 | { |
2a451106 KB |
694 | /* One way to find the end of the prologue (which works well |
695 | for unoptimized code) is to do the following: | |
696 | ||
697 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
698 | ||
699 | if (sal.line == 0) | |
eb5492fa | 700 | prologue_end = prev_pc; |
2a451106 KB |
701 | else if (sal.end < prologue_end) |
702 | prologue_end = sal.end; | |
703 | ||
704 | This mechanism is very accurate so long as the optimizer | |
705 | doesn't move any instructions from the function body into the | |
706 | prologue. If this happens, sal.end will be the last | |
707 | instruction in the first hunk of prologue code just before | |
708 | the first instruction that the scheduler has moved from | |
709 | the body to the prologue. | |
710 | ||
711 | In order to make sure that we scan all of the prologue | |
712 | instructions, we use a slightly less accurate mechanism which | |
713 | may scan more than necessary. To help compensate for this | |
714 | lack of accuracy, the prologue scanning loop below contains | |
715 | several clauses which'll cause the loop to terminate early if | |
716 | an implausible prologue instruction is encountered. | |
717 | ||
718 | The expression | |
719 | ||
720 | prologue_start + 64 | |
721 | ||
722 | is a suitable endpoint since it accounts for the largest | |
723 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 724 | the scheduler. */ |
2a451106 KB |
725 | |
726 | if (prologue_end > prologue_start + 64) | |
727 | { | |
94c30b78 | 728 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 729 | } |
c906108c SS |
730 | } |
731 | else | |
732 | { | |
eb5492fa DJ |
733 | /* We have no symbol information. Our only option is to assume this |
734 | function has a standard stack frame and the normal frame register. | |
735 | Then, we can find the value of our frame pointer on entrance to | |
736 | the callee (or at the present moment if this is the innermost frame). | |
737 | The value stored there should be the address of the stmfd + 8. */ | |
738 | CORE_ADDR frame_loc; | |
739 | LONGEST return_value; | |
740 | ||
741 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
742 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
743 | return; |
744 | else | |
745 | { | |
746 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 747 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 748 | } |
c906108c SS |
749 | } |
750 | ||
eb5492fa DJ |
751 | if (prev_pc < prologue_end) |
752 | prologue_end = prev_pc; | |
753 | ||
c906108c | 754 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 755 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 756 | |
96baa820 JM |
757 | Be careful, however, and if it doesn't look like a prologue, |
758 | don't try to scan it. If, for instance, a frameless function | |
759 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 760 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
761 | and other operations that rely on a knowledge of the stack |
762 | traceback. | |
763 | ||
764 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 765 | if we don't see this as the first insn, we will stop. |
c906108c | 766 | |
f43845b3 MS |
767 | [Note: This doesn't seem to be true any longer, so it's now an |
768 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 769 | |
f43845b3 MS |
770 | [Note further: The "mov ip,sp" only seems to be missing in |
771 | frameless functions at optimization level "-O2" or above, | |
772 | in which case it is often (but not always) replaced by | |
b8d5e71d | 773 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 774 | |
28cd8767 | 775 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 776 | |
94c30b78 MS |
777 | for (current_pc = prologue_start; |
778 | current_pc < prologue_end; | |
f43845b3 | 779 | current_pc += 4) |
96baa820 | 780 | { |
d4473757 KB |
781 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
782 | ||
94c30b78 | 783 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 784 | { |
28cd8767 JG |
785 | ip_offset = 0; |
786 | continue; | |
787 | } | |
788 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
789 | { | |
790 | unsigned imm = insn & 0xff; /* immediate value */ | |
791 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
792 | imm = (imm >> rot) | (imm << (32 - rot)); | |
793 | ip_offset = imm; | |
794 | continue; | |
795 | } | |
796 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
797 | { | |
798 | unsigned imm = insn & 0xff; /* immediate value */ | |
799 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
800 | imm = (imm >> rot) | (imm << (32 - rot)); | |
801 | ip_offset = -imm; | |
f43845b3 MS |
802 | continue; |
803 | } | |
94c30b78 | 804 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 805 | { |
e28a332c JG |
806 | sp_offset -= 4; |
807 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
808 | continue; |
809 | } | |
810 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
811 | /* stmfd sp!, {..., fp, ip, lr, pc} |
812 | or | |
813 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 814 | { |
d4473757 | 815 | int mask = insn & 0xffff; |
ed9a39eb | 816 | |
94c30b78 | 817 | /* Calculate offsets of saved registers. */ |
34e8f22d | 818 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
819 | if (mask & (1 << regno)) |
820 | { | |
821 | sp_offset -= 4; | |
eb5492fa | 822 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
823 | } |
824 | } | |
b8d5e71d MS |
825 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
826 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
827 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
828 | { | |
829 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
830 | continue; | |
831 | } | |
832 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
833 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
834 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
835 | { |
836 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
837 | continue; | |
838 | } | |
d4473757 KB |
839 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
840 | { | |
94c30b78 MS |
841 | unsigned imm = insn & 0xff; /* immediate value */ |
842 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 843 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 844 | fp_offset = -imm + ip_offset; |
9b8d791a | 845 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
846 | } |
847 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
848 | { | |
94c30b78 MS |
849 | unsigned imm = insn & 0xff; /* immediate value */ |
850 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
851 | imm = (imm >> rot) | (imm << (32 - rot)); |
852 | sp_offset -= imm; | |
853 | } | |
854 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
855 | { | |
856 | sp_offset -= 12; | |
34e8f22d | 857 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 858 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
859 | } |
860 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
861 | { | |
862 | int n_saved_fp_regs; | |
863 | unsigned int fp_start_reg, fp_bound_reg; | |
864 | ||
94c30b78 | 865 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 866 | { |
d4473757 KB |
867 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
868 | n_saved_fp_regs = 3; | |
869 | else | |
870 | n_saved_fp_regs = 1; | |
96baa820 | 871 | } |
d4473757 | 872 | else |
96baa820 | 873 | { |
d4473757 KB |
874 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
875 | n_saved_fp_regs = 2; | |
876 | else | |
877 | n_saved_fp_regs = 4; | |
96baa820 | 878 | } |
d4473757 | 879 | |
34e8f22d | 880 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
881 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
882 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
883 | { |
884 | sp_offset -= 12; | |
eb5492fa | 885 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 886 | } |
c906108c | 887 | } |
d4473757 | 888 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 889 | break; /* Condition not true, exit early */ |
b8d5e71d | 890 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 891 | break; /* Don't scan past a block load */ |
d4473757 KB |
892 | else |
893 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 894 | so we just skip what we don't recognize. */ |
d4473757 | 895 | continue; |
c906108c SS |
896 | } |
897 | ||
94c30b78 MS |
898 | /* The frame size is just the negative of the offset (from the |
899 | original SP) of the last thing thing we pushed on the stack. | |
900 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
901 | cache->framesize = -sp_offset; |
902 | if (cache->framereg == ARM_FP_REGNUM) | |
903 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 904 | else |
9b8d791a | 905 | cache->frameoffset = 0; |
c906108c SS |
906 | } |
907 | ||
eb5492fa DJ |
908 | static struct arm_prologue_cache * |
909 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 910 | { |
eb5492fa DJ |
911 | int reg; |
912 | struct arm_prologue_cache *cache; | |
913 | CORE_ADDR unwound_fp; | |
c5aa993b | 914 | |
eb5492fa DJ |
915 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
916 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 917 | |
eb5492fa | 918 | arm_scan_prologue (next_frame, cache); |
848cfffb | 919 | |
eb5492fa DJ |
920 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
921 | if (unwound_fp == 0) | |
922 | return cache; | |
c906108c | 923 | |
eb5492fa | 924 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 925 | |
eb5492fa DJ |
926 | /* Calculate actual addresses of saved registers using offsets |
927 | determined by arm_scan_prologue. */ | |
928 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 929 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
930 | cache->saved_regs[reg].addr += cache->prev_sp; |
931 | ||
932 | return cache; | |
c906108c SS |
933 | } |
934 | ||
eb5492fa DJ |
935 | /* Our frame ID for a normal frame is the current function's starting PC |
936 | and the caller's SP when we were called. */ | |
c906108c | 937 | |
148754e5 | 938 | static void |
eb5492fa DJ |
939 | arm_prologue_this_id (struct frame_info *next_frame, |
940 | void **this_cache, | |
941 | struct frame_id *this_id) | |
c906108c | 942 | { |
eb5492fa DJ |
943 | struct arm_prologue_cache *cache; |
944 | struct frame_id id; | |
945 | CORE_ADDR func; | |
f079148d | 946 | |
eb5492fa DJ |
947 | if (*this_cache == NULL) |
948 | *this_cache = arm_make_prologue_cache (next_frame); | |
949 | cache = *this_cache; | |
2a451106 | 950 | |
eb5492fa | 951 | func = frame_func_unwind (next_frame); |
2a451106 | 952 | |
eb5492fa DJ |
953 | /* This is meant to halt the backtrace at "_start". Make sure we |
954 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 955 | if (func <= LOWEST_PC) |
eb5492fa | 956 | return; |
5a203e44 | 957 | |
eb5492fa DJ |
958 | /* If we've hit a wall, stop. */ |
959 | if (cache->prev_sp == 0) | |
960 | return; | |
24de872b | 961 | |
eb5492fa | 962 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 963 | *this_id = id; |
c906108c SS |
964 | } |
965 | ||
eb5492fa DJ |
966 | static void |
967 | arm_prologue_prev_register (struct frame_info *next_frame, | |
968 | void **this_cache, | |
969 | int prev_regnum, | |
970 | int *optimized, | |
971 | enum lval_type *lvalp, | |
972 | CORE_ADDR *addrp, | |
973 | int *realnump, | |
974 | void *valuep) | |
24de872b DJ |
975 | { |
976 | struct arm_prologue_cache *cache; | |
977 | ||
eb5492fa DJ |
978 | if (*this_cache == NULL) |
979 | *this_cache = arm_make_prologue_cache (next_frame); | |
980 | cache = *this_cache; | |
24de872b | 981 | |
eb5492fa DJ |
982 | /* If we are asked to unwind the PC, then we need to return the LR |
983 | instead. The saved value of PC points into this frame's | |
984 | prologue, not the next frame's resume location. */ | |
985 | if (prev_regnum == ARM_PC_REGNUM) | |
986 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 987 | |
eb5492fa DJ |
988 | /* SP is generally not saved to the stack, but this frame is |
989 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
990 | The value was already reconstructed into PREV_SP. */ | |
991 | if (prev_regnum == ARM_SP_REGNUM) | |
992 | { | |
993 | *lvalp = not_lval; | |
994 | if (valuep) | |
995 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
996 | return; | |
997 | } | |
998 | ||
1f67027d AC |
999 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
1000 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
1001 | } |
1002 | ||
1003 | struct frame_unwind arm_prologue_unwind = { | |
1004 | NORMAL_FRAME, | |
1005 | arm_prologue_this_id, | |
1006 | arm_prologue_prev_register | |
1007 | }; | |
1008 | ||
1009 | static const struct frame_unwind * | |
1010 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
1011 | { | |
1012 | return &arm_prologue_unwind; | |
24de872b DJ |
1013 | } |
1014 | ||
1015 | static CORE_ADDR | |
eb5492fa | 1016 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1017 | { |
1018 | struct arm_prologue_cache *cache; | |
1019 | ||
eb5492fa DJ |
1020 | if (*this_cache == NULL) |
1021 | *this_cache = arm_make_prologue_cache (next_frame); | |
1022 | cache = *this_cache; | |
1023 | ||
1024 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1025 | } |
1026 | ||
eb5492fa DJ |
1027 | struct frame_base arm_normal_base = { |
1028 | &arm_prologue_unwind, | |
1029 | arm_normal_frame_base, | |
1030 | arm_normal_frame_base, | |
1031 | arm_normal_frame_base | |
1032 | }; | |
1033 | ||
1034 | static struct arm_prologue_cache * | |
1035 | arm_make_sigtramp_cache (struct frame_info *next_frame) | |
24de872b DJ |
1036 | { |
1037 | struct arm_prologue_cache *cache; | |
eb5492fa DJ |
1038 | int reg; |
1039 | ||
1040 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
24de872b | 1041 | |
eb5492fa | 1042 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
24de872b | 1043 | |
eb5492fa | 1044 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
24de872b | 1045 | |
eb5492fa DJ |
1046 | for (reg = 0; reg < NUM_REGS; reg++) |
1047 | cache->saved_regs[reg].addr | |
1048 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, | |
1049 | frame_pc_unwind (next_frame), reg); | |
24de872b | 1050 | |
eb5492fa DJ |
1051 | /* FIXME: What about thumb mode? */ |
1052 | cache->framereg = ARM_SP_REGNUM; | |
1053 | cache->prev_sp | |
1054 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, | |
7a5ea0d4 | 1055 | register_size (current_gdbarch, cache->framereg)); |
eb5492fa DJ |
1056 | |
1057 | return cache; | |
24de872b | 1058 | } |
c906108c | 1059 | |
eb5492fa DJ |
1060 | static void |
1061 | arm_sigtramp_this_id (struct frame_info *next_frame, | |
1062 | void **this_cache, | |
1063 | struct frame_id *this_id) | |
1064 | { | |
1065 | struct arm_prologue_cache *cache; | |
c906108c | 1066 | |
eb5492fa DJ |
1067 | if (*this_cache == NULL) |
1068 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1069 | cache = *this_cache; | |
c906108c | 1070 | |
eb5492fa DJ |
1071 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
1072 | the sigtramp frame; the PC should be the beginning of the trampoline. */ | |
1073 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); | |
1074 | } | |
1075 | ||
1076 | static void | |
1077 | arm_sigtramp_prev_register (struct frame_info *next_frame, | |
1078 | void **this_cache, | |
1079 | int prev_regnum, | |
1080 | int *optimized, | |
1081 | enum lval_type *lvalp, | |
1082 | CORE_ADDR *addrp, | |
1083 | int *realnump, | |
1084 | void *valuep) | |
c906108c | 1085 | { |
eb5492fa | 1086 | struct arm_prologue_cache *cache; |
848cfffb | 1087 | |
eb5492fa DJ |
1088 | if (*this_cache == NULL) |
1089 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1090 | cache = *this_cache; | |
1091 | ||
1f67027d AC |
1092 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
1093 | optimized, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1094 | } |
1095 | ||
eb5492fa DJ |
1096 | struct frame_unwind arm_sigtramp_unwind = { |
1097 | SIGTRAMP_FRAME, | |
1098 | arm_sigtramp_this_id, | |
1099 | arm_sigtramp_prev_register | |
1100 | }; | |
c906108c | 1101 | |
eb5492fa DJ |
1102 | static const struct frame_unwind * |
1103 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) | |
c906108c | 1104 | { |
eb5492fa | 1105 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
0b281939 | 1106 | && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0)) |
eb5492fa DJ |
1107 | return &arm_sigtramp_unwind; |
1108 | ||
1109 | return NULL; | |
c906108c SS |
1110 | } |
1111 | ||
eb5492fa DJ |
1112 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1113 | dummy frame. The frame ID's base needs to match the TOS value | |
1114 | saved by save_dummy_frame_tos() and returned from | |
1115 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1116 | breakpoint. */ | |
c906108c | 1117 | |
eb5492fa DJ |
1118 | static struct frame_id |
1119 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1120 | { |
eb5492fa DJ |
1121 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1122 | frame_pc_unwind (next_frame)); | |
1123 | } | |
c3b4394c | 1124 | |
eb5492fa DJ |
1125 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1126 | be used to construct the previous frame's ID, after looking up the | |
1127 | containing function). */ | |
c3b4394c | 1128 | |
eb5492fa DJ |
1129 | static CORE_ADDR |
1130 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1131 | { | |
1132 | CORE_ADDR pc; | |
1133 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1134 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1135 | } | |
1136 | ||
1137 | static CORE_ADDR | |
1138 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1139 | { | |
1140 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1141 | } |
1142 | ||
2dd604e7 RE |
1143 | /* When arguments must be pushed onto the stack, they go on in reverse |
1144 | order. The code below implements a FILO (stack) to do this. */ | |
1145 | ||
1146 | struct stack_item | |
1147 | { | |
1148 | int len; | |
1149 | struct stack_item *prev; | |
1150 | void *data; | |
1151 | }; | |
1152 | ||
1153 | static struct stack_item * | |
1154 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1155 | { | |
1156 | struct stack_item *si; | |
1157 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1158 | si->data = xmalloc (len); |
2dd604e7 RE |
1159 | si->len = len; |
1160 | si->prev = prev; | |
1161 | memcpy (si->data, contents, len); | |
1162 | return si; | |
1163 | } | |
1164 | ||
1165 | static struct stack_item * | |
1166 | pop_stack_item (struct stack_item *si) | |
1167 | { | |
1168 | struct stack_item *dead = si; | |
1169 | si = si->prev; | |
1170 | xfree (dead->data); | |
1171 | xfree (dead); | |
1172 | return si; | |
1173 | } | |
1174 | ||
1175 | /* We currently only support passing parameters in integer registers. This | |
1176 | conforms with GCC's default model. Several other variants exist and | |
1177 | we should probably support some of them based on the selected ABI. */ | |
1178 | ||
1179 | static CORE_ADDR | |
7d9b040b | 1180 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1181 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1182 | struct value **args, CORE_ADDR sp, int struct_return, | |
1183 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1184 | { |
1185 | int argnum; | |
1186 | int argreg; | |
1187 | int nstack; | |
1188 | struct stack_item *si = NULL; | |
1189 | ||
6a65450a AC |
1190 | /* Set the return address. For the ARM, the return breakpoint is |
1191 | always at BP_ADDR. */ | |
2dd604e7 | 1192 | /* XXX Fix for Thumb. */ |
6a65450a | 1193 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1194 | |
1195 | /* Walk through the list of args and determine how large a temporary | |
1196 | stack is required. Need to take care here as structs may be | |
1197 | passed on the stack, and we have to to push them. */ | |
1198 | nstack = 0; | |
1199 | ||
1200 | argreg = ARM_A1_REGNUM; | |
1201 | nstack = 0; | |
1202 | ||
1203 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1204 | is correctly aligned before we start. We always do this even if | |
1205 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1206 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1207 | |
1208 | /* The struct_return pointer occupies the first parameter | |
1209 | passing register. */ | |
1210 | if (struct_return) | |
1211 | { | |
1212 | if (arm_debug) | |
1213 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1214 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1215 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1216 | argreg++; | |
1217 | } | |
1218 | ||
1219 | for (argnum = 0; argnum < nargs; argnum++) | |
1220 | { | |
1221 | int len; | |
1222 | struct type *arg_type; | |
1223 | struct type *target_type; | |
1224 | enum type_code typecode; | |
1225 | char *val; | |
1226 | ||
df407dfe | 1227 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1228 | len = TYPE_LENGTH (arg_type); |
1229 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1230 | typecode = TYPE_CODE (arg_type); | |
1231 | val = VALUE_CONTENTS (args[argnum]); | |
1232 | ||
1233 | /* If the argument is a pointer to a function, and it is a | |
1234 | Thumb function, create a LOCAL copy of the value and set | |
1235 | the THUMB bit in it. */ | |
1236 | if (TYPE_CODE_PTR == typecode | |
1237 | && target_type != NULL | |
1238 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1239 | { | |
7c0b4a20 | 1240 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1241 | if (arm_pc_is_thumb (regval)) |
1242 | { | |
1243 | val = alloca (len); | |
fbd9dcd3 | 1244 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1245 | } |
1246 | } | |
1247 | ||
1248 | /* Copy the argument to general registers or the stack in | |
1249 | register-sized pieces. Large arguments are split between | |
1250 | registers and stack. */ | |
1251 | while (len > 0) | |
1252 | { | |
b1e29e33 | 1253 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1254 | |
1255 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1256 | { | |
1257 | /* The argument is being passed in a general purpose | |
1258 | register. */ | |
7c0b4a20 | 1259 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1260 | if (arm_debug) |
1261 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1262 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1263 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1264 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1265 | argreg++; | |
1266 | } | |
1267 | else | |
1268 | { | |
1269 | /* Push the arguments onto the stack. */ | |
1270 | if (arm_debug) | |
1271 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1272 | argnum, nstack); | |
b1e29e33 AC |
1273 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1274 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1275 | } |
1276 | ||
1277 | len -= partial_len; | |
1278 | val += partial_len; | |
1279 | } | |
1280 | } | |
1281 | /* If we have an odd number of words to push, then decrement the stack | |
1282 | by one word now, so first stack argument will be dword aligned. */ | |
1283 | if (nstack & 4) | |
1284 | sp -= 4; | |
1285 | ||
1286 | while (si) | |
1287 | { | |
1288 | sp -= si->len; | |
1289 | write_memory (sp, si->data, si->len); | |
1290 | si = pop_stack_item (si); | |
1291 | } | |
1292 | ||
1293 | /* Finally, update teh SP register. */ | |
1294 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1295 | ||
1296 | return sp; | |
1297 | } | |
1298 | ||
c906108c | 1299 | static void |
ed9a39eb | 1300 | print_fpu_flags (int flags) |
c906108c | 1301 | { |
c5aa993b JM |
1302 | if (flags & (1 << 0)) |
1303 | fputs ("IVO ", stdout); | |
1304 | if (flags & (1 << 1)) | |
1305 | fputs ("DVZ ", stdout); | |
1306 | if (flags & (1 << 2)) | |
1307 | fputs ("OFL ", stdout); | |
1308 | if (flags & (1 << 3)) | |
1309 | fputs ("UFL ", stdout); | |
1310 | if (flags & (1 << 4)) | |
1311 | fputs ("INX ", stdout); | |
1312 | putchar ('\n'); | |
c906108c SS |
1313 | } |
1314 | ||
5e74b15c RE |
1315 | /* Print interesting information about the floating point processor |
1316 | (if present) or emulator. */ | |
34e8f22d | 1317 | static void |
d855c300 | 1318 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1319 | struct frame_info *frame, const char *args) |
c906108c | 1320 | { |
52f0bd74 | 1321 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1322 | int type; |
1323 | ||
1324 | type = (status >> 24) & 127; | |
1325 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1326 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1327 | type); |
1328 | fputs ("mask: ", stdout); | |
1329 | print_fpu_flags (status >> 16); | |
1330 | fputs ("flags: ", stdout); | |
1331 | print_fpu_flags (status); | |
c906108c SS |
1332 | } |
1333 | ||
34e8f22d RE |
1334 | /* Return the GDB type object for the "standard" data type of data in |
1335 | register N. */ | |
1336 | ||
1337 | static struct type * | |
7a5ea0d4 | 1338 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1339 | { |
34e8f22d | 1340 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1341 | { |
d7449b42 | 1342 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1343 | return builtin_type_arm_ext_big; |
1344 | else | |
1345 | return builtin_type_arm_ext_littlebyte_bigword; | |
1346 | } | |
1347 | else | |
1348 | return builtin_type_int32; | |
1349 | } | |
1350 | ||
34e8f22d RE |
1351 | /* Index within `registers' of the first byte of the space for |
1352 | register N. */ | |
1353 | ||
1354 | static int | |
1355 | arm_register_byte (int regnum) | |
1356 | { | |
1357 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1358 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1359 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1360 | return (NUM_GREGS * INT_REGISTER_SIZE |
1361 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1362 | else |
7a5ea0d4 DJ |
1363 | return (NUM_GREGS * INT_REGISTER_SIZE |
1364 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1365 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1366 | } | |
1367 | ||
26216b98 AC |
1368 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1369 | static int | |
1370 | arm_register_sim_regno (int regnum) | |
1371 | { | |
1372 | int reg = regnum; | |
1373 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1374 | ||
1375 | if (reg < NUM_GREGS) | |
1376 | return SIM_ARM_R0_REGNUM + reg; | |
1377 | reg -= NUM_GREGS; | |
1378 | ||
1379 | if (reg < NUM_FREGS) | |
1380 | return SIM_ARM_FP0_REGNUM + reg; | |
1381 | reg -= NUM_FREGS; | |
1382 | ||
1383 | if (reg < NUM_SREGS) | |
1384 | return SIM_ARM_FPS_REGNUM + reg; | |
1385 | reg -= NUM_SREGS; | |
1386 | ||
1387 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1388 | } | |
34e8f22d | 1389 | |
a37b3cc0 AC |
1390 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1391 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1392 | It is thought that this is is the floating-point register format on | |
1393 | little-endian systems. */ | |
c906108c | 1394 | |
ed9a39eb | 1395 | static void |
b508a996 RE |
1396 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1397 | void *dbl) | |
c906108c | 1398 | { |
a37b3cc0 | 1399 | DOUBLEST d; |
d7449b42 | 1400 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1401 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1402 | else | |
1403 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1404 | ptr, &d); | |
b508a996 | 1405 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1406 | } |
1407 | ||
34e8f22d | 1408 | static void |
b508a996 | 1409 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1410 | { |
a37b3cc0 | 1411 | DOUBLEST d; |
b508a996 | 1412 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1413 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1414 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1415 | else | |
1416 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1417 | &d, dbl); | |
c906108c | 1418 | } |
ed9a39eb | 1419 | |
c906108c | 1420 | static int |
ed9a39eb | 1421 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1422 | { |
1423 | if (cond == INST_AL || cond == INST_NV) | |
1424 | return 1; | |
1425 | ||
1426 | switch (cond) | |
1427 | { | |
1428 | case INST_EQ: | |
1429 | return ((status_reg & FLAG_Z) != 0); | |
1430 | case INST_NE: | |
1431 | return ((status_reg & FLAG_Z) == 0); | |
1432 | case INST_CS: | |
1433 | return ((status_reg & FLAG_C) != 0); | |
1434 | case INST_CC: | |
1435 | return ((status_reg & FLAG_C) == 0); | |
1436 | case INST_MI: | |
1437 | return ((status_reg & FLAG_N) != 0); | |
1438 | case INST_PL: | |
1439 | return ((status_reg & FLAG_N) == 0); | |
1440 | case INST_VS: | |
1441 | return ((status_reg & FLAG_V) != 0); | |
1442 | case INST_VC: | |
1443 | return ((status_reg & FLAG_V) == 0); | |
1444 | case INST_HI: | |
1445 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1446 | case INST_LS: | |
1447 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1448 | case INST_GE: | |
1449 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1450 | case INST_LT: | |
1451 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1452 | case INST_GT: | |
1453 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1454 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1455 | case INST_LE: |
1456 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1457 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1458 | } |
1459 | return 1; | |
1460 | } | |
1461 | ||
9512d7fd | 1462 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1463 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1464 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1465 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1466 | #define sbits(obj,st,fn) \ | |
1467 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1468 | #define BranchDest(addr,instr) \ | |
1469 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1470 | #define ARM_PC_32 1 | |
1471 | ||
1472 | static unsigned long | |
ed9a39eb JM |
1473 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1474 | unsigned long status_reg) | |
c906108c SS |
1475 | { |
1476 | unsigned long res, shift; | |
1477 | int rm = bits (inst, 0, 3); | |
1478 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1479 | |
1480 | if (bit (inst, 4)) | |
c906108c SS |
1481 | { |
1482 | int rs = bits (inst, 8, 11); | |
1483 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1484 | } | |
1485 | else | |
1486 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1487 | |
1488 | res = (rm == 15 | |
c906108c | 1489 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1490 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1491 | : read_register (rm)); |
1492 | ||
1493 | switch (shifttype) | |
1494 | { | |
c5aa993b | 1495 | case 0: /* LSL */ |
c906108c SS |
1496 | res = shift >= 32 ? 0 : res << shift; |
1497 | break; | |
c5aa993b JM |
1498 | |
1499 | case 1: /* LSR */ | |
c906108c SS |
1500 | res = shift >= 32 ? 0 : res >> shift; |
1501 | break; | |
1502 | ||
c5aa993b JM |
1503 | case 2: /* ASR */ |
1504 | if (shift >= 32) | |
1505 | shift = 31; | |
c906108c SS |
1506 | res = ((res & 0x80000000L) |
1507 | ? ~((~res) >> shift) : res >> shift); | |
1508 | break; | |
1509 | ||
c5aa993b | 1510 | case 3: /* ROR/RRX */ |
c906108c SS |
1511 | shift &= 31; |
1512 | if (shift == 0) | |
1513 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1514 | else | |
c5aa993b | 1515 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1516 | break; |
1517 | } | |
1518 | ||
1519 | return res & 0xffffffff; | |
1520 | } | |
1521 | ||
c906108c SS |
1522 | /* Return number of 1-bits in VAL. */ |
1523 | ||
1524 | static int | |
ed9a39eb | 1525 | bitcount (unsigned long val) |
c906108c SS |
1526 | { |
1527 | int nbits; | |
1528 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1529 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1530 | return nbits; |
1531 | } | |
1532 | ||
34e8f22d | 1533 | CORE_ADDR |
ed9a39eb | 1534 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1535 | { |
c5aa993b | 1536 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1537 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1538 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1539 | unsigned long offset; |
1540 | ||
1541 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1542 | { | |
1543 | CORE_ADDR sp; | |
1544 | ||
1545 | /* Fetch the saved PC from the stack. It's stored above | |
1546 | all of the other registers. */ | |
b1e29e33 | 1547 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1548 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1549 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1550 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1551 | if (nextpc == pc) | |
1552 | error ("Infinite loop detected"); | |
1553 | } | |
1554 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1555 | { | |
34e8f22d | 1556 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1557 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1558 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1559 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1560 | } | |
1561 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1562 | { | |
1563 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1564 | } | |
aa17d93e | 1565 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c SS |
1566 | { |
1567 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1568 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1569 | nextpc = pc_val + offset; |
aa17d93e DJ |
1570 | /* For BLX make sure to clear the low bits. */ |
1571 | if (bits (inst2, 11, 12) == 1) | |
1572 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1573 | } |
aa17d93e | 1574 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1575 | { |
1576 | if (bits (inst1, 3, 6) == 0x0f) | |
1577 | nextpc = pc_val; | |
1578 | else | |
1579 | nextpc = read_register (bits (inst1, 3, 6)); | |
1580 | ||
1581 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1582 | if (nextpc == pc) | |
1583 | error ("Infinite loop detected"); | |
1584 | } | |
c906108c SS |
1585 | |
1586 | return nextpc; | |
1587 | } | |
1588 | ||
34e8f22d | 1589 | CORE_ADDR |
ed9a39eb | 1590 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1591 | { |
1592 | unsigned long pc_val; | |
1593 | unsigned long this_instr; | |
1594 | unsigned long status; | |
1595 | CORE_ADDR nextpc; | |
1596 | ||
1597 | if (arm_pc_is_thumb (pc)) | |
1598 | return thumb_get_next_pc (pc); | |
1599 | ||
1600 | pc_val = (unsigned long) pc; | |
1601 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1602 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1603 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1604 | |
1605 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1606 | { | |
1607 | switch (bits (this_instr, 24, 27)) | |
1608 | { | |
c5aa993b | 1609 | case 0x0: |
94c30b78 | 1610 | case 0x1: /* data processing */ |
c5aa993b JM |
1611 | case 0x2: |
1612 | case 0x3: | |
c906108c SS |
1613 | { |
1614 | unsigned long operand1, operand2, result = 0; | |
1615 | unsigned long rn; | |
1616 | int c; | |
c5aa993b | 1617 | |
c906108c SS |
1618 | if (bits (this_instr, 12, 15) != 15) |
1619 | break; | |
1620 | ||
1621 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1622 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1623 | error ("Illegal update to pc in instruction"); |
1624 | ||
9498281f DJ |
1625 | /* BX <reg>, BLX <reg> */ |
1626 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1627 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1628 | { | |
1629 | rn = bits (this_instr, 0, 3); | |
1630 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1631 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1632 | ||
1633 | if (nextpc == pc) | |
1634 | error ("Infinite loop detected"); | |
1635 | ||
1636 | return nextpc; | |
1637 | } | |
1638 | ||
c906108c SS |
1639 | /* Multiply into PC */ |
1640 | c = (status & FLAG_C) ? 1 : 0; | |
1641 | rn = bits (this_instr, 16, 19); | |
1642 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1643 | |
c906108c SS |
1644 | if (bit (this_instr, 25)) |
1645 | { | |
1646 | unsigned long immval = bits (this_instr, 0, 7); | |
1647 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1648 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1649 | & 0xffffffff; | |
c906108c | 1650 | } |
c5aa993b | 1651 | else /* operand 2 is a shifted register */ |
c906108c | 1652 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1653 | |
c906108c SS |
1654 | switch (bits (this_instr, 21, 24)) |
1655 | { | |
c5aa993b | 1656 | case 0x0: /*and */ |
c906108c SS |
1657 | result = operand1 & operand2; |
1658 | break; | |
1659 | ||
c5aa993b | 1660 | case 0x1: /*eor */ |
c906108c SS |
1661 | result = operand1 ^ operand2; |
1662 | break; | |
1663 | ||
c5aa993b | 1664 | case 0x2: /*sub */ |
c906108c SS |
1665 | result = operand1 - operand2; |
1666 | break; | |
1667 | ||
c5aa993b | 1668 | case 0x3: /*rsb */ |
c906108c SS |
1669 | result = operand2 - operand1; |
1670 | break; | |
1671 | ||
c5aa993b | 1672 | case 0x4: /*add */ |
c906108c SS |
1673 | result = operand1 + operand2; |
1674 | break; | |
1675 | ||
c5aa993b | 1676 | case 0x5: /*adc */ |
c906108c SS |
1677 | result = operand1 + operand2 + c; |
1678 | break; | |
1679 | ||
c5aa993b | 1680 | case 0x6: /*sbc */ |
c906108c SS |
1681 | result = operand1 - operand2 + c; |
1682 | break; | |
1683 | ||
c5aa993b | 1684 | case 0x7: /*rsc */ |
c906108c SS |
1685 | result = operand2 - operand1 + c; |
1686 | break; | |
1687 | ||
c5aa993b JM |
1688 | case 0x8: |
1689 | case 0x9: | |
1690 | case 0xa: | |
1691 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1692 | result = (unsigned long) nextpc; |
1693 | break; | |
1694 | ||
c5aa993b | 1695 | case 0xc: /*orr */ |
c906108c SS |
1696 | result = operand1 | operand2; |
1697 | break; | |
1698 | ||
c5aa993b | 1699 | case 0xd: /*mov */ |
c906108c SS |
1700 | /* Always step into a function. */ |
1701 | result = operand2; | |
c5aa993b | 1702 | break; |
c906108c | 1703 | |
c5aa993b | 1704 | case 0xe: /*bic */ |
c906108c SS |
1705 | result = operand1 & ~operand2; |
1706 | break; | |
1707 | ||
c5aa993b | 1708 | case 0xf: /*mvn */ |
c906108c SS |
1709 | result = ~operand2; |
1710 | break; | |
1711 | } | |
1712 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1713 | ||
1714 | if (nextpc == pc) | |
1715 | error ("Infinite loop detected"); | |
1716 | break; | |
1717 | } | |
c5aa993b JM |
1718 | |
1719 | case 0x4: | |
1720 | case 0x5: /* data transfer */ | |
1721 | case 0x6: | |
1722 | case 0x7: | |
c906108c SS |
1723 | if (bit (this_instr, 20)) |
1724 | { | |
1725 | /* load */ | |
1726 | if (bits (this_instr, 12, 15) == 15) | |
1727 | { | |
1728 | /* rd == pc */ | |
c5aa993b | 1729 | unsigned long rn; |
c906108c | 1730 | unsigned long base; |
c5aa993b | 1731 | |
c906108c SS |
1732 | if (bit (this_instr, 22)) |
1733 | error ("Illegal update to pc in instruction"); | |
1734 | ||
1735 | /* byte write to PC */ | |
1736 | rn = bits (this_instr, 16, 19); | |
1737 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1738 | if (bit (this_instr, 24)) | |
1739 | { | |
1740 | /* pre-indexed */ | |
1741 | int c = (status & FLAG_C) ? 1 : 0; | |
1742 | unsigned long offset = | |
c5aa993b | 1743 | (bit (this_instr, 25) |
ed9a39eb | 1744 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1745 | : bits (this_instr, 0, 11)); |
c906108c SS |
1746 | |
1747 | if (bit (this_instr, 23)) | |
1748 | base += offset; | |
1749 | else | |
1750 | base -= offset; | |
1751 | } | |
c5aa993b | 1752 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1753 | 4); |
c5aa993b | 1754 | |
c906108c SS |
1755 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1756 | ||
1757 | if (nextpc == pc) | |
1758 | error ("Infinite loop detected"); | |
1759 | } | |
1760 | } | |
1761 | break; | |
c5aa993b JM |
1762 | |
1763 | case 0x8: | |
1764 | case 0x9: /* block transfer */ | |
c906108c SS |
1765 | if (bit (this_instr, 20)) |
1766 | { | |
1767 | /* LDM */ | |
1768 | if (bit (this_instr, 15)) | |
1769 | { | |
1770 | /* loading pc */ | |
1771 | int offset = 0; | |
1772 | ||
1773 | if (bit (this_instr, 23)) | |
1774 | { | |
1775 | /* up */ | |
1776 | unsigned long reglist = bits (this_instr, 0, 14); | |
1777 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1778 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1779 | offset += 4; |
1780 | } | |
1781 | else if (bit (this_instr, 24)) | |
1782 | offset = -4; | |
c5aa993b | 1783 | |
c906108c | 1784 | { |
c5aa993b JM |
1785 | unsigned long rn_val = |
1786 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1787 | nextpc = |
1788 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1789 | + offset), |
c906108c SS |
1790 | 4); |
1791 | } | |
1792 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1793 | if (nextpc == pc) | |
1794 | error ("Infinite loop detected"); | |
1795 | } | |
1796 | } | |
1797 | break; | |
c5aa993b JM |
1798 | |
1799 | case 0xb: /* branch & link */ | |
1800 | case 0xa: /* branch */ | |
c906108c SS |
1801 | { |
1802 | nextpc = BranchDest (pc, this_instr); | |
1803 | ||
9498281f DJ |
1804 | /* BLX */ |
1805 | if (bits (this_instr, 28, 31) == INST_NV) | |
1806 | nextpc |= bit (this_instr, 24) << 1; | |
1807 | ||
c906108c SS |
1808 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1809 | if (nextpc == pc) | |
1810 | error ("Infinite loop detected"); | |
1811 | break; | |
1812 | } | |
c5aa993b JM |
1813 | |
1814 | case 0xc: | |
1815 | case 0xd: | |
1816 | case 0xe: /* coproc ops */ | |
1817 | case 0xf: /* SWI */ | |
c906108c SS |
1818 | break; |
1819 | ||
1820 | default: | |
97e03143 | 1821 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
1822 | return (pc); |
1823 | } | |
1824 | } | |
1825 | ||
1826 | return nextpc; | |
1827 | } | |
1828 | ||
9512d7fd FN |
1829 | /* single_step() is called just before we want to resume the inferior, |
1830 | if we want to single-step it but there is no hardware or kernel | |
1831 | single-step support. We find the target of the coming instruction | |
1832 | and breakpoint it. | |
1833 | ||
94c30b78 MS |
1834 | single_step() is also called just after the inferior stops. If we |
1835 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1836 | |
34e8f22d RE |
1837 | static void |
1838 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1839 | { |
b8d5e71d | 1840 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
1841 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
1842 | ||
1843 | if (insert_bpt) | |
1844 | { | |
34e8f22d | 1845 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 1846 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1847 | } |
1848 | else | |
80fcf3f0 | 1849 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1850 | } |
9512d7fd | 1851 | |
c906108c SS |
1852 | #include "bfd-in2.h" |
1853 | #include "libcoff.h" | |
1854 | ||
1855 | static int | |
ed9a39eb | 1856 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1857 | { |
1858 | if (arm_pc_is_thumb (memaddr)) | |
1859 | { | |
c5aa993b JM |
1860 | static asymbol *asym; |
1861 | static combined_entry_type ce; | |
1862 | static struct coff_symbol_struct csym; | |
27cddce2 | 1863 | static struct bfd fake_bfd; |
c5aa993b | 1864 | static bfd_target fake_target; |
c906108c SS |
1865 | |
1866 | if (csym.native == NULL) | |
1867 | { | |
da3c6d4a MS |
1868 | /* Create a fake symbol vector containing a Thumb symbol. |
1869 | This is solely so that the code in print_insn_little_arm() | |
1870 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1871 | the presence of a Thumb symbol and switch to decoding | |
1872 | Thumb instructions. */ | |
c5aa993b JM |
1873 | |
1874 | fake_target.flavour = bfd_target_coff_flavour; | |
1875 | fake_bfd.xvec = &fake_target; | |
c906108c | 1876 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1877 | csym.native = &ce; |
1878 | csym.symbol.the_bfd = &fake_bfd; | |
1879 | csym.symbol.name = "fake"; | |
1880 | asym = (asymbol *) & csym; | |
c906108c | 1881 | } |
c5aa993b | 1882 | |
c906108c | 1883 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1884 | info->symbols = &asym; |
c906108c SS |
1885 | } |
1886 | else | |
1887 | info->symbols = NULL; | |
c5aa993b | 1888 | |
d7449b42 | 1889 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1890 | return print_insn_big_arm (memaddr, info); |
1891 | else | |
1892 | return print_insn_little_arm (memaddr, info); | |
1893 | } | |
1894 | ||
66e810cd RE |
1895 | /* The following define instruction sequences that will cause ARM |
1896 | cpu's to take an undefined instruction trap. These are used to | |
1897 | signal a breakpoint to GDB. | |
1898 | ||
1899 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1900 | modes. A different instruction is required for each mode. The ARM | |
1901 | cpu's can also be big or little endian. Thus four different | |
1902 | instructions are needed to support all cases. | |
1903 | ||
1904 | Note: ARMv4 defines several new instructions that will take the | |
1905 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1906 | not in fact add the new instructions. The new undefined | |
1907 | instructions in ARMv4 are all instructions that had no defined | |
1908 | behaviour in earlier chips. There is no guarantee that they will | |
1909 | raise an exception, but may be treated as NOP's. In practice, it | |
1910 | may only safe to rely on instructions matching: | |
1911 | ||
1912 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1913 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1914 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1915 | ||
1916 | Even this may only true if the condition predicate is true. The | |
1917 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1918 | ||
1919 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1920 | and NetBSD all use a software interrupt rather than an undefined | |
1921 | instruction to force a trap. This can be handled by by the | |
1922 | abi-specific code during establishment of the gdbarch vector. */ | |
1923 | ||
1924 | ||
d7b486e7 RE |
1925 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1926 | override these definitions. */ | |
66e810cd RE |
1927 | #ifndef ARM_LE_BREAKPOINT |
1928 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1929 | #endif | |
1930 | #ifndef ARM_BE_BREAKPOINT | |
1931 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1932 | #endif | |
1933 | #ifndef THUMB_LE_BREAKPOINT | |
1934 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1935 | #endif | |
1936 | #ifndef THUMB_BE_BREAKPOINT | |
1937 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1938 | #endif | |
1939 | ||
1940 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1941 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1942 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1943 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1944 | ||
34e8f22d RE |
1945 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1946 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1947 | breakpoint should be used. It returns a pointer to a string of |
1948 | bytes that encode a breakpoint instruction, stores the length of | |
1949 | the string to *lenptr, and adjusts the program counter (if | |
1950 | necessary) to point to the actual memory location where the | |
c906108c SS |
1951 | breakpoint should be inserted. */ |
1952 | ||
34e8f22d RE |
1953 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
1954 | breakpoints and storing their handles instread of what was in | |
1955 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 1956 | otherwise remote-rdp will have to change. */ |
34e8f22d | 1957 | |
ab89facf | 1958 | static const unsigned char * |
ed9a39eb | 1959 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1960 | { |
66e810cd RE |
1961 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1962 | ||
c906108c SS |
1963 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
1964 | { | |
66e810cd RE |
1965 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1966 | *lenptr = tdep->thumb_breakpoint_size; | |
1967 | return tdep->thumb_breakpoint; | |
c906108c SS |
1968 | } |
1969 | else | |
1970 | { | |
66e810cd RE |
1971 | *lenptr = tdep->arm_breakpoint_size; |
1972 | return tdep->arm_breakpoint; | |
c906108c SS |
1973 | } |
1974 | } | |
ed9a39eb JM |
1975 | |
1976 | /* Extract from an array REGBUF containing the (raw) register state a | |
1977 | function return value of type TYPE, and copy that, in virtual | |
1978 | format, into VALBUF. */ | |
1979 | ||
34e8f22d | 1980 | static void |
ed9a39eb | 1981 | arm_extract_return_value (struct type *type, |
b508a996 RE |
1982 | struct regcache *regs, |
1983 | void *dst) | |
ed9a39eb | 1984 | { |
b508a996 RE |
1985 | bfd_byte *valbuf = dst; |
1986 | ||
ed9a39eb | 1987 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 1988 | { |
fd50bc42 | 1989 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
1990 | { |
1991 | case ARM_FLOAT_FPA: | |
b508a996 RE |
1992 | { |
1993 | /* The value is in register F0 in internal format. We need to | |
1994 | extract the raw value and then convert it to the desired | |
1995 | internal type. */ | |
7a5ea0d4 | 1996 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
1997 | |
1998 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
1999 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2000 | valbuf); | |
2001 | } | |
08216dd7 RE |
2002 | break; |
2003 | ||
fd50bc42 | 2004 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2005 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2006 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2007 | if (TYPE_LENGTH (type) > 4) | |
2008 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2009 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2010 | break; |
2011 | ||
2012 | default: | |
2013 | internal_error | |
2014 | (__FILE__, __LINE__, | |
2015 | "arm_extract_return_value: Floating point model not supported"); | |
2016 | break; | |
2017 | } | |
2018 | } | |
b508a996 RE |
2019 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2020 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2021 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2022 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2023 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2024 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2025 | { | |
2026 | /* If the the type is a plain integer, then the access is | |
2027 | straight-forward. Otherwise we have to play around a bit more. */ | |
2028 | int len = TYPE_LENGTH (type); | |
2029 | int regno = ARM_A1_REGNUM; | |
2030 | ULONGEST tmp; | |
2031 | ||
2032 | while (len > 0) | |
2033 | { | |
2034 | /* By using store_unsigned_integer we avoid having to do | |
2035 | anything special for small big-endian values. */ | |
2036 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2037 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2038 | (len > INT_REGISTER_SIZE |
2039 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2040 | tmp); |
7a5ea0d4 DJ |
2041 | len -= INT_REGISTER_SIZE; |
2042 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2043 | } |
2044 | } | |
ed9a39eb | 2045 | else |
b508a996 RE |
2046 | { |
2047 | /* For a structure or union the behaviour is as if the value had | |
2048 | been stored to word-aligned memory and then loaded into | |
2049 | registers with 32-bit load instruction(s). */ | |
2050 | int len = TYPE_LENGTH (type); | |
2051 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2052 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2053 | |
2054 | while (len > 0) | |
2055 | { | |
2056 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2057 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2058 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2059 | len -= INT_REGISTER_SIZE; | |
2060 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2061 | } |
2062 | } | |
34e8f22d RE |
2063 | } |
2064 | ||
67255d04 RE |
2065 | /* Extract from an array REGBUF containing the (raw) register state |
2066 | the address in which a function should return its structure value. */ | |
2067 | ||
2068 | static CORE_ADDR | |
95f95911 | 2069 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2070 | { |
95f95911 MS |
2071 | ULONGEST ret; |
2072 | ||
2073 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2074 | return ret; | |
67255d04 RE |
2075 | } |
2076 | ||
2077 | /* Will a function return an aggregate type in memory or in a | |
2078 | register? Return 0 if an aggregate type can be returned in a | |
2079 | register, 1 if it must be returned in memory. */ | |
2080 | ||
2081 | static int | |
2082 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2083 | { | |
2084 | int nRc; | |
52f0bd74 | 2085 | enum type_code code; |
67255d04 | 2086 | |
44e1a9eb DJ |
2087 | CHECK_TYPEDEF (type); |
2088 | ||
67255d04 RE |
2089 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2090 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2091 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2092 | offset of each addressable subfield must be zero. Note that bit | |
2093 | fields are not addressable, and all addressable subfields of | |
2094 | unions always start at offset zero. | |
67255d04 RE |
2095 | |
2096 | This function is based on the behaviour of GCC 2.95.1. | |
2097 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2098 | ||
2099 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2100 | parameters correctly for a function returning the following | |
2101 | structure: struct { float f;}; This should be returned in memory, | |
2102 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2103 | know of any way to detect if a function like the above has been | |
2104 | compiled with the correct calling convention. */ | |
2105 | ||
2106 | /* All aggregate types that won't fit in a register must be returned | |
2107 | in memory. */ | |
b1e29e33 | 2108 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2109 | { |
2110 | return 1; | |
2111 | } | |
2112 | ||
2113 | /* The only aggregate types that can be returned in a register are | |
2114 | structs and unions. Arrays must be returned in memory. */ | |
2115 | code = TYPE_CODE (type); | |
2116 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2117 | { | |
2118 | return 1; | |
2119 | } | |
2120 | ||
2121 | /* Assume all other aggregate types can be returned in a register. | |
2122 | Run a check for structures, unions and arrays. */ | |
2123 | nRc = 0; | |
2124 | ||
2125 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2126 | { | |
2127 | int i; | |
2128 | /* Need to check if this struct/union is "integer" like. For | |
2129 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2130 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2131 | subfield must be zero. Note that bit fields are not | |
2132 | addressable, and unions always start at offset zero. If any | |
2133 | of the subfields is a floating point type, the struct/union | |
2134 | cannot be an integer type. */ | |
67255d04 RE |
2135 | |
2136 | /* For each field in the object, check: | |
2137 | 1) Is it FP? --> yes, nRc = 1; | |
2138 | 2) Is it addressable (bitpos != 0) and | |
2139 | not packed (bitsize == 0)? | |
2140 | --> yes, nRc = 1 | |
2141 | */ | |
2142 | ||
2143 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2144 | { | |
2145 | enum type_code field_type_code; | |
44e1a9eb | 2146 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2147 | |
2148 | /* Is it a floating point type field? */ | |
2149 | if (field_type_code == TYPE_CODE_FLT) | |
2150 | { | |
2151 | nRc = 1; | |
2152 | break; | |
2153 | } | |
2154 | ||
2155 | /* If bitpos != 0, then we have to care about it. */ | |
2156 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2157 | { | |
2158 | /* Bitfields are not addressable. If the field bitsize is | |
2159 | zero, then the field is not packed. Hence it cannot be | |
2160 | a bitfield or any other packed type. */ | |
2161 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2162 | { | |
2163 | nRc = 1; | |
2164 | break; | |
2165 | } | |
2166 | } | |
2167 | } | |
2168 | } | |
2169 | ||
2170 | return nRc; | |
2171 | } | |
2172 | ||
34e8f22d RE |
2173 | /* Write into appropriate registers a function return value of type |
2174 | TYPE, given in virtual format. */ | |
2175 | ||
2176 | static void | |
b508a996 RE |
2177 | arm_store_return_value (struct type *type, struct regcache *regs, |
2178 | const void *src) | |
34e8f22d | 2179 | { |
b508a996 RE |
2180 | const bfd_byte *valbuf = src; |
2181 | ||
34e8f22d RE |
2182 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2183 | { | |
7a5ea0d4 | 2184 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2185 | |
fd50bc42 | 2186 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2187 | { |
2188 | case ARM_FLOAT_FPA: | |
2189 | ||
b508a996 RE |
2190 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2191 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2192 | break; |
2193 | ||
fd50bc42 | 2194 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2195 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2196 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2197 | if (TYPE_LENGTH (type) > 4) | |
2198 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2199 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2200 | break; |
2201 | ||
2202 | default: | |
2203 | internal_error | |
2204 | (__FILE__, __LINE__, | |
2205 | "arm_store_return_value: Floating point model not supported"); | |
2206 | break; | |
2207 | } | |
34e8f22d | 2208 | } |
b508a996 RE |
2209 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2210 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2211 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2212 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2213 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2214 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2215 | { | |
2216 | if (TYPE_LENGTH (type) <= 4) | |
2217 | { | |
2218 | /* Values of one word or less are zero/sign-extended and | |
2219 | returned in r0. */ | |
7a5ea0d4 | 2220 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2221 | LONGEST val = unpack_long (type, valbuf); |
2222 | ||
7a5ea0d4 | 2223 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2224 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2225 | } | |
2226 | else | |
2227 | { | |
2228 | /* Integral values greater than one word are stored in consecutive | |
2229 | registers starting with r0. This will always be a multiple of | |
2230 | the regiser size. */ | |
2231 | int len = TYPE_LENGTH (type); | |
2232 | int regno = ARM_A1_REGNUM; | |
2233 | ||
2234 | while (len > 0) | |
2235 | { | |
2236 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2237 | len -= INT_REGISTER_SIZE; |
2238 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2239 | } |
2240 | } | |
2241 | } | |
34e8f22d | 2242 | else |
b508a996 RE |
2243 | { |
2244 | /* For a structure or union the behaviour is as if the value had | |
2245 | been stored to word-aligned memory and then loaded into | |
2246 | registers with 32-bit load instruction(s). */ | |
2247 | int len = TYPE_LENGTH (type); | |
2248 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2249 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2250 | |
2251 | while (len > 0) | |
2252 | { | |
2253 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2254 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2255 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2256 | len -= INT_REGISTER_SIZE; |
2257 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2258 | } |
2259 | } | |
34e8f22d RE |
2260 | } |
2261 | ||
9df628e0 RE |
2262 | static int |
2263 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2264 | { | |
2265 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2266 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2267 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2268 | ||
2269 | jb_addr = read_register (ARM_A1_REGNUM); | |
2270 | ||
2271 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2272 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2273 | return 0; |
2274 | ||
7a5ea0d4 | 2275 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2276 | return 1; |
2277 | } | |
2278 | ||
ed9a39eb | 2279 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2280 | |
2281 | int | |
ed9a39eb | 2282 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2283 | { |
2284 | CORE_ADDR start_addr; | |
2285 | ||
ed9a39eb JM |
2286 | /* Find the starting address of the function containing the PC. If |
2287 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2288 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2289 | &start_addr, NULL)) | |
c906108c SS |
2290 | return 0; |
2291 | ||
2292 | return strncmp (name, "_call_via_r", 11) == 0; | |
2293 | } | |
2294 | ||
ed9a39eb JM |
2295 | /* If PC is in a Thumb call or return stub, return the address of the |
2296 | target PC, which is in a register. The thunk functions are called | |
2297 | _called_via_xx, where x is the register name. The possible names | |
2298 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2299 | |
2300 | CORE_ADDR | |
ed9a39eb | 2301 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2302 | { |
c5aa993b | 2303 | char *name; |
c906108c SS |
2304 | CORE_ADDR start_addr; |
2305 | ||
2306 | /* Find the starting address and name of the function containing the PC. */ | |
2307 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2308 | return 0; | |
2309 | ||
2310 | /* Call thunks always start with "_call_via_". */ | |
2311 | if (strncmp (name, "_call_via_", 10) == 0) | |
2312 | { | |
ed9a39eb JM |
2313 | /* Use the name suffix to determine which register contains the |
2314 | target PC. */ | |
c5aa993b JM |
2315 | static char *table[15] = |
2316 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2317 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2318 | }; | |
c906108c SS |
2319 | int regno; |
2320 | ||
2321 | for (regno = 0; regno <= 14; regno++) | |
2322 | if (strcmp (&name[10], table[regno]) == 0) | |
2323 | return read_register (regno); | |
2324 | } | |
ed9a39eb | 2325 | |
c5aa993b | 2326 | return 0; /* not a stub */ |
c906108c SS |
2327 | } |
2328 | ||
afd7eef0 RE |
2329 | static void |
2330 | set_arm_command (char *args, int from_tty) | |
2331 | { | |
2332 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); | |
2333 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); | |
2334 | } | |
2335 | ||
2336 | static void | |
2337 | show_arm_command (char *args, int from_tty) | |
2338 | { | |
26304000 | 2339 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2340 | } |
2341 | ||
fd50bc42 RE |
2342 | enum arm_float_model |
2343 | arm_get_fp_model (struct gdbarch *gdbarch) | |
2344 | { | |
2345 | if (arm_fp_model == ARM_FLOAT_AUTO) | |
2346 | return gdbarch_tdep (gdbarch)->fp_model; | |
2347 | ||
2348 | return arm_fp_model; | |
2349 | } | |
2350 | ||
2351 | static void | |
2352 | arm_set_fp (struct gdbarch *gdbarch) | |
2353 | { | |
2354 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); | |
2355 | ||
2356 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE | |
2357 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) | |
2358 | { | |
2359 | set_gdbarch_double_format (gdbarch, | |
2360 | &floatformat_ieee_double_littlebyte_bigword); | |
2361 | set_gdbarch_long_double_format | |
2362 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2363 | } | |
2364 | else | |
2365 | { | |
2366 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2367 | set_gdbarch_long_double_format (gdbarch, | |
2368 | &floatformat_ieee_double_little); | |
2369 | } | |
2370 | } | |
2371 | ||
2372 | static void | |
2373 | set_fp_model_sfunc (char *args, int from_tty, | |
2374 | struct cmd_list_element *c) | |
2375 | { | |
2376 | enum arm_float_model fp_model; | |
2377 | ||
2378 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2379 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2380 | { | |
2381 | arm_fp_model = fp_model; | |
2382 | break; | |
2383 | } | |
2384 | ||
2385 | if (fp_model == ARM_FLOAT_LAST) | |
2386 | internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", | |
2387 | current_fp_model); | |
2388 | ||
2389 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2390 | arm_set_fp (current_gdbarch); | |
2391 | } | |
2392 | ||
2393 | static void | |
2394 | show_fp_model (char *args, int from_tty, | |
2395 | struct cmd_list_element *c) | |
2396 | { | |
2397 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2398 | ||
2399 | if (arm_fp_model == ARM_FLOAT_AUTO | |
2400 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2401 | printf_filtered (" - the default for the current ABI is \"%s\".\n", | |
2402 | fp_model_strings[tdep->fp_model]); | |
2403 | } | |
2404 | ||
afd7eef0 RE |
2405 | /* If the user changes the register disassembly style used for info |
2406 | register and other commands, we have to also switch the style used | |
2407 | in opcodes for disassembly output. This function is run in the "set | |
2408 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2409 | |
2410 | static void | |
afd7eef0 | 2411 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2412 | struct cmd_list_element *c) |
2413 | { | |
afd7eef0 | 2414 | set_disassembly_style (); |
bc90b915 FN |
2415 | } |
2416 | \f | |
966fbf70 | 2417 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2418 | static const char * |
34e8f22d | 2419 | arm_register_name (int i) |
966fbf70 RE |
2420 | { |
2421 | return arm_register_names[i]; | |
2422 | } | |
2423 | ||
bc90b915 | 2424 | static void |
afd7eef0 | 2425 | set_disassembly_style (void) |
bc90b915 FN |
2426 | { |
2427 | const char *setname, *setdesc, **regnames; | |
2428 | int numregs, j; | |
2429 | ||
afd7eef0 | 2430 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2431 | int current = 0; |
2432 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2433 | while ((disassembly_style != setname) |
2434 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2435 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2436 | current_option = current; | |
2437 | ||
94c30b78 | 2438 | /* Fill our copy. */ |
bc90b915 FN |
2439 | for (j = 0; j < numregs; j++) |
2440 | arm_register_names[j] = (char *) regnames[j]; | |
2441 | ||
94c30b78 | 2442 | /* Adjust case. */ |
34e8f22d | 2443 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2444 | { |
34e8f22d RE |
2445 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2446 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2447 | } |
2448 | else | |
2449 | { | |
34e8f22d RE |
2450 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2451 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2452 | } |
2453 | ||
94c30b78 | 2454 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2455 | set_arm_regname_option (current); |
2456 | } | |
2457 | ||
afd7eef0 RE |
2458 | /* arm_othernames implements the "othernames" command. This is deprecated |
2459 | by the "set arm disassembly" command. */ | |
bc90b915 FN |
2460 | |
2461 | static void | |
2462 | arm_othernames (char *names, int n) | |
2463 | { | |
94c30b78 | 2464 | /* Circle through the various flavors. */ |
afd7eef0 | 2465 | current_option = (current_option + 1) % num_disassembly_options; |
bc90b915 | 2466 | |
afd7eef0 RE |
2467 | disassembly_style = valid_disassembly_styles[current_option]; |
2468 | set_disassembly_style (); | |
bc90b915 FN |
2469 | } |
2470 | ||
082fc60d RE |
2471 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2472 | function. */ | |
2473 | ||
2474 | static int | |
2475 | coff_sym_is_thumb (int val) | |
2476 | { | |
2477 | return (val == C_THUMBEXT || | |
2478 | val == C_THUMBSTAT || | |
2479 | val == C_THUMBEXTFUNC || | |
2480 | val == C_THUMBSTATFUNC || | |
2481 | val == C_THUMBLABEL); | |
2482 | } | |
2483 | ||
2484 | /* arm_coff_make_msymbol_special() | |
2485 | arm_elf_make_msymbol_special() | |
2486 | ||
2487 | These functions test whether the COFF or ELF symbol corresponds to | |
2488 | an address in thumb code, and set a "special" bit in a minimal | |
2489 | symbol to indicate that it does. */ | |
2490 | ||
34e8f22d | 2491 | static void |
082fc60d RE |
2492 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2493 | { | |
2494 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2495 | STT_ARM_TFUNC). */ | |
2496 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2497 | == STT_LOPROC) | |
2498 | MSYMBOL_SET_SPECIAL (msym); | |
2499 | } | |
2500 | ||
34e8f22d | 2501 | static void |
082fc60d RE |
2502 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2503 | { | |
2504 | if (coff_sym_is_thumb (val)) | |
2505 | MSYMBOL_SET_SPECIAL (msym); | |
2506 | } | |
2507 | ||
756fe439 DJ |
2508 | static void |
2509 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2510 | { | |
2511 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2512 | ||
2513 | /* If necessary, set the T bit. */ | |
2514 | if (arm_apcs_32) | |
2515 | { | |
2516 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2517 | if (arm_pc_is_thumb (pc)) | |
2518 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2519 | else | |
2520 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2521 | } | |
2522 | } | |
97e03143 | 2523 | \f |
70f80edf JT |
2524 | static enum gdb_osabi |
2525 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2526 | { |
70f80edf JT |
2527 | unsigned int elfosabi, eflags; |
2528 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2529 | |
70f80edf | 2530 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2531 | |
70f80edf | 2532 | switch (elfosabi) |
97e03143 | 2533 | { |
70f80edf JT |
2534 | case ELFOSABI_NONE: |
2535 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2536 | file are conforming to the base specification for that machine | |
2537 | (there are no OS-specific extensions). In order to determine the | |
2538 | real OS in use we must look for OS notes that have been added. */ | |
2539 | bfd_map_over_sections (abfd, | |
2540 | generic_elf_osabi_sniff_abi_tag_sections, | |
2541 | &osabi); | |
2542 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2543 | { |
70f80edf JT |
2544 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2545 | field for more information. */ | |
2546 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2547 | switch (eflags) | |
97e03143 | 2548 | { |
70f80edf JT |
2549 | case EF_ARM_EABI_VER1: |
2550 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2551 | break; |
2552 | ||
70f80edf JT |
2553 | case EF_ARM_EABI_VER2: |
2554 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2555 | break; |
2556 | ||
70f80edf JT |
2557 | case EF_ARM_EABI_UNKNOWN: |
2558 | /* Assume GNU tools. */ | |
2559 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2560 | break; |
2561 | ||
70f80edf JT |
2562 | default: |
2563 | internal_error (__FILE__, __LINE__, | |
2564 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2565 | "version 0x%x", eflags); | |
97e03143 RE |
2566 | } |
2567 | } | |
70f80edf | 2568 | break; |
97e03143 | 2569 | |
70f80edf JT |
2570 | case ELFOSABI_ARM: |
2571 | /* GNU tools use this value. Check note sections in this case, | |
2572 | as well. */ | |
97e03143 | 2573 | bfd_map_over_sections (abfd, |
70f80edf JT |
2574 | generic_elf_osabi_sniff_abi_tag_sections, |
2575 | &osabi); | |
2576 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2577 | { |
70f80edf JT |
2578 | /* Assume APCS ABI. */ |
2579 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2580 | } |
2581 | break; | |
2582 | ||
97e03143 | 2583 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2584 | osabi = GDB_OSABI_FREEBSD_ELF; |
2585 | break; | |
97e03143 | 2586 | |
70f80edf JT |
2587 | case ELFOSABI_NETBSD: |
2588 | osabi = GDB_OSABI_NETBSD_ELF; | |
2589 | break; | |
97e03143 | 2590 | |
70f80edf JT |
2591 | case ELFOSABI_LINUX: |
2592 | osabi = GDB_OSABI_LINUX; | |
2593 | break; | |
97e03143 RE |
2594 | } |
2595 | ||
70f80edf | 2596 | return osabi; |
97e03143 RE |
2597 | } |
2598 | ||
70f80edf | 2599 | \f |
da3c6d4a MS |
2600 | /* Initialize the current architecture based on INFO. If possible, |
2601 | re-use an architecture from ARCHES, which is a list of | |
2602 | architectures already created during this debugging session. | |
97e03143 | 2603 | |
da3c6d4a MS |
2604 | Called e.g. at program startup, when reading a core file, and when |
2605 | reading a binary file. */ | |
97e03143 | 2606 | |
39bbf761 RE |
2607 | static struct gdbarch * |
2608 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2609 | { | |
97e03143 | 2610 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2611 | struct gdbarch *gdbarch; |
2612 | ||
97e03143 | 2613 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2614 | |
4be87837 | 2615 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2616 | { |
4be87837 | 2617 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2618 | { |
4be87837 DJ |
2619 | case bfd_target_aout_flavour: |
2620 | /* Assume it's an old APCS-style ABI. */ | |
2621 | info.osabi = GDB_OSABI_ARM_APCS; | |
2622 | break; | |
97e03143 | 2623 | |
4be87837 DJ |
2624 | case bfd_target_coff_flavour: |
2625 | /* Assume it's an old APCS-style ABI. */ | |
2626 | /* XXX WinCE? */ | |
2627 | info.osabi = GDB_OSABI_ARM_APCS; | |
2628 | break; | |
97e03143 | 2629 | |
4be87837 DJ |
2630 | default: |
2631 | /* Leave it as "unknown". */ | |
50ceaba5 | 2632 | break; |
97e03143 RE |
2633 | } |
2634 | } | |
2635 | ||
4be87837 DJ |
2636 | /* If there is already a candidate, use it. */ |
2637 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2638 | if (arches != NULL) | |
2639 | return arches->gdbarch; | |
97e03143 RE |
2640 | |
2641 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2642 | gdbarch = gdbarch_alloc (&info, tdep); | |
2643 | ||
fd50bc42 RE |
2644 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
2645 | now, and we now provide a way for the user to force the model. So | |
2646 | default to the most useful variant. */ | |
2647 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
08216dd7 RE |
2648 | |
2649 | /* Breakpoints. */ | |
67255d04 RE |
2650 | switch (info.byte_order) |
2651 | { | |
2652 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2653 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2654 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2655 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2656 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2657 | ||
67255d04 RE |
2658 | break; |
2659 | ||
2660 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2661 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2662 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2663 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2664 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2665 | ||
67255d04 RE |
2666 | break; |
2667 | ||
2668 | default: | |
2669 | internal_error (__FILE__, __LINE__, | |
2670 | "arm_gdbarch_init: bad byte order for float format"); | |
2671 | } | |
2672 | ||
d7b486e7 RE |
2673 | /* On ARM targets char defaults to unsigned. */ |
2674 | set_gdbarch_char_signed (gdbarch, 0); | |
2675 | ||
9df628e0 | 2676 | /* This should be low enough for everything. */ |
97e03143 | 2677 | tdep->lowest_pc = 0x20; |
94c30b78 | 2678 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2679 | |
2dd604e7 | 2680 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2681 | |
756fe439 DJ |
2682 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2683 | ||
148754e5 | 2684 | /* Frame handling. */ |
eb5492fa DJ |
2685 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2686 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2687 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2688 | ||
eb5492fa | 2689 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2690 | |
34e8f22d RE |
2691 | /* Address manipulation. */ |
2692 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2693 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2694 | ||
34e8f22d RE |
2695 | /* Advance PC across function entry code. */ |
2696 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2697 | ||
2698 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2699 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2700 | |
2701 | /* The stack grows downward. */ | |
2702 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2703 | ||
2704 | /* Breakpoint manipulation. */ | |
2705 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2706 | |
2707 | /* Information about registers, etc. */ | |
2708 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2709 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2710 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2711 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2712 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2713 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2714 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2715 | |
26216b98 AC |
2716 | /* Internal <-> external register number maps. */ |
2717 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2718 | ||
34e8f22d | 2719 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2720 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2721 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2722 | ||
2723 | /* Returning results. */ | |
b508a996 RE |
2724 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2725 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
b5622e8d | 2726 | set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention); |
74055713 | 2727 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); |
34e8f22d RE |
2728 | |
2729 | /* Single stepping. */ | |
2730 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2731 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2732 | ||
03d48a7d RE |
2733 | /* Disassembly. */ |
2734 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2735 | ||
34e8f22d RE |
2736 | /* Minsymbol frobbing. */ |
2737 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2738 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2739 | arm_coff_make_msymbol_special); | |
2740 | ||
97e03143 | 2741 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2742 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2743 | |
eb5492fa DJ |
2744 | /* Add some default predicates. */ |
2745 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); | |
2746 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); | |
2747 | ||
97e03143 RE |
2748 | /* Now we have tuned the configuration, set a few final things, |
2749 | based on what the OS ABI has told us. */ | |
2750 | ||
9df628e0 RE |
2751 | if (tdep->jb_pc >= 0) |
2752 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2753 | ||
08216dd7 RE |
2754 | /* Floating point sizes and format. */ |
2755 | switch (info.byte_order) | |
2756 | { | |
2757 | case BFD_ENDIAN_BIG: | |
2758 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2759 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2760 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2761 | ||
2762 | break; | |
2763 | ||
2764 | case BFD_ENDIAN_LITTLE: | |
2765 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
fd50bc42 | 2766 | arm_set_fp (gdbarch); |
08216dd7 RE |
2767 | break; |
2768 | ||
2769 | default: | |
2770 | internal_error (__FILE__, __LINE__, | |
2771 | "arm_gdbarch_init: bad byte order for float format"); | |
2772 | } | |
2773 | ||
39bbf761 RE |
2774 | return gdbarch; |
2775 | } | |
2776 | ||
97e03143 RE |
2777 | static void |
2778 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2779 | { | |
2780 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2781 | ||
2782 | if (tdep == NULL) | |
2783 | return; | |
2784 | ||
97e03143 RE |
2785 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
2786 | (unsigned long) tdep->lowest_pc); | |
2787 | } | |
2788 | ||
2789 | static void | |
2790 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2791 | struct gdbarch *gdbarch) | |
2792 | { | |
2793 | /* Place-holder. */ | |
2794 | } | |
2795 | ||
2796 | static void | |
2797 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2798 | struct gdbarch *gdbarch) | |
2799 | { | |
2800 | /* Place-holder. */ | |
2801 | } | |
2802 | ||
2803 | static void | |
2804 | arm_init_abi_apcs (struct gdbarch_info info, | |
2805 | struct gdbarch *gdbarch) | |
2806 | { | |
2807 | /* Place-holder. */ | |
2808 | } | |
2809 | ||
a78f21af AC |
2810 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2811 | ||
c906108c | 2812 | void |
ed9a39eb | 2813 | _initialize_arm_tdep (void) |
c906108c | 2814 | { |
bc90b915 FN |
2815 | struct ui_file *stb; |
2816 | long length; | |
26304000 | 2817 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2818 | const char *setname; |
2819 | const char *setdesc; | |
2820 | const char **regnames; | |
bc90b915 FN |
2821 | int numregs, i, j; |
2822 | static char *helptext; | |
085dd6e6 | 2823 | |
42cf1509 | 2824 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2825 | |
70f80edf JT |
2826 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2827 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2828 | bfd_target_elf_flavour, | |
2829 | arm_elf_osabi_sniffer); | |
2830 | ||
97e03143 | 2831 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 2832 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 2833 | arm_init_abi_eabi_v1); |
05816f70 | 2834 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 2835 | arm_init_abi_eabi_v2); |
05816f70 | 2836 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 2837 | arm_init_abi_apcs); |
39bbf761 | 2838 | |
94c30b78 | 2839 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2840 | num_disassembly_options = get_arm_regname_num_options (); |
2841 | ||
2842 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2843 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
2844 | "Various ARM-specific commands.", | |
2845 | &setarmcmdlist, "set arm ", 0, &setlist); | |
2846 | ||
2847 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
2848 | "Various ARM-specific commands.", | |
2849 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 2850 | |
94c30b78 | 2851 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2852 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2853 | |
94c30b78 | 2854 | /* Begin creating the help text. */ |
bc90b915 | 2855 | stb = mem_fileopen (); |
afd7eef0 RE |
2856 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
2857 | "The valid values are:\n"); | |
ed9a39eb | 2858 | |
94c30b78 | 2859 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
afd7eef0 RE |
2860 | valid_disassembly_styles |
2861 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2862 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2863 | { |
2864 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2865 | valid_disassembly_styles[i] = setname; |
bc90b915 FN |
2866 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
2867 | setdesc); | |
94c30b78 | 2868 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2869 | if (!strcmp (setname, "std")) |
2870 | { | |
afd7eef0 | 2871 | disassembly_style = setname; |
bc90b915 FN |
2872 | current_option = i; |
2873 | for (j = 0; j < numregs; j++) | |
2874 | arm_register_names[j] = (char *) regnames[j]; | |
2875 | set_arm_regname_option (i); | |
2876 | } | |
2877 | } | |
94c30b78 | 2878 | /* Mark the end of valid options. */ |
afd7eef0 | 2879 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2880 | |
94c30b78 | 2881 | /* Finish the creation of the help text. */ |
bc90b915 FN |
2882 | fprintf_unfiltered (stb, "The default is \"std\"."); |
2883 | helptext = ui_file_xstrdup (stb, &length); | |
2884 | ui_file_delete (stb); | |
ed9a39eb | 2885 | |
afd7eef0 | 2886 | /* Add the deprecated disassembly-flavor command. */ |
26304000 | 2887 | new_set = add_set_enum_cmd ("disassembly-flavor", no_class, |
afd7eef0 RE |
2888 | valid_disassembly_styles, |
2889 | &disassembly_style, | |
bc90b915 | 2890 | helptext, |
ed9a39eb | 2891 | &setlist); |
26304000 RE |
2892 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
2893 | deprecate_cmd (new_set, "set arm disassembly"); | |
cb1a6d5f | 2894 | deprecate_cmd (deprecated_add_show_from_set (new_set, &showlist), |
afd7eef0 RE |
2895 | "show arm disassembly"); |
2896 | ||
2897 | /* And now add the new interface. */ | |
30757f90 | 2898 | new_set = add_set_enum_cmd ("disassembler", no_class, |
26304000 RE |
2899 | valid_disassembly_styles, &disassembly_style, |
2900 | helptext, &setarmcmdlist); | |
2901 | ||
fd50bc42 | 2902 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
cb1a6d5f | 2903 | deprecated_add_show_from_set (new_set, &showarmcmdlist); |
26304000 | 2904 | |
3b64bf98 AC |
2905 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, "\ |
2906 | Set usage of ARM 32-bit mode.", "\ | |
2907 | Show usage of ARM 32-bit mode.", "\ | |
2908 | When off, a 26-bit PC will be used.\n\ | |
2909 | When off, a 26-bit PC will be used.", "\ | |
2910 | Usage of ARM 32-bit mode is %s.", | |
26304000 RE |
2911 | NULL, NULL, |
2912 | &setarmcmdlist, &showarmcmdlist); | |
c906108c | 2913 | |
fd50bc42 RE |
2914 | /* Add a command to allow the user to force the FPU model. */ |
2915 | new_set = add_set_enum_cmd | |
2916 | ("fpu", no_class, fp_model_strings, ¤t_fp_model, | |
2917 | "Set the floating point type.\n" | |
2918 | "auto - Determine the FP typefrom the OS-ABI.\n" | |
2919 | "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" | |
2920 | "fpa - FPA co-processor (GCC compiled).\n" | |
2921 | "softvfp - Software FP with pure-endian doubles.\n" | |
2922 | "vfp - VFP co-processor.", | |
2923 | &setarmcmdlist); | |
2924 | set_cmd_sfunc (new_set, set_fp_model_sfunc); | |
cb1a6d5f AC |
2925 | set_cmd_sfunc (deprecated_add_show_from_set (new_set, &showarmcmdlist), |
2926 | show_fp_model); | |
fd50bc42 | 2927 | |
94c30b78 | 2928 | /* Add the deprecated "othernames" command. */ |
afd7eef0 RE |
2929 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
2930 | "Switch to the next set of register names."), | |
2931 | "set arm disassembly"); | |
c3b4394c | 2932 | |
6529d2dd | 2933 | /* Debugging flag. */ |
3b64bf98 AC |
2934 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, "\ |
2935 | Set ARM debugging.", "\ | |
2936 | Show ARM debugging.", "\ | |
2937 | When on, arm-specific debugging is enabled.", "\ | |
2938 | ARM debugging is %s.", | |
26304000 RE |
2939 | NULL, NULL, |
2940 | &setdebuglist, &showdebuglist); | |
c906108c | 2941 | } |