Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
34e8f22d RE |
37 | |
38 | #include "arm-tdep.h" | |
39 | ||
082fc60d RE |
40 | #include "elf-bfd.h" |
41 | #include "coff/internal.h" | |
97e03143 | 42 | #include "elf/arm.h" |
c906108c | 43 | |
2a451106 KB |
44 | /* Each OS has a different mechanism for accessing the various |
45 | registers stored in the sigcontext structure. | |
46 | ||
47 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
48 | function pointer) which may be used to determine the addresses | |
49 | of the various saved registers in the sigcontext structure. | |
50 | ||
51 | For the ARM target, there are three parameters to this function. | |
52 | The first is the pc value of the frame under consideration, the | |
53 | second the stack pointer of this frame, and the last is the | |
54 | register number to fetch. | |
55 | ||
56 | If the tm.h file does not define this macro, then it's assumed that | |
57 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
58 | be 0. | |
59 | ||
60 | When it comes time to multi-arching this code, see the identically | |
61 | named machinery in ia64-tdep.c for an example of how it could be | |
62 | done. It should not be necessary to modify the code below where | |
63 | this macro is used. */ | |
64 | ||
3bb04bdd AC |
65 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
66 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
67 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
68 | #endif | |
69 | #else | |
70 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
71 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
72 | #endif |
73 | ||
082fc60d RE |
74 | /* Macros for setting and testing a bit in a minimal symbol that marks |
75 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
76 | is used for this purpose. This field is already being used to store | |
77 | the symbol size, so the assumption is that the symbol size cannot | |
78 | exceed 2^31. | |
79 | ||
80 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
81 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
82 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
83 | i.e. the "info" field with the "special" bit | |
84 | masked out. */ | |
85 | ||
86 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
87 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
88 | | 0x80000000) | |
89 | ||
90 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
91 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
92 | ||
93 | #define MSYMBOL_SIZE(msym) \ | |
94 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 95 | |
ed9d4749 | 96 | /* This table matches the indices assigned to enum arm_abi. |
94c30b78 | 97 | Keep them in sync. */ |
97e03143 RE |
98 | |
99 | static const char * const arm_abi_names[] = | |
100 | { | |
101 | "<unknown>", | |
102 | "ARM EABI (version 1)", | |
103 | "ARM EABI (version 2)", | |
104 | "GNU/Linux", | |
105 | "NetBSD (a.out)", | |
106 | "NetBSD (ELF)", | |
107 | "APCS", | |
108 | "FreeBSD", | |
109 | "Windows CE", | |
110 | NULL | |
111 | }; | |
112 | ||
94c30b78 | 113 | /* Number of different reg name sets (options). */ |
bc90b915 FN |
114 | static int num_flavor_options; |
115 | ||
116 | /* We have more registers than the disassembler as gdb can print the value | |
117 | of special registers as well. | |
118 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 119 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 120 | |
94c30b78 | 121 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 122 | static char * arm_register_name_strings[] = |
da59e081 JM |
123 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
124 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
125 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
126 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
127 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
128 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 129 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 130 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 131 | |
bc90b915 | 132 | /* Valid register name flavors. */ |
53904c9e | 133 | static const char **valid_flavors; |
ed9a39eb | 134 | |
94c30b78 | 135 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 136 | static const char *disassembly_flavor; |
94c30b78 | 137 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 138 | static int current_option; |
96baa820 | 139 | |
ed9a39eb JM |
140 | /* This is used to keep the bfd arch_info in sync with the disassembly |
141 | flavor. */ | |
142 | static void set_disassembly_flavor_sfunc(char *, int, | |
143 | struct cmd_list_element *); | |
144 | static void set_disassembly_flavor (void); | |
145 | ||
146 | static void convert_from_extended (void *ptr, void *dbl); | |
147 | ||
148 | /* Define other aspects of the stack frame. We keep the offsets of | |
149 | all saved registers, 'cause we need 'em a lot! We also keep the | |
150 | current size of the stack frame, and the offset of the frame | |
151 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 152 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
153 | |
154 | struct frame_extra_info | |
c3b4394c RE |
155 | { |
156 | int framesize; | |
157 | int frameoffset; | |
158 | int framereg; | |
159 | }; | |
ed9a39eb | 160 | |
bc90b915 FN |
161 | /* Addresses for calling Thumb functions have the bit 0 set. |
162 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
163 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
164 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
165 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
166 | ||
39bbf761 | 167 | static int |
ed9a39eb | 168 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 169 | { |
c906108c SS |
170 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
171 | } | |
172 | ||
94c30b78 | 173 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
174 | |
175 | int arm_apcs_32 = 1; | |
176 | ||
ed9a39eb JM |
177 | /* Flag set by arm_fix_call_dummy that tells whether the target |
178 | function is a Thumb function. This flag is checked by | |
179 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
180 | its use in valops.c) to pass the function address as an additional | |
181 | parameter. */ | |
c906108c SS |
182 | |
183 | static int target_is_thumb; | |
184 | ||
ed9a39eb JM |
185 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
186 | function is a Thumb function. This flag is checked by | |
187 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
188 | |
189 | static int caller_is_thumb; | |
190 | ||
ed9a39eb JM |
191 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
192 | function. */ | |
c906108c | 193 | |
34e8f22d | 194 | int |
2a451106 | 195 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 196 | { |
c5aa993b | 197 | struct minimal_symbol *sym; |
c906108c | 198 | |
ed9a39eb | 199 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
200 | if (IS_THUMB_ADDR (memaddr)) |
201 | return 1; | |
202 | ||
ed9a39eb | 203 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
204 | sym = lookup_minimal_symbol_by_pc (memaddr); |
205 | if (sym) | |
206 | { | |
c5aa993b | 207 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
208 | } |
209 | else | |
ed9a39eb JM |
210 | { |
211 | return 0; | |
212 | } | |
c906108c SS |
213 | } |
214 | ||
ed9a39eb JM |
215 | /* Determine if the program counter specified in MEMADDR is in a call |
216 | dummy being called from a Thumb function. */ | |
c906108c | 217 | |
34e8f22d | 218 | int |
2a451106 | 219 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 220 | { |
c5aa993b | 221 | CORE_ADDR sp = read_sp (); |
c906108c | 222 | |
dfcd3bfb JM |
223 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
224 | is the best we can do. We are trying to determine if the pc is on | |
225 | the stack, which (hopefully) will only happen in a call dummy. | |
226 | We hope the current stack pointer is not so far alway from the dummy | |
227 | frame location (true if we have not pushed large data structures or | |
228 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 229 | code regions as part of the stack (true for most practical purposes). */ |
dfcd3bfb | 230 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
231 | return caller_is_thumb; |
232 | else | |
233 | return 0; | |
234 | } | |
235 | ||
181c1381 | 236 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 237 | static CORE_ADDR |
ed9a39eb | 238 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
239 | { |
240 | if (arm_pc_is_thumb (val)) | |
241 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
242 | else | |
243 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
244 | } | |
245 | ||
181c1381 RE |
246 | /* When reading symbols, we need to zap the low bit of the address, |
247 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 248 | static CORE_ADDR |
181c1381 RE |
249 | arm_smash_text_address (CORE_ADDR val) |
250 | { | |
251 | return val & ~1; | |
252 | } | |
253 | ||
34e8f22d RE |
254 | /* Immediately after a function call, return the saved pc. Can't |
255 | always go through the frames for this because on some machines the | |
256 | new frame is not set up until the new function executes some | |
257 | instructions. */ | |
258 | ||
259 | static CORE_ADDR | |
ed9a39eb | 260 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 261 | { |
34e8f22d | 262 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
263 | } |
264 | ||
0defa245 RE |
265 | /* Determine whether the function invocation represented by FI has a |
266 | frame on the stack associated with it. If it does return zero, | |
267 | otherwise return 1. */ | |
268 | ||
148754e5 | 269 | static int |
ed9a39eb | 270 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 271 | { |
392a587b | 272 | CORE_ADDR func_start, after_prologue; |
96baa820 | 273 | int frameless; |
ed9a39eb | 274 | |
0defa245 RE |
275 | /* Sometimes we have functions that do a little setup (like saving the |
276 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
277 | The symbol table will report this as a prologue. However, it is | |
278 | important not to try to parse these partial frames as frames, or we | |
279 | will get really confused. | |
280 | ||
281 | So I will demand 3 instructions between the start & end of the | |
282 | prologue before I call it a real prologue, i.e. at least | |
283 | mov ip, sp, | |
284 | stmdb sp!, {} | |
285 | sub sp, ip, #4. */ | |
286 | ||
392a587b | 287 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 288 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 289 | |
96baa820 | 290 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 291 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 292 | be func_start + 8. */ |
ed9a39eb | 293 | |
96baa820 | 294 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
295 | return frameless; |
296 | } | |
297 | ||
0defa245 | 298 | /* The address of the arguments in the frame. */ |
148754e5 | 299 | static CORE_ADDR |
0defa245 RE |
300 | arm_frame_args_address (struct frame_info *fi) |
301 | { | |
302 | return fi->frame; | |
303 | } | |
304 | ||
305 | /* The address of the local variables in the frame. */ | |
148754e5 | 306 | static CORE_ADDR |
0defa245 RE |
307 | arm_frame_locals_address (struct frame_info *fi) |
308 | { | |
309 | return fi->frame; | |
310 | } | |
311 | ||
312 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 313 | static int |
0defa245 RE |
314 | arm_frame_num_args (struct frame_info *fi) |
315 | { | |
316 | /* We have no way of knowing. */ | |
317 | return -1; | |
318 | } | |
319 | ||
c906108c | 320 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
321 | push {r7, lr} |
322 | add sp, sp, #-28 | |
323 | add r7, sp, #12 | |
c906108c | 324 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
325 | mov r7, sp |
326 | ||
327 | or like this: | |
328 | push {r7, lr} | |
329 | mov r7, sp | |
330 | sub sp, #12 | |
331 | ||
332 | or, on tpcs, like this: | |
333 | sub sp,#16 | |
334 | push {r7, lr} | |
335 | (many instructions) | |
336 | mov r7, sp | |
337 | sub sp, #12 | |
338 | ||
339 | There is always one instruction of three classes: | |
340 | 1 - push | |
341 | 2 - setting of r7 | |
342 | 3 - adjusting of sp | |
343 | ||
344 | When we have found at least one of each class we are done with the prolog. | |
345 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 346 | */ |
c906108c SS |
347 | |
348 | static CORE_ADDR | |
c7885828 | 349 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
350 | { |
351 | CORE_ADDR current_pc; | |
da3c6d4a MS |
352 | /* findmask: |
353 | bit 0 - push { rlist } | |
354 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
355 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
356 | */ | |
357 | int findmask = 0; | |
358 | ||
94c30b78 MS |
359 | for (current_pc = pc; |
360 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 361 | current_pc += 2) |
c906108c SS |
362 | { |
363 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
364 | ||
94c30b78 | 365 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 366 | { |
94c30b78 | 367 | findmask |= 1; /* push found */ |
da59e081 | 368 | } |
da3c6d4a MS |
369 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
370 | sub sp, #simm */ | |
da59e081 | 371 | { |
94c30b78 | 372 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
373 | continue; |
374 | else | |
94c30b78 | 375 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
376 | } |
377 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
378 | { | |
94c30b78 | 379 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
380 | } |
381 | else if (insn == 0x466f) /* mov r7, sp */ | |
382 | { | |
94c30b78 | 383 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 384 | } |
3d74b771 FF |
385 | else if (findmask == (4+2+1)) |
386 | { | |
da3c6d4a MS |
387 | /* We have found one of each type of prologue instruction */ |
388 | break; | |
3d74b771 | 389 | } |
da59e081 | 390 | else |
94c30b78 | 391 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 392 | instruction from outside the prolog scheduled here for |
94c30b78 | 393 | optimization. */ |
da3c6d4a | 394 | continue; |
c906108c SS |
395 | } |
396 | ||
397 | return current_pc; | |
398 | } | |
399 | ||
da3c6d4a MS |
400 | /* Advance the PC across any function entry prologue instructions to |
401 | reach some "real" code. | |
34e8f22d RE |
402 | |
403 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 404 | prologue: |
c906108c | 405 | |
c5aa993b JM |
406 | mov ip, sp |
407 | [stmfd sp!, {a1,a2,a3,a4}] | |
408 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
409 | [stfe f7, [sp, #-12]!] |
410 | [stfe f6, [sp, #-12]!] | |
411 | [stfe f5, [sp, #-12]!] | |
412 | [stfe f4, [sp, #-12]!] | |
413 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 414 | |
34e8f22d | 415 | static CORE_ADDR |
ed9a39eb | 416 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
417 | { |
418 | unsigned long inst; | |
419 | CORE_ADDR skip_pc; | |
b8d5e71d | 420 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 421 | char *func_name; |
c906108c SS |
422 | struct symtab_and_line sal; |
423 | ||
848cfffb AC |
424 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
425 | if (USE_GENERIC_DUMMY_FRAMES | |
426 | && PC_IN_CALL_DUMMY (pc, 0, 0)) | |
427 | return pc; | |
428 | ||
96baa820 | 429 | /* See what the symbol table says. */ |
ed9a39eb | 430 | |
50f6fb4b | 431 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 432 | { |
50f6fb4b CV |
433 | struct symbol *sym; |
434 | ||
435 | /* Found a function. */ | |
436 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
437 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
438 | { | |
94c30b78 | 439 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
440 | sal = find_pc_line (func_addr, 0); |
441 | if ((sal.line != 0) && (sal.end < func_end)) | |
442 | return sal.end; | |
443 | } | |
c906108c SS |
444 | } |
445 | ||
446 | /* Check if this is Thumb code. */ | |
447 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 448 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
449 | |
450 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 451 | by disassembling the instructions. */ |
c906108c | 452 | |
b8d5e71d MS |
453 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
454 | if (func_end == 0 || func_end > pc + 64) | |
455 | func_end = pc + 64; | |
c906108c | 456 | |
b8d5e71d | 457 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 458 | { |
f43845b3 | 459 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 460 | |
b8d5e71d MS |
461 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
462 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
463 | continue; | |
c906108c | 464 | |
b8d5e71d MS |
465 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
466 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
467 | continue; | |
c906108c | 468 | |
b8d5e71d MS |
469 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
470 | continue; | |
c906108c | 471 | |
b8d5e71d MS |
472 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
473 | continue; | |
11d3b27d | 474 | |
b8d5e71d MS |
475 | /* Any insns after this point may float into the code, if it makes |
476 | for better instruction scheduling, so we skip them only if we | |
477 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 478 | |
b8d5e71d MS |
479 | /* We may have either one sfmfd instruction here, or several stfe |
480 | insns, depending on the version of floating point code we | |
481 | support. */ | |
482 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
483 | continue; | |
484 | ||
485 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
486 | continue; | |
487 | ||
488 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
489 | continue; | |
490 | ||
491 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
492 | continue; | |
493 | ||
494 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
495 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
496 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
497 | continue; | |
498 | ||
499 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
500 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
501 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
502 | continue; | |
503 | ||
504 | /* Un-recognized instruction; stop scanning. */ | |
505 | break; | |
f43845b3 | 506 | } |
c906108c | 507 | |
b8d5e71d | 508 | return skip_pc; /* End of prologue */ |
c906108c | 509 | } |
94c30b78 | 510 | |
c5aa993b | 511 | /* *INDENT-OFF* */ |
c906108c SS |
512 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
513 | This function decodes a Thumb function prologue to determine: | |
514 | 1) the size of the stack frame | |
515 | 2) which registers are saved on it | |
516 | 3) the offsets of saved regs | |
517 | 4) the offset from the stack pointer to the frame pointer | |
518 | This information is stored in the "extra" fields of the frame_info. | |
519 | ||
da59e081 JM |
520 | A typical Thumb function prologue would create this stack frame |
521 | (offsets relative to FP) | |
c906108c SS |
522 | old SP -> 24 stack parameters |
523 | 20 LR | |
524 | 16 R7 | |
525 | R7 -> 0 local variables (16 bytes) | |
526 | SP -> -12 additional stack space (12 bytes) | |
527 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
528 | 12 bytes. The frame register is R7. |
529 | ||
da3c6d4a MS |
530 | The comments for thumb_skip_prolog() describe the algorithm we use |
531 | to detect the end of the prolog. */ | |
c5aa993b JM |
532 | /* *INDENT-ON* */ |
533 | ||
c906108c | 534 | static void |
ed9a39eb | 535 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
536 | { |
537 | CORE_ADDR prologue_start; | |
538 | CORE_ADDR prologue_end; | |
539 | CORE_ADDR current_pc; | |
94c30b78 | 540 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
541 | int saved_reg[16]; |
542 | /* findmask: | |
543 | bit 0 - push { rlist } | |
544 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
545 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
546 | */ | |
547 | int findmask = 0; | |
c5aa993b | 548 | int i; |
c906108c | 549 | |
848cfffb AC |
550 | /* Don't try to scan dummy frames. */ |
551 | if (USE_GENERIC_DUMMY_FRAMES | |
552 | && fi != NULL | |
553 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
554 | return; | |
555 | ||
c5aa993b | 556 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
557 | { |
558 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
559 | ||
94c30b78 | 560 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
561 | prologue_end = fi->pc; |
562 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
94c30b78 | 563 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
564 | } |
565 | else | |
da3c6d4a MS |
566 | /* We're in the boondocks: allow for |
567 | 16 pushes, an add, and "mv fp,sp". */ | |
568 | prologue_end = prologue_start + 40; | |
c906108c SS |
569 | |
570 | prologue_end = min (prologue_end, fi->pc); | |
571 | ||
572 | /* Initialize the saved register map. When register H is copied to | |
573 | register L, we will put H in saved_reg[L]. */ | |
574 | for (i = 0; i < 16; i++) | |
575 | saved_reg[i] = i; | |
576 | ||
577 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
578 | frame pointer, adjust the stack pointer, and save registers. |
579 | Do this until all basic prolog instructions are found. */ | |
c906108c | 580 | |
c3b4394c | 581 | fi->extra_info->framesize = 0; |
da59e081 JM |
582 | for (current_pc = prologue_start; |
583 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
584 | current_pc += 2) | |
c906108c SS |
585 | { |
586 | unsigned short insn; | |
587 | int regno; | |
588 | int offset; | |
589 | ||
590 | insn = read_memory_unsigned_integer (current_pc, 2); | |
591 | ||
c5aa993b | 592 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 593 | { |
da59e081 | 594 | int mask; |
94c30b78 | 595 | findmask |= 1; /* push found */ |
c906108c SS |
596 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
597 | whether to save LR (R14). */ | |
da59e081 | 598 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 599 | |
b8d5e71d | 600 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 601 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 602 | if (mask & (1 << regno)) |
c5aa993b | 603 | { |
c3b4394c RE |
604 | fi->extra_info->framesize += 4; |
605 | fi->saved_regs[saved_reg[regno]] = | |
606 | -(fi->extra_info->framesize); | |
da3c6d4a MS |
607 | /* Reset saved register map. */ |
608 | saved_reg[regno] = regno; | |
c906108c SS |
609 | } |
610 | } | |
da3c6d4a MS |
611 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
612 | sub sp, #simm */ | |
c906108c | 613 | { |
b8d5e71d | 614 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
615 | continue; |
616 | else | |
94c30b78 | 617 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 618 | |
94c30b78 MS |
619 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
620 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 621 | { |
c3b4394c | 622 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
623 | offset = -offset; |
624 | } | |
c3b4394c | 625 | fi->extra_info->framesize -= offset; |
c906108c SS |
626 | } |
627 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
628 | { | |
94c30b78 | 629 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
630 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
631 | /* get scaled offset */ | |
632 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 633 | } |
da59e081 | 634 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 635 | { |
94c30b78 | 636 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
637 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
638 | fi->extra_info->frameoffset = 0; | |
34e8f22d | 639 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
640 | } |
641 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
642 | { | |
da3c6d4a | 643 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 644 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 645 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
646 | } |
647 | else | |
da3c6d4a MS |
648 | /* Something in the prolog that we don't care about or some |
649 | instruction from outside the prolog scheduled here for | |
650 | optimization. */ | |
651 | continue; | |
c906108c SS |
652 | } |
653 | } | |
654 | ||
ed9a39eb JM |
655 | /* Check if prologue for this frame's PC has already been scanned. If |
656 | it has, copy the relevant information about that prologue and | |
c906108c SS |
657 | return non-zero. Otherwise do not copy anything and return zero. |
658 | ||
659 | The information saved in the cache includes: | |
c5aa993b JM |
660 | * the frame register number; |
661 | * the size of the stack frame; | |
662 | * the offsets of saved regs (relative to the old SP); and | |
663 | * the offset from the stack pointer to the frame pointer | |
c906108c | 664 | |
ed9a39eb JM |
665 | The cache contains only one entry, since this is adequate for the |
666 | typical sequence of prologue scan requests we get. When performing | |
667 | a backtrace, GDB will usually ask to scan the same function twice | |
668 | in a row (once to get the frame chain, and once to fill in the | |
669 | extra frame information). */ | |
c906108c SS |
670 | |
671 | static struct frame_info prologue_cache; | |
672 | ||
673 | static int | |
ed9a39eb | 674 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
675 | { |
676 | int i; | |
677 | ||
678 | if (fi->pc == prologue_cache.pc) | |
679 | { | |
c3b4394c RE |
680 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
681 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
682 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
683 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
684 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
685 | return 1; |
686 | } | |
687 | else | |
688 | return 0; | |
689 | } | |
690 | ||
691 | ||
ed9a39eb | 692 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
693 | |
694 | static void | |
ed9a39eb | 695 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
696 | { |
697 | int i; | |
698 | ||
c5aa993b | 699 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
700 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
701 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
702 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 703 | |
c3b4394c RE |
704 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
705 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
706 | } |
707 | ||
708 | ||
ed9a39eb | 709 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
710 | 1) the size of the stack frame |
711 | 2) which registers are saved on it | |
712 | 3) the offsets of saved regs | |
713 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
714 | This information is stored in the "extra" fields of the frame_info. |
715 | ||
96baa820 JM |
716 | There are two basic forms for the ARM prologue. The fixed argument |
717 | function call will look like: | |
ed9a39eb JM |
718 | |
719 | mov ip, sp | |
720 | stmfd sp!, {fp, ip, lr, pc} | |
721 | sub fp, ip, #4 | |
722 | [sub sp, sp, #4] | |
96baa820 | 723 | |
c906108c | 724 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
725 | IP -> 4 (caller's stack) |
726 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
727 | -4 LR (return address in caller) | |
728 | -8 IP (copy of caller's SP) | |
729 | -12 FP (caller's FP) | |
730 | SP -> -28 Local variables | |
731 | ||
c906108c | 732 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
733 | 28 bytes. The stmfd call can also save any of the vN registers it |
734 | plans to use, which increases the frame size accordingly. | |
735 | ||
736 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
737 | because the ARM Store instructions always store PC + 8 when you read | |
738 | the PC register. | |
ed9a39eb | 739 | |
96baa820 JM |
740 | A variable argument function call will look like: |
741 | ||
ed9a39eb JM |
742 | mov ip, sp |
743 | stmfd sp!, {a1, a2, a3, a4} | |
744 | stmfd sp!, {fp, ip, lr, pc} | |
745 | sub fp, ip, #20 | |
746 | ||
96baa820 | 747 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
748 | IP -> 20 (caller's stack) |
749 | 16 A4 | |
750 | 12 A3 | |
751 | 8 A2 | |
752 | 4 A1 | |
753 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
754 | -4 LR (return address in caller) | |
755 | -8 IP (copy of caller's SP) | |
756 | -12 FP (caller's FP) | |
757 | SP -> -28 Local variables | |
96baa820 JM |
758 | |
759 | The frame size would thus be 48 bytes, and the frame offset would be | |
760 | 28 bytes. | |
761 | ||
762 | There is another potential complication, which is that the optimizer | |
763 | will try to separate the store of fp in the "stmfd" instruction from | |
764 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
765 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
766 | ||
767 | Also, note, the original version of the ARM toolchain claimed that there | |
768 | should be an | |
769 | ||
770 | instruction at the end of the prologue. I have never seen GCC produce | |
771 | this, and the ARM docs don't mention it. We still test for it below in | |
772 | case it happens... | |
ed9a39eb JM |
773 | |
774 | */ | |
c906108c SS |
775 | |
776 | static void | |
ed9a39eb | 777 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
778 | { |
779 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 780 | LONGEST return_value; |
c906108c SS |
781 | CORE_ADDR prologue_start, prologue_end, current_pc; |
782 | ||
94c30b78 | 783 | /* Check if this function is already in the cache of frame information. */ |
c906108c SS |
784 | if (check_prologue_cache (fi)) |
785 | return; | |
786 | ||
787 | /* Assume there is no frame until proven otherwise. */ | |
34e8f22d | 788 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
789 | fi->extra_info->framesize = 0; |
790 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
791 | |
792 | /* Check for Thumb prologue. */ | |
793 | if (arm_pc_is_thumb (fi->pc)) | |
794 | { | |
795 | thumb_scan_prologue (fi); | |
796 | save_prologue_cache (fi); | |
797 | return; | |
798 | } | |
799 | ||
800 | /* Find the function prologue. If we can't find the function in | |
801 | the symbol table, peek in the stack frame to find the PC. */ | |
802 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
803 | { | |
2a451106 KB |
804 | /* One way to find the end of the prologue (which works well |
805 | for unoptimized code) is to do the following: | |
806 | ||
807 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
808 | ||
809 | if (sal.line == 0) | |
810 | prologue_end = fi->pc; | |
811 | else if (sal.end < prologue_end) | |
812 | prologue_end = sal.end; | |
813 | ||
814 | This mechanism is very accurate so long as the optimizer | |
815 | doesn't move any instructions from the function body into the | |
816 | prologue. If this happens, sal.end will be the last | |
817 | instruction in the first hunk of prologue code just before | |
818 | the first instruction that the scheduler has moved from | |
819 | the body to the prologue. | |
820 | ||
821 | In order to make sure that we scan all of the prologue | |
822 | instructions, we use a slightly less accurate mechanism which | |
823 | may scan more than necessary. To help compensate for this | |
824 | lack of accuracy, the prologue scanning loop below contains | |
825 | several clauses which'll cause the loop to terminate early if | |
826 | an implausible prologue instruction is encountered. | |
827 | ||
828 | The expression | |
829 | ||
830 | prologue_start + 64 | |
831 | ||
832 | is a suitable endpoint since it accounts for the largest | |
833 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 834 | the scheduler. */ |
2a451106 KB |
835 | |
836 | if (prologue_end > prologue_start + 64) | |
837 | { | |
94c30b78 | 838 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 839 | } |
c906108c SS |
840 | } |
841 | else | |
842 | { | |
94c30b78 MS |
843 | /* Get address of the stmfd in the prologue of the callee; |
844 | the saved PC is the address of the stmfd + 8. */ | |
16a0f3e7 EZ |
845 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
846 | return; | |
847 | else | |
848 | { | |
849 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 850 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 851 | } |
c906108c SS |
852 | } |
853 | ||
854 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 855 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 856 | |
96baa820 JM |
857 | Be careful, however, and if it doesn't look like a prologue, |
858 | don't try to scan it. If, for instance, a frameless function | |
859 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 860 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
861 | and other operations that rely on a knowledge of the stack |
862 | traceback. | |
863 | ||
864 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 865 | if we don't see this as the first insn, we will stop. |
c906108c | 866 | |
f43845b3 MS |
867 | [Note: This doesn't seem to be true any longer, so it's now an |
868 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 869 | |
f43845b3 MS |
870 | [Note further: The "mov ip,sp" only seems to be missing in |
871 | frameless functions at optimization level "-O2" or above, | |
872 | in which case it is often (but not always) replaced by | |
b8d5e71d | 873 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 874 | |
f43845b3 MS |
875 | sp_offset = fp_offset = 0; |
876 | ||
94c30b78 MS |
877 | for (current_pc = prologue_start; |
878 | current_pc < prologue_end; | |
f43845b3 | 879 | current_pc += 4) |
96baa820 | 880 | { |
d4473757 KB |
881 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
882 | ||
94c30b78 | 883 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
884 | { |
885 | continue; | |
886 | } | |
94c30b78 | 887 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
888 | { |
889 | /* Function is frameless: extra_info defaults OK? */ | |
890 | continue; | |
891 | } | |
892 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
893 | /* stmfd sp!, {..., fp, ip, lr, pc} |
894 | or | |
895 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 896 | { |
d4473757 | 897 | int mask = insn & 0xffff; |
ed9a39eb | 898 | |
94c30b78 | 899 | /* Calculate offsets of saved registers. */ |
34e8f22d | 900 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
901 | if (mask & (1 << regno)) |
902 | { | |
903 | sp_offset -= 4; | |
c3b4394c | 904 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
905 | } |
906 | } | |
b8d5e71d MS |
907 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
908 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
909 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
910 | { | |
911 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
912 | continue; | |
913 | } | |
914 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
915 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
916 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
917 | { |
918 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
919 | continue; | |
920 | } | |
d4473757 KB |
921 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
922 | { | |
94c30b78 MS |
923 | unsigned imm = insn & 0xff; /* immediate value */ |
924 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
925 | imm = (imm >> rot) | (imm << (32 - rot)); |
926 | fp_offset = -imm; | |
34e8f22d | 927 | fi->extra_info->framereg = ARM_FP_REGNUM; |
d4473757 KB |
928 | } |
929 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
930 | { | |
94c30b78 MS |
931 | unsigned imm = insn & 0xff; /* immediate value */ |
932 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
933 | imm = (imm >> rot) | (imm << (32 - rot)); |
934 | sp_offset -= imm; | |
935 | } | |
936 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
937 | { | |
938 | sp_offset -= 12; | |
34e8f22d | 939 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
c3b4394c | 940 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
941 | } |
942 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
943 | { | |
944 | int n_saved_fp_regs; | |
945 | unsigned int fp_start_reg, fp_bound_reg; | |
946 | ||
94c30b78 | 947 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 948 | { |
d4473757 KB |
949 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
950 | n_saved_fp_regs = 3; | |
951 | else | |
952 | n_saved_fp_regs = 1; | |
96baa820 | 953 | } |
d4473757 | 954 | else |
96baa820 | 955 | { |
d4473757 KB |
956 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
957 | n_saved_fp_regs = 2; | |
958 | else | |
959 | n_saved_fp_regs = 4; | |
96baa820 | 960 | } |
d4473757 | 961 | |
34e8f22d | 962 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
963 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
964 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
965 | { |
966 | sp_offset -= 12; | |
c3b4394c | 967 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 968 | } |
c906108c | 969 | } |
d4473757 | 970 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 971 | break; /* Condition not true, exit early */ |
b8d5e71d | 972 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 973 | break; /* Don't scan past a block load */ |
d4473757 KB |
974 | else |
975 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 976 | so we just skip what we don't recognize. */ |
d4473757 | 977 | continue; |
c906108c SS |
978 | } |
979 | ||
94c30b78 MS |
980 | /* The frame size is just the negative of the offset (from the |
981 | original SP) of the last thing thing we pushed on the stack. | |
982 | The frame offset is [new FP] - [new SP]. */ | |
c3b4394c | 983 | fi->extra_info->framesize = -sp_offset; |
34e8f22d | 984 | if (fi->extra_info->framereg == ARM_FP_REGNUM) |
c3b4394c | 985 | fi->extra_info->frameoffset = fp_offset - sp_offset; |
d4473757 | 986 | else |
c3b4394c | 987 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 988 | |
c906108c SS |
989 | save_prologue_cache (fi); |
990 | } | |
991 | ||
ed9a39eb JM |
992 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
993 | One thing we might want to do here is to check REGNUM against the | |
994 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
995 | the stack somewhere. This would provide a graceful failure mode | |
996 | when trying to get the value of caller-saves registers for an inner | |
997 | frame. */ | |
c906108c SS |
998 | |
999 | static CORE_ADDR | |
ed9a39eb | 1000 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 1001 | { |
848cfffb AC |
1002 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
1003 | needed. Instead the (still being written) register unwind | |
1004 | function could be called directly. */ | |
c906108c | 1005 | for (; fi; fi = fi->next) |
848cfffb AC |
1006 | { |
1007 | if (USE_GENERIC_DUMMY_FRAMES | |
1008 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
1009 | { | |
1010 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
1011 | } | |
1012 | else if (fi->saved_regs[regnum] != 0) | |
1013 | { | |
1014 | /* NOTE: cagney/2002-05-03: This would normally need to | |
1015 | handle ARM_SP_REGNUM as a special case as, according to | |
1016 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
1017 | SP value not its address. It appears that the ARM isn't | |
1018 | doing this though. */ | |
1019 | return read_memory_integer (fi->saved_regs[regnum], | |
1020 | REGISTER_RAW_SIZE (regnum)); | |
1021 | } | |
1022 | } | |
c906108c SS |
1023 | return read_register (regnum); |
1024 | } | |
148754e5 RE |
1025 | /* Function: frame_chain Given a GDB frame, determine the address of |
1026 | the calling function's frame. This will be used to create a new | |
1027 | GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC | |
1028 | will be called for the new frame. For ARM, we save the frame size | |
1029 | when we initialize the frame_info. */ | |
c5aa993b | 1030 | |
148754e5 | 1031 | static CORE_ADDR |
ed9a39eb | 1032 | arm_frame_chain (struct frame_info *fi) |
c906108c | 1033 | { |
848cfffb | 1034 | CORE_ADDR caller_pc; |
c3b4394c | 1035 | int framereg = fi->extra_info->framereg; |
c906108c | 1036 | |
848cfffb AC |
1037 | if (USE_GENERIC_DUMMY_FRAMES |
1038 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
1039 | /* A generic call dummy's frame is the same as caller's. */ | |
1040 | return fi->frame; | |
1041 | ||
c906108c SS |
1042 | if (fi->pc < LOWEST_PC) |
1043 | return 0; | |
1044 | ||
1045 | /* If the caller is the startup code, we're at the end of the chain. */ | |
1046 | caller_pc = FRAME_SAVED_PC (fi); | |
c906108c SS |
1047 | |
1048 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1049 | the frame register of the caller is different from ours. | |
1050 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 1051 | frame register number. */ |
c3b4394c RE |
1052 | /* XXX Fixme, we should try to do this without creating a temporary |
1053 | caller_fi. */ | |
c906108c SS |
1054 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1055 | { | |
c3b4394c RE |
1056 | struct frame_info caller_fi; |
1057 | struct cleanup *old_chain; | |
1058 | ||
1059 | /* Create a temporary frame suitable for scanning the caller's | |
1060 | prologue. (Ugh.) */ | |
c5aa993b | 1061 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1062 | caller_fi.extra_info = (struct frame_extra_info *) |
1063 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1064 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1065 | caller_fi.saved_regs = (CORE_ADDR *) | |
1066 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1067 | make_cleanup (xfree, caller_fi.saved_regs); | |
1068 | ||
1069 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1070 | caller_fi.pc = caller_pc; |
c5aa993b | 1071 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1072 | framereg = caller_fi.extra_info->framereg; |
1073 | ||
1074 | /* Deallocate the storage associated with the temporary frame | |
1075 | created above. */ | |
1076 | do_cleanups (old_chain); | |
c906108c SS |
1077 | } |
1078 | ||
1079 | /* If the caller used a frame register, return its value. | |
1080 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1081 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1082 | return arm_find_callers_reg (fi, framereg); |
1083 | else | |
c3b4394c | 1084 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1085 | } |
1086 | ||
ed9a39eb JM |
1087 | /* This function actually figures out the frame address for a given pc |
1088 | and sp. This is tricky because we sometimes don't use an explicit | |
1089 | frame pointer, and the previous stack pointer isn't necessarily | |
1090 | recorded on the stack. The only reliable way to get this info is | |
1091 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1092 | this is the next frame up the chain AFTER a frameless function. If | |
1093 | this is true, then the frame value for this frame is still in the | |
1094 | fp register. */ | |
c906108c | 1095 | |
148754e5 | 1096 | static void |
ed9a39eb | 1097 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1098 | { |
1099 | int reg; | |
f079148d | 1100 | CORE_ADDR sp; |
c906108c | 1101 | |
c3b4394c RE |
1102 | if (fi->saved_regs == NULL) |
1103 | frame_saved_regs_zalloc (fi); | |
1104 | ||
1105 | fi->extra_info = (struct frame_extra_info *) | |
1106 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1107 | ||
1108 | fi->extra_info->framesize = 0; | |
1109 | fi->extra_info->frameoffset = 0; | |
1110 | fi->extra_info->framereg = 0; | |
1111 | ||
c906108c SS |
1112 | if (fi->next) |
1113 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1114 | ||
c3b4394c | 1115 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1116 | |
da3c6d4a MS |
1117 | /* Compute stack pointer for this frame. We use this value for both |
1118 | the sigtramp and call dummy cases. */ | |
f079148d KB |
1119 | if (!fi->next) |
1120 | sp = read_sp(); | |
848cfffb AC |
1121 | else if (USE_GENERIC_DUMMY_FRAMES |
1122 | && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) | |
1123 | /* For generic dummy frames, pull the value direct from the frame. | |
1124 | Having an unwind function to do this would be nice. */ | |
1125 | sp = generic_read_register_dummy (fi->next->pc, fi->next->frame, | |
1126 | ARM_SP_REGNUM); | |
f079148d | 1127 | else |
c3b4394c RE |
1128 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1129 | + fi->next->extra_info->framesize); | |
f079148d | 1130 | |
d7bd68ca | 1131 | /* Determine whether or not we're in a sigtramp frame. |
2a451106 KB |
1132 | Unfortunately, it isn't sufficient to test |
1133 | fi->signal_handler_caller because this value is sometimes set | |
1134 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
d7bd68ca AC |
1135 | fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we |
1136 | need to use the sigcontext addresses for the saved registers. | |
2a451106 | 1137 | |
d7bd68ca AC |
1138 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1139 | against the name of the function, the code below will have to be | |
1140 | changed to first fetch the name of the function and then pass | |
1141 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1142 | |
3bb04bdd | 1143 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
d7bd68ca | 1144 | && (fi->signal_handler_caller || PC_IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1145 | { |
2a451106 | 1146 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1147 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 | 1148 | |
94c30b78 | 1149 | /* FIXME: What about thumb mode? */ |
34e8f22d | 1150 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
1151 | fi->frame = |
1152 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1153 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1154 | fi->extra_info->framesize = 0; | |
1155 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1156 | |
1157 | } | |
f079148d KB |
1158 | else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame)) |
1159 | { | |
1160 | CORE_ADDR rp; | |
1161 | CORE_ADDR callers_sp; | |
1162 | ||
1163 | /* Set rp point at the high end of the saved registers. */ | |
1164 | rp = fi->frame - REGISTER_SIZE; | |
1165 | ||
1166 | /* Fill in addresses of saved registers. */ | |
34e8f22d RE |
1167 | fi->saved_regs[ARM_PS_REGNUM] = rp; |
1168 | rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM); | |
1169 | for (reg = ARM_PC_REGNUM; reg >= 0; reg--) | |
f079148d | 1170 | { |
c3b4394c | 1171 | fi->saved_regs[reg] = rp; |
f079148d KB |
1172 | rp -= REGISTER_RAW_SIZE (reg); |
1173 | } | |
1174 | ||
34e8f22d RE |
1175 | callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM], |
1176 | REGISTER_RAW_SIZE (ARM_SP_REGNUM)); | |
1177 | fi->extra_info->framereg = ARM_FP_REGNUM; | |
c3b4394c RE |
1178 | fi->extra_info->framesize = callers_sp - sp; |
1179 | fi->extra_info->frameoffset = fi->frame - sp; | |
f079148d | 1180 | } |
2a451106 | 1181 | else |
c906108c SS |
1182 | { |
1183 | arm_scan_prologue (fi); | |
1184 | ||
104c1213 | 1185 | if (!fi->next) |
94c30b78 | 1186 | /* This is the innermost frame? */ |
c3b4394c | 1187 | fi->frame = read_register (fi->extra_info->framereg); |
848cfffb AC |
1188 | else if (USE_GENERIC_DUMMY_FRAMES |
1189 | && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) | |
1190 | /* Next inner most frame is a dummy, just grab its frame. | |
1191 | Dummy frames always have the same FP as their caller. */ | |
1192 | fi->frame = fi->next->frame; | |
34e8f22d | 1193 | else if (fi->extra_info->framereg == ARM_FP_REGNUM |
c3b4394c | 1194 | || fi->extra_info->framereg == THUMB_FP_REGNUM) |
ed9a39eb JM |
1195 | { |
1196 | /* not the innermost frame */ | |
94c30b78 | 1197 | /* If we have an FP, the callee saved it. */ |
c3b4394c | 1198 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1199 | fi->frame = |
c3b4394c RE |
1200 | read_memory_integer (fi->next |
1201 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1202 | else if (fromleaf) |
1203 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1204 | still in the frame pointer register on the board... */ |
ed9a39eb JM |
1205 | fi->frame = read_fp (); |
1206 | } | |
c906108c | 1207 | |
ed9a39eb JM |
1208 | /* Calculate actual addresses of saved registers using offsets |
1209 | determined by arm_scan_prologue. */ | |
c906108c | 1210 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1211 | if (fi->saved_regs[reg] != 0) |
1212 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1213 | - fi->extra_info->frameoffset); | |
c906108c SS |
1214 | } |
1215 | } | |
1216 | ||
1217 | ||
34e8f22d | 1218 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1219 | is saved in the stack anywhere, otherwise we get it from the |
1220 | registers. | |
c906108c SS |
1221 | |
1222 | The old definition of this function was a macro: | |
c5aa993b | 1223 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1224 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1225 | |
148754e5 | 1226 | static CORE_ADDR |
ed9a39eb | 1227 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1228 | { |
848cfffb AC |
1229 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
1230 | if (USE_GENERIC_DUMMY_FRAMES | |
1231 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
34e8f22d | 1232 | return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM); |
848cfffb | 1233 | |
c3b4394c RE |
1234 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
1235 | fi->frame)) | |
f079148d | 1236 | { |
34e8f22d RE |
1237 | return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM], |
1238 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); | |
f079148d KB |
1239 | } |
1240 | else | |
c906108c | 1241 | { |
34e8f22d | 1242 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1243 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1244 | } | |
1245 | } | |
1246 | ||
c906108c SS |
1247 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1248 | Examine the Program Status Register to decide which state we're in. */ | |
1249 | ||
148754e5 RE |
1250 | static CORE_ADDR |
1251 | arm_read_fp (void) | |
c906108c | 1252 | { |
34e8f22d | 1253 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1254 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1255 | else | |
34e8f22d | 1256 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1257 | } |
1258 | ||
148754e5 RE |
1259 | /* Store into a struct frame_saved_regs the addresses of the saved |
1260 | registers of frame described by FRAME_INFO. This includes special | |
1261 | registers such as PC and FP saved in special ways in the stack | |
1262 | frame. SP is even more special: the address we return for it IS | |
1263 | the sp for the next frame. */ | |
c906108c | 1264 | |
148754e5 | 1265 | static void |
c3b4394c | 1266 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1267 | { |
c3b4394c RE |
1268 | |
1269 | if (fip->saved_regs) | |
1270 | return; | |
1271 | ||
1272 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1273 | } |
1274 | ||
848cfffb AC |
1275 | /* Set the return address for a generic dummy frame. ARM uses the |
1276 | entry point. */ | |
1277 | ||
1278 | static CORE_ADDR | |
1279 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1280 | { | |
1281 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1282 | return sp; | |
1283 | } | |
1284 | ||
148754e5 RE |
1285 | /* Push an empty stack frame, to record the current PC, etc. */ |
1286 | ||
1287 | static void | |
ed9a39eb | 1288 | arm_push_dummy_frame (void) |
c906108c | 1289 | { |
34e8f22d | 1290 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1291 | CORE_ADDR sp = old_sp; |
1292 | CORE_ADDR fp, prologue_start; | |
1293 | int regnum; | |
1294 | ||
1295 | /* Push the two dummy prologue instructions in reverse order, | |
1296 | so that they'll be in the correct low-to-high order in memory. */ | |
1297 | /* sub fp, ip, #4 */ | |
1298 | sp = push_word (sp, 0xe24cb004); | |
1299 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1300 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1301 | ||
ed9a39eb JM |
1302 | /* Push a pointer to the dummy prologue + 12, because when stm |
1303 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1304 | instruction itself plus 12. */ |
1305 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1306 | |
f079148d | 1307 | /* Push the processor status. */ |
34e8f22d | 1308 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1309 | |
1310 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1311 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1312 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1313 | |
f079148d | 1314 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1315 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1316 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1317 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1318 | } |
1319 | ||
6eb69eab RE |
1320 | /* CALL_DUMMY_WORDS: |
1321 | This sequence of words is the instructions | |
1322 | ||
1323 | mov lr,pc | |
1324 | mov pc,r4 | |
1325 | illegal | |
1326 | ||
1327 | Note this is 12 bytes. */ | |
1328 | ||
34e8f22d | 1329 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1330 | { |
1331 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1332 | }; | |
1333 | ||
3fb4b924 RE |
1334 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1335 | breakpoint to the proper address in the call dummy, so that | |
1336 | `finish' after a stop in a call dummy works. | |
1337 | ||
d7b486e7 RE |
1338 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1339 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1340 | followed by a call to run_stack_dummy, which is the only function | |
1341 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1342 | |
1343 | ||
1344 | static void | |
1345 | arm_set_call_dummy_breakpoint_offset (void) | |
1346 | { | |
1347 | if (caller_is_thumb) | |
1348 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1349 | else | |
1350 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1351 | } | |
1352 | ||
c906108c | 1353 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1354 | in Thumb or ARM mode, and whether the target function is Thumb or |
1355 | ARM. There are three different situations requiring three | |
c906108c SS |
1356 | different dummies: |
1357 | ||
1358 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1359 | been copied into the dummy parameter to this function. |
c906108c | 1360 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1361 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1362 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1363 | works for calling both ARM and Thumb functions. |
c906108c | 1364 | |
ed9a39eb JM |
1365 | All three call dummies expect to receive the target function |
1366 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1367 | |
34e8f22d | 1368 | static void |
ed9a39eb | 1369 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1370 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1371 | { |
1372 | static short thumb_dummy[4] = | |
1373 | { | |
c5aa993b JM |
1374 | 0xf000, 0xf801, /* bl label */ |
1375 | 0xdf18, /* swi 24 */ | |
1376 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1377 | }; |
1378 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1379 | ||
94c30b78 | 1380 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1381 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1382 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1383 | |
ed9a39eb JM |
1384 | /* If the target function is Thumb, set the low bit of the function |
1385 | address. And if the CPU is currently in ARM mode, patch the | |
1386 | second instruction of call dummy to use a BX instruction to | |
1387 | switch to Thumb mode. */ | |
c906108c SS |
1388 | target_is_thumb = arm_pc_is_thumb (fun); |
1389 | if (target_is_thumb) | |
1390 | { | |
1391 | fun |= 1; | |
1392 | if (!caller_is_thumb) | |
1393 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1394 | } | |
1395 | ||
1396 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1397 | instead of the ARM one that's already been copied. This will | |
1398 | work for both Thumb and ARM target functions. */ | |
1399 | if (caller_is_thumb) | |
1400 | { | |
1401 | int i; | |
1402 | char *p = dummy; | |
1403 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1404 | ||
1405 | for (i = 0; i < len; i++) | |
1406 | { | |
1407 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1408 | p += sizeof (thumb_dummy[0]); | |
1409 | } | |
1410 | } | |
1411 | ||
ed9a39eb | 1412 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1413 | the PC. */ |
c906108c SS |
1414 | write_register (4, fun); |
1415 | } | |
1416 | ||
ed9a39eb JM |
1417 | /* Note: ScottB |
1418 | ||
1419 | This function does not support passing parameters using the FPA | |
1420 | variant of the APCS. It passes any floating point arguments in the | |
1421 | general registers and/or on the stack. */ | |
c906108c | 1422 | |
39bbf761 | 1423 | static CORE_ADDR |
ea7c478f | 1424 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1425 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1426 | { |
ed9a39eb JM |
1427 | char *fp; |
1428 | int argnum, argreg, nstack_size; | |
1429 | ||
1430 | /* Walk through the list of args and determine how large a temporary | |
1431 | stack is required. Need to take care here as structs may be | |
1432 | passed on the stack, and we have to to push them. */ | |
1433 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
94c30b78 | 1434 | if (struct_return) /* The struct address goes in A1. */ |
ed9a39eb JM |
1435 | nstack_size += REGISTER_SIZE; |
1436 | ||
1437 | /* Walk through the arguments and add their size to nstack_size. */ | |
1438 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1439 | { |
c906108c | 1440 | int len; |
ed9a39eb JM |
1441 | struct type *arg_type; |
1442 | ||
1443 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1444 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1445 | |
6b230f1b | 1446 | nstack_size += len; |
ed9a39eb | 1447 | } |
c906108c | 1448 | |
ed9a39eb JM |
1449 | /* Allocate room on the stack, and initialize our stack frame |
1450 | pointer. */ | |
1451 | fp = NULL; | |
1452 | if (nstack_size > 0) | |
1453 | { | |
1454 | sp -= nstack_size; | |
1455 | fp = (char *) sp; | |
1456 | } | |
1457 | ||
1458 | /* Initialize the integer argument register pointer. */ | |
34e8f22d | 1459 | argreg = ARM_A1_REGNUM; |
c906108c | 1460 | |
ed9a39eb JM |
1461 | /* The struct_return pointer occupies the first parameter passing |
1462 | register. */ | |
c906108c | 1463 | if (struct_return) |
c5aa993b | 1464 | write_register (argreg++, struct_addr); |
c906108c | 1465 | |
ed9a39eb JM |
1466 | /* Process arguments from left to right. Store as many as allowed |
1467 | in the parameter passing registers (A1-A4), and save the rest on | |
1468 | the temporary stack. */ | |
c5aa993b | 1469 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1470 | { |
ed9a39eb | 1471 | int len; |
c5aa993b | 1472 | char *val; |
c5aa993b | 1473 | CORE_ADDR regval; |
ed9a39eb JM |
1474 | enum type_code typecode; |
1475 | struct type *arg_type, *target_type; | |
1476 | ||
1477 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1478 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1479 | len = TYPE_LENGTH (arg_type); | |
1480 | typecode = TYPE_CODE (arg_type); | |
1481 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1482 | ||
da59e081 JM |
1483 | #if 1 |
1484 | /* I don't know why this code was disable. The only logical use | |
1485 | for a function pointer is to call that function, so setting | |
94c30b78 | 1486 | the mode bit is perfectly fine. FN */ |
ed9a39eb | 1487 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1488 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1489 | if (TYPE_CODE_PTR == typecode |
1490 | && NULL != target_type | |
1491 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1492 | { |
ed9a39eb | 1493 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1494 | if (arm_pc_is_thumb (regval)) |
1495 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1496 | } | |
c906108c | 1497 | #endif |
ed9a39eb JM |
1498 | /* Copy the argument to general registers or the stack in |
1499 | register-sized pieces. Large arguments are split between | |
1500 | registers and stack. */ | |
1501 | while (len > 0) | |
c906108c | 1502 | { |
ed9a39eb JM |
1503 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1504 | ||
1505 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1506 | { |
ed9a39eb JM |
1507 | /* It's an argument being passed in a general register. */ |
1508 | regval = extract_address (val, partial_len); | |
1509 | write_register (argreg++, regval); | |
c906108c | 1510 | } |
ed9a39eb JM |
1511 | else |
1512 | { | |
1513 | /* Push the arguments onto the stack. */ | |
1514 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1515 | fp += REGISTER_SIZE; | |
1516 | } | |
1517 | ||
1518 | len -= partial_len; | |
1519 | val += partial_len; | |
c906108c SS |
1520 | } |
1521 | } | |
c906108c SS |
1522 | |
1523 | /* Return adjusted stack pointer. */ | |
1524 | return sp; | |
1525 | } | |
1526 | ||
da3c6d4a MS |
1527 | /* Pop the current frame. So long as the frame info has been |
1528 | initialized properly (see arm_init_extra_frame_info), this code | |
1529 | works for dummy frames as well as regular frames. I.e, there's no | |
1530 | need to have a special case for dummy frames. */ | |
148754e5 | 1531 | static void |
ed9a39eb | 1532 | arm_pop_frame (void) |
c906108c | 1533 | { |
c906108c | 1534 | int regnum; |
8b93c638 | 1535 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1536 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1537 | + frame->extra_info->framesize); | |
c906108c | 1538 | |
848cfffb AC |
1539 | if (USE_GENERIC_DUMMY_FRAMES |
1540 | && PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
1541 | { | |
1542 | generic_pop_dummy_frame (); | |
1543 | flush_cached_frames (); | |
1544 | return; | |
1545 | } | |
1546 | ||
f079148d | 1547 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1548 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1549 | write_register (regnum, |
c3b4394c | 1550 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1551 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1552 | |
34e8f22d RE |
1553 | write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame)); |
1554 | write_register (ARM_SP_REGNUM, old_SP); | |
c906108c SS |
1555 | |
1556 | flush_cached_frames (); | |
1557 | } | |
1558 | ||
1559 | static void | |
ed9a39eb | 1560 | print_fpu_flags (int flags) |
c906108c | 1561 | { |
c5aa993b JM |
1562 | if (flags & (1 << 0)) |
1563 | fputs ("IVO ", stdout); | |
1564 | if (flags & (1 << 1)) | |
1565 | fputs ("DVZ ", stdout); | |
1566 | if (flags & (1 << 2)) | |
1567 | fputs ("OFL ", stdout); | |
1568 | if (flags & (1 << 3)) | |
1569 | fputs ("UFL ", stdout); | |
1570 | if (flags & (1 << 4)) | |
1571 | fputs ("INX ", stdout); | |
1572 | putchar ('\n'); | |
c906108c SS |
1573 | } |
1574 | ||
5e74b15c RE |
1575 | /* Print interesting information about the floating point processor |
1576 | (if present) or emulator. */ | |
34e8f22d | 1577 | static void |
5e74b15c | 1578 | arm_print_float_info (void) |
c906108c | 1579 | { |
34e8f22d | 1580 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1581 | int type; |
1582 | ||
1583 | type = (status >> 24) & 127; | |
1584 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1585 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1586 | type); |
1587 | fputs ("mask: ", stdout); | |
1588 | print_fpu_flags (status >> 16); | |
1589 | fputs ("flags: ", stdout); | |
1590 | print_fpu_flags (status); | |
c906108c SS |
1591 | } |
1592 | ||
34e8f22d RE |
1593 | /* Return the GDB type object for the "standard" data type of data in |
1594 | register N. */ | |
1595 | ||
1596 | static struct type * | |
032758dc AC |
1597 | arm_register_type (int regnum) |
1598 | { | |
34e8f22d | 1599 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1600 | { |
d7449b42 | 1601 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1602 | return builtin_type_arm_ext_big; |
1603 | else | |
1604 | return builtin_type_arm_ext_littlebyte_bigword; | |
1605 | } | |
1606 | else | |
1607 | return builtin_type_int32; | |
1608 | } | |
1609 | ||
34e8f22d RE |
1610 | /* Index within `registers' of the first byte of the space for |
1611 | register N. */ | |
1612 | ||
1613 | static int | |
1614 | arm_register_byte (int regnum) | |
1615 | { | |
1616 | if (regnum < ARM_F0_REGNUM) | |
1617 | return regnum * INT_REGISTER_RAW_SIZE; | |
1618 | else if (regnum < ARM_PS_REGNUM) | |
1619 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1620 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1621 | else | |
1622 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1623 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1624 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1625 | } | |
1626 | ||
1627 | /* Number of bytes of storage in the actual machine representation for | |
1628 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1629 | 12 bytes in length. */ | |
1630 | ||
1631 | static int | |
1632 | arm_register_raw_size (int regnum) | |
1633 | { | |
1634 | if (regnum < ARM_F0_REGNUM) | |
1635 | return INT_REGISTER_RAW_SIZE; | |
1636 | else if (regnum < ARM_FPS_REGNUM) | |
1637 | return FP_REGISTER_RAW_SIZE; | |
1638 | else | |
1639 | return STATUS_REGISTER_SIZE; | |
1640 | } | |
1641 | ||
1642 | /* Number of bytes of storage in a program's representation | |
1643 | for register N. */ | |
1644 | static int | |
1645 | arm_register_virtual_size (int regnum) | |
1646 | { | |
1647 | if (regnum < ARM_F0_REGNUM) | |
1648 | return INT_REGISTER_VIRTUAL_SIZE; | |
1649 | else if (regnum < ARM_FPS_REGNUM) | |
1650 | return FP_REGISTER_VIRTUAL_SIZE; | |
1651 | else | |
1652 | return STATUS_REGISTER_SIZE; | |
1653 | } | |
1654 | ||
1655 | ||
a37b3cc0 AC |
1656 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1657 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1658 | It is thought that this is is the floating-point register format on | |
1659 | little-endian systems. */ | |
c906108c | 1660 | |
ed9a39eb JM |
1661 | static void |
1662 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1663 | { |
a37b3cc0 | 1664 | DOUBLEST d; |
d7449b42 | 1665 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1666 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1667 | else | |
1668 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1669 | ptr, &d); | |
1670 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1671 | } |
1672 | ||
34e8f22d | 1673 | static void |
ed9a39eb | 1674 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1675 | { |
a37b3cc0 AC |
1676 | DOUBLEST d; |
1677 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1678 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1679 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1680 | else | |
1681 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1682 | &d, dbl); | |
c906108c | 1683 | } |
ed9a39eb | 1684 | |
c906108c | 1685 | static int |
ed9a39eb | 1686 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1687 | { |
1688 | if (cond == INST_AL || cond == INST_NV) | |
1689 | return 1; | |
1690 | ||
1691 | switch (cond) | |
1692 | { | |
1693 | case INST_EQ: | |
1694 | return ((status_reg & FLAG_Z) != 0); | |
1695 | case INST_NE: | |
1696 | return ((status_reg & FLAG_Z) == 0); | |
1697 | case INST_CS: | |
1698 | return ((status_reg & FLAG_C) != 0); | |
1699 | case INST_CC: | |
1700 | return ((status_reg & FLAG_C) == 0); | |
1701 | case INST_MI: | |
1702 | return ((status_reg & FLAG_N) != 0); | |
1703 | case INST_PL: | |
1704 | return ((status_reg & FLAG_N) == 0); | |
1705 | case INST_VS: | |
1706 | return ((status_reg & FLAG_V) != 0); | |
1707 | case INST_VC: | |
1708 | return ((status_reg & FLAG_V) == 0); | |
1709 | case INST_HI: | |
1710 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1711 | case INST_LS: | |
1712 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1713 | case INST_GE: | |
1714 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1715 | case INST_LT: | |
1716 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1717 | case INST_GT: | |
1718 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1719 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1720 | case INST_LE: |
1721 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1722 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1723 | } |
1724 | return 1; | |
1725 | } | |
1726 | ||
9512d7fd | 1727 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1728 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1729 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1730 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1731 | #define sbits(obj,st,fn) \ | |
1732 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1733 | #define BranchDest(addr,instr) \ | |
1734 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1735 | #define ARM_PC_32 1 | |
1736 | ||
1737 | static unsigned long | |
ed9a39eb JM |
1738 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1739 | unsigned long status_reg) | |
c906108c SS |
1740 | { |
1741 | unsigned long res, shift; | |
1742 | int rm = bits (inst, 0, 3); | |
1743 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1744 | |
1745 | if (bit (inst, 4)) | |
c906108c SS |
1746 | { |
1747 | int rs = bits (inst, 8, 11); | |
1748 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1749 | } | |
1750 | else | |
1751 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1752 | |
1753 | res = (rm == 15 | |
c906108c | 1754 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1755 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1756 | : read_register (rm)); |
1757 | ||
1758 | switch (shifttype) | |
1759 | { | |
c5aa993b | 1760 | case 0: /* LSL */ |
c906108c SS |
1761 | res = shift >= 32 ? 0 : res << shift; |
1762 | break; | |
c5aa993b JM |
1763 | |
1764 | case 1: /* LSR */ | |
c906108c SS |
1765 | res = shift >= 32 ? 0 : res >> shift; |
1766 | break; | |
1767 | ||
c5aa993b JM |
1768 | case 2: /* ASR */ |
1769 | if (shift >= 32) | |
1770 | shift = 31; | |
c906108c SS |
1771 | res = ((res & 0x80000000L) |
1772 | ? ~((~res) >> shift) : res >> shift); | |
1773 | break; | |
1774 | ||
c5aa993b | 1775 | case 3: /* ROR/RRX */ |
c906108c SS |
1776 | shift &= 31; |
1777 | if (shift == 0) | |
1778 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1779 | else | |
c5aa993b | 1780 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1781 | break; |
1782 | } | |
1783 | ||
1784 | return res & 0xffffffff; | |
1785 | } | |
1786 | ||
c906108c SS |
1787 | /* Return number of 1-bits in VAL. */ |
1788 | ||
1789 | static int | |
ed9a39eb | 1790 | bitcount (unsigned long val) |
c906108c SS |
1791 | { |
1792 | int nbits; | |
1793 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1794 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1795 | return nbits; |
1796 | } | |
1797 | ||
34e8f22d | 1798 | CORE_ADDR |
ed9a39eb | 1799 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1800 | { |
c5aa993b | 1801 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1802 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1803 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1804 | unsigned long offset; |
1805 | ||
1806 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1807 | { | |
1808 | CORE_ADDR sp; | |
1809 | ||
1810 | /* Fetch the saved PC from the stack. It's stored above | |
1811 | all of the other registers. */ | |
1812 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1813 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1814 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1815 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1816 | if (nextpc == pc) | |
1817 | error ("Infinite loop detected"); | |
1818 | } | |
1819 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1820 | { | |
34e8f22d | 1821 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1822 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1823 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1824 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1825 | } | |
1826 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1827 | { | |
1828 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1829 | } | |
1830 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1831 | { | |
1832 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1833 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1834 | nextpc = pc_val + offset; |
1835 | } | |
1836 | ||
1837 | return nextpc; | |
1838 | } | |
1839 | ||
34e8f22d | 1840 | CORE_ADDR |
ed9a39eb | 1841 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1842 | { |
1843 | unsigned long pc_val; | |
1844 | unsigned long this_instr; | |
1845 | unsigned long status; | |
1846 | CORE_ADDR nextpc; | |
1847 | ||
1848 | if (arm_pc_is_thumb (pc)) | |
1849 | return thumb_get_next_pc (pc); | |
1850 | ||
1851 | pc_val = (unsigned long) pc; | |
1852 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1853 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1854 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1855 | |
1856 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1857 | { | |
1858 | switch (bits (this_instr, 24, 27)) | |
1859 | { | |
c5aa993b | 1860 | case 0x0: |
94c30b78 | 1861 | case 0x1: /* data processing */ |
c5aa993b JM |
1862 | case 0x2: |
1863 | case 0x3: | |
c906108c SS |
1864 | { |
1865 | unsigned long operand1, operand2, result = 0; | |
1866 | unsigned long rn; | |
1867 | int c; | |
c5aa993b | 1868 | |
c906108c SS |
1869 | if (bits (this_instr, 12, 15) != 15) |
1870 | break; | |
1871 | ||
1872 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1873 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1874 | error ("Illegal update to pc in instruction"); |
1875 | ||
1876 | /* Multiply into PC */ | |
1877 | c = (status & FLAG_C) ? 1 : 0; | |
1878 | rn = bits (this_instr, 16, 19); | |
1879 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1880 | |
c906108c SS |
1881 | if (bit (this_instr, 25)) |
1882 | { | |
1883 | unsigned long immval = bits (this_instr, 0, 7); | |
1884 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1885 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1886 | & 0xffffffff; | |
c906108c | 1887 | } |
c5aa993b | 1888 | else /* operand 2 is a shifted register */ |
c906108c | 1889 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1890 | |
c906108c SS |
1891 | switch (bits (this_instr, 21, 24)) |
1892 | { | |
c5aa993b | 1893 | case 0x0: /*and */ |
c906108c SS |
1894 | result = operand1 & operand2; |
1895 | break; | |
1896 | ||
c5aa993b | 1897 | case 0x1: /*eor */ |
c906108c SS |
1898 | result = operand1 ^ operand2; |
1899 | break; | |
1900 | ||
c5aa993b | 1901 | case 0x2: /*sub */ |
c906108c SS |
1902 | result = operand1 - operand2; |
1903 | break; | |
1904 | ||
c5aa993b | 1905 | case 0x3: /*rsb */ |
c906108c SS |
1906 | result = operand2 - operand1; |
1907 | break; | |
1908 | ||
c5aa993b | 1909 | case 0x4: /*add */ |
c906108c SS |
1910 | result = operand1 + operand2; |
1911 | break; | |
1912 | ||
c5aa993b | 1913 | case 0x5: /*adc */ |
c906108c SS |
1914 | result = operand1 + operand2 + c; |
1915 | break; | |
1916 | ||
c5aa993b | 1917 | case 0x6: /*sbc */ |
c906108c SS |
1918 | result = operand1 - operand2 + c; |
1919 | break; | |
1920 | ||
c5aa993b | 1921 | case 0x7: /*rsc */ |
c906108c SS |
1922 | result = operand2 - operand1 + c; |
1923 | break; | |
1924 | ||
c5aa993b JM |
1925 | case 0x8: |
1926 | case 0x9: | |
1927 | case 0xa: | |
1928 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1929 | result = (unsigned long) nextpc; |
1930 | break; | |
1931 | ||
c5aa993b | 1932 | case 0xc: /*orr */ |
c906108c SS |
1933 | result = operand1 | operand2; |
1934 | break; | |
1935 | ||
c5aa993b | 1936 | case 0xd: /*mov */ |
c906108c SS |
1937 | /* Always step into a function. */ |
1938 | result = operand2; | |
c5aa993b | 1939 | break; |
c906108c | 1940 | |
c5aa993b | 1941 | case 0xe: /*bic */ |
c906108c SS |
1942 | result = operand1 & ~operand2; |
1943 | break; | |
1944 | ||
c5aa993b | 1945 | case 0xf: /*mvn */ |
c906108c SS |
1946 | result = ~operand2; |
1947 | break; | |
1948 | } | |
1949 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1950 | ||
1951 | if (nextpc == pc) | |
1952 | error ("Infinite loop detected"); | |
1953 | break; | |
1954 | } | |
c5aa993b JM |
1955 | |
1956 | case 0x4: | |
1957 | case 0x5: /* data transfer */ | |
1958 | case 0x6: | |
1959 | case 0x7: | |
c906108c SS |
1960 | if (bit (this_instr, 20)) |
1961 | { | |
1962 | /* load */ | |
1963 | if (bits (this_instr, 12, 15) == 15) | |
1964 | { | |
1965 | /* rd == pc */ | |
c5aa993b | 1966 | unsigned long rn; |
c906108c | 1967 | unsigned long base; |
c5aa993b | 1968 | |
c906108c SS |
1969 | if (bit (this_instr, 22)) |
1970 | error ("Illegal update to pc in instruction"); | |
1971 | ||
1972 | /* byte write to PC */ | |
1973 | rn = bits (this_instr, 16, 19); | |
1974 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1975 | if (bit (this_instr, 24)) | |
1976 | { | |
1977 | /* pre-indexed */ | |
1978 | int c = (status & FLAG_C) ? 1 : 0; | |
1979 | unsigned long offset = | |
c5aa993b | 1980 | (bit (this_instr, 25) |
ed9a39eb | 1981 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1982 | : bits (this_instr, 0, 11)); |
c906108c SS |
1983 | |
1984 | if (bit (this_instr, 23)) | |
1985 | base += offset; | |
1986 | else | |
1987 | base -= offset; | |
1988 | } | |
c5aa993b | 1989 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1990 | 4); |
c5aa993b | 1991 | |
c906108c SS |
1992 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1993 | ||
1994 | if (nextpc == pc) | |
1995 | error ("Infinite loop detected"); | |
1996 | } | |
1997 | } | |
1998 | break; | |
c5aa993b JM |
1999 | |
2000 | case 0x8: | |
2001 | case 0x9: /* block transfer */ | |
c906108c SS |
2002 | if (bit (this_instr, 20)) |
2003 | { | |
2004 | /* LDM */ | |
2005 | if (bit (this_instr, 15)) | |
2006 | { | |
2007 | /* loading pc */ | |
2008 | int offset = 0; | |
2009 | ||
2010 | if (bit (this_instr, 23)) | |
2011 | { | |
2012 | /* up */ | |
2013 | unsigned long reglist = bits (this_instr, 0, 14); | |
2014 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2015 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2016 | offset += 4; |
2017 | } | |
2018 | else if (bit (this_instr, 24)) | |
2019 | offset = -4; | |
c5aa993b | 2020 | |
c906108c | 2021 | { |
c5aa993b JM |
2022 | unsigned long rn_val = |
2023 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
2024 | nextpc = |
2025 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2026 | + offset), |
c906108c SS |
2027 | 4); |
2028 | } | |
2029 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2030 | if (nextpc == pc) | |
2031 | error ("Infinite loop detected"); | |
2032 | } | |
2033 | } | |
2034 | break; | |
c5aa993b JM |
2035 | |
2036 | case 0xb: /* branch & link */ | |
2037 | case 0xa: /* branch */ | |
c906108c SS |
2038 | { |
2039 | nextpc = BranchDest (pc, this_instr); | |
2040 | ||
2041 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2042 | if (nextpc == pc) | |
2043 | error ("Infinite loop detected"); | |
2044 | break; | |
2045 | } | |
c5aa993b JM |
2046 | |
2047 | case 0xc: | |
2048 | case 0xd: | |
2049 | case 0xe: /* coproc ops */ | |
2050 | case 0xf: /* SWI */ | |
c906108c SS |
2051 | break; |
2052 | ||
2053 | default: | |
97e03143 | 2054 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2055 | return (pc); |
2056 | } | |
2057 | } | |
2058 | ||
2059 | return nextpc; | |
2060 | } | |
2061 | ||
9512d7fd FN |
2062 | /* single_step() is called just before we want to resume the inferior, |
2063 | if we want to single-step it but there is no hardware or kernel | |
2064 | single-step support. We find the target of the coming instruction | |
2065 | and breakpoint it. | |
2066 | ||
94c30b78 MS |
2067 | single_step() is also called just after the inferior stops. If we |
2068 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2069 | |
34e8f22d RE |
2070 | static void |
2071 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2072 | { |
b8d5e71d | 2073 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2074 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2075 | ||
2076 | if (insert_bpt) | |
2077 | { | |
34e8f22d | 2078 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2079 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2080 | } |
2081 | else | |
80fcf3f0 | 2082 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2083 | } |
9512d7fd | 2084 | |
c906108c SS |
2085 | #include "bfd-in2.h" |
2086 | #include "libcoff.h" | |
2087 | ||
2088 | static int | |
ed9a39eb | 2089 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2090 | { |
2091 | if (arm_pc_is_thumb (memaddr)) | |
2092 | { | |
c5aa993b JM |
2093 | static asymbol *asym; |
2094 | static combined_entry_type ce; | |
2095 | static struct coff_symbol_struct csym; | |
2096 | static struct _bfd fake_bfd; | |
2097 | static bfd_target fake_target; | |
c906108c SS |
2098 | |
2099 | if (csym.native == NULL) | |
2100 | { | |
da3c6d4a MS |
2101 | /* Create a fake symbol vector containing a Thumb symbol. |
2102 | This is solely so that the code in print_insn_little_arm() | |
2103 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2104 | the presence of a Thumb symbol and switch to decoding | |
2105 | Thumb instructions. */ | |
c5aa993b JM |
2106 | |
2107 | fake_target.flavour = bfd_target_coff_flavour; | |
2108 | fake_bfd.xvec = &fake_target; | |
c906108c | 2109 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2110 | csym.native = &ce; |
2111 | csym.symbol.the_bfd = &fake_bfd; | |
2112 | csym.symbol.name = "fake"; | |
2113 | asym = (asymbol *) & csym; | |
c906108c | 2114 | } |
c5aa993b | 2115 | |
c906108c | 2116 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2117 | info->symbols = &asym; |
c906108c SS |
2118 | } |
2119 | else | |
2120 | info->symbols = NULL; | |
c5aa993b | 2121 | |
d7449b42 | 2122 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2123 | return print_insn_big_arm (memaddr, info); |
2124 | else | |
2125 | return print_insn_little_arm (memaddr, info); | |
2126 | } | |
2127 | ||
66e810cd RE |
2128 | /* The following define instruction sequences that will cause ARM |
2129 | cpu's to take an undefined instruction trap. These are used to | |
2130 | signal a breakpoint to GDB. | |
2131 | ||
2132 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2133 | modes. A different instruction is required for each mode. The ARM | |
2134 | cpu's can also be big or little endian. Thus four different | |
2135 | instructions are needed to support all cases. | |
2136 | ||
2137 | Note: ARMv4 defines several new instructions that will take the | |
2138 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2139 | not in fact add the new instructions. The new undefined | |
2140 | instructions in ARMv4 are all instructions that had no defined | |
2141 | behaviour in earlier chips. There is no guarantee that they will | |
2142 | raise an exception, but may be treated as NOP's. In practice, it | |
2143 | may only safe to rely on instructions matching: | |
2144 | ||
2145 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2146 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2147 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2148 | ||
2149 | Even this may only true if the condition predicate is true. The | |
2150 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2151 | ||
2152 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2153 | and NetBSD all use a software interrupt rather than an undefined | |
2154 | instruction to force a trap. This can be handled by by the | |
2155 | abi-specific code during establishment of the gdbarch vector. */ | |
2156 | ||
2157 | ||
d7b486e7 RE |
2158 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2159 | override these definitions. */ | |
66e810cd RE |
2160 | #ifndef ARM_LE_BREAKPOINT |
2161 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2162 | #endif | |
2163 | #ifndef ARM_BE_BREAKPOINT | |
2164 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2165 | #endif | |
2166 | #ifndef THUMB_LE_BREAKPOINT | |
2167 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2168 | #endif | |
2169 | #ifndef THUMB_BE_BREAKPOINT | |
2170 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2171 | #endif | |
2172 | ||
2173 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2174 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2175 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2176 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2177 | ||
34e8f22d RE |
2178 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2179 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2180 | breakpoint should be used. It returns a pointer to a string of |
2181 | bytes that encode a breakpoint instruction, stores the length of | |
2182 | the string to *lenptr, and adjusts the program counter (if | |
2183 | necessary) to point to the actual memory location where the | |
c906108c SS |
2184 | breakpoint should be inserted. */ |
2185 | ||
34e8f22d RE |
2186 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2187 | breakpoints and storing their handles instread of what was in | |
2188 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2189 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2190 | |
ab89facf | 2191 | static const unsigned char * |
ed9a39eb | 2192 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2193 | { |
66e810cd RE |
2194 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2195 | ||
c906108c SS |
2196 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2197 | { | |
66e810cd RE |
2198 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2199 | *lenptr = tdep->thumb_breakpoint_size; | |
2200 | return tdep->thumb_breakpoint; | |
c906108c SS |
2201 | } |
2202 | else | |
2203 | { | |
66e810cd RE |
2204 | *lenptr = tdep->arm_breakpoint_size; |
2205 | return tdep->arm_breakpoint; | |
c906108c SS |
2206 | } |
2207 | } | |
ed9a39eb JM |
2208 | |
2209 | /* Extract from an array REGBUF containing the (raw) register state a | |
2210 | function return value of type TYPE, and copy that, in virtual | |
2211 | format, into VALBUF. */ | |
2212 | ||
34e8f22d | 2213 | static void |
ed9a39eb JM |
2214 | arm_extract_return_value (struct type *type, |
2215 | char regbuf[REGISTER_BYTES], | |
2216 | char *valbuf) | |
2217 | { | |
2218 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 RE |
2219 | { |
2220 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2221 | ||
2222 | switch (tdep->fp_model) | |
2223 | { | |
2224 | case ARM_FLOAT_FPA: | |
2225 | convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)], | |
2226 | valbuf); | |
2227 | break; | |
2228 | ||
2229 | case ARM_FLOAT_SOFT: | |
2230 | case ARM_FLOAT_SOFT_VFP: | |
2231 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], | |
2232 | TYPE_LENGTH (type)); | |
2233 | break; | |
2234 | ||
2235 | default: | |
2236 | internal_error | |
2237 | (__FILE__, __LINE__, | |
2238 | "arm_extract_return_value: Floating point model not supported"); | |
2239 | break; | |
2240 | } | |
2241 | } | |
ed9a39eb | 2242 | else |
34e8f22d RE |
2243 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], |
2244 | TYPE_LENGTH (type)); | |
2245 | } | |
2246 | ||
67255d04 RE |
2247 | /* Extract from an array REGBUF containing the (raw) register state |
2248 | the address in which a function should return its structure value. */ | |
2249 | ||
2250 | static CORE_ADDR | |
2251 | arm_extract_struct_value_address (char *regbuf) | |
2252 | { | |
2253 | return extract_address (regbuf, REGISTER_RAW_SIZE(ARM_A1_REGNUM)); | |
2254 | } | |
2255 | ||
2256 | /* Will a function return an aggregate type in memory or in a | |
2257 | register? Return 0 if an aggregate type can be returned in a | |
2258 | register, 1 if it must be returned in memory. */ | |
2259 | ||
2260 | static int | |
2261 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2262 | { | |
2263 | int nRc; | |
2264 | register enum type_code code; | |
2265 | ||
2266 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2267 | registers. For an aggregate type to be integer like, its size | |
2268 | must be less than or equal to REGISTER_SIZE and the offset of | |
2269 | each addressable subfield must be zero. Note that bit fields are | |
2270 | not addressable, and all addressable subfields of unions always | |
2271 | start at offset zero. | |
2272 | ||
2273 | This function is based on the behaviour of GCC 2.95.1. | |
2274 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2275 | ||
2276 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2277 | parameters correctly for a function returning the following | |
2278 | structure: struct { float f;}; This should be returned in memory, | |
2279 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2280 | know of any way to detect if a function like the above has been | |
2281 | compiled with the correct calling convention. */ | |
2282 | ||
2283 | /* All aggregate types that won't fit in a register must be returned | |
2284 | in memory. */ | |
2285 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2286 | { | |
2287 | return 1; | |
2288 | } | |
2289 | ||
2290 | /* The only aggregate types that can be returned in a register are | |
2291 | structs and unions. Arrays must be returned in memory. */ | |
2292 | code = TYPE_CODE (type); | |
2293 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2294 | { | |
2295 | return 1; | |
2296 | } | |
2297 | ||
2298 | /* Assume all other aggregate types can be returned in a register. | |
2299 | Run a check for structures, unions and arrays. */ | |
2300 | nRc = 0; | |
2301 | ||
2302 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2303 | { | |
2304 | int i; | |
2305 | /* Need to check if this struct/union is "integer" like. For | |
2306 | this to be true, its size must be less than or equal to | |
2307 | REGISTER_SIZE and the offset of each addressable subfield | |
2308 | must be zero. Note that bit fields are not addressable, and | |
2309 | unions always start at offset zero. If any of the subfields | |
2310 | is a floating point type, the struct/union cannot be an | |
2311 | integer type. */ | |
2312 | ||
2313 | /* For each field in the object, check: | |
2314 | 1) Is it FP? --> yes, nRc = 1; | |
2315 | 2) Is it addressable (bitpos != 0) and | |
2316 | not packed (bitsize == 0)? | |
2317 | --> yes, nRc = 1 | |
2318 | */ | |
2319 | ||
2320 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2321 | { | |
2322 | enum type_code field_type_code; | |
2323 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2324 | ||
2325 | /* Is it a floating point type field? */ | |
2326 | if (field_type_code == TYPE_CODE_FLT) | |
2327 | { | |
2328 | nRc = 1; | |
2329 | break; | |
2330 | } | |
2331 | ||
2332 | /* If bitpos != 0, then we have to care about it. */ | |
2333 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2334 | { | |
2335 | /* Bitfields are not addressable. If the field bitsize is | |
2336 | zero, then the field is not packed. Hence it cannot be | |
2337 | a bitfield or any other packed type. */ | |
2338 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2339 | { | |
2340 | nRc = 1; | |
2341 | break; | |
2342 | } | |
2343 | } | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | return nRc; | |
2348 | } | |
2349 | ||
34e8f22d RE |
2350 | /* Write into appropriate registers a function return value of type |
2351 | TYPE, given in virtual format. */ | |
2352 | ||
2353 | static void | |
2354 | arm_store_return_value (struct type *type, char *valbuf) | |
2355 | { | |
2356 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2357 | { | |
08216dd7 | 2358 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2359 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2360 | |
08216dd7 RE |
2361 | switch (tdep->fp_model) |
2362 | { | |
2363 | case ARM_FLOAT_FPA: | |
2364 | ||
2365 | convert_to_extended (valbuf, buf); | |
2366 | write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf, | |
7bbcf283 | 2367 | FP_REGISTER_RAW_SIZE); |
08216dd7 RE |
2368 | break; |
2369 | ||
2370 | case ARM_FLOAT_SOFT: | |
2371 | case ARM_FLOAT_SOFT_VFP: | |
2372 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); | |
2373 | break; | |
2374 | ||
2375 | default: | |
2376 | internal_error | |
2377 | (__FILE__, __LINE__, | |
2378 | "arm_store_return_value: Floating point model not supported"); | |
2379 | break; | |
2380 | } | |
34e8f22d RE |
2381 | } |
2382 | else | |
08216dd7 | 2383 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); |
34e8f22d RE |
2384 | } |
2385 | ||
2386 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2387 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2388 | |
2389 | static void | |
2390 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2391 | { | |
2392 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2393 | } |
2394 | ||
9df628e0 RE |
2395 | static int |
2396 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2397 | { | |
2398 | CORE_ADDR jb_addr; | |
2399 | char buf[INT_REGISTER_RAW_SIZE]; | |
2400 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2401 | ||
2402 | jb_addr = read_register (ARM_A1_REGNUM); | |
2403 | ||
2404 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2405 | INT_REGISTER_RAW_SIZE)) | |
2406 | return 0; | |
2407 | ||
2408 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2409 | return 1; | |
2410 | } | |
2411 | ||
ed9a39eb | 2412 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2413 | |
2414 | int | |
ed9a39eb | 2415 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2416 | { |
2417 | CORE_ADDR start_addr; | |
2418 | ||
ed9a39eb JM |
2419 | /* Find the starting address of the function containing the PC. If |
2420 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2421 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2422 | &start_addr, NULL)) | |
c906108c SS |
2423 | return 0; |
2424 | ||
2425 | return strncmp (name, "_call_via_r", 11) == 0; | |
2426 | } | |
2427 | ||
ed9a39eb JM |
2428 | /* If PC is in a Thumb call or return stub, return the address of the |
2429 | target PC, which is in a register. The thunk functions are called | |
2430 | _called_via_xx, where x is the register name. The possible names | |
2431 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2432 | |
2433 | CORE_ADDR | |
ed9a39eb | 2434 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2435 | { |
c5aa993b | 2436 | char *name; |
c906108c SS |
2437 | CORE_ADDR start_addr; |
2438 | ||
2439 | /* Find the starting address and name of the function containing the PC. */ | |
2440 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2441 | return 0; | |
2442 | ||
2443 | /* Call thunks always start with "_call_via_". */ | |
2444 | if (strncmp (name, "_call_via_", 10) == 0) | |
2445 | { | |
ed9a39eb JM |
2446 | /* Use the name suffix to determine which register contains the |
2447 | target PC. */ | |
c5aa993b JM |
2448 | static char *table[15] = |
2449 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2450 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2451 | }; | |
c906108c SS |
2452 | int regno; |
2453 | ||
2454 | for (regno = 0; regno <= 14; regno++) | |
2455 | if (strcmp (&name[10], table[regno]) == 0) | |
2456 | return read_register (regno); | |
2457 | } | |
ed9a39eb | 2458 | |
c5aa993b | 2459 | return 0; /* not a stub */ |
c906108c SS |
2460 | } |
2461 | ||
da3c6d4a MS |
2462 | /* If the user changes the register disassembly flavor used for info |
2463 | register and other commands, we have to also switch the flavor used | |
2464 | in opcodes for disassembly output. This function is run in the set | |
94c30b78 | 2465 | disassembly_flavor command, and does that. */ |
bc90b915 FN |
2466 | |
2467 | static void | |
2468 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2469 | struct cmd_list_element *c) | |
2470 | { | |
2471 | set_disassembly_flavor (); | |
2472 | } | |
2473 | \f | |
966fbf70 | 2474 | /* Return the ARM register name corresponding to register I. */ |
34e8f22d RE |
2475 | static char * |
2476 | arm_register_name (int i) | |
966fbf70 RE |
2477 | { |
2478 | return arm_register_names[i]; | |
2479 | } | |
2480 | ||
bc90b915 FN |
2481 | static void |
2482 | set_disassembly_flavor (void) | |
2483 | { | |
2484 | const char *setname, *setdesc, **regnames; | |
2485 | int numregs, j; | |
2486 | ||
94c30b78 | 2487 | /* Find the flavor that the user wants in the opcodes table. */ |
bc90b915 FN |
2488 | int current = 0; |
2489 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2490 | while ((disassembly_flavor != setname) | |
2491 | && (current < num_flavor_options)) | |
2492 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2493 | current_option = current; | |
2494 | ||
94c30b78 | 2495 | /* Fill our copy. */ |
bc90b915 FN |
2496 | for (j = 0; j < numregs; j++) |
2497 | arm_register_names[j] = (char *) regnames[j]; | |
2498 | ||
94c30b78 | 2499 | /* Adjust case. */ |
34e8f22d | 2500 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2501 | { |
34e8f22d RE |
2502 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2503 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2504 | } |
2505 | else | |
2506 | { | |
34e8f22d RE |
2507 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2508 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2509 | } |
2510 | ||
94c30b78 | 2511 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2512 | set_arm_regname_option (current); |
2513 | } | |
2514 | ||
2515 | /* arm_othernames implements the "othernames" command. This is kind | |
2516 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2517 | also used for the x86 gdb. I will keep this around, however, in | |
94c30b78 | 2518 | case anyone is actually using it. */ |
bc90b915 FN |
2519 | |
2520 | static void | |
2521 | arm_othernames (char *names, int n) | |
2522 | { | |
94c30b78 | 2523 | /* Circle through the various flavors. */ |
bc90b915 FN |
2524 | current_option = (current_option + 1) % num_flavor_options; |
2525 | ||
2526 | disassembly_flavor = valid_flavors[current_option]; | |
94c30b78 | 2527 | set_disassembly_flavor (); |
bc90b915 FN |
2528 | } |
2529 | ||
a42dd537 KB |
2530 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2531 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2532 | Note, however, that link.h is not actually referred to in this file. | |
2533 | Instead, the relevant structs offsets were obtained from examining | |
2534 | link.h. (We can't refer to link.h from this file because the host | |
2535 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2536 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2537 | |
2538 | struct link_map_offsets * | |
2539 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2540 | { | |
2541 | static struct link_map_offsets lmo; | |
2542 | static struct link_map_offsets *lmp = 0; | |
2543 | ||
2544 | if (lmp == 0) | |
2545 | { | |
2546 | lmp = &lmo; | |
2547 | ||
2548 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2549 | need. */ |
a42dd537 KB |
2550 | |
2551 | lmo.r_map_offset = 4; | |
2552 | lmo.r_map_size = 4; | |
2553 | ||
2554 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2555 | need. */ |
a42dd537 KB |
2556 | |
2557 | lmo.l_addr_offset = 0; | |
2558 | lmo.l_addr_size = 4; | |
2559 | ||
2560 | lmo.l_name_offset = 4; | |
2561 | lmo.l_name_size = 4; | |
2562 | ||
2563 | lmo.l_next_offset = 12; | |
2564 | lmo.l_next_size = 4; | |
2565 | ||
2566 | lmo.l_prev_offset = 16; | |
2567 | lmo.l_prev_size = 4; | |
2568 | } | |
2569 | ||
2570 | return lmp; | |
2571 | } | |
2572 | ||
082fc60d RE |
2573 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2574 | function. */ | |
2575 | ||
2576 | static int | |
2577 | coff_sym_is_thumb (int val) | |
2578 | { | |
2579 | return (val == C_THUMBEXT || | |
2580 | val == C_THUMBSTAT || | |
2581 | val == C_THUMBEXTFUNC || | |
2582 | val == C_THUMBSTATFUNC || | |
2583 | val == C_THUMBLABEL); | |
2584 | } | |
2585 | ||
2586 | /* arm_coff_make_msymbol_special() | |
2587 | arm_elf_make_msymbol_special() | |
2588 | ||
2589 | These functions test whether the COFF or ELF symbol corresponds to | |
2590 | an address in thumb code, and set a "special" bit in a minimal | |
2591 | symbol to indicate that it does. */ | |
2592 | ||
34e8f22d | 2593 | static void |
082fc60d RE |
2594 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2595 | { | |
2596 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2597 | STT_ARM_TFUNC). */ | |
2598 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2599 | == STT_LOPROC) | |
2600 | MSYMBOL_SET_SPECIAL (msym); | |
2601 | } | |
2602 | ||
34e8f22d | 2603 | static void |
082fc60d RE |
2604 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2605 | { | |
2606 | if (coff_sym_is_thumb (val)) | |
2607 | MSYMBOL_SET_SPECIAL (msym); | |
2608 | } | |
2609 | ||
97e03143 RE |
2610 | \f |
2611 | static void | |
2612 | process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj) | |
2613 | { | |
2614 | enum arm_abi *os_ident_ptr = obj; | |
2615 | const char *name; | |
2616 | unsigned int sectsize; | |
2617 | ||
2618 | name = bfd_get_section_name (abfd, sect); | |
2619 | sectsize = bfd_section_size (abfd, sect); | |
2620 | ||
2621 | if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0) | |
2622 | { | |
2623 | unsigned int name_length, data_length, note_type; | |
2624 | char *note; | |
2625 | ||
2626 | /* If the section is larger than this, it's probably not what we are | |
2627 | looking for. */ | |
2628 | if (sectsize > 128) | |
2629 | sectsize = 128; | |
2630 | ||
2631 | note = alloca (sectsize); | |
2632 | ||
2633 | bfd_get_section_contents (abfd, sect, note, | |
2634 | (file_ptr) 0, (bfd_size_type) sectsize); | |
2635 | ||
2636 | name_length = bfd_h_get_32 (abfd, note); | |
2637 | data_length = bfd_h_get_32 (abfd, note + 4); | |
2638 | note_type = bfd_h_get_32 (abfd, note + 8); | |
2639 | ||
2640 | if (name_length == 4 && data_length == 16 && note_type == 1 | |
2641 | && strcmp (note + 12, "GNU") == 0) | |
2642 | { | |
2643 | int os_number = bfd_h_get_32 (abfd, note + 16); | |
2644 | ||
d7afb4c9 | 2645 | /* The case numbers are from abi-tags in glibc. */ |
97e03143 RE |
2646 | switch (os_number) |
2647 | { | |
2648 | case 0 : | |
2649 | *os_ident_ptr = ARM_ABI_LINUX; | |
2650 | break; | |
2651 | ||
2652 | case 1 : | |
2653 | internal_error | |
2654 | (__FILE__, __LINE__, | |
2655 | "process_note_abi_sections: Hurd objects not supported"); | |
2656 | break; | |
2657 | ||
2658 | case 2 : | |
2659 | internal_error | |
2660 | (__FILE__, __LINE__, | |
2661 | "process_note_abi_sections: Solaris objects not supported"); | |
2662 | break; | |
2663 | ||
2664 | default : | |
2665 | internal_error | |
2666 | (__FILE__, __LINE__, | |
2667 | "process_note_abi_sections: unknown OS number %d", | |
2668 | os_number); | |
2669 | break; | |
2670 | } | |
2671 | } | |
2672 | } | |
2673 | /* NetBSD uses a similar trick. */ | |
2674 | else if (strcmp (name, ".note.netbsd.ident") == 0 && sectsize > 0) | |
2675 | { | |
2676 | unsigned int name_length, desc_length, note_type; | |
2677 | char *note; | |
2678 | ||
2679 | /* If the section is larger than this, it's probably not what we are | |
2680 | looking for. */ | |
2681 | if (sectsize > 128) | |
2682 | sectsize = 128; | |
2683 | ||
2684 | note = alloca (sectsize); | |
2685 | ||
2686 | bfd_get_section_contents (abfd, sect, note, | |
2687 | (file_ptr) 0, (bfd_size_type) sectsize); | |
2688 | ||
2689 | name_length = bfd_h_get_32 (abfd, note); | |
2690 | desc_length = bfd_h_get_32 (abfd, note + 4); | |
2691 | note_type = bfd_h_get_32 (abfd, note + 8); | |
2692 | ||
2693 | if (name_length == 7 && desc_length == 4 && note_type == 1 | |
2694 | && strcmp (note + 12, "NetBSD") == 0) | |
2695 | /* XXX Should we check the version here? | |
2696 | Probably not necessary yet. */ | |
2697 | *os_ident_ptr = ARM_ABI_NETBSD_ELF; | |
2698 | } | |
2699 | } | |
2700 | ||
2701 | /* Return one of the ELFOSABI_ constants for BFDs representing ELF | |
2702 | executables. If it's not an ELF executable or if the OS/ABI couldn't | |
d7afb4c9 | 2703 | be determined, simply return -1. */ |
97e03143 RE |
2704 | |
2705 | static int | |
2706 | get_elfosabi (bfd *abfd) | |
2707 | { | |
2708 | int elfosabi; | |
2709 | enum arm_abi arm_abi = ARM_ABI_UNKNOWN; | |
2710 | ||
2711 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; | |
2712 | ||
2713 | /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate | |
2714 | that we're on a SYSV system. However, GNU/Linux uses a note section | |
2715 | to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we | |
2716 | have to check the note sections too. | |
2717 | ||
2718 | GNU/ARM tools set the EI_OSABI field to ELFOSABI_ARM, so handle that | |
d7afb4c9 | 2719 | as well. */ |
97e03143 RE |
2720 | if (elfosabi == 0 || elfosabi == ELFOSABI_ARM) |
2721 | { | |
2722 | bfd_map_over_sections (abfd, | |
2723 | process_note_abi_tag_sections, | |
2724 | &arm_abi); | |
2725 | } | |
2726 | ||
2727 | if (arm_abi != ARM_ABI_UNKNOWN) | |
2728 | return arm_abi; | |
2729 | ||
2730 | switch (elfosabi) | |
2731 | { | |
2732 | case ELFOSABI_NONE: | |
2733 | /* Existing ARM Tools don't set this field, so look at the EI_FLAGS | |
2734 | field for more information. */ | |
2735 | ||
2736 | switch (EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags)) | |
2737 | { | |
2738 | case EF_ARM_EABI_VER1: | |
2739 | return ARM_ABI_EABI_V1; | |
2740 | ||
2741 | case EF_ARM_EABI_VER2: | |
2742 | return ARM_ABI_EABI_V2; | |
2743 | ||
2744 | case EF_ARM_EABI_UNKNOWN: | |
2745 | /* Assume GNU tools. */ | |
2746 | return ARM_ABI_APCS; | |
2747 | ||
2748 | default: | |
2749 | internal_error (__FILE__, __LINE__, | |
2750 | "get_elfosabi: Unknown ARM EABI version 0x%lx", | |
2751 | EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags)); | |
2752 | ||
2753 | } | |
2754 | break; | |
2755 | ||
2756 | case ELFOSABI_NETBSD: | |
2757 | return ARM_ABI_NETBSD_ELF; | |
2758 | ||
2759 | case ELFOSABI_FREEBSD: | |
2760 | return ARM_ABI_FREEBSD; | |
2761 | ||
2762 | case ELFOSABI_LINUX: | |
2763 | return ARM_ABI_LINUX; | |
2764 | ||
2765 | case ELFOSABI_ARM: | |
2766 | /* Assume GNU tools with the old APCS abi. */ | |
2767 | return ARM_ABI_APCS; | |
2768 | ||
2769 | default: | |
2770 | } | |
2771 | ||
2772 | return ARM_ABI_UNKNOWN; | |
2773 | } | |
2774 | ||
2775 | struct arm_abi_handler | |
2776 | { | |
2777 | struct arm_abi_handler *next; | |
2778 | enum arm_abi abi; | |
2779 | void (*init_abi)(struct gdbarch_info, struct gdbarch *); | |
2780 | }; | |
2781 | ||
2782 | struct arm_abi_handler *arm_abi_handler_list = NULL; | |
2783 | ||
2784 | void | |
2785 | arm_gdbarch_register_os_abi (enum arm_abi abi, | |
2786 | void (*init_abi)(struct gdbarch_info, | |
2787 | struct gdbarch *)) | |
2788 | { | |
2789 | struct arm_abi_handler **handler_p; | |
2790 | ||
2791 | for (handler_p = &arm_abi_handler_list; *handler_p != NULL; | |
2792 | handler_p = &(*handler_p)->next) | |
2793 | { | |
2794 | if ((*handler_p)->abi == abi) | |
2795 | { | |
2796 | internal_error | |
2797 | (__FILE__, __LINE__, | |
2798 | "arm_gdbarch_register_os_abi: A handler for this ABI variant (%d)" | |
2799 | " has already been registered", (int)abi); | |
2800 | /* If user wants to continue, override previous definition. */ | |
2801 | (*handler_p)->init_abi = init_abi; | |
2802 | return; | |
2803 | } | |
2804 | } | |
2805 | ||
2806 | (*handler_p) | |
2807 | = (struct arm_abi_handler *) xmalloc (sizeof (struct arm_abi_handler)); | |
2808 | (*handler_p)->next = NULL; | |
2809 | (*handler_p)->abi = abi; | |
2810 | (*handler_p)->init_abi = init_abi; | |
2811 | } | |
2812 | ||
da3c6d4a MS |
2813 | /* Initialize the current architecture based on INFO. If possible, |
2814 | re-use an architecture from ARCHES, which is a list of | |
2815 | architectures already created during this debugging session. | |
97e03143 | 2816 | |
da3c6d4a MS |
2817 | Called e.g. at program startup, when reading a core file, and when |
2818 | reading a binary file. */ | |
97e03143 | 2819 | |
39bbf761 RE |
2820 | static struct gdbarch * |
2821 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2822 | { | |
97e03143 | 2823 | struct gdbarch_tdep *tdep; |
39bbf761 | 2824 | struct gdbarch *gdbarch; |
97e03143 RE |
2825 | enum arm_abi arm_abi = ARM_ABI_UNKNOWN; |
2826 | struct arm_abi_handler *abi_handler; | |
39bbf761 | 2827 | |
97e03143 | 2828 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2829 | |
97e03143 RE |
2830 | if (info.abfd != NULL) |
2831 | { | |
2832 | switch (bfd_get_flavour (info.abfd)) | |
2833 | { | |
2834 | case bfd_target_elf_flavour: | |
2835 | arm_abi = get_elfosabi (info.abfd); | |
2836 | break; | |
2837 | ||
2838 | case bfd_target_aout_flavour: | |
2839 | if (strcmp (bfd_get_target(info.abfd), "a.out-arm-netbsd") == 0) | |
2840 | arm_abi = ARM_ABI_NETBSD_AOUT; | |
2841 | else | |
2842 | /* Assume it's an old APCS-style ABI. */ | |
2843 | arm_abi = ARM_ABI_APCS; | |
2844 | break; | |
2845 | ||
2846 | case bfd_target_coff_flavour: | |
2847 | /* Assume it's an old APCS-style ABI. */ | |
2848 | /* XXX WinCE? */ | |
2849 | arm_abi = ARM_ABI_APCS; | |
2850 | break; | |
2851 | ||
2852 | default: | |
2853 | /* Not sure what to do here, leave the ABI as unknown. */ | |
2854 | break; | |
2855 | } | |
2856 | } | |
2857 | ||
d7afb4c9 | 2858 | /* Find a candidate among extant architectures. */ |
97e03143 RE |
2859 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2860 | arches != NULL; | |
2861 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2862 | { | |
2863 | /* Make sure the ABI selection matches. */ | |
2864 | tdep = gdbarch_tdep (arches->gdbarch); | |
2865 | if (tdep && tdep->arm_abi == arm_abi) | |
2866 | return arches->gdbarch; | |
2867 | } | |
2868 | ||
2869 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2870 | gdbarch = gdbarch_alloc (&info, tdep); | |
2871 | ||
2872 | tdep->arm_abi = arm_abi; | |
2873 | if (arm_abi < ARM_ABI_INVALID) | |
2874 | tdep->abi_name = arm_abi_names[arm_abi]; | |
2875 | else | |
2876 | { | |
2877 | internal_error (__FILE__, __LINE__, "Invalid setting of arm_abi %d", | |
2878 | (int) arm_abi); | |
2879 | tdep->abi_name = "<invalid>"; | |
2880 | } | |
39bbf761 | 2881 | |
08216dd7 RE |
2882 | /* This is the way it has always defaulted. */ |
2883 | tdep->fp_model = ARM_FLOAT_FPA; | |
2884 | ||
2885 | /* Breakpoints. */ | |
67255d04 RE |
2886 | switch (info.byte_order) |
2887 | { | |
2888 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2889 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2890 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2891 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2892 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2893 | ||
67255d04 RE |
2894 | break; |
2895 | ||
2896 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2897 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2898 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2899 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2900 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2901 | ||
67255d04 RE |
2902 | break; |
2903 | ||
2904 | default: | |
2905 | internal_error (__FILE__, __LINE__, | |
2906 | "arm_gdbarch_init: bad byte order for float format"); | |
2907 | } | |
2908 | ||
d7b486e7 RE |
2909 | /* On ARM targets char defaults to unsigned. */ |
2910 | set_gdbarch_char_signed (gdbarch, 0); | |
2911 | ||
9df628e0 | 2912 | /* This should be low enough for everything. */ |
97e03143 | 2913 | tdep->lowest_pc = 0x20; |
94c30b78 | 2914 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2915 | |
848cfffb AC |
2916 | #if OLD_STYLE_ARM_DUMMY_FRAMES |
2917 | /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM | |
2918 | specific (non-generic) dummy frame code. Might be useful if | |
2919 | there appears to be a problem with the generic dummy frame | |
2920 | mechanism that replaced it. */ | |
39bbf761 RE |
2921 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
2922 | ||
2923 | /* Call dummy code. */ | |
2924 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2925 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
3fb4b924 RE |
2926 | /* We have to give this a value now, even though we will re-set it |
2927 | during each call to arm_fix_call_dummy. */ | |
2928 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8); | |
39bbf761 RE |
2929 | set_gdbarch_call_dummy_p (gdbarch, 1); |
2930 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2931 | ||
34e8f22d RE |
2932 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); |
2933 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words)); | |
2934 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
d7b486e7 | 2935 | set_gdbarch_call_dummy_length (gdbarch, 0); |
34e8f22d RE |
2936 | |
2937 | set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy); | |
2938 | ||
39bbf761 | 2939 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
848cfffb AC |
2940 | #else |
2941 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
2942 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
2943 | ||
2944 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
2945 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2946 | ||
2947 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2948 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2949 | ||
2950 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2951 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2952 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2953 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2954 | ||
2955 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
2956 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
2957 | ||
2958 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2959 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
2960 | #endif | |
39bbf761 RE |
2961 | |
2962 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
2963 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); | |
d7afb4c9 RE |
2964 | set_gdbarch_coerce_float_to_double (gdbarch, |
2965 | standard_coerce_float_to_double); | |
39bbf761 | 2966 | |
148754e5 | 2967 | /* Frame handling. */ |
39bbf761 | 2968 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
148754e5 RE |
2969 | set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
2970 | set_gdbarch_read_fp (gdbarch, arm_read_fp); | |
2971 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2972 | set_gdbarch_frameless_function_invocation | |
2973 | (gdbarch, arm_frameless_function_invocation); | |
2974 | set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc); | |
2975 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); | |
2976 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2977 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2978 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2979 | set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); | |
848cfffb AC |
2980 | #if OLD_STYLE_ARM_DUMMY_FRAMES |
2981 | /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM | |
2982 | specific (non-generic) dummy frame code. Might be useful if | |
2983 | there appears to be a problem with the generic dummy frame | |
2984 | mechanism that replaced it. */ | |
148754e5 | 2985 | set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame); |
848cfffb AC |
2986 | #else |
2987 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
2988 | #endif | |
148754e5 RE |
2989 | set_gdbarch_pop_frame (gdbarch, arm_pop_frame); |
2990 | ||
34e8f22d RE |
2991 | /* Address manipulation. */ |
2992 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2993 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2994 | ||
2995 | /* Offset from address of function to start of its code. */ | |
2996 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2997 | ||
2998 | /* Advance PC across function entry code. */ | |
2999 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
3000 | ||
3001 | /* Get the PC when a frame might not be available. */ | |
3002 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
3003 | ||
3004 | /* The stack grows downward. */ | |
3005 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3006 | ||
3007 | /* Breakpoint manipulation. */ | |
3008 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
3009 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3010 | ||
3011 | /* Information about registers, etc. */ | |
3012 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 3013 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
3014 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
3015 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
3016 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
3017 | set_gdbarch_register_bytes (gdbarch, | |
3018 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
3019 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
3020 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
3021 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
3022 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
3023 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
3024 | set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); | |
3025 | set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
3026 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); | |
3027 | ||
3028 | /* Integer registers are 4 bytes. */ | |
3029 | set_gdbarch_register_size (gdbarch, 4); | |
3030 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
3031 | ||
3032 | /* Returning results. */ | |
3033 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); | |
3034 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
3035 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); | |
67255d04 RE |
3036 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
3037 | set_gdbarch_extract_struct_value_address (gdbarch, | |
3038 | arm_extract_struct_value_address); | |
34e8f22d RE |
3039 | |
3040 | /* Single stepping. */ | |
3041 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
3042 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
3043 | ||
3044 | /* Minsymbol frobbing. */ | |
3045 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
3046 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
3047 | arm_coff_make_msymbol_special); | |
3048 | ||
97e03143 RE |
3049 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
3050 | if (arm_abi == ARM_ABI_UNKNOWN) | |
3051 | { | |
08216dd7 RE |
3052 | /* Don't complain about not knowing the ABI variant if we don't |
3053 | have an inferior. */ | |
3054 | if (info.abfd) | |
3055 | fprintf_filtered | |
3056 | (gdb_stderr, "GDB doesn't recognize the ABI of the inferior. " | |
3057 | "Attempting to continue with the default ARM settings"); | |
97e03143 RE |
3058 | } |
3059 | else | |
3060 | { | |
3061 | for (abi_handler = arm_abi_handler_list; abi_handler != NULL; | |
3062 | abi_handler = abi_handler->next) | |
3063 | if (abi_handler->abi == arm_abi) | |
3064 | break; | |
3065 | ||
3066 | if (abi_handler) | |
3067 | abi_handler->init_abi (info, gdbarch); | |
3068 | else | |
3069 | { | |
3070 | /* We assume that if GDB_MULTI_ARCH is less than | |
3071 | GDB_MULTI_ARCH_TM that an ABI variant can be supported by | |
3072 | overriding definitions in this file. */ | |
3073 | if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
3074 | fprintf_filtered | |
3075 | (gdb_stderr, | |
3076 | "A handler for the ABI variant \"%s\" is not built into this " | |
3077 | "configuration of GDB. " | |
3078 | "Attempting to continue with the default ARM settings", | |
3079 | arm_abi_names[arm_abi]); | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | /* Now we have tuned the configuration, set a few final things, | |
3084 | based on what the OS ABI has told us. */ | |
3085 | ||
9df628e0 RE |
3086 | if (tdep->jb_pc >= 0) |
3087 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3088 | ||
08216dd7 RE |
3089 | /* Floating point sizes and format. */ |
3090 | switch (info.byte_order) | |
3091 | { | |
3092 | case BFD_ENDIAN_BIG: | |
3093 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
3094 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
3095 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
3096 | ||
3097 | break; | |
3098 | ||
3099 | case BFD_ENDIAN_LITTLE: | |
3100 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
3101 | if (tdep->fp_model == ARM_FLOAT_VFP | |
3102 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
3103 | { | |
3104 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
3105 | set_gdbarch_long_double_format (gdbarch, | |
3106 | &floatformat_ieee_double_little); | |
3107 | } | |
3108 | else | |
3109 | { | |
3110 | set_gdbarch_double_format | |
3111 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3112 | set_gdbarch_long_double_format | |
3113 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3114 | } | |
3115 | break; | |
3116 | ||
3117 | default: | |
3118 | internal_error (__FILE__, __LINE__, | |
3119 | "arm_gdbarch_init: bad byte order for float format"); | |
3120 | } | |
3121 | ||
97e03143 | 3122 | /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still |
34e8f22d RE |
3123 | references the old architecture vector, not the one we are |
3124 | building here. */ | |
3125 | if (prologue_cache.saved_regs != NULL) | |
3126 | xfree (prologue_cache.saved_regs); | |
3127 | ||
a0abec03 AC |
3128 | /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still |
3129 | references the old architecture vector, not the one we are | |
3130 | building here. */ | |
34e8f22d RE |
3131 | prologue_cache.saved_regs = (CORE_ADDR *) |
3132 | xcalloc (1, (sizeof (CORE_ADDR) | |
29673b29 AC |
3133 | * (gdbarch_num_regs (gdbarch) |
3134 | + gdbarch_num_pseudo_regs (gdbarch)))); | |
39bbf761 RE |
3135 | |
3136 | return gdbarch; | |
3137 | } | |
3138 | ||
97e03143 RE |
3139 | static void |
3140 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3141 | { | |
3142 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3143 | ||
3144 | if (tdep == NULL) | |
3145 | return; | |
3146 | ||
3147 | if (tdep->abi_name != NULL) | |
3148 | fprintf_unfiltered (file, "arm_dump_tdep: ABI = %s\n", tdep->abi_name); | |
3149 | else | |
3150 | internal_error (__FILE__, __LINE__, | |
3151 | "arm_dump_tdep: illegal setting of tdep->arm_abi (%d)", | |
3152 | (int) tdep->arm_abi); | |
3153 | ||
3154 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", | |
3155 | (unsigned long) tdep->lowest_pc); | |
3156 | } | |
3157 | ||
3158 | static void | |
3159 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
3160 | struct gdbarch *gdbarch) | |
3161 | { | |
3162 | /* Place-holder. */ | |
3163 | } | |
3164 | ||
3165 | static void | |
3166 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
3167 | struct gdbarch *gdbarch) | |
3168 | { | |
3169 | /* Place-holder. */ | |
3170 | } | |
3171 | ||
3172 | static void | |
3173 | arm_init_abi_apcs (struct gdbarch_info info, | |
3174 | struct gdbarch *gdbarch) | |
3175 | { | |
3176 | /* Place-holder. */ | |
3177 | } | |
3178 | ||
c906108c | 3179 | void |
ed9a39eb | 3180 | _initialize_arm_tdep (void) |
c906108c | 3181 | { |
bc90b915 FN |
3182 | struct ui_file *stb; |
3183 | long length; | |
96baa820 | 3184 | struct cmd_list_element *new_cmd; |
53904c9e AC |
3185 | const char *setname; |
3186 | const char *setdesc; | |
3187 | const char **regnames; | |
bc90b915 FN |
3188 | int numregs, i, j; |
3189 | static char *helptext; | |
085dd6e6 | 3190 | |
39bbf761 | 3191 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3192 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3193 | ||
3194 | /* Register some ABI variants for embedded systems. */ | |
3195 | arm_gdbarch_register_os_abi (ARM_ABI_EABI_V1, arm_init_abi_eabi_v1); | |
3196 | arm_gdbarch_register_os_abi (ARM_ABI_EABI_V2, arm_init_abi_eabi_v2); | |
3197 | arm_gdbarch_register_os_abi (ARM_ABI_APCS, arm_init_abi_apcs); | |
39bbf761 | 3198 | |
c906108c | 3199 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3200 | |
94c30b78 | 3201 | /* Get the number of possible sets of register names defined in opcodes. */ |
bc90b915 FN |
3202 | num_flavor_options = get_arm_regname_num_options (); |
3203 | ||
94c30b78 | 3204 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3205 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3206 | |
94c30b78 | 3207 | /* Begin creating the help text. */ |
bc90b915 FN |
3208 | stb = mem_fileopen (); |
3209 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3210 | The valid values are:\n"); | |
ed9a39eb | 3211 | |
94c30b78 | 3212 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
bc90b915 FN |
3213 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
3214 | for (i = 0; i < num_flavor_options; i++) | |
3215 | { | |
3216 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3217 | valid_flavors[i] = setname; |
bc90b915 FN |
3218 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3219 | setdesc); | |
94c30b78 | 3220 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3221 | if (!strcmp (setname, "std")) |
3222 | { | |
53904c9e | 3223 | disassembly_flavor = setname; |
bc90b915 FN |
3224 | current_option = i; |
3225 | for (j = 0; j < numregs; j++) | |
3226 | arm_register_names[j] = (char *) regnames[j]; | |
3227 | set_arm_regname_option (i); | |
3228 | } | |
3229 | } | |
94c30b78 | 3230 | /* Mark the end of valid options. */ |
bc90b915 | 3231 | valid_flavors[num_flavor_options] = NULL; |
c906108c | 3232 | |
94c30b78 | 3233 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3234 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3235 | helptext = ui_file_xstrdup (stb, &length); | |
3236 | ui_file_delete (stb); | |
ed9a39eb | 3237 | |
94c30b78 | 3238 | /* Add the disassembly-flavor command. */ |
96baa820 | 3239 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3240 | valid_flavors, |
1ed2a135 | 3241 | &disassembly_flavor, |
bc90b915 | 3242 | helptext, |
ed9a39eb | 3243 | &setlist); |
9f60d481 | 3244 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3245 | add_show_from_set (new_cmd, &showlist); |
3246 | ||
c906108c SS |
3247 | /* ??? Maybe this should be a boolean. */ |
3248 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3249 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3250 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3251 | &showlist); |
c906108c | 3252 | |
94c30b78 | 3253 | /* Add the deprecated "othernames" command. */ |
bc90b915 FN |
3254 | |
3255 | add_com ("othernames", class_obscure, arm_othernames, | |
3256 | "Switch to the next set of register names."); | |
c3b4394c RE |
3257 | |
3258 | /* Fill in the prologue_cache fields. */ | |
34e8f22d | 3259 | prologue_cache.saved_regs = NULL; |
c3b4394c RE |
3260 | prologue_cache.extra_info = (struct frame_extra_info *) |
3261 | xcalloc (1, sizeof (struct frame_extra_info)); | |
c906108c | 3262 | } |