Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
197e01b6 | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, |
25224166 MK |
4 | 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
22 | Boston, MA 02110-1301, USA. */ | |
c906108c | 23 | |
34e8f22d RE |
24 | #include <ctype.h> /* XXX for isupper () */ |
25 | ||
c906108c SS |
26 | #include "defs.h" |
27 | #include "frame.h" | |
28 | #include "inferior.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
c906108c | 31 | #include "gdb_string.h" |
afd7eef0 | 32 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 33 | #include "regcache.h" |
d16aafd8 | 34 | #include "doublest.h" |
fd0407d6 | 35 | #include "value.h" |
34e8f22d | 36 | #include "arch-utils.h" |
4be87837 | 37 | #include "osabi.h" |
eb5492fa DJ |
38 | #include "frame-unwind.h" |
39 | #include "frame-base.h" | |
40 | #include "trad-frame.h" | |
842e1f1e DJ |
41 | #include "objfiles.h" |
42 | #include "dwarf2-frame.h" | |
e4c16157 | 43 | #include "gdbtypes.h" |
34e8f22d RE |
44 | |
45 | #include "arm-tdep.h" | |
26216b98 | 46 | #include "gdb/sim-arm.h" |
34e8f22d | 47 | |
082fc60d RE |
48 | #include "elf-bfd.h" |
49 | #include "coff/internal.h" | |
97e03143 | 50 | #include "elf/arm.h" |
c906108c | 51 | |
26216b98 AC |
52 | #include "gdb_assert.h" |
53 | ||
6529d2dd AC |
54 | static int arm_debug; |
55 | ||
082fc60d RE |
56 | /* Macros for setting and testing a bit in a minimal symbol that marks |
57 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 58 | is used for this purpose. |
082fc60d RE |
59 | |
60 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 61 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
62 | |
63 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
64 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
65 | | 0x80000000) | |
66 | ||
67 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
68 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
69 | ||
afd7eef0 RE |
70 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
71 | static struct cmd_list_element *setarmcmdlist = NULL; | |
72 | static struct cmd_list_element *showarmcmdlist = NULL; | |
73 | ||
fd50bc42 RE |
74 | /* The type of floating-point to use. Keep this in sync with enum |
75 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
76 | static const char *fp_model_strings[] = | |
77 | { | |
78 | "auto", | |
79 | "softfpa", | |
80 | "fpa", | |
81 | "softvfp", | |
28e97307 DJ |
82 | "vfp", |
83 | NULL | |
fd50bc42 RE |
84 | }; |
85 | ||
86 | /* A variable that can be configured by the user. */ | |
87 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
88 | static const char *current_fp_model = "auto"; | |
89 | ||
28e97307 DJ |
90 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
91 | static const char *arm_abi_strings[] = | |
92 | { | |
93 | "auto", | |
94 | "APCS", | |
95 | "AAPCS", | |
96 | NULL | |
97 | }; | |
98 | ||
99 | /* A variable that can be configured by the user. */ | |
100 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
101 | static const char *arm_abi_string = "auto"; | |
102 | ||
94c30b78 | 103 | /* Number of different reg name sets (options). */ |
afd7eef0 | 104 | static int num_disassembly_options; |
bc90b915 FN |
105 | |
106 | /* We have more registers than the disassembler as gdb can print the value | |
107 | of special registers as well. | |
108 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 109 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 110 | |
94c30b78 | 111 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 112 | static char * arm_register_name_strings[] = |
da59e081 JM |
113 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
114 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
115 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
116 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
117 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
118 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 119 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 120 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 121 | |
afd7eef0 RE |
122 | /* Valid register name styles. */ |
123 | static const char **valid_disassembly_styles; | |
ed9a39eb | 124 | |
afd7eef0 RE |
125 | /* Disassembly style to use. Default to "std" register names. */ |
126 | static const char *disassembly_style; | |
94c30b78 | 127 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 128 | static int current_option; |
96baa820 | 129 | |
ed9a39eb | 130 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
131 | style. */ |
132 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 133 | struct cmd_list_element *); |
afd7eef0 | 134 | static void set_disassembly_style (void); |
ed9a39eb | 135 | |
b508a996 RE |
136 | static void convert_from_extended (const struct floatformat *, const void *, |
137 | void *); | |
138 | static void convert_to_extended (const struct floatformat *, void *, | |
139 | const void *); | |
ed9a39eb | 140 | |
9b8d791a | 141 | struct arm_prologue_cache |
c3b4394c | 142 | { |
eb5492fa DJ |
143 | /* The stack pointer at the time this frame was created; i.e. the |
144 | caller's stack pointer when this function was called. It is used | |
145 | to identify this frame. */ | |
146 | CORE_ADDR prev_sp; | |
147 | ||
148 | /* The frame base for this frame is just prev_sp + frame offset - | |
149 | frame size. FRAMESIZE is the size of this stack frame, and | |
150 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
151 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
152 | ||
c3b4394c RE |
153 | int framesize; |
154 | int frameoffset; | |
eb5492fa DJ |
155 | |
156 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 157 | int framereg; |
eb5492fa DJ |
158 | |
159 | /* Saved register offsets. */ | |
160 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 161 | }; |
ed9a39eb | 162 | |
bc90b915 FN |
163 | /* Addresses for calling Thumb functions have the bit 0 set. |
164 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
165 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
166 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
167 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
168 | ||
94c30b78 | 169 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
170 | |
171 | int arm_apcs_32 = 1; | |
172 | ||
ed9a39eb JM |
173 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
174 | function. */ | |
c906108c | 175 | |
34e8f22d | 176 | int |
2a451106 | 177 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 178 | { |
c5aa993b | 179 | struct minimal_symbol *sym; |
c906108c | 180 | |
ed9a39eb | 181 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
182 | if (IS_THUMB_ADDR (memaddr)) |
183 | return 1; | |
184 | ||
ed9a39eb | 185 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
186 | sym = lookup_minimal_symbol_by_pc (memaddr); |
187 | if (sym) | |
188 | { | |
c5aa993b | 189 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
190 | } |
191 | else | |
ed9a39eb JM |
192 | { |
193 | return 0; | |
194 | } | |
c906108c SS |
195 | } |
196 | ||
181c1381 | 197 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 198 | static CORE_ADDR |
ed9a39eb | 199 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 200 | { |
a3a2ee65 JT |
201 | if (arm_apcs_32) |
202 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 203 | else |
a3a2ee65 | 204 | return (val & 0x03fffffc); |
c906108c SS |
205 | } |
206 | ||
181c1381 RE |
207 | /* When reading symbols, we need to zap the low bit of the address, |
208 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 209 | static CORE_ADDR |
181c1381 RE |
210 | arm_smash_text_address (CORE_ADDR val) |
211 | { | |
212 | return val & ~1; | |
213 | } | |
214 | ||
34e8f22d RE |
215 | /* Immediately after a function call, return the saved pc. Can't |
216 | always go through the frames for this because on some machines the | |
217 | new frame is not set up until the new function executes some | |
218 | instructions. */ | |
219 | ||
220 | static CORE_ADDR | |
ed9a39eb | 221 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 222 | { |
34e8f22d | 223 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
224 | } |
225 | ||
226 | /* A typical Thumb prologue looks like this: | |
c5aa993b JM |
227 | push {r7, lr} |
228 | add sp, sp, #-28 | |
229 | add r7, sp, #12 | |
c906108c | 230 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
231 | mov r7, sp |
232 | ||
233 | or like this: | |
234 | push {r7, lr} | |
235 | mov r7, sp | |
236 | sub sp, #12 | |
237 | ||
238 | or, on tpcs, like this: | |
239 | sub sp,#16 | |
240 | push {r7, lr} | |
241 | (many instructions) | |
242 | mov r7, sp | |
243 | sub sp, #12 | |
244 | ||
245 | There is always one instruction of three classes: | |
246 | 1 - push | |
247 | 2 - setting of r7 | |
248 | 3 - adjusting of sp | |
249 | ||
250 | When we have found at least one of each class we are done with the prolog. | |
251 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 252 | */ |
c906108c SS |
253 | |
254 | static CORE_ADDR | |
c7885828 | 255 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
256 | { |
257 | CORE_ADDR current_pc; | |
da3c6d4a MS |
258 | /* findmask: |
259 | bit 0 - push { rlist } | |
260 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
261 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
262 | */ | |
263 | int findmask = 0; | |
264 | ||
94c30b78 MS |
265 | for (current_pc = pc; |
266 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 267 | current_pc += 2) |
c906108c SS |
268 | { |
269 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
270 | ||
94c30b78 | 271 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 272 | { |
94c30b78 | 273 | findmask |= 1; /* push found */ |
da59e081 | 274 | } |
da3c6d4a MS |
275 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
276 | sub sp, #simm */ | |
da59e081 | 277 | { |
94c30b78 | 278 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
279 | continue; |
280 | else | |
94c30b78 | 281 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
282 | } |
283 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
284 | { | |
94c30b78 | 285 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
286 | } |
287 | else if (insn == 0x466f) /* mov r7, sp */ | |
288 | { | |
94c30b78 | 289 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 290 | } |
3d74b771 FF |
291 | else if (findmask == (4+2+1)) |
292 | { | |
da3c6d4a MS |
293 | /* We have found one of each type of prologue instruction */ |
294 | break; | |
3d74b771 | 295 | } |
da59e081 | 296 | else |
94c30b78 | 297 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 298 | instruction from outside the prolog scheduled here for |
94c30b78 | 299 | optimization. */ |
da3c6d4a | 300 | continue; |
c906108c SS |
301 | } |
302 | ||
303 | return current_pc; | |
304 | } | |
305 | ||
da3c6d4a MS |
306 | /* Advance the PC across any function entry prologue instructions to |
307 | reach some "real" code. | |
34e8f22d RE |
308 | |
309 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 310 | prologue: |
c906108c | 311 | |
c5aa993b JM |
312 | mov ip, sp |
313 | [stmfd sp!, {a1,a2,a3,a4}] | |
314 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
315 | [stfe f7, [sp, #-12]!] |
316 | [stfe f6, [sp, #-12]!] | |
317 | [stfe f5, [sp, #-12]!] | |
318 | [stfe f4, [sp, #-12]!] | |
319 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 320 | |
34e8f22d | 321 | static CORE_ADDR |
ed9a39eb | 322 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
323 | { |
324 | unsigned long inst; | |
325 | CORE_ADDR skip_pc; | |
b8d5e71d | 326 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 327 | char *func_name; |
c906108c SS |
328 | struct symtab_and_line sal; |
329 | ||
848cfffb | 330 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 331 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
332 | return pc; |
333 | ||
96baa820 | 334 | /* See what the symbol table says. */ |
ed9a39eb | 335 | |
50f6fb4b | 336 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 337 | { |
50f6fb4b CV |
338 | struct symbol *sym; |
339 | ||
340 | /* Found a function. */ | |
176620f1 | 341 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
342 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
343 | { | |
94c30b78 | 344 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
345 | sal = find_pc_line (func_addr, 0); |
346 | if ((sal.line != 0) && (sal.end < func_end)) | |
347 | return sal.end; | |
348 | } | |
c906108c SS |
349 | } |
350 | ||
351 | /* Check if this is Thumb code. */ | |
352 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 353 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
354 | |
355 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 356 | by disassembling the instructions. */ |
c906108c | 357 | |
b8d5e71d MS |
358 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
359 | if (func_end == 0 || func_end > pc + 64) | |
360 | func_end = pc + 64; | |
c906108c | 361 | |
b8d5e71d | 362 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 363 | { |
1c5bada0 | 364 | inst = read_memory_unsigned_integer (skip_pc, 4); |
f43845b3 | 365 | |
b8d5e71d MS |
366 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
367 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
368 | continue; | |
c906108c | 369 | |
28cd8767 JG |
370 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
371 | continue; | |
372 | ||
373 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
374 | continue; | |
375 | ||
b8d5e71d MS |
376 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
377 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
378 | continue; | |
c906108c | 379 | |
b8d5e71d MS |
380 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
381 | continue; | |
c906108c | 382 | |
b8d5e71d MS |
383 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
384 | continue; | |
11d3b27d | 385 | |
b8d5e71d MS |
386 | /* Any insns after this point may float into the code, if it makes |
387 | for better instruction scheduling, so we skip them only if we | |
388 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 389 | |
b8d5e71d MS |
390 | /* We may have either one sfmfd instruction here, or several stfe |
391 | insns, depending on the version of floating point code we | |
392 | support. */ | |
393 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
394 | continue; | |
395 | ||
396 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
397 | continue; | |
398 | ||
399 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
400 | continue; | |
401 | ||
402 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
403 | continue; | |
404 | ||
405 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
406 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
407 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
408 | continue; | |
409 | ||
410 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
411 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
412 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
413 | continue; | |
414 | ||
415 | /* Un-recognized instruction; stop scanning. */ | |
416 | break; | |
f43845b3 | 417 | } |
c906108c | 418 | |
b8d5e71d | 419 | return skip_pc; /* End of prologue */ |
c906108c | 420 | } |
94c30b78 | 421 | |
c5aa993b | 422 | /* *INDENT-OFF* */ |
c906108c SS |
423 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
424 | This function decodes a Thumb function prologue to determine: | |
425 | 1) the size of the stack frame | |
426 | 2) which registers are saved on it | |
427 | 3) the offsets of saved regs | |
428 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 429 | |
da59e081 JM |
430 | A typical Thumb function prologue would create this stack frame |
431 | (offsets relative to FP) | |
c906108c SS |
432 | old SP -> 24 stack parameters |
433 | 20 LR | |
434 | 16 R7 | |
435 | R7 -> 0 local variables (16 bytes) | |
436 | SP -> -12 additional stack space (12 bytes) | |
437 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
438 | 12 bytes. The frame register is R7. |
439 | ||
da3c6d4a MS |
440 | The comments for thumb_skip_prolog() describe the algorithm we use |
441 | to detect the end of the prolog. */ | |
c5aa993b JM |
442 | /* *INDENT-ON* */ |
443 | ||
c906108c | 444 | static void |
eb5492fa | 445 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
446 | { |
447 | CORE_ADDR prologue_start; | |
448 | CORE_ADDR prologue_end; | |
449 | CORE_ADDR current_pc; | |
94c30b78 | 450 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
451 | int saved_reg[16]; |
452 | /* findmask: | |
453 | bit 0 - push { rlist } | |
454 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
455 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
456 | */ | |
457 | int findmask = 0; | |
c5aa993b | 458 | int i; |
c906108c | 459 | |
eb5492fa | 460 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
461 | { |
462 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
463 | ||
94c30b78 | 464 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 465 | prologue_end = prev_pc; |
c906108c | 466 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 467 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
468 | } |
469 | else | |
f7060f85 DJ |
470 | /* We're in the boondocks: we have no idea where the start of the |
471 | function is. */ | |
472 | return; | |
c906108c | 473 | |
eb5492fa | 474 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
475 | |
476 | /* Initialize the saved register map. When register H is copied to | |
477 | register L, we will put H in saved_reg[L]. */ | |
478 | for (i = 0; i < 16; i++) | |
479 | saved_reg[i] = i; | |
480 | ||
481 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
482 | frame pointer, adjust the stack pointer, and save registers. |
483 | Do this until all basic prolog instructions are found. */ | |
c906108c | 484 | |
9b8d791a | 485 | cache->framesize = 0; |
da59e081 JM |
486 | for (current_pc = prologue_start; |
487 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
488 | current_pc += 2) | |
c906108c SS |
489 | { |
490 | unsigned short insn; | |
491 | int regno; | |
492 | int offset; | |
493 | ||
494 | insn = read_memory_unsigned_integer (current_pc, 2); | |
495 | ||
c5aa993b | 496 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 497 | { |
da59e081 | 498 | int mask; |
94c30b78 | 499 | findmask |= 1; /* push found */ |
c906108c SS |
500 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
501 | whether to save LR (R14). */ | |
da59e081 | 502 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 503 | |
b8d5e71d | 504 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 505 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 506 | if (mask & (1 << regno)) |
c5aa993b | 507 | { |
9b8d791a | 508 | cache->framesize += 4; |
eb5492fa | 509 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
510 | /* Reset saved register map. */ |
511 | saved_reg[regno] = regno; | |
c906108c SS |
512 | } |
513 | } | |
da3c6d4a MS |
514 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
515 | sub sp, #simm */ | |
c906108c | 516 | { |
b8d5e71d | 517 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
518 | continue; |
519 | else | |
94c30b78 | 520 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 521 | |
94c30b78 MS |
522 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
523 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 524 | { |
9b8d791a | 525 | cache->frameoffset += offset; |
da59e081 JM |
526 | offset = -offset; |
527 | } | |
9b8d791a | 528 | cache->framesize -= offset; |
c906108c SS |
529 | } |
530 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
531 | { | |
94c30b78 | 532 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 533 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 534 | /* get scaled offset */ |
9b8d791a | 535 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 536 | } |
da59e081 | 537 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 538 | { |
94c30b78 | 539 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
540 | cache->framereg = THUMB_FP_REGNUM; |
541 | cache->frameoffset = 0; | |
34e8f22d | 542 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
543 | } |
544 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
545 | { | |
da3c6d4a | 546 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 547 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 548 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
549 | } |
550 | else | |
da3c6d4a MS |
551 | /* Something in the prolog that we don't care about or some |
552 | instruction from outside the prolog scheduled here for | |
553 | optimization. */ | |
554 | continue; | |
c906108c SS |
555 | } |
556 | } | |
557 | ||
ed9a39eb | 558 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
559 | 1) the size of the stack frame |
560 | 2) which registers are saved on it | |
561 | 3) the offsets of saved regs | |
562 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
563 | This information is stored in the "extra" fields of the frame_info. |
564 | ||
96baa820 JM |
565 | There are two basic forms for the ARM prologue. The fixed argument |
566 | function call will look like: | |
ed9a39eb JM |
567 | |
568 | mov ip, sp | |
569 | stmfd sp!, {fp, ip, lr, pc} | |
570 | sub fp, ip, #4 | |
571 | [sub sp, sp, #4] | |
96baa820 | 572 | |
c906108c | 573 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
574 | IP -> 4 (caller's stack) |
575 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
576 | -4 LR (return address in caller) | |
577 | -8 IP (copy of caller's SP) | |
578 | -12 FP (caller's FP) | |
579 | SP -> -28 Local variables | |
580 | ||
c906108c | 581 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
582 | 28 bytes. The stmfd call can also save any of the vN registers it |
583 | plans to use, which increases the frame size accordingly. | |
584 | ||
585 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
586 | because the ARM Store instructions always store PC + 8 when you read | |
587 | the PC register. | |
ed9a39eb | 588 | |
96baa820 JM |
589 | A variable argument function call will look like: |
590 | ||
ed9a39eb JM |
591 | mov ip, sp |
592 | stmfd sp!, {a1, a2, a3, a4} | |
593 | stmfd sp!, {fp, ip, lr, pc} | |
594 | sub fp, ip, #20 | |
595 | ||
96baa820 | 596 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
597 | IP -> 20 (caller's stack) |
598 | 16 A4 | |
599 | 12 A3 | |
600 | 8 A2 | |
601 | 4 A1 | |
602 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
603 | -4 LR (return address in caller) | |
604 | -8 IP (copy of caller's SP) | |
605 | -12 FP (caller's FP) | |
606 | SP -> -28 Local variables | |
96baa820 JM |
607 | |
608 | The frame size would thus be 48 bytes, and the frame offset would be | |
609 | 28 bytes. | |
610 | ||
611 | There is another potential complication, which is that the optimizer | |
612 | will try to separate the store of fp in the "stmfd" instruction from | |
613 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
614 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
615 | ||
616 | Also, note, the original version of the ARM toolchain claimed that there | |
617 | should be an | |
618 | ||
619 | instruction at the end of the prologue. I have never seen GCC produce | |
620 | this, and the ARM docs don't mention it. We still test for it below in | |
621 | case it happens... | |
ed9a39eb JM |
622 | |
623 | */ | |
c906108c SS |
624 | |
625 | static void | |
eb5492fa | 626 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 627 | { |
28cd8767 | 628 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 629 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 630 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 631 | |
c906108c | 632 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
633 | cache->framereg = ARM_SP_REGNUM; |
634 | cache->framesize = 0; | |
635 | cache->frameoffset = 0; | |
c906108c SS |
636 | |
637 | /* Check for Thumb prologue. */ | |
eb5492fa | 638 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 639 | { |
eb5492fa | 640 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
641 | return; |
642 | } | |
643 | ||
644 | /* Find the function prologue. If we can't find the function in | |
645 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 646 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 647 | { |
2a451106 KB |
648 | /* One way to find the end of the prologue (which works well |
649 | for unoptimized code) is to do the following: | |
650 | ||
651 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
652 | ||
653 | if (sal.line == 0) | |
eb5492fa | 654 | prologue_end = prev_pc; |
2a451106 KB |
655 | else if (sal.end < prologue_end) |
656 | prologue_end = sal.end; | |
657 | ||
658 | This mechanism is very accurate so long as the optimizer | |
659 | doesn't move any instructions from the function body into the | |
660 | prologue. If this happens, sal.end will be the last | |
661 | instruction in the first hunk of prologue code just before | |
662 | the first instruction that the scheduler has moved from | |
663 | the body to the prologue. | |
664 | ||
665 | In order to make sure that we scan all of the prologue | |
666 | instructions, we use a slightly less accurate mechanism which | |
667 | may scan more than necessary. To help compensate for this | |
668 | lack of accuracy, the prologue scanning loop below contains | |
669 | several clauses which'll cause the loop to terminate early if | |
670 | an implausible prologue instruction is encountered. | |
671 | ||
672 | The expression | |
673 | ||
674 | prologue_start + 64 | |
675 | ||
676 | is a suitable endpoint since it accounts for the largest | |
677 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 678 | the scheduler. */ |
2a451106 KB |
679 | |
680 | if (prologue_end > prologue_start + 64) | |
681 | { | |
94c30b78 | 682 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 683 | } |
c906108c SS |
684 | } |
685 | else | |
686 | { | |
eb5492fa DJ |
687 | /* We have no symbol information. Our only option is to assume this |
688 | function has a standard stack frame and the normal frame register. | |
689 | Then, we can find the value of our frame pointer on entrance to | |
690 | the callee (or at the present moment if this is the innermost frame). | |
691 | The value stored there should be the address of the stmfd + 8. */ | |
692 | CORE_ADDR frame_loc; | |
693 | LONGEST return_value; | |
694 | ||
695 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
696 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
697 | return; |
698 | else | |
699 | { | |
700 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 701 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 702 | } |
c906108c SS |
703 | } |
704 | ||
eb5492fa DJ |
705 | if (prev_pc < prologue_end) |
706 | prologue_end = prev_pc; | |
707 | ||
c906108c | 708 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 709 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 710 | |
96baa820 JM |
711 | Be careful, however, and if it doesn't look like a prologue, |
712 | don't try to scan it. If, for instance, a frameless function | |
713 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 714 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
715 | and other operations that rely on a knowledge of the stack |
716 | traceback. | |
717 | ||
718 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 719 | if we don't see this as the first insn, we will stop. |
c906108c | 720 | |
f43845b3 MS |
721 | [Note: This doesn't seem to be true any longer, so it's now an |
722 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 723 | |
f43845b3 MS |
724 | [Note further: The "mov ip,sp" only seems to be missing in |
725 | frameless functions at optimization level "-O2" or above, | |
726 | in which case it is often (but not always) replaced by | |
b8d5e71d | 727 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 728 | |
28cd8767 | 729 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 730 | |
94c30b78 MS |
731 | for (current_pc = prologue_start; |
732 | current_pc < prologue_end; | |
f43845b3 | 733 | current_pc += 4) |
96baa820 | 734 | { |
d4473757 KB |
735 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
736 | ||
94c30b78 | 737 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 738 | { |
28cd8767 JG |
739 | ip_offset = 0; |
740 | continue; | |
741 | } | |
742 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
743 | { | |
744 | unsigned imm = insn & 0xff; /* immediate value */ | |
745 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
746 | imm = (imm >> rot) | (imm << (32 - rot)); | |
747 | ip_offset = imm; | |
748 | continue; | |
749 | } | |
750 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
751 | { | |
752 | unsigned imm = insn & 0xff; /* immediate value */ | |
753 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
754 | imm = (imm >> rot) | (imm << (32 - rot)); | |
755 | ip_offset = -imm; | |
f43845b3 MS |
756 | continue; |
757 | } | |
94c30b78 | 758 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 759 | { |
e28a332c JG |
760 | sp_offset -= 4; |
761 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
762 | continue; |
763 | } | |
764 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
765 | /* stmfd sp!, {..., fp, ip, lr, pc} |
766 | or | |
767 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 768 | { |
d4473757 | 769 | int mask = insn & 0xffff; |
ed9a39eb | 770 | |
94c30b78 | 771 | /* Calculate offsets of saved registers. */ |
34e8f22d | 772 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
773 | if (mask & (1 << regno)) |
774 | { | |
775 | sp_offset -= 4; | |
eb5492fa | 776 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
777 | } |
778 | } | |
b8d5e71d MS |
779 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
780 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
781 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
782 | { | |
783 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
784 | continue; | |
785 | } | |
786 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
787 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
788 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
789 | { |
790 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
791 | continue; | |
792 | } | |
d4473757 KB |
793 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
794 | { | |
94c30b78 MS |
795 | unsigned imm = insn & 0xff; /* immediate value */ |
796 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 797 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 798 | fp_offset = -imm + ip_offset; |
9b8d791a | 799 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
800 | } |
801 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
802 | { | |
94c30b78 MS |
803 | unsigned imm = insn & 0xff; /* immediate value */ |
804 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
805 | imm = (imm >> rot) | (imm << (32 - rot)); |
806 | sp_offset -= imm; | |
807 | } | |
808 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
809 | { | |
810 | sp_offset -= 12; | |
34e8f22d | 811 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 812 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
813 | } |
814 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
815 | { | |
816 | int n_saved_fp_regs; | |
817 | unsigned int fp_start_reg, fp_bound_reg; | |
818 | ||
94c30b78 | 819 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 820 | { |
d4473757 KB |
821 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
822 | n_saved_fp_regs = 3; | |
823 | else | |
824 | n_saved_fp_regs = 1; | |
96baa820 | 825 | } |
d4473757 | 826 | else |
96baa820 | 827 | { |
d4473757 KB |
828 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
829 | n_saved_fp_regs = 2; | |
830 | else | |
831 | n_saved_fp_regs = 4; | |
96baa820 | 832 | } |
d4473757 | 833 | |
34e8f22d | 834 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
835 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
836 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
837 | { |
838 | sp_offset -= 12; | |
eb5492fa | 839 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 840 | } |
c906108c | 841 | } |
d4473757 | 842 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 843 | break; /* Condition not true, exit early */ |
b8d5e71d | 844 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 845 | break; /* Don't scan past a block load */ |
d4473757 KB |
846 | else |
847 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 848 | so we just skip what we don't recognize. */ |
d4473757 | 849 | continue; |
c906108c SS |
850 | } |
851 | ||
94c30b78 MS |
852 | /* The frame size is just the negative of the offset (from the |
853 | original SP) of the last thing thing we pushed on the stack. | |
854 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
855 | cache->framesize = -sp_offset; |
856 | if (cache->framereg == ARM_FP_REGNUM) | |
857 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 858 | else |
9b8d791a | 859 | cache->frameoffset = 0; |
c906108c SS |
860 | } |
861 | ||
eb5492fa DJ |
862 | static struct arm_prologue_cache * |
863 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 864 | { |
eb5492fa DJ |
865 | int reg; |
866 | struct arm_prologue_cache *cache; | |
867 | CORE_ADDR unwound_fp; | |
c5aa993b | 868 | |
eb5492fa DJ |
869 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
870 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 871 | |
eb5492fa | 872 | arm_scan_prologue (next_frame, cache); |
848cfffb | 873 | |
eb5492fa DJ |
874 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
875 | if (unwound_fp == 0) | |
876 | return cache; | |
c906108c | 877 | |
eb5492fa | 878 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 879 | |
eb5492fa DJ |
880 | /* Calculate actual addresses of saved registers using offsets |
881 | determined by arm_scan_prologue. */ | |
882 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 883 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
884 | cache->saved_regs[reg].addr += cache->prev_sp; |
885 | ||
886 | return cache; | |
c906108c SS |
887 | } |
888 | ||
eb5492fa DJ |
889 | /* Our frame ID for a normal frame is the current function's starting PC |
890 | and the caller's SP when we were called. */ | |
c906108c | 891 | |
148754e5 | 892 | static void |
eb5492fa DJ |
893 | arm_prologue_this_id (struct frame_info *next_frame, |
894 | void **this_cache, | |
895 | struct frame_id *this_id) | |
c906108c | 896 | { |
eb5492fa DJ |
897 | struct arm_prologue_cache *cache; |
898 | struct frame_id id; | |
899 | CORE_ADDR func; | |
f079148d | 900 | |
eb5492fa DJ |
901 | if (*this_cache == NULL) |
902 | *this_cache = arm_make_prologue_cache (next_frame); | |
903 | cache = *this_cache; | |
2a451106 | 904 | |
eb5492fa | 905 | func = frame_func_unwind (next_frame); |
2a451106 | 906 | |
eb5492fa DJ |
907 | /* This is meant to halt the backtrace at "_start". Make sure we |
908 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 909 | if (func <= LOWEST_PC) |
eb5492fa | 910 | return; |
5a203e44 | 911 | |
eb5492fa DJ |
912 | /* If we've hit a wall, stop. */ |
913 | if (cache->prev_sp == 0) | |
914 | return; | |
24de872b | 915 | |
eb5492fa | 916 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 917 | *this_id = id; |
c906108c SS |
918 | } |
919 | ||
eb5492fa DJ |
920 | static void |
921 | arm_prologue_prev_register (struct frame_info *next_frame, | |
922 | void **this_cache, | |
923 | int prev_regnum, | |
924 | int *optimized, | |
925 | enum lval_type *lvalp, | |
926 | CORE_ADDR *addrp, | |
927 | int *realnump, | |
9af75ef6 | 928 | gdb_byte *valuep) |
24de872b DJ |
929 | { |
930 | struct arm_prologue_cache *cache; | |
931 | ||
eb5492fa DJ |
932 | if (*this_cache == NULL) |
933 | *this_cache = arm_make_prologue_cache (next_frame); | |
934 | cache = *this_cache; | |
24de872b | 935 | |
eb5492fa DJ |
936 | /* If we are asked to unwind the PC, then we need to return the LR |
937 | instead. The saved value of PC points into this frame's | |
938 | prologue, not the next frame's resume location. */ | |
939 | if (prev_regnum == ARM_PC_REGNUM) | |
940 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 941 | |
eb5492fa DJ |
942 | /* SP is generally not saved to the stack, but this frame is |
943 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
944 | The value was already reconstructed into PREV_SP. */ | |
945 | if (prev_regnum == ARM_SP_REGNUM) | |
946 | { | |
947 | *lvalp = not_lval; | |
948 | if (valuep) | |
949 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
950 | return; | |
951 | } | |
952 | ||
1f67027d AC |
953 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
954 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
955 | } |
956 | ||
957 | struct frame_unwind arm_prologue_unwind = { | |
958 | NORMAL_FRAME, | |
959 | arm_prologue_this_id, | |
960 | arm_prologue_prev_register | |
961 | }; | |
962 | ||
963 | static const struct frame_unwind * | |
964 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
965 | { | |
966 | return &arm_prologue_unwind; | |
24de872b DJ |
967 | } |
968 | ||
909cf6ea DJ |
969 | static struct arm_prologue_cache * |
970 | arm_make_stub_cache (struct frame_info *next_frame) | |
971 | { | |
972 | int reg; | |
973 | struct arm_prologue_cache *cache; | |
974 | CORE_ADDR unwound_fp; | |
975 | ||
976 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
977 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
978 | ||
979 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
980 | ||
981 | return cache; | |
982 | } | |
983 | ||
984 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
985 | ||
986 | static void | |
987 | arm_stub_this_id (struct frame_info *next_frame, | |
988 | void **this_cache, | |
989 | struct frame_id *this_id) | |
990 | { | |
991 | struct arm_prologue_cache *cache; | |
992 | ||
993 | if (*this_cache == NULL) | |
994 | *this_cache = arm_make_stub_cache (next_frame); | |
995 | cache = *this_cache; | |
996 | ||
997 | *this_id = frame_id_build (cache->prev_sp, | |
998 | frame_pc_unwind (next_frame)); | |
999 | } | |
1000 | ||
1001 | struct frame_unwind arm_stub_unwind = { | |
1002 | NORMAL_FRAME, | |
1003 | arm_stub_this_id, | |
1004 | arm_prologue_prev_register | |
1005 | }; | |
1006 | ||
1007 | static const struct frame_unwind * | |
1008 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1009 | { | |
1010 | char dummy[4]; | |
1011 | ||
1012 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
1013 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
1014 | return &arm_stub_unwind; | |
1015 | ||
1016 | return NULL; | |
1017 | } | |
1018 | ||
24de872b | 1019 | static CORE_ADDR |
eb5492fa | 1020 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1021 | { |
1022 | struct arm_prologue_cache *cache; | |
1023 | ||
eb5492fa DJ |
1024 | if (*this_cache == NULL) |
1025 | *this_cache = arm_make_prologue_cache (next_frame); | |
1026 | cache = *this_cache; | |
1027 | ||
1028 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1029 | } |
1030 | ||
eb5492fa DJ |
1031 | struct frame_base arm_normal_base = { |
1032 | &arm_prologue_unwind, | |
1033 | arm_normal_frame_base, | |
1034 | arm_normal_frame_base, | |
1035 | arm_normal_frame_base | |
1036 | }; | |
1037 | ||
eb5492fa DJ |
1038 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1039 | dummy frame. The frame ID's base needs to match the TOS value | |
1040 | saved by save_dummy_frame_tos() and returned from | |
1041 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1042 | breakpoint. */ | |
c906108c | 1043 | |
eb5492fa DJ |
1044 | static struct frame_id |
1045 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1046 | { |
eb5492fa DJ |
1047 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1048 | frame_pc_unwind (next_frame)); | |
1049 | } | |
c3b4394c | 1050 | |
eb5492fa DJ |
1051 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1052 | be used to construct the previous frame's ID, after looking up the | |
1053 | containing function). */ | |
c3b4394c | 1054 | |
eb5492fa DJ |
1055 | static CORE_ADDR |
1056 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1057 | { | |
1058 | CORE_ADDR pc; | |
1059 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1060 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1061 | } | |
1062 | ||
1063 | static CORE_ADDR | |
1064 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1065 | { | |
1066 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1067 | } |
1068 | ||
2dd604e7 RE |
1069 | /* When arguments must be pushed onto the stack, they go on in reverse |
1070 | order. The code below implements a FILO (stack) to do this. */ | |
1071 | ||
1072 | struct stack_item | |
1073 | { | |
1074 | int len; | |
1075 | struct stack_item *prev; | |
1076 | void *data; | |
1077 | }; | |
1078 | ||
1079 | static struct stack_item * | |
1080 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1081 | { | |
1082 | struct stack_item *si; | |
1083 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1084 | si->data = xmalloc (len); |
2dd604e7 RE |
1085 | si->len = len; |
1086 | si->prev = prev; | |
1087 | memcpy (si->data, contents, len); | |
1088 | return si; | |
1089 | } | |
1090 | ||
1091 | static struct stack_item * | |
1092 | pop_stack_item (struct stack_item *si) | |
1093 | { | |
1094 | struct stack_item *dead = si; | |
1095 | si = si->prev; | |
1096 | xfree (dead->data); | |
1097 | xfree (dead); | |
1098 | return si; | |
1099 | } | |
1100 | ||
2af48f68 PB |
1101 | |
1102 | /* Return the alignment (in bytes) of the given type. */ | |
1103 | ||
1104 | static int | |
1105 | arm_type_align (struct type *t) | |
1106 | { | |
1107 | int n; | |
1108 | int align; | |
1109 | int falign; | |
1110 | ||
1111 | t = check_typedef (t); | |
1112 | switch (TYPE_CODE (t)) | |
1113 | { | |
1114 | default: | |
1115 | /* Should never happen. */ | |
1116 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1117 | return 4; | |
1118 | ||
1119 | case TYPE_CODE_PTR: | |
1120 | case TYPE_CODE_ENUM: | |
1121 | case TYPE_CODE_INT: | |
1122 | case TYPE_CODE_FLT: | |
1123 | case TYPE_CODE_SET: | |
1124 | case TYPE_CODE_RANGE: | |
1125 | case TYPE_CODE_BITSTRING: | |
1126 | case TYPE_CODE_REF: | |
1127 | case TYPE_CODE_CHAR: | |
1128 | case TYPE_CODE_BOOL: | |
1129 | return TYPE_LENGTH (t); | |
1130 | ||
1131 | case TYPE_CODE_ARRAY: | |
1132 | case TYPE_CODE_COMPLEX: | |
1133 | /* TODO: What about vector types? */ | |
1134 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1135 | ||
1136 | case TYPE_CODE_STRUCT: | |
1137 | case TYPE_CODE_UNION: | |
1138 | align = 1; | |
1139 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1140 | { | |
1141 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1142 | if (falign > align) | |
1143 | align = falign; | |
1144 | } | |
1145 | return align; | |
1146 | } | |
1147 | } | |
1148 | ||
2dd604e7 RE |
1149 | /* We currently only support passing parameters in integer registers. This |
1150 | conforms with GCC's default model. Several other variants exist and | |
1151 | we should probably support some of them based on the selected ABI. */ | |
1152 | ||
1153 | static CORE_ADDR | |
7d9b040b | 1154 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1155 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1156 | struct value **args, CORE_ADDR sp, int struct_return, | |
1157 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1158 | { |
1159 | int argnum; | |
1160 | int argreg; | |
1161 | int nstack; | |
1162 | struct stack_item *si = NULL; | |
1163 | ||
6a65450a AC |
1164 | /* Set the return address. For the ARM, the return breakpoint is |
1165 | always at BP_ADDR. */ | |
2dd604e7 | 1166 | /* XXX Fix for Thumb. */ |
6a65450a | 1167 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1168 | |
1169 | /* Walk through the list of args and determine how large a temporary | |
1170 | stack is required. Need to take care here as structs may be | |
1171 | passed on the stack, and we have to to push them. */ | |
1172 | nstack = 0; | |
1173 | ||
1174 | argreg = ARM_A1_REGNUM; | |
1175 | nstack = 0; | |
1176 | ||
2dd604e7 RE |
1177 | /* The struct_return pointer occupies the first parameter |
1178 | passing register. */ | |
1179 | if (struct_return) | |
1180 | { | |
1181 | if (arm_debug) | |
1182 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1183 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1184 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1185 | argreg++; | |
1186 | } | |
1187 | ||
1188 | for (argnum = 0; argnum < nargs; argnum++) | |
1189 | { | |
1190 | int len; | |
1191 | struct type *arg_type; | |
1192 | struct type *target_type; | |
1193 | enum type_code typecode; | |
0fd88904 | 1194 | bfd_byte *val; |
2af48f68 | 1195 | int align; |
2dd604e7 | 1196 | |
df407dfe | 1197 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1198 | len = TYPE_LENGTH (arg_type); |
1199 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1200 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1201 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1202 | |
2af48f68 PB |
1203 | align = arm_type_align (arg_type); |
1204 | /* Round alignment up to a whole number of words. */ | |
1205 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1206 | /* Different ABIs have different maximum alignments. */ | |
1207 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1208 | { | |
1209 | /* The APCS ABI only requires word alignment. */ | |
1210 | align = INT_REGISTER_SIZE; | |
1211 | } | |
1212 | else | |
1213 | { | |
1214 | /* The AAPCS requires at most doubleword alignment. */ | |
1215 | if (align > INT_REGISTER_SIZE * 2) | |
1216 | align = INT_REGISTER_SIZE * 2; | |
1217 | } | |
1218 | ||
1219 | /* Push stack padding for dowubleword alignment. */ | |
1220 | if (nstack & (align - 1)) | |
1221 | { | |
1222 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1223 | nstack += INT_REGISTER_SIZE; | |
1224 | } | |
1225 | ||
1226 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1227 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1228 | && align > INT_REGISTER_SIZE | |
1229 | && argreg & 1) | |
1230 | argreg++; | |
1231 | ||
2dd604e7 RE |
1232 | /* If the argument is a pointer to a function, and it is a |
1233 | Thumb function, create a LOCAL copy of the value and set | |
1234 | the THUMB bit in it. */ | |
1235 | if (TYPE_CODE_PTR == typecode | |
1236 | && target_type != NULL | |
1237 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1238 | { | |
7c0b4a20 | 1239 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1240 | if (arm_pc_is_thumb (regval)) |
1241 | { | |
1242 | val = alloca (len); | |
fbd9dcd3 | 1243 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1244 | } |
1245 | } | |
1246 | ||
1247 | /* Copy the argument to general registers or the stack in | |
1248 | register-sized pieces. Large arguments are split between | |
1249 | registers and stack. */ | |
1250 | while (len > 0) | |
1251 | { | |
b1e29e33 | 1252 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1253 | |
1254 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1255 | { | |
1256 | /* The argument is being passed in a general purpose | |
1257 | register. */ | |
7c0b4a20 | 1258 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1259 | if (arm_debug) |
1260 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1261 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1262 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1263 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1264 | argreg++; | |
1265 | } | |
1266 | else | |
1267 | { | |
1268 | /* Push the arguments onto the stack. */ | |
1269 | if (arm_debug) | |
1270 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1271 | argnum, nstack); | |
b1e29e33 AC |
1272 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1273 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1274 | } |
1275 | ||
1276 | len -= partial_len; | |
1277 | val += partial_len; | |
1278 | } | |
1279 | } | |
1280 | /* If we have an odd number of words to push, then decrement the stack | |
1281 | by one word now, so first stack argument will be dword aligned. */ | |
1282 | if (nstack & 4) | |
1283 | sp -= 4; | |
1284 | ||
1285 | while (si) | |
1286 | { | |
1287 | sp -= si->len; | |
1288 | write_memory (sp, si->data, si->len); | |
1289 | si = pop_stack_item (si); | |
1290 | } | |
1291 | ||
1292 | /* Finally, update teh SP register. */ | |
1293 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1294 | ||
1295 | return sp; | |
1296 | } | |
1297 | ||
f53f0d0b PB |
1298 | |
1299 | /* Always align the frame to an 8-byte boundary. This is required on | |
1300 | some platforms and harmless on the rest. */ | |
1301 | ||
1302 | static CORE_ADDR | |
1303 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1304 | { | |
1305 | /* Align the stack to eight bytes. */ | |
1306 | return sp & ~ (CORE_ADDR) 7; | |
1307 | } | |
1308 | ||
c906108c | 1309 | static void |
ed9a39eb | 1310 | print_fpu_flags (int flags) |
c906108c | 1311 | { |
c5aa993b JM |
1312 | if (flags & (1 << 0)) |
1313 | fputs ("IVO ", stdout); | |
1314 | if (flags & (1 << 1)) | |
1315 | fputs ("DVZ ", stdout); | |
1316 | if (flags & (1 << 2)) | |
1317 | fputs ("OFL ", stdout); | |
1318 | if (flags & (1 << 3)) | |
1319 | fputs ("UFL ", stdout); | |
1320 | if (flags & (1 << 4)) | |
1321 | fputs ("INX ", stdout); | |
1322 | putchar ('\n'); | |
c906108c SS |
1323 | } |
1324 | ||
5e74b15c RE |
1325 | /* Print interesting information about the floating point processor |
1326 | (if present) or emulator. */ | |
34e8f22d | 1327 | static void |
d855c300 | 1328 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1329 | struct frame_info *frame, const char *args) |
c906108c | 1330 | { |
52f0bd74 | 1331 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1332 | int type; |
1333 | ||
1334 | type = (status >> 24) & 127; | |
edefbb7c AC |
1335 | if (status & (1 << 31)) |
1336 | printf (_("Hardware FPU type %d\n"), type); | |
1337 | else | |
1338 | printf (_("Software FPU type %d\n"), type); | |
1339 | /* i18n: [floating point unit] mask */ | |
1340 | fputs (_("mask: "), stdout); | |
c5aa993b | 1341 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1342 | /* i18n: [floating point unit] flags */ |
1343 | fputs (_("flags: "), stdout); | |
c5aa993b | 1344 | print_fpu_flags (status); |
c906108c SS |
1345 | } |
1346 | ||
34e8f22d RE |
1347 | /* Return the GDB type object for the "standard" data type of data in |
1348 | register N. */ | |
1349 | ||
1350 | static struct type * | |
7a5ea0d4 | 1351 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1352 | { |
34e8f22d | 1353 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1354 | { |
d7449b42 | 1355 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1356 | return builtin_type_arm_ext_big; |
1357 | else | |
1358 | return builtin_type_arm_ext_littlebyte_bigword; | |
1359 | } | |
e4c16157 DJ |
1360 | else if (regnum == ARM_SP_REGNUM) |
1361 | return builtin_type_void_data_ptr; | |
1362 | else if (regnum == ARM_PC_REGNUM) | |
1363 | return builtin_type_void_func_ptr; | |
032758dc | 1364 | else |
e4c16157 | 1365 | return builtin_type_uint32; |
032758dc AC |
1366 | } |
1367 | ||
34e8f22d RE |
1368 | /* Index within `registers' of the first byte of the space for |
1369 | register N. */ | |
1370 | ||
1371 | static int | |
1372 | arm_register_byte (int regnum) | |
1373 | { | |
1374 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1375 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1376 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1377 | return (NUM_GREGS * INT_REGISTER_SIZE |
1378 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1379 | else |
7a5ea0d4 DJ |
1380 | return (NUM_GREGS * INT_REGISTER_SIZE |
1381 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1382 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1383 | } | |
1384 | ||
26216b98 AC |
1385 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1386 | static int | |
1387 | arm_register_sim_regno (int regnum) | |
1388 | { | |
1389 | int reg = regnum; | |
1390 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1391 | ||
1392 | if (reg < NUM_GREGS) | |
1393 | return SIM_ARM_R0_REGNUM + reg; | |
1394 | reg -= NUM_GREGS; | |
1395 | ||
1396 | if (reg < NUM_FREGS) | |
1397 | return SIM_ARM_FP0_REGNUM + reg; | |
1398 | reg -= NUM_FREGS; | |
1399 | ||
1400 | if (reg < NUM_SREGS) | |
1401 | return SIM_ARM_FPS_REGNUM + reg; | |
1402 | reg -= NUM_SREGS; | |
1403 | ||
edefbb7c | 1404 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1405 | } |
34e8f22d | 1406 | |
a37b3cc0 AC |
1407 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1408 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1409 | It is thought that this is is the floating-point register format on | |
1410 | little-endian systems. */ | |
c906108c | 1411 | |
ed9a39eb | 1412 | static void |
b508a996 RE |
1413 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1414 | void *dbl) | |
c906108c | 1415 | { |
a37b3cc0 | 1416 | DOUBLEST d; |
d7449b42 | 1417 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1418 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1419 | else | |
1420 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1421 | ptr, &d); | |
b508a996 | 1422 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1423 | } |
1424 | ||
34e8f22d | 1425 | static void |
b508a996 | 1426 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1427 | { |
a37b3cc0 | 1428 | DOUBLEST d; |
b508a996 | 1429 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1430 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1431 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1432 | else | |
1433 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1434 | &d, dbl); | |
c906108c | 1435 | } |
ed9a39eb | 1436 | |
c906108c | 1437 | static int |
ed9a39eb | 1438 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1439 | { |
1440 | if (cond == INST_AL || cond == INST_NV) | |
1441 | return 1; | |
1442 | ||
1443 | switch (cond) | |
1444 | { | |
1445 | case INST_EQ: | |
1446 | return ((status_reg & FLAG_Z) != 0); | |
1447 | case INST_NE: | |
1448 | return ((status_reg & FLAG_Z) == 0); | |
1449 | case INST_CS: | |
1450 | return ((status_reg & FLAG_C) != 0); | |
1451 | case INST_CC: | |
1452 | return ((status_reg & FLAG_C) == 0); | |
1453 | case INST_MI: | |
1454 | return ((status_reg & FLAG_N) != 0); | |
1455 | case INST_PL: | |
1456 | return ((status_reg & FLAG_N) == 0); | |
1457 | case INST_VS: | |
1458 | return ((status_reg & FLAG_V) != 0); | |
1459 | case INST_VC: | |
1460 | return ((status_reg & FLAG_V) == 0); | |
1461 | case INST_HI: | |
1462 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1463 | case INST_LS: | |
1464 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1465 | case INST_GE: | |
1466 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1467 | case INST_LT: | |
1468 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1469 | case INST_GT: | |
1470 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1471 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1472 | case INST_LE: |
1473 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1474 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1475 | } |
1476 | return 1; | |
1477 | } | |
1478 | ||
9512d7fd | 1479 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1480 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1481 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1482 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1483 | #define sbits(obj,st,fn) \ | |
1484 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1485 | #define BranchDest(addr,instr) \ | |
1486 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1487 | #define ARM_PC_32 1 | |
1488 | ||
1489 | static unsigned long | |
ed9a39eb JM |
1490 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1491 | unsigned long status_reg) | |
c906108c SS |
1492 | { |
1493 | unsigned long res, shift; | |
1494 | int rm = bits (inst, 0, 3); | |
1495 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1496 | |
1497 | if (bit (inst, 4)) | |
c906108c SS |
1498 | { |
1499 | int rs = bits (inst, 8, 11); | |
1500 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1501 | } | |
1502 | else | |
1503 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1504 | |
1505 | res = (rm == 15 | |
c906108c | 1506 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1507 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1508 | : read_register (rm)); |
1509 | ||
1510 | switch (shifttype) | |
1511 | { | |
c5aa993b | 1512 | case 0: /* LSL */ |
c906108c SS |
1513 | res = shift >= 32 ? 0 : res << shift; |
1514 | break; | |
c5aa993b JM |
1515 | |
1516 | case 1: /* LSR */ | |
c906108c SS |
1517 | res = shift >= 32 ? 0 : res >> shift; |
1518 | break; | |
1519 | ||
c5aa993b JM |
1520 | case 2: /* ASR */ |
1521 | if (shift >= 32) | |
1522 | shift = 31; | |
c906108c SS |
1523 | res = ((res & 0x80000000L) |
1524 | ? ~((~res) >> shift) : res >> shift); | |
1525 | break; | |
1526 | ||
c5aa993b | 1527 | case 3: /* ROR/RRX */ |
c906108c SS |
1528 | shift &= 31; |
1529 | if (shift == 0) | |
1530 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1531 | else | |
c5aa993b | 1532 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1533 | break; |
1534 | } | |
1535 | ||
1536 | return res & 0xffffffff; | |
1537 | } | |
1538 | ||
c906108c SS |
1539 | /* Return number of 1-bits in VAL. */ |
1540 | ||
1541 | static int | |
ed9a39eb | 1542 | bitcount (unsigned long val) |
c906108c SS |
1543 | { |
1544 | int nbits; | |
1545 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1546 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1547 | return nbits; |
1548 | } | |
1549 | ||
34e8f22d | 1550 | CORE_ADDR |
ed9a39eb | 1551 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1552 | { |
c5aa993b | 1553 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
1c5bada0 | 1554 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
94c30b78 | 1555 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1556 | unsigned long offset; |
1557 | ||
1558 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1559 | { | |
1560 | CORE_ADDR sp; | |
1561 | ||
1562 | /* Fetch the saved PC from the stack. It's stored above | |
1563 | all of the other registers. */ | |
b1e29e33 | 1564 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1565 | sp = read_register (ARM_SP_REGNUM); |
1c5bada0 | 1566 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
c906108c SS |
1567 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1568 | if (nextpc == pc) | |
edefbb7c | 1569 | error (_("Infinite loop detected")); |
c906108c SS |
1570 | } |
1571 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1572 | { | |
34e8f22d | 1573 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1574 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1575 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1576 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1577 | } | |
1578 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1579 | { | |
1580 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1581 | } | |
aa17d93e | 1582 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1583 | { |
1c5bada0 | 1584 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
c5aa993b | 1585 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1586 | nextpc = pc_val + offset; |
aa17d93e DJ |
1587 | /* For BLX make sure to clear the low bits. */ |
1588 | if (bits (inst2, 11, 12) == 1) | |
1589 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1590 | } |
aa17d93e | 1591 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1592 | { |
1593 | if (bits (inst1, 3, 6) == 0x0f) | |
1594 | nextpc = pc_val; | |
1595 | else | |
1596 | nextpc = read_register (bits (inst1, 3, 6)); | |
1597 | ||
1598 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1599 | if (nextpc == pc) | |
edefbb7c | 1600 | error (_("Infinite loop detected")); |
9498281f | 1601 | } |
c906108c SS |
1602 | |
1603 | return nextpc; | |
1604 | } | |
1605 | ||
34e8f22d | 1606 | CORE_ADDR |
ed9a39eb | 1607 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1608 | { |
1609 | unsigned long pc_val; | |
1610 | unsigned long this_instr; | |
1611 | unsigned long status; | |
1612 | CORE_ADDR nextpc; | |
1613 | ||
1614 | if (arm_pc_is_thumb (pc)) | |
1615 | return thumb_get_next_pc (pc); | |
1616 | ||
1617 | pc_val = (unsigned long) pc; | |
1c5bada0 | 1618 | this_instr = read_memory_unsigned_integer (pc, 4); |
34e8f22d | 1619 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1620 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1621 | |
1622 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1623 | { | |
1624 | switch (bits (this_instr, 24, 27)) | |
1625 | { | |
c5aa993b | 1626 | case 0x0: |
94c30b78 | 1627 | case 0x1: /* data processing */ |
c5aa993b JM |
1628 | case 0x2: |
1629 | case 0x3: | |
c906108c SS |
1630 | { |
1631 | unsigned long operand1, operand2, result = 0; | |
1632 | unsigned long rn; | |
1633 | int c; | |
c5aa993b | 1634 | |
c906108c SS |
1635 | if (bits (this_instr, 12, 15) != 15) |
1636 | break; | |
1637 | ||
1638 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1639 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1640 | error (_("Invalid update to pc in instruction")); |
c906108c | 1641 | |
9498281f DJ |
1642 | /* BX <reg>, BLX <reg> */ |
1643 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1644 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1645 | { | |
1646 | rn = bits (this_instr, 0, 3); | |
1647 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1648 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1649 | ||
1650 | if (nextpc == pc) | |
edefbb7c | 1651 | error (_("Infinite loop detected")); |
9498281f DJ |
1652 | |
1653 | return nextpc; | |
1654 | } | |
1655 | ||
c906108c SS |
1656 | /* Multiply into PC */ |
1657 | c = (status & FLAG_C) ? 1 : 0; | |
1658 | rn = bits (this_instr, 16, 19); | |
1659 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1660 | |
c906108c SS |
1661 | if (bit (this_instr, 25)) |
1662 | { | |
1663 | unsigned long immval = bits (this_instr, 0, 7); | |
1664 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1665 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1666 | & 0xffffffff; | |
c906108c | 1667 | } |
c5aa993b | 1668 | else /* operand 2 is a shifted register */ |
c906108c | 1669 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1670 | |
c906108c SS |
1671 | switch (bits (this_instr, 21, 24)) |
1672 | { | |
c5aa993b | 1673 | case 0x0: /*and */ |
c906108c SS |
1674 | result = operand1 & operand2; |
1675 | break; | |
1676 | ||
c5aa993b | 1677 | case 0x1: /*eor */ |
c906108c SS |
1678 | result = operand1 ^ operand2; |
1679 | break; | |
1680 | ||
c5aa993b | 1681 | case 0x2: /*sub */ |
c906108c SS |
1682 | result = operand1 - operand2; |
1683 | break; | |
1684 | ||
c5aa993b | 1685 | case 0x3: /*rsb */ |
c906108c SS |
1686 | result = operand2 - operand1; |
1687 | break; | |
1688 | ||
c5aa993b | 1689 | case 0x4: /*add */ |
c906108c SS |
1690 | result = operand1 + operand2; |
1691 | break; | |
1692 | ||
c5aa993b | 1693 | case 0x5: /*adc */ |
c906108c SS |
1694 | result = operand1 + operand2 + c; |
1695 | break; | |
1696 | ||
c5aa993b | 1697 | case 0x6: /*sbc */ |
c906108c SS |
1698 | result = operand1 - operand2 + c; |
1699 | break; | |
1700 | ||
c5aa993b | 1701 | case 0x7: /*rsc */ |
c906108c SS |
1702 | result = operand2 - operand1 + c; |
1703 | break; | |
1704 | ||
c5aa993b JM |
1705 | case 0x8: |
1706 | case 0x9: | |
1707 | case 0xa: | |
1708 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1709 | result = (unsigned long) nextpc; |
1710 | break; | |
1711 | ||
c5aa993b | 1712 | case 0xc: /*orr */ |
c906108c SS |
1713 | result = operand1 | operand2; |
1714 | break; | |
1715 | ||
c5aa993b | 1716 | case 0xd: /*mov */ |
c906108c SS |
1717 | /* Always step into a function. */ |
1718 | result = operand2; | |
c5aa993b | 1719 | break; |
c906108c | 1720 | |
c5aa993b | 1721 | case 0xe: /*bic */ |
c906108c SS |
1722 | result = operand1 & ~operand2; |
1723 | break; | |
1724 | ||
c5aa993b | 1725 | case 0xf: /*mvn */ |
c906108c SS |
1726 | result = ~operand2; |
1727 | break; | |
1728 | } | |
1729 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1730 | ||
1731 | if (nextpc == pc) | |
edefbb7c | 1732 | error (_("Infinite loop detected")); |
c906108c SS |
1733 | break; |
1734 | } | |
c5aa993b JM |
1735 | |
1736 | case 0x4: | |
1737 | case 0x5: /* data transfer */ | |
1738 | case 0x6: | |
1739 | case 0x7: | |
c906108c SS |
1740 | if (bit (this_instr, 20)) |
1741 | { | |
1742 | /* load */ | |
1743 | if (bits (this_instr, 12, 15) == 15) | |
1744 | { | |
1745 | /* rd == pc */ | |
c5aa993b | 1746 | unsigned long rn; |
c906108c | 1747 | unsigned long base; |
c5aa993b | 1748 | |
c906108c | 1749 | if (bit (this_instr, 22)) |
edefbb7c | 1750 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1751 | |
1752 | /* byte write to PC */ | |
1753 | rn = bits (this_instr, 16, 19); | |
1754 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1755 | if (bit (this_instr, 24)) | |
1756 | { | |
1757 | /* pre-indexed */ | |
1758 | int c = (status & FLAG_C) ? 1 : 0; | |
1759 | unsigned long offset = | |
c5aa993b | 1760 | (bit (this_instr, 25) |
ed9a39eb | 1761 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1762 | : bits (this_instr, 0, 11)); |
c906108c SS |
1763 | |
1764 | if (bit (this_instr, 23)) | |
1765 | base += offset; | |
1766 | else | |
1767 | base -= offset; | |
1768 | } | |
c5aa993b | 1769 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1770 | 4); |
c5aa993b | 1771 | |
c906108c SS |
1772 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1773 | ||
1774 | if (nextpc == pc) | |
edefbb7c | 1775 | error (_("Infinite loop detected")); |
c906108c SS |
1776 | } |
1777 | } | |
1778 | break; | |
c5aa993b JM |
1779 | |
1780 | case 0x8: | |
1781 | case 0x9: /* block transfer */ | |
c906108c SS |
1782 | if (bit (this_instr, 20)) |
1783 | { | |
1784 | /* LDM */ | |
1785 | if (bit (this_instr, 15)) | |
1786 | { | |
1787 | /* loading pc */ | |
1788 | int offset = 0; | |
1789 | ||
1790 | if (bit (this_instr, 23)) | |
1791 | { | |
1792 | /* up */ | |
1793 | unsigned long reglist = bits (this_instr, 0, 14); | |
1794 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1795 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1796 | offset += 4; |
1797 | } | |
1798 | else if (bit (this_instr, 24)) | |
1799 | offset = -4; | |
c5aa993b | 1800 | |
c906108c | 1801 | { |
c5aa993b JM |
1802 | unsigned long rn_val = |
1803 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1804 | nextpc = |
1805 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1806 | + offset), |
c906108c SS |
1807 | 4); |
1808 | } | |
1809 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1810 | if (nextpc == pc) | |
edefbb7c | 1811 | error (_("Infinite loop detected")); |
c906108c SS |
1812 | } |
1813 | } | |
1814 | break; | |
c5aa993b JM |
1815 | |
1816 | case 0xb: /* branch & link */ | |
1817 | case 0xa: /* branch */ | |
c906108c SS |
1818 | { |
1819 | nextpc = BranchDest (pc, this_instr); | |
1820 | ||
9498281f DJ |
1821 | /* BLX */ |
1822 | if (bits (this_instr, 28, 31) == INST_NV) | |
1823 | nextpc |= bit (this_instr, 24) << 1; | |
1824 | ||
c906108c SS |
1825 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1826 | if (nextpc == pc) | |
edefbb7c | 1827 | error (_("Infinite loop detected")); |
c906108c SS |
1828 | break; |
1829 | } | |
c5aa993b JM |
1830 | |
1831 | case 0xc: | |
1832 | case 0xd: | |
1833 | case 0xe: /* coproc ops */ | |
1834 | case 0xf: /* SWI */ | |
c906108c SS |
1835 | break; |
1836 | ||
1837 | default: | |
edefbb7c | 1838 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1839 | return (pc); |
1840 | } | |
1841 | } | |
1842 | ||
1843 | return nextpc; | |
1844 | } | |
1845 | ||
9512d7fd FN |
1846 | /* single_step() is called just before we want to resume the inferior, |
1847 | if we want to single-step it but there is no hardware or kernel | |
1848 | single-step support. We find the target of the coming instruction | |
1849 | and breakpoint it. | |
1850 | ||
94c30b78 MS |
1851 | single_step() is also called just after the inferior stops. If we |
1852 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1853 | |
34e8f22d RE |
1854 | static void |
1855 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1856 | { |
8181d85f DJ |
1857 | /* NOTE: This may insert the wrong breakpoint instruction when |
1858 | single-stepping over a mode-changing instruction, if the | |
1859 | CPSR heuristics are used. */ | |
9512d7fd FN |
1860 | |
1861 | if (insert_bpt) | |
1862 | { | |
8181d85f DJ |
1863 | CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
1864 | ||
1865 | insert_single_step_breakpoint (next_pc); | |
9512d7fd FN |
1866 | } |
1867 | else | |
8181d85f | 1868 | remove_single_step_breakpoints (); |
9512d7fd | 1869 | } |
9512d7fd | 1870 | |
c906108c SS |
1871 | #include "bfd-in2.h" |
1872 | #include "libcoff.h" | |
1873 | ||
1874 | static int | |
ed9a39eb | 1875 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1876 | { |
1877 | if (arm_pc_is_thumb (memaddr)) | |
1878 | { | |
c5aa993b JM |
1879 | static asymbol *asym; |
1880 | static combined_entry_type ce; | |
1881 | static struct coff_symbol_struct csym; | |
27cddce2 | 1882 | static struct bfd fake_bfd; |
c5aa993b | 1883 | static bfd_target fake_target; |
c906108c SS |
1884 | |
1885 | if (csym.native == NULL) | |
1886 | { | |
da3c6d4a MS |
1887 | /* Create a fake symbol vector containing a Thumb symbol. |
1888 | This is solely so that the code in print_insn_little_arm() | |
1889 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1890 | the presence of a Thumb symbol and switch to decoding | |
1891 | Thumb instructions. */ | |
c5aa993b JM |
1892 | |
1893 | fake_target.flavour = bfd_target_coff_flavour; | |
1894 | fake_bfd.xvec = &fake_target; | |
c906108c | 1895 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1896 | csym.native = &ce; |
1897 | csym.symbol.the_bfd = &fake_bfd; | |
1898 | csym.symbol.name = "fake"; | |
1899 | asym = (asymbol *) & csym; | |
c906108c | 1900 | } |
c5aa993b | 1901 | |
c906108c | 1902 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1903 | info->symbols = &asym; |
c906108c SS |
1904 | } |
1905 | else | |
1906 | info->symbols = NULL; | |
c5aa993b | 1907 | |
d7449b42 | 1908 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1909 | return print_insn_big_arm (memaddr, info); |
1910 | else | |
1911 | return print_insn_little_arm (memaddr, info); | |
1912 | } | |
1913 | ||
66e810cd RE |
1914 | /* The following define instruction sequences that will cause ARM |
1915 | cpu's to take an undefined instruction trap. These are used to | |
1916 | signal a breakpoint to GDB. | |
1917 | ||
1918 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1919 | modes. A different instruction is required for each mode. The ARM | |
1920 | cpu's can also be big or little endian. Thus four different | |
1921 | instructions are needed to support all cases. | |
1922 | ||
1923 | Note: ARMv4 defines several new instructions that will take the | |
1924 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1925 | not in fact add the new instructions. The new undefined | |
1926 | instructions in ARMv4 are all instructions that had no defined | |
1927 | behaviour in earlier chips. There is no guarantee that they will | |
1928 | raise an exception, but may be treated as NOP's. In practice, it | |
1929 | may only safe to rely on instructions matching: | |
1930 | ||
1931 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1932 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1933 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1934 | ||
1935 | Even this may only true if the condition predicate is true. The | |
1936 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1937 | ||
1938 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1939 | and NetBSD all use a software interrupt rather than an undefined | |
1940 | instruction to force a trap. This can be handled by by the | |
1941 | abi-specific code during establishment of the gdbarch vector. */ | |
1942 | ||
1943 | ||
d7b486e7 RE |
1944 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1945 | override these definitions. */ | |
66e810cd RE |
1946 | #ifndef ARM_LE_BREAKPOINT |
1947 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1948 | #endif | |
1949 | #ifndef ARM_BE_BREAKPOINT | |
1950 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1951 | #endif | |
1952 | #ifndef THUMB_LE_BREAKPOINT | |
1953 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1954 | #endif | |
1955 | #ifndef THUMB_BE_BREAKPOINT | |
1956 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1957 | #endif | |
1958 | ||
1959 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1960 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1961 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1962 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1963 | ||
34e8f22d RE |
1964 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1965 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1966 | breakpoint should be used. It returns a pointer to a string of |
1967 | bytes that encode a breakpoint instruction, stores the length of | |
1968 | the string to *lenptr, and adjusts the program counter (if | |
1969 | necessary) to point to the actual memory location where the | |
c906108c SS |
1970 | breakpoint should be inserted. */ |
1971 | ||
ab89facf | 1972 | static const unsigned char * |
ed9a39eb | 1973 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1974 | { |
66e810cd RE |
1975 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1976 | ||
4bf7064c | 1977 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 1978 | { |
66e810cd RE |
1979 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1980 | *lenptr = tdep->thumb_breakpoint_size; | |
1981 | return tdep->thumb_breakpoint; | |
c906108c SS |
1982 | } |
1983 | else | |
1984 | { | |
66e810cd RE |
1985 | *lenptr = tdep->arm_breakpoint_size; |
1986 | return tdep->arm_breakpoint; | |
c906108c SS |
1987 | } |
1988 | } | |
ed9a39eb JM |
1989 | |
1990 | /* Extract from an array REGBUF containing the (raw) register state a | |
1991 | function return value of type TYPE, and copy that, in virtual | |
1992 | format, into VALBUF. */ | |
1993 | ||
34e8f22d | 1994 | static void |
5238cf52 MK |
1995 | arm_extract_return_value (struct type *type, struct regcache *regs, |
1996 | gdb_byte *valbuf) | |
ed9a39eb JM |
1997 | { |
1998 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 | 1999 | { |
28e97307 | 2000 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2001 | { |
2002 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2003 | { |
2004 | /* The value is in register F0 in internal format. We need to | |
2005 | extract the raw value and then convert it to the desired | |
2006 | internal type. */ | |
7a5ea0d4 | 2007 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2008 | |
2009 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2010 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2011 | valbuf); | |
2012 | } | |
08216dd7 RE |
2013 | break; |
2014 | ||
fd50bc42 | 2015 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2016 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2017 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2018 | if (TYPE_LENGTH (type) > 4) | |
2019 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2020 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2021 | break; |
2022 | ||
2023 | default: | |
2024 | internal_error | |
2025 | (__FILE__, __LINE__, | |
edefbb7c | 2026 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2027 | break; |
2028 | } | |
2029 | } | |
b508a996 RE |
2030 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2031 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2032 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2033 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2034 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2035 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2036 | { | |
2037 | /* If the the type is a plain integer, then the access is | |
2038 | straight-forward. Otherwise we have to play around a bit more. */ | |
2039 | int len = TYPE_LENGTH (type); | |
2040 | int regno = ARM_A1_REGNUM; | |
2041 | ULONGEST tmp; | |
2042 | ||
2043 | while (len > 0) | |
2044 | { | |
2045 | /* By using store_unsigned_integer we avoid having to do | |
2046 | anything special for small big-endian values. */ | |
2047 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2048 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2049 | (len > INT_REGISTER_SIZE |
2050 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2051 | tmp); |
7a5ea0d4 DJ |
2052 | len -= INT_REGISTER_SIZE; |
2053 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2054 | } |
2055 | } | |
ed9a39eb | 2056 | else |
b508a996 RE |
2057 | { |
2058 | /* For a structure or union the behaviour is as if the value had | |
2059 | been stored to word-aligned memory and then loaded into | |
2060 | registers with 32-bit load instruction(s). */ | |
2061 | int len = TYPE_LENGTH (type); | |
2062 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2063 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2064 | |
2065 | while (len > 0) | |
2066 | { | |
2067 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2068 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2069 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2070 | len -= INT_REGISTER_SIZE; | |
2071 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2072 | } |
2073 | } | |
34e8f22d RE |
2074 | } |
2075 | ||
67255d04 RE |
2076 | |
2077 | /* Will a function return an aggregate type in memory or in a | |
2078 | register? Return 0 if an aggregate type can be returned in a | |
2079 | register, 1 if it must be returned in memory. */ | |
2080 | ||
2081 | static int | |
2af48f68 | 2082 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2083 | { |
2084 | int nRc; | |
52f0bd74 | 2085 | enum type_code code; |
67255d04 | 2086 | |
44e1a9eb DJ |
2087 | CHECK_TYPEDEF (type); |
2088 | ||
67255d04 RE |
2089 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2090 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2091 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2092 | offset of each addressable subfield must be zero. Note that bit | |
2093 | fields are not addressable, and all addressable subfields of | |
2094 | unions always start at offset zero. | |
67255d04 RE |
2095 | |
2096 | This function is based on the behaviour of GCC 2.95.1. | |
2097 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2098 | ||
2099 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2100 | parameters correctly for a function returning the following | |
2101 | structure: struct { float f;}; This should be returned in memory, | |
2102 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2103 | know of any way to detect if a function like the above has been | |
2104 | compiled with the correct calling convention. */ | |
2105 | ||
2106 | /* All aggregate types that won't fit in a register must be returned | |
2107 | in memory. */ | |
b1e29e33 | 2108 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2109 | { |
2110 | return 1; | |
2111 | } | |
2112 | ||
2af48f68 PB |
2113 | /* The AAPCS says all aggregates not larger than a word are returned |
2114 | in a register. */ | |
2115 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2116 | return 0; | |
2117 | ||
67255d04 RE |
2118 | /* The only aggregate types that can be returned in a register are |
2119 | structs and unions. Arrays must be returned in memory. */ | |
2120 | code = TYPE_CODE (type); | |
2121 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2122 | { | |
2123 | return 1; | |
2124 | } | |
2125 | ||
2126 | /* Assume all other aggregate types can be returned in a register. | |
2127 | Run a check for structures, unions and arrays. */ | |
2128 | nRc = 0; | |
2129 | ||
2130 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2131 | { | |
2132 | int i; | |
2133 | /* Need to check if this struct/union is "integer" like. For | |
2134 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2135 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2136 | subfield must be zero. Note that bit fields are not | |
2137 | addressable, and unions always start at offset zero. If any | |
2138 | of the subfields is a floating point type, the struct/union | |
2139 | cannot be an integer type. */ | |
67255d04 RE |
2140 | |
2141 | /* For each field in the object, check: | |
2142 | 1) Is it FP? --> yes, nRc = 1; | |
2143 | 2) Is it addressable (bitpos != 0) and | |
2144 | not packed (bitsize == 0)? | |
2145 | --> yes, nRc = 1 | |
2146 | */ | |
2147 | ||
2148 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2149 | { | |
2150 | enum type_code field_type_code; | |
44e1a9eb | 2151 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2152 | |
2153 | /* Is it a floating point type field? */ | |
2154 | if (field_type_code == TYPE_CODE_FLT) | |
2155 | { | |
2156 | nRc = 1; | |
2157 | break; | |
2158 | } | |
2159 | ||
2160 | /* If bitpos != 0, then we have to care about it. */ | |
2161 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2162 | { | |
2163 | /* Bitfields are not addressable. If the field bitsize is | |
2164 | zero, then the field is not packed. Hence it cannot be | |
2165 | a bitfield or any other packed type. */ | |
2166 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2167 | { | |
2168 | nRc = 1; | |
2169 | break; | |
2170 | } | |
2171 | } | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | return nRc; | |
2176 | } | |
2177 | ||
34e8f22d RE |
2178 | /* Write into appropriate registers a function return value of type |
2179 | TYPE, given in virtual format. */ | |
2180 | ||
2181 | static void | |
b508a996 | 2182 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2183 | const gdb_byte *valbuf) |
34e8f22d RE |
2184 | { |
2185 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2186 | { | |
7a5ea0d4 | 2187 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2188 | |
28e97307 | 2189 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2190 | { |
2191 | case ARM_FLOAT_FPA: | |
2192 | ||
b508a996 RE |
2193 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2194 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2195 | break; |
2196 | ||
fd50bc42 | 2197 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2198 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2199 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2200 | if (TYPE_LENGTH (type) > 4) | |
2201 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2202 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2203 | break; |
2204 | ||
2205 | default: | |
2206 | internal_error | |
2207 | (__FILE__, __LINE__, | |
edefbb7c | 2208 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2209 | break; |
2210 | } | |
34e8f22d | 2211 | } |
b508a996 RE |
2212 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2213 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2214 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2215 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2216 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2217 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2218 | { | |
2219 | if (TYPE_LENGTH (type) <= 4) | |
2220 | { | |
2221 | /* Values of one word or less are zero/sign-extended and | |
2222 | returned in r0. */ | |
7a5ea0d4 | 2223 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2224 | LONGEST val = unpack_long (type, valbuf); |
2225 | ||
7a5ea0d4 | 2226 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2227 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2228 | } | |
2229 | else | |
2230 | { | |
2231 | /* Integral values greater than one word are stored in consecutive | |
2232 | registers starting with r0. This will always be a multiple of | |
2233 | the regiser size. */ | |
2234 | int len = TYPE_LENGTH (type); | |
2235 | int regno = ARM_A1_REGNUM; | |
2236 | ||
2237 | while (len > 0) | |
2238 | { | |
2239 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2240 | len -= INT_REGISTER_SIZE; |
2241 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2242 | } |
2243 | } | |
2244 | } | |
34e8f22d | 2245 | else |
b508a996 RE |
2246 | { |
2247 | /* For a structure or union the behaviour is as if the value had | |
2248 | been stored to word-aligned memory and then loaded into | |
2249 | registers with 32-bit load instruction(s). */ | |
2250 | int len = TYPE_LENGTH (type); | |
2251 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2252 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2253 | |
2254 | while (len > 0) | |
2255 | { | |
2256 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2257 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2258 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2259 | len -= INT_REGISTER_SIZE; |
2260 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2261 | } |
2262 | } | |
34e8f22d RE |
2263 | } |
2264 | ||
2af48f68 PB |
2265 | |
2266 | /* Handle function return values. */ | |
2267 | ||
2268 | static enum return_value_convention | |
2269 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
25224166 MK |
2270 | struct regcache *regcache, gdb_byte *readbuf, |
2271 | const gdb_byte *writebuf) | |
2af48f68 PB |
2272 | { |
2273 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2274 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2275 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2276 | { | |
2277 | if (arm_return_in_memory (gdbarch, valtype)) | |
2278 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2279 | } | |
2280 | ||
2281 | if (writebuf) | |
2282 | arm_store_return_value (valtype, regcache, writebuf); | |
2283 | ||
2284 | if (readbuf) | |
2285 | arm_extract_return_value (valtype, regcache, readbuf); | |
2286 | ||
2287 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2288 | } | |
2289 | ||
2290 | ||
9df628e0 RE |
2291 | static int |
2292 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2293 | { | |
2294 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2295 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2296 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2297 | ||
2298 | jb_addr = read_register (ARM_A1_REGNUM); | |
2299 | ||
2300 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2301 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2302 | return 0; |
2303 | ||
7a5ea0d4 | 2304 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2305 | return 1; |
2306 | } | |
2307 | ||
ed9a39eb | 2308 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2309 | |
2310 | int | |
ed9a39eb | 2311 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2312 | { |
2313 | CORE_ADDR start_addr; | |
2314 | ||
ed9a39eb JM |
2315 | /* Find the starting address of the function containing the PC. If |
2316 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2317 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2318 | &start_addr, NULL)) | |
c906108c SS |
2319 | return 0; |
2320 | ||
2321 | return strncmp (name, "_call_via_r", 11) == 0; | |
2322 | } | |
2323 | ||
ed9a39eb JM |
2324 | /* If PC is in a Thumb call or return stub, return the address of the |
2325 | target PC, which is in a register. The thunk functions are called | |
2326 | _called_via_xx, where x is the register name. The possible names | |
2327 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2328 | |
2329 | CORE_ADDR | |
ed9a39eb | 2330 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2331 | { |
c5aa993b | 2332 | char *name; |
c906108c SS |
2333 | CORE_ADDR start_addr; |
2334 | ||
2335 | /* Find the starting address and name of the function containing the PC. */ | |
2336 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2337 | return 0; | |
2338 | ||
2339 | /* Call thunks always start with "_call_via_". */ | |
2340 | if (strncmp (name, "_call_via_", 10) == 0) | |
2341 | { | |
ed9a39eb JM |
2342 | /* Use the name suffix to determine which register contains the |
2343 | target PC. */ | |
c5aa993b JM |
2344 | static char *table[15] = |
2345 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2346 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2347 | }; | |
c906108c SS |
2348 | int regno; |
2349 | ||
2350 | for (regno = 0; regno <= 14; regno++) | |
2351 | if (strcmp (&name[10], table[regno]) == 0) | |
2352 | return read_register (regno); | |
2353 | } | |
ed9a39eb | 2354 | |
c5aa993b | 2355 | return 0; /* not a stub */ |
c906108c SS |
2356 | } |
2357 | ||
afd7eef0 RE |
2358 | static void |
2359 | set_arm_command (char *args, int from_tty) | |
2360 | { | |
edefbb7c AC |
2361 | printf_unfiltered (_("\ |
2362 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2363 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2364 | } | |
2365 | ||
2366 | static void | |
2367 | show_arm_command (char *args, int from_tty) | |
2368 | { | |
26304000 | 2369 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2370 | } |
2371 | ||
28e97307 DJ |
2372 | static void |
2373 | arm_update_current_architecture (void) | |
fd50bc42 | 2374 | { |
28e97307 | 2375 | struct gdbarch_info info; |
fd50bc42 | 2376 | |
28e97307 DJ |
2377 | /* If the current architecture is not ARM, we have nothing to do. */ |
2378 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2379 | return; | |
fd50bc42 | 2380 | |
28e97307 DJ |
2381 | /* Update the architecture. */ |
2382 | gdbarch_info_init (&info); | |
fd50bc42 | 2383 | |
28e97307 DJ |
2384 | if (!gdbarch_update_p (info)) |
2385 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2386 | } |
2387 | ||
2388 | static void | |
2389 | set_fp_model_sfunc (char *args, int from_tty, | |
2390 | struct cmd_list_element *c) | |
2391 | { | |
2392 | enum arm_float_model fp_model; | |
2393 | ||
2394 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2395 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2396 | { | |
2397 | arm_fp_model = fp_model; | |
2398 | break; | |
2399 | } | |
2400 | ||
2401 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2402 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2403 | current_fp_model); |
2404 | ||
28e97307 | 2405 | arm_update_current_architecture (); |
fd50bc42 RE |
2406 | } |
2407 | ||
2408 | static void | |
08546159 AC |
2409 | show_fp_model (struct ui_file *file, int from_tty, |
2410 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2411 | { |
2412 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2413 | ||
28e97307 | 2414 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2415 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2416 | fprintf_filtered (file, _("\ |
2417 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2418 | fp_model_strings[tdep->fp_model]); | |
2419 | else | |
2420 | fprintf_filtered (file, _("\ | |
2421 | The current ARM floating point model is \"%s\".\n"), | |
2422 | fp_model_strings[arm_fp_model]); | |
2423 | } | |
2424 | ||
2425 | static void | |
2426 | arm_set_abi (char *args, int from_tty, | |
2427 | struct cmd_list_element *c) | |
2428 | { | |
2429 | enum arm_abi_kind arm_abi; | |
2430 | ||
2431 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2432 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2433 | { | |
2434 | arm_abi_global = arm_abi; | |
2435 | break; | |
2436 | } | |
2437 | ||
2438 | if (arm_abi == ARM_ABI_LAST) | |
2439 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2440 | arm_abi_string); | |
2441 | ||
2442 | arm_update_current_architecture (); | |
2443 | } | |
2444 | ||
2445 | static void | |
2446 | arm_show_abi (struct ui_file *file, int from_tty, | |
2447 | struct cmd_list_element *c, const char *value) | |
2448 | { | |
2449 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2450 | ||
2451 | if (arm_abi_global == ARM_ABI_AUTO | |
2452 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2453 | fprintf_filtered (file, _("\ | |
2454 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2455 | arm_abi_strings[tdep->arm_abi]); | |
2456 | else | |
2457 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2458 | arm_abi_string); | |
fd50bc42 RE |
2459 | } |
2460 | ||
afd7eef0 RE |
2461 | /* If the user changes the register disassembly style used for info |
2462 | register and other commands, we have to also switch the style used | |
2463 | in opcodes for disassembly output. This function is run in the "set | |
2464 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2465 | |
2466 | static void | |
afd7eef0 | 2467 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2468 | struct cmd_list_element *c) |
2469 | { | |
afd7eef0 | 2470 | set_disassembly_style (); |
bc90b915 FN |
2471 | } |
2472 | \f | |
966fbf70 | 2473 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2474 | static const char * |
34e8f22d | 2475 | arm_register_name (int i) |
966fbf70 RE |
2476 | { |
2477 | return arm_register_names[i]; | |
2478 | } | |
2479 | ||
bc90b915 | 2480 | static void |
afd7eef0 | 2481 | set_disassembly_style (void) |
bc90b915 | 2482 | { |
4bd7b427 | 2483 | const char *setname, *setdesc, *const *regnames; |
bc90b915 FN |
2484 | int numregs, j; |
2485 | ||
afd7eef0 | 2486 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2487 | int current = 0; |
2488 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2489 | while ((disassembly_style != setname) |
2490 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2491 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2492 | current_option = current; | |
2493 | ||
94c30b78 | 2494 | /* Fill our copy. */ |
bc90b915 FN |
2495 | for (j = 0; j < numregs; j++) |
2496 | arm_register_names[j] = (char *) regnames[j]; | |
2497 | ||
94c30b78 | 2498 | /* Adjust case. */ |
34e8f22d | 2499 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2500 | { |
34e8f22d RE |
2501 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2502 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2503 | } |
2504 | else | |
2505 | { | |
34e8f22d RE |
2506 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2507 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2508 | } |
2509 | ||
94c30b78 | 2510 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2511 | set_arm_regname_option (current); |
2512 | } | |
2513 | ||
082fc60d RE |
2514 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2515 | function. */ | |
2516 | ||
2517 | static int | |
2518 | coff_sym_is_thumb (int val) | |
2519 | { | |
2520 | return (val == C_THUMBEXT || | |
2521 | val == C_THUMBSTAT || | |
2522 | val == C_THUMBEXTFUNC || | |
2523 | val == C_THUMBSTATFUNC || | |
2524 | val == C_THUMBLABEL); | |
2525 | } | |
2526 | ||
2527 | /* arm_coff_make_msymbol_special() | |
2528 | arm_elf_make_msymbol_special() | |
2529 | ||
2530 | These functions test whether the COFF or ELF symbol corresponds to | |
2531 | an address in thumb code, and set a "special" bit in a minimal | |
2532 | symbol to indicate that it does. */ | |
2533 | ||
34e8f22d | 2534 | static void |
082fc60d RE |
2535 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2536 | { | |
2537 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2538 | STT_ARM_TFUNC). */ | |
2539 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2540 | == STT_LOPROC) | |
2541 | MSYMBOL_SET_SPECIAL (msym); | |
2542 | } | |
2543 | ||
34e8f22d | 2544 | static void |
082fc60d RE |
2545 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2546 | { | |
2547 | if (coff_sym_is_thumb (val)) | |
2548 | MSYMBOL_SET_SPECIAL (msym); | |
2549 | } | |
2550 | ||
756fe439 DJ |
2551 | static void |
2552 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2553 | { | |
2554 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2555 | ||
2556 | /* If necessary, set the T bit. */ | |
2557 | if (arm_apcs_32) | |
2558 | { | |
2559 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2560 | if (arm_pc_is_thumb (pc)) | |
2561 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2562 | else | |
2563 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2564 | } | |
2565 | } | |
97e03143 | 2566 | \f |
70f80edf JT |
2567 | static enum gdb_osabi |
2568 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2569 | { |
2af48f68 | 2570 | unsigned int elfosabi; |
70f80edf | 2571 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2572 | |
70f80edf | 2573 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2574 | |
28e97307 DJ |
2575 | if (elfosabi == ELFOSABI_ARM) |
2576 | /* GNU tools use this value. Check note sections in this case, | |
2577 | as well. */ | |
2578 | bfd_map_over_sections (abfd, | |
2579 | generic_elf_osabi_sniff_abi_tag_sections, | |
2580 | &osabi); | |
97e03143 | 2581 | |
28e97307 | 2582 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2583 | return osabi; |
97e03143 RE |
2584 | } |
2585 | ||
70f80edf | 2586 | \f |
da3c6d4a MS |
2587 | /* Initialize the current architecture based on INFO. If possible, |
2588 | re-use an architecture from ARCHES, which is a list of | |
2589 | architectures already created during this debugging session. | |
97e03143 | 2590 | |
da3c6d4a MS |
2591 | Called e.g. at program startup, when reading a core file, and when |
2592 | reading a binary file. */ | |
97e03143 | 2593 | |
39bbf761 RE |
2594 | static struct gdbarch * |
2595 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2596 | { | |
97e03143 | 2597 | struct gdbarch_tdep *tdep; |
39bbf761 | 2598 | struct gdbarch *gdbarch; |
28e97307 DJ |
2599 | struct gdbarch_list *best_arch; |
2600 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2601 | enum arm_float_model fp_model = arm_fp_model; | |
39bbf761 | 2602 | |
28e97307 DJ |
2603 | /* If we have an object to base this architecture on, try to determine |
2604 | its ABI. */ | |
39bbf761 | 2605 | |
28e97307 | 2606 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2607 | { |
28e97307 DJ |
2608 | int ei_osabi; |
2609 | ||
4be87837 | 2610 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2611 | { |
4be87837 DJ |
2612 | case bfd_target_aout_flavour: |
2613 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2614 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2615 | break; |
97e03143 | 2616 | |
4be87837 DJ |
2617 | case bfd_target_coff_flavour: |
2618 | /* Assume it's an old APCS-style ABI. */ | |
2619 | /* XXX WinCE? */ | |
28e97307 DJ |
2620 | arm_abi = ARM_ABI_APCS; |
2621 | break; | |
2622 | ||
2623 | case bfd_target_elf_flavour: | |
2624 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
2625 | if (ei_osabi == ELFOSABI_ARM) | |
2626 | { | |
2627 | /* GNU tools used to use this value, but do not for EABI | |
2628 | objects. There's nowhere to tag an EABI version anyway, | |
2629 | so assume APCS. */ | |
2630 | arm_abi = ARM_ABI_APCS; | |
2631 | } | |
2632 | else if (ei_osabi == ELFOSABI_NONE) | |
2633 | { | |
2634 | int e_flags, eabi_ver; | |
2635 | ||
2636 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
2637 | eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
2638 | ||
2639 | switch (eabi_ver) | |
2640 | { | |
2641 | case EF_ARM_EABI_UNKNOWN: | |
2642 | /* Assume GNU tools. */ | |
2643 | arm_abi = ARM_ABI_APCS; | |
2644 | break; | |
2645 | ||
2646 | case EF_ARM_EABI_VER4: | |
2647 | arm_abi = ARM_ABI_AAPCS; | |
2af48f68 PB |
2648 | /* EABI binaries default to VFP float ordering. */ |
2649 | if (fp_model == ARM_FLOAT_AUTO) | |
2650 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2651 | break; |
2652 | ||
2653 | default: | |
2654 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
2655 | arm_abi = ARM_ABI_APCS; | |
2656 | break; | |
2657 | } | |
2658 | } | |
4be87837 | 2659 | break; |
97e03143 | 2660 | |
4be87837 | 2661 | default: |
28e97307 | 2662 | /* Leave it as "auto". */ |
50ceaba5 | 2663 | break; |
97e03143 RE |
2664 | } |
2665 | } | |
2666 | ||
28e97307 DJ |
2667 | /* Now that we have inferred any architecture settings that we |
2668 | can, try to inherit from the last ARM ABI. */ | |
4be87837 | 2669 | if (arches != NULL) |
28e97307 DJ |
2670 | { |
2671 | if (arm_abi == ARM_ABI_AUTO) | |
2672 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; | |
2673 | ||
2674 | if (fp_model == ARM_FLOAT_AUTO) | |
2675 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; | |
2676 | } | |
2677 | else | |
2678 | { | |
2679 | /* There was no prior ARM architecture; fill in default values. */ | |
2680 | ||
2681 | if (arm_abi == ARM_ABI_AUTO) | |
2682 | arm_abi = ARM_ABI_APCS; | |
2683 | ||
2684 | /* We used to default to FPA for generic ARM, but almost nobody | |
2685 | uses that now, and we now provide a way for the user to force | |
2686 | the model. So default to the most useful variant. */ | |
2687 | if (fp_model == ARM_FLOAT_AUTO) | |
2688 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2689 | } | |
2690 | ||
2691 | /* If there is already a candidate, use it. */ | |
2692 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2693 | best_arch != NULL; | |
2694 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2695 | { | |
2696 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
2697 | continue; | |
2698 | ||
2699 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
2700 | continue; | |
2701 | ||
2702 | /* Found a match. */ | |
2703 | break; | |
2704 | } | |
97e03143 | 2705 | |
28e97307 DJ |
2706 | if (best_arch != NULL) |
2707 | return best_arch->gdbarch; | |
2708 | ||
2709 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2710 | gdbarch = gdbarch_alloc (&info, tdep); |
2711 | ||
28e97307 DJ |
2712 | /* Record additional information about the architecture we are defining. |
2713 | These are gdbarch discriminators, like the OSABI. */ | |
2714 | tdep->arm_abi = arm_abi; | |
2715 | tdep->fp_model = fp_model; | |
08216dd7 RE |
2716 | |
2717 | /* Breakpoints. */ | |
67255d04 RE |
2718 | switch (info.byte_order) |
2719 | { | |
2720 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2721 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2722 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2723 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2724 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2725 | ||
67255d04 RE |
2726 | break; |
2727 | ||
2728 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2729 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2730 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2731 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2732 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2733 | ||
67255d04 RE |
2734 | break; |
2735 | ||
2736 | default: | |
2737 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2738 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2739 | } |
2740 | ||
d7b486e7 RE |
2741 | /* On ARM targets char defaults to unsigned. */ |
2742 | set_gdbarch_char_signed (gdbarch, 0); | |
2743 | ||
9df628e0 | 2744 | /* This should be low enough for everything. */ |
97e03143 | 2745 | tdep->lowest_pc = 0x20; |
94c30b78 | 2746 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2747 | |
2dd604e7 | 2748 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 2749 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 2750 | |
756fe439 DJ |
2751 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2752 | ||
148754e5 | 2753 | /* Frame handling. */ |
eb5492fa DJ |
2754 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2755 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2756 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2757 | ||
eb5492fa | 2758 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2759 | |
34e8f22d RE |
2760 | /* Address manipulation. */ |
2761 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2762 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2763 | ||
34e8f22d RE |
2764 | /* Advance PC across function entry code. */ |
2765 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2766 | ||
2767 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2768 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2769 | |
2770 | /* The stack grows downward. */ | |
2771 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2772 | ||
2773 | /* Breakpoint manipulation. */ | |
2774 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2775 | |
2776 | /* Information about registers, etc. */ | |
2777 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2778 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2779 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2780 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2781 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2782 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2783 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2784 | |
26216b98 AC |
2785 | /* Internal <-> external register number maps. */ |
2786 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2787 | ||
34e8f22d | 2788 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2789 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2790 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2791 | ||
2792 | /* Returning results. */ | |
2af48f68 | 2793 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d RE |
2794 | |
2795 | /* Single stepping. */ | |
2796 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2797 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2798 | ||
03d48a7d RE |
2799 | /* Disassembly. */ |
2800 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2801 | ||
34e8f22d RE |
2802 | /* Minsymbol frobbing. */ |
2803 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2804 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2805 | arm_coff_make_msymbol_special); | |
2806 | ||
97e03143 | 2807 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2808 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2809 | |
eb5492fa | 2810 | /* Add some default predicates. */ |
909cf6ea | 2811 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
842e1f1e | 2812 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2813 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2814 | ||
97e03143 RE |
2815 | /* Now we have tuned the configuration, set a few final things, |
2816 | based on what the OS ABI has told us. */ | |
2817 | ||
9df628e0 RE |
2818 | if (tdep->jb_pc >= 0) |
2819 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2820 | ||
08216dd7 RE |
2821 | /* Floating point sizes and format. */ |
2822 | switch (info.byte_order) | |
2823 | { | |
2824 | case BFD_ENDIAN_BIG: | |
2825 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2826 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2827 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
08216dd7 RE |
2828 | break; |
2829 | ||
2830 | case BFD_ENDIAN_LITTLE: | |
2831 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
28e97307 DJ |
2832 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
2833 | { | |
2834 | set_gdbarch_double_format | |
2835 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2836 | set_gdbarch_long_double_format | |
2837 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2838 | } | |
2839 | else | |
2840 | { | |
2841 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2842 | set_gdbarch_long_double_format (gdbarch, | |
2843 | &floatformat_ieee_double_little); | |
2844 | } | |
08216dd7 RE |
2845 | break; |
2846 | ||
2847 | default: | |
2848 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2849 | _("arm_gdbarch_init: bad byte order for float format")); |
08216dd7 RE |
2850 | } |
2851 | ||
39bbf761 RE |
2852 | return gdbarch; |
2853 | } | |
2854 | ||
97e03143 RE |
2855 | static void |
2856 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2857 | { | |
2858 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2859 | ||
2860 | if (tdep == NULL) | |
2861 | return; | |
2862 | ||
edefbb7c | 2863 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
2864 | (unsigned long) tdep->lowest_pc); |
2865 | } | |
2866 | ||
a78f21af AC |
2867 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2868 | ||
c906108c | 2869 | void |
ed9a39eb | 2870 | _initialize_arm_tdep (void) |
c906108c | 2871 | { |
bc90b915 FN |
2872 | struct ui_file *stb; |
2873 | long length; | |
26304000 | 2874 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2875 | const char *setname; |
2876 | const char *setdesc; | |
4bd7b427 | 2877 | const char *const *regnames; |
bc90b915 FN |
2878 | int numregs, i, j; |
2879 | static char *helptext; | |
edefbb7c AC |
2880 | char regdesc[1024], *rdptr = regdesc; |
2881 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 2882 | |
42cf1509 | 2883 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2884 | |
70f80edf JT |
2885 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2886 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2887 | bfd_target_elf_flavour, | |
2888 | arm_elf_osabi_sniffer); | |
2889 | ||
94c30b78 | 2890 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2891 | num_disassembly_options = get_arm_regname_num_options (); |
2892 | ||
2893 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2894 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 2895 | _("Various ARM-specific commands."), |
afd7eef0 RE |
2896 | &setarmcmdlist, "set arm ", 0, &setlist); |
2897 | ||
2898 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 2899 | _("Various ARM-specific commands."), |
afd7eef0 | 2900 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 2901 | |
94c30b78 | 2902 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2903 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2904 | |
eefe576e AC |
2905 | /* Initialize the array that will be passed to |
2906 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
2907 | valid_disassembly_styles |
2908 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2909 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2910 | { |
2911 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2912 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
2913 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
2914 | rdptr += length; | |
2915 | rest -= length; | |
94c30b78 | 2916 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2917 | if (!strcmp (setname, "std")) |
2918 | { | |
afd7eef0 | 2919 | disassembly_style = setname; |
bc90b915 FN |
2920 | current_option = i; |
2921 | for (j = 0; j < numregs; j++) | |
2922 | arm_register_names[j] = (char *) regnames[j]; | |
2923 | set_arm_regname_option (i); | |
2924 | } | |
2925 | } | |
94c30b78 | 2926 | /* Mark the end of valid options. */ |
afd7eef0 | 2927 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2928 | |
edefbb7c AC |
2929 | /* Create the help text. */ |
2930 | stb = mem_fileopen (); | |
2931 | fprintf_unfiltered (stb, "%s%s%s", | |
2932 | _("The valid values are:\n"), | |
2933 | regdesc, | |
2934 | _("The default is \"std\".")); | |
bc90b915 FN |
2935 | helptext = ui_file_xstrdup (stb, &length); |
2936 | ui_file_delete (stb); | |
ed9a39eb | 2937 | |
edefbb7c AC |
2938 | add_setshow_enum_cmd("disassembler", no_class, |
2939 | valid_disassembly_styles, &disassembly_style, | |
2940 | _("Set the disassembly style."), | |
2941 | _("Show the disassembly style."), | |
2942 | helptext, | |
2c5b56ce | 2943 | set_disassembly_style_sfunc, |
7915a72c | 2944 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 2945 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
2946 | |
2947 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2948 | _("Set usage of ARM 32-bit mode."), | |
2949 | _("Show usage of ARM 32-bit mode."), | |
2950 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 2951 | NULL, |
7915a72c | 2952 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 2953 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 2954 | |
fd50bc42 | 2955 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
2956 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
2957 | _("Set the floating point type."), | |
2958 | _("Show the floating point type."), | |
2959 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
2960 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
2961 | fpa - FPA co-processor (GCC compiled).\n\ | |
2962 | softvfp - Software FP with pure-endian doubles.\n\ | |
2963 | vfp - VFP co-processor."), | |
edefbb7c | 2964 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 2965 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 2966 | |
28e97307 DJ |
2967 | /* Add a command to allow the user to force the ABI. */ |
2968 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
2969 | _("Set the ABI."), | |
2970 | _("Show the ABI."), | |
2971 | NULL, arm_set_abi, arm_show_abi, | |
2972 | &setarmcmdlist, &showarmcmdlist); | |
2973 | ||
6529d2dd | 2974 | /* Debugging flag. */ |
edefbb7c AC |
2975 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2976 | _("Set ARM debugging."), | |
2977 | _("Show ARM debugging."), | |
2978 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 2979 | NULL, |
7915a72c | 2980 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 2981 | &setdebuglist, &showdebuglist); |
c906108c | 2982 | } |