Commit | Line | Data |
---|---|---|
7a292a7a SS |
1 | /* Target-dependent code for the Acorn Risc Machine (ARM). |
2 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995-1999 | |
c906108c SS |
3 | Free Software Foundation, Inc. |
4 | ||
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "gdb_string.h" | |
29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
30 | ||
31 | /* | |
c5aa993b JM |
32 | The following macros are actually wrong. Neither arm nor thumb can |
33 | or should set the lsb on addr. | |
34 | The thumb addresses are mod 2, so (addr & 2) would be a good heuristic | |
35 | to use when checking for thumb (see arm_pc_is_thumb() below). | |
36 | Unfortunately, something else depends on these (incorrect) macros, so | |
37 | fixing them actually breaks gdb. I didn't have time to investigate. Z.R. | |
38 | */ | |
c906108c SS |
39 | /* Thumb function addresses are odd (bit 0 is set). Here are some |
40 | macros to test, set, or clear bit 0 of addresses. */ | |
41 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
42 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
43 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
44 | ||
45 | /* Macros to round N up or down to the next A boundary; A must be | |
46 | a power of two. */ | |
47 | #define ROUND_DOWN(n,a) ((n) & ~((a) - 1)) | |
48 | #define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1)) | |
085dd6e6 JM |
49 | |
50 | static char *APCS_register_names[] = | |
c5aa993b JM |
51 | {"a1", "a2", "a3", "a4", /* 0 1 2 3 */ |
52 | "v1", "v2", "v3", "v4", /* 4 5 6 7 */ | |
53 | "v5", "v6", "sl", "fp", /* 8 9 10 11 */ | |
54 | "ip", "sp", "lr", "pc", /* 12 13 14 15 */ | |
55 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
56 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
57 | "fps", "ps"} /* 24 25 */ ; | |
085dd6e6 JM |
58 | |
59 | /* These names are the ones which gcc emits, and | |
60 | I find them less confusing. Toggle between them | |
61 | using the `othernames' command. */ | |
62 | static char *additional_register_names[] = | |
c5aa993b JM |
63 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
64 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
65 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
66 | "r12", "r13", "r14", "pc", /* 12 13 14 15 */ | |
67 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
68 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
69 | "fps", "ps"} /* 24 25 */ ; | |
085dd6e6 JM |
70 | |
71 | /* By default use the APCS registers names */ | |
72 | ||
73 | char **arm_register_names = APCS_register_names; | |
74 | ||
c906108c SS |
75 | /* Should call_function allocate stack space for a struct return? */ |
76 | /* The system C compiler uses a similar structure return convention to gcc */ | |
77 | int | |
78 | arm_use_struct_convention (gcc_p, type) | |
79 | int gcc_p; | |
80 | struct type *type; | |
81 | { | |
82 | return (TYPE_LENGTH (type) > 4); | |
83 | } | |
84 | ||
85 | int | |
86 | arm_frame_chain_valid (chain, thisframe) | |
87 | CORE_ADDR chain; | |
88 | struct frame_info *thisframe; | |
89 | { | |
c5aa993b | 90 | #define LOWEST_PC 0x20 /* the first 0x20 bytes are the trap vectors. */ |
c906108c SS |
91 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
92 | } | |
93 | ||
94 | /* Set to true if the 32-bit mode is in use. */ | |
95 | ||
96 | int arm_apcs_32 = 1; | |
97 | ||
98 | /* Flag set by arm_fix_call_dummy that tells whether the target function | |
99 | is a Thumb function. This flag is checked by arm_push_arguments. | |
100 | FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to | |
101 | pass the function address as an additional parameter. */ | |
102 | ||
103 | static int target_is_thumb; | |
104 | ||
105 | /* Flag set by arm_fix_call_dummy that tells whether the calling function | |
106 | is a Thumb function. This flag is checked by arm_pc_is_thumb | |
107 | and arm_call_dummy_breakpoint_offset. */ | |
108 | ||
109 | static int caller_is_thumb; | |
110 | ||
111 | /* Tell if the program counter value in MEMADDR is in a Thumb function. */ | |
112 | ||
113 | int | |
114 | arm_pc_is_thumb (memaddr) | |
115 | bfd_vma memaddr; | |
116 | { | |
c5aa993b | 117 | struct minimal_symbol *sym; |
c906108c SS |
118 | CORE_ADDR sp; |
119 | ||
120 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
121 | if (IS_THUMB_ADDR (memaddr)) | |
122 | return 1; | |
123 | ||
124 | /* Thumb function have a "special" bit set in minimal symbols */ | |
125 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
126 | if (sym) | |
127 | { | |
c5aa993b | 128 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
129 | } |
130 | else | |
131 | return 0; | |
132 | } | |
133 | ||
134 | /* Tell if the program counter value in MEMADDR is in a call dummy that | |
135 | is being called from a Thumb function. */ | |
136 | ||
137 | int | |
138 | arm_pc_is_thumb_dummy (memaddr) | |
139 | bfd_vma memaddr; | |
140 | { | |
c5aa993b | 141 | CORE_ADDR sp = read_sp (); |
c906108c | 142 | |
c5aa993b | 143 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 64)) |
c906108c SS |
144 | return caller_is_thumb; |
145 | else | |
146 | return 0; | |
147 | } | |
148 | ||
149 | CORE_ADDR | |
150 | arm_addr_bits_remove (val) | |
151 | CORE_ADDR val; | |
152 | { | |
153 | if (arm_pc_is_thumb (val)) | |
154 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
155 | else | |
156 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
157 | } | |
158 | ||
159 | CORE_ADDR | |
160 | arm_saved_pc_after_call (frame) | |
161 | struct frame_info *frame; | |
162 | { | |
163 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
164 | } | |
165 | ||
392a587b JM |
166 | int |
167 | arm_frameless_function_invocation (fi) | |
168 | struct frame_info *fi; | |
169 | { | |
170 | int frameless; | |
171 | CORE_ADDR func_start, after_prologue; | |
172 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); | |
173 | after_prologue = func_start; | |
174 | SKIP_PROLOGUE (after_prologue); | |
175 | frameless = (after_prologue == func_start); | |
176 | return frameless; | |
177 | } | |
178 | ||
c906108c | 179 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
180 | push {r7, lr} |
181 | add sp, sp, #-28 | |
182 | add r7, sp, #12 | |
c906108c | 183 | Sometimes the latter instruction may be replaced by: |
c5aa993b JM |
184 | mov r7, sp |
185 | */ | |
c906108c SS |
186 | |
187 | static CORE_ADDR | |
188 | thumb_skip_prologue (pc) | |
189 | CORE_ADDR pc; | |
190 | { | |
191 | CORE_ADDR current_pc; | |
192 | ||
193 | for (current_pc = pc; current_pc < pc + 20; current_pc += 2) | |
194 | { | |
195 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
196 | ||
c5aa993b JM |
197 | if ((insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ |
198 | && (insn & 0xff00) != 0xb000 /* add sp, #simm */ | |
199 | && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ | |
200 | && insn != 0x466f /* mov r7, sp */ | |
c906108c SS |
201 | && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ |
202 | break; | |
203 | } | |
204 | ||
205 | return current_pc; | |
206 | } | |
207 | ||
208 | /* APCS (ARM procedure call standard) defines the following prologue: | |
209 | ||
c5aa993b JM |
210 | mov ip, sp |
211 | [stmfd sp!, {a1,a2,a3,a4}] | |
212 | stmfd sp!, {...,fp,ip,lr,pc} | |
213 | [stfe f7, [sp, #-12]!] | |
214 | [stfe f6, [sp, #-12]!] | |
215 | [stfe f5, [sp, #-12]!] | |
216 | [stfe f4, [sp, #-12]!] | |
217 | sub fp, ip, #nn // nn == 20 or 4 depending on second ins | |
218 | */ | |
c906108c SS |
219 | |
220 | CORE_ADDR | |
221 | arm_skip_prologue (pc) | |
222 | CORE_ADDR pc; | |
223 | { | |
224 | unsigned long inst; | |
225 | CORE_ADDR skip_pc; | |
226 | CORE_ADDR func_addr, func_end; | |
227 | struct symtab_and_line sal; | |
228 | ||
229 | /* See what the symbol table says. */ | |
c5aa993b | 230 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c906108c SS |
231 | { |
232 | sal = find_pc_line (func_addr, 0); | |
233 | if (sal.line != 0 && sal.end < func_end) | |
234 | return sal.end; | |
235 | } | |
236 | ||
237 | /* Check if this is Thumb code. */ | |
238 | if (arm_pc_is_thumb (pc)) | |
239 | return thumb_skip_prologue (pc); | |
240 | ||
241 | /* Can't find the prologue end in the symbol table, try it the hard way | |
242 | by disassembling the instructions. */ | |
243 | skip_pc = pc; | |
244 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 245 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
246 | return pc; |
247 | ||
248 | skip_pc += 4; | |
249 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 250 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
251 | { |
252 | skip_pc += 4; | |
253 | inst = read_memory_integer (skip_pc, 4); | |
254 | } | |
255 | ||
c5aa993b | 256 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
257 | return pc; |
258 | ||
259 | skip_pc += 4; | |
260 | inst = read_memory_integer (skip_pc, 4); | |
261 | ||
262 | /* Any insns after this point may float into the code, if it makes | |
263 | for better instruction scheduling, so we skip them only if | |
264 | we find them, but still consdier the function to be frame-ful */ | |
265 | ||
266 | /* We may have either one sfmfd instruction here, or several stfe insns, | |
267 | depending on the version of floating point code we support. */ | |
c5aa993b | 268 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
269 | { |
270 | skip_pc += 4; | |
271 | inst = read_memory_integer (skip_pc, 4); | |
272 | } | |
273 | else | |
274 | { | |
c5aa993b JM |
275 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
276 | { | |
277 | skip_pc += 4; | |
278 | inst = read_memory_integer (skip_pc, 4); | |
279 | } | |
c906108c SS |
280 | } |
281 | ||
c5aa993b | 282 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
283 | skip_pc += 4; |
284 | ||
285 | return skip_pc; | |
286 | } | |
c5aa993b | 287 | /* *INDENT-OFF* */ |
c906108c SS |
288 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
289 | This function decodes a Thumb function prologue to determine: | |
290 | 1) the size of the stack frame | |
291 | 2) which registers are saved on it | |
292 | 3) the offsets of saved regs | |
293 | 4) the offset from the stack pointer to the frame pointer | |
294 | This information is stored in the "extra" fields of the frame_info. | |
295 | ||
296 | A typical Thumb function prologue might look like this: | |
297 | push {r7, lr} | |
298 | sub sp, #28, | |
299 | add r7, sp, #12 | |
300 | Which would create this stack frame (offsets relative to FP) | |
301 | old SP -> 24 stack parameters | |
302 | 20 LR | |
303 | 16 R7 | |
304 | R7 -> 0 local variables (16 bytes) | |
305 | SP -> -12 additional stack space (12 bytes) | |
306 | The frame size would thus be 36 bytes, and the frame offset would be | |
307 | 12 bytes. The frame register is R7. */ | |
c5aa993b JM |
308 | /* *INDENT-ON* */ |
309 | ||
310 | ||
311 | ||
312 | ||
c906108c SS |
313 | static void |
314 | thumb_scan_prologue (fi) | |
c5aa993b | 315 | struct frame_info *fi; |
c906108c SS |
316 | { |
317 | CORE_ADDR prologue_start; | |
318 | CORE_ADDR prologue_end; | |
319 | CORE_ADDR current_pc; | |
c5aa993b JM |
320 | int saved_reg[16]; /* which register has been copied to register n? */ |
321 | int i; | |
c906108c | 322 | |
c5aa993b | 323 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
324 | { |
325 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
326 | ||
c5aa993b | 327 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
328 | prologue_end = fi->pc; |
329 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 330 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
331 | } |
332 | else | |
c5aa993b JM |
333 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
334 | /* 16 pushes, an add, and "mv fp,sp" */ | |
c906108c SS |
335 | |
336 | prologue_end = min (prologue_end, fi->pc); | |
337 | ||
338 | /* Initialize the saved register map. When register H is copied to | |
339 | register L, we will put H in saved_reg[L]. */ | |
340 | for (i = 0; i < 16; i++) | |
341 | saved_reg[i] = i; | |
342 | ||
343 | /* Search the prologue looking for instructions that set up the | |
344 | frame pointer, adjust the stack pointer, and save registers. */ | |
345 | ||
346 | fi->framesize = 0; | |
347 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 2) | |
348 | { | |
349 | unsigned short insn; | |
350 | int regno; | |
351 | int offset; | |
352 | ||
353 | insn = read_memory_unsigned_integer (current_pc, 2); | |
354 | ||
c5aa993b | 355 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c SS |
356 | { |
357 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
358 | whether to save LR (R14). */ | |
359 | int mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
360 | ||
361 | /* Calculate offsets of saved R0-R7 and LR. */ | |
362 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
363 | if (mask & (1 << regno)) | |
c5aa993b | 364 | { |
c906108c SS |
365 | fi->framesize += 4; |
366 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); | |
367 | saved_reg[regno] = regno; /* reset saved register map */ | |
368 | } | |
369 | } | |
370 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm */ | |
371 | { | |
c5aa993b JM |
372 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
373 | if (insn & 0x80) /* is it signed? */ | |
374 | offset = -offset; | |
c906108c SS |
375 | fi->framesize -= offset; |
376 | } | |
377 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
378 | { | |
379 | fi->framereg = THUMB_FP_REGNUM; | |
c5aa993b | 380 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ |
c906108c | 381 | } |
c5aa993b | 382 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c SS |
383 | { |
384 | fi->framereg = THUMB_FP_REGNUM; | |
385 | fi->frameoffset = 0; | |
386 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; | |
387 | } | |
388 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
389 | { | |
c5aa993b | 390 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 391 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 392 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
393 | } |
394 | else | |
c5aa993b | 395 | break; /* anything else isn't prologue */ |
c906108c SS |
396 | } |
397 | } | |
398 | ||
399 | /* Function: check_prologue_cache | |
400 | Check if prologue for this frame's PC has already been scanned. | |
401 | If it has, copy the relevant information about that prologue and | |
402 | return non-zero. Otherwise do not copy anything and return zero. | |
403 | ||
404 | The information saved in the cache includes: | |
c5aa993b JM |
405 | * the frame register number; |
406 | * the size of the stack frame; | |
407 | * the offsets of saved regs (relative to the old SP); and | |
408 | * the offset from the stack pointer to the frame pointer | |
c906108c SS |
409 | |
410 | The cache contains only one entry, since this is adequate | |
411 | for the typical sequence of prologue scan requests we get. | |
412 | When performing a backtrace, GDB will usually ask to scan | |
413 | the same function twice in a row (once to get the frame chain, | |
414 | and once to fill in the extra frame information). | |
c5aa993b | 415 | */ |
c906108c SS |
416 | |
417 | static struct frame_info prologue_cache; | |
418 | ||
419 | static int | |
420 | check_prologue_cache (fi) | |
c5aa993b | 421 | struct frame_info *fi; |
c906108c SS |
422 | { |
423 | int i; | |
424 | ||
425 | if (fi->pc == prologue_cache.pc) | |
426 | { | |
427 | fi->framereg = prologue_cache.framereg; | |
428 | fi->framesize = prologue_cache.framesize; | |
429 | fi->frameoffset = prologue_cache.frameoffset; | |
430 | for (i = 0; i <= NUM_REGS; i++) | |
431 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; | |
432 | return 1; | |
433 | } | |
434 | else | |
435 | return 0; | |
436 | } | |
437 | ||
438 | ||
439 | /* Function: save_prologue_cache | |
440 | Copy the prologue information from fi to the prologue cache. | |
c5aa993b | 441 | */ |
c906108c SS |
442 | |
443 | static void | |
444 | save_prologue_cache (fi) | |
c5aa993b | 445 | struct frame_info *fi; |
c906108c SS |
446 | { |
447 | int i; | |
448 | ||
c5aa993b JM |
449 | prologue_cache.pc = fi->pc; |
450 | prologue_cache.framereg = fi->framereg; | |
451 | prologue_cache.framesize = fi->framesize; | |
c906108c | 452 | prologue_cache.frameoffset = fi->frameoffset; |
c5aa993b | 453 | |
c906108c SS |
454 | for (i = 0; i <= NUM_REGS; i++) |
455 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; | |
456 | } | |
457 | ||
458 | ||
459 | /* Function: arm_scan_prologue | |
460 | This function decodes an ARM function prologue to determine: | |
c5aa993b JM |
461 | 1) the size of the stack frame |
462 | 2) which registers are saved on it | |
463 | 3) the offsets of saved regs | |
464 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
465 | This information is stored in the "extra" fields of the frame_info. |
466 | ||
467 | A typical Arm function prologue might look like this: | |
c5aa993b JM |
468 | mov ip, sp |
469 | stmfd sp!, {fp, ip, lr, pc} | |
470 | sub fp, ip, #4 | |
471 | sub sp, sp, #16 | |
c906108c | 472 | Which would create this stack frame (offsets relative to FP): |
c5aa993b JM |
473 | IP -> 4 (caller's stack) |
474 | FP -> 0 PC (points to address of stmfd instruction + 12 in callee) | |
475 | -4 LR (return address in caller) | |
476 | -8 IP (copy of caller's SP) | |
477 | -12 FP (caller's FP) | |
478 | SP -> -28 Local variables | |
c906108c SS |
479 | The frame size would thus be 32 bytes, and the frame offset would be |
480 | 28 bytes. */ | |
481 | ||
482 | static void | |
483 | arm_scan_prologue (fi) | |
c5aa993b | 484 | struct frame_info *fi; |
c906108c SS |
485 | { |
486 | int regno, sp_offset, fp_offset; | |
487 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
488 | ||
489 | /* Check if this function is already in the cache of frame information. */ | |
490 | if (check_prologue_cache (fi)) | |
491 | return; | |
492 | ||
493 | /* Assume there is no frame until proven otherwise. */ | |
c5aa993b JM |
494 | fi->framereg = SP_REGNUM; |
495 | fi->framesize = 0; | |
c906108c SS |
496 | fi->frameoffset = 0; |
497 | ||
498 | /* Check for Thumb prologue. */ | |
499 | if (arm_pc_is_thumb (fi->pc)) | |
500 | { | |
501 | thumb_scan_prologue (fi); | |
502 | save_prologue_cache (fi); | |
503 | return; | |
504 | } | |
505 | ||
506 | /* Find the function prologue. If we can't find the function in | |
507 | the symbol table, peek in the stack frame to find the PC. */ | |
508 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
509 | { | |
510 | /* Assume the prologue is everything between the first instruction | |
511 | in the function and the first source line. */ | |
512 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
513 | ||
c5aa993b | 514 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
515 | prologue_end = fi->pc; |
516 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 517 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
518 | } |
519 | else | |
520 | { | |
521 | /* Get address of the stmfd in the prologue of the callee; the saved | |
522 | PC is the address of the stmfd + 12. */ | |
c5aa993b JM |
523 | prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4)) - 12; |
524 | prologue_end = prologue_start + 40; /* FIXME: should be big enough */ | |
c906108c SS |
525 | } |
526 | ||
527 | /* Now search the prologue looking for instructions that set up the | |
528 | frame pointer, adjust the stack pointer, and save registers. */ | |
529 | ||
530 | sp_offset = fp_offset = 0; | |
531 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 4) | |
532 | { | |
533 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); | |
534 | ||
535 | if ((insn & 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., r7, lr} */ | |
536 | { | |
537 | int mask = insn & 0xffff; | |
538 | ||
539 | /* Calculate offsets of saved registers. */ | |
540 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
541 | if (mask & (1 << regno)) | |
542 | { | |
543 | sp_offset -= 4; | |
544 | fi->fsr.regs[regno] = sp_offset; | |
545 | } | |
546 | } | |
547 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
548 | { | |
c5aa993b JM |
549 | unsigned imm = insn & 0xff; /* immediate value */ |
550 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
551 | imm = (imm >> rot) | (imm << (32 - rot)); | |
c906108c SS |
552 | fp_offset = -imm; |
553 | fi->framereg = FP_REGNUM; | |
554 | } | |
555 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
556 | { | |
c5aa993b JM |
557 | unsigned imm = insn & 0xff; /* immediate value */ |
558 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
559 | imm = (imm >> rot) | (imm << (32 - rot)); | |
c906108c SS |
560 | sp_offset -= imm; |
561 | } | |
c5aa993b | 562 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
c906108c SS |
563 | { |
564 | sp_offset -= 12; | |
565 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
566 | fi->fsr.regs[regno] = sp_offset; | |
567 | } | |
c5aa993b | 568 | else if (insn == 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
569 | continue; |
570 | else | |
c5aa993b | 571 | break; /* not a recognized prologue instruction */ |
c906108c SS |
572 | } |
573 | ||
574 | /* The frame size is just the negative of the offset (from the original SP) | |
575 | of the last thing thing we pushed on the stack. The frame offset is | |
576 | [new FP] - [new SP]. */ | |
577 | fi->framesize = -sp_offset; | |
578 | fi->frameoffset = fp_offset - sp_offset; | |
c5aa993b | 579 | |
c906108c SS |
580 | save_prologue_cache (fi); |
581 | } | |
582 | ||
583 | ||
584 | /* Function: find_callers_reg | |
585 | Find REGNUM on the stack. Otherwise, it's in an active register. One thing | |
586 | we might want to do here is to check REGNUM against the clobber mask, and | |
587 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
588 | would provide a graceful failure mode when trying to get the value of | |
589 | caller-saves registers for an inner frame. */ | |
590 | ||
591 | static CORE_ADDR | |
592 | arm_find_callers_reg (fi, regnum) | |
c5aa993b | 593 | struct frame_info *fi; |
c906108c SS |
594 | int regnum; |
595 | { | |
596 | for (; fi; fi = fi->next) | |
c5aa993b JM |
597 | |
598 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
c906108c SS |
599 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
600 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
601 | else | |
602 | #endif | |
c5aa993b JM |
603 | if (fi->fsr.regs[regnum] != 0) |
604 | return read_memory_integer (fi->fsr.regs[regnum], | |
605 | REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
606 | return read_register (regnum); |
607 | } | |
c5aa993b | 608 | /* *INDENT-OFF* */ |
c906108c SS |
609 | /* Function: frame_chain |
610 | Given a GDB frame, determine the address of the calling function's frame. | |
611 | This will be used to create a new GDB frame struct, and then | |
612 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
613 | For ARM, we save the frame size when we initialize the frame_info. | |
614 | ||
615 | The original definition of this function was a macro in tm-arm.h: | |
616 | { In the case of the ARM, the frame's nominal address is the FP value, | |
617 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
618 | ||
619 | #define FRAME_CHAIN(thisframe) \ | |
620 | ((thisframe)->pc >= LOWEST_PC ? \ | |
621 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
622 | 0) | |
623 | */ | |
c5aa993b JM |
624 | /* *INDENT-ON* */ |
625 | ||
626 | ||
627 | ||
c906108c SS |
628 | |
629 | CORE_ADDR | |
630 | arm_frame_chain (fi) | |
c5aa993b | 631 | struct frame_info *fi; |
c906108c | 632 | { |
c5aa993b | 633 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
634 | CORE_ADDR fn_start, callers_pc, fp; |
635 | ||
636 | /* is this a dummy frame? */ | |
637 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 638 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
639 | |
640 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 641 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
c906108c | 642 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
c5aa993b JM |
643 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
644 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
645 | |
646 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
647 | if (fn_start == entry_point_address ()) | |
c5aa993b | 648 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
649 | #endif |
650 | CORE_ADDR caller_pc, fn_start; | |
651 | struct frame_info caller_fi; | |
652 | int framereg = fi->framereg; | |
653 | ||
654 | if (fi->pc < LOWEST_PC) | |
655 | return 0; | |
656 | ||
657 | /* If the caller is the startup code, we're at the end of the chain. */ | |
658 | caller_pc = FRAME_SAVED_PC (fi); | |
659 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
660 | if (fn_start == entry_point_address ()) | |
661 | return 0; | |
662 | ||
663 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
664 | the frame register of the caller is different from ours. | |
665 | So we must scan the prologue of the caller to determine its | |
666 | frame register number. */ | |
667 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) | |
668 | { | |
c5aa993b | 669 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c906108c | 670 | caller_fi.pc = caller_pc; |
c5aa993b | 671 | arm_scan_prologue (&caller_fi); |
c906108c SS |
672 | framereg = caller_fi.framereg; |
673 | } | |
674 | ||
675 | /* If the caller used a frame register, return its value. | |
676 | Otherwise, return the caller's stack pointer. */ | |
677 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
678 | return arm_find_callers_reg (fi, framereg); | |
679 | else | |
680 | return fi->frame + fi->framesize; | |
681 | } | |
682 | ||
683 | /* Function: init_extra_frame_info | |
684 | This function actually figures out the frame address for a given pc and | |
685 | sp. This is tricky because we sometimes don't use an explicit | |
686 | frame pointer, and the previous stack pointer isn't necessarily recorded | |
687 | on the stack. The only reliable way to get this info is to | |
688 | examine the prologue. */ | |
689 | ||
690 | void | |
691 | arm_init_extra_frame_info (fi) | |
c5aa993b | 692 | struct frame_info *fi; |
c906108c SS |
693 | { |
694 | int reg; | |
695 | ||
696 | if (fi->next) | |
697 | fi->pc = FRAME_SAVED_PC (fi->next); | |
698 | ||
699 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); | |
700 | ||
c5aa993b | 701 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
702 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
703 | { | |
704 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
705 | by assuming it's always FP. */ |
706 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
707 | fi->framesize = 0; | |
c906108c SS |
708 | fi->frameoffset = 0; |
709 | return; | |
710 | } | |
c5aa993b | 711 | else |
c906108c SS |
712 | #endif |
713 | { | |
714 | arm_scan_prologue (fi); | |
715 | ||
c5aa993b | 716 | if (!fi->next) /* this is the innermost frame? */ |
c906108c | 717 | fi->frame = read_register (fi->framereg); |
c5aa993b JM |
718 | else |
719 | /* not the innermost frame */ | |
720 | /* If we have an FP, the callee saved it. */ if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) | |
721 | if (fi->next->fsr.regs[fi->framereg] != 0) | |
722 | fi->frame = read_memory_integer (fi->next->fsr.regs[fi->framereg], | |
723 | 4); | |
c906108c SS |
724 | |
725 | /* Calculate actual addresses of saved registers using offsets determined | |
726 | by arm_scan_prologue. */ | |
727 | for (reg = 0; reg < NUM_REGS; reg++) | |
728 | if (fi->fsr.regs[reg] != 0) | |
729 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; | |
730 | } | |
731 | } | |
732 | ||
733 | ||
734 | /* Function: frame_saved_pc | |
735 | Find the caller of this frame. We do this by seeing if LR_REGNUM is saved | |
736 | in the stack anywhere, otherwise we get it from the registers. | |
737 | ||
738 | The old definition of this function was a macro: | |
c5aa993b JM |
739 | #define FRAME_SAVED_PC(FRAME) \ |
740 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) | |
741 | */ | |
c906108c SS |
742 | |
743 | CORE_ADDR | |
744 | arm_frame_saved_pc (fi) | |
c5aa993b | 745 | struct frame_info *fi; |
c906108c | 746 | { |
c5aa993b | 747 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
748 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
749 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
750 | else | |
751 | #endif | |
752 | { | |
753 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
754 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
755 | } | |
756 | } | |
757 | ||
758 | ||
759 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. | |
760 | Examine the Program Status Register to decide which state we're in. */ | |
761 | ||
762 | CORE_ADDR | |
763 | arm_target_read_fp () | |
764 | { | |
765 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
766 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
767 | else | |
c5aa993b | 768 | return read_register (FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
769 | } |
770 | ||
771 | ||
772 | /* Calculate the frame offsets of the saved registers (ARM version). */ | |
773 | void | |
774 | arm_frame_find_saved_regs (fi, regaddr) | |
775 | struct frame_info *fi; | |
776 | struct frame_saved_regs *regaddr; | |
777 | { | |
778 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); | |
779 | } | |
780 | ||
781 | ||
782 | void | |
783 | arm_push_dummy_frame () | |
784 | { | |
785 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
786 | CORE_ADDR sp = old_sp; | |
787 | CORE_ADDR fp, prologue_start; | |
788 | int regnum; | |
789 | ||
790 | /* Push the two dummy prologue instructions in reverse order, | |
791 | so that they'll be in the correct low-to-high order in memory. */ | |
792 | /* sub fp, ip, #4 */ | |
793 | sp = push_word (sp, 0xe24cb004); | |
794 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
795 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
796 | ||
797 | /* push a pointer to the dummy prologue + 12, because when | |
798 | stm instruction stores the PC, it stores the address of the stm | |
799 | instruction itself plus 12. */ | |
800 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 801 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ |
c906108c SS |
802 | sp = push_word (sp, old_sp); |
803 | sp = push_word (sp, read_register (FP_REGNUM)); | |
c5aa993b JM |
804 | |
805 | for (regnum = 10; regnum >= 0; regnum--) | |
c906108c | 806 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 807 | |
c906108c SS |
808 | write_register (FP_REGNUM, fp); |
809 | write_register (THUMB_FP_REGNUM, fp); | |
810 | write_register (SP_REGNUM, sp); | |
811 | } | |
812 | ||
813 | /* Fix up the call dummy, based on whether the processor is currently | |
814 | in Thumb or ARM mode, and whether the target function is Thumb | |
815 | or ARM. There are three different situations requiring three | |
816 | different dummies: | |
817 | ||
818 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 819 | been copied into the dummy parameter to this function. |
c906108c | 820 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 821 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 822 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 823 | works for calling both ARM and Thumb functions. |
c906108c SS |
824 | |
825 | All three call dummies expect to receive the target function address | |
826 | in R4, with the low bit set if it's a Thumb function. | |
c5aa993b | 827 | */ |
c906108c SS |
828 | |
829 | void | |
830 | arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) | |
c5aa993b JM |
831 | char *dummy; |
832 | CORE_ADDR pc; | |
833 | CORE_ADDR fun; | |
834 | int nargs; | |
835 | value_ptr *args; | |
836 | struct type *type; | |
837 | int gcc_p; | |
c906108c SS |
838 | { |
839 | static short thumb_dummy[4] = | |
840 | { | |
c5aa993b JM |
841 | 0xf000, 0xf801, /* bl label */ |
842 | 0xdf18, /* swi 24 */ | |
843 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
844 | }; |
845 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
846 | ||
847 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 848 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
c906108c SS |
849 | |
850 | /* If the target function is Thumb, set the low bit of the function address. | |
851 | And if the CPU is currently in ARM mode, patch the second instruction | |
852 | of call dummy to use a BX instruction to switch to Thumb mode. */ | |
853 | target_is_thumb = arm_pc_is_thumb (fun); | |
854 | if (target_is_thumb) | |
855 | { | |
856 | fun |= 1; | |
857 | if (!caller_is_thumb) | |
858 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
859 | } | |
860 | ||
861 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
862 | instead of the ARM one that's already been copied. This will | |
863 | work for both Thumb and ARM target functions. */ | |
864 | if (caller_is_thumb) | |
865 | { | |
866 | int i; | |
867 | char *p = dummy; | |
868 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
869 | ||
870 | for (i = 0; i < len; i++) | |
871 | { | |
872 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
873 | p += sizeof (thumb_dummy[0]); | |
874 | } | |
875 | } | |
876 | ||
877 | /* Put the target address in r4; the call dummy will copy this to the PC. */ | |
878 | write_register (4, fun); | |
879 | } | |
880 | ||
881 | ||
882 | /* Return the offset in the call dummy of the instruction that needs | |
883 | to have a breakpoint placed on it. This is the offset of the 'swi 24' | |
884 | instruction, which is no longer actually used, but simply acts | |
885 | as a place-holder now. | |
886 | ||
887 | This implements the CALL_DUMMY_BREAK_OFFSET macro. | |
c5aa993b | 888 | */ |
c906108c SS |
889 | |
890 | int | |
891 | arm_call_dummy_breakpoint_offset () | |
892 | { | |
893 | if (caller_is_thumb) | |
894 | return 4; | |
895 | else | |
896 | return 8; | |
897 | } | |
898 | ||
899 | ||
900 | CORE_ADDR | |
c5aa993b JM |
901 | arm_push_arguments (nargs, args, sp, struct_return, struct_addr) |
902 | int nargs; | |
903 | value_ptr *args; | |
904 | CORE_ADDR sp; | |
905 | int struct_return; | |
906 | CORE_ADDR struct_addr; | |
c906108c SS |
907 | { |
908 | int argreg; | |
909 | int float_argreg; | |
910 | int argnum; | |
911 | int stack_offset; | |
c5aa993b JM |
912 | struct stack_arg |
913 | { | |
c906108c SS |
914 | char *val; |
915 | int len; | |
916 | int offset; | |
917 | }; | |
918 | struct stack_arg *stack_args = | |
c5aa993b | 919 | (struct stack_arg *) alloca (nargs * sizeof (struct stack_arg)); |
c906108c SS |
920 | int nstack_args = 0; |
921 | ||
922 | ||
923 | /* Initialize the integer and float register pointers. */ | |
924 | argreg = A1_REGNUM; | |
925 | float_argreg = F0_REGNUM; | |
926 | ||
927 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
928 | if (struct_return) | |
c5aa993b | 929 | write_register (argreg++, struct_addr); |
c906108c SS |
930 | |
931 | /* The offset onto the stack at which we will start copying parameters | |
932 | (after the registers are used up) begins at 16 in the old ABI. | |
933 | This leaves room for the "home" area for register parameters. */ | |
934 | stack_offset = REGISTER_SIZE * 4; | |
935 | ||
936 | /* Process args from left to right. Store as many as allowed in | |
c5aa993b JM |
937 | registers, save the rest to be pushed on the stack */ |
938 | for (argnum = 0; argnum < nargs; argnum++) | |
c906108c | 939 | { |
c5aa993b JM |
940 | char *val; |
941 | value_ptr arg = args[argnum]; | |
942 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
943 | struct type *target_type = TYPE_TARGET_TYPE (arg_type); | |
944 | int len = TYPE_LENGTH (arg_type); | |
c906108c | 945 | enum type_code typecode = TYPE_CODE (arg_type); |
c5aa993b | 946 | CORE_ADDR regval; |
c906108c SS |
947 | int newarg; |
948 | ||
949 | val = (char *) VALUE_CONTENTS (arg); | |
950 | ||
951 | /* If the argument is a pointer to a function, and it's a Thumb | |
952 | function, set the low bit of the pointer. */ | |
953 | if (typecode == TYPE_CODE_PTR | |
954 | && target_type != NULL | |
955 | && TYPE_CODE (target_type) == TYPE_CODE_FUNC) | |
956 | { | |
957 | regval = extract_address (val, len); | |
958 | if (arm_pc_is_thumb (regval)) | |
959 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
960 | } | |
961 | ||
c5aa993b | 962 | #define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */ |
c906108c SS |
963 | #if MAPCS_FLOAT |
964 | /* Up to four floating point arguments can be passed in floating | |
965 | point registers on ARM (not on Thumb). */ | |
966 | if (typecode == TYPE_CODE_FLT | |
967 | && float_argreg <= ARM_LAST_FP_ARG_REGNUM | |
968 | && !target_is_thumb) | |
969 | { | |
970 | /* This is a floating point value that fits entirely | |
971 | in a single register. */ | |
972 | regval = extract_address (val, len); | |
973 | write_register (float_argreg++, regval); | |
974 | } | |
975 | else | |
976 | #endif | |
977 | { | |
978 | /* Copy the argument to general registers or the stack in | |
979 | register-sized pieces. Large arguments are split between | |
980 | registers and stack. */ | |
981 | while (len > 0) | |
982 | { | |
983 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
984 | { | |
c5aa993b | 985 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
c906108c SS |
986 | regval = extract_address (val, partial_len); |
987 | ||
988 | /* It's a simple argument being passed in a general | |
989 | register. */ | |
990 | write_register (argreg, regval); | |
991 | argreg++; | |
c5aa993b JM |
992 | len -= partial_len; |
993 | val += partial_len; | |
c906108c SS |
994 | } |
995 | else | |
996 | { | |
997 | /* keep for later pushing */ | |
998 | stack_args[nstack_args].val = val; | |
999 | stack_args[nstack_args++].len = len; | |
1000 | break; | |
1001 | } | |
1002 | } | |
1003 | } | |
1004 | } | |
c5aa993b JM |
1005 | /* now do the real stack pushing, process args right to left */ |
1006 | while (nstack_args--) | |
1007 | { | |
1008 | sp -= stack_args[nstack_args].len; | |
1009 | write_memory (sp, stack_args[nstack_args].val, | |
1010 | stack_args[nstack_args].len); | |
1011 | } | |
c906108c SS |
1012 | |
1013 | /* Return adjusted stack pointer. */ | |
1014 | return sp; | |
1015 | } | |
1016 | ||
1017 | void | |
1018 | arm_pop_frame () | |
1019 | { | |
c5aa993b | 1020 | struct frame_info *frame = get_current_frame (); |
c906108c | 1021 | int regnum; |
7a292a7a | 1022 | CORE_ADDR old_SP; |
c906108c | 1023 | |
7a292a7a | 1024 | old_SP = read_register (frame->framereg); |
c906108c SS |
1025 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
1026 | if (frame->fsr.regs[regnum] != 0) | |
c5aa993b | 1027 | write_register (regnum, |
c906108c SS |
1028 | read_memory_integer (frame->fsr.regs[regnum], 4)); |
1029 | ||
1030 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); | |
7a292a7a | 1031 | write_register (SP_REGNUM, old_SP); |
c906108c SS |
1032 | |
1033 | flush_cached_frames (); | |
1034 | } | |
1035 | ||
1036 | static void | |
1037 | print_fpu_flags (flags) | |
1038 | int flags; | |
1039 | { | |
c5aa993b JM |
1040 | if (flags & (1 << 0)) |
1041 | fputs ("IVO ", stdout); | |
1042 | if (flags & (1 << 1)) | |
1043 | fputs ("DVZ ", stdout); | |
1044 | if (flags & (1 << 2)) | |
1045 | fputs ("OFL ", stdout); | |
1046 | if (flags & (1 << 3)) | |
1047 | fputs ("UFL ", stdout); | |
1048 | if (flags & (1 << 4)) | |
1049 | fputs ("INX ", stdout); | |
1050 | putchar ('\n'); | |
c906108c SS |
1051 | } |
1052 | ||
1053 | void | |
1054 | arm_float_info () | |
1055 | { | |
c5aa993b JM |
1056 | register unsigned long status = read_register (FPS_REGNUM); |
1057 | int type; | |
1058 | ||
1059 | type = (status >> 24) & 127; | |
1060 | printf ("%s FPU type %d\n", | |
1061 | (status & (1 << 31)) ? "Hardware" : "Software", | |
1062 | type); | |
1063 | fputs ("mask: ", stdout); | |
1064 | print_fpu_flags (status >> 16); | |
1065 | fputs ("flags: ", stdout); | |
1066 | print_fpu_flags (status); | |
c906108c SS |
1067 | } |
1068 | ||
c906108c SS |
1069 | static void |
1070 | arm_othernames () | |
1071 | { | |
085dd6e6 | 1072 | |
c5aa993b JM |
1073 | if (arm_register_names == APCS_register_names) |
1074 | { | |
1075 | arm_register_names = additional_register_names; | |
1076 | arm_toggle_regnames (); | |
1077 | } | |
1078 | else | |
1079 | { | |
1080 | arm_register_names = APCS_register_names; | |
1081 | arm_toggle_regnames (); | |
1082 | } | |
1083 | ||
c906108c SS |
1084 | } |
1085 | ||
1086 | /* FIXME: Fill in with the 'right thing', see asm | |
1087 | template in arm-convert.s */ | |
1088 | ||
c5aa993b | 1089 | void |
c906108c | 1090 | convert_from_extended (ptr, dbl) |
c5aa993b JM |
1091 | void *ptr; |
1092 | double *dbl; | |
c906108c | 1093 | { |
c5aa993b | 1094 | *dbl = *(double *) ptr; |
c906108c SS |
1095 | } |
1096 | ||
c5aa993b | 1097 | void |
c906108c | 1098 | convert_to_extended (dbl, ptr) |
c5aa993b JM |
1099 | void *ptr; |
1100 | double *dbl; | |
c906108c | 1101 | { |
c5aa993b | 1102 | *(double *) ptr = *dbl; |
c906108c SS |
1103 | } |
1104 | ||
1105 | static int | |
1106 | condition_true (cond, status_reg) | |
1107 | unsigned long cond; | |
1108 | unsigned long status_reg; | |
1109 | { | |
1110 | if (cond == INST_AL || cond == INST_NV) | |
1111 | return 1; | |
1112 | ||
1113 | switch (cond) | |
1114 | { | |
1115 | case INST_EQ: | |
1116 | return ((status_reg & FLAG_Z) != 0); | |
1117 | case INST_NE: | |
1118 | return ((status_reg & FLAG_Z) == 0); | |
1119 | case INST_CS: | |
1120 | return ((status_reg & FLAG_C) != 0); | |
1121 | case INST_CC: | |
1122 | return ((status_reg & FLAG_C) == 0); | |
1123 | case INST_MI: | |
1124 | return ((status_reg & FLAG_N) != 0); | |
1125 | case INST_PL: | |
1126 | return ((status_reg & FLAG_N) == 0); | |
1127 | case INST_VS: | |
1128 | return ((status_reg & FLAG_V) != 0); | |
1129 | case INST_VC: | |
1130 | return ((status_reg & FLAG_V) == 0); | |
1131 | case INST_HI: | |
1132 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1133 | case INST_LS: | |
1134 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1135 | case INST_GE: | |
1136 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1137 | case INST_LT: | |
1138 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1139 | case INST_GT: | |
1140 | return (((status_reg & FLAG_Z) == 0) && | |
c5aa993b | 1141 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1142 | case INST_LE: |
1143 | return (((status_reg & FLAG_Z) != 0) || | |
c5aa993b | 1144 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1145 | } |
1146 | return 1; | |
1147 | } | |
1148 | ||
1149 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
1150 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1151 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1152 | #define sbits(obj,st,fn) \ | |
1153 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1154 | #define BranchDest(addr,instr) \ | |
1155 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1156 | #define ARM_PC_32 1 | |
1157 | ||
1158 | static unsigned long | |
1159 | shifted_reg_val (inst, carry, pc_val, status_reg) | |
1160 | unsigned long inst; | |
1161 | int carry; | |
1162 | unsigned long pc_val; | |
1163 | unsigned long status_reg; | |
1164 | { | |
1165 | unsigned long res, shift; | |
1166 | int rm = bits (inst, 0, 3); | |
1167 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1168 | |
1169 | if (bit (inst, 4)) | |
c906108c SS |
1170 | { |
1171 | int rs = bits (inst, 8, 11); | |
1172 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1173 | } | |
1174 | else | |
1175 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1176 | |
1177 | res = (rm == 15 | |
c906108c | 1178 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1179 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1180 | : read_register (rm)); |
1181 | ||
1182 | switch (shifttype) | |
1183 | { | |
c5aa993b | 1184 | case 0: /* LSL */ |
c906108c SS |
1185 | res = shift >= 32 ? 0 : res << shift; |
1186 | break; | |
c5aa993b JM |
1187 | |
1188 | case 1: /* LSR */ | |
c906108c SS |
1189 | res = shift >= 32 ? 0 : res >> shift; |
1190 | break; | |
1191 | ||
c5aa993b JM |
1192 | case 2: /* ASR */ |
1193 | if (shift >= 32) | |
1194 | shift = 31; | |
c906108c SS |
1195 | res = ((res & 0x80000000L) |
1196 | ? ~((~res) >> shift) : res >> shift); | |
1197 | break; | |
1198 | ||
c5aa993b | 1199 | case 3: /* ROR/RRX */ |
c906108c SS |
1200 | shift &= 31; |
1201 | if (shift == 0) | |
1202 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1203 | else | |
c5aa993b | 1204 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1205 | break; |
1206 | } | |
1207 | ||
1208 | return res & 0xffffffff; | |
1209 | } | |
1210 | ||
1211 | ||
1212 | /* Return number of 1-bits in VAL. */ | |
1213 | ||
1214 | static int | |
1215 | bitcount (val) | |
1216 | unsigned long val; | |
1217 | { | |
1218 | int nbits; | |
1219 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1220 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1221 | return nbits; |
1222 | } | |
1223 | ||
1224 | ||
1225 | static CORE_ADDR | |
1226 | thumb_get_next_pc (pc) | |
1227 | CORE_ADDR pc; | |
1228 | { | |
c5aa993b | 1229 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1230 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1231 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1232 | unsigned long offset; |
1233 | ||
1234 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1235 | { | |
1236 | CORE_ADDR sp; | |
1237 | ||
1238 | /* Fetch the saved PC from the stack. It's stored above | |
1239 | all of the other registers. */ | |
1240 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1241 | sp = read_register (SP_REGNUM); | |
1242 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1243 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1244 | if (nextpc == pc) | |
1245 | error ("Infinite loop detected"); | |
1246 | } | |
1247 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1248 | { | |
1249 | unsigned long status = read_register (PS_REGNUM); | |
c5aa993b | 1250 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1251 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1252 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1253 | } | |
1254 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1255 | { | |
1256 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1257 | } | |
1258 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1259 | { | |
1260 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1261 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1262 | nextpc = pc_val + offset; |
1263 | } | |
1264 | ||
1265 | return nextpc; | |
1266 | } | |
1267 | ||
1268 | ||
1269 | CORE_ADDR | |
1270 | arm_get_next_pc (pc) | |
1271 | CORE_ADDR pc; | |
1272 | { | |
1273 | unsigned long pc_val; | |
1274 | unsigned long this_instr; | |
1275 | unsigned long status; | |
1276 | CORE_ADDR nextpc; | |
1277 | ||
1278 | if (arm_pc_is_thumb (pc)) | |
1279 | return thumb_get_next_pc (pc); | |
1280 | ||
1281 | pc_val = (unsigned long) pc; | |
1282 | this_instr = read_memory_integer (pc, 4); | |
1283 | status = read_register (PS_REGNUM); | |
c5aa993b | 1284 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1285 | |
1286 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1287 | { | |
1288 | switch (bits (this_instr, 24, 27)) | |
1289 | { | |
c5aa993b JM |
1290 | case 0x0: |
1291 | case 0x1: /* data processing */ | |
1292 | case 0x2: | |
1293 | case 0x3: | |
c906108c SS |
1294 | { |
1295 | unsigned long operand1, operand2, result = 0; | |
1296 | unsigned long rn; | |
1297 | int c; | |
c5aa993b | 1298 | |
c906108c SS |
1299 | if (bits (this_instr, 12, 15) != 15) |
1300 | break; | |
1301 | ||
1302 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1303 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1304 | error ("Illegal update to pc in instruction"); |
1305 | ||
1306 | /* Multiply into PC */ | |
1307 | c = (status & FLAG_C) ? 1 : 0; | |
1308 | rn = bits (this_instr, 16, 19); | |
1309 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1310 | |
c906108c SS |
1311 | if (bit (this_instr, 25)) |
1312 | { | |
1313 | unsigned long immval = bits (this_instr, 0, 7); | |
1314 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1315 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1316 | & 0xffffffff; | |
c906108c | 1317 | } |
c5aa993b | 1318 | else /* operand 2 is a shifted register */ |
c906108c | 1319 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1320 | |
c906108c SS |
1321 | switch (bits (this_instr, 21, 24)) |
1322 | { | |
c5aa993b | 1323 | case 0x0: /*and */ |
c906108c SS |
1324 | result = operand1 & operand2; |
1325 | break; | |
1326 | ||
c5aa993b | 1327 | case 0x1: /*eor */ |
c906108c SS |
1328 | result = operand1 ^ operand2; |
1329 | break; | |
1330 | ||
c5aa993b | 1331 | case 0x2: /*sub */ |
c906108c SS |
1332 | result = operand1 - operand2; |
1333 | break; | |
1334 | ||
c5aa993b | 1335 | case 0x3: /*rsb */ |
c906108c SS |
1336 | result = operand2 - operand1; |
1337 | break; | |
1338 | ||
c5aa993b | 1339 | case 0x4: /*add */ |
c906108c SS |
1340 | result = operand1 + operand2; |
1341 | break; | |
1342 | ||
c5aa993b | 1343 | case 0x5: /*adc */ |
c906108c SS |
1344 | result = operand1 + operand2 + c; |
1345 | break; | |
1346 | ||
c5aa993b | 1347 | case 0x6: /*sbc */ |
c906108c SS |
1348 | result = operand1 - operand2 + c; |
1349 | break; | |
1350 | ||
c5aa993b | 1351 | case 0x7: /*rsc */ |
c906108c SS |
1352 | result = operand2 - operand1 + c; |
1353 | break; | |
1354 | ||
c5aa993b JM |
1355 | case 0x8: |
1356 | case 0x9: | |
1357 | case 0xa: | |
1358 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1359 | result = (unsigned long) nextpc; |
1360 | break; | |
1361 | ||
c5aa993b | 1362 | case 0xc: /*orr */ |
c906108c SS |
1363 | result = operand1 | operand2; |
1364 | break; | |
1365 | ||
c5aa993b | 1366 | case 0xd: /*mov */ |
c906108c SS |
1367 | /* Always step into a function. */ |
1368 | result = operand2; | |
c5aa993b | 1369 | break; |
c906108c | 1370 | |
c5aa993b | 1371 | case 0xe: /*bic */ |
c906108c SS |
1372 | result = operand1 & ~operand2; |
1373 | break; | |
1374 | ||
c5aa993b | 1375 | case 0xf: /*mvn */ |
c906108c SS |
1376 | result = ~operand2; |
1377 | break; | |
1378 | } | |
1379 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1380 | ||
1381 | if (nextpc == pc) | |
1382 | error ("Infinite loop detected"); | |
1383 | break; | |
1384 | } | |
c5aa993b JM |
1385 | |
1386 | case 0x4: | |
1387 | case 0x5: /* data transfer */ | |
1388 | case 0x6: | |
1389 | case 0x7: | |
c906108c SS |
1390 | if (bit (this_instr, 20)) |
1391 | { | |
1392 | /* load */ | |
1393 | if (bits (this_instr, 12, 15) == 15) | |
1394 | { | |
1395 | /* rd == pc */ | |
c5aa993b | 1396 | unsigned long rn; |
c906108c | 1397 | unsigned long base; |
c5aa993b | 1398 | |
c906108c SS |
1399 | if (bit (this_instr, 22)) |
1400 | error ("Illegal update to pc in instruction"); | |
1401 | ||
1402 | /* byte write to PC */ | |
1403 | rn = bits (this_instr, 16, 19); | |
1404 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1405 | if (bit (this_instr, 24)) | |
1406 | { | |
1407 | /* pre-indexed */ | |
1408 | int c = (status & FLAG_C) ? 1 : 0; | |
1409 | unsigned long offset = | |
c5aa993b JM |
1410 | (bit (this_instr, 25) |
1411 | ? shifted_reg_val (this_instr, c, pc_val) | |
1412 | : bits (this_instr, 0, 11)); | |
c906108c SS |
1413 | |
1414 | if (bit (this_instr, 23)) | |
1415 | base += offset; | |
1416 | else | |
1417 | base -= offset; | |
1418 | } | |
c5aa993b | 1419 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1420 | 4); |
c5aa993b | 1421 | |
c906108c SS |
1422 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1423 | ||
1424 | if (nextpc == pc) | |
1425 | error ("Infinite loop detected"); | |
1426 | } | |
1427 | } | |
1428 | break; | |
c5aa993b JM |
1429 | |
1430 | case 0x8: | |
1431 | case 0x9: /* block transfer */ | |
c906108c SS |
1432 | if (bit (this_instr, 20)) |
1433 | { | |
1434 | /* LDM */ | |
1435 | if (bit (this_instr, 15)) | |
1436 | { | |
1437 | /* loading pc */ | |
1438 | int offset = 0; | |
1439 | ||
1440 | if (bit (this_instr, 23)) | |
1441 | { | |
1442 | /* up */ | |
1443 | unsigned long reglist = bits (this_instr, 0, 14); | |
1444 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1445 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1446 | offset += 4; |
1447 | } | |
1448 | else if (bit (this_instr, 24)) | |
1449 | offset = -4; | |
c5aa993b | 1450 | |
c906108c | 1451 | { |
c5aa993b JM |
1452 | unsigned long rn_val = |
1453 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1454 | nextpc = |
1455 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1456 | + offset), |
c906108c SS |
1457 | 4); |
1458 | } | |
1459 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1460 | if (nextpc == pc) | |
1461 | error ("Infinite loop detected"); | |
1462 | } | |
1463 | } | |
1464 | break; | |
c5aa993b JM |
1465 | |
1466 | case 0xb: /* branch & link */ | |
1467 | case 0xa: /* branch */ | |
c906108c SS |
1468 | { |
1469 | nextpc = BranchDest (pc, this_instr); | |
1470 | ||
1471 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1472 | if (nextpc == pc) | |
1473 | error ("Infinite loop detected"); | |
1474 | break; | |
1475 | } | |
c5aa993b JM |
1476 | |
1477 | case 0xc: | |
1478 | case 0xd: | |
1479 | case 0xe: /* coproc ops */ | |
1480 | case 0xf: /* SWI */ | |
c906108c SS |
1481 | break; |
1482 | ||
1483 | default: | |
1484 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1485 | return (pc); | |
1486 | } | |
1487 | } | |
1488 | ||
1489 | return nextpc; | |
1490 | } | |
1491 | ||
1492 | #include "bfd-in2.h" | |
1493 | #include "libcoff.h" | |
1494 | ||
1495 | static int | |
1496 | gdb_print_insn_arm (memaddr, info) | |
1497 | bfd_vma memaddr; | |
c5aa993b | 1498 | disassemble_info *info; |
c906108c SS |
1499 | { |
1500 | if (arm_pc_is_thumb (memaddr)) | |
1501 | { | |
c5aa993b JM |
1502 | static asymbol *asym; |
1503 | static combined_entry_type ce; | |
1504 | static struct coff_symbol_struct csym; | |
1505 | static struct _bfd fake_bfd; | |
1506 | static bfd_target fake_target; | |
c906108c SS |
1507 | |
1508 | if (csym.native == NULL) | |
1509 | { | |
1510 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1511 | solely so that the code in print_insn_little_arm() and | |
1512 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1513 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
c5aa993b JM |
1514 | |
1515 | fake_target.flavour = bfd_target_coff_flavour; | |
1516 | fake_bfd.xvec = &fake_target; | |
c906108c | 1517 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1518 | csym.native = &ce; |
1519 | csym.symbol.the_bfd = &fake_bfd; | |
1520 | csym.symbol.name = "fake"; | |
1521 | asym = (asymbol *) & csym; | |
c906108c | 1522 | } |
c5aa993b | 1523 | |
c906108c | 1524 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1525 | info->symbols = &asym; |
c906108c SS |
1526 | } |
1527 | else | |
1528 | info->symbols = NULL; | |
c5aa993b | 1529 | |
c906108c SS |
1530 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1531 | return print_insn_big_arm (memaddr, info); | |
1532 | else | |
1533 | return print_insn_little_arm (memaddr, info); | |
1534 | } | |
1535 | ||
1536 | /* Sequence of bytes for breakpoint instruction. */ | |
c5aa993b JM |
1537 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} /* Recognized illegal opcodes */ |
1538 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1539 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1540 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
c906108c SS |
1541 | |
1542 | /* The following has been superseded by BREAKPOINT_FOR_PC, but | |
1543 | is defined merely to keep mem-break.c happy. */ | |
1544 | #define LITTLE_BREAKPOINT ARM_LE_BREAKPOINT | |
1545 | #define BIG_BREAKPOINT ARM_BE_BREAKPOINT | |
1546 | ||
1547 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
1548 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
1549 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
1550 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
1551 | (if necessary) to point to the actual memory location where the | |
1552 | breakpoint should be inserted. */ | |
1553 | ||
1554 | unsigned char * | |
1555 | arm_breakpoint_from_pc (pcptr, lenptr) | |
c5aa993b JM |
1556 | CORE_ADDR *pcptr; |
1557 | int *lenptr; | |
c906108c SS |
1558 | { |
1559 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
1560 | { | |
1561 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1562 | { |
1563 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1564 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1565 | *lenptr = sizeof (thumb_breakpoint); | |
1566 | return thumb_breakpoint; | |
1567 | } | |
c906108c | 1568 | else |
c5aa993b JM |
1569 | { |
1570 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1571 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1572 | *lenptr = sizeof (thumb_breakpoint); | |
1573 | return thumb_breakpoint; | |
1574 | } | |
c906108c SS |
1575 | } |
1576 | else | |
1577 | { | |
1578 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1579 | { |
1580 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
1581 | *lenptr = sizeof (arm_breakpoint); | |
1582 | return arm_breakpoint; | |
1583 | } | |
c906108c | 1584 | else |
c5aa993b JM |
1585 | { |
1586 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
1587 | *lenptr = sizeof (arm_breakpoint); | |
1588 | return arm_breakpoint; | |
1589 | } | |
c906108c SS |
1590 | } |
1591 | } | |
1592 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
1593 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
1594 | ||
1595 | int | |
1596 | arm_in_call_stub (pc, name) | |
1597 | CORE_ADDR pc; | |
c5aa993b | 1598 | char *name; |
c906108c SS |
1599 | { |
1600 | CORE_ADDR start_addr; | |
1601 | ||
1602 | /* Find the starting address of the function containing the PC. If the | |
1603 | caller didn't give us a name, look it up at the same time. */ | |
1604 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
1605 | return 0; | |
1606 | ||
1607 | return strncmp (name, "_call_via_r", 11) == 0; | |
1608 | } | |
1609 | ||
1610 | ||
1611 | /* If PC is in a Thumb call or return stub, return the address of the target | |
1612 | PC, which is in a register. The thunk functions are called _called_via_xx, | |
1613 | where x is the register name. The possible names are r0-r9, sl, fp, ip, | |
1614 | sp, and lr. */ | |
1615 | ||
1616 | CORE_ADDR | |
1617 | arm_skip_stub (pc) | |
1618 | CORE_ADDR pc; | |
1619 | { | |
c5aa993b | 1620 | char *name; |
c906108c SS |
1621 | CORE_ADDR start_addr; |
1622 | ||
1623 | /* Find the starting address and name of the function containing the PC. */ | |
1624 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1625 | return 0; | |
1626 | ||
1627 | /* Call thunks always start with "_call_via_". */ | |
1628 | if (strncmp (name, "_call_via_", 10) == 0) | |
1629 | { | |
1630 | /* Use the name suffix to determine which register contains | |
1631 | the target PC. */ | |
c5aa993b JM |
1632 | static char *table[15] = |
1633 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1634 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
1635 | }; | |
c906108c SS |
1636 | int regno; |
1637 | ||
1638 | for (regno = 0; regno <= 14; regno++) | |
1639 | if (strcmp (&name[10], table[regno]) == 0) | |
1640 | return read_register (regno); | |
1641 | } | |
c5aa993b | 1642 | return 0; /* not a stub */ |
c906108c SS |
1643 | } |
1644 | ||
1645 | ||
1646 | void | |
1647 | _initialize_arm_tdep () | |
1648 | { | |
c5aa993b | 1649 | int regname_is_APCS = (arm_register_names == APCS_register_names); |
085dd6e6 | 1650 | |
c906108c | 1651 | tm_print_insn = gdb_print_insn_arm; |
c5aa993b | 1652 | |
085dd6e6 | 1653 | /* Sync the opcode insn printer with our register viewer: */ |
c906108c | 1654 | |
085dd6e6 JM |
1655 | if (arm_toggle_regnames () != regname_is_APCS) |
1656 | arm_toggle_regnames (); | |
c5aa993b | 1657 | |
c906108c SS |
1658 | add_com ("othernames", class_obscure, arm_othernames, |
1659 | "Switch to the other set of register names."); | |
1660 | ||
1661 | /* ??? Maybe this should be a boolean. */ | |
1662 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
c5aa993b JM |
1663 | var_zinteger, (char *) &arm_apcs_32, |
1664 | "Set usage of ARM 32-bit mode.\n", &setlist), | |
1665 | &showlist); | |
c906108c SS |
1666 | |
1667 | } | |
1668 | ||
1669 | /* Test whether the coff symbol specific value corresponds to a Thumb function */ | |
1670 | int | |
c5aa993b | 1671 | coff_sym_is_thumb (int val) |
c906108c | 1672 | { |
c5aa993b JM |
1673 | return (val == C_THUMBEXT || |
1674 | val == C_THUMBSTAT || | |
1675 | val == C_THUMBEXTFUNC || | |
1676 | val == C_THUMBSTATFUNC || | |
1677 | val == C_THUMBLABEL); | |
c906108c | 1678 | } |