Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
197e01b6 | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, |
0fd88904 | 4 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
c906108c | 22 | |
34e8f22d RE |
23 | #include <ctype.h> /* XXX for isupper () */ |
24 | ||
c906108c SS |
25 | #include "defs.h" |
26 | #include "frame.h" | |
27 | #include "inferior.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
c906108c | 30 | #include "gdb_string.h" |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
4be87837 | 36 | #include "osabi.h" |
eb5492fa DJ |
37 | #include "frame-unwind.h" |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
842e1f1e DJ |
40 | #include "objfiles.h" |
41 | #include "dwarf2-frame.h" | |
34e8f22d RE |
42 | |
43 | #include "arm-tdep.h" | |
26216b98 | 44 | #include "gdb/sim-arm.h" |
34e8f22d | 45 | |
082fc60d RE |
46 | #include "elf-bfd.h" |
47 | #include "coff/internal.h" | |
97e03143 | 48 | #include "elf/arm.h" |
c906108c | 49 | |
26216b98 AC |
50 | #include "gdb_assert.h" |
51 | ||
6529d2dd AC |
52 | static int arm_debug; |
53 | ||
082fc60d RE |
54 | /* Macros for setting and testing a bit in a minimal symbol that marks |
55 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 56 | is used for this purpose. |
082fc60d RE |
57 | |
58 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 59 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
60 | |
61 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
62 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
63 | | 0x80000000) | |
64 | ||
65 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
66 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
67 | ||
afd7eef0 RE |
68 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
69 | static struct cmd_list_element *setarmcmdlist = NULL; | |
70 | static struct cmd_list_element *showarmcmdlist = NULL; | |
71 | ||
fd50bc42 RE |
72 | /* The type of floating-point to use. Keep this in sync with enum |
73 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
74 | static const char *fp_model_strings[] = | |
75 | { | |
76 | "auto", | |
77 | "softfpa", | |
78 | "fpa", | |
79 | "softvfp", | |
28e97307 DJ |
80 | "vfp", |
81 | NULL | |
fd50bc42 RE |
82 | }; |
83 | ||
84 | /* A variable that can be configured by the user. */ | |
85 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
86 | static const char *current_fp_model = "auto"; | |
87 | ||
28e97307 DJ |
88 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
89 | static const char *arm_abi_strings[] = | |
90 | { | |
91 | "auto", | |
92 | "APCS", | |
93 | "AAPCS", | |
94 | NULL | |
95 | }; | |
96 | ||
97 | /* A variable that can be configured by the user. */ | |
98 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
99 | static const char *arm_abi_string = "auto"; | |
100 | ||
94c30b78 | 101 | /* Number of different reg name sets (options). */ |
afd7eef0 | 102 | static int num_disassembly_options; |
bc90b915 FN |
103 | |
104 | /* We have more registers than the disassembler as gdb can print the value | |
105 | of special registers as well. | |
106 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 107 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 108 | |
94c30b78 | 109 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 110 | static char * arm_register_name_strings[] = |
da59e081 JM |
111 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
112 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
113 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
114 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
115 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
116 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 117 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 118 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 119 | |
afd7eef0 RE |
120 | /* Valid register name styles. */ |
121 | static const char **valid_disassembly_styles; | |
ed9a39eb | 122 | |
afd7eef0 RE |
123 | /* Disassembly style to use. Default to "std" register names. */ |
124 | static const char *disassembly_style; | |
94c30b78 | 125 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 126 | static int current_option; |
96baa820 | 127 | |
ed9a39eb | 128 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
129 | style. */ |
130 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 131 | struct cmd_list_element *); |
afd7eef0 | 132 | static void set_disassembly_style (void); |
ed9a39eb | 133 | |
b508a996 RE |
134 | static void convert_from_extended (const struct floatformat *, const void *, |
135 | void *); | |
136 | static void convert_to_extended (const struct floatformat *, void *, | |
137 | const void *); | |
ed9a39eb | 138 | |
9b8d791a | 139 | struct arm_prologue_cache |
c3b4394c | 140 | { |
eb5492fa DJ |
141 | /* The stack pointer at the time this frame was created; i.e. the |
142 | caller's stack pointer when this function was called. It is used | |
143 | to identify this frame. */ | |
144 | CORE_ADDR prev_sp; | |
145 | ||
146 | /* The frame base for this frame is just prev_sp + frame offset - | |
147 | frame size. FRAMESIZE is the size of this stack frame, and | |
148 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
149 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
150 | ||
c3b4394c RE |
151 | int framesize; |
152 | int frameoffset; | |
eb5492fa DJ |
153 | |
154 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 155 | int framereg; |
eb5492fa DJ |
156 | |
157 | /* Saved register offsets. */ | |
158 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 159 | }; |
ed9a39eb | 160 | |
bc90b915 FN |
161 | /* Addresses for calling Thumb functions have the bit 0 set. |
162 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
163 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
164 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
165 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
166 | ||
94c30b78 | 167 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
168 | |
169 | int arm_apcs_32 = 1; | |
170 | ||
ed9a39eb JM |
171 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
172 | function. */ | |
c906108c | 173 | |
34e8f22d | 174 | int |
2a451106 | 175 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 176 | { |
c5aa993b | 177 | struct minimal_symbol *sym; |
c906108c | 178 | |
ed9a39eb | 179 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
180 | if (IS_THUMB_ADDR (memaddr)) |
181 | return 1; | |
182 | ||
ed9a39eb | 183 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
184 | sym = lookup_minimal_symbol_by_pc (memaddr); |
185 | if (sym) | |
186 | { | |
c5aa993b | 187 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
188 | } |
189 | else | |
ed9a39eb JM |
190 | { |
191 | return 0; | |
192 | } | |
c906108c SS |
193 | } |
194 | ||
181c1381 | 195 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 196 | static CORE_ADDR |
ed9a39eb | 197 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 198 | { |
a3a2ee65 JT |
199 | if (arm_apcs_32) |
200 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 201 | else |
a3a2ee65 | 202 | return (val & 0x03fffffc); |
c906108c SS |
203 | } |
204 | ||
181c1381 RE |
205 | /* When reading symbols, we need to zap the low bit of the address, |
206 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 207 | static CORE_ADDR |
181c1381 RE |
208 | arm_smash_text_address (CORE_ADDR val) |
209 | { | |
210 | return val & ~1; | |
211 | } | |
212 | ||
34e8f22d RE |
213 | /* Immediately after a function call, return the saved pc. Can't |
214 | always go through the frames for this because on some machines the | |
215 | new frame is not set up until the new function executes some | |
216 | instructions. */ | |
217 | ||
218 | static CORE_ADDR | |
ed9a39eb | 219 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 220 | { |
34e8f22d | 221 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
222 | } |
223 | ||
224 | /* A typical Thumb prologue looks like this: | |
c5aa993b JM |
225 | push {r7, lr} |
226 | add sp, sp, #-28 | |
227 | add r7, sp, #12 | |
c906108c | 228 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
229 | mov r7, sp |
230 | ||
231 | or like this: | |
232 | push {r7, lr} | |
233 | mov r7, sp | |
234 | sub sp, #12 | |
235 | ||
236 | or, on tpcs, like this: | |
237 | sub sp,#16 | |
238 | push {r7, lr} | |
239 | (many instructions) | |
240 | mov r7, sp | |
241 | sub sp, #12 | |
242 | ||
243 | There is always one instruction of three classes: | |
244 | 1 - push | |
245 | 2 - setting of r7 | |
246 | 3 - adjusting of sp | |
247 | ||
248 | When we have found at least one of each class we are done with the prolog. | |
249 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 250 | */ |
c906108c SS |
251 | |
252 | static CORE_ADDR | |
c7885828 | 253 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
254 | { |
255 | CORE_ADDR current_pc; | |
da3c6d4a MS |
256 | /* findmask: |
257 | bit 0 - push { rlist } | |
258 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
259 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
260 | */ | |
261 | int findmask = 0; | |
262 | ||
94c30b78 MS |
263 | for (current_pc = pc; |
264 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 265 | current_pc += 2) |
c906108c SS |
266 | { |
267 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
268 | ||
94c30b78 | 269 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 270 | { |
94c30b78 | 271 | findmask |= 1; /* push found */ |
da59e081 | 272 | } |
da3c6d4a MS |
273 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
274 | sub sp, #simm */ | |
da59e081 | 275 | { |
94c30b78 | 276 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
277 | continue; |
278 | else | |
94c30b78 | 279 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
280 | } |
281 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
282 | { | |
94c30b78 | 283 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
284 | } |
285 | else if (insn == 0x466f) /* mov r7, sp */ | |
286 | { | |
94c30b78 | 287 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 288 | } |
3d74b771 FF |
289 | else if (findmask == (4+2+1)) |
290 | { | |
da3c6d4a MS |
291 | /* We have found one of each type of prologue instruction */ |
292 | break; | |
3d74b771 | 293 | } |
da59e081 | 294 | else |
94c30b78 | 295 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 296 | instruction from outside the prolog scheduled here for |
94c30b78 | 297 | optimization. */ |
da3c6d4a | 298 | continue; |
c906108c SS |
299 | } |
300 | ||
301 | return current_pc; | |
302 | } | |
303 | ||
da3c6d4a MS |
304 | /* Advance the PC across any function entry prologue instructions to |
305 | reach some "real" code. | |
34e8f22d RE |
306 | |
307 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 308 | prologue: |
c906108c | 309 | |
c5aa993b JM |
310 | mov ip, sp |
311 | [stmfd sp!, {a1,a2,a3,a4}] | |
312 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
313 | [stfe f7, [sp, #-12]!] |
314 | [stfe f6, [sp, #-12]!] | |
315 | [stfe f5, [sp, #-12]!] | |
316 | [stfe f4, [sp, #-12]!] | |
317 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 318 | |
34e8f22d | 319 | static CORE_ADDR |
ed9a39eb | 320 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
321 | { |
322 | unsigned long inst; | |
323 | CORE_ADDR skip_pc; | |
b8d5e71d | 324 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 325 | char *func_name; |
c906108c SS |
326 | struct symtab_and_line sal; |
327 | ||
848cfffb | 328 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 329 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
330 | return pc; |
331 | ||
96baa820 | 332 | /* See what the symbol table says. */ |
ed9a39eb | 333 | |
50f6fb4b | 334 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 335 | { |
50f6fb4b CV |
336 | struct symbol *sym; |
337 | ||
338 | /* Found a function. */ | |
176620f1 | 339 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
340 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
341 | { | |
94c30b78 | 342 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
343 | sal = find_pc_line (func_addr, 0); |
344 | if ((sal.line != 0) && (sal.end < func_end)) | |
345 | return sal.end; | |
346 | } | |
c906108c SS |
347 | } |
348 | ||
349 | /* Check if this is Thumb code. */ | |
350 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 351 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
352 | |
353 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 354 | by disassembling the instructions. */ |
c906108c | 355 | |
b8d5e71d MS |
356 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
357 | if (func_end == 0 || func_end > pc + 64) | |
358 | func_end = pc + 64; | |
c906108c | 359 | |
b8d5e71d | 360 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 361 | { |
f43845b3 | 362 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 363 | |
b8d5e71d MS |
364 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
365 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
366 | continue; | |
c906108c | 367 | |
28cd8767 JG |
368 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
369 | continue; | |
370 | ||
371 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
372 | continue; | |
373 | ||
b8d5e71d MS |
374 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
375 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
376 | continue; | |
c906108c | 377 | |
b8d5e71d MS |
378 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
379 | continue; | |
c906108c | 380 | |
b8d5e71d MS |
381 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
382 | continue; | |
11d3b27d | 383 | |
b8d5e71d MS |
384 | /* Any insns after this point may float into the code, if it makes |
385 | for better instruction scheduling, so we skip them only if we | |
386 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 387 | |
b8d5e71d MS |
388 | /* We may have either one sfmfd instruction here, or several stfe |
389 | insns, depending on the version of floating point code we | |
390 | support. */ | |
391 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
392 | continue; | |
393 | ||
394 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
395 | continue; | |
396 | ||
397 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
398 | continue; | |
399 | ||
400 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
401 | continue; | |
402 | ||
403 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
404 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
405 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
406 | continue; | |
407 | ||
408 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
409 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
410 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
411 | continue; | |
412 | ||
413 | /* Un-recognized instruction; stop scanning. */ | |
414 | break; | |
f43845b3 | 415 | } |
c906108c | 416 | |
b8d5e71d | 417 | return skip_pc; /* End of prologue */ |
c906108c | 418 | } |
94c30b78 | 419 | |
c5aa993b | 420 | /* *INDENT-OFF* */ |
c906108c SS |
421 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
422 | This function decodes a Thumb function prologue to determine: | |
423 | 1) the size of the stack frame | |
424 | 2) which registers are saved on it | |
425 | 3) the offsets of saved regs | |
426 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 427 | |
da59e081 JM |
428 | A typical Thumb function prologue would create this stack frame |
429 | (offsets relative to FP) | |
c906108c SS |
430 | old SP -> 24 stack parameters |
431 | 20 LR | |
432 | 16 R7 | |
433 | R7 -> 0 local variables (16 bytes) | |
434 | SP -> -12 additional stack space (12 bytes) | |
435 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
436 | 12 bytes. The frame register is R7. |
437 | ||
da3c6d4a MS |
438 | The comments for thumb_skip_prolog() describe the algorithm we use |
439 | to detect the end of the prolog. */ | |
c5aa993b JM |
440 | /* *INDENT-ON* */ |
441 | ||
c906108c | 442 | static void |
eb5492fa | 443 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
444 | { |
445 | CORE_ADDR prologue_start; | |
446 | CORE_ADDR prologue_end; | |
447 | CORE_ADDR current_pc; | |
94c30b78 | 448 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
449 | int saved_reg[16]; |
450 | /* findmask: | |
451 | bit 0 - push { rlist } | |
452 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
453 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
454 | */ | |
455 | int findmask = 0; | |
c5aa993b | 456 | int i; |
c906108c | 457 | |
eb5492fa | 458 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
459 | { |
460 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
461 | ||
94c30b78 | 462 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 463 | prologue_end = prev_pc; |
c906108c | 464 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 465 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
466 | } |
467 | else | |
da3c6d4a MS |
468 | /* We're in the boondocks: allow for |
469 | 16 pushes, an add, and "mv fp,sp". */ | |
470 | prologue_end = prologue_start + 40; | |
c906108c | 471 | |
eb5492fa | 472 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
473 | |
474 | /* Initialize the saved register map. When register H is copied to | |
475 | register L, we will put H in saved_reg[L]. */ | |
476 | for (i = 0; i < 16; i++) | |
477 | saved_reg[i] = i; | |
478 | ||
479 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
480 | frame pointer, adjust the stack pointer, and save registers. |
481 | Do this until all basic prolog instructions are found. */ | |
c906108c | 482 | |
9b8d791a | 483 | cache->framesize = 0; |
da59e081 JM |
484 | for (current_pc = prologue_start; |
485 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
486 | current_pc += 2) | |
c906108c SS |
487 | { |
488 | unsigned short insn; | |
489 | int regno; | |
490 | int offset; | |
491 | ||
492 | insn = read_memory_unsigned_integer (current_pc, 2); | |
493 | ||
c5aa993b | 494 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 495 | { |
da59e081 | 496 | int mask; |
94c30b78 | 497 | findmask |= 1; /* push found */ |
c906108c SS |
498 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
499 | whether to save LR (R14). */ | |
da59e081 | 500 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 501 | |
b8d5e71d | 502 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 503 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 504 | if (mask & (1 << regno)) |
c5aa993b | 505 | { |
9b8d791a | 506 | cache->framesize += 4; |
eb5492fa | 507 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
508 | /* Reset saved register map. */ |
509 | saved_reg[regno] = regno; | |
c906108c SS |
510 | } |
511 | } | |
da3c6d4a MS |
512 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
513 | sub sp, #simm */ | |
c906108c | 514 | { |
b8d5e71d | 515 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
516 | continue; |
517 | else | |
94c30b78 | 518 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 519 | |
94c30b78 MS |
520 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
521 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 522 | { |
9b8d791a | 523 | cache->frameoffset += offset; |
da59e081 JM |
524 | offset = -offset; |
525 | } | |
9b8d791a | 526 | cache->framesize -= offset; |
c906108c SS |
527 | } |
528 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
529 | { | |
94c30b78 | 530 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 531 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 532 | /* get scaled offset */ |
9b8d791a | 533 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 534 | } |
da59e081 | 535 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 536 | { |
94c30b78 | 537 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
538 | cache->framereg = THUMB_FP_REGNUM; |
539 | cache->frameoffset = 0; | |
34e8f22d | 540 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
541 | } |
542 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
543 | { | |
da3c6d4a | 544 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 545 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 546 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
547 | } |
548 | else | |
da3c6d4a MS |
549 | /* Something in the prolog that we don't care about or some |
550 | instruction from outside the prolog scheduled here for | |
551 | optimization. */ | |
552 | continue; | |
c906108c SS |
553 | } |
554 | } | |
555 | ||
ed9a39eb | 556 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
557 | 1) the size of the stack frame |
558 | 2) which registers are saved on it | |
559 | 3) the offsets of saved regs | |
560 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
561 | This information is stored in the "extra" fields of the frame_info. |
562 | ||
96baa820 JM |
563 | There are two basic forms for the ARM prologue. The fixed argument |
564 | function call will look like: | |
ed9a39eb JM |
565 | |
566 | mov ip, sp | |
567 | stmfd sp!, {fp, ip, lr, pc} | |
568 | sub fp, ip, #4 | |
569 | [sub sp, sp, #4] | |
96baa820 | 570 | |
c906108c | 571 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
572 | IP -> 4 (caller's stack) |
573 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
574 | -4 LR (return address in caller) | |
575 | -8 IP (copy of caller's SP) | |
576 | -12 FP (caller's FP) | |
577 | SP -> -28 Local variables | |
578 | ||
c906108c | 579 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
580 | 28 bytes. The stmfd call can also save any of the vN registers it |
581 | plans to use, which increases the frame size accordingly. | |
582 | ||
583 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
584 | because the ARM Store instructions always store PC + 8 when you read | |
585 | the PC register. | |
ed9a39eb | 586 | |
96baa820 JM |
587 | A variable argument function call will look like: |
588 | ||
ed9a39eb JM |
589 | mov ip, sp |
590 | stmfd sp!, {a1, a2, a3, a4} | |
591 | stmfd sp!, {fp, ip, lr, pc} | |
592 | sub fp, ip, #20 | |
593 | ||
96baa820 | 594 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
595 | IP -> 20 (caller's stack) |
596 | 16 A4 | |
597 | 12 A3 | |
598 | 8 A2 | |
599 | 4 A1 | |
600 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
601 | -4 LR (return address in caller) | |
602 | -8 IP (copy of caller's SP) | |
603 | -12 FP (caller's FP) | |
604 | SP -> -28 Local variables | |
96baa820 JM |
605 | |
606 | The frame size would thus be 48 bytes, and the frame offset would be | |
607 | 28 bytes. | |
608 | ||
609 | There is another potential complication, which is that the optimizer | |
610 | will try to separate the store of fp in the "stmfd" instruction from | |
611 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
612 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
613 | ||
614 | Also, note, the original version of the ARM toolchain claimed that there | |
615 | should be an | |
616 | ||
617 | instruction at the end of the prologue. I have never seen GCC produce | |
618 | this, and the ARM docs don't mention it. We still test for it below in | |
619 | case it happens... | |
ed9a39eb JM |
620 | |
621 | */ | |
c906108c SS |
622 | |
623 | static void | |
eb5492fa | 624 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 625 | { |
28cd8767 | 626 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 627 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 628 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 629 | |
c906108c | 630 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
631 | cache->framereg = ARM_SP_REGNUM; |
632 | cache->framesize = 0; | |
633 | cache->frameoffset = 0; | |
c906108c SS |
634 | |
635 | /* Check for Thumb prologue. */ | |
eb5492fa | 636 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 637 | { |
eb5492fa | 638 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
639 | return; |
640 | } | |
641 | ||
642 | /* Find the function prologue. If we can't find the function in | |
643 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 644 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 645 | { |
2a451106 KB |
646 | /* One way to find the end of the prologue (which works well |
647 | for unoptimized code) is to do the following: | |
648 | ||
649 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
650 | ||
651 | if (sal.line == 0) | |
eb5492fa | 652 | prologue_end = prev_pc; |
2a451106 KB |
653 | else if (sal.end < prologue_end) |
654 | prologue_end = sal.end; | |
655 | ||
656 | This mechanism is very accurate so long as the optimizer | |
657 | doesn't move any instructions from the function body into the | |
658 | prologue. If this happens, sal.end will be the last | |
659 | instruction in the first hunk of prologue code just before | |
660 | the first instruction that the scheduler has moved from | |
661 | the body to the prologue. | |
662 | ||
663 | In order to make sure that we scan all of the prologue | |
664 | instructions, we use a slightly less accurate mechanism which | |
665 | may scan more than necessary. To help compensate for this | |
666 | lack of accuracy, the prologue scanning loop below contains | |
667 | several clauses which'll cause the loop to terminate early if | |
668 | an implausible prologue instruction is encountered. | |
669 | ||
670 | The expression | |
671 | ||
672 | prologue_start + 64 | |
673 | ||
674 | is a suitable endpoint since it accounts for the largest | |
675 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 676 | the scheduler. */ |
2a451106 KB |
677 | |
678 | if (prologue_end > prologue_start + 64) | |
679 | { | |
94c30b78 | 680 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 681 | } |
c906108c SS |
682 | } |
683 | else | |
684 | { | |
eb5492fa DJ |
685 | /* We have no symbol information. Our only option is to assume this |
686 | function has a standard stack frame and the normal frame register. | |
687 | Then, we can find the value of our frame pointer on entrance to | |
688 | the callee (or at the present moment if this is the innermost frame). | |
689 | The value stored there should be the address of the stmfd + 8. */ | |
690 | CORE_ADDR frame_loc; | |
691 | LONGEST return_value; | |
692 | ||
693 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
694 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
695 | return; |
696 | else | |
697 | { | |
698 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 699 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 700 | } |
c906108c SS |
701 | } |
702 | ||
eb5492fa DJ |
703 | if (prev_pc < prologue_end) |
704 | prologue_end = prev_pc; | |
705 | ||
c906108c | 706 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 707 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 708 | |
96baa820 JM |
709 | Be careful, however, and if it doesn't look like a prologue, |
710 | don't try to scan it. If, for instance, a frameless function | |
711 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 712 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
713 | and other operations that rely on a knowledge of the stack |
714 | traceback. | |
715 | ||
716 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 717 | if we don't see this as the first insn, we will stop. |
c906108c | 718 | |
f43845b3 MS |
719 | [Note: This doesn't seem to be true any longer, so it's now an |
720 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 721 | |
f43845b3 MS |
722 | [Note further: The "mov ip,sp" only seems to be missing in |
723 | frameless functions at optimization level "-O2" or above, | |
724 | in which case it is often (but not always) replaced by | |
b8d5e71d | 725 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 726 | |
28cd8767 | 727 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 728 | |
94c30b78 MS |
729 | for (current_pc = prologue_start; |
730 | current_pc < prologue_end; | |
f43845b3 | 731 | current_pc += 4) |
96baa820 | 732 | { |
d4473757 KB |
733 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
734 | ||
94c30b78 | 735 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 736 | { |
28cd8767 JG |
737 | ip_offset = 0; |
738 | continue; | |
739 | } | |
740 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
741 | { | |
742 | unsigned imm = insn & 0xff; /* immediate value */ | |
743 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
744 | imm = (imm >> rot) | (imm << (32 - rot)); | |
745 | ip_offset = imm; | |
746 | continue; | |
747 | } | |
748 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
749 | { | |
750 | unsigned imm = insn & 0xff; /* immediate value */ | |
751 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
752 | imm = (imm >> rot) | (imm << (32 - rot)); | |
753 | ip_offset = -imm; | |
f43845b3 MS |
754 | continue; |
755 | } | |
94c30b78 | 756 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 757 | { |
e28a332c JG |
758 | sp_offset -= 4; |
759 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
760 | continue; |
761 | } | |
762 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
763 | /* stmfd sp!, {..., fp, ip, lr, pc} |
764 | or | |
765 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 766 | { |
d4473757 | 767 | int mask = insn & 0xffff; |
ed9a39eb | 768 | |
94c30b78 | 769 | /* Calculate offsets of saved registers. */ |
34e8f22d | 770 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
771 | if (mask & (1 << regno)) |
772 | { | |
773 | sp_offset -= 4; | |
eb5492fa | 774 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
775 | } |
776 | } | |
b8d5e71d MS |
777 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
778 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
779 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
780 | { | |
781 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
782 | continue; | |
783 | } | |
784 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
785 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
786 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
787 | { |
788 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
789 | continue; | |
790 | } | |
d4473757 KB |
791 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
792 | { | |
94c30b78 MS |
793 | unsigned imm = insn & 0xff; /* immediate value */ |
794 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 795 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 796 | fp_offset = -imm + ip_offset; |
9b8d791a | 797 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
798 | } |
799 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
800 | { | |
94c30b78 MS |
801 | unsigned imm = insn & 0xff; /* immediate value */ |
802 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
803 | imm = (imm >> rot) | (imm << (32 - rot)); |
804 | sp_offset -= imm; | |
805 | } | |
806 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
807 | { | |
808 | sp_offset -= 12; | |
34e8f22d | 809 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 810 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
811 | } |
812 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
813 | { | |
814 | int n_saved_fp_regs; | |
815 | unsigned int fp_start_reg, fp_bound_reg; | |
816 | ||
94c30b78 | 817 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 818 | { |
d4473757 KB |
819 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
820 | n_saved_fp_regs = 3; | |
821 | else | |
822 | n_saved_fp_regs = 1; | |
96baa820 | 823 | } |
d4473757 | 824 | else |
96baa820 | 825 | { |
d4473757 KB |
826 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
827 | n_saved_fp_regs = 2; | |
828 | else | |
829 | n_saved_fp_regs = 4; | |
96baa820 | 830 | } |
d4473757 | 831 | |
34e8f22d | 832 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
833 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
834 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
835 | { |
836 | sp_offset -= 12; | |
eb5492fa | 837 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 838 | } |
c906108c | 839 | } |
d4473757 | 840 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 841 | break; /* Condition not true, exit early */ |
b8d5e71d | 842 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 843 | break; /* Don't scan past a block load */ |
d4473757 KB |
844 | else |
845 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 846 | so we just skip what we don't recognize. */ |
d4473757 | 847 | continue; |
c906108c SS |
848 | } |
849 | ||
94c30b78 MS |
850 | /* The frame size is just the negative of the offset (from the |
851 | original SP) of the last thing thing we pushed on the stack. | |
852 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
853 | cache->framesize = -sp_offset; |
854 | if (cache->framereg == ARM_FP_REGNUM) | |
855 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 856 | else |
9b8d791a | 857 | cache->frameoffset = 0; |
c906108c SS |
858 | } |
859 | ||
eb5492fa DJ |
860 | static struct arm_prologue_cache * |
861 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 862 | { |
eb5492fa DJ |
863 | int reg; |
864 | struct arm_prologue_cache *cache; | |
865 | CORE_ADDR unwound_fp; | |
c5aa993b | 866 | |
eb5492fa DJ |
867 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
868 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 869 | |
eb5492fa | 870 | arm_scan_prologue (next_frame, cache); |
848cfffb | 871 | |
eb5492fa DJ |
872 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
873 | if (unwound_fp == 0) | |
874 | return cache; | |
c906108c | 875 | |
eb5492fa | 876 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 877 | |
eb5492fa DJ |
878 | /* Calculate actual addresses of saved registers using offsets |
879 | determined by arm_scan_prologue. */ | |
880 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 881 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
882 | cache->saved_regs[reg].addr += cache->prev_sp; |
883 | ||
884 | return cache; | |
c906108c SS |
885 | } |
886 | ||
eb5492fa DJ |
887 | /* Our frame ID for a normal frame is the current function's starting PC |
888 | and the caller's SP when we were called. */ | |
c906108c | 889 | |
148754e5 | 890 | static void |
eb5492fa DJ |
891 | arm_prologue_this_id (struct frame_info *next_frame, |
892 | void **this_cache, | |
893 | struct frame_id *this_id) | |
c906108c | 894 | { |
eb5492fa DJ |
895 | struct arm_prologue_cache *cache; |
896 | struct frame_id id; | |
897 | CORE_ADDR func; | |
f079148d | 898 | |
eb5492fa DJ |
899 | if (*this_cache == NULL) |
900 | *this_cache = arm_make_prologue_cache (next_frame); | |
901 | cache = *this_cache; | |
2a451106 | 902 | |
eb5492fa | 903 | func = frame_func_unwind (next_frame); |
2a451106 | 904 | |
eb5492fa DJ |
905 | /* This is meant to halt the backtrace at "_start". Make sure we |
906 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 907 | if (func <= LOWEST_PC) |
eb5492fa | 908 | return; |
5a203e44 | 909 | |
eb5492fa DJ |
910 | /* If we've hit a wall, stop. */ |
911 | if (cache->prev_sp == 0) | |
912 | return; | |
24de872b | 913 | |
eb5492fa | 914 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 915 | *this_id = id; |
c906108c SS |
916 | } |
917 | ||
eb5492fa DJ |
918 | static void |
919 | arm_prologue_prev_register (struct frame_info *next_frame, | |
920 | void **this_cache, | |
921 | int prev_regnum, | |
922 | int *optimized, | |
923 | enum lval_type *lvalp, | |
924 | CORE_ADDR *addrp, | |
925 | int *realnump, | |
9af75ef6 | 926 | gdb_byte *valuep) |
24de872b DJ |
927 | { |
928 | struct arm_prologue_cache *cache; | |
929 | ||
eb5492fa DJ |
930 | if (*this_cache == NULL) |
931 | *this_cache = arm_make_prologue_cache (next_frame); | |
932 | cache = *this_cache; | |
24de872b | 933 | |
eb5492fa DJ |
934 | /* If we are asked to unwind the PC, then we need to return the LR |
935 | instead. The saved value of PC points into this frame's | |
936 | prologue, not the next frame's resume location. */ | |
937 | if (prev_regnum == ARM_PC_REGNUM) | |
938 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 939 | |
eb5492fa DJ |
940 | /* SP is generally not saved to the stack, but this frame is |
941 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
942 | The value was already reconstructed into PREV_SP. */ | |
943 | if (prev_regnum == ARM_SP_REGNUM) | |
944 | { | |
945 | *lvalp = not_lval; | |
946 | if (valuep) | |
947 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
948 | return; | |
949 | } | |
950 | ||
1f67027d AC |
951 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
952 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
953 | } |
954 | ||
955 | struct frame_unwind arm_prologue_unwind = { | |
956 | NORMAL_FRAME, | |
957 | arm_prologue_this_id, | |
958 | arm_prologue_prev_register | |
959 | }; | |
960 | ||
961 | static const struct frame_unwind * | |
962 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
963 | { | |
964 | return &arm_prologue_unwind; | |
24de872b DJ |
965 | } |
966 | ||
909cf6ea DJ |
967 | static struct arm_prologue_cache * |
968 | arm_make_stub_cache (struct frame_info *next_frame) | |
969 | { | |
970 | int reg; | |
971 | struct arm_prologue_cache *cache; | |
972 | CORE_ADDR unwound_fp; | |
973 | ||
974 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
975 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
976 | ||
977 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
978 | ||
979 | return cache; | |
980 | } | |
981 | ||
982 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
983 | ||
984 | static void | |
985 | arm_stub_this_id (struct frame_info *next_frame, | |
986 | void **this_cache, | |
987 | struct frame_id *this_id) | |
988 | { | |
989 | struct arm_prologue_cache *cache; | |
990 | ||
991 | if (*this_cache == NULL) | |
992 | *this_cache = arm_make_stub_cache (next_frame); | |
993 | cache = *this_cache; | |
994 | ||
995 | *this_id = frame_id_build (cache->prev_sp, | |
996 | frame_pc_unwind (next_frame)); | |
997 | } | |
998 | ||
999 | struct frame_unwind arm_stub_unwind = { | |
1000 | NORMAL_FRAME, | |
1001 | arm_stub_this_id, | |
1002 | arm_prologue_prev_register | |
1003 | }; | |
1004 | ||
1005 | static const struct frame_unwind * | |
1006 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1007 | { | |
1008 | char dummy[4]; | |
1009 | ||
1010 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
1011 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
1012 | return &arm_stub_unwind; | |
1013 | ||
1014 | return NULL; | |
1015 | } | |
1016 | ||
24de872b | 1017 | static CORE_ADDR |
eb5492fa | 1018 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1019 | { |
1020 | struct arm_prologue_cache *cache; | |
1021 | ||
eb5492fa DJ |
1022 | if (*this_cache == NULL) |
1023 | *this_cache = arm_make_prologue_cache (next_frame); | |
1024 | cache = *this_cache; | |
1025 | ||
1026 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1027 | } |
1028 | ||
eb5492fa DJ |
1029 | struct frame_base arm_normal_base = { |
1030 | &arm_prologue_unwind, | |
1031 | arm_normal_frame_base, | |
1032 | arm_normal_frame_base, | |
1033 | arm_normal_frame_base | |
1034 | }; | |
1035 | ||
eb5492fa DJ |
1036 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1037 | dummy frame. The frame ID's base needs to match the TOS value | |
1038 | saved by save_dummy_frame_tos() and returned from | |
1039 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1040 | breakpoint. */ | |
c906108c | 1041 | |
eb5492fa DJ |
1042 | static struct frame_id |
1043 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1044 | { |
eb5492fa DJ |
1045 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1046 | frame_pc_unwind (next_frame)); | |
1047 | } | |
c3b4394c | 1048 | |
eb5492fa DJ |
1049 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1050 | be used to construct the previous frame's ID, after looking up the | |
1051 | containing function). */ | |
c3b4394c | 1052 | |
eb5492fa DJ |
1053 | static CORE_ADDR |
1054 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1055 | { | |
1056 | CORE_ADDR pc; | |
1057 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1058 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1059 | } | |
1060 | ||
1061 | static CORE_ADDR | |
1062 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1063 | { | |
1064 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1065 | } |
1066 | ||
2dd604e7 RE |
1067 | /* When arguments must be pushed onto the stack, they go on in reverse |
1068 | order. The code below implements a FILO (stack) to do this. */ | |
1069 | ||
1070 | struct stack_item | |
1071 | { | |
1072 | int len; | |
1073 | struct stack_item *prev; | |
1074 | void *data; | |
1075 | }; | |
1076 | ||
1077 | static struct stack_item * | |
1078 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1079 | { | |
1080 | struct stack_item *si; | |
1081 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1082 | si->data = xmalloc (len); |
2dd604e7 RE |
1083 | si->len = len; |
1084 | si->prev = prev; | |
1085 | memcpy (si->data, contents, len); | |
1086 | return si; | |
1087 | } | |
1088 | ||
1089 | static struct stack_item * | |
1090 | pop_stack_item (struct stack_item *si) | |
1091 | { | |
1092 | struct stack_item *dead = si; | |
1093 | si = si->prev; | |
1094 | xfree (dead->data); | |
1095 | xfree (dead); | |
1096 | return si; | |
1097 | } | |
1098 | ||
2af48f68 PB |
1099 | |
1100 | /* Return the alignment (in bytes) of the given type. */ | |
1101 | ||
1102 | static int | |
1103 | arm_type_align (struct type *t) | |
1104 | { | |
1105 | int n; | |
1106 | int align; | |
1107 | int falign; | |
1108 | ||
1109 | t = check_typedef (t); | |
1110 | switch (TYPE_CODE (t)) | |
1111 | { | |
1112 | default: | |
1113 | /* Should never happen. */ | |
1114 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1115 | return 4; | |
1116 | ||
1117 | case TYPE_CODE_PTR: | |
1118 | case TYPE_CODE_ENUM: | |
1119 | case TYPE_CODE_INT: | |
1120 | case TYPE_CODE_FLT: | |
1121 | case TYPE_CODE_SET: | |
1122 | case TYPE_CODE_RANGE: | |
1123 | case TYPE_CODE_BITSTRING: | |
1124 | case TYPE_CODE_REF: | |
1125 | case TYPE_CODE_CHAR: | |
1126 | case TYPE_CODE_BOOL: | |
1127 | return TYPE_LENGTH (t); | |
1128 | ||
1129 | case TYPE_CODE_ARRAY: | |
1130 | case TYPE_CODE_COMPLEX: | |
1131 | /* TODO: What about vector types? */ | |
1132 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1133 | ||
1134 | case TYPE_CODE_STRUCT: | |
1135 | case TYPE_CODE_UNION: | |
1136 | align = 1; | |
1137 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1138 | { | |
1139 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1140 | if (falign > align) | |
1141 | align = falign; | |
1142 | } | |
1143 | return align; | |
1144 | } | |
1145 | } | |
1146 | ||
2dd604e7 RE |
1147 | /* We currently only support passing parameters in integer registers. This |
1148 | conforms with GCC's default model. Several other variants exist and | |
1149 | we should probably support some of them based on the selected ABI. */ | |
1150 | ||
1151 | static CORE_ADDR | |
7d9b040b | 1152 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1153 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1154 | struct value **args, CORE_ADDR sp, int struct_return, | |
1155 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1156 | { |
1157 | int argnum; | |
1158 | int argreg; | |
1159 | int nstack; | |
1160 | struct stack_item *si = NULL; | |
1161 | ||
6a65450a AC |
1162 | /* Set the return address. For the ARM, the return breakpoint is |
1163 | always at BP_ADDR. */ | |
2dd604e7 | 1164 | /* XXX Fix for Thumb. */ |
6a65450a | 1165 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1166 | |
1167 | /* Walk through the list of args and determine how large a temporary | |
1168 | stack is required. Need to take care here as structs may be | |
1169 | passed on the stack, and we have to to push them. */ | |
1170 | nstack = 0; | |
1171 | ||
1172 | argreg = ARM_A1_REGNUM; | |
1173 | nstack = 0; | |
1174 | ||
1175 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1176 | is correctly aligned before we start. We always do this even if | |
1177 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1178 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1179 | |
1180 | /* The struct_return pointer occupies the first parameter | |
1181 | passing register. */ | |
1182 | if (struct_return) | |
1183 | { | |
1184 | if (arm_debug) | |
1185 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1186 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1187 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1188 | argreg++; | |
1189 | } | |
1190 | ||
1191 | for (argnum = 0; argnum < nargs; argnum++) | |
1192 | { | |
1193 | int len; | |
1194 | struct type *arg_type; | |
1195 | struct type *target_type; | |
1196 | enum type_code typecode; | |
0fd88904 | 1197 | bfd_byte *val; |
2af48f68 | 1198 | int align; |
2dd604e7 | 1199 | |
df407dfe | 1200 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1201 | len = TYPE_LENGTH (arg_type); |
1202 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1203 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1204 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1205 | |
2af48f68 PB |
1206 | align = arm_type_align (arg_type); |
1207 | /* Round alignment up to a whole number of words. */ | |
1208 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1209 | /* Different ABIs have different maximum alignments. */ | |
1210 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1211 | { | |
1212 | /* The APCS ABI only requires word alignment. */ | |
1213 | align = INT_REGISTER_SIZE; | |
1214 | } | |
1215 | else | |
1216 | { | |
1217 | /* The AAPCS requires at most doubleword alignment. */ | |
1218 | if (align > INT_REGISTER_SIZE * 2) | |
1219 | align = INT_REGISTER_SIZE * 2; | |
1220 | } | |
1221 | ||
1222 | /* Push stack padding for dowubleword alignment. */ | |
1223 | if (nstack & (align - 1)) | |
1224 | { | |
1225 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1226 | nstack += INT_REGISTER_SIZE; | |
1227 | } | |
1228 | ||
1229 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1230 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1231 | && align > INT_REGISTER_SIZE | |
1232 | && argreg & 1) | |
1233 | argreg++; | |
1234 | ||
2dd604e7 RE |
1235 | /* If the argument is a pointer to a function, and it is a |
1236 | Thumb function, create a LOCAL copy of the value and set | |
1237 | the THUMB bit in it. */ | |
1238 | if (TYPE_CODE_PTR == typecode | |
1239 | && target_type != NULL | |
1240 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1241 | { | |
7c0b4a20 | 1242 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1243 | if (arm_pc_is_thumb (regval)) |
1244 | { | |
1245 | val = alloca (len); | |
fbd9dcd3 | 1246 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1247 | } |
1248 | } | |
1249 | ||
1250 | /* Copy the argument to general registers or the stack in | |
1251 | register-sized pieces. Large arguments are split between | |
1252 | registers and stack. */ | |
1253 | while (len > 0) | |
1254 | { | |
b1e29e33 | 1255 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1256 | |
1257 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1258 | { | |
1259 | /* The argument is being passed in a general purpose | |
1260 | register. */ | |
7c0b4a20 | 1261 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1262 | if (arm_debug) |
1263 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1264 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1265 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1266 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1267 | argreg++; | |
1268 | } | |
1269 | else | |
1270 | { | |
1271 | /* Push the arguments onto the stack. */ | |
1272 | if (arm_debug) | |
1273 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1274 | argnum, nstack); | |
b1e29e33 AC |
1275 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1276 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1277 | } |
1278 | ||
1279 | len -= partial_len; | |
1280 | val += partial_len; | |
1281 | } | |
1282 | } | |
1283 | /* If we have an odd number of words to push, then decrement the stack | |
1284 | by one word now, so first stack argument will be dword aligned. */ | |
1285 | if (nstack & 4) | |
1286 | sp -= 4; | |
1287 | ||
1288 | while (si) | |
1289 | { | |
1290 | sp -= si->len; | |
1291 | write_memory (sp, si->data, si->len); | |
1292 | si = pop_stack_item (si); | |
1293 | } | |
1294 | ||
1295 | /* Finally, update teh SP register. */ | |
1296 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1297 | ||
1298 | return sp; | |
1299 | } | |
1300 | ||
c906108c | 1301 | static void |
ed9a39eb | 1302 | print_fpu_flags (int flags) |
c906108c | 1303 | { |
c5aa993b JM |
1304 | if (flags & (1 << 0)) |
1305 | fputs ("IVO ", stdout); | |
1306 | if (flags & (1 << 1)) | |
1307 | fputs ("DVZ ", stdout); | |
1308 | if (flags & (1 << 2)) | |
1309 | fputs ("OFL ", stdout); | |
1310 | if (flags & (1 << 3)) | |
1311 | fputs ("UFL ", stdout); | |
1312 | if (flags & (1 << 4)) | |
1313 | fputs ("INX ", stdout); | |
1314 | putchar ('\n'); | |
c906108c SS |
1315 | } |
1316 | ||
5e74b15c RE |
1317 | /* Print interesting information about the floating point processor |
1318 | (if present) or emulator. */ | |
34e8f22d | 1319 | static void |
d855c300 | 1320 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1321 | struct frame_info *frame, const char *args) |
c906108c | 1322 | { |
52f0bd74 | 1323 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1324 | int type; |
1325 | ||
1326 | type = (status >> 24) & 127; | |
edefbb7c AC |
1327 | if (status & (1 << 31)) |
1328 | printf (_("Hardware FPU type %d\n"), type); | |
1329 | else | |
1330 | printf (_("Software FPU type %d\n"), type); | |
1331 | /* i18n: [floating point unit] mask */ | |
1332 | fputs (_("mask: "), stdout); | |
c5aa993b | 1333 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1334 | /* i18n: [floating point unit] flags */ |
1335 | fputs (_("flags: "), stdout); | |
c5aa993b | 1336 | print_fpu_flags (status); |
c906108c SS |
1337 | } |
1338 | ||
34e8f22d RE |
1339 | /* Return the GDB type object for the "standard" data type of data in |
1340 | register N. */ | |
1341 | ||
1342 | static struct type * | |
7a5ea0d4 | 1343 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1344 | { |
34e8f22d | 1345 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1346 | { |
d7449b42 | 1347 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1348 | return builtin_type_arm_ext_big; |
1349 | else | |
1350 | return builtin_type_arm_ext_littlebyte_bigword; | |
1351 | } | |
1352 | else | |
1353 | return builtin_type_int32; | |
1354 | } | |
1355 | ||
34e8f22d RE |
1356 | /* Index within `registers' of the first byte of the space for |
1357 | register N. */ | |
1358 | ||
1359 | static int | |
1360 | arm_register_byte (int regnum) | |
1361 | { | |
1362 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1363 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1364 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1365 | return (NUM_GREGS * INT_REGISTER_SIZE |
1366 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1367 | else |
7a5ea0d4 DJ |
1368 | return (NUM_GREGS * INT_REGISTER_SIZE |
1369 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1370 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1371 | } | |
1372 | ||
26216b98 AC |
1373 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1374 | static int | |
1375 | arm_register_sim_regno (int regnum) | |
1376 | { | |
1377 | int reg = regnum; | |
1378 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1379 | ||
1380 | if (reg < NUM_GREGS) | |
1381 | return SIM_ARM_R0_REGNUM + reg; | |
1382 | reg -= NUM_GREGS; | |
1383 | ||
1384 | if (reg < NUM_FREGS) | |
1385 | return SIM_ARM_FP0_REGNUM + reg; | |
1386 | reg -= NUM_FREGS; | |
1387 | ||
1388 | if (reg < NUM_SREGS) | |
1389 | return SIM_ARM_FPS_REGNUM + reg; | |
1390 | reg -= NUM_SREGS; | |
1391 | ||
edefbb7c | 1392 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1393 | } |
34e8f22d | 1394 | |
a37b3cc0 AC |
1395 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1396 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1397 | It is thought that this is is the floating-point register format on | |
1398 | little-endian systems. */ | |
c906108c | 1399 | |
ed9a39eb | 1400 | static void |
b508a996 RE |
1401 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1402 | void *dbl) | |
c906108c | 1403 | { |
a37b3cc0 | 1404 | DOUBLEST d; |
d7449b42 | 1405 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1406 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1407 | else | |
1408 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1409 | ptr, &d); | |
b508a996 | 1410 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1411 | } |
1412 | ||
34e8f22d | 1413 | static void |
b508a996 | 1414 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1415 | { |
a37b3cc0 | 1416 | DOUBLEST d; |
b508a996 | 1417 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1418 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1419 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1420 | else | |
1421 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1422 | &d, dbl); | |
c906108c | 1423 | } |
ed9a39eb | 1424 | |
c906108c | 1425 | static int |
ed9a39eb | 1426 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1427 | { |
1428 | if (cond == INST_AL || cond == INST_NV) | |
1429 | return 1; | |
1430 | ||
1431 | switch (cond) | |
1432 | { | |
1433 | case INST_EQ: | |
1434 | return ((status_reg & FLAG_Z) != 0); | |
1435 | case INST_NE: | |
1436 | return ((status_reg & FLAG_Z) == 0); | |
1437 | case INST_CS: | |
1438 | return ((status_reg & FLAG_C) != 0); | |
1439 | case INST_CC: | |
1440 | return ((status_reg & FLAG_C) == 0); | |
1441 | case INST_MI: | |
1442 | return ((status_reg & FLAG_N) != 0); | |
1443 | case INST_PL: | |
1444 | return ((status_reg & FLAG_N) == 0); | |
1445 | case INST_VS: | |
1446 | return ((status_reg & FLAG_V) != 0); | |
1447 | case INST_VC: | |
1448 | return ((status_reg & FLAG_V) == 0); | |
1449 | case INST_HI: | |
1450 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1451 | case INST_LS: | |
1452 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1453 | case INST_GE: | |
1454 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1455 | case INST_LT: | |
1456 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1457 | case INST_GT: | |
1458 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1459 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1460 | case INST_LE: |
1461 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1462 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1463 | } |
1464 | return 1; | |
1465 | } | |
1466 | ||
9512d7fd | 1467 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1468 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1469 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1470 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1471 | #define sbits(obj,st,fn) \ | |
1472 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1473 | #define BranchDest(addr,instr) \ | |
1474 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1475 | #define ARM_PC_32 1 | |
1476 | ||
1477 | static unsigned long | |
ed9a39eb JM |
1478 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1479 | unsigned long status_reg) | |
c906108c SS |
1480 | { |
1481 | unsigned long res, shift; | |
1482 | int rm = bits (inst, 0, 3); | |
1483 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1484 | |
1485 | if (bit (inst, 4)) | |
c906108c SS |
1486 | { |
1487 | int rs = bits (inst, 8, 11); | |
1488 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1489 | } | |
1490 | else | |
1491 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1492 | |
1493 | res = (rm == 15 | |
c906108c | 1494 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1495 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1496 | : read_register (rm)); |
1497 | ||
1498 | switch (shifttype) | |
1499 | { | |
c5aa993b | 1500 | case 0: /* LSL */ |
c906108c SS |
1501 | res = shift >= 32 ? 0 : res << shift; |
1502 | break; | |
c5aa993b JM |
1503 | |
1504 | case 1: /* LSR */ | |
c906108c SS |
1505 | res = shift >= 32 ? 0 : res >> shift; |
1506 | break; | |
1507 | ||
c5aa993b JM |
1508 | case 2: /* ASR */ |
1509 | if (shift >= 32) | |
1510 | shift = 31; | |
c906108c SS |
1511 | res = ((res & 0x80000000L) |
1512 | ? ~((~res) >> shift) : res >> shift); | |
1513 | break; | |
1514 | ||
c5aa993b | 1515 | case 3: /* ROR/RRX */ |
c906108c SS |
1516 | shift &= 31; |
1517 | if (shift == 0) | |
1518 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1519 | else | |
c5aa993b | 1520 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1521 | break; |
1522 | } | |
1523 | ||
1524 | return res & 0xffffffff; | |
1525 | } | |
1526 | ||
c906108c SS |
1527 | /* Return number of 1-bits in VAL. */ |
1528 | ||
1529 | static int | |
ed9a39eb | 1530 | bitcount (unsigned long val) |
c906108c SS |
1531 | { |
1532 | int nbits; | |
1533 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1534 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1535 | return nbits; |
1536 | } | |
1537 | ||
34e8f22d | 1538 | CORE_ADDR |
ed9a39eb | 1539 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1540 | { |
c5aa993b | 1541 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1542 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1543 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1544 | unsigned long offset; |
1545 | ||
1546 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1547 | { | |
1548 | CORE_ADDR sp; | |
1549 | ||
1550 | /* Fetch the saved PC from the stack. It's stored above | |
1551 | all of the other registers. */ | |
b1e29e33 | 1552 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1553 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1554 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1555 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1556 | if (nextpc == pc) | |
edefbb7c | 1557 | error (_("Infinite loop detected")); |
c906108c SS |
1558 | } |
1559 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1560 | { | |
34e8f22d | 1561 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1562 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1563 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1564 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1565 | } | |
1566 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1567 | { | |
1568 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1569 | } | |
aa17d93e | 1570 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c SS |
1571 | { |
1572 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1573 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1574 | nextpc = pc_val + offset; |
aa17d93e DJ |
1575 | /* For BLX make sure to clear the low bits. */ |
1576 | if (bits (inst2, 11, 12) == 1) | |
1577 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1578 | } |
aa17d93e | 1579 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1580 | { |
1581 | if (bits (inst1, 3, 6) == 0x0f) | |
1582 | nextpc = pc_val; | |
1583 | else | |
1584 | nextpc = read_register (bits (inst1, 3, 6)); | |
1585 | ||
1586 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1587 | if (nextpc == pc) | |
edefbb7c | 1588 | error (_("Infinite loop detected")); |
9498281f | 1589 | } |
c906108c SS |
1590 | |
1591 | return nextpc; | |
1592 | } | |
1593 | ||
34e8f22d | 1594 | CORE_ADDR |
ed9a39eb | 1595 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1596 | { |
1597 | unsigned long pc_val; | |
1598 | unsigned long this_instr; | |
1599 | unsigned long status; | |
1600 | CORE_ADDR nextpc; | |
1601 | ||
1602 | if (arm_pc_is_thumb (pc)) | |
1603 | return thumb_get_next_pc (pc); | |
1604 | ||
1605 | pc_val = (unsigned long) pc; | |
1606 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1607 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1608 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1609 | |
1610 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1611 | { | |
1612 | switch (bits (this_instr, 24, 27)) | |
1613 | { | |
c5aa993b | 1614 | case 0x0: |
94c30b78 | 1615 | case 0x1: /* data processing */ |
c5aa993b JM |
1616 | case 0x2: |
1617 | case 0x3: | |
c906108c SS |
1618 | { |
1619 | unsigned long operand1, operand2, result = 0; | |
1620 | unsigned long rn; | |
1621 | int c; | |
c5aa993b | 1622 | |
c906108c SS |
1623 | if (bits (this_instr, 12, 15) != 15) |
1624 | break; | |
1625 | ||
1626 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1627 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1628 | error (_("Invalid update to pc in instruction")); |
c906108c | 1629 | |
9498281f DJ |
1630 | /* BX <reg>, BLX <reg> */ |
1631 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1632 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1633 | { | |
1634 | rn = bits (this_instr, 0, 3); | |
1635 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1636 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1637 | ||
1638 | if (nextpc == pc) | |
edefbb7c | 1639 | error (_("Infinite loop detected")); |
9498281f DJ |
1640 | |
1641 | return nextpc; | |
1642 | } | |
1643 | ||
c906108c SS |
1644 | /* Multiply into PC */ |
1645 | c = (status & FLAG_C) ? 1 : 0; | |
1646 | rn = bits (this_instr, 16, 19); | |
1647 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1648 | |
c906108c SS |
1649 | if (bit (this_instr, 25)) |
1650 | { | |
1651 | unsigned long immval = bits (this_instr, 0, 7); | |
1652 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1653 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1654 | & 0xffffffff; | |
c906108c | 1655 | } |
c5aa993b | 1656 | else /* operand 2 is a shifted register */ |
c906108c | 1657 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1658 | |
c906108c SS |
1659 | switch (bits (this_instr, 21, 24)) |
1660 | { | |
c5aa993b | 1661 | case 0x0: /*and */ |
c906108c SS |
1662 | result = operand1 & operand2; |
1663 | break; | |
1664 | ||
c5aa993b | 1665 | case 0x1: /*eor */ |
c906108c SS |
1666 | result = operand1 ^ operand2; |
1667 | break; | |
1668 | ||
c5aa993b | 1669 | case 0x2: /*sub */ |
c906108c SS |
1670 | result = operand1 - operand2; |
1671 | break; | |
1672 | ||
c5aa993b | 1673 | case 0x3: /*rsb */ |
c906108c SS |
1674 | result = operand2 - operand1; |
1675 | break; | |
1676 | ||
c5aa993b | 1677 | case 0x4: /*add */ |
c906108c SS |
1678 | result = operand1 + operand2; |
1679 | break; | |
1680 | ||
c5aa993b | 1681 | case 0x5: /*adc */ |
c906108c SS |
1682 | result = operand1 + operand2 + c; |
1683 | break; | |
1684 | ||
c5aa993b | 1685 | case 0x6: /*sbc */ |
c906108c SS |
1686 | result = operand1 - operand2 + c; |
1687 | break; | |
1688 | ||
c5aa993b | 1689 | case 0x7: /*rsc */ |
c906108c SS |
1690 | result = operand2 - operand1 + c; |
1691 | break; | |
1692 | ||
c5aa993b JM |
1693 | case 0x8: |
1694 | case 0x9: | |
1695 | case 0xa: | |
1696 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1697 | result = (unsigned long) nextpc; |
1698 | break; | |
1699 | ||
c5aa993b | 1700 | case 0xc: /*orr */ |
c906108c SS |
1701 | result = operand1 | operand2; |
1702 | break; | |
1703 | ||
c5aa993b | 1704 | case 0xd: /*mov */ |
c906108c SS |
1705 | /* Always step into a function. */ |
1706 | result = operand2; | |
c5aa993b | 1707 | break; |
c906108c | 1708 | |
c5aa993b | 1709 | case 0xe: /*bic */ |
c906108c SS |
1710 | result = operand1 & ~operand2; |
1711 | break; | |
1712 | ||
c5aa993b | 1713 | case 0xf: /*mvn */ |
c906108c SS |
1714 | result = ~operand2; |
1715 | break; | |
1716 | } | |
1717 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1718 | ||
1719 | if (nextpc == pc) | |
edefbb7c | 1720 | error (_("Infinite loop detected")); |
c906108c SS |
1721 | break; |
1722 | } | |
c5aa993b JM |
1723 | |
1724 | case 0x4: | |
1725 | case 0x5: /* data transfer */ | |
1726 | case 0x6: | |
1727 | case 0x7: | |
c906108c SS |
1728 | if (bit (this_instr, 20)) |
1729 | { | |
1730 | /* load */ | |
1731 | if (bits (this_instr, 12, 15) == 15) | |
1732 | { | |
1733 | /* rd == pc */ | |
c5aa993b | 1734 | unsigned long rn; |
c906108c | 1735 | unsigned long base; |
c5aa993b | 1736 | |
c906108c | 1737 | if (bit (this_instr, 22)) |
edefbb7c | 1738 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1739 | |
1740 | /* byte write to PC */ | |
1741 | rn = bits (this_instr, 16, 19); | |
1742 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1743 | if (bit (this_instr, 24)) | |
1744 | { | |
1745 | /* pre-indexed */ | |
1746 | int c = (status & FLAG_C) ? 1 : 0; | |
1747 | unsigned long offset = | |
c5aa993b | 1748 | (bit (this_instr, 25) |
ed9a39eb | 1749 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1750 | : bits (this_instr, 0, 11)); |
c906108c SS |
1751 | |
1752 | if (bit (this_instr, 23)) | |
1753 | base += offset; | |
1754 | else | |
1755 | base -= offset; | |
1756 | } | |
c5aa993b | 1757 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1758 | 4); |
c5aa993b | 1759 | |
c906108c SS |
1760 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1761 | ||
1762 | if (nextpc == pc) | |
edefbb7c | 1763 | error (_("Infinite loop detected")); |
c906108c SS |
1764 | } |
1765 | } | |
1766 | break; | |
c5aa993b JM |
1767 | |
1768 | case 0x8: | |
1769 | case 0x9: /* block transfer */ | |
c906108c SS |
1770 | if (bit (this_instr, 20)) |
1771 | { | |
1772 | /* LDM */ | |
1773 | if (bit (this_instr, 15)) | |
1774 | { | |
1775 | /* loading pc */ | |
1776 | int offset = 0; | |
1777 | ||
1778 | if (bit (this_instr, 23)) | |
1779 | { | |
1780 | /* up */ | |
1781 | unsigned long reglist = bits (this_instr, 0, 14); | |
1782 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1783 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1784 | offset += 4; |
1785 | } | |
1786 | else if (bit (this_instr, 24)) | |
1787 | offset = -4; | |
c5aa993b | 1788 | |
c906108c | 1789 | { |
c5aa993b JM |
1790 | unsigned long rn_val = |
1791 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1792 | nextpc = |
1793 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1794 | + offset), |
c906108c SS |
1795 | 4); |
1796 | } | |
1797 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1798 | if (nextpc == pc) | |
edefbb7c | 1799 | error (_("Infinite loop detected")); |
c906108c SS |
1800 | } |
1801 | } | |
1802 | break; | |
c5aa993b JM |
1803 | |
1804 | case 0xb: /* branch & link */ | |
1805 | case 0xa: /* branch */ | |
c906108c SS |
1806 | { |
1807 | nextpc = BranchDest (pc, this_instr); | |
1808 | ||
9498281f DJ |
1809 | /* BLX */ |
1810 | if (bits (this_instr, 28, 31) == INST_NV) | |
1811 | nextpc |= bit (this_instr, 24) << 1; | |
1812 | ||
c906108c SS |
1813 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1814 | if (nextpc == pc) | |
edefbb7c | 1815 | error (_("Infinite loop detected")); |
c906108c SS |
1816 | break; |
1817 | } | |
c5aa993b JM |
1818 | |
1819 | case 0xc: | |
1820 | case 0xd: | |
1821 | case 0xe: /* coproc ops */ | |
1822 | case 0xf: /* SWI */ | |
c906108c SS |
1823 | break; |
1824 | ||
1825 | default: | |
edefbb7c | 1826 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1827 | return (pc); |
1828 | } | |
1829 | } | |
1830 | ||
1831 | return nextpc; | |
1832 | } | |
1833 | ||
9512d7fd FN |
1834 | /* single_step() is called just before we want to resume the inferior, |
1835 | if we want to single-step it but there is no hardware or kernel | |
1836 | single-step support. We find the target of the coming instruction | |
1837 | and breakpoint it. | |
1838 | ||
94c30b78 MS |
1839 | single_step() is also called just after the inferior stops. If we |
1840 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1841 | |
34e8f22d RE |
1842 | static void |
1843 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1844 | { |
b8d5e71d | 1845 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
1846 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
1847 | ||
1848 | if (insert_bpt) | |
1849 | { | |
34e8f22d | 1850 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 1851 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1852 | } |
1853 | else | |
80fcf3f0 | 1854 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1855 | } |
9512d7fd | 1856 | |
c906108c SS |
1857 | #include "bfd-in2.h" |
1858 | #include "libcoff.h" | |
1859 | ||
1860 | static int | |
ed9a39eb | 1861 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1862 | { |
1863 | if (arm_pc_is_thumb (memaddr)) | |
1864 | { | |
c5aa993b JM |
1865 | static asymbol *asym; |
1866 | static combined_entry_type ce; | |
1867 | static struct coff_symbol_struct csym; | |
27cddce2 | 1868 | static struct bfd fake_bfd; |
c5aa993b | 1869 | static bfd_target fake_target; |
c906108c SS |
1870 | |
1871 | if (csym.native == NULL) | |
1872 | { | |
da3c6d4a MS |
1873 | /* Create a fake symbol vector containing a Thumb symbol. |
1874 | This is solely so that the code in print_insn_little_arm() | |
1875 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1876 | the presence of a Thumb symbol and switch to decoding | |
1877 | Thumb instructions. */ | |
c5aa993b JM |
1878 | |
1879 | fake_target.flavour = bfd_target_coff_flavour; | |
1880 | fake_bfd.xvec = &fake_target; | |
c906108c | 1881 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1882 | csym.native = &ce; |
1883 | csym.symbol.the_bfd = &fake_bfd; | |
1884 | csym.symbol.name = "fake"; | |
1885 | asym = (asymbol *) & csym; | |
c906108c | 1886 | } |
c5aa993b | 1887 | |
c906108c | 1888 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1889 | info->symbols = &asym; |
c906108c SS |
1890 | } |
1891 | else | |
1892 | info->symbols = NULL; | |
c5aa993b | 1893 | |
d7449b42 | 1894 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1895 | return print_insn_big_arm (memaddr, info); |
1896 | else | |
1897 | return print_insn_little_arm (memaddr, info); | |
1898 | } | |
1899 | ||
66e810cd RE |
1900 | /* The following define instruction sequences that will cause ARM |
1901 | cpu's to take an undefined instruction trap. These are used to | |
1902 | signal a breakpoint to GDB. | |
1903 | ||
1904 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1905 | modes. A different instruction is required for each mode. The ARM | |
1906 | cpu's can also be big or little endian. Thus four different | |
1907 | instructions are needed to support all cases. | |
1908 | ||
1909 | Note: ARMv4 defines several new instructions that will take the | |
1910 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1911 | not in fact add the new instructions. The new undefined | |
1912 | instructions in ARMv4 are all instructions that had no defined | |
1913 | behaviour in earlier chips. There is no guarantee that they will | |
1914 | raise an exception, but may be treated as NOP's. In practice, it | |
1915 | may only safe to rely on instructions matching: | |
1916 | ||
1917 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1918 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1919 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1920 | ||
1921 | Even this may only true if the condition predicate is true. The | |
1922 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1923 | ||
1924 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1925 | and NetBSD all use a software interrupt rather than an undefined | |
1926 | instruction to force a trap. This can be handled by by the | |
1927 | abi-specific code during establishment of the gdbarch vector. */ | |
1928 | ||
1929 | ||
d7b486e7 RE |
1930 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1931 | override these definitions. */ | |
66e810cd RE |
1932 | #ifndef ARM_LE_BREAKPOINT |
1933 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1934 | #endif | |
1935 | #ifndef ARM_BE_BREAKPOINT | |
1936 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1937 | #endif | |
1938 | #ifndef THUMB_LE_BREAKPOINT | |
1939 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1940 | #endif | |
1941 | #ifndef THUMB_BE_BREAKPOINT | |
1942 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1943 | #endif | |
1944 | ||
1945 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1946 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1947 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1948 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1949 | ||
34e8f22d RE |
1950 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1951 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1952 | breakpoint should be used. It returns a pointer to a string of |
1953 | bytes that encode a breakpoint instruction, stores the length of | |
1954 | the string to *lenptr, and adjusts the program counter (if | |
1955 | necessary) to point to the actual memory location where the | |
c906108c SS |
1956 | breakpoint should be inserted. */ |
1957 | ||
34e8f22d RE |
1958 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
1959 | breakpoints and storing their handles instread of what was in | |
1960 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 1961 | otherwise remote-rdp will have to change. */ |
34e8f22d | 1962 | |
ab89facf | 1963 | static const unsigned char * |
ed9a39eb | 1964 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1965 | { |
66e810cd RE |
1966 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1967 | ||
4bf7064c | 1968 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 1969 | { |
66e810cd RE |
1970 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1971 | *lenptr = tdep->thumb_breakpoint_size; | |
1972 | return tdep->thumb_breakpoint; | |
c906108c SS |
1973 | } |
1974 | else | |
1975 | { | |
66e810cd RE |
1976 | *lenptr = tdep->arm_breakpoint_size; |
1977 | return tdep->arm_breakpoint; | |
c906108c SS |
1978 | } |
1979 | } | |
ed9a39eb JM |
1980 | |
1981 | /* Extract from an array REGBUF containing the (raw) register state a | |
1982 | function return value of type TYPE, and copy that, in virtual | |
1983 | format, into VALBUF. */ | |
1984 | ||
34e8f22d | 1985 | static void |
5238cf52 MK |
1986 | arm_extract_return_value (struct type *type, struct regcache *regs, |
1987 | gdb_byte *valbuf) | |
ed9a39eb JM |
1988 | { |
1989 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 | 1990 | { |
28e97307 | 1991 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
1992 | { |
1993 | case ARM_FLOAT_FPA: | |
b508a996 RE |
1994 | { |
1995 | /* The value is in register F0 in internal format. We need to | |
1996 | extract the raw value and then convert it to the desired | |
1997 | internal type. */ | |
7a5ea0d4 | 1998 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
1999 | |
2000 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2001 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2002 | valbuf); | |
2003 | } | |
08216dd7 RE |
2004 | break; |
2005 | ||
fd50bc42 | 2006 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2007 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2008 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2009 | if (TYPE_LENGTH (type) > 4) | |
2010 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2011 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2012 | break; |
2013 | ||
2014 | default: | |
2015 | internal_error | |
2016 | (__FILE__, __LINE__, | |
edefbb7c | 2017 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2018 | break; |
2019 | } | |
2020 | } | |
b508a996 RE |
2021 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2022 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2023 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2024 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2025 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2026 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2027 | { | |
2028 | /* If the the type is a plain integer, then the access is | |
2029 | straight-forward. Otherwise we have to play around a bit more. */ | |
2030 | int len = TYPE_LENGTH (type); | |
2031 | int regno = ARM_A1_REGNUM; | |
2032 | ULONGEST tmp; | |
2033 | ||
2034 | while (len > 0) | |
2035 | { | |
2036 | /* By using store_unsigned_integer we avoid having to do | |
2037 | anything special for small big-endian values. */ | |
2038 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2039 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2040 | (len > INT_REGISTER_SIZE |
2041 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2042 | tmp); |
7a5ea0d4 DJ |
2043 | len -= INT_REGISTER_SIZE; |
2044 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2045 | } |
2046 | } | |
ed9a39eb | 2047 | else |
b508a996 RE |
2048 | { |
2049 | /* For a structure or union the behaviour is as if the value had | |
2050 | been stored to word-aligned memory and then loaded into | |
2051 | registers with 32-bit load instruction(s). */ | |
2052 | int len = TYPE_LENGTH (type); | |
2053 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2054 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2055 | |
2056 | while (len > 0) | |
2057 | { | |
2058 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2059 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2060 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2061 | len -= INT_REGISTER_SIZE; | |
2062 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2063 | } |
2064 | } | |
34e8f22d RE |
2065 | } |
2066 | ||
67255d04 RE |
2067 | |
2068 | /* Will a function return an aggregate type in memory or in a | |
2069 | register? Return 0 if an aggregate type can be returned in a | |
2070 | register, 1 if it must be returned in memory. */ | |
2071 | ||
2072 | static int | |
2af48f68 | 2073 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2074 | { |
2075 | int nRc; | |
52f0bd74 | 2076 | enum type_code code; |
67255d04 | 2077 | |
44e1a9eb DJ |
2078 | CHECK_TYPEDEF (type); |
2079 | ||
67255d04 RE |
2080 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2081 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2082 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2083 | offset of each addressable subfield must be zero. Note that bit | |
2084 | fields are not addressable, and all addressable subfields of | |
2085 | unions always start at offset zero. | |
67255d04 RE |
2086 | |
2087 | This function is based on the behaviour of GCC 2.95.1. | |
2088 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2089 | ||
2090 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2091 | parameters correctly for a function returning the following | |
2092 | structure: struct { float f;}; This should be returned in memory, | |
2093 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2094 | know of any way to detect if a function like the above has been | |
2095 | compiled with the correct calling convention. */ | |
2096 | ||
2097 | /* All aggregate types that won't fit in a register must be returned | |
2098 | in memory. */ | |
b1e29e33 | 2099 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2100 | { |
2101 | return 1; | |
2102 | } | |
2103 | ||
2af48f68 PB |
2104 | /* The AAPCS says all aggregates not larger than a word are returned |
2105 | in a register. */ | |
2106 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2107 | return 0; | |
2108 | ||
67255d04 RE |
2109 | /* The only aggregate types that can be returned in a register are |
2110 | structs and unions. Arrays must be returned in memory. */ | |
2111 | code = TYPE_CODE (type); | |
2112 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2113 | { | |
2114 | return 1; | |
2115 | } | |
2116 | ||
2117 | /* Assume all other aggregate types can be returned in a register. | |
2118 | Run a check for structures, unions and arrays. */ | |
2119 | nRc = 0; | |
2120 | ||
2121 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2122 | { | |
2123 | int i; | |
2124 | /* Need to check if this struct/union is "integer" like. For | |
2125 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2126 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2127 | subfield must be zero. Note that bit fields are not | |
2128 | addressable, and unions always start at offset zero. If any | |
2129 | of the subfields is a floating point type, the struct/union | |
2130 | cannot be an integer type. */ | |
67255d04 RE |
2131 | |
2132 | /* For each field in the object, check: | |
2133 | 1) Is it FP? --> yes, nRc = 1; | |
2134 | 2) Is it addressable (bitpos != 0) and | |
2135 | not packed (bitsize == 0)? | |
2136 | --> yes, nRc = 1 | |
2137 | */ | |
2138 | ||
2139 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2140 | { | |
2141 | enum type_code field_type_code; | |
44e1a9eb | 2142 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2143 | |
2144 | /* Is it a floating point type field? */ | |
2145 | if (field_type_code == TYPE_CODE_FLT) | |
2146 | { | |
2147 | nRc = 1; | |
2148 | break; | |
2149 | } | |
2150 | ||
2151 | /* If bitpos != 0, then we have to care about it. */ | |
2152 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2153 | { | |
2154 | /* Bitfields are not addressable. If the field bitsize is | |
2155 | zero, then the field is not packed. Hence it cannot be | |
2156 | a bitfield or any other packed type. */ | |
2157 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2158 | { | |
2159 | nRc = 1; | |
2160 | break; | |
2161 | } | |
2162 | } | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | return nRc; | |
2167 | } | |
2168 | ||
34e8f22d RE |
2169 | /* Write into appropriate registers a function return value of type |
2170 | TYPE, given in virtual format. */ | |
2171 | ||
2172 | static void | |
b508a996 | 2173 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2174 | const gdb_byte *valbuf) |
34e8f22d RE |
2175 | { |
2176 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2177 | { | |
7a5ea0d4 | 2178 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2179 | |
28e97307 | 2180 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2181 | { |
2182 | case ARM_FLOAT_FPA: | |
2183 | ||
b508a996 RE |
2184 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2185 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2186 | break; |
2187 | ||
fd50bc42 | 2188 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2189 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2190 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2191 | if (TYPE_LENGTH (type) > 4) | |
2192 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2193 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2194 | break; |
2195 | ||
2196 | default: | |
2197 | internal_error | |
2198 | (__FILE__, __LINE__, | |
edefbb7c | 2199 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2200 | break; |
2201 | } | |
34e8f22d | 2202 | } |
b508a996 RE |
2203 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2204 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2205 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2206 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2207 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2208 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2209 | { | |
2210 | if (TYPE_LENGTH (type) <= 4) | |
2211 | { | |
2212 | /* Values of one word or less are zero/sign-extended and | |
2213 | returned in r0. */ | |
7a5ea0d4 | 2214 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2215 | LONGEST val = unpack_long (type, valbuf); |
2216 | ||
7a5ea0d4 | 2217 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2218 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2219 | } | |
2220 | else | |
2221 | { | |
2222 | /* Integral values greater than one word are stored in consecutive | |
2223 | registers starting with r0. This will always be a multiple of | |
2224 | the regiser size. */ | |
2225 | int len = TYPE_LENGTH (type); | |
2226 | int regno = ARM_A1_REGNUM; | |
2227 | ||
2228 | while (len > 0) | |
2229 | { | |
2230 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2231 | len -= INT_REGISTER_SIZE; |
2232 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2233 | } |
2234 | } | |
2235 | } | |
34e8f22d | 2236 | else |
b508a996 RE |
2237 | { |
2238 | /* For a structure or union the behaviour is as if the value had | |
2239 | been stored to word-aligned memory and then loaded into | |
2240 | registers with 32-bit load instruction(s). */ | |
2241 | int len = TYPE_LENGTH (type); | |
2242 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2243 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2244 | |
2245 | while (len > 0) | |
2246 | { | |
2247 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2248 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2249 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2250 | len -= INT_REGISTER_SIZE; |
2251 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2252 | } |
2253 | } | |
34e8f22d RE |
2254 | } |
2255 | ||
2af48f68 PB |
2256 | |
2257 | /* Handle function return values. */ | |
2258 | ||
2259 | static enum return_value_convention | |
2260 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
2261 | struct regcache *regcache, void *readbuf, | |
2262 | const void *writebuf) | |
2263 | { | |
2264 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2265 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2266 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2267 | { | |
2268 | if (arm_return_in_memory (gdbarch, valtype)) | |
2269 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2270 | } | |
2271 | ||
2272 | if (writebuf) | |
2273 | arm_store_return_value (valtype, regcache, writebuf); | |
2274 | ||
2275 | if (readbuf) | |
2276 | arm_extract_return_value (valtype, regcache, readbuf); | |
2277 | ||
2278 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2279 | } | |
2280 | ||
2281 | ||
9df628e0 RE |
2282 | static int |
2283 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2284 | { | |
2285 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2286 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2287 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2288 | ||
2289 | jb_addr = read_register (ARM_A1_REGNUM); | |
2290 | ||
2291 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2292 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2293 | return 0; |
2294 | ||
7a5ea0d4 | 2295 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2296 | return 1; |
2297 | } | |
2298 | ||
ed9a39eb | 2299 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2300 | |
2301 | int | |
ed9a39eb | 2302 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2303 | { |
2304 | CORE_ADDR start_addr; | |
2305 | ||
ed9a39eb JM |
2306 | /* Find the starting address of the function containing the PC. If |
2307 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2308 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2309 | &start_addr, NULL)) | |
c906108c SS |
2310 | return 0; |
2311 | ||
2312 | return strncmp (name, "_call_via_r", 11) == 0; | |
2313 | } | |
2314 | ||
ed9a39eb JM |
2315 | /* If PC is in a Thumb call or return stub, return the address of the |
2316 | target PC, which is in a register. The thunk functions are called | |
2317 | _called_via_xx, where x is the register name. The possible names | |
2318 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2319 | |
2320 | CORE_ADDR | |
ed9a39eb | 2321 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2322 | { |
c5aa993b | 2323 | char *name; |
c906108c SS |
2324 | CORE_ADDR start_addr; |
2325 | ||
2326 | /* Find the starting address and name of the function containing the PC. */ | |
2327 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2328 | return 0; | |
2329 | ||
2330 | /* Call thunks always start with "_call_via_". */ | |
2331 | if (strncmp (name, "_call_via_", 10) == 0) | |
2332 | { | |
ed9a39eb JM |
2333 | /* Use the name suffix to determine which register contains the |
2334 | target PC. */ | |
c5aa993b JM |
2335 | static char *table[15] = |
2336 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2337 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2338 | }; | |
c906108c SS |
2339 | int regno; |
2340 | ||
2341 | for (regno = 0; regno <= 14; regno++) | |
2342 | if (strcmp (&name[10], table[regno]) == 0) | |
2343 | return read_register (regno); | |
2344 | } | |
ed9a39eb | 2345 | |
c5aa993b | 2346 | return 0; /* not a stub */ |
c906108c SS |
2347 | } |
2348 | ||
afd7eef0 RE |
2349 | static void |
2350 | set_arm_command (char *args, int from_tty) | |
2351 | { | |
edefbb7c AC |
2352 | printf_unfiltered (_("\ |
2353 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2354 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2355 | } | |
2356 | ||
2357 | static void | |
2358 | show_arm_command (char *args, int from_tty) | |
2359 | { | |
26304000 | 2360 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2361 | } |
2362 | ||
28e97307 DJ |
2363 | static void |
2364 | arm_update_current_architecture (void) | |
fd50bc42 | 2365 | { |
28e97307 | 2366 | struct gdbarch_info info; |
fd50bc42 | 2367 | |
28e97307 DJ |
2368 | /* If the current architecture is not ARM, we have nothing to do. */ |
2369 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2370 | return; | |
fd50bc42 | 2371 | |
28e97307 DJ |
2372 | /* Update the architecture. */ |
2373 | gdbarch_info_init (&info); | |
fd50bc42 | 2374 | |
28e97307 DJ |
2375 | if (!gdbarch_update_p (info)) |
2376 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2377 | } |
2378 | ||
2379 | static void | |
2380 | set_fp_model_sfunc (char *args, int from_tty, | |
2381 | struct cmd_list_element *c) | |
2382 | { | |
2383 | enum arm_float_model fp_model; | |
2384 | ||
2385 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2386 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2387 | { | |
2388 | arm_fp_model = fp_model; | |
2389 | break; | |
2390 | } | |
2391 | ||
2392 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2393 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2394 | current_fp_model); |
2395 | ||
28e97307 | 2396 | arm_update_current_architecture (); |
fd50bc42 RE |
2397 | } |
2398 | ||
2399 | static void | |
08546159 AC |
2400 | show_fp_model (struct ui_file *file, int from_tty, |
2401 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2402 | { |
2403 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2404 | ||
28e97307 | 2405 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2406 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2407 | fprintf_filtered (file, _("\ |
2408 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2409 | fp_model_strings[tdep->fp_model]); | |
2410 | else | |
2411 | fprintf_filtered (file, _("\ | |
2412 | The current ARM floating point model is \"%s\".\n"), | |
2413 | fp_model_strings[arm_fp_model]); | |
2414 | } | |
2415 | ||
2416 | static void | |
2417 | arm_set_abi (char *args, int from_tty, | |
2418 | struct cmd_list_element *c) | |
2419 | { | |
2420 | enum arm_abi_kind arm_abi; | |
2421 | ||
2422 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2423 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2424 | { | |
2425 | arm_abi_global = arm_abi; | |
2426 | break; | |
2427 | } | |
2428 | ||
2429 | if (arm_abi == ARM_ABI_LAST) | |
2430 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2431 | arm_abi_string); | |
2432 | ||
2433 | arm_update_current_architecture (); | |
2434 | } | |
2435 | ||
2436 | static void | |
2437 | arm_show_abi (struct ui_file *file, int from_tty, | |
2438 | struct cmd_list_element *c, const char *value) | |
2439 | { | |
2440 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2441 | ||
2442 | if (arm_abi_global == ARM_ABI_AUTO | |
2443 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2444 | fprintf_filtered (file, _("\ | |
2445 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2446 | arm_abi_strings[tdep->arm_abi]); | |
2447 | else | |
2448 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2449 | arm_abi_string); | |
fd50bc42 RE |
2450 | } |
2451 | ||
afd7eef0 RE |
2452 | /* If the user changes the register disassembly style used for info |
2453 | register and other commands, we have to also switch the style used | |
2454 | in opcodes for disassembly output. This function is run in the "set | |
2455 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2456 | |
2457 | static void | |
afd7eef0 | 2458 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2459 | struct cmd_list_element *c) |
2460 | { | |
afd7eef0 | 2461 | set_disassembly_style (); |
bc90b915 FN |
2462 | } |
2463 | \f | |
966fbf70 | 2464 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2465 | static const char * |
34e8f22d | 2466 | arm_register_name (int i) |
966fbf70 RE |
2467 | { |
2468 | return arm_register_names[i]; | |
2469 | } | |
2470 | ||
bc90b915 | 2471 | static void |
afd7eef0 | 2472 | set_disassembly_style (void) |
bc90b915 | 2473 | { |
4bd7b427 | 2474 | const char *setname, *setdesc, *const *regnames; |
bc90b915 FN |
2475 | int numregs, j; |
2476 | ||
afd7eef0 | 2477 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2478 | int current = 0; |
2479 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2480 | while ((disassembly_style != setname) |
2481 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2482 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2483 | current_option = current; | |
2484 | ||
94c30b78 | 2485 | /* Fill our copy. */ |
bc90b915 FN |
2486 | for (j = 0; j < numregs; j++) |
2487 | arm_register_names[j] = (char *) regnames[j]; | |
2488 | ||
94c30b78 | 2489 | /* Adjust case. */ |
34e8f22d | 2490 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2491 | { |
34e8f22d RE |
2492 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2493 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2494 | } |
2495 | else | |
2496 | { | |
34e8f22d RE |
2497 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2498 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2499 | } |
2500 | ||
94c30b78 | 2501 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2502 | set_arm_regname_option (current); |
2503 | } | |
2504 | ||
082fc60d RE |
2505 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2506 | function. */ | |
2507 | ||
2508 | static int | |
2509 | coff_sym_is_thumb (int val) | |
2510 | { | |
2511 | return (val == C_THUMBEXT || | |
2512 | val == C_THUMBSTAT || | |
2513 | val == C_THUMBEXTFUNC || | |
2514 | val == C_THUMBSTATFUNC || | |
2515 | val == C_THUMBLABEL); | |
2516 | } | |
2517 | ||
2518 | /* arm_coff_make_msymbol_special() | |
2519 | arm_elf_make_msymbol_special() | |
2520 | ||
2521 | These functions test whether the COFF or ELF symbol corresponds to | |
2522 | an address in thumb code, and set a "special" bit in a minimal | |
2523 | symbol to indicate that it does. */ | |
2524 | ||
34e8f22d | 2525 | static void |
082fc60d RE |
2526 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2527 | { | |
2528 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2529 | STT_ARM_TFUNC). */ | |
2530 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2531 | == STT_LOPROC) | |
2532 | MSYMBOL_SET_SPECIAL (msym); | |
2533 | } | |
2534 | ||
34e8f22d | 2535 | static void |
082fc60d RE |
2536 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2537 | { | |
2538 | if (coff_sym_is_thumb (val)) | |
2539 | MSYMBOL_SET_SPECIAL (msym); | |
2540 | } | |
2541 | ||
756fe439 DJ |
2542 | static void |
2543 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2544 | { | |
2545 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2546 | ||
2547 | /* If necessary, set the T bit. */ | |
2548 | if (arm_apcs_32) | |
2549 | { | |
2550 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2551 | if (arm_pc_is_thumb (pc)) | |
2552 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2553 | else | |
2554 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2555 | } | |
2556 | } | |
97e03143 | 2557 | \f |
70f80edf JT |
2558 | static enum gdb_osabi |
2559 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2560 | { |
2af48f68 | 2561 | unsigned int elfosabi; |
70f80edf | 2562 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2563 | |
70f80edf | 2564 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2565 | |
28e97307 DJ |
2566 | if (elfosabi == ELFOSABI_ARM) |
2567 | /* GNU tools use this value. Check note sections in this case, | |
2568 | as well. */ | |
2569 | bfd_map_over_sections (abfd, | |
2570 | generic_elf_osabi_sniff_abi_tag_sections, | |
2571 | &osabi); | |
97e03143 | 2572 | |
28e97307 | 2573 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2574 | return osabi; |
97e03143 RE |
2575 | } |
2576 | ||
70f80edf | 2577 | \f |
da3c6d4a MS |
2578 | /* Initialize the current architecture based on INFO. If possible, |
2579 | re-use an architecture from ARCHES, which is a list of | |
2580 | architectures already created during this debugging session. | |
97e03143 | 2581 | |
da3c6d4a MS |
2582 | Called e.g. at program startup, when reading a core file, and when |
2583 | reading a binary file. */ | |
97e03143 | 2584 | |
39bbf761 RE |
2585 | static struct gdbarch * |
2586 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2587 | { | |
97e03143 | 2588 | struct gdbarch_tdep *tdep; |
39bbf761 | 2589 | struct gdbarch *gdbarch; |
28e97307 DJ |
2590 | struct gdbarch_list *best_arch; |
2591 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2592 | enum arm_float_model fp_model = arm_fp_model; | |
39bbf761 | 2593 | |
28e97307 DJ |
2594 | /* If we have an object to base this architecture on, try to determine |
2595 | its ABI. */ | |
39bbf761 | 2596 | |
28e97307 | 2597 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2598 | { |
28e97307 DJ |
2599 | int ei_osabi; |
2600 | ||
4be87837 | 2601 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2602 | { |
4be87837 DJ |
2603 | case bfd_target_aout_flavour: |
2604 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2605 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2606 | break; |
97e03143 | 2607 | |
4be87837 DJ |
2608 | case bfd_target_coff_flavour: |
2609 | /* Assume it's an old APCS-style ABI. */ | |
2610 | /* XXX WinCE? */ | |
28e97307 DJ |
2611 | arm_abi = ARM_ABI_APCS; |
2612 | break; | |
2613 | ||
2614 | case bfd_target_elf_flavour: | |
2615 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
2616 | if (ei_osabi == ELFOSABI_ARM) | |
2617 | { | |
2618 | /* GNU tools used to use this value, but do not for EABI | |
2619 | objects. There's nowhere to tag an EABI version anyway, | |
2620 | so assume APCS. */ | |
2621 | arm_abi = ARM_ABI_APCS; | |
2622 | } | |
2623 | else if (ei_osabi == ELFOSABI_NONE) | |
2624 | { | |
2625 | int e_flags, eabi_ver; | |
2626 | ||
2627 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
2628 | eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
2629 | ||
2630 | switch (eabi_ver) | |
2631 | { | |
2632 | case EF_ARM_EABI_UNKNOWN: | |
2633 | /* Assume GNU tools. */ | |
2634 | arm_abi = ARM_ABI_APCS; | |
2635 | break; | |
2636 | ||
2637 | case EF_ARM_EABI_VER4: | |
2638 | arm_abi = ARM_ABI_AAPCS; | |
2af48f68 PB |
2639 | /* EABI binaries default to VFP float ordering. */ |
2640 | if (fp_model == ARM_FLOAT_AUTO) | |
2641 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2642 | break; |
2643 | ||
2644 | default: | |
2645 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
2646 | arm_abi = ARM_ABI_APCS; | |
2647 | break; | |
2648 | } | |
2649 | } | |
4be87837 | 2650 | break; |
97e03143 | 2651 | |
4be87837 | 2652 | default: |
28e97307 | 2653 | /* Leave it as "auto". */ |
50ceaba5 | 2654 | break; |
97e03143 RE |
2655 | } |
2656 | } | |
2657 | ||
28e97307 DJ |
2658 | /* Now that we have inferred any architecture settings that we |
2659 | can, try to inherit from the last ARM ABI. */ | |
4be87837 | 2660 | if (arches != NULL) |
28e97307 DJ |
2661 | { |
2662 | if (arm_abi == ARM_ABI_AUTO) | |
2663 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; | |
2664 | ||
2665 | if (fp_model == ARM_FLOAT_AUTO) | |
2666 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; | |
2667 | } | |
2668 | else | |
2669 | { | |
2670 | /* There was no prior ARM architecture; fill in default values. */ | |
2671 | ||
2672 | if (arm_abi == ARM_ABI_AUTO) | |
2673 | arm_abi = ARM_ABI_APCS; | |
2674 | ||
2675 | /* We used to default to FPA for generic ARM, but almost nobody | |
2676 | uses that now, and we now provide a way for the user to force | |
2677 | the model. So default to the most useful variant. */ | |
2678 | if (fp_model == ARM_FLOAT_AUTO) | |
2679 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2680 | } | |
2681 | ||
2682 | /* If there is already a candidate, use it. */ | |
2683 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2684 | best_arch != NULL; | |
2685 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2686 | { | |
2687 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
2688 | continue; | |
2689 | ||
2690 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
2691 | continue; | |
2692 | ||
2693 | /* Found a match. */ | |
2694 | break; | |
2695 | } | |
97e03143 | 2696 | |
28e97307 DJ |
2697 | if (best_arch != NULL) |
2698 | return best_arch->gdbarch; | |
2699 | ||
2700 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2701 | gdbarch = gdbarch_alloc (&info, tdep); |
2702 | ||
28e97307 DJ |
2703 | /* Record additional information about the architecture we are defining. |
2704 | These are gdbarch discriminators, like the OSABI. */ | |
2705 | tdep->arm_abi = arm_abi; | |
2706 | tdep->fp_model = fp_model; | |
08216dd7 RE |
2707 | |
2708 | /* Breakpoints. */ | |
67255d04 RE |
2709 | switch (info.byte_order) |
2710 | { | |
2711 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2712 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2713 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2714 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2715 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2716 | ||
67255d04 RE |
2717 | break; |
2718 | ||
2719 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2720 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2721 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2722 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2723 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2724 | ||
67255d04 RE |
2725 | break; |
2726 | ||
2727 | default: | |
2728 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2729 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2730 | } |
2731 | ||
d7b486e7 RE |
2732 | /* On ARM targets char defaults to unsigned. */ |
2733 | set_gdbarch_char_signed (gdbarch, 0); | |
2734 | ||
9df628e0 | 2735 | /* This should be low enough for everything. */ |
97e03143 | 2736 | tdep->lowest_pc = 0x20; |
94c30b78 | 2737 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2738 | |
2dd604e7 | 2739 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2740 | |
756fe439 DJ |
2741 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2742 | ||
148754e5 | 2743 | /* Frame handling. */ |
eb5492fa DJ |
2744 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2745 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2746 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2747 | ||
eb5492fa | 2748 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2749 | |
34e8f22d RE |
2750 | /* Address manipulation. */ |
2751 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2752 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2753 | ||
34e8f22d RE |
2754 | /* Advance PC across function entry code. */ |
2755 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2756 | ||
2757 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2758 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2759 | |
2760 | /* The stack grows downward. */ | |
2761 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2762 | ||
2763 | /* Breakpoint manipulation. */ | |
2764 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2765 | |
2766 | /* Information about registers, etc. */ | |
2767 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2768 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2769 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2770 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2771 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2772 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2773 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2774 | |
26216b98 AC |
2775 | /* Internal <-> external register number maps. */ |
2776 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2777 | ||
34e8f22d | 2778 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2779 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2780 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2781 | ||
2782 | /* Returning results. */ | |
2af48f68 | 2783 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d RE |
2784 | |
2785 | /* Single stepping. */ | |
2786 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2787 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2788 | ||
03d48a7d RE |
2789 | /* Disassembly. */ |
2790 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2791 | ||
34e8f22d RE |
2792 | /* Minsymbol frobbing. */ |
2793 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2794 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2795 | arm_coff_make_msymbol_special); | |
2796 | ||
97e03143 | 2797 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2798 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2799 | |
eb5492fa | 2800 | /* Add some default predicates. */ |
909cf6ea | 2801 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
842e1f1e | 2802 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2803 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2804 | ||
97e03143 RE |
2805 | /* Now we have tuned the configuration, set a few final things, |
2806 | based on what the OS ABI has told us. */ | |
2807 | ||
9df628e0 RE |
2808 | if (tdep->jb_pc >= 0) |
2809 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2810 | ||
08216dd7 RE |
2811 | /* Floating point sizes and format. */ |
2812 | switch (info.byte_order) | |
2813 | { | |
2814 | case BFD_ENDIAN_BIG: | |
2815 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2816 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2817 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
08216dd7 RE |
2818 | break; |
2819 | ||
2820 | case BFD_ENDIAN_LITTLE: | |
2821 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
28e97307 DJ |
2822 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
2823 | { | |
2824 | set_gdbarch_double_format | |
2825 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2826 | set_gdbarch_long_double_format | |
2827 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2828 | } | |
2829 | else | |
2830 | { | |
2831 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2832 | set_gdbarch_long_double_format (gdbarch, | |
2833 | &floatformat_ieee_double_little); | |
2834 | } | |
08216dd7 RE |
2835 | break; |
2836 | ||
2837 | default: | |
2838 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2839 | _("arm_gdbarch_init: bad byte order for float format")); |
08216dd7 RE |
2840 | } |
2841 | ||
39bbf761 RE |
2842 | return gdbarch; |
2843 | } | |
2844 | ||
97e03143 RE |
2845 | static void |
2846 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2847 | { | |
2848 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2849 | ||
2850 | if (tdep == NULL) | |
2851 | return; | |
2852 | ||
edefbb7c | 2853 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
2854 | (unsigned long) tdep->lowest_pc); |
2855 | } | |
2856 | ||
a78f21af AC |
2857 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2858 | ||
c906108c | 2859 | void |
ed9a39eb | 2860 | _initialize_arm_tdep (void) |
c906108c | 2861 | { |
bc90b915 FN |
2862 | struct ui_file *stb; |
2863 | long length; | |
26304000 | 2864 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2865 | const char *setname; |
2866 | const char *setdesc; | |
4bd7b427 | 2867 | const char *const *regnames; |
bc90b915 FN |
2868 | int numregs, i, j; |
2869 | static char *helptext; | |
edefbb7c AC |
2870 | char regdesc[1024], *rdptr = regdesc; |
2871 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 2872 | |
42cf1509 | 2873 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2874 | |
70f80edf JT |
2875 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2876 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2877 | bfd_target_elf_flavour, | |
2878 | arm_elf_osabi_sniffer); | |
2879 | ||
94c30b78 | 2880 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2881 | num_disassembly_options = get_arm_regname_num_options (); |
2882 | ||
2883 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2884 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 2885 | _("Various ARM-specific commands."), |
afd7eef0 RE |
2886 | &setarmcmdlist, "set arm ", 0, &setlist); |
2887 | ||
2888 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 2889 | _("Various ARM-specific commands."), |
afd7eef0 | 2890 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 2891 | |
94c30b78 | 2892 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2893 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2894 | |
eefe576e AC |
2895 | /* Initialize the array that will be passed to |
2896 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
2897 | valid_disassembly_styles |
2898 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2899 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2900 | { |
2901 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2902 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
2903 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
2904 | rdptr += length; | |
2905 | rest -= length; | |
94c30b78 | 2906 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2907 | if (!strcmp (setname, "std")) |
2908 | { | |
afd7eef0 | 2909 | disassembly_style = setname; |
bc90b915 FN |
2910 | current_option = i; |
2911 | for (j = 0; j < numregs; j++) | |
2912 | arm_register_names[j] = (char *) regnames[j]; | |
2913 | set_arm_regname_option (i); | |
2914 | } | |
2915 | } | |
94c30b78 | 2916 | /* Mark the end of valid options. */ |
afd7eef0 | 2917 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2918 | |
edefbb7c AC |
2919 | /* Create the help text. */ |
2920 | stb = mem_fileopen (); | |
2921 | fprintf_unfiltered (stb, "%s%s%s", | |
2922 | _("The valid values are:\n"), | |
2923 | regdesc, | |
2924 | _("The default is \"std\".")); | |
bc90b915 FN |
2925 | helptext = ui_file_xstrdup (stb, &length); |
2926 | ui_file_delete (stb); | |
ed9a39eb | 2927 | |
edefbb7c AC |
2928 | add_setshow_enum_cmd("disassembler", no_class, |
2929 | valid_disassembly_styles, &disassembly_style, | |
2930 | _("Set the disassembly style."), | |
2931 | _("Show the disassembly style."), | |
2932 | helptext, | |
2c5b56ce | 2933 | set_disassembly_style_sfunc, |
7915a72c | 2934 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 2935 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
2936 | |
2937 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2938 | _("Set usage of ARM 32-bit mode."), | |
2939 | _("Show usage of ARM 32-bit mode."), | |
2940 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 2941 | NULL, |
7915a72c | 2942 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 2943 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 2944 | |
fd50bc42 | 2945 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
2946 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
2947 | _("Set the floating point type."), | |
2948 | _("Show the floating point type."), | |
2949 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
2950 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
2951 | fpa - FPA co-processor (GCC compiled).\n\ | |
2952 | softvfp - Software FP with pure-endian doubles.\n\ | |
2953 | vfp - VFP co-processor."), | |
edefbb7c | 2954 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 2955 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 2956 | |
28e97307 DJ |
2957 | /* Add a command to allow the user to force the ABI. */ |
2958 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
2959 | _("Set the ABI."), | |
2960 | _("Show the ABI."), | |
2961 | NULL, arm_set_abi, arm_show_abi, | |
2962 | &setarmcmdlist, &showarmcmdlist); | |
2963 | ||
6529d2dd | 2964 | /* Debugging flag. */ |
edefbb7c AC |
2965 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2966 | _("Set ARM debugging."), | |
2967 | _("Show ARM debugging."), | |
2968 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 2969 | NULL, |
7915a72c | 2970 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 2971 | &setdebuglist, &showdebuglist); |
c906108c | 2972 | } |