Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
197e01b6 | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, |
25224166 MK |
4 | 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
22 | Boston, MA 02110-1301, USA. */ | |
c906108c | 23 | |
34e8f22d RE |
24 | #include <ctype.h> /* XXX for isupper () */ |
25 | ||
c906108c SS |
26 | #include "defs.h" |
27 | #include "frame.h" | |
28 | #include "inferior.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
c906108c | 31 | #include "gdb_string.h" |
afd7eef0 | 32 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 33 | #include "regcache.h" |
d16aafd8 | 34 | #include "doublest.h" |
fd0407d6 | 35 | #include "value.h" |
34e8f22d | 36 | #include "arch-utils.h" |
4be87837 | 37 | #include "osabi.h" |
eb5492fa DJ |
38 | #include "frame-unwind.h" |
39 | #include "frame-base.h" | |
40 | #include "trad-frame.h" | |
842e1f1e DJ |
41 | #include "objfiles.h" |
42 | #include "dwarf2-frame.h" | |
e4c16157 | 43 | #include "gdbtypes.h" |
29d73ae4 | 44 | #include "prologue-value.h" |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 AC |
53 | #include "gdb_assert.h" |
54 | ||
6529d2dd AC |
55 | static int arm_debug; |
56 | ||
082fc60d RE |
57 | /* Macros for setting and testing a bit in a minimal symbol that marks |
58 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 59 | is used for this purpose. |
082fc60d RE |
60 | |
61 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 62 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
63 | |
64 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
65 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
66 | | 0x80000000) | |
67 | ||
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
69 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
70 | ||
afd7eef0 RE |
71 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
72 | static struct cmd_list_element *setarmcmdlist = NULL; | |
73 | static struct cmd_list_element *showarmcmdlist = NULL; | |
74 | ||
fd50bc42 RE |
75 | /* The type of floating-point to use. Keep this in sync with enum |
76 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
77 | static const char *fp_model_strings[] = | |
78 | { | |
79 | "auto", | |
80 | "softfpa", | |
81 | "fpa", | |
82 | "softvfp", | |
28e97307 DJ |
83 | "vfp", |
84 | NULL | |
fd50bc42 RE |
85 | }; |
86 | ||
87 | /* A variable that can be configured by the user. */ | |
88 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
89 | static const char *current_fp_model = "auto"; | |
90 | ||
28e97307 DJ |
91 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
92 | static const char *arm_abi_strings[] = | |
93 | { | |
94 | "auto", | |
95 | "APCS", | |
96 | "AAPCS", | |
97 | NULL | |
98 | }; | |
99 | ||
100 | /* A variable that can be configured by the user. */ | |
101 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
102 | static const char *arm_abi_string = "auto"; | |
103 | ||
94c30b78 | 104 | /* Number of different reg name sets (options). */ |
afd7eef0 | 105 | static int num_disassembly_options; |
bc90b915 FN |
106 | |
107 | /* We have more registers than the disassembler as gdb can print the value | |
108 | of special registers as well. | |
109 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 110 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 111 | |
94c30b78 | 112 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 113 | static char * arm_register_name_strings[] = |
da59e081 JM |
114 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
115 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
116 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
117 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
118 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
119 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 120 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 121 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 122 | |
afd7eef0 RE |
123 | /* Valid register name styles. */ |
124 | static const char **valid_disassembly_styles; | |
ed9a39eb | 125 | |
afd7eef0 RE |
126 | /* Disassembly style to use. Default to "std" register names. */ |
127 | static const char *disassembly_style; | |
94c30b78 | 128 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 129 | static int current_option; |
96baa820 | 130 | |
ed9a39eb | 131 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
132 | style. */ |
133 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 134 | struct cmd_list_element *); |
afd7eef0 | 135 | static void set_disassembly_style (void); |
ed9a39eb | 136 | |
b508a996 RE |
137 | static void convert_from_extended (const struct floatformat *, const void *, |
138 | void *); | |
139 | static void convert_to_extended (const struct floatformat *, void *, | |
140 | const void *); | |
ed9a39eb | 141 | |
9b8d791a | 142 | struct arm_prologue_cache |
c3b4394c | 143 | { |
eb5492fa DJ |
144 | /* The stack pointer at the time this frame was created; i.e. the |
145 | caller's stack pointer when this function was called. It is used | |
146 | to identify this frame. */ | |
147 | CORE_ADDR prev_sp; | |
148 | ||
149 | /* The frame base for this frame is just prev_sp + frame offset - | |
150 | frame size. FRAMESIZE is the size of this stack frame, and | |
151 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
152 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
153 | ||
c3b4394c RE |
154 | int framesize; |
155 | int frameoffset; | |
eb5492fa DJ |
156 | |
157 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 158 | int framereg; |
eb5492fa DJ |
159 | |
160 | /* Saved register offsets. */ | |
161 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 162 | }; |
ed9a39eb | 163 | |
bc90b915 FN |
164 | /* Addresses for calling Thumb functions have the bit 0 set. |
165 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
166 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
167 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
168 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
169 | ||
94c30b78 | 170 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
171 | |
172 | int arm_apcs_32 = 1; | |
173 | ||
ed9a39eb JM |
174 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
175 | function. */ | |
c906108c | 176 | |
34e8f22d | 177 | int |
2a451106 | 178 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 179 | { |
c5aa993b | 180 | struct minimal_symbol *sym; |
c906108c | 181 | |
ed9a39eb | 182 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
183 | if (IS_THUMB_ADDR (memaddr)) |
184 | return 1; | |
185 | ||
ed9a39eb | 186 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
187 | sym = lookup_minimal_symbol_by_pc (memaddr); |
188 | if (sym) | |
189 | { | |
c5aa993b | 190 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
191 | } |
192 | else | |
ed9a39eb JM |
193 | { |
194 | return 0; | |
195 | } | |
c906108c SS |
196 | } |
197 | ||
181c1381 | 198 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 199 | static CORE_ADDR |
ed9a39eb | 200 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 201 | { |
a3a2ee65 JT |
202 | if (arm_apcs_32) |
203 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 204 | else |
a3a2ee65 | 205 | return (val & 0x03fffffc); |
c906108c SS |
206 | } |
207 | ||
181c1381 RE |
208 | /* When reading symbols, we need to zap the low bit of the address, |
209 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 210 | static CORE_ADDR |
181c1381 RE |
211 | arm_smash_text_address (CORE_ADDR val) |
212 | { | |
213 | return val & ~1; | |
214 | } | |
215 | ||
29d73ae4 DJ |
216 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
217 | and frame pointer. Scan until we encounter a store that could | |
218 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
219 | |
220 | static CORE_ADDR | |
29d73ae4 DJ |
221 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
222 | CORE_ADDR start, CORE_ADDR limit, | |
223 | struct arm_prologue_cache *cache) | |
c906108c | 224 | { |
29d73ae4 DJ |
225 | int i; |
226 | pv_t regs[16]; | |
227 | struct pv_area *stack; | |
228 | struct cleanup *back_to; | |
229 | CORE_ADDR offset; | |
da3c6d4a | 230 | |
29d73ae4 DJ |
231 | for (i = 0; i < 16; i++) |
232 | regs[i] = pv_register (i, 0); | |
233 | stack = make_pv_area (ARM_SP_REGNUM); | |
234 | back_to = make_cleanup_free_pv_area (stack); | |
235 | ||
236 | /* The call instruction saved PC in LR, and the current PC is not | |
237 | interesting. Due to this file's conventions, we want the value | |
238 | of LR at this function's entry, not at the call site, so we do | |
239 | not record the save of the PC - when the ARM prologue analyzer | |
240 | has also been converted to the pv mechanism, we could record the | |
241 | save here and remove the hack in prev_register. */ | |
242 | regs[ARM_PC_REGNUM] = pv_unknown (); | |
243 | ||
244 | while (start < limit) | |
c906108c | 245 | { |
29d73ae4 DJ |
246 | unsigned short insn; |
247 | ||
248 | insn = read_memory_unsigned_integer (start, 2); | |
c906108c | 249 | |
94c30b78 | 250 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 251 | { |
29d73ae4 DJ |
252 | int regno; |
253 | int mask; | |
254 | int stop = 0; | |
255 | ||
256 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
257 | whether to save LR (R14). */ | |
258 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
259 | ||
260 | /* Calculate offsets of saved R0-R7 and LR. */ | |
261 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
262 | if (mask & (1 << regno)) | |
263 | { | |
264 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
265 | { | |
266 | stop = 1; | |
267 | break; | |
268 | } | |
269 | ||
270 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
271 | -4); | |
272 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
273 | } | |
274 | ||
275 | if (stop) | |
276 | break; | |
da59e081 | 277 | } |
da3c6d4a MS |
278 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
279 | sub sp, #simm */ | |
da59e081 | 280 | { |
29d73ae4 DJ |
281 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
282 | if (insn & 0x80) /* Check for SUB. */ | |
283 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
284 | -offset); | |
da59e081 | 285 | else |
29d73ae4 DJ |
286 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
287 | offset); | |
da59e081 JM |
288 | } |
289 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
290 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
291 | (insn & 0xff) << 2); | |
292 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 293 | { |
29d73ae4 DJ |
294 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
295 | int src_reg = (insn & 0x78) >> 3; | |
296 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 297 | } |
29d73ae4 | 298 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 299 | { |
29d73ae4 DJ |
300 | /* Handle stores to the stack. Normally pushes are used, |
301 | but with GCC -mtpcs-frame, there may be other stores | |
302 | in the prologue to create the frame. */ | |
303 | int regno = (insn >> 8) & 0x7; | |
304 | pv_t addr; | |
305 | ||
306 | offset = (insn & 0xff) << 2; | |
307 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
308 | ||
309 | if (pv_area_store_would_trash (stack, addr)) | |
310 | break; | |
311 | ||
312 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 313 | } |
29d73ae4 | 314 | else |
3d74b771 | 315 | { |
29d73ae4 DJ |
316 | /* We don't know what this instruction is. We're finished |
317 | scanning. NOTE: Recognizing more safe-to-ignore | |
318 | instructions here will improve support for optimized | |
319 | code. */ | |
da3c6d4a | 320 | break; |
3d74b771 | 321 | } |
29d73ae4 DJ |
322 | |
323 | start += 2; | |
c906108c SS |
324 | } |
325 | ||
29d73ae4 DJ |
326 | if (cache == NULL) |
327 | { | |
328 | do_cleanups (back_to); | |
329 | return start; | |
330 | } | |
331 | ||
332 | /* frameoffset is unused for this unwinder. */ | |
333 | cache->frameoffset = 0; | |
334 | ||
335 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
336 | { | |
337 | /* Frame pointer is fp. Frame size is constant. */ | |
338 | cache->framereg = ARM_FP_REGNUM; | |
339 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
340 | } | |
341 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
342 | { | |
343 | /* Frame pointer is r7. Frame size is constant. */ | |
344 | cache->framereg = THUMB_FP_REGNUM; | |
345 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
346 | } | |
347 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
348 | { | |
349 | /* Try the stack pointer... this is a bit desperate. */ | |
350 | cache->framereg = ARM_SP_REGNUM; | |
351 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
352 | } | |
353 | else | |
354 | { | |
355 | /* We're just out of luck. We don't know where the frame is. */ | |
356 | cache->framereg = -1; | |
357 | cache->framesize = 0; | |
358 | } | |
359 | ||
360 | for (i = 0; i < 16; i++) | |
361 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
362 | cache->saved_regs[i].addr = offset; | |
363 | ||
364 | do_cleanups (back_to); | |
365 | return start; | |
c906108c SS |
366 | } |
367 | ||
da3c6d4a MS |
368 | /* Advance the PC across any function entry prologue instructions to |
369 | reach some "real" code. | |
34e8f22d RE |
370 | |
371 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 372 | prologue: |
c906108c | 373 | |
c5aa993b JM |
374 | mov ip, sp |
375 | [stmfd sp!, {a1,a2,a3,a4}] | |
376 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
377 | [stfe f7, [sp, #-12]!] |
378 | [stfe f6, [sp, #-12]!] | |
379 | [stfe f5, [sp, #-12]!] | |
380 | [stfe f4, [sp, #-12]!] | |
381 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 382 | |
34e8f22d | 383 | static CORE_ADDR |
ed9a39eb | 384 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
385 | { |
386 | unsigned long inst; | |
387 | CORE_ADDR skip_pc; | |
b8d5e71d | 388 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 389 | char *func_name; |
c906108c SS |
390 | struct symtab_and_line sal; |
391 | ||
848cfffb | 392 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 393 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
394 | return pc; |
395 | ||
96baa820 | 396 | /* See what the symbol table says. */ |
ed9a39eb | 397 | |
50f6fb4b | 398 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 399 | { |
50f6fb4b CV |
400 | struct symbol *sym; |
401 | ||
402 | /* Found a function. */ | |
176620f1 | 403 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
404 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
405 | { | |
94c30b78 | 406 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
407 | sal = find_pc_line (func_addr, 0); |
408 | if ((sal.line != 0) && (sal.end < func_end)) | |
409 | return sal.end; | |
410 | } | |
c906108c SS |
411 | } |
412 | ||
c906108c | 413 | /* Can't find the prologue end in the symbol table, try it the hard way |
94c30b78 | 414 | by disassembling the instructions. */ |
c906108c | 415 | |
b8d5e71d MS |
416 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
417 | if (func_end == 0 || func_end > pc + 64) | |
418 | func_end = pc + 64; | |
c906108c | 419 | |
29d73ae4 DJ |
420 | /* Check if this is Thumb code. */ |
421 | if (arm_pc_is_thumb (pc)) | |
422 | return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL); | |
423 | ||
b8d5e71d | 424 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 425 | { |
1c5bada0 | 426 | inst = read_memory_unsigned_integer (skip_pc, 4); |
f43845b3 | 427 | |
b8d5e71d MS |
428 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
429 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
430 | continue; | |
c906108c | 431 | |
28cd8767 JG |
432 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
433 | continue; | |
434 | ||
435 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
436 | continue; | |
437 | ||
b8d5e71d MS |
438 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
439 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
440 | continue; | |
c906108c | 441 | |
b8d5e71d MS |
442 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
443 | continue; | |
c906108c | 444 | |
b8d5e71d MS |
445 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
446 | continue; | |
11d3b27d | 447 | |
b8d5e71d MS |
448 | /* Any insns after this point may float into the code, if it makes |
449 | for better instruction scheduling, so we skip them only if we | |
450 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 451 | |
b8d5e71d MS |
452 | /* We may have either one sfmfd instruction here, or several stfe |
453 | insns, depending on the version of floating point code we | |
454 | support. */ | |
455 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
456 | continue; | |
457 | ||
458 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
459 | continue; | |
460 | ||
461 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
462 | continue; | |
463 | ||
464 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
465 | continue; | |
466 | ||
467 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
468 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
469 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
470 | continue; | |
471 | ||
472 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
473 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
474 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
475 | continue; | |
476 | ||
477 | /* Un-recognized instruction; stop scanning. */ | |
478 | break; | |
f43845b3 | 479 | } |
c906108c | 480 | |
b8d5e71d | 481 | return skip_pc; /* End of prologue */ |
c906108c | 482 | } |
94c30b78 | 483 | |
c5aa993b | 484 | /* *INDENT-OFF* */ |
c906108c SS |
485 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
486 | This function decodes a Thumb function prologue to determine: | |
487 | 1) the size of the stack frame | |
488 | 2) which registers are saved on it | |
489 | 3) the offsets of saved regs | |
490 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 491 | |
da59e081 JM |
492 | A typical Thumb function prologue would create this stack frame |
493 | (offsets relative to FP) | |
c906108c SS |
494 | old SP -> 24 stack parameters |
495 | 20 LR | |
496 | 16 R7 | |
497 | R7 -> 0 local variables (16 bytes) | |
498 | SP -> -12 additional stack space (12 bytes) | |
499 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
500 | 12 bytes. The frame register is R7. |
501 | ||
da3c6d4a MS |
502 | The comments for thumb_skip_prolog() describe the algorithm we use |
503 | to detect the end of the prolog. */ | |
c5aa993b JM |
504 | /* *INDENT-ON* */ |
505 | ||
c906108c | 506 | static void |
eb5492fa | 507 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
508 | { |
509 | CORE_ADDR prologue_start; | |
510 | CORE_ADDR prologue_end; | |
511 | CORE_ADDR current_pc; | |
94c30b78 | 512 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
513 | int saved_reg[16]; |
514 | /* findmask: | |
515 | bit 0 - push { rlist } | |
516 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
517 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
518 | */ | |
519 | int findmask = 0; | |
c5aa993b | 520 | int i; |
c906108c | 521 | |
eb5492fa | 522 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
523 | { |
524 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
525 | ||
94c30b78 | 526 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 527 | prologue_end = prev_pc; |
c906108c | 528 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 529 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
530 | } |
531 | else | |
f7060f85 DJ |
532 | /* We're in the boondocks: we have no idea where the start of the |
533 | function is. */ | |
534 | return; | |
c906108c | 535 | |
eb5492fa | 536 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 537 | |
29d73ae4 DJ |
538 | thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end, |
539 | cache); | |
c906108c SS |
540 | } |
541 | ||
ed9a39eb | 542 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
543 | 1) the size of the stack frame |
544 | 2) which registers are saved on it | |
545 | 3) the offsets of saved regs | |
546 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
547 | This information is stored in the "extra" fields of the frame_info. |
548 | ||
96baa820 JM |
549 | There are two basic forms for the ARM prologue. The fixed argument |
550 | function call will look like: | |
ed9a39eb JM |
551 | |
552 | mov ip, sp | |
553 | stmfd sp!, {fp, ip, lr, pc} | |
554 | sub fp, ip, #4 | |
555 | [sub sp, sp, #4] | |
96baa820 | 556 | |
c906108c | 557 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
558 | IP -> 4 (caller's stack) |
559 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
560 | -4 LR (return address in caller) | |
561 | -8 IP (copy of caller's SP) | |
562 | -12 FP (caller's FP) | |
563 | SP -> -28 Local variables | |
564 | ||
c906108c | 565 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
566 | 28 bytes. The stmfd call can also save any of the vN registers it |
567 | plans to use, which increases the frame size accordingly. | |
568 | ||
569 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
570 | because the ARM Store instructions always store PC + 8 when you read | |
571 | the PC register. | |
ed9a39eb | 572 | |
96baa820 JM |
573 | A variable argument function call will look like: |
574 | ||
ed9a39eb JM |
575 | mov ip, sp |
576 | stmfd sp!, {a1, a2, a3, a4} | |
577 | stmfd sp!, {fp, ip, lr, pc} | |
578 | sub fp, ip, #20 | |
579 | ||
96baa820 | 580 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
581 | IP -> 20 (caller's stack) |
582 | 16 A4 | |
583 | 12 A3 | |
584 | 8 A2 | |
585 | 4 A1 | |
586 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
587 | -4 LR (return address in caller) | |
588 | -8 IP (copy of caller's SP) | |
589 | -12 FP (caller's FP) | |
590 | SP -> -28 Local variables | |
96baa820 JM |
591 | |
592 | The frame size would thus be 48 bytes, and the frame offset would be | |
593 | 28 bytes. | |
594 | ||
595 | There is another potential complication, which is that the optimizer | |
596 | will try to separate the store of fp in the "stmfd" instruction from | |
597 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
598 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
599 | ||
600 | Also, note, the original version of the ARM toolchain claimed that there | |
601 | should be an | |
602 | ||
603 | instruction at the end of the prologue. I have never seen GCC produce | |
604 | this, and the ARM docs don't mention it. We still test for it below in | |
605 | case it happens... | |
ed9a39eb JM |
606 | |
607 | */ | |
c906108c SS |
608 | |
609 | static void | |
eb5492fa | 610 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 611 | { |
28cd8767 | 612 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 613 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 614 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 615 | |
c906108c | 616 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
617 | cache->framereg = ARM_SP_REGNUM; |
618 | cache->framesize = 0; | |
619 | cache->frameoffset = 0; | |
c906108c SS |
620 | |
621 | /* Check for Thumb prologue. */ | |
eb5492fa | 622 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 623 | { |
eb5492fa | 624 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
625 | return; |
626 | } | |
627 | ||
628 | /* Find the function prologue. If we can't find the function in | |
629 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 630 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 631 | { |
2a451106 KB |
632 | /* One way to find the end of the prologue (which works well |
633 | for unoptimized code) is to do the following: | |
634 | ||
635 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
636 | ||
637 | if (sal.line == 0) | |
eb5492fa | 638 | prologue_end = prev_pc; |
2a451106 KB |
639 | else if (sal.end < prologue_end) |
640 | prologue_end = sal.end; | |
641 | ||
642 | This mechanism is very accurate so long as the optimizer | |
643 | doesn't move any instructions from the function body into the | |
644 | prologue. If this happens, sal.end will be the last | |
645 | instruction in the first hunk of prologue code just before | |
646 | the first instruction that the scheduler has moved from | |
647 | the body to the prologue. | |
648 | ||
649 | In order to make sure that we scan all of the prologue | |
650 | instructions, we use a slightly less accurate mechanism which | |
651 | may scan more than necessary. To help compensate for this | |
652 | lack of accuracy, the prologue scanning loop below contains | |
653 | several clauses which'll cause the loop to terminate early if | |
654 | an implausible prologue instruction is encountered. | |
655 | ||
656 | The expression | |
657 | ||
658 | prologue_start + 64 | |
659 | ||
660 | is a suitable endpoint since it accounts for the largest | |
661 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 662 | the scheduler. */ |
2a451106 KB |
663 | |
664 | if (prologue_end > prologue_start + 64) | |
665 | { | |
94c30b78 | 666 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 667 | } |
c906108c SS |
668 | } |
669 | else | |
670 | { | |
eb5492fa DJ |
671 | /* We have no symbol information. Our only option is to assume this |
672 | function has a standard stack frame and the normal frame register. | |
673 | Then, we can find the value of our frame pointer on entrance to | |
674 | the callee (or at the present moment if this is the innermost frame). | |
675 | The value stored there should be the address of the stmfd + 8. */ | |
676 | CORE_ADDR frame_loc; | |
677 | LONGEST return_value; | |
678 | ||
679 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
680 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
681 | return; |
682 | else | |
683 | { | |
684 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 685 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 686 | } |
c906108c SS |
687 | } |
688 | ||
eb5492fa DJ |
689 | if (prev_pc < prologue_end) |
690 | prologue_end = prev_pc; | |
691 | ||
c906108c | 692 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 693 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 694 | |
96baa820 JM |
695 | Be careful, however, and if it doesn't look like a prologue, |
696 | don't try to scan it. If, for instance, a frameless function | |
697 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 698 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
699 | and other operations that rely on a knowledge of the stack |
700 | traceback. | |
701 | ||
702 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 703 | if we don't see this as the first insn, we will stop. |
c906108c | 704 | |
f43845b3 MS |
705 | [Note: This doesn't seem to be true any longer, so it's now an |
706 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 707 | |
f43845b3 MS |
708 | [Note further: The "mov ip,sp" only seems to be missing in |
709 | frameless functions at optimization level "-O2" or above, | |
710 | in which case it is often (but not always) replaced by | |
b8d5e71d | 711 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 712 | |
28cd8767 | 713 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 714 | |
94c30b78 MS |
715 | for (current_pc = prologue_start; |
716 | current_pc < prologue_end; | |
f43845b3 | 717 | current_pc += 4) |
96baa820 | 718 | { |
d4473757 KB |
719 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
720 | ||
94c30b78 | 721 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 722 | { |
28cd8767 JG |
723 | ip_offset = 0; |
724 | continue; | |
725 | } | |
726 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
727 | { | |
728 | unsigned imm = insn & 0xff; /* immediate value */ | |
729 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
730 | imm = (imm >> rot) | (imm << (32 - rot)); | |
731 | ip_offset = imm; | |
732 | continue; | |
733 | } | |
734 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
735 | { | |
736 | unsigned imm = insn & 0xff; /* immediate value */ | |
737 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
738 | imm = (imm >> rot) | (imm << (32 - rot)); | |
739 | ip_offset = -imm; | |
f43845b3 MS |
740 | continue; |
741 | } | |
94c30b78 | 742 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 743 | { |
e28a332c JG |
744 | sp_offset -= 4; |
745 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
746 | continue; |
747 | } | |
748 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
749 | /* stmfd sp!, {..., fp, ip, lr, pc} |
750 | or | |
751 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 752 | { |
d4473757 | 753 | int mask = insn & 0xffff; |
ed9a39eb | 754 | |
94c30b78 | 755 | /* Calculate offsets of saved registers. */ |
34e8f22d | 756 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
757 | if (mask & (1 << regno)) |
758 | { | |
759 | sp_offset -= 4; | |
eb5492fa | 760 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
761 | } |
762 | } | |
b8d5e71d MS |
763 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
764 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
765 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
766 | { | |
767 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
768 | continue; | |
769 | } | |
770 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
771 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
772 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
773 | { |
774 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
775 | continue; | |
776 | } | |
d4473757 KB |
777 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
778 | { | |
94c30b78 MS |
779 | unsigned imm = insn & 0xff; /* immediate value */ |
780 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 781 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 782 | fp_offset = -imm + ip_offset; |
9b8d791a | 783 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
784 | } |
785 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
786 | { | |
94c30b78 MS |
787 | unsigned imm = insn & 0xff; /* immediate value */ |
788 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
789 | imm = (imm >> rot) | (imm << (32 - rot)); |
790 | sp_offset -= imm; | |
791 | } | |
792 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
793 | { | |
794 | sp_offset -= 12; | |
34e8f22d | 795 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 796 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
797 | } |
798 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
799 | { | |
800 | int n_saved_fp_regs; | |
801 | unsigned int fp_start_reg, fp_bound_reg; | |
802 | ||
94c30b78 | 803 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 804 | { |
d4473757 KB |
805 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
806 | n_saved_fp_regs = 3; | |
807 | else | |
808 | n_saved_fp_regs = 1; | |
96baa820 | 809 | } |
d4473757 | 810 | else |
96baa820 | 811 | { |
d4473757 KB |
812 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
813 | n_saved_fp_regs = 2; | |
814 | else | |
815 | n_saved_fp_regs = 4; | |
96baa820 | 816 | } |
d4473757 | 817 | |
34e8f22d | 818 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
819 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
820 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
821 | { |
822 | sp_offset -= 12; | |
eb5492fa | 823 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 824 | } |
c906108c | 825 | } |
d4473757 | 826 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 827 | break; /* Condition not true, exit early */ |
b8d5e71d | 828 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 829 | break; /* Don't scan past a block load */ |
d4473757 KB |
830 | else |
831 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 832 | so we just skip what we don't recognize. */ |
d4473757 | 833 | continue; |
c906108c SS |
834 | } |
835 | ||
94c30b78 MS |
836 | /* The frame size is just the negative of the offset (from the |
837 | original SP) of the last thing thing we pushed on the stack. | |
838 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
839 | cache->framesize = -sp_offset; |
840 | if (cache->framereg == ARM_FP_REGNUM) | |
841 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 842 | else |
9b8d791a | 843 | cache->frameoffset = 0; |
c906108c SS |
844 | } |
845 | ||
eb5492fa DJ |
846 | static struct arm_prologue_cache * |
847 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 848 | { |
eb5492fa DJ |
849 | int reg; |
850 | struct arm_prologue_cache *cache; | |
851 | CORE_ADDR unwound_fp; | |
c5aa993b | 852 | |
35d5d4ee | 853 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
eb5492fa | 854 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
c906108c | 855 | |
eb5492fa | 856 | arm_scan_prologue (next_frame, cache); |
848cfffb | 857 | |
eb5492fa DJ |
858 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
859 | if (unwound_fp == 0) | |
860 | return cache; | |
c906108c | 861 | |
eb5492fa | 862 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 863 | |
eb5492fa DJ |
864 | /* Calculate actual addresses of saved registers using offsets |
865 | determined by arm_scan_prologue. */ | |
866 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 867 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
868 | cache->saved_regs[reg].addr += cache->prev_sp; |
869 | ||
870 | return cache; | |
c906108c SS |
871 | } |
872 | ||
eb5492fa DJ |
873 | /* Our frame ID for a normal frame is the current function's starting PC |
874 | and the caller's SP when we were called. */ | |
c906108c | 875 | |
148754e5 | 876 | static void |
eb5492fa DJ |
877 | arm_prologue_this_id (struct frame_info *next_frame, |
878 | void **this_cache, | |
879 | struct frame_id *this_id) | |
c906108c | 880 | { |
eb5492fa DJ |
881 | struct arm_prologue_cache *cache; |
882 | struct frame_id id; | |
883 | CORE_ADDR func; | |
f079148d | 884 | |
eb5492fa DJ |
885 | if (*this_cache == NULL) |
886 | *this_cache = arm_make_prologue_cache (next_frame); | |
887 | cache = *this_cache; | |
2a451106 | 888 | |
eb5492fa | 889 | func = frame_func_unwind (next_frame); |
2a451106 | 890 | |
eb5492fa DJ |
891 | /* This is meant to halt the backtrace at "_start". Make sure we |
892 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 893 | if (func <= LOWEST_PC) |
eb5492fa | 894 | return; |
5a203e44 | 895 | |
eb5492fa DJ |
896 | /* If we've hit a wall, stop. */ |
897 | if (cache->prev_sp == 0) | |
898 | return; | |
24de872b | 899 | |
eb5492fa | 900 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 901 | *this_id = id; |
c906108c SS |
902 | } |
903 | ||
eb5492fa DJ |
904 | static void |
905 | arm_prologue_prev_register (struct frame_info *next_frame, | |
906 | void **this_cache, | |
907 | int prev_regnum, | |
908 | int *optimized, | |
909 | enum lval_type *lvalp, | |
910 | CORE_ADDR *addrp, | |
911 | int *realnump, | |
9af75ef6 | 912 | gdb_byte *valuep) |
24de872b DJ |
913 | { |
914 | struct arm_prologue_cache *cache; | |
915 | ||
eb5492fa DJ |
916 | if (*this_cache == NULL) |
917 | *this_cache = arm_make_prologue_cache (next_frame); | |
918 | cache = *this_cache; | |
24de872b | 919 | |
eb5492fa DJ |
920 | /* If we are asked to unwind the PC, then we need to return the LR |
921 | instead. The saved value of PC points into this frame's | |
922 | prologue, not the next frame's resume location. */ | |
923 | if (prev_regnum == ARM_PC_REGNUM) | |
924 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 925 | |
eb5492fa DJ |
926 | /* SP is generally not saved to the stack, but this frame is |
927 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
928 | The value was already reconstructed into PREV_SP. */ | |
929 | if (prev_regnum == ARM_SP_REGNUM) | |
930 | { | |
931 | *lvalp = not_lval; | |
932 | if (valuep) | |
933 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
934 | return; | |
935 | } | |
936 | ||
1f67027d AC |
937 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
938 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
939 | } |
940 | ||
941 | struct frame_unwind arm_prologue_unwind = { | |
942 | NORMAL_FRAME, | |
943 | arm_prologue_this_id, | |
944 | arm_prologue_prev_register | |
945 | }; | |
946 | ||
947 | static const struct frame_unwind * | |
948 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
949 | { | |
950 | return &arm_prologue_unwind; | |
24de872b DJ |
951 | } |
952 | ||
909cf6ea DJ |
953 | static struct arm_prologue_cache * |
954 | arm_make_stub_cache (struct frame_info *next_frame) | |
955 | { | |
956 | int reg; | |
957 | struct arm_prologue_cache *cache; | |
958 | CORE_ADDR unwound_fp; | |
959 | ||
35d5d4ee | 960 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
909cf6ea DJ |
961 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
962 | ||
963 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
964 | ||
965 | return cache; | |
966 | } | |
967 | ||
968 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
969 | ||
970 | static void | |
971 | arm_stub_this_id (struct frame_info *next_frame, | |
972 | void **this_cache, | |
973 | struct frame_id *this_id) | |
974 | { | |
975 | struct arm_prologue_cache *cache; | |
976 | ||
977 | if (*this_cache == NULL) | |
978 | *this_cache = arm_make_stub_cache (next_frame); | |
979 | cache = *this_cache; | |
980 | ||
981 | *this_id = frame_id_build (cache->prev_sp, | |
982 | frame_pc_unwind (next_frame)); | |
983 | } | |
984 | ||
985 | struct frame_unwind arm_stub_unwind = { | |
986 | NORMAL_FRAME, | |
987 | arm_stub_this_id, | |
988 | arm_prologue_prev_register | |
989 | }; | |
990 | ||
991 | static const struct frame_unwind * | |
992 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
993 | { | |
994 | char dummy[4]; | |
995 | ||
996 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
997 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
998 | return &arm_stub_unwind; | |
999 | ||
1000 | return NULL; | |
1001 | } | |
1002 | ||
24de872b | 1003 | static CORE_ADDR |
eb5492fa | 1004 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1005 | { |
1006 | struct arm_prologue_cache *cache; | |
1007 | ||
eb5492fa DJ |
1008 | if (*this_cache == NULL) |
1009 | *this_cache = arm_make_prologue_cache (next_frame); | |
1010 | cache = *this_cache; | |
1011 | ||
1012 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1013 | } |
1014 | ||
eb5492fa DJ |
1015 | struct frame_base arm_normal_base = { |
1016 | &arm_prologue_unwind, | |
1017 | arm_normal_frame_base, | |
1018 | arm_normal_frame_base, | |
1019 | arm_normal_frame_base | |
1020 | }; | |
1021 | ||
eb5492fa DJ |
1022 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1023 | dummy frame. The frame ID's base needs to match the TOS value | |
1024 | saved by save_dummy_frame_tos() and returned from | |
1025 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1026 | breakpoint. */ | |
c906108c | 1027 | |
eb5492fa DJ |
1028 | static struct frame_id |
1029 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1030 | { |
eb5492fa DJ |
1031 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1032 | frame_pc_unwind (next_frame)); | |
1033 | } | |
c3b4394c | 1034 | |
eb5492fa DJ |
1035 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1036 | be used to construct the previous frame's ID, after looking up the | |
1037 | containing function). */ | |
c3b4394c | 1038 | |
eb5492fa DJ |
1039 | static CORE_ADDR |
1040 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1041 | { | |
1042 | CORE_ADDR pc; | |
1043 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
59ea4f70 | 1044 | return arm_addr_bits_remove (pc); |
eb5492fa DJ |
1045 | } |
1046 | ||
1047 | static CORE_ADDR | |
1048 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1049 | { | |
1050 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1051 | } |
1052 | ||
2dd604e7 RE |
1053 | /* When arguments must be pushed onto the stack, they go on in reverse |
1054 | order. The code below implements a FILO (stack) to do this. */ | |
1055 | ||
1056 | struct stack_item | |
1057 | { | |
1058 | int len; | |
1059 | struct stack_item *prev; | |
1060 | void *data; | |
1061 | }; | |
1062 | ||
1063 | static struct stack_item * | |
1064 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1065 | { | |
1066 | struct stack_item *si; | |
1067 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1068 | si->data = xmalloc (len); |
2dd604e7 RE |
1069 | si->len = len; |
1070 | si->prev = prev; | |
1071 | memcpy (si->data, contents, len); | |
1072 | return si; | |
1073 | } | |
1074 | ||
1075 | static struct stack_item * | |
1076 | pop_stack_item (struct stack_item *si) | |
1077 | { | |
1078 | struct stack_item *dead = si; | |
1079 | si = si->prev; | |
1080 | xfree (dead->data); | |
1081 | xfree (dead); | |
1082 | return si; | |
1083 | } | |
1084 | ||
2af48f68 PB |
1085 | |
1086 | /* Return the alignment (in bytes) of the given type. */ | |
1087 | ||
1088 | static int | |
1089 | arm_type_align (struct type *t) | |
1090 | { | |
1091 | int n; | |
1092 | int align; | |
1093 | int falign; | |
1094 | ||
1095 | t = check_typedef (t); | |
1096 | switch (TYPE_CODE (t)) | |
1097 | { | |
1098 | default: | |
1099 | /* Should never happen. */ | |
1100 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1101 | return 4; | |
1102 | ||
1103 | case TYPE_CODE_PTR: | |
1104 | case TYPE_CODE_ENUM: | |
1105 | case TYPE_CODE_INT: | |
1106 | case TYPE_CODE_FLT: | |
1107 | case TYPE_CODE_SET: | |
1108 | case TYPE_CODE_RANGE: | |
1109 | case TYPE_CODE_BITSTRING: | |
1110 | case TYPE_CODE_REF: | |
1111 | case TYPE_CODE_CHAR: | |
1112 | case TYPE_CODE_BOOL: | |
1113 | return TYPE_LENGTH (t); | |
1114 | ||
1115 | case TYPE_CODE_ARRAY: | |
1116 | case TYPE_CODE_COMPLEX: | |
1117 | /* TODO: What about vector types? */ | |
1118 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1119 | ||
1120 | case TYPE_CODE_STRUCT: | |
1121 | case TYPE_CODE_UNION: | |
1122 | align = 1; | |
1123 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1124 | { | |
1125 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1126 | if (falign > align) | |
1127 | align = falign; | |
1128 | } | |
1129 | return align; | |
1130 | } | |
1131 | } | |
1132 | ||
2dd604e7 RE |
1133 | /* We currently only support passing parameters in integer registers. This |
1134 | conforms with GCC's default model. Several other variants exist and | |
1135 | we should probably support some of them based on the selected ABI. */ | |
1136 | ||
1137 | static CORE_ADDR | |
7d9b040b | 1138 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1139 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1140 | struct value **args, CORE_ADDR sp, int struct_return, | |
1141 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1142 | { |
1143 | int argnum; | |
1144 | int argreg; | |
1145 | int nstack; | |
1146 | struct stack_item *si = NULL; | |
1147 | ||
6a65450a AC |
1148 | /* Set the return address. For the ARM, the return breakpoint is |
1149 | always at BP_ADDR. */ | |
2dd604e7 | 1150 | /* XXX Fix for Thumb. */ |
6a65450a | 1151 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1152 | |
1153 | /* Walk through the list of args and determine how large a temporary | |
1154 | stack is required. Need to take care here as structs may be | |
1155 | passed on the stack, and we have to to push them. */ | |
1156 | nstack = 0; | |
1157 | ||
1158 | argreg = ARM_A1_REGNUM; | |
1159 | nstack = 0; | |
1160 | ||
2dd604e7 RE |
1161 | /* The struct_return pointer occupies the first parameter |
1162 | passing register. */ | |
1163 | if (struct_return) | |
1164 | { | |
1165 | if (arm_debug) | |
1166 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1167 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1168 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1169 | argreg++; | |
1170 | } | |
1171 | ||
1172 | for (argnum = 0; argnum < nargs; argnum++) | |
1173 | { | |
1174 | int len; | |
1175 | struct type *arg_type; | |
1176 | struct type *target_type; | |
1177 | enum type_code typecode; | |
0fd88904 | 1178 | bfd_byte *val; |
2af48f68 | 1179 | int align; |
2dd604e7 | 1180 | |
df407dfe | 1181 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1182 | len = TYPE_LENGTH (arg_type); |
1183 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1184 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1185 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1186 | |
2af48f68 PB |
1187 | align = arm_type_align (arg_type); |
1188 | /* Round alignment up to a whole number of words. */ | |
1189 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1190 | /* Different ABIs have different maximum alignments. */ | |
1191 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1192 | { | |
1193 | /* The APCS ABI only requires word alignment. */ | |
1194 | align = INT_REGISTER_SIZE; | |
1195 | } | |
1196 | else | |
1197 | { | |
1198 | /* The AAPCS requires at most doubleword alignment. */ | |
1199 | if (align > INT_REGISTER_SIZE * 2) | |
1200 | align = INT_REGISTER_SIZE * 2; | |
1201 | } | |
1202 | ||
1203 | /* Push stack padding for dowubleword alignment. */ | |
1204 | if (nstack & (align - 1)) | |
1205 | { | |
1206 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1207 | nstack += INT_REGISTER_SIZE; | |
1208 | } | |
1209 | ||
1210 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1211 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1212 | && align > INT_REGISTER_SIZE | |
1213 | && argreg & 1) | |
1214 | argreg++; | |
1215 | ||
2dd604e7 RE |
1216 | /* If the argument is a pointer to a function, and it is a |
1217 | Thumb function, create a LOCAL copy of the value and set | |
1218 | the THUMB bit in it. */ | |
1219 | if (TYPE_CODE_PTR == typecode | |
1220 | && target_type != NULL | |
1221 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1222 | { | |
7c0b4a20 | 1223 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1224 | if (arm_pc_is_thumb (regval)) |
1225 | { | |
1226 | val = alloca (len); | |
fbd9dcd3 | 1227 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1228 | } |
1229 | } | |
1230 | ||
1231 | /* Copy the argument to general registers or the stack in | |
1232 | register-sized pieces. Large arguments are split between | |
1233 | registers and stack. */ | |
1234 | while (len > 0) | |
1235 | { | |
b1e29e33 | 1236 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1237 | |
1238 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1239 | { | |
1240 | /* The argument is being passed in a general purpose | |
1241 | register. */ | |
7c0b4a20 | 1242 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1243 | if (arm_debug) |
1244 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1245 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1246 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1247 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1248 | argreg++; | |
1249 | } | |
1250 | else | |
1251 | { | |
1252 | /* Push the arguments onto the stack. */ | |
1253 | if (arm_debug) | |
1254 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1255 | argnum, nstack); | |
b1e29e33 AC |
1256 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1257 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1258 | } |
1259 | ||
1260 | len -= partial_len; | |
1261 | val += partial_len; | |
1262 | } | |
1263 | } | |
1264 | /* If we have an odd number of words to push, then decrement the stack | |
1265 | by one word now, so first stack argument will be dword aligned. */ | |
1266 | if (nstack & 4) | |
1267 | sp -= 4; | |
1268 | ||
1269 | while (si) | |
1270 | { | |
1271 | sp -= si->len; | |
1272 | write_memory (sp, si->data, si->len); | |
1273 | si = pop_stack_item (si); | |
1274 | } | |
1275 | ||
1276 | /* Finally, update teh SP register. */ | |
1277 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1278 | ||
1279 | return sp; | |
1280 | } | |
1281 | ||
f53f0d0b PB |
1282 | |
1283 | /* Always align the frame to an 8-byte boundary. This is required on | |
1284 | some platforms and harmless on the rest. */ | |
1285 | ||
1286 | static CORE_ADDR | |
1287 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1288 | { | |
1289 | /* Align the stack to eight bytes. */ | |
1290 | return sp & ~ (CORE_ADDR) 7; | |
1291 | } | |
1292 | ||
c906108c | 1293 | static void |
ed9a39eb | 1294 | print_fpu_flags (int flags) |
c906108c | 1295 | { |
c5aa993b JM |
1296 | if (flags & (1 << 0)) |
1297 | fputs ("IVO ", stdout); | |
1298 | if (flags & (1 << 1)) | |
1299 | fputs ("DVZ ", stdout); | |
1300 | if (flags & (1 << 2)) | |
1301 | fputs ("OFL ", stdout); | |
1302 | if (flags & (1 << 3)) | |
1303 | fputs ("UFL ", stdout); | |
1304 | if (flags & (1 << 4)) | |
1305 | fputs ("INX ", stdout); | |
1306 | putchar ('\n'); | |
c906108c SS |
1307 | } |
1308 | ||
5e74b15c RE |
1309 | /* Print interesting information about the floating point processor |
1310 | (if present) or emulator. */ | |
34e8f22d | 1311 | static void |
d855c300 | 1312 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1313 | struct frame_info *frame, const char *args) |
c906108c | 1314 | { |
52f0bd74 | 1315 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1316 | int type; |
1317 | ||
1318 | type = (status >> 24) & 127; | |
edefbb7c AC |
1319 | if (status & (1 << 31)) |
1320 | printf (_("Hardware FPU type %d\n"), type); | |
1321 | else | |
1322 | printf (_("Software FPU type %d\n"), type); | |
1323 | /* i18n: [floating point unit] mask */ | |
1324 | fputs (_("mask: "), stdout); | |
c5aa993b | 1325 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1326 | /* i18n: [floating point unit] flags */ |
1327 | fputs (_("flags: "), stdout); | |
c5aa993b | 1328 | print_fpu_flags (status); |
c906108c SS |
1329 | } |
1330 | ||
34e8f22d RE |
1331 | /* Return the GDB type object for the "standard" data type of data in |
1332 | register N. */ | |
1333 | ||
1334 | static struct type * | |
7a5ea0d4 | 1335 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1336 | { |
34e8f22d | 1337 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1338 | { |
d7449b42 | 1339 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1340 | return builtin_type_arm_ext_big; |
1341 | else | |
1342 | return builtin_type_arm_ext_littlebyte_bigword; | |
1343 | } | |
e4c16157 DJ |
1344 | else if (regnum == ARM_SP_REGNUM) |
1345 | return builtin_type_void_data_ptr; | |
1346 | else if (regnum == ARM_PC_REGNUM) | |
1347 | return builtin_type_void_func_ptr; | |
032758dc | 1348 | else |
e4c16157 | 1349 | return builtin_type_uint32; |
032758dc AC |
1350 | } |
1351 | ||
34e8f22d RE |
1352 | /* Index within `registers' of the first byte of the space for |
1353 | register N. */ | |
1354 | ||
1355 | static int | |
1356 | arm_register_byte (int regnum) | |
1357 | { | |
1358 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1359 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1360 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1361 | return (NUM_GREGS * INT_REGISTER_SIZE |
1362 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1363 | else |
7a5ea0d4 DJ |
1364 | return (NUM_GREGS * INT_REGISTER_SIZE |
1365 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1366 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1367 | } | |
1368 | ||
26216b98 AC |
1369 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1370 | static int | |
1371 | arm_register_sim_regno (int regnum) | |
1372 | { | |
1373 | int reg = regnum; | |
1374 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1375 | ||
1376 | if (reg < NUM_GREGS) | |
1377 | return SIM_ARM_R0_REGNUM + reg; | |
1378 | reg -= NUM_GREGS; | |
1379 | ||
1380 | if (reg < NUM_FREGS) | |
1381 | return SIM_ARM_FP0_REGNUM + reg; | |
1382 | reg -= NUM_FREGS; | |
1383 | ||
1384 | if (reg < NUM_SREGS) | |
1385 | return SIM_ARM_FPS_REGNUM + reg; | |
1386 | reg -= NUM_SREGS; | |
1387 | ||
edefbb7c | 1388 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1389 | } |
34e8f22d | 1390 | |
a37b3cc0 AC |
1391 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1392 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1393 | It is thought that this is is the floating-point register format on | |
1394 | little-endian systems. */ | |
c906108c | 1395 | |
ed9a39eb | 1396 | static void |
b508a996 RE |
1397 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1398 | void *dbl) | |
c906108c | 1399 | { |
a37b3cc0 | 1400 | DOUBLEST d; |
d7449b42 | 1401 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1402 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1403 | else | |
1404 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1405 | ptr, &d); | |
b508a996 | 1406 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1407 | } |
1408 | ||
34e8f22d | 1409 | static void |
b508a996 | 1410 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1411 | { |
a37b3cc0 | 1412 | DOUBLEST d; |
b508a996 | 1413 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1414 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1415 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1416 | else | |
1417 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1418 | &d, dbl); | |
c906108c | 1419 | } |
ed9a39eb | 1420 | |
c906108c | 1421 | static int |
ed9a39eb | 1422 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1423 | { |
1424 | if (cond == INST_AL || cond == INST_NV) | |
1425 | return 1; | |
1426 | ||
1427 | switch (cond) | |
1428 | { | |
1429 | case INST_EQ: | |
1430 | return ((status_reg & FLAG_Z) != 0); | |
1431 | case INST_NE: | |
1432 | return ((status_reg & FLAG_Z) == 0); | |
1433 | case INST_CS: | |
1434 | return ((status_reg & FLAG_C) != 0); | |
1435 | case INST_CC: | |
1436 | return ((status_reg & FLAG_C) == 0); | |
1437 | case INST_MI: | |
1438 | return ((status_reg & FLAG_N) != 0); | |
1439 | case INST_PL: | |
1440 | return ((status_reg & FLAG_N) == 0); | |
1441 | case INST_VS: | |
1442 | return ((status_reg & FLAG_V) != 0); | |
1443 | case INST_VC: | |
1444 | return ((status_reg & FLAG_V) == 0); | |
1445 | case INST_HI: | |
1446 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1447 | case INST_LS: | |
1448 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1449 | case INST_GE: | |
1450 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1451 | case INST_LT: | |
1452 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1453 | case INST_GT: | |
1454 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1455 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1456 | case INST_LE: |
1457 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1458 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1459 | } |
1460 | return 1; | |
1461 | } | |
1462 | ||
9512d7fd | 1463 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1464 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1465 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1466 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1467 | #define sbits(obj,st,fn) \ | |
1468 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1469 | #define BranchDest(addr,instr) \ | |
1470 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1471 | #define ARM_PC_32 1 | |
1472 | ||
1473 | static unsigned long | |
ed9a39eb JM |
1474 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1475 | unsigned long status_reg) | |
c906108c SS |
1476 | { |
1477 | unsigned long res, shift; | |
1478 | int rm = bits (inst, 0, 3); | |
1479 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1480 | |
1481 | if (bit (inst, 4)) | |
c906108c SS |
1482 | { |
1483 | int rs = bits (inst, 8, 11); | |
1484 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1485 | } | |
1486 | else | |
1487 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1488 | |
1489 | res = (rm == 15 | |
c906108c | 1490 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1491 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1492 | : read_register (rm)); |
1493 | ||
1494 | switch (shifttype) | |
1495 | { | |
c5aa993b | 1496 | case 0: /* LSL */ |
c906108c SS |
1497 | res = shift >= 32 ? 0 : res << shift; |
1498 | break; | |
c5aa993b JM |
1499 | |
1500 | case 1: /* LSR */ | |
c906108c SS |
1501 | res = shift >= 32 ? 0 : res >> shift; |
1502 | break; | |
1503 | ||
c5aa993b JM |
1504 | case 2: /* ASR */ |
1505 | if (shift >= 32) | |
1506 | shift = 31; | |
c906108c SS |
1507 | res = ((res & 0x80000000L) |
1508 | ? ~((~res) >> shift) : res >> shift); | |
1509 | break; | |
1510 | ||
c5aa993b | 1511 | case 3: /* ROR/RRX */ |
c906108c SS |
1512 | shift &= 31; |
1513 | if (shift == 0) | |
1514 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1515 | else | |
c5aa993b | 1516 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1517 | break; |
1518 | } | |
1519 | ||
1520 | return res & 0xffffffff; | |
1521 | } | |
1522 | ||
c906108c SS |
1523 | /* Return number of 1-bits in VAL. */ |
1524 | ||
1525 | static int | |
ed9a39eb | 1526 | bitcount (unsigned long val) |
c906108c SS |
1527 | { |
1528 | int nbits; | |
1529 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1530 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1531 | return nbits; |
1532 | } | |
1533 | ||
34e8f22d | 1534 | CORE_ADDR |
ed9a39eb | 1535 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1536 | { |
c5aa993b | 1537 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
1c5bada0 | 1538 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
94c30b78 | 1539 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1540 | unsigned long offset; |
1541 | ||
1542 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1543 | { | |
1544 | CORE_ADDR sp; | |
1545 | ||
1546 | /* Fetch the saved PC from the stack. It's stored above | |
1547 | all of the other registers. */ | |
b1e29e33 | 1548 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1549 | sp = read_register (ARM_SP_REGNUM); |
1c5bada0 | 1550 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
c906108c SS |
1551 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1552 | if (nextpc == pc) | |
edefbb7c | 1553 | error (_("Infinite loop detected")); |
c906108c SS |
1554 | } |
1555 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1556 | { | |
34e8f22d | 1557 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1558 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1559 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1560 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1561 | } | |
1562 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1563 | { | |
1564 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1565 | } | |
aa17d93e | 1566 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1567 | { |
1c5bada0 | 1568 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
c5aa993b | 1569 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1570 | nextpc = pc_val + offset; |
aa17d93e DJ |
1571 | /* For BLX make sure to clear the low bits. */ |
1572 | if (bits (inst2, 11, 12) == 1) | |
1573 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1574 | } |
aa17d93e | 1575 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1576 | { |
1577 | if (bits (inst1, 3, 6) == 0x0f) | |
1578 | nextpc = pc_val; | |
1579 | else | |
1580 | nextpc = read_register (bits (inst1, 3, 6)); | |
1581 | ||
1582 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1583 | if (nextpc == pc) | |
edefbb7c | 1584 | error (_("Infinite loop detected")); |
9498281f | 1585 | } |
c906108c SS |
1586 | |
1587 | return nextpc; | |
1588 | } | |
1589 | ||
34e8f22d | 1590 | CORE_ADDR |
ed9a39eb | 1591 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1592 | { |
1593 | unsigned long pc_val; | |
1594 | unsigned long this_instr; | |
1595 | unsigned long status; | |
1596 | CORE_ADDR nextpc; | |
1597 | ||
1598 | if (arm_pc_is_thumb (pc)) | |
1599 | return thumb_get_next_pc (pc); | |
1600 | ||
1601 | pc_val = (unsigned long) pc; | |
1c5bada0 | 1602 | this_instr = read_memory_unsigned_integer (pc, 4); |
34e8f22d | 1603 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1604 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1605 | |
1606 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1607 | { | |
1608 | switch (bits (this_instr, 24, 27)) | |
1609 | { | |
c5aa993b | 1610 | case 0x0: |
94c30b78 | 1611 | case 0x1: /* data processing */ |
c5aa993b JM |
1612 | case 0x2: |
1613 | case 0x3: | |
c906108c SS |
1614 | { |
1615 | unsigned long operand1, operand2, result = 0; | |
1616 | unsigned long rn; | |
1617 | int c; | |
c5aa993b | 1618 | |
c906108c SS |
1619 | if (bits (this_instr, 12, 15) != 15) |
1620 | break; | |
1621 | ||
1622 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1623 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1624 | error (_("Invalid update to pc in instruction")); |
c906108c | 1625 | |
9498281f DJ |
1626 | /* BX <reg>, BLX <reg> */ |
1627 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1628 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1629 | { | |
1630 | rn = bits (this_instr, 0, 3); | |
1631 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1632 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1633 | ||
1634 | if (nextpc == pc) | |
edefbb7c | 1635 | error (_("Infinite loop detected")); |
9498281f DJ |
1636 | |
1637 | return nextpc; | |
1638 | } | |
1639 | ||
c906108c SS |
1640 | /* Multiply into PC */ |
1641 | c = (status & FLAG_C) ? 1 : 0; | |
1642 | rn = bits (this_instr, 16, 19); | |
1643 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1644 | |
c906108c SS |
1645 | if (bit (this_instr, 25)) |
1646 | { | |
1647 | unsigned long immval = bits (this_instr, 0, 7); | |
1648 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1649 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1650 | & 0xffffffff; | |
c906108c | 1651 | } |
c5aa993b | 1652 | else /* operand 2 is a shifted register */ |
c906108c | 1653 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1654 | |
c906108c SS |
1655 | switch (bits (this_instr, 21, 24)) |
1656 | { | |
c5aa993b | 1657 | case 0x0: /*and */ |
c906108c SS |
1658 | result = operand1 & operand2; |
1659 | break; | |
1660 | ||
c5aa993b | 1661 | case 0x1: /*eor */ |
c906108c SS |
1662 | result = operand1 ^ operand2; |
1663 | break; | |
1664 | ||
c5aa993b | 1665 | case 0x2: /*sub */ |
c906108c SS |
1666 | result = operand1 - operand2; |
1667 | break; | |
1668 | ||
c5aa993b | 1669 | case 0x3: /*rsb */ |
c906108c SS |
1670 | result = operand2 - operand1; |
1671 | break; | |
1672 | ||
c5aa993b | 1673 | case 0x4: /*add */ |
c906108c SS |
1674 | result = operand1 + operand2; |
1675 | break; | |
1676 | ||
c5aa993b | 1677 | case 0x5: /*adc */ |
c906108c SS |
1678 | result = operand1 + operand2 + c; |
1679 | break; | |
1680 | ||
c5aa993b | 1681 | case 0x6: /*sbc */ |
c906108c SS |
1682 | result = operand1 - operand2 + c; |
1683 | break; | |
1684 | ||
c5aa993b | 1685 | case 0x7: /*rsc */ |
c906108c SS |
1686 | result = operand2 - operand1 + c; |
1687 | break; | |
1688 | ||
c5aa993b JM |
1689 | case 0x8: |
1690 | case 0x9: | |
1691 | case 0xa: | |
1692 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1693 | result = (unsigned long) nextpc; |
1694 | break; | |
1695 | ||
c5aa993b | 1696 | case 0xc: /*orr */ |
c906108c SS |
1697 | result = operand1 | operand2; |
1698 | break; | |
1699 | ||
c5aa993b | 1700 | case 0xd: /*mov */ |
c906108c SS |
1701 | /* Always step into a function. */ |
1702 | result = operand2; | |
c5aa993b | 1703 | break; |
c906108c | 1704 | |
c5aa993b | 1705 | case 0xe: /*bic */ |
c906108c SS |
1706 | result = operand1 & ~operand2; |
1707 | break; | |
1708 | ||
c5aa993b | 1709 | case 0xf: /*mvn */ |
c906108c SS |
1710 | result = ~operand2; |
1711 | break; | |
1712 | } | |
1713 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1714 | ||
1715 | if (nextpc == pc) | |
edefbb7c | 1716 | error (_("Infinite loop detected")); |
c906108c SS |
1717 | break; |
1718 | } | |
c5aa993b JM |
1719 | |
1720 | case 0x4: | |
1721 | case 0x5: /* data transfer */ | |
1722 | case 0x6: | |
1723 | case 0x7: | |
c906108c SS |
1724 | if (bit (this_instr, 20)) |
1725 | { | |
1726 | /* load */ | |
1727 | if (bits (this_instr, 12, 15) == 15) | |
1728 | { | |
1729 | /* rd == pc */ | |
c5aa993b | 1730 | unsigned long rn; |
c906108c | 1731 | unsigned long base; |
c5aa993b | 1732 | |
c906108c | 1733 | if (bit (this_instr, 22)) |
edefbb7c | 1734 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1735 | |
1736 | /* byte write to PC */ | |
1737 | rn = bits (this_instr, 16, 19); | |
1738 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1739 | if (bit (this_instr, 24)) | |
1740 | { | |
1741 | /* pre-indexed */ | |
1742 | int c = (status & FLAG_C) ? 1 : 0; | |
1743 | unsigned long offset = | |
c5aa993b | 1744 | (bit (this_instr, 25) |
ed9a39eb | 1745 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1746 | : bits (this_instr, 0, 11)); |
c906108c SS |
1747 | |
1748 | if (bit (this_instr, 23)) | |
1749 | base += offset; | |
1750 | else | |
1751 | base -= offset; | |
1752 | } | |
c5aa993b | 1753 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1754 | 4); |
c5aa993b | 1755 | |
c906108c SS |
1756 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1757 | ||
1758 | if (nextpc == pc) | |
edefbb7c | 1759 | error (_("Infinite loop detected")); |
c906108c SS |
1760 | } |
1761 | } | |
1762 | break; | |
c5aa993b JM |
1763 | |
1764 | case 0x8: | |
1765 | case 0x9: /* block transfer */ | |
c906108c SS |
1766 | if (bit (this_instr, 20)) |
1767 | { | |
1768 | /* LDM */ | |
1769 | if (bit (this_instr, 15)) | |
1770 | { | |
1771 | /* loading pc */ | |
1772 | int offset = 0; | |
1773 | ||
1774 | if (bit (this_instr, 23)) | |
1775 | { | |
1776 | /* up */ | |
1777 | unsigned long reglist = bits (this_instr, 0, 14); | |
1778 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1779 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1780 | offset += 4; |
1781 | } | |
1782 | else if (bit (this_instr, 24)) | |
1783 | offset = -4; | |
c5aa993b | 1784 | |
c906108c | 1785 | { |
c5aa993b JM |
1786 | unsigned long rn_val = |
1787 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1788 | nextpc = |
1789 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1790 | + offset), |
c906108c SS |
1791 | 4); |
1792 | } | |
1793 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1794 | if (nextpc == pc) | |
edefbb7c | 1795 | error (_("Infinite loop detected")); |
c906108c SS |
1796 | } |
1797 | } | |
1798 | break; | |
c5aa993b JM |
1799 | |
1800 | case 0xb: /* branch & link */ | |
1801 | case 0xa: /* branch */ | |
c906108c SS |
1802 | { |
1803 | nextpc = BranchDest (pc, this_instr); | |
1804 | ||
9498281f DJ |
1805 | /* BLX */ |
1806 | if (bits (this_instr, 28, 31) == INST_NV) | |
1807 | nextpc |= bit (this_instr, 24) << 1; | |
1808 | ||
c906108c SS |
1809 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1810 | if (nextpc == pc) | |
edefbb7c | 1811 | error (_("Infinite loop detected")); |
c906108c SS |
1812 | break; |
1813 | } | |
c5aa993b JM |
1814 | |
1815 | case 0xc: | |
1816 | case 0xd: | |
1817 | case 0xe: /* coproc ops */ | |
1818 | case 0xf: /* SWI */ | |
c906108c SS |
1819 | break; |
1820 | ||
1821 | default: | |
edefbb7c | 1822 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1823 | return (pc); |
1824 | } | |
1825 | } | |
1826 | ||
1827 | return nextpc; | |
1828 | } | |
1829 | ||
9512d7fd FN |
1830 | /* single_step() is called just before we want to resume the inferior, |
1831 | if we want to single-step it but there is no hardware or kernel | |
1832 | single-step support. We find the target of the coming instruction | |
1833 | and breakpoint it. | |
1834 | ||
94c30b78 MS |
1835 | single_step() is also called just after the inferior stops. If we |
1836 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1837 | |
34e8f22d RE |
1838 | static void |
1839 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1840 | { |
8181d85f DJ |
1841 | /* NOTE: This may insert the wrong breakpoint instruction when |
1842 | single-stepping over a mode-changing instruction, if the | |
1843 | CPSR heuristics are used. */ | |
9512d7fd FN |
1844 | |
1845 | if (insert_bpt) | |
1846 | { | |
8181d85f DJ |
1847 | CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
1848 | ||
1849 | insert_single_step_breakpoint (next_pc); | |
9512d7fd FN |
1850 | } |
1851 | else | |
8181d85f | 1852 | remove_single_step_breakpoints (); |
9512d7fd | 1853 | } |
9512d7fd | 1854 | |
c906108c SS |
1855 | #include "bfd-in2.h" |
1856 | #include "libcoff.h" | |
1857 | ||
1858 | static int | |
ed9a39eb | 1859 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1860 | { |
1861 | if (arm_pc_is_thumb (memaddr)) | |
1862 | { | |
c5aa993b JM |
1863 | static asymbol *asym; |
1864 | static combined_entry_type ce; | |
1865 | static struct coff_symbol_struct csym; | |
27cddce2 | 1866 | static struct bfd fake_bfd; |
c5aa993b | 1867 | static bfd_target fake_target; |
c906108c SS |
1868 | |
1869 | if (csym.native == NULL) | |
1870 | { | |
da3c6d4a MS |
1871 | /* Create a fake symbol vector containing a Thumb symbol. |
1872 | This is solely so that the code in print_insn_little_arm() | |
1873 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1874 | the presence of a Thumb symbol and switch to decoding | |
1875 | Thumb instructions. */ | |
c5aa993b JM |
1876 | |
1877 | fake_target.flavour = bfd_target_coff_flavour; | |
1878 | fake_bfd.xvec = &fake_target; | |
c906108c | 1879 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1880 | csym.native = &ce; |
1881 | csym.symbol.the_bfd = &fake_bfd; | |
1882 | csym.symbol.name = "fake"; | |
1883 | asym = (asymbol *) & csym; | |
c906108c | 1884 | } |
c5aa993b | 1885 | |
c906108c | 1886 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1887 | info->symbols = &asym; |
c906108c SS |
1888 | } |
1889 | else | |
1890 | info->symbols = NULL; | |
c5aa993b | 1891 | |
d7449b42 | 1892 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1893 | return print_insn_big_arm (memaddr, info); |
1894 | else | |
1895 | return print_insn_little_arm (memaddr, info); | |
1896 | } | |
1897 | ||
66e810cd RE |
1898 | /* The following define instruction sequences that will cause ARM |
1899 | cpu's to take an undefined instruction trap. These are used to | |
1900 | signal a breakpoint to GDB. | |
1901 | ||
1902 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1903 | modes. A different instruction is required for each mode. The ARM | |
1904 | cpu's can also be big or little endian. Thus four different | |
1905 | instructions are needed to support all cases. | |
1906 | ||
1907 | Note: ARMv4 defines several new instructions that will take the | |
1908 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1909 | not in fact add the new instructions. The new undefined | |
1910 | instructions in ARMv4 are all instructions that had no defined | |
1911 | behaviour in earlier chips. There is no guarantee that they will | |
1912 | raise an exception, but may be treated as NOP's. In practice, it | |
1913 | may only safe to rely on instructions matching: | |
1914 | ||
1915 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1916 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1917 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1918 | ||
1919 | Even this may only true if the condition predicate is true. The | |
1920 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1921 | ||
1922 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1923 | and NetBSD all use a software interrupt rather than an undefined | |
1924 | instruction to force a trap. This can be handled by by the | |
1925 | abi-specific code during establishment of the gdbarch vector. */ | |
1926 | ||
1927 | ||
d7b486e7 RE |
1928 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1929 | override these definitions. */ | |
66e810cd RE |
1930 | #ifndef ARM_LE_BREAKPOINT |
1931 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1932 | #endif | |
1933 | #ifndef ARM_BE_BREAKPOINT | |
1934 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1935 | #endif | |
1936 | #ifndef THUMB_LE_BREAKPOINT | |
1937 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1938 | #endif | |
1939 | #ifndef THUMB_BE_BREAKPOINT | |
1940 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1941 | #endif | |
1942 | ||
1943 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1944 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1945 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1946 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1947 | ||
34e8f22d RE |
1948 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1949 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1950 | breakpoint should be used. It returns a pointer to a string of |
1951 | bytes that encode a breakpoint instruction, stores the length of | |
1952 | the string to *lenptr, and adjusts the program counter (if | |
1953 | necessary) to point to the actual memory location where the | |
c906108c SS |
1954 | breakpoint should be inserted. */ |
1955 | ||
ab89facf | 1956 | static const unsigned char * |
ed9a39eb | 1957 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1958 | { |
66e810cd RE |
1959 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1960 | ||
4bf7064c | 1961 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 1962 | { |
66e810cd RE |
1963 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1964 | *lenptr = tdep->thumb_breakpoint_size; | |
1965 | return tdep->thumb_breakpoint; | |
c906108c SS |
1966 | } |
1967 | else | |
1968 | { | |
66e810cd RE |
1969 | *lenptr = tdep->arm_breakpoint_size; |
1970 | return tdep->arm_breakpoint; | |
c906108c SS |
1971 | } |
1972 | } | |
ed9a39eb JM |
1973 | |
1974 | /* Extract from an array REGBUF containing the (raw) register state a | |
1975 | function return value of type TYPE, and copy that, in virtual | |
1976 | format, into VALBUF. */ | |
1977 | ||
34e8f22d | 1978 | static void |
5238cf52 MK |
1979 | arm_extract_return_value (struct type *type, struct regcache *regs, |
1980 | gdb_byte *valbuf) | |
ed9a39eb JM |
1981 | { |
1982 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 | 1983 | { |
28e97307 | 1984 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
1985 | { |
1986 | case ARM_FLOAT_FPA: | |
b508a996 RE |
1987 | { |
1988 | /* The value is in register F0 in internal format. We need to | |
1989 | extract the raw value and then convert it to the desired | |
1990 | internal type. */ | |
7a5ea0d4 | 1991 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
1992 | |
1993 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
1994 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
1995 | valbuf); | |
1996 | } | |
08216dd7 RE |
1997 | break; |
1998 | ||
fd50bc42 | 1999 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2000 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2001 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2002 | if (TYPE_LENGTH (type) > 4) | |
2003 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2004 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2005 | break; |
2006 | ||
2007 | default: | |
2008 | internal_error | |
2009 | (__FILE__, __LINE__, | |
edefbb7c | 2010 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2011 | break; |
2012 | } | |
2013 | } | |
b508a996 RE |
2014 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2015 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2016 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2017 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2018 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2019 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2020 | { | |
2021 | /* If the the type is a plain integer, then the access is | |
2022 | straight-forward. Otherwise we have to play around a bit more. */ | |
2023 | int len = TYPE_LENGTH (type); | |
2024 | int regno = ARM_A1_REGNUM; | |
2025 | ULONGEST tmp; | |
2026 | ||
2027 | while (len > 0) | |
2028 | { | |
2029 | /* By using store_unsigned_integer we avoid having to do | |
2030 | anything special for small big-endian values. */ | |
2031 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2032 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2033 | (len > INT_REGISTER_SIZE |
2034 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2035 | tmp); |
7a5ea0d4 DJ |
2036 | len -= INT_REGISTER_SIZE; |
2037 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2038 | } |
2039 | } | |
ed9a39eb | 2040 | else |
b508a996 RE |
2041 | { |
2042 | /* For a structure or union the behaviour is as if the value had | |
2043 | been stored to word-aligned memory and then loaded into | |
2044 | registers with 32-bit load instruction(s). */ | |
2045 | int len = TYPE_LENGTH (type); | |
2046 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2047 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2048 | |
2049 | while (len > 0) | |
2050 | { | |
2051 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2052 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2053 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2054 | len -= INT_REGISTER_SIZE; | |
2055 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2056 | } |
2057 | } | |
34e8f22d RE |
2058 | } |
2059 | ||
67255d04 RE |
2060 | |
2061 | /* Will a function return an aggregate type in memory or in a | |
2062 | register? Return 0 if an aggregate type can be returned in a | |
2063 | register, 1 if it must be returned in memory. */ | |
2064 | ||
2065 | static int | |
2af48f68 | 2066 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2067 | { |
2068 | int nRc; | |
52f0bd74 | 2069 | enum type_code code; |
67255d04 | 2070 | |
44e1a9eb DJ |
2071 | CHECK_TYPEDEF (type); |
2072 | ||
67255d04 RE |
2073 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2074 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2075 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2076 | offset of each addressable subfield must be zero. Note that bit | |
2077 | fields are not addressable, and all addressable subfields of | |
2078 | unions always start at offset zero. | |
67255d04 RE |
2079 | |
2080 | This function is based on the behaviour of GCC 2.95.1. | |
2081 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2082 | ||
2083 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2084 | parameters correctly for a function returning the following | |
2085 | structure: struct { float f;}; This should be returned in memory, | |
2086 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2087 | know of any way to detect if a function like the above has been | |
2088 | compiled with the correct calling convention. */ | |
2089 | ||
2090 | /* All aggregate types that won't fit in a register must be returned | |
2091 | in memory. */ | |
b1e29e33 | 2092 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2093 | { |
2094 | return 1; | |
2095 | } | |
2096 | ||
2af48f68 PB |
2097 | /* The AAPCS says all aggregates not larger than a word are returned |
2098 | in a register. */ | |
2099 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2100 | return 0; | |
2101 | ||
67255d04 RE |
2102 | /* The only aggregate types that can be returned in a register are |
2103 | structs and unions. Arrays must be returned in memory. */ | |
2104 | code = TYPE_CODE (type); | |
2105 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2106 | { | |
2107 | return 1; | |
2108 | } | |
2109 | ||
2110 | /* Assume all other aggregate types can be returned in a register. | |
2111 | Run a check for structures, unions and arrays. */ | |
2112 | nRc = 0; | |
2113 | ||
2114 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2115 | { | |
2116 | int i; | |
2117 | /* Need to check if this struct/union is "integer" like. For | |
2118 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2119 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2120 | subfield must be zero. Note that bit fields are not | |
2121 | addressable, and unions always start at offset zero. If any | |
2122 | of the subfields is a floating point type, the struct/union | |
2123 | cannot be an integer type. */ | |
67255d04 RE |
2124 | |
2125 | /* For each field in the object, check: | |
2126 | 1) Is it FP? --> yes, nRc = 1; | |
2127 | 2) Is it addressable (bitpos != 0) and | |
2128 | not packed (bitsize == 0)? | |
2129 | --> yes, nRc = 1 | |
2130 | */ | |
2131 | ||
2132 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2133 | { | |
2134 | enum type_code field_type_code; | |
44e1a9eb | 2135 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2136 | |
2137 | /* Is it a floating point type field? */ | |
2138 | if (field_type_code == TYPE_CODE_FLT) | |
2139 | { | |
2140 | nRc = 1; | |
2141 | break; | |
2142 | } | |
2143 | ||
2144 | /* If bitpos != 0, then we have to care about it. */ | |
2145 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2146 | { | |
2147 | /* Bitfields are not addressable. If the field bitsize is | |
2148 | zero, then the field is not packed. Hence it cannot be | |
2149 | a bitfield or any other packed type. */ | |
2150 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2151 | { | |
2152 | nRc = 1; | |
2153 | break; | |
2154 | } | |
2155 | } | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | return nRc; | |
2160 | } | |
2161 | ||
34e8f22d RE |
2162 | /* Write into appropriate registers a function return value of type |
2163 | TYPE, given in virtual format. */ | |
2164 | ||
2165 | static void | |
b508a996 | 2166 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2167 | const gdb_byte *valbuf) |
34e8f22d RE |
2168 | { |
2169 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2170 | { | |
7a5ea0d4 | 2171 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2172 | |
28e97307 | 2173 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2174 | { |
2175 | case ARM_FLOAT_FPA: | |
2176 | ||
b508a996 RE |
2177 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2178 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2179 | break; |
2180 | ||
fd50bc42 | 2181 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2182 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2183 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2184 | if (TYPE_LENGTH (type) > 4) | |
2185 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2186 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2187 | break; |
2188 | ||
2189 | default: | |
2190 | internal_error | |
2191 | (__FILE__, __LINE__, | |
edefbb7c | 2192 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2193 | break; |
2194 | } | |
34e8f22d | 2195 | } |
b508a996 RE |
2196 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2197 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2198 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2199 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2200 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2201 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2202 | { | |
2203 | if (TYPE_LENGTH (type) <= 4) | |
2204 | { | |
2205 | /* Values of one word or less are zero/sign-extended and | |
2206 | returned in r0. */ | |
7a5ea0d4 | 2207 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2208 | LONGEST val = unpack_long (type, valbuf); |
2209 | ||
7a5ea0d4 | 2210 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2211 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2212 | } | |
2213 | else | |
2214 | { | |
2215 | /* Integral values greater than one word are stored in consecutive | |
2216 | registers starting with r0. This will always be a multiple of | |
2217 | the regiser size. */ | |
2218 | int len = TYPE_LENGTH (type); | |
2219 | int regno = ARM_A1_REGNUM; | |
2220 | ||
2221 | while (len > 0) | |
2222 | { | |
2223 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2224 | len -= INT_REGISTER_SIZE; |
2225 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2226 | } |
2227 | } | |
2228 | } | |
34e8f22d | 2229 | else |
b508a996 RE |
2230 | { |
2231 | /* For a structure or union the behaviour is as if the value had | |
2232 | been stored to word-aligned memory and then loaded into | |
2233 | registers with 32-bit load instruction(s). */ | |
2234 | int len = TYPE_LENGTH (type); | |
2235 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2236 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2237 | |
2238 | while (len > 0) | |
2239 | { | |
2240 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2241 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2242 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2243 | len -= INT_REGISTER_SIZE; |
2244 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2245 | } |
2246 | } | |
34e8f22d RE |
2247 | } |
2248 | ||
2af48f68 PB |
2249 | |
2250 | /* Handle function return values. */ | |
2251 | ||
2252 | static enum return_value_convention | |
2253 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
25224166 MK |
2254 | struct regcache *regcache, gdb_byte *readbuf, |
2255 | const gdb_byte *writebuf) | |
2af48f68 | 2256 | { |
7c00367c MK |
2257 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2258 | ||
2af48f68 PB |
2259 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
2260 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2261 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2262 | { | |
7c00367c MK |
2263 | if (tdep->struct_return == pcc_struct_return |
2264 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
2265 | return RETURN_VALUE_STRUCT_CONVENTION; |
2266 | } | |
2267 | ||
2268 | if (writebuf) | |
2269 | arm_store_return_value (valtype, regcache, writebuf); | |
2270 | ||
2271 | if (readbuf) | |
2272 | arm_extract_return_value (valtype, regcache, readbuf); | |
2273 | ||
2274 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2275 | } | |
2276 | ||
2277 | ||
9df628e0 RE |
2278 | static int |
2279 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2280 | { | |
2281 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2282 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2283 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2284 | ||
2285 | jb_addr = read_register (ARM_A1_REGNUM); | |
2286 | ||
2287 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2288 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2289 | return 0; |
2290 | ||
7a5ea0d4 | 2291 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2292 | return 1; |
2293 | } | |
2294 | ||
ed9a39eb | 2295 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2296 | |
2297 | int | |
ed9a39eb | 2298 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2299 | { |
2300 | CORE_ADDR start_addr; | |
2301 | ||
ed9a39eb JM |
2302 | /* Find the starting address of the function containing the PC. If |
2303 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2304 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2305 | &start_addr, NULL)) | |
c906108c SS |
2306 | return 0; |
2307 | ||
2308 | return strncmp (name, "_call_via_r", 11) == 0; | |
2309 | } | |
2310 | ||
ed9a39eb JM |
2311 | /* If PC is in a Thumb call or return stub, return the address of the |
2312 | target PC, which is in a register. The thunk functions are called | |
2313 | _called_via_xx, where x is the register name. The possible names | |
2314 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2315 | |
2316 | CORE_ADDR | |
ed9a39eb | 2317 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2318 | { |
c5aa993b | 2319 | char *name; |
c906108c SS |
2320 | CORE_ADDR start_addr; |
2321 | ||
2322 | /* Find the starting address and name of the function containing the PC. */ | |
2323 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2324 | return 0; | |
2325 | ||
2326 | /* Call thunks always start with "_call_via_". */ | |
2327 | if (strncmp (name, "_call_via_", 10) == 0) | |
2328 | { | |
ed9a39eb JM |
2329 | /* Use the name suffix to determine which register contains the |
2330 | target PC. */ | |
c5aa993b JM |
2331 | static char *table[15] = |
2332 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2333 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2334 | }; | |
c906108c SS |
2335 | int regno; |
2336 | ||
2337 | for (regno = 0; regno <= 14; regno++) | |
2338 | if (strcmp (&name[10], table[regno]) == 0) | |
2339 | return read_register (regno); | |
2340 | } | |
ed9a39eb | 2341 | |
c5aa993b | 2342 | return 0; /* not a stub */ |
c906108c SS |
2343 | } |
2344 | ||
afd7eef0 RE |
2345 | static void |
2346 | set_arm_command (char *args, int from_tty) | |
2347 | { | |
edefbb7c AC |
2348 | printf_unfiltered (_("\ |
2349 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2350 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2351 | } | |
2352 | ||
2353 | static void | |
2354 | show_arm_command (char *args, int from_tty) | |
2355 | { | |
26304000 | 2356 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2357 | } |
2358 | ||
28e97307 DJ |
2359 | static void |
2360 | arm_update_current_architecture (void) | |
fd50bc42 | 2361 | { |
28e97307 | 2362 | struct gdbarch_info info; |
fd50bc42 | 2363 | |
28e97307 DJ |
2364 | /* If the current architecture is not ARM, we have nothing to do. */ |
2365 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2366 | return; | |
fd50bc42 | 2367 | |
28e97307 DJ |
2368 | /* Update the architecture. */ |
2369 | gdbarch_info_init (&info); | |
fd50bc42 | 2370 | |
28e97307 DJ |
2371 | if (!gdbarch_update_p (info)) |
2372 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2373 | } |
2374 | ||
2375 | static void | |
2376 | set_fp_model_sfunc (char *args, int from_tty, | |
2377 | struct cmd_list_element *c) | |
2378 | { | |
2379 | enum arm_float_model fp_model; | |
2380 | ||
2381 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2382 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2383 | { | |
2384 | arm_fp_model = fp_model; | |
2385 | break; | |
2386 | } | |
2387 | ||
2388 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2389 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2390 | current_fp_model); |
2391 | ||
28e97307 | 2392 | arm_update_current_architecture (); |
fd50bc42 RE |
2393 | } |
2394 | ||
2395 | static void | |
08546159 AC |
2396 | show_fp_model (struct ui_file *file, int from_tty, |
2397 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2398 | { |
2399 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2400 | ||
28e97307 | 2401 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2402 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2403 | fprintf_filtered (file, _("\ |
2404 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2405 | fp_model_strings[tdep->fp_model]); | |
2406 | else | |
2407 | fprintf_filtered (file, _("\ | |
2408 | The current ARM floating point model is \"%s\".\n"), | |
2409 | fp_model_strings[arm_fp_model]); | |
2410 | } | |
2411 | ||
2412 | static void | |
2413 | arm_set_abi (char *args, int from_tty, | |
2414 | struct cmd_list_element *c) | |
2415 | { | |
2416 | enum arm_abi_kind arm_abi; | |
2417 | ||
2418 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2419 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2420 | { | |
2421 | arm_abi_global = arm_abi; | |
2422 | break; | |
2423 | } | |
2424 | ||
2425 | if (arm_abi == ARM_ABI_LAST) | |
2426 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2427 | arm_abi_string); | |
2428 | ||
2429 | arm_update_current_architecture (); | |
2430 | } | |
2431 | ||
2432 | static void | |
2433 | arm_show_abi (struct ui_file *file, int from_tty, | |
2434 | struct cmd_list_element *c, const char *value) | |
2435 | { | |
2436 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2437 | ||
2438 | if (arm_abi_global == ARM_ABI_AUTO | |
2439 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2440 | fprintf_filtered (file, _("\ | |
2441 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2442 | arm_abi_strings[tdep->arm_abi]); | |
2443 | else | |
2444 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2445 | arm_abi_string); | |
fd50bc42 RE |
2446 | } |
2447 | ||
afd7eef0 RE |
2448 | /* If the user changes the register disassembly style used for info |
2449 | register and other commands, we have to also switch the style used | |
2450 | in opcodes for disassembly output. This function is run in the "set | |
2451 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2452 | |
2453 | static void | |
afd7eef0 | 2454 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2455 | struct cmd_list_element *c) |
2456 | { | |
afd7eef0 | 2457 | set_disassembly_style (); |
bc90b915 FN |
2458 | } |
2459 | \f | |
966fbf70 | 2460 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2461 | static const char * |
34e8f22d | 2462 | arm_register_name (int i) |
966fbf70 RE |
2463 | { |
2464 | return arm_register_names[i]; | |
2465 | } | |
2466 | ||
bc90b915 | 2467 | static void |
afd7eef0 | 2468 | set_disassembly_style (void) |
bc90b915 | 2469 | { |
4bd7b427 | 2470 | const char *setname, *setdesc, *const *regnames; |
bc90b915 FN |
2471 | int numregs, j; |
2472 | ||
afd7eef0 | 2473 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2474 | int current = 0; |
2475 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2476 | while ((disassembly_style != setname) |
2477 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2478 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2479 | current_option = current; | |
2480 | ||
94c30b78 | 2481 | /* Fill our copy. */ |
bc90b915 FN |
2482 | for (j = 0; j < numregs; j++) |
2483 | arm_register_names[j] = (char *) regnames[j]; | |
2484 | ||
94c30b78 | 2485 | /* Adjust case. */ |
34e8f22d | 2486 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2487 | { |
34e8f22d RE |
2488 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2489 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2490 | } |
2491 | else | |
2492 | { | |
34e8f22d RE |
2493 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2494 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2495 | } |
2496 | ||
94c30b78 | 2497 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2498 | set_arm_regname_option (current); |
2499 | } | |
2500 | ||
082fc60d RE |
2501 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2502 | function. */ | |
2503 | ||
2504 | static int | |
2505 | coff_sym_is_thumb (int val) | |
2506 | { | |
2507 | return (val == C_THUMBEXT || | |
2508 | val == C_THUMBSTAT || | |
2509 | val == C_THUMBEXTFUNC || | |
2510 | val == C_THUMBSTATFUNC || | |
2511 | val == C_THUMBLABEL); | |
2512 | } | |
2513 | ||
2514 | /* arm_coff_make_msymbol_special() | |
2515 | arm_elf_make_msymbol_special() | |
2516 | ||
2517 | These functions test whether the COFF or ELF symbol corresponds to | |
2518 | an address in thumb code, and set a "special" bit in a minimal | |
2519 | symbol to indicate that it does. */ | |
2520 | ||
34e8f22d | 2521 | static void |
082fc60d RE |
2522 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2523 | { | |
2524 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2525 | STT_ARM_TFUNC). */ | |
2526 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2527 | == STT_LOPROC) | |
2528 | MSYMBOL_SET_SPECIAL (msym); | |
2529 | } | |
2530 | ||
34e8f22d | 2531 | static void |
082fc60d RE |
2532 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2533 | { | |
2534 | if (coff_sym_is_thumb (val)) | |
2535 | MSYMBOL_SET_SPECIAL (msym); | |
2536 | } | |
2537 | ||
756fe439 DJ |
2538 | static void |
2539 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2540 | { | |
2541 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2542 | ||
2543 | /* If necessary, set the T bit. */ | |
2544 | if (arm_apcs_32) | |
2545 | { | |
2546 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2547 | if (arm_pc_is_thumb (pc)) | |
2548 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2549 | else | |
2550 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2551 | } | |
2552 | } | |
97e03143 | 2553 | \f |
70f80edf JT |
2554 | static enum gdb_osabi |
2555 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2556 | { |
2af48f68 | 2557 | unsigned int elfosabi; |
70f80edf | 2558 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2559 | |
70f80edf | 2560 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2561 | |
28e97307 DJ |
2562 | if (elfosabi == ELFOSABI_ARM) |
2563 | /* GNU tools use this value. Check note sections in this case, | |
2564 | as well. */ | |
2565 | bfd_map_over_sections (abfd, | |
2566 | generic_elf_osabi_sniff_abi_tag_sections, | |
2567 | &osabi); | |
97e03143 | 2568 | |
28e97307 | 2569 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2570 | return osabi; |
97e03143 RE |
2571 | } |
2572 | ||
70f80edf | 2573 | \f |
da3c6d4a MS |
2574 | /* Initialize the current architecture based on INFO. If possible, |
2575 | re-use an architecture from ARCHES, which is a list of | |
2576 | architectures already created during this debugging session. | |
97e03143 | 2577 | |
da3c6d4a MS |
2578 | Called e.g. at program startup, when reading a core file, and when |
2579 | reading a binary file. */ | |
97e03143 | 2580 | |
39bbf761 RE |
2581 | static struct gdbarch * |
2582 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2583 | { | |
97e03143 | 2584 | struct gdbarch_tdep *tdep; |
39bbf761 | 2585 | struct gdbarch *gdbarch; |
28e97307 DJ |
2586 | struct gdbarch_list *best_arch; |
2587 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2588 | enum arm_float_model fp_model = arm_fp_model; | |
39bbf761 | 2589 | |
28e97307 DJ |
2590 | /* If we have an object to base this architecture on, try to determine |
2591 | its ABI. */ | |
39bbf761 | 2592 | |
28e97307 | 2593 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2594 | { |
6b26d61a | 2595 | int ei_osabi, e_flags; |
28e97307 | 2596 | |
4be87837 | 2597 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2598 | { |
4be87837 DJ |
2599 | case bfd_target_aout_flavour: |
2600 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2601 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2602 | break; |
97e03143 | 2603 | |
4be87837 DJ |
2604 | case bfd_target_coff_flavour: |
2605 | /* Assume it's an old APCS-style ABI. */ | |
2606 | /* XXX WinCE? */ | |
28e97307 DJ |
2607 | arm_abi = ARM_ABI_APCS; |
2608 | break; | |
2609 | ||
2610 | case bfd_target_elf_flavour: | |
2611 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
2612 | e_flags = elf_elfheader (info.abfd)->e_flags; |
2613 | ||
28e97307 DJ |
2614 | if (ei_osabi == ELFOSABI_ARM) |
2615 | { | |
2616 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
2617 | objects. There's nowhere to tag an EABI version |
2618 | anyway, so assume APCS. */ | |
28e97307 DJ |
2619 | arm_abi = ARM_ABI_APCS; |
2620 | } | |
2621 | else if (ei_osabi == ELFOSABI_NONE) | |
2622 | { | |
6b26d61a | 2623 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
2624 | |
2625 | switch (eabi_ver) | |
2626 | { | |
2627 | case EF_ARM_EABI_UNKNOWN: | |
2628 | /* Assume GNU tools. */ | |
2629 | arm_abi = ARM_ABI_APCS; | |
2630 | break; | |
2631 | ||
2632 | case EF_ARM_EABI_VER4: | |
625b5003 | 2633 | case EF_ARM_EABI_VER5: |
28e97307 | 2634 | arm_abi = ARM_ABI_AAPCS; |
2af48f68 PB |
2635 | /* EABI binaries default to VFP float ordering. */ |
2636 | if (fp_model == ARM_FLOAT_AUTO) | |
2637 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2638 | break; |
2639 | ||
2640 | default: | |
6b26d61a | 2641 | /* Leave it as "auto". */ |
28e97307 | 2642 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
2643 | break; |
2644 | } | |
2645 | } | |
2646 | ||
2647 | if (fp_model == ARM_FLOAT_AUTO) | |
2648 | { | |
2649 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2650 | ||
2651 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
2652 | { | |
2653 | case 0: | |
2654 | /* Leave it as "auto". Strictly speaking this case | |
2655 | means FPA, but almost nobody uses that now, and | |
2656 | many toolchains fail to set the appropriate bits | |
2657 | for the floating-point model they use. */ | |
2658 | break; | |
2659 | case EF_ARM_SOFT_FLOAT: | |
2660 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2661 | break; | |
2662 | case EF_ARM_VFP_FLOAT: | |
2663 | fp_model = ARM_FLOAT_VFP; | |
2664 | break; | |
2665 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
2666 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2667 | break; |
2668 | } | |
2669 | } | |
4be87837 | 2670 | break; |
97e03143 | 2671 | |
4be87837 | 2672 | default: |
28e97307 | 2673 | /* Leave it as "auto". */ |
50ceaba5 | 2674 | break; |
97e03143 RE |
2675 | } |
2676 | } | |
2677 | ||
28e97307 DJ |
2678 | /* Now that we have inferred any architecture settings that we |
2679 | can, try to inherit from the last ARM ABI. */ | |
4be87837 | 2680 | if (arches != NULL) |
28e97307 DJ |
2681 | { |
2682 | if (arm_abi == ARM_ABI_AUTO) | |
2683 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; | |
2684 | ||
2685 | if (fp_model == ARM_FLOAT_AUTO) | |
2686 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; | |
2687 | } | |
2688 | else | |
2689 | { | |
2690 | /* There was no prior ARM architecture; fill in default values. */ | |
2691 | ||
2692 | if (arm_abi == ARM_ABI_AUTO) | |
2693 | arm_abi = ARM_ABI_APCS; | |
2694 | ||
2695 | /* We used to default to FPA for generic ARM, but almost nobody | |
2696 | uses that now, and we now provide a way for the user to force | |
2697 | the model. So default to the most useful variant. */ | |
2698 | if (fp_model == ARM_FLOAT_AUTO) | |
2699 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2700 | } | |
2701 | ||
2702 | /* If there is already a candidate, use it. */ | |
2703 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2704 | best_arch != NULL; | |
2705 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2706 | { | |
2707 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
2708 | continue; | |
2709 | ||
2710 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
2711 | continue; | |
2712 | ||
2713 | /* Found a match. */ | |
2714 | break; | |
2715 | } | |
97e03143 | 2716 | |
28e97307 DJ |
2717 | if (best_arch != NULL) |
2718 | return best_arch->gdbarch; | |
2719 | ||
2720 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2721 | gdbarch = gdbarch_alloc (&info, tdep); |
2722 | ||
28e97307 DJ |
2723 | /* Record additional information about the architecture we are defining. |
2724 | These are gdbarch discriminators, like the OSABI. */ | |
2725 | tdep->arm_abi = arm_abi; | |
2726 | tdep->fp_model = fp_model; | |
08216dd7 RE |
2727 | |
2728 | /* Breakpoints. */ | |
67255d04 RE |
2729 | switch (info.byte_order) |
2730 | { | |
2731 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2732 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2733 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2734 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2735 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2736 | ||
67255d04 RE |
2737 | break; |
2738 | ||
2739 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2740 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2741 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2742 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2743 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2744 | ||
67255d04 RE |
2745 | break; |
2746 | ||
2747 | default: | |
2748 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2749 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2750 | } |
2751 | ||
d7b486e7 RE |
2752 | /* On ARM targets char defaults to unsigned. */ |
2753 | set_gdbarch_char_signed (gdbarch, 0); | |
2754 | ||
9df628e0 | 2755 | /* This should be low enough for everything. */ |
97e03143 | 2756 | tdep->lowest_pc = 0x20; |
94c30b78 | 2757 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2758 | |
7c00367c MK |
2759 | /* The default, for both APCS and AAPCS, is to return small |
2760 | structures in registers. */ | |
2761 | tdep->struct_return = reg_struct_return; | |
2762 | ||
2dd604e7 | 2763 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 2764 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 2765 | |
756fe439 DJ |
2766 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2767 | ||
148754e5 | 2768 | /* Frame handling. */ |
eb5492fa DJ |
2769 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2770 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2771 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2772 | ||
eb5492fa | 2773 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2774 | |
34e8f22d RE |
2775 | /* Address manipulation. */ |
2776 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2777 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2778 | ||
34e8f22d RE |
2779 | /* Advance PC across function entry code. */ |
2780 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2781 | ||
34e8f22d RE |
2782 | /* The stack grows downward. */ |
2783 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2784 | ||
2785 | /* Breakpoint manipulation. */ | |
2786 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2787 | |
2788 | /* Information about registers, etc. */ | |
2789 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2790 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2791 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2792 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2793 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2794 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2795 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2796 | |
26216b98 AC |
2797 | /* Internal <-> external register number maps. */ |
2798 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2799 | ||
34e8f22d | 2800 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2801 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2802 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2803 | ||
2804 | /* Returning results. */ | |
2af48f68 | 2805 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d RE |
2806 | |
2807 | /* Single stepping. */ | |
2808 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2809 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2810 | ||
03d48a7d RE |
2811 | /* Disassembly. */ |
2812 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2813 | ||
34e8f22d RE |
2814 | /* Minsymbol frobbing. */ |
2815 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2816 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2817 | arm_coff_make_msymbol_special); | |
2818 | ||
97e03143 | 2819 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2820 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2821 | |
eb5492fa | 2822 | /* Add some default predicates. */ |
909cf6ea | 2823 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
842e1f1e | 2824 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2825 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2826 | ||
97e03143 RE |
2827 | /* Now we have tuned the configuration, set a few final things, |
2828 | based on what the OS ABI has told us. */ | |
2829 | ||
9df628e0 RE |
2830 | if (tdep->jb_pc >= 0) |
2831 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2832 | ||
08216dd7 RE |
2833 | /* Floating point sizes and format. */ |
2834 | switch (info.byte_order) | |
2835 | { | |
2836 | case BFD_ENDIAN_BIG: | |
2837 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2838 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2839 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
08216dd7 RE |
2840 | break; |
2841 | ||
2842 | case BFD_ENDIAN_LITTLE: | |
2843 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
28e97307 DJ |
2844 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
2845 | { | |
2846 | set_gdbarch_double_format | |
2847 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2848 | set_gdbarch_long_double_format | |
2849 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2850 | } | |
2851 | else | |
2852 | { | |
2853 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2854 | set_gdbarch_long_double_format (gdbarch, | |
2855 | &floatformat_ieee_double_little); | |
2856 | } | |
08216dd7 RE |
2857 | break; |
2858 | ||
2859 | default: | |
2860 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2861 | _("arm_gdbarch_init: bad byte order for float format")); |
08216dd7 RE |
2862 | } |
2863 | ||
39bbf761 RE |
2864 | return gdbarch; |
2865 | } | |
2866 | ||
97e03143 RE |
2867 | static void |
2868 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2869 | { | |
2870 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2871 | ||
2872 | if (tdep == NULL) | |
2873 | return; | |
2874 | ||
edefbb7c | 2875 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
2876 | (unsigned long) tdep->lowest_pc); |
2877 | } | |
2878 | ||
a78f21af AC |
2879 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2880 | ||
c906108c | 2881 | void |
ed9a39eb | 2882 | _initialize_arm_tdep (void) |
c906108c | 2883 | { |
bc90b915 FN |
2884 | struct ui_file *stb; |
2885 | long length; | |
26304000 | 2886 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2887 | const char *setname; |
2888 | const char *setdesc; | |
4bd7b427 | 2889 | const char *const *regnames; |
bc90b915 FN |
2890 | int numregs, i, j; |
2891 | static char *helptext; | |
edefbb7c AC |
2892 | char regdesc[1024], *rdptr = regdesc; |
2893 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 2894 | |
42cf1509 | 2895 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2896 | |
70f80edf JT |
2897 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2898 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2899 | bfd_target_elf_flavour, | |
2900 | arm_elf_osabi_sniffer); | |
2901 | ||
94c30b78 | 2902 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2903 | num_disassembly_options = get_arm_regname_num_options (); |
2904 | ||
2905 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2906 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 2907 | _("Various ARM-specific commands."), |
afd7eef0 RE |
2908 | &setarmcmdlist, "set arm ", 0, &setlist); |
2909 | ||
2910 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 2911 | _("Various ARM-specific commands."), |
afd7eef0 | 2912 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 2913 | |
94c30b78 | 2914 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2915 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2916 | |
eefe576e AC |
2917 | /* Initialize the array that will be passed to |
2918 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
2919 | valid_disassembly_styles |
2920 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2921 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2922 | { |
2923 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2924 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
2925 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
2926 | rdptr += length; | |
2927 | rest -= length; | |
94c30b78 | 2928 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2929 | if (!strcmp (setname, "std")) |
2930 | { | |
afd7eef0 | 2931 | disassembly_style = setname; |
bc90b915 FN |
2932 | current_option = i; |
2933 | for (j = 0; j < numregs; j++) | |
2934 | arm_register_names[j] = (char *) regnames[j]; | |
2935 | set_arm_regname_option (i); | |
2936 | } | |
2937 | } | |
94c30b78 | 2938 | /* Mark the end of valid options. */ |
afd7eef0 | 2939 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2940 | |
edefbb7c AC |
2941 | /* Create the help text. */ |
2942 | stb = mem_fileopen (); | |
2943 | fprintf_unfiltered (stb, "%s%s%s", | |
2944 | _("The valid values are:\n"), | |
2945 | regdesc, | |
2946 | _("The default is \"std\".")); | |
bc90b915 FN |
2947 | helptext = ui_file_xstrdup (stb, &length); |
2948 | ui_file_delete (stb); | |
ed9a39eb | 2949 | |
edefbb7c AC |
2950 | add_setshow_enum_cmd("disassembler", no_class, |
2951 | valid_disassembly_styles, &disassembly_style, | |
2952 | _("Set the disassembly style."), | |
2953 | _("Show the disassembly style."), | |
2954 | helptext, | |
2c5b56ce | 2955 | set_disassembly_style_sfunc, |
7915a72c | 2956 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 2957 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
2958 | |
2959 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2960 | _("Set usage of ARM 32-bit mode."), | |
2961 | _("Show usage of ARM 32-bit mode."), | |
2962 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 2963 | NULL, |
7915a72c | 2964 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 2965 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 2966 | |
fd50bc42 | 2967 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
2968 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
2969 | _("Set the floating point type."), | |
2970 | _("Show the floating point type."), | |
2971 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
2972 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
2973 | fpa - FPA co-processor (GCC compiled).\n\ | |
2974 | softvfp - Software FP with pure-endian doubles.\n\ | |
2975 | vfp - VFP co-processor."), | |
edefbb7c | 2976 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 2977 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 2978 | |
28e97307 DJ |
2979 | /* Add a command to allow the user to force the ABI. */ |
2980 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
2981 | _("Set the ABI."), | |
2982 | _("Show the ABI."), | |
2983 | NULL, arm_set_abi, arm_show_abi, | |
2984 | &setarmcmdlist, &showarmcmdlist); | |
2985 | ||
6529d2dd | 2986 | /* Debugging flag. */ |
edefbb7c AC |
2987 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2988 | _("Set ARM debugging."), | |
2989 | _("Show ARM debugging."), | |
2990 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 2991 | NULL, |
7915a72c | 2992 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 2993 | &setdebuglist, &showdebuglist); |
c906108c | 2994 | } |