Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 AC |
2 | |
3 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, | |
4 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c | 22 | |
34e8f22d RE |
23 | #include <ctype.h> /* XXX for isupper () */ |
24 | ||
c906108c SS |
25 | #include "defs.h" |
26 | #include "frame.h" | |
27 | #include "inferior.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
c906108c | 30 | #include "gdb_string.h" |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
4be87837 | 36 | #include "osabi.h" |
eb5492fa DJ |
37 | #include "frame-unwind.h" |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
842e1f1e DJ |
40 | #include "objfiles.h" |
41 | #include "dwarf2-frame.h" | |
34e8f22d RE |
42 | |
43 | #include "arm-tdep.h" | |
26216b98 | 44 | #include "gdb/sim-arm.h" |
34e8f22d | 45 | |
082fc60d RE |
46 | #include "elf-bfd.h" |
47 | #include "coff/internal.h" | |
97e03143 | 48 | #include "elf/arm.h" |
c906108c | 49 | |
26216b98 AC |
50 | #include "gdb_assert.h" |
51 | ||
6529d2dd AC |
52 | static int arm_debug; |
53 | ||
2a451106 KB |
54 | /* Each OS has a different mechanism for accessing the various |
55 | registers stored in the sigcontext structure. | |
56 | ||
57 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
58 | function pointer) which may be used to determine the addresses | |
59 | of the various saved registers in the sigcontext structure. | |
60 | ||
61 | For the ARM target, there are three parameters to this function. | |
62 | The first is the pc value of the frame under consideration, the | |
63 | second the stack pointer of this frame, and the last is the | |
64 | register number to fetch. | |
65 | ||
66 | If the tm.h file does not define this macro, then it's assumed that | |
67 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
68 | be 0. | |
69 | ||
70 | When it comes time to multi-arching this code, see the identically | |
71 | named machinery in ia64-tdep.c for an example of how it could be | |
72 | done. It should not be necessary to modify the code below where | |
73 | this macro is used. */ | |
74 | ||
3bb04bdd AC |
75 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
76 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
78 | #endif | |
79 | #else | |
80 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
81 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
82 | #endif |
83 | ||
082fc60d RE |
84 | /* Macros for setting and testing a bit in a minimal symbol that marks |
85 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 86 | is used for this purpose. |
082fc60d RE |
87 | |
88 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 89 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
90 | |
91 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
92 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
93 | | 0x80000000) | |
94 | ||
95 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
96 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
97 | ||
afd7eef0 RE |
98 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
99 | static struct cmd_list_element *setarmcmdlist = NULL; | |
100 | static struct cmd_list_element *showarmcmdlist = NULL; | |
101 | ||
fd50bc42 RE |
102 | /* The type of floating-point to use. Keep this in sync with enum |
103 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
104 | static const char *fp_model_strings[] = | |
105 | { | |
106 | "auto", | |
107 | "softfpa", | |
108 | "fpa", | |
109 | "softvfp", | |
110 | "vfp" | |
111 | }; | |
112 | ||
113 | /* A variable that can be configured by the user. */ | |
114 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
115 | static const char *current_fp_model = "auto"; | |
116 | ||
94c30b78 | 117 | /* Number of different reg name sets (options). */ |
afd7eef0 | 118 | static int num_disassembly_options; |
bc90b915 FN |
119 | |
120 | /* We have more registers than the disassembler as gdb can print the value | |
121 | of special registers as well. | |
122 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 123 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 124 | |
94c30b78 | 125 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 126 | static char * arm_register_name_strings[] = |
da59e081 JM |
127 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
128 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
129 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
130 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
131 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
132 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 133 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 134 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 135 | |
afd7eef0 RE |
136 | /* Valid register name styles. */ |
137 | static const char **valid_disassembly_styles; | |
ed9a39eb | 138 | |
afd7eef0 RE |
139 | /* Disassembly style to use. Default to "std" register names. */ |
140 | static const char *disassembly_style; | |
94c30b78 | 141 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 142 | static int current_option; |
96baa820 | 143 | |
ed9a39eb | 144 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
145 | style. */ |
146 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 147 | struct cmd_list_element *); |
afd7eef0 | 148 | static void set_disassembly_style (void); |
ed9a39eb | 149 | |
b508a996 RE |
150 | static void convert_from_extended (const struct floatformat *, const void *, |
151 | void *); | |
152 | static void convert_to_extended (const struct floatformat *, void *, | |
153 | const void *); | |
ed9a39eb | 154 | |
9b8d791a | 155 | struct arm_prologue_cache |
c3b4394c | 156 | { |
eb5492fa DJ |
157 | /* The stack pointer at the time this frame was created; i.e. the |
158 | caller's stack pointer when this function was called. It is used | |
159 | to identify this frame. */ | |
160 | CORE_ADDR prev_sp; | |
161 | ||
162 | /* The frame base for this frame is just prev_sp + frame offset - | |
163 | frame size. FRAMESIZE is the size of this stack frame, and | |
164 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
165 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
166 | ||
c3b4394c RE |
167 | int framesize; |
168 | int frameoffset; | |
eb5492fa DJ |
169 | |
170 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 171 | int framereg; |
eb5492fa DJ |
172 | |
173 | /* Saved register offsets. */ | |
174 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 175 | }; |
ed9a39eb | 176 | |
bc90b915 FN |
177 | /* Addresses for calling Thumb functions have the bit 0 set. |
178 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
179 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
180 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
181 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
182 | ||
94c30b78 | 183 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
184 | |
185 | int arm_apcs_32 = 1; | |
186 | ||
ed9a39eb JM |
187 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
188 | function. */ | |
c906108c | 189 | |
34e8f22d | 190 | int |
2a451106 | 191 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 192 | { |
c5aa993b | 193 | struct minimal_symbol *sym; |
c906108c | 194 | |
ed9a39eb | 195 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
196 | if (IS_THUMB_ADDR (memaddr)) |
197 | return 1; | |
198 | ||
ed9a39eb | 199 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
200 | sym = lookup_minimal_symbol_by_pc (memaddr); |
201 | if (sym) | |
202 | { | |
c5aa993b | 203 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
204 | } |
205 | else | |
ed9a39eb JM |
206 | { |
207 | return 0; | |
208 | } | |
c906108c SS |
209 | } |
210 | ||
181c1381 | 211 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 212 | static CORE_ADDR |
ed9a39eb | 213 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 214 | { |
a3a2ee65 JT |
215 | if (arm_apcs_32) |
216 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 217 | else |
a3a2ee65 | 218 | return (val & 0x03fffffc); |
c906108c SS |
219 | } |
220 | ||
181c1381 RE |
221 | /* When reading symbols, we need to zap the low bit of the address, |
222 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 223 | static CORE_ADDR |
181c1381 RE |
224 | arm_smash_text_address (CORE_ADDR val) |
225 | { | |
226 | return val & ~1; | |
227 | } | |
228 | ||
34e8f22d RE |
229 | /* Immediately after a function call, return the saved pc. Can't |
230 | always go through the frames for this because on some machines the | |
231 | new frame is not set up until the new function executes some | |
232 | instructions. */ | |
233 | ||
234 | static CORE_ADDR | |
ed9a39eb | 235 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 236 | { |
34e8f22d | 237 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
238 | } |
239 | ||
240 | /* A typical Thumb prologue looks like this: | |
c5aa993b JM |
241 | push {r7, lr} |
242 | add sp, sp, #-28 | |
243 | add r7, sp, #12 | |
c906108c | 244 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
245 | mov r7, sp |
246 | ||
247 | or like this: | |
248 | push {r7, lr} | |
249 | mov r7, sp | |
250 | sub sp, #12 | |
251 | ||
252 | or, on tpcs, like this: | |
253 | sub sp,#16 | |
254 | push {r7, lr} | |
255 | (many instructions) | |
256 | mov r7, sp | |
257 | sub sp, #12 | |
258 | ||
259 | There is always one instruction of three classes: | |
260 | 1 - push | |
261 | 2 - setting of r7 | |
262 | 3 - adjusting of sp | |
263 | ||
264 | When we have found at least one of each class we are done with the prolog. | |
265 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 266 | */ |
c906108c SS |
267 | |
268 | static CORE_ADDR | |
c7885828 | 269 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
270 | { |
271 | CORE_ADDR current_pc; | |
da3c6d4a MS |
272 | /* findmask: |
273 | bit 0 - push { rlist } | |
274 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
275 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
276 | */ | |
277 | int findmask = 0; | |
278 | ||
94c30b78 MS |
279 | for (current_pc = pc; |
280 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 281 | current_pc += 2) |
c906108c SS |
282 | { |
283 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
284 | ||
94c30b78 | 285 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 286 | { |
94c30b78 | 287 | findmask |= 1; /* push found */ |
da59e081 | 288 | } |
da3c6d4a MS |
289 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
290 | sub sp, #simm */ | |
da59e081 | 291 | { |
94c30b78 | 292 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
293 | continue; |
294 | else | |
94c30b78 | 295 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
296 | } |
297 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
298 | { | |
94c30b78 | 299 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
300 | } |
301 | else if (insn == 0x466f) /* mov r7, sp */ | |
302 | { | |
94c30b78 | 303 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 304 | } |
3d74b771 FF |
305 | else if (findmask == (4+2+1)) |
306 | { | |
da3c6d4a MS |
307 | /* We have found one of each type of prologue instruction */ |
308 | break; | |
3d74b771 | 309 | } |
da59e081 | 310 | else |
94c30b78 | 311 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 312 | instruction from outside the prolog scheduled here for |
94c30b78 | 313 | optimization. */ |
da3c6d4a | 314 | continue; |
c906108c SS |
315 | } |
316 | ||
317 | return current_pc; | |
318 | } | |
319 | ||
da3c6d4a MS |
320 | /* Advance the PC across any function entry prologue instructions to |
321 | reach some "real" code. | |
34e8f22d RE |
322 | |
323 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 324 | prologue: |
c906108c | 325 | |
c5aa993b JM |
326 | mov ip, sp |
327 | [stmfd sp!, {a1,a2,a3,a4}] | |
328 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
329 | [stfe f7, [sp, #-12]!] |
330 | [stfe f6, [sp, #-12]!] | |
331 | [stfe f5, [sp, #-12]!] | |
332 | [stfe f4, [sp, #-12]!] | |
333 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 334 | |
34e8f22d | 335 | static CORE_ADDR |
ed9a39eb | 336 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
337 | { |
338 | unsigned long inst; | |
339 | CORE_ADDR skip_pc; | |
b8d5e71d | 340 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 341 | char *func_name; |
c906108c SS |
342 | struct symtab_and_line sal; |
343 | ||
848cfffb | 344 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 345 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
346 | return pc; |
347 | ||
96baa820 | 348 | /* See what the symbol table says. */ |
ed9a39eb | 349 | |
50f6fb4b | 350 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 351 | { |
50f6fb4b CV |
352 | struct symbol *sym; |
353 | ||
354 | /* Found a function. */ | |
176620f1 | 355 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
356 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
357 | { | |
94c30b78 | 358 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
359 | sal = find_pc_line (func_addr, 0); |
360 | if ((sal.line != 0) && (sal.end < func_end)) | |
361 | return sal.end; | |
362 | } | |
c906108c SS |
363 | } |
364 | ||
365 | /* Check if this is Thumb code. */ | |
366 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 367 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
368 | |
369 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 370 | by disassembling the instructions. */ |
c906108c | 371 | |
b8d5e71d MS |
372 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
373 | if (func_end == 0 || func_end > pc + 64) | |
374 | func_end = pc + 64; | |
c906108c | 375 | |
b8d5e71d | 376 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 377 | { |
f43845b3 | 378 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 379 | |
b8d5e71d MS |
380 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
381 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
382 | continue; | |
c906108c | 383 | |
28cd8767 JG |
384 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
385 | continue; | |
386 | ||
387 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
388 | continue; | |
389 | ||
b8d5e71d MS |
390 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
391 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
392 | continue; | |
c906108c | 393 | |
b8d5e71d MS |
394 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
395 | continue; | |
c906108c | 396 | |
b8d5e71d MS |
397 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
398 | continue; | |
11d3b27d | 399 | |
b8d5e71d MS |
400 | /* Any insns after this point may float into the code, if it makes |
401 | for better instruction scheduling, so we skip them only if we | |
402 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 403 | |
b8d5e71d MS |
404 | /* We may have either one sfmfd instruction here, or several stfe |
405 | insns, depending on the version of floating point code we | |
406 | support. */ | |
407 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
408 | continue; | |
409 | ||
410 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
411 | continue; | |
412 | ||
413 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
414 | continue; | |
415 | ||
416 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
417 | continue; | |
418 | ||
419 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
420 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
421 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
422 | continue; | |
423 | ||
424 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
425 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
426 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
427 | continue; | |
428 | ||
429 | /* Un-recognized instruction; stop scanning. */ | |
430 | break; | |
f43845b3 | 431 | } |
c906108c | 432 | |
b8d5e71d | 433 | return skip_pc; /* End of prologue */ |
c906108c | 434 | } |
94c30b78 | 435 | |
c5aa993b | 436 | /* *INDENT-OFF* */ |
c906108c SS |
437 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
438 | This function decodes a Thumb function prologue to determine: | |
439 | 1) the size of the stack frame | |
440 | 2) which registers are saved on it | |
441 | 3) the offsets of saved regs | |
442 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 443 | |
da59e081 JM |
444 | A typical Thumb function prologue would create this stack frame |
445 | (offsets relative to FP) | |
c906108c SS |
446 | old SP -> 24 stack parameters |
447 | 20 LR | |
448 | 16 R7 | |
449 | R7 -> 0 local variables (16 bytes) | |
450 | SP -> -12 additional stack space (12 bytes) | |
451 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
452 | 12 bytes. The frame register is R7. |
453 | ||
da3c6d4a MS |
454 | The comments for thumb_skip_prolog() describe the algorithm we use |
455 | to detect the end of the prolog. */ | |
c5aa993b JM |
456 | /* *INDENT-ON* */ |
457 | ||
c906108c | 458 | static void |
eb5492fa | 459 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
460 | { |
461 | CORE_ADDR prologue_start; | |
462 | CORE_ADDR prologue_end; | |
463 | CORE_ADDR current_pc; | |
94c30b78 | 464 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
465 | int saved_reg[16]; |
466 | /* findmask: | |
467 | bit 0 - push { rlist } | |
468 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
469 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
470 | */ | |
471 | int findmask = 0; | |
c5aa993b | 472 | int i; |
c906108c | 473 | |
eb5492fa | 474 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
475 | { |
476 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
477 | ||
94c30b78 | 478 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 479 | prologue_end = prev_pc; |
c906108c | 480 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 481 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
482 | } |
483 | else | |
da3c6d4a MS |
484 | /* We're in the boondocks: allow for |
485 | 16 pushes, an add, and "mv fp,sp". */ | |
486 | prologue_end = prologue_start + 40; | |
c906108c | 487 | |
eb5492fa | 488 | prologue_end = min (prologue_end, prev_pc); |
c906108c SS |
489 | |
490 | /* Initialize the saved register map. When register H is copied to | |
491 | register L, we will put H in saved_reg[L]. */ | |
492 | for (i = 0; i < 16; i++) | |
493 | saved_reg[i] = i; | |
494 | ||
495 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
496 | frame pointer, adjust the stack pointer, and save registers. |
497 | Do this until all basic prolog instructions are found. */ | |
c906108c | 498 | |
9b8d791a | 499 | cache->framesize = 0; |
da59e081 JM |
500 | for (current_pc = prologue_start; |
501 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
502 | current_pc += 2) | |
c906108c SS |
503 | { |
504 | unsigned short insn; | |
505 | int regno; | |
506 | int offset; | |
507 | ||
508 | insn = read_memory_unsigned_integer (current_pc, 2); | |
509 | ||
c5aa993b | 510 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 511 | { |
da59e081 | 512 | int mask; |
94c30b78 | 513 | findmask |= 1; /* push found */ |
c906108c SS |
514 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
515 | whether to save LR (R14). */ | |
da59e081 | 516 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 517 | |
b8d5e71d | 518 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 519 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 520 | if (mask & (1 << regno)) |
c5aa993b | 521 | { |
9b8d791a | 522 | cache->framesize += 4; |
eb5492fa | 523 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
da3c6d4a MS |
524 | /* Reset saved register map. */ |
525 | saved_reg[regno] = regno; | |
c906108c SS |
526 | } |
527 | } | |
da3c6d4a MS |
528 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
529 | sub sp, #simm */ | |
c906108c | 530 | { |
b8d5e71d | 531 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
532 | continue; |
533 | else | |
94c30b78 | 534 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 535 | |
94c30b78 MS |
536 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
537 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 538 | { |
9b8d791a | 539 | cache->frameoffset += offset; |
da59e081 JM |
540 | offset = -offset; |
541 | } | |
9b8d791a | 542 | cache->framesize -= offset; |
c906108c SS |
543 | } |
544 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
545 | { | |
94c30b78 | 546 | findmask |= 2; /* setting of r7 found */ |
9b8d791a | 547 | cache->framereg = THUMB_FP_REGNUM; |
c3b4394c | 548 | /* get scaled offset */ |
9b8d791a | 549 | cache->frameoffset = (insn & 0xff) << 2; |
c906108c | 550 | } |
da59e081 | 551 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 552 | { |
94c30b78 | 553 | findmask |= 2; /* setting of r7 found */ |
9b8d791a DJ |
554 | cache->framereg = THUMB_FP_REGNUM; |
555 | cache->frameoffset = 0; | |
34e8f22d | 556 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
557 | } |
558 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
559 | { | |
da3c6d4a | 560 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 561 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 562 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
563 | } |
564 | else | |
da3c6d4a MS |
565 | /* Something in the prolog that we don't care about or some |
566 | instruction from outside the prolog scheduled here for | |
567 | optimization. */ | |
568 | continue; | |
c906108c SS |
569 | } |
570 | } | |
571 | ||
ed9a39eb | 572 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
573 | 1) the size of the stack frame |
574 | 2) which registers are saved on it | |
575 | 3) the offsets of saved regs | |
576 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
577 | This information is stored in the "extra" fields of the frame_info. |
578 | ||
96baa820 JM |
579 | There are two basic forms for the ARM prologue. The fixed argument |
580 | function call will look like: | |
ed9a39eb JM |
581 | |
582 | mov ip, sp | |
583 | stmfd sp!, {fp, ip, lr, pc} | |
584 | sub fp, ip, #4 | |
585 | [sub sp, sp, #4] | |
96baa820 | 586 | |
c906108c | 587 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
588 | IP -> 4 (caller's stack) |
589 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
590 | -4 LR (return address in caller) | |
591 | -8 IP (copy of caller's SP) | |
592 | -12 FP (caller's FP) | |
593 | SP -> -28 Local variables | |
594 | ||
c906108c | 595 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
596 | 28 bytes. The stmfd call can also save any of the vN registers it |
597 | plans to use, which increases the frame size accordingly. | |
598 | ||
599 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
600 | because the ARM Store instructions always store PC + 8 when you read | |
601 | the PC register. | |
ed9a39eb | 602 | |
96baa820 JM |
603 | A variable argument function call will look like: |
604 | ||
ed9a39eb JM |
605 | mov ip, sp |
606 | stmfd sp!, {a1, a2, a3, a4} | |
607 | stmfd sp!, {fp, ip, lr, pc} | |
608 | sub fp, ip, #20 | |
609 | ||
96baa820 | 610 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
611 | IP -> 20 (caller's stack) |
612 | 16 A4 | |
613 | 12 A3 | |
614 | 8 A2 | |
615 | 4 A1 | |
616 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
617 | -4 LR (return address in caller) | |
618 | -8 IP (copy of caller's SP) | |
619 | -12 FP (caller's FP) | |
620 | SP -> -28 Local variables | |
96baa820 JM |
621 | |
622 | The frame size would thus be 48 bytes, and the frame offset would be | |
623 | 28 bytes. | |
624 | ||
625 | There is another potential complication, which is that the optimizer | |
626 | will try to separate the store of fp in the "stmfd" instruction from | |
627 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
628 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
629 | ||
630 | Also, note, the original version of the ARM toolchain claimed that there | |
631 | should be an | |
632 | ||
633 | instruction at the end of the prologue. I have never seen GCC produce | |
634 | this, and the ARM docs don't mention it. We still test for it below in | |
635 | case it happens... | |
ed9a39eb JM |
636 | |
637 | */ | |
c906108c SS |
638 | |
639 | static void | |
eb5492fa | 640 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 641 | { |
28cd8767 | 642 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 643 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 644 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 645 | |
c906108c | 646 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
647 | cache->framereg = ARM_SP_REGNUM; |
648 | cache->framesize = 0; | |
649 | cache->frameoffset = 0; | |
c906108c SS |
650 | |
651 | /* Check for Thumb prologue. */ | |
eb5492fa | 652 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 653 | { |
eb5492fa | 654 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
655 | return; |
656 | } | |
657 | ||
658 | /* Find the function prologue. If we can't find the function in | |
659 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 660 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 661 | { |
2a451106 KB |
662 | /* One way to find the end of the prologue (which works well |
663 | for unoptimized code) is to do the following: | |
664 | ||
665 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
666 | ||
667 | if (sal.line == 0) | |
eb5492fa | 668 | prologue_end = prev_pc; |
2a451106 KB |
669 | else if (sal.end < prologue_end) |
670 | prologue_end = sal.end; | |
671 | ||
672 | This mechanism is very accurate so long as the optimizer | |
673 | doesn't move any instructions from the function body into the | |
674 | prologue. If this happens, sal.end will be the last | |
675 | instruction in the first hunk of prologue code just before | |
676 | the first instruction that the scheduler has moved from | |
677 | the body to the prologue. | |
678 | ||
679 | In order to make sure that we scan all of the prologue | |
680 | instructions, we use a slightly less accurate mechanism which | |
681 | may scan more than necessary. To help compensate for this | |
682 | lack of accuracy, the prologue scanning loop below contains | |
683 | several clauses which'll cause the loop to terminate early if | |
684 | an implausible prologue instruction is encountered. | |
685 | ||
686 | The expression | |
687 | ||
688 | prologue_start + 64 | |
689 | ||
690 | is a suitable endpoint since it accounts for the largest | |
691 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 692 | the scheduler. */ |
2a451106 KB |
693 | |
694 | if (prologue_end > prologue_start + 64) | |
695 | { | |
94c30b78 | 696 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 697 | } |
c906108c SS |
698 | } |
699 | else | |
700 | { | |
eb5492fa DJ |
701 | /* We have no symbol information. Our only option is to assume this |
702 | function has a standard stack frame and the normal frame register. | |
703 | Then, we can find the value of our frame pointer on entrance to | |
704 | the callee (or at the present moment if this is the innermost frame). | |
705 | The value stored there should be the address of the stmfd + 8. */ | |
706 | CORE_ADDR frame_loc; | |
707 | LONGEST return_value; | |
708 | ||
709 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
710 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
711 | return; |
712 | else | |
713 | { | |
714 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 715 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 716 | } |
c906108c SS |
717 | } |
718 | ||
eb5492fa DJ |
719 | if (prev_pc < prologue_end) |
720 | prologue_end = prev_pc; | |
721 | ||
c906108c | 722 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 723 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 724 | |
96baa820 JM |
725 | Be careful, however, and if it doesn't look like a prologue, |
726 | don't try to scan it. If, for instance, a frameless function | |
727 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 728 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
729 | and other operations that rely on a knowledge of the stack |
730 | traceback. | |
731 | ||
732 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 733 | if we don't see this as the first insn, we will stop. |
c906108c | 734 | |
f43845b3 MS |
735 | [Note: This doesn't seem to be true any longer, so it's now an |
736 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 737 | |
f43845b3 MS |
738 | [Note further: The "mov ip,sp" only seems to be missing in |
739 | frameless functions at optimization level "-O2" or above, | |
740 | in which case it is often (but not always) replaced by | |
b8d5e71d | 741 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 742 | |
28cd8767 | 743 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 744 | |
94c30b78 MS |
745 | for (current_pc = prologue_start; |
746 | current_pc < prologue_end; | |
f43845b3 | 747 | current_pc += 4) |
96baa820 | 748 | { |
d4473757 KB |
749 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
750 | ||
94c30b78 | 751 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 752 | { |
28cd8767 JG |
753 | ip_offset = 0; |
754 | continue; | |
755 | } | |
756 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
757 | { | |
758 | unsigned imm = insn & 0xff; /* immediate value */ | |
759 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
760 | imm = (imm >> rot) | (imm << (32 - rot)); | |
761 | ip_offset = imm; | |
762 | continue; | |
763 | } | |
764 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
765 | { | |
766 | unsigned imm = insn & 0xff; /* immediate value */ | |
767 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
768 | imm = (imm >> rot) | (imm << (32 - rot)); | |
769 | ip_offset = -imm; | |
f43845b3 MS |
770 | continue; |
771 | } | |
94c30b78 | 772 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 773 | { |
e28a332c JG |
774 | sp_offset -= 4; |
775 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
776 | continue; |
777 | } | |
778 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
779 | /* stmfd sp!, {..., fp, ip, lr, pc} |
780 | or | |
781 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 782 | { |
d4473757 | 783 | int mask = insn & 0xffff; |
ed9a39eb | 784 | |
94c30b78 | 785 | /* Calculate offsets of saved registers. */ |
34e8f22d | 786 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
787 | if (mask & (1 << regno)) |
788 | { | |
789 | sp_offset -= 4; | |
eb5492fa | 790 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
791 | } |
792 | } | |
b8d5e71d MS |
793 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
794 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
795 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
796 | { | |
797 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
798 | continue; | |
799 | } | |
800 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
801 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
802 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
803 | { |
804 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
805 | continue; | |
806 | } | |
d4473757 KB |
807 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
808 | { | |
94c30b78 MS |
809 | unsigned imm = insn & 0xff; /* immediate value */ |
810 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 811 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 812 | fp_offset = -imm + ip_offset; |
9b8d791a | 813 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
814 | } |
815 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
816 | { | |
94c30b78 MS |
817 | unsigned imm = insn & 0xff; /* immediate value */ |
818 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
819 | imm = (imm >> rot) | (imm << (32 - rot)); |
820 | sp_offset -= imm; | |
821 | } | |
822 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
823 | { | |
824 | sp_offset -= 12; | |
34e8f22d | 825 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 826 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
827 | } |
828 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
829 | { | |
830 | int n_saved_fp_regs; | |
831 | unsigned int fp_start_reg, fp_bound_reg; | |
832 | ||
94c30b78 | 833 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 834 | { |
d4473757 KB |
835 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
836 | n_saved_fp_regs = 3; | |
837 | else | |
838 | n_saved_fp_regs = 1; | |
96baa820 | 839 | } |
d4473757 | 840 | else |
96baa820 | 841 | { |
d4473757 KB |
842 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
843 | n_saved_fp_regs = 2; | |
844 | else | |
845 | n_saved_fp_regs = 4; | |
96baa820 | 846 | } |
d4473757 | 847 | |
34e8f22d | 848 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
849 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
850 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
851 | { |
852 | sp_offset -= 12; | |
eb5492fa | 853 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 854 | } |
c906108c | 855 | } |
d4473757 | 856 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 857 | break; /* Condition not true, exit early */ |
b8d5e71d | 858 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 859 | break; /* Don't scan past a block load */ |
d4473757 KB |
860 | else |
861 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 862 | so we just skip what we don't recognize. */ |
d4473757 | 863 | continue; |
c906108c SS |
864 | } |
865 | ||
94c30b78 MS |
866 | /* The frame size is just the negative of the offset (from the |
867 | original SP) of the last thing thing we pushed on the stack. | |
868 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
869 | cache->framesize = -sp_offset; |
870 | if (cache->framereg == ARM_FP_REGNUM) | |
871 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 872 | else |
9b8d791a | 873 | cache->frameoffset = 0; |
c906108c SS |
874 | } |
875 | ||
eb5492fa DJ |
876 | static struct arm_prologue_cache * |
877 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 878 | { |
eb5492fa DJ |
879 | int reg; |
880 | struct arm_prologue_cache *cache; | |
881 | CORE_ADDR unwound_fp; | |
c5aa993b | 882 | |
eb5492fa DJ |
883 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
884 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c906108c | 885 | |
eb5492fa | 886 | arm_scan_prologue (next_frame, cache); |
848cfffb | 887 | |
eb5492fa DJ |
888 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
889 | if (unwound_fp == 0) | |
890 | return cache; | |
c906108c | 891 | |
eb5492fa | 892 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 893 | |
eb5492fa DJ |
894 | /* Calculate actual addresses of saved registers using offsets |
895 | determined by arm_scan_prologue. */ | |
896 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 897 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
898 | cache->saved_regs[reg].addr += cache->prev_sp; |
899 | ||
900 | return cache; | |
c906108c SS |
901 | } |
902 | ||
eb5492fa DJ |
903 | /* Our frame ID for a normal frame is the current function's starting PC |
904 | and the caller's SP when we were called. */ | |
c906108c | 905 | |
148754e5 | 906 | static void |
eb5492fa DJ |
907 | arm_prologue_this_id (struct frame_info *next_frame, |
908 | void **this_cache, | |
909 | struct frame_id *this_id) | |
c906108c | 910 | { |
eb5492fa DJ |
911 | struct arm_prologue_cache *cache; |
912 | struct frame_id id; | |
913 | CORE_ADDR func; | |
f079148d | 914 | |
eb5492fa DJ |
915 | if (*this_cache == NULL) |
916 | *this_cache = arm_make_prologue_cache (next_frame); | |
917 | cache = *this_cache; | |
2a451106 | 918 | |
eb5492fa | 919 | func = frame_func_unwind (next_frame); |
2a451106 | 920 | |
eb5492fa DJ |
921 | /* This is meant to halt the backtrace at "_start". Make sure we |
922 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 923 | if (func <= LOWEST_PC) |
eb5492fa | 924 | return; |
5a203e44 | 925 | |
eb5492fa DJ |
926 | /* If we've hit a wall, stop. */ |
927 | if (cache->prev_sp == 0) | |
928 | return; | |
24de872b | 929 | |
eb5492fa | 930 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 931 | *this_id = id; |
c906108c SS |
932 | } |
933 | ||
eb5492fa DJ |
934 | static void |
935 | arm_prologue_prev_register (struct frame_info *next_frame, | |
936 | void **this_cache, | |
937 | int prev_regnum, | |
938 | int *optimized, | |
939 | enum lval_type *lvalp, | |
940 | CORE_ADDR *addrp, | |
941 | int *realnump, | |
942 | void *valuep) | |
24de872b DJ |
943 | { |
944 | struct arm_prologue_cache *cache; | |
945 | ||
eb5492fa DJ |
946 | if (*this_cache == NULL) |
947 | *this_cache = arm_make_prologue_cache (next_frame); | |
948 | cache = *this_cache; | |
24de872b | 949 | |
eb5492fa DJ |
950 | /* If we are asked to unwind the PC, then we need to return the LR |
951 | instead. The saved value of PC points into this frame's | |
952 | prologue, not the next frame's resume location. */ | |
953 | if (prev_regnum == ARM_PC_REGNUM) | |
954 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 955 | |
eb5492fa DJ |
956 | /* SP is generally not saved to the stack, but this frame is |
957 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
958 | The value was already reconstructed into PREV_SP. */ | |
959 | if (prev_regnum == ARM_SP_REGNUM) | |
960 | { | |
961 | *lvalp = not_lval; | |
962 | if (valuep) | |
963 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
964 | return; | |
965 | } | |
966 | ||
1f67027d AC |
967 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
968 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
969 | } |
970 | ||
971 | struct frame_unwind arm_prologue_unwind = { | |
972 | NORMAL_FRAME, | |
973 | arm_prologue_this_id, | |
974 | arm_prologue_prev_register | |
975 | }; | |
976 | ||
977 | static const struct frame_unwind * | |
978 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
979 | { | |
980 | return &arm_prologue_unwind; | |
24de872b DJ |
981 | } |
982 | ||
909cf6ea DJ |
983 | static struct arm_prologue_cache * |
984 | arm_make_stub_cache (struct frame_info *next_frame) | |
985 | { | |
986 | int reg; | |
987 | struct arm_prologue_cache *cache; | |
988 | CORE_ADDR unwound_fp; | |
989 | ||
990 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
991 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
992 | ||
993 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
994 | ||
995 | return cache; | |
996 | } | |
997 | ||
998 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
999 | ||
1000 | static void | |
1001 | arm_stub_this_id (struct frame_info *next_frame, | |
1002 | void **this_cache, | |
1003 | struct frame_id *this_id) | |
1004 | { | |
1005 | struct arm_prologue_cache *cache; | |
1006 | ||
1007 | if (*this_cache == NULL) | |
1008 | *this_cache = arm_make_stub_cache (next_frame); | |
1009 | cache = *this_cache; | |
1010 | ||
1011 | *this_id = frame_id_build (cache->prev_sp, | |
1012 | frame_pc_unwind (next_frame)); | |
1013 | } | |
1014 | ||
1015 | struct frame_unwind arm_stub_unwind = { | |
1016 | NORMAL_FRAME, | |
1017 | arm_stub_this_id, | |
1018 | arm_prologue_prev_register | |
1019 | }; | |
1020 | ||
1021 | static const struct frame_unwind * | |
1022 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1023 | { | |
1024 | char dummy[4]; | |
1025 | ||
1026 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
1027 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
1028 | return &arm_stub_unwind; | |
1029 | ||
1030 | return NULL; | |
1031 | } | |
1032 | ||
24de872b | 1033 | static CORE_ADDR |
eb5492fa | 1034 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1035 | { |
1036 | struct arm_prologue_cache *cache; | |
1037 | ||
eb5492fa DJ |
1038 | if (*this_cache == NULL) |
1039 | *this_cache = arm_make_prologue_cache (next_frame); | |
1040 | cache = *this_cache; | |
1041 | ||
1042 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1043 | } |
1044 | ||
eb5492fa DJ |
1045 | struct frame_base arm_normal_base = { |
1046 | &arm_prologue_unwind, | |
1047 | arm_normal_frame_base, | |
1048 | arm_normal_frame_base, | |
1049 | arm_normal_frame_base | |
1050 | }; | |
1051 | ||
1052 | static struct arm_prologue_cache * | |
1053 | arm_make_sigtramp_cache (struct frame_info *next_frame) | |
24de872b DJ |
1054 | { |
1055 | struct arm_prologue_cache *cache; | |
eb5492fa DJ |
1056 | int reg; |
1057 | ||
1058 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); | |
24de872b | 1059 | |
eb5492fa | 1060 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
24de872b | 1061 | |
eb5492fa | 1062 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
24de872b | 1063 | |
eb5492fa DJ |
1064 | for (reg = 0; reg < NUM_REGS; reg++) |
1065 | cache->saved_regs[reg].addr | |
1066 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, | |
1067 | frame_pc_unwind (next_frame), reg); | |
24de872b | 1068 | |
eb5492fa DJ |
1069 | /* FIXME: What about thumb mode? */ |
1070 | cache->framereg = ARM_SP_REGNUM; | |
1071 | cache->prev_sp | |
1072 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, | |
7a5ea0d4 | 1073 | register_size (current_gdbarch, cache->framereg)); |
eb5492fa DJ |
1074 | |
1075 | return cache; | |
24de872b | 1076 | } |
c906108c | 1077 | |
eb5492fa DJ |
1078 | static void |
1079 | arm_sigtramp_this_id (struct frame_info *next_frame, | |
1080 | void **this_cache, | |
1081 | struct frame_id *this_id) | |
1082 | { | |
1083 | struct arm_prologue_cache *cache; | |
c906108c | 1084 | |
eb5492fa DJ |
1085 | if (*this_cache == NULL) |
1086 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1087 | cache = *this_cache; | |
c906108c | 1088 | |
eb5492fa DJ |
1089 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
1090 | the sigtramp frame; the PC should be the beginning of the trampoline. */ | |
1091 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); | |
1092 | } | |
1093 | ||
1094 | static void | |
1095 | arm_sigtramp_prev_register (struct frame_info *next_frame, | |
1096 | void **this_cache, | |
1097 | int prev_regnum, | |
1098 | int *optimized, | |
1099 | enum lval_type *lvalp, | |
1100 | CORE_ADDR *addrp, | |
1101 | int *realnump, | |
1102 | void *valuep) | |
c906108c | 1103 | { |
eb5492fa | 1104 | struct arm_prologue_cache *cache; |
848cfffb | 1105 | |
eb5492fa DJ |
1106 | if (*this_cache == NULL) |
1107 | *this_cache = arm_make_sigtramp_cache (next_frame); | |
1108 | cache = *this_cache; | |
1109 | ||
1f67027d AC |
1110 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
1111 | optimized, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1112 | } |
1113 | ||
eb5492fa DJ |
1114 | struct frame_unwind arm_sigtramp_unwind = { |
1115 | SIGTRAMP_FRAME, | |
1116 | arm_sigtramp_this_id, | |
1117 | arm_sigtramp_prev_register | |
1118 | }; | |
c906108c | 1119 | |
eb5492fa DJ |
1120 | static const struct frame_unwind * |
1121 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) | |
c906108c | 1122 | { |
eb5492fa | 1123 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
0b281939 | 1124 | && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0)) |
eb5492fa DJ |
1125 | return &arm_sigtramp_unwind; |
1126 | ||
1127 | return NULL; | |
c906108c SS |
1128 | } |
1129 | ||
eb5492fa DJ |
1130 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1131 | dummy frame. The frame ID's base needs to match the TOS value | |
1132 | saved by save_dummy_frame_tos() and returned from | |
1133 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1134 | breakpoint. */ | |
c906108c | 1135 | |
eb5492fa DJ |
1136 | static struct frame_id |
1137 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1138 | { |
eb5492fa DJ |
1139 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1140 | frame_pc_unwind (next_frame)); | |
1141 | } | |
c3b4394c | 1142 | |
eb5492fa DJ |
1143 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1144 | be used to construct the previous frame's ID, after looking up the | |
1145 | containing function). */ | |
c3b4394c | 1146 | |
eb5492fa DJ |
1147 | static CORE_ADDR |
1148 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1149 | { | |
1150 | CORE_ADDR pc; | |
1151 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
1152 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1153 | } | |
1154 | ||
1155 | static CORE_ADDR | |
1156 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1157 | { | |
1158 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1159 | } |
1160 | ||
2dd604e7 RE |
1161 | /* When arguments must be pushed onto the stack, they go on in reverse |
1162 | order. The code below implements a FILO (stack) to do this. */ | |
1163 | ||
1164 | struct stack_item | |
1165 | { | |
1166 | int len; | |
1167 | struct stack_item *prev; | |
1168 | void *data; | |
1169 | }; | |
1170 | ||
1171 | static struct stack_item * | |
1172 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1173 | { | |
1174 | struct stack_item *si; | |
1175 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1176 | si->data = xmalloc (len); |
2dd604e7 RE |
1177 | si->len = len; |
1178 | si->prev = prev; | |
1179 | memcpy (si->data, contents, len); | |
1180 | return si; | |
1181 | } | |
1182 | ||
1183 | static struct stack_item * | |
1184 | pop_stack_item (struct stack_item *si) | |
1185 | { | |
1186 | struct stack_item *dead = si; | |
1187 | si = si->prev; | |
1188 | xfree (dead->data); | |
1189 | xfree (dead); | |
1190 | return si; | |
1191 | } | |
1192 | ||
1193 | /* We currently only support passing parameters in integer registers. This | |
1194 | conforms with GCC's default model. Several other variants exist and | |
1195 | we should probably support some of them based on the selected ABI. */ | |
1196 | ||
1197 | static CORE_ADDR | |
7d9b040b | 1198 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1199 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1200 | struct value **args, CORE_ADDR sp, int struct_return, | |
1201 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1202 | { |
1203 | int argnum; | |
1204 | int argreg; | |
1205 | int nstack; | |
1206 | struct stack_item *si = NULL; | |
1207 | ||
6a65450a AC |
1208 | /* Set the return address. For the ARM, the return breakpoint is |
1209 | always at BP_ADDR. */ | |
2dd604e7 | 1210 | /* XXX Fix for Thumb. */ |
6a65450a | 1211 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1212 | |
1213 | /* Walk through the list of args and determine how large a temporary | |
1214 | stack is required. Need to take care here as structs may be | |
1215 | passed on the stack, and we have to to push them. */ | |
1216 | nstack = 0; | |
1217 | ||
1218 | argreg = ARM_A1_REGNUM; | |
1219 | nstack = 0; | |
1220 | ||
1221 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1222 | is correctly aligned before we start. We always do this even if | |
1223 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1224 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1225 | |
1226 | /* The struct_return pointer occupies the first parameter | |
1227 | passing register. */ | |
1228 | if (struct_return) | |
1229 | { | |
1230 | if (arm_debug) | |
1231 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1232 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1233 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1234 | argreg++; | |
1235 | } | |
1236 | ||
1237 | for (argnum = 0; argnum < nargs; argnum++) | |
1238 | { | |
1239 | int len; | |
1240 | struct type *arg_type; | |
1241 | struct type *target_type; | |
1242 | enum type_code typecode; | |
0fd88904 | 1243 | bfd_byte *val; |
2dd604e7 | 1244 | |
df407dfe | 1245 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1246 | len = TYPE_LENGTH (arg_type); |
1247 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1248 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1249 | val = value_contents_writeable (args[argnum]); |
2dd604e7 RE |
1250 | |
1251 | /* If the argument is a pointer to a function, and it is a | |
1252 | Thumb function, create a LOCAL copy of the value and set | |
1253 | the THUMB bit in it. */ | |
1254 | if (TYPE_CODE_PTR == typecode | |
1255 | && target_type != NULL | |
1256 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1257 | { | |
7c0b4a20 | 1258 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1259 | if (arm_pc_is_thumb (regval)) |
1260 | { | |
1261 | val = alloca (len); | |
fbd9dcd3 | 1262 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1263 | } |
1264 | } | |
1265 | ||
1266 | /* Copy the argument to general registers or the stack in | |
1267 | register-sized pieces. Large arguments are split between | |
1268 | registers and stack. */ | |
1269 | while (len > 0) | |
1270 | { | |
b1e29e33 | 1271 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1272 | |
1273 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1274 | { | |
1275 | /* The argument is being passed in a general purpose | |
1276 | register. */ | |
7c0b4a20 | 1277 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1278 | if (arm_debug) |
1279 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1280 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1281 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1282 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1283 | argreg++; | |
1284 | } | |
1285 | else | |
1286 | { | |
1287 | /* Push the arguments onto the stack. */ | |
1288 | if (arm_debug) | |
1289 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1290 | argnum, nstack); | |
b1e29e33 AC |
1291 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1292 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1293 | } |
1294 | ||
1295 | len -= partial_len; | |
1296 | val += partial_len; | |
1297 | } | |
1298 | } | |
1299 | /* If we have an odd number of words to push, then decrement the stack | |
1300 | by one word now, so first stack argument will be dword aligned. */ | |
1301 | if (nstack & 4) | |
1302 | sp -= 4; | |
1303 | ||
1304 | while (si) | |
1305 | { | |
1306 | sp -= si->len; | |
1307 | write_memory (sp, si->data, si->len); | |
1308 | si = pop_stack_item (si); | |
1309 | } | |
1310 | ||
1311 | /* Finally, update teh SP register. */ | |
1312 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1313 | ||
1314 | return sp; | |
1315 | } | |
1316 | ||
c906108c | 1317 | static void |
ed9a39eb | 1318 | print_fpu_flags (int flags) |
c906108c | 1319 | { |
c5aa993b JM |
1320 | if (flags & (1 << 0)) |
1321 | fputs ("IVO ", stdout); | |
1322 | if (flags & (1 << 1)) | |
1323 | fputs ("DVZ ", stdout); | |
1324 | if (flags & (1 << 2)) | |
1325 | fputs ("OFL ", stdout); | |
1326 | if (flags & (1 << 3)) | |
1327 | fputs ("UFL ", stdout); | |
1328 | if (flags & (1 << 4)) | |
1329 | fputs ("INX ", stdout); | |
1330 | putchar ('\n'); | |
c906108c SS |
1331 | } |
1332 | ||
5e74b15c RE |
1333 | /* Print interesting information about the floating point processor |
1334 | (if present) or emulator. */ | |
34e8f22d | 1335 | static void |
d855c300 | 1336 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1337 | struct frame_info *frame, const char *args) |
c906108c | 1338 | { |
52f0bd74 | 1339 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1340 | int type; |
1341 | ||
1342 | type = (status >> 24) & 127; | |
edefbb7c AC |
1343 | if (status & (1 << 31)) |
1344 | printf (_("Hardware FPU type %d\n"), type); | |
1345 | else | |
1346 | printf (_("Software FPU type %d\n"), type); | |
1347 | /* i18n: [floating point unit] mask */ | |
1348 | fputs (_("mask: "), stdout); | |
c5aa993b | 1349 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1350 | /* i18n: [floating point unit] flags */ |
1351 | fputs (_("flags: "), stdout); | |
c5aa993b | 1352 | print_fpu_flags (status); |
c906108c SS |
1353 | } |
1354 | ||
34e8f22d RE |
1355 | /* Return the GDB type object for the "standard" data type of data in |
1356 | register N. */ | |
1357 | ||
1358 | static struct type * | |
7a5ea0d4 | 1359 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1360 | { |
34e8f22d | 1361 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1362 | { |
d7449b42 | 1363 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1364 | return builtin_type_arm_ext_big; |
1365 | else | |
1366 | return builtin_type_arm_ext_littlebyte_bigword; | |
1367 | } | |
1368 | else | |
1369 | return builtin_type_int32; | |
1370 | } | |
1371 | ||
34e8f22d RE |
1372 | /* Index within `registers' of the first byte of the space for |
1373 | register N. */ | |
1374 | ||
1375 | static int | |
1376 | arm_register_byte (int regnum) | |
1377 | { | |
1378 | if (regnum < ARM_F0_REGNUM) | |
7a5ea0d4 | 1379 | return regnum * INT_REGISTER_SIZE; |
34e8f22d | 1380 | else if (regnum < ARM_PS_REGNUM) |
7a5ea0d4 DJ |
1381 | return (NUM_GREGS * INT_REGISTER_SIZE |
1382 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); | |
34e8f22d | 1383 | else |
7a5ea0d4 DJ |
1384 | return (NUM_GREGS * INT_REGISTER_SIZE |
1385 | + NUM_FREGS * FP_REGISTER_SIZE | |
34e8f22d RE |
1386 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
1387 | } | |
1388 | ||
26216b98 AC |
1389 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1390 | static int | |
1391 | arm_register_sim_regno (int regnum) | |
1392 | { | |
1393 | int reg = regnum; | |
1394 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1395 | ||
1396 | if (reg < NUM_GREGS) | |
1397 | return SIM_ARM_R0_REGNUM + reg; | |
1398 | reg -= NUM_GREGS; | |
1399 | ||
1400 | if (reg < NUM_FREGS) | |
1401 | return SIM_ARM_FP0_REGNUM + reg; | |
1402 | reg -= NUM_FREGS; | |
1403 | ||
1404 | if (reg < NUM_SREGS) | |
1405 | return SIM_ARM_FPS_REGNUM + reg; | |
1406 | reg -= NUM_SREGS; | |
1407 | ||
edefbb7c | 1408 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1409 | } |
34e8f22d | 1410 | |
a37b3cc0 AC |
1411 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1412 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1413 | It is thought that this is is the floating-point register format on | |
1414 | little-endian systems. */ | |
c906108c | 1415 | |
ed9a39eb | 1416 | static void |
b508a996 RE |
1417 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1418 | void *dbl) | |
c906108c | 1419 | { |
a37b3cc0 | 1420 | DOUBLEST d; |
d7449b42 | 1421 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1422 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1423 | else | |
1424 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1425 | ptr, &d); | |
b508a996 | 1426 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1427 | } |
1428 | ||
34e8f22d | 1429 | static void |
b508a996 | 1430 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1431 | { |
a37b3cc0 | 1432 | DOUBLEST d; |
b508a996 | 1433 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1434 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1435 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1436 | else | |
1437 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1438 | &d, dbl); | |
c906108c | 1439 | } |
ed9a39eb | 1440 | |
c906108c | 1441 | static int |
ed9a39eb | 1442 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1443 | { |
1444 | if (cond == INST_AL || cond == INST_NV) | |
1445 | return 1; | |
1446 | ||
1447 | switch (cond) | |
1448 | { | |
1449 | case INST_EQ: | |
1450 | return ((status_reg & FLAG_Z) != 0); | |
1451 | case INST_NE: | |
1452 | return ((status_reg & FLAG_Z) == 0); | |
1453 | case INST_CS: | |
1454 | return ((status_reg & FLAG_C) != 0); | |
1455 | case INST_CC: | |
1456 | return ((status_reg & FLAG_C) == 0); | |
1457 | case INST_MI: | |
1458 | return ((status_reg & FLAG_N) != 0); | |
1459 | case INST_PL: | |
1460 | return ((status_reg & FLAG_N) == 0); | |
1461 | case INST_VS: | |
1462 | return ((status_reg & FLAG_V) != 0); | |
1463 | case INST_VC: | |
1464 | return ((status_reg & FLAG_V) == 0); | |
1465 | case INST_HI: | |
1466 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1467 | case INST_LS: | |
1468 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1469 | case INST_GE: | |
1470 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1471 | case INST_LT: | |
1472 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1473 | case INST_GT: | |
1474 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1475 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1476 | case INST_LE: |
1477 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1478 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1479 | } |
1480 | return 1; | |
1481 | } | |
1482 | ||
9512d7fd | 1483 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1484 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1485 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1486 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1487 | #define sbits(obj,st,fn) \ | |
1488 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1489 | #define BranchDest(addr,instr) \ | |
1490 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1491 | #define ARM_PC_32 1 | |
1492 | ||
1493 | static unsigned long | |
ed9a39eb JM |
1494 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1495 | unsigned long status_reg) | |
c906108c SS |
1496 | { |
1497 | unsigned long res, shift; | |
1498 | int rm = bits (inst, 0, 3); | |
1499 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1500 | |
1501 | if (bit (inst, 4)) | |
c906108c SS |
1502 | { |
1503 | int rs = bits (inst, 8, 11); | |
1504 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1505 | } | |
1506 | else | |
1507 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1508 | |
1509 | res = (rm == 15 | |
c906108c | 1510 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1511 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1512 | : read_register (rm)); |
1513 | ||
1514 | switch (shifttype) | |
1515 | { | |
c5aa993b | 1516 | case 0: /* LSL */ |
c906108c SS |
1517 | res = shift >= 32 ? 0 : res << shift; |
1518 | break; | |
c5aa993b JM |
1519 | |
1520 | case 1: /* LSR */ | |
c906108c SS |
1521 | res = shift >= 32 ? 0 : res >> shift; |
1522 | break; | |
1523 | ||
c5aa993b JM |
1524 | case 2: /* ASR */ |
1525 | if (shift >= 32) | |
1526 | shift = 31; | |
c906108c SS |
1527 | res = ((res & 0x80000000L) |
1528 | ? ~((~res) >> shift) : res >> shift); | |
1529 | break; | |
1530 | ||
c5aa993b | 1531 | case 3: /* ROR/RRX */ |
c906108c SS |
1532 | shift &= 31; |
1533 | if (shift == 0) | |
1534 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1535 | else | |
c5aa993b | 1536 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1537 | break; |
1538 | } | |
1539 | ||
1540 | return res & 0xffffffff; | |
1541 | } | |
1542 | ||
c906108c SS |
1543 | /* Return number of 1-bits in VAL. */ |
1544 | ||
1545 | static int | |
ed9a39eb | 1546 | bitcount (unsigned long val) |
c906108c SS |
1547 | { |
1548 | int nbits; | |
1549 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1550 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1551 | return nbits; |
1552 | } | |
1553 | ||
34e8f22d | 1554 | CORE_ADDR |
ed9a39eb | 1555 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1556 | { |
c5aa993b | 1557 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1558 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1559 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1560 | unsigned long offset; |
1561 | ||
1562 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1563 | { | |
1564 | CORE_ADDR sp; | |
1565 | ||
1566 | /* Fetch the saved PC from the stack. It's stored above | |
1567 | all of the other registers. */ | |
b1e29e33 | 1568 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1569 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1570 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1571 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1572 | if (nextpc == pc) | |
edefbb7c | 1573 | error (_("Infinite loop detected")); |
c906108c SS |
1574 | } |
1575 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1576 | { | |
34e8f22d | 1577 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1578 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1579 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1580 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1581 | } | |
1582 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1583 | { | |
1584 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1585 | } | |
aa17d93e | 1586 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c SS |
1587 | { |
1588 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1589 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1590 | nextpc = pc_val + offset; |
aa17d93e DJ |
1591 | /* For BLX make sure to clear the low bits. */ |
1592 | if (bits (inst2, 11, 12) == 1) | |
1593 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1594 | } |
aa17d93e | 1595 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1596 | { |
1597 | if (bits (inst1, 3, 6) == 0x0f) | |
1598 | nextpc = pc_val; | |
1599 | else | |
1600 | nextpc = read_register (bits (inst1, 3, 6)); | |
1601 | ||
1602 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1603 | if (nextpc == pc) | |
edefbb7c | 1604 | error (_("Infinite loop detected")); |
9498281f | 1605 | } |
c906108c SS |
1606 | |
1607 | return nextpc; | |
1608 | } | |
1609 | ||
34e8f22d | 1610 | CORE_ADDR |
ed9a39eb | 1611 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1612 | { |
1613 | unsigned long pc_val; | |
1614 | unsigned long this_instr; | |
1615 | unsigned long status; | |
1616 | CORE_ADDR nextpc; | |
1617 | ||
1618 | if (arm_pc_is_thumb (pc)) | |
1619 | return thumb_get_next_pc (pc); | |
1620 | ||
1621 | pc_val = (unsigned long) pc; | |
1622 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1623 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1624 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1625 | |
1626 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1627 | { | |
1628 | switch (bits (this_instr, 24, 27)) | |
1629 | { | |
c5aa993b | 1630 | case 0x0: |
94c30b78 | 1631 | case 0x1: /* data processing */ |
c5aa993b JM |
1632 | case 0x2: |
1633 | case 0x3: | |
c906108c SS |
1634 | { |
1635 | unsigned long operand1, operand2, result = 0; | |
1636 | unsigned long rn; | |
1637 | int c; | |
c5aa993b | 1638 | |
c906108c SS |
1639 | if (bits (this_instr, 12, 15) != 15) |
1640 | break; | |
1641 | ||
1642 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1643 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1644 | error (_("Invalid update to pc in instruction")); |
c906108c | 1645 | |
9498281f DJ |
1646 | /* BX <reg>, BLX <reg> */ |
1647 | if (bits (this_instr, 4, 28) == 0x12fff1 | |
1648 | || bits (this_instr, 4, 28) == 0x12fff3) | |
1649 | { | |
1650 | rn = bits (this_instr, 0, 3); | |
1651 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1652 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1653 | ||
1654 | if (nextpc == pc) | |
edefbb7c | 1655 | error (_("Infinite loop detected")); |
9498281f DJ |
1656 | |
1657 | return nextpc; | |
1658 | } | |
1659 | ||
c906108c SS |
1660 | /* Multiply into PC */ |
1661 | c = (status & FLAG_C) ? 1 : 0; | |
1662 | rn = bits (this_instr, 16, 19); | |
1663 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1664 | |
c906108c SS |
1665 | if (bit (this_instr, 25)) |
1666 | { | |
1667 | unsigned long immval = bits (this_instr, 0, 7); | |
1668 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1669 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1670 | & 0xffffffff; | |
c906108c | 1671 | } |
c5aa993b | 1672 | else /* operand 2 is a shifted register */ |
c906108c | 1673 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1674 | |
c906108c SS |
1675 | switch (bits (this_instr, 21, 24)) |
1676 | { | |
c5aa993b | 1677 | case 0x0: /*and */ |
c906108c SS |
1678 | result = operand1 & operand2; |
1679 | break; | |
1680 | ||
c5aa993b | 1681 | case 0x1: /*eor */ |
c906108c SS |
1682 | result = operand1 ^ operand2; |
1683 | break; | |
1684 | ||
c5aa993b | 1685 | case 0x2: /*sub */ |
c906108c SS |
1686 | result = operand1 - operand2; |
1687 | break; | |
1688 | ||
c5aa993b | 1689 | case 0x3: /*rsb */ |
c906108c SS |
1690 | result = operand2 - operand1; |
1691 | break; | |
1692 | ||
c5aa993b | 1693 | case 0x4: /*add */ |
c906108c SS |
1694 | result = operand1 + operand2; |
1695 | break; | |
1696 | ||
c5aa993b | 1697 | case 0x5: /*adc */ |
c906108c SS |
1698 | result = operand1 + operand2 + c; |
1699 | break; | |
1700 | ||
c5aa993b | 1701 | case 0x6: /*sbc */ |
c906108c SS |
1702 | result = operand1 - operand2 + c; |
1703 | break; | |
1704 | ||
c5aa993b | 1705 | case 0x7: /*rsc */ |
c906108c SS |
1706 | result = operand2 - operand1 + c; |
1707 | break; | |
1708 | ||
c5aa993b JM |
1709 | case 0x8: |
1710 | case 0x9: | |
1711 | case 0xa: | |
1712 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1713 | result = (unsigned long) nextpc; |
1714 | break; | |
1715 | ||
c5aa993b | 1716 | case 0xc: /*orr */ |
c906108c SS |
1717 | result = operand1 | operand2; |
1718 | break; | |
1719 | ||
c5aa993b | 1720 | case 0xd: /*mov */ |
c906108c SS |
1721 | /* Always step into a function. */ |
1722 | result = operand2; | |
c5aa993b | 1723 | break; |
c906108c | 1724 | |
c5aa993b | 1725 | case 0xe: /*bic */ |
c906108c SS |
1726 | result = operand1 & ~operand2; |
1727 | break; | |
1728 | ||
c5aa993b | 1729 | case 0xf: /*mvn */ |
c906108c SS |
1730 | result = ~operand2; |
1731 | break; | |
1732 | } | |
1733 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1734 | ||
1735 | if (nextpc == pc) | |
edefbb7c | 1736 | error (_("Infinite loop detected")); |
c906108c SS |
1737 | break; |
1738 | } | |
c5aa993b JM |
1739 | |
1740 | case 0x4: | |
1741 | case 0x5: /* data transfer */ | |
1742 | case 0x6: | |
1743 | case 0x7: | |
c906108c SS |
1744 | if (bit (this_instr, 20)) |
1745 | { | |
1746 | /* load */ | |
1747 | if (bits (this_instr, 12, 15) == 15) | |
1748 | { | |
1749 | /* rd == pc */ | |
c5aa993b | 1750 | unsigned long rn; |
c906108c | 1751 | unsigned long base; |
c5aa993b | 1752 | |
c906108c | 1753 | if (bit (this_instr, 22)) |
edefbb7c | 1754 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1755 | |
1756 | /* byte write to PC */ | |
1757 | rn = bits (this_instr, 16, 19); | |
1758 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1759 | if (bit (this_instr, 24)) | |
1760 | { | |
1761 | /* pre-indexed */ | |
1762 | int c = (status & FLAG_C) ? 1 : 0; | |
1763 | unsigned long offset = | |
c5aa993b | 1764 | (bit (this_instr, 25) |
ed9a39eb | 1765 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1766 | : bits (this_instr, 0, 11)); |
c906108c SS |
1767 | |
1768 | if (bit (this_instr, 23)) | |
1769 | base += offset; | |
1770 | else | |
1771 | base -= offset; | |
1772 | } | |
c5aa993b | 1773 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1774 | 4); |
c5aa993b | 1775 | |
c906108c SS |
1776 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1777 | ||
1778 | if (nextpc == pc) | |
edefbb7c | 1779 | error (_("Infinite loop detected")); |
c906108c SS |
1780 | } |
1781 | } | |
1782 | break; | |
c5aa993b JM |
1783 | |
1784 | case 0x8: | |
1785 | case 0x9: /* block transfer */ | |
c906108c SS |
1786 | if (bit (this_instr, 20)) |
1787 | { | |
1788 | /* LDM */ | |
1789 | if (bit (this_instr, 15)) | |
1790 | { | |
1791 | /* loading pc */ | |
1792 | int offset = 0; | |
1793 | ||
1794 | if (bit (this_instr, 23)) | |
1795 | { | |
1796 | /* up */ | |
1797 | unsigned long reglist = bits (this_instr, 0, 14); | |
1798 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1799 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1800 | offset += 4; |
1801 | } | |
1802 | else if (bit (this_instr, 24)) | |
1803 | offset = -4; | |
c5aa993b | 1804 | |
c906108c | 1805 | { |
c5aa993b JM |
1806 | unsigned long rn_val = |
1807 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1808 | nextpc = |
1809 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1810 | + offset), |
c906108c SS |
1811 | 4); |
1812 | } | |
1813 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1814 | if (nextpc == pc) | |
edefbb7c | 1815 | error (_("Infinite loop detected")); |
c906108c SS |
1816 | } |
1817 | } | |
1818 | break; | |
c5aa993b JM |
1819 | |
1820 | case 0xb: /* branch & link */ | |
1821 | case 0xa: /* branch */ | |
c906108c SS |
1822 | { |
1823 | nextpc = BranchDest (pc, this_instr); | |
1824 | ||
9498281f DJ |
1825 | /* BLX */ |
1826 | if (bits (this_instr, 28, 31) == INST_NV) | |
1827 | nextpc |= bit (this_instr, 24) << 1; | |
1828 | ||
c906108c SS |
1829 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1830 | if (nextpc == pc) | |
edefbb7c | 1831 | error (_("Infinite loop detected")); |
c906108c SS |
1832 | break; |
1833 | } | |
c5aa993b JM |
1834 | |
1835 | case 0xc: | |
1836 | case 0xd: | |
1837 | case 0xe: /* coproc ops */ | |
1838 | case 0xf: /* SWI */ | |
c906108c SS |
1839 | break; |
1840 | ||
1841 | default: | |
edefbb7c | 1842 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1843 | return (pc); |
1844 | } | |
1845 | } | |
1846 | ||
1847 | return nextpc; | |
1848 | } | |
1849 | ||
9512d7fd FN |
1850 | /* single_step() is called just before we want to resume the inferior, |
1851 | if we want to single-step it but there is no hardware or kernel | |
1852 | single-step support. We find the target of the coming instruction | |
1853 | and breakpoint it. | |
1854 | ||
94c30b78 MS |
1855 | single_step() is also called just after the inferior stops. If we |
1856 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1857 | |
34e8f22d RE |
1858 | static void |
1859 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1860 | { |
b8d5e71d | 1861 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
1862 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
1863 | ||
1864 | if (insert_bpt) | |
1865 | { | |
34e8f22d | 1866 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 1867 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1868 | } |
1869 | else | |
80fcf3f0 | 1870 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1871 | } |
9512d7fd | 1872 | |
c906108c SS |
1873 | #include "bfd-in2.h" |
1874 | #include "libcoff.h" | |
1875 | ||
1876 | static int | |
ed9a39eb | 1877 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1878 | { |
1879 | if (arm_pc_is_thumb (memaddr)) | |
1880 | { | |
c5aa993b JM |
1881 | static asymbol *asym; |
1882 | static combined_entry_type ce; | |
1883 | static struct coff_symbol_struct csym; | |
27cddce2 | 1884 | static struct bfd fake_bfd; |
c5aa993b | 1885 | static bfd_target fake_target; |
c906108c SS |
1886 | |
1887 | if (csym.native == NULL) | |
1888 | { | |
da3c6d4a MS |
1889 | /* Create a fake symbol vector containing a Thumb symbol. |
1890 | This is solely so that the code in print_insn_little_arm() | |
1891 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1892 | the presence of a Thumb symbol and switch to decoding | |
1893 | Thumb instructions. */ | |
c5aa993b JM |
1894 | |
1895 | fake_target.flavour = bfd_target_coff_flavour; | |
1896 | fake_bfd.xvec = &fake_target; | |
c906108c | 1897 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1898 | csym.native = &ce; |
1899 | csym.symbol.the_bfd = &fake_bfd; | |
1900 | csym.symbol.name = "fake"; | |
1901 | asym = (asymbol *) & csym; | |
c906108c | 1902 | } |
c5aa993b | 1903 | |
c906108c | 1904 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1905 | info->symbols = &asym; |
c906108c SS |
1906 | } |
1907 | else | |
1908 | info->symbols = NULL; | |
c5aa993b | 1909 | |
d7449b42 | 1910 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1911 | return print_insn_big_arm (memaddr, info); |
1912 | else | |
1913 | return print_insn_little_arm (memaddr, info); | |
1914 | } | |
1915 | ||
66e810cd RE |
1916 | /* The following define instruction sequences that will cause ARM |
1917 | cpu's to take an undefined instruction trap. These are used to | |
1918 | signal a breakpoint to GDB. | |
1919 | ||
1920 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1921 | modes. A different instruction is required for each mode. The ARM | |
1922 | cpu's can also be big or little endian. Thus four different | |
1923 | instructions are needed to support all cases. | |
1924 | ||
1925 | Note: ARMv4 defines several new instructions that will take the | |
1926 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1927 | not in fact add the new instructions. The new undefined | |
1928 | instructions in ARMv4 are all instructions that had no defined | |
1929 | behaviour in earlier chips. There is no guarantee that they will | |
1930 | raise an exception, but may be treated as NOP's. In practice, it | |
1931 | may only safe to rely on instructions matching: | |
1932 | ||
1933 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1934 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1935 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1936 | ||
1937 | Even this may only true if the condition predicate is true. The | |
1938 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1939 | ||
1940 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1941 | and NetBSD all use a software interrupt rather than an undefined | |
1942 | instruction to force a trap. This can be handled by by the | |
1943 | abi-specific code during establishment of the gdbarch vector. */ | |
1944 | ||
1945 | ||
d7b486e7 RE |
1946 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1947 | override these definitions. */ | |
66e810cd RE |
1948 | #ifndef ARM_LE_BREAKPOINT |
1949 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
1950 | #endif | |
1951 | #ifndef ARM_BE_BREAKPOINT | |
1952 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1953 | #endif | |
1954 | #ifndef THUMB_LE_BREAKPOINT | |
1955 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1956 | #endif | |
1957 | #ifndef THUMB_BE_BREAKPOINT | |
1958 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1959 | #endif | |
1960 | ||
1961 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
1962 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
1963 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1964 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1965 | ||
34e8f22d RE |
1966 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
1967 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
1968 | breakpoint should be used. It returns a pointer to a string of |
1969 | bytes that encode a breakpoint instruction, stores the length of | |
1970 | the string to *lenptr, and adjusts the program counter (if | |
1971 | necessary) to point to the actual memory location where the | |
c906108c SS |
1972 | breakpoint should be inserted. */ |
1973 | ||
34e8f22d RE |
1974 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
1975 | breakpoints and storing their handles instread of what was in | |
1976 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 1977 | otherwise remote-rdp will have to change. */ |
34e8f22d | 1978 | |
ab89facf | 1979 | static const unsigned char * |
ed9a39eb | 1980 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 1981 | { |
66e810cd RE |
1982 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1983 | ||
4bf7064c | 1984 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 1985 | { |
66e810cd RE |
1986 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
1987 | *lenptr = tdep->thumb_breakpoint_size; | |
1988 | return tdep->thumb_breakpoint; | |
c906108c SS |
1989 | } |
1990 | else | |
1991 | { | |
66e810cd RE |
1992 | *lenptr = tdep->arm_breakpoint_size; |
1993 | return tdep->arm_breakpoint; | |
c906108c SS |
1994 | } |
1995 | } | |
ed9a39eb JM |
1996 | |
1997 | /* Extract from an array REGBUF containing the (raw) register state a | |
1998 | function return value of type TYPE, and copy that, in virtual | |
1999 | format, into VALBUF. */ | |
2000 | ||
34e8f22d | 2001 | static void |
ed9a39eb | 2002 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2003 | struct regcache *regs, |
2004 | void *dst) | |
ed9a39eb | 2005 | { |
b508a996 RE |
2006 | bfd_byte *valbuf = dst; |
2007 | ||
ed9a39eb | 2008 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2009 | { |
fd50bc42 | 2010 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2011 | { |
2012 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2013 | { |
2014 | /* The value is in register F0 in internal format. We need to | |
2015 | extract the raw value and then convert it to the desired | |
2016 | internal type. */ | |
7a5ea0d4 | 2017 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2018 | |
2019 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2020 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2021 | valbuf); | |
2022 | } | |
08216dd7 RE |
2023 | break; |
2024 | ||
fd50bc42 | 2025 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2026 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2027 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2028 | if (TYPE_LENGTH (type) > 4) | |
2029 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2030 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2031 | break; |
2032 | ||
2033 | default: | |
2034 | internal_error | |
2035 | (__FILE__, __LINE__, | |
edefbb7c | 2036 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2037 | break; |
2038 | } | |
2039 | } | |
b508a996 RE |
2040 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2041 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2042 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2043 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2044 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2045 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2046 | { | |
2047 | /* If the the type is a plain integer, then the access is | |
2048 | straight-forward. Otherwise we have to play around a bit more. */ | |
2049 | int len = TYPE_LENGTH (type); | |
2050 | int regno = ARM_A1_REGNUM; | |
2051 | ULONGEST tmp; | |
2052 | ||
2053 | while (len > 0) | |
2054 | { | |
2055 | /* By using store_unsigned_integer we avoid having to do | |
2056 | anything special for small big-endian values. */ | |
2057 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2058 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2059 | (len > INT_REGISTER_SIZE |
2060 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2061 | tmp); |
7a5ea0d4 DJ |
2062 | len -= INT_REGISTER_SIZE; |
2063 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2064 | } |
2065 | } | |
ed9a39eb | 2066 | else |
b508a996 RE |
2067 | { |
2068 | /* For a structure or union the behaviour is as if the value had | |
2069 | been stored to word-aligned memory and then loaded into | |
2070 | registers with 32-bit load instruction(s). */ | |
2071 | int len = TYPE_LENGTH (type); | |
2072 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2073 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2074 | |
2075 | while (len > 0) | |
2076 | { | |
2077 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2078 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2079 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2080 | len -= INT_REGISTER_SIZE; | |
2081 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2082 | } |
2083 | } | |
34e8f22d RE |
2084 | } |
2085 | ||
67255d04 RE |
2086 | /* Extract from an array REGBUF containing the (raw) register state |
2087 | the address in which a function should return its structure value. */ | |
2088 | ||
2089 | static CORE_ADDR | |
95f95911 | 2090 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2091 | { |
95f95911 MS |
2092 | ULONGEST ret; |
2093 | ||
2094 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2095 | return ret; | |
67255d04 RE |
2096 | } |
2097 | ||
2098 | /* Will a function return an aggregate type in memory or in a | |
2099 | register? Return 0 if an aggregate type can be returned in a | |
2100 | register, 1 if it must be returned in memory. */ | |
2101 | ||
2102 | static int | |
2103 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2104 | { | |
2105 | int nRc; | |
52f0bd74 | 2106 | enum type_code code; |
67255d04 | 2107 | |
44e1a9eb DJ |
2108 | CHECK_TYPEDEF (type); |
2109 | ||
67255d04 RE |
2110 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2111 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2112 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2113 | offset of each addressable subfield must be zero. Note that bit | |
2114 | fields are not addressable, and all addressable subfields of | |
2115 | unions always start at offset zero. | |
67255d04 RE |
2116 | |
2117 | This function is based on the behaviour of GCC 2.95.1. | |
2118 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2119 | ||
2120 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2121 | parameters correctly for a function returning the following | |
2122 | structure: struct { float f;}; This should be returned in memory, | |
2123 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2124 | know of any way to detect if a function like the above has been | |
2125 | compiled with the correct calling convention. */ | |
2126 | ||
2127 | /* All aggregate types that won't fit in a register must be returned | |
2128 | in memory. */ | |
b1e29e33 | 2129 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2130 | { |
2131 | return 1; | |
2132 | } | |
2133 | ||
2134 | /* The only aggregate types that can be returned in a register are | |
2135 | structs and unions. Arrays must be returned in memory. */ | |
2136 | code = TYPE_CODE (type); | |
2137 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2138 | { | |
2139 | return 1; | |
2140 | } | |
2141 | ||
2142 | /* Assume all other aggregate types can be returned in a register. | |
2143 | Run a check for structures, unions and arrays. */ | |
2144 | nRc = 0; | |
2145 | ||
2146 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2147 | { | |
2148 | int i; | |
2149 | /* Need to check if this struct/union is "integer" like. For | |
2150 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2151 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2152 | subfield must be zero. Note that bit fields are not | |
2153 | addressable, and unions always start at offset zero. If any | |
2154 | of the subfields is a floating point type, the struct/union | |
2155 | cannot be an integer type. */ | |
67255d04 RE |
2156 | |
2157 | /* For each field in the object, check: | |
2158 | 1) Is it FP? --> yes, nRc = 1; | |
2159 | 2) Is it addressable (bitpos != 0) and | |
2160 | not packed (bitsize == 0)? | |
2161 | --> yes, nRc = 1 | |
2162 | */ | |
2163 | ||
2164 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2165 | { | |
2166 | enum type_code field_type_code; | |
44e1a9eb | 2167 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2168 | |
2169 | /* Is it a floating point type field? */ | |
2170 | if (field_type_code == TYPE_CODE_FLT) | |
2171 | { | |
2172 | nRc = 1; | |
2173 | break; | |
2174 | } | |
2175 | ||
2176 | /* If bitpos != 0, then we have to care about it. */ | |
2177 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2178 | { | |
2179 | /* Bitfields are not addressable. If the field bitsize is | |
2180 | zero, then the field is not packed. Hence it cannot be | |
2181 | a bitfield or any other packed type. */ | |
2182 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2183 | { | |
2184 | nRc = 1; | |
2185 | break; | |
2186 | } | |
2187 | } | |
2188 | } | |
2189 | } | |
2190 | ||
2191 | return nRc; | |
2192 | } | |
2193 | ||
34e8f22d RE |
2194 | /* Write into appropriate registers a function return value of type |
2195 | TYPE, given in virtual format. */ | |
2196 | ||
2197 | static void | |
b508a996 RE |
2198 | arm_store_return_value (struct type *type, struct regcache *regs, |
2199 | const void *src) | |
34e8f22d | 2200 | { |
b508a996 RE |
2201 | const bfd_byte *valbuf = src; |
2202 | ||
34e8f22d RE |
2203 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2204 | { | |
7a5ea0d4 | 2205 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2206 | |
fd50bc42 | 2207 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2208 | { |
2209 | case ARM_FLOAT_FPA: | |
2210 | ||
b508a996 RE |
2211 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2212 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2213 | break; |
2214 | ||
fd50bc42 | 2215 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2216 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2217 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2218 | if (TYPE_LENGTH (type) > 4) | |
2219 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2220 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2221 | break; |
2222 | ||
2223 | default: | |
2224 | internal_error | |
2225 | (__FILE__, __LINE__, | |
edefbb7c | 2226 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2227 | break; |
2228 | } | |
34e8f22d | 2229 | } |
b508a996 RE |
2230 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2231 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2232 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2233 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2234 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2235 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2236 | { | |
2237 | if (TYPE_LENGTH (type) <= 4) | |
2238 | { | |
2239 | /* Values of one word or less are zero/sign-extended and | |
2240 | returned in r0. */ | |
7a5ea0d4 | 2241 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2242 | LONGEST val = unpack_long (type, valbuf); |
2243 | ||
7a5ea0d4 | 2244 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2245 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2246 | } | |
2247 | else | |
2248 | { | |
2249 | /* Integral values greater than one word are stored in consecutive | |
2250 | registers starting with r0. This will always be a multiple of | |
2251 | the regiser size. */ | |
2252 | int len = TYPE_LENGTH (type); | |
2253 | int regno = ARM_A1_REGNUM; | |
2254 | ||
2255 | while (len > 0) | |
2256 | { | |
2257 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2258 | len -= INT_REGISTER_SIZE; |
2259 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2260 | } |
2261 | } | |
2262 | } | |
34e8f22d | 2263 | else |
b508a996 RE |
2264 | { |
2265 | /* For a structure or union the behaviour is as if the value had | |
2266 | been stored to word-aligned memory and then loaded into | |
2267 | registers with 32-bit load instruction(s). */ | |
2268 | int len = TYPE_LENGTH (type); | |
2269 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2270 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2271 | |
2272 | while (len > 0) | |
2273 | { | |
2274 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2275 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2276 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2277 | len -= INT_REGISTER_SIZE; |
2278 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2279 | } |
2280 | } | |
34e8f22d RE |
2281 | } |
2282 | ||
9df628e0 RE |
2283 | static int |
2284 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2285 | { | |
2286 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2287 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2288 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2289 | ||
2290 | jb_addr = read_register (ARM_A1_REGNUM); | |
2291 | ||
2292 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2293 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2294 | return 0; |
2295 | ||
7a5ea0d4 | 2296 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2297 | return 1; |
2298 | } | |
2299 | ||
ed9a39eb | 2300 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2301 | |
2302 | int | |
ed9a39eb | 2303 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2304 | { |
2305 | CORE_ADDR start_addr; | |
2306 | ||
ed9a39eb JM |
2307 | /* Find the starting address of the function containing the PC. If |
2308 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2309 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2310 | &start_addr, NULL)) | |
c906108c SS |
2311 | return 0; |
2312 | ||
2313 | return strncmp (name, "_call_via_r", 11) == 0; | |
2314 | } | |
2315 | ||
ed9a39eb JM |
2316 | /* If PC is in a Thumb call or return stub, return the address of the |
2317 | target PC, which is in a register. The thunk functions are called | |
2318 | _called_via_xx, where x is the register name. The possible names | |
2319 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2320 | |
2321 | CORE_ADDR | |
ed9a39eb | 2322 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2323 | { |
c5aa993b | 2324 | char *name; |
c906108c SS |
2325 | CORE_ADDR start_addr; |
2326 | ||
2327 | /* Find the starting address and name of the function containing the PC. */ | |
2328 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2329 | return 0; | |
2330 | ||
2331 | /* Call thunks always start with "_call_via_". */ | |
2332 | if (strncmp (name, "_call_via_", 10) == 0) | |
2333 | { | |
ed9a39eb JM |
2334 | /* Use the name suffix to determine which register contains the |
2335 | target PC. */ | |
c5aa993b JM |
2336 | static char *table[15] = |
2337 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2338 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2339 | }; | |
c906108c SS |
2340 | int regno; |
2341 | ||
2342 | for (regno = 0; regno <= 14; regno++) | |
2343 | if (strcmp (&name[10], table[regno]) == 0) | |
2344 | return read_register (regno); | |
2345 | } | |
ed9a39eb | 2346 | |
c5aa993b | 2347 | return 0; /* not a stub */ |
c906108c SS |
2348 | } |
2349 | ||
afd7eef0 RE |
2350 | static void |
2351 | set_arm_command (char *args, int from_tty) | |
2352 | { | |
edefbb7c AC |
2353 | printf_unfiltered (_("\ |
2354 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2355 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2356 | } | |
2357 | ||
2358 | static void | |
2359 | show_arm_command (char *args, int from_tty) | |
2360 | { | |
26304000 | 2361 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2362 | } |
2363 | ||
fd50bc42 RE |
2364 | enum arm_float_model |
2365 | arm_get_fp_model (struct gdbarch *gdbarch) | |
2366 | { | |
2367 | if (arm_fp_model == ARM_FLOAT_AUTO) | |
2368 | return gdbarch_tdep (gdbarch)->fp_model; | |
2369 | ||
2370 | return arm_fp_model; | |
2371 | } | |
2372 | ||
2373 | static void | |
2374 | arm_set_fp (struct gdbarch *gdbarch) | |
2375 | { | |
2376 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); | |
2377 | ||
2378 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE | |
2379 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) | |
2380 | { | |
2381 | set_gdbarch_double_format (gdbarch, | |
2382 | &floatformat_ieee_double_littlebyte_bigword); | |
2383 | set_gdbarch_long_double_format | |
2384 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2385 | } | |
2386 | else | |
2387 | { | |
2388 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2389 | set_gdbarch_long_double_format (gdbarch, | |
2390 | &floatformat_ieee_double_little); | |
2391 | } | |
2392 | } | |
2393 | ||
2394 | static void | |
2395 | set_fp_model_sfunc (char *args, int from_tty, | |
2396 | struct cmd_list_element *c) | |
2397 | { | |
2398 | enum arm_float_model fp_model; | |
2399 | ||
2400 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2401 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2402 | { | |
2403 | arm_fp_model = fp_model; | |
2404 | break; | |
2405 | } | |
2406 | ||
2407 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2408 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2409 | current_fp_model); |
2410 | ||
2411 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2412 | arm_set_fp (current_gdbarch); | |
2413 | } | |
2414 | ||
2415 | static void | |
08546159 AC |
2416 | show_fp_model (struct ui_file *file, int from_tty, |
2417 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2418 | { |
2419 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2420 | ||
08546159 | 2421 | deprecated_show_value_hack (file, from_tty, c, value); |
fd50bc42 RE |
2422 | if (arm_fp_model == ARM_FLOAT_AUTO |
2423 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
edefbb7c AC |
2424 | /* i18n: "the default [floating point model] for the current ABI..." */ |
2425 | printf_filtered (_(" - the default for the current ABI is \"%s\".\n"), | |
fd50bc42 RE |
2426 | fp_model_strings[tdep->fp_model]); |
2427 | } | |
2428 | ||
afd7eef0 RE |
2429 | /* If the user changes the register disassembly style used for info |
2430 | register and other commands, we have to also switch the style used | |
2431 | in opcodes for disassembly output. This function is run in the "set | |
2432 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2433 | |
2434 | static void | |
afd7eef0 | 2435 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2436 | struct cmd_list_element *c) |
2437 | { | |
afd7eef0 | 2438 | set_disassembly_style (); |
bc90b915 FN |
2439 | } |
2440 | \f | |
966fbf70 | 2441 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2442 | static const char * |
34e8f22d | 2443 | arm_register_name (int i) |
966fbf70 RE |
2444 | { |
2445 | return arm_register_names[i]; | |
2446 | } | |
2447 | ||
bc90b915 | 2448 | static void |
afd7eef0 | 2449 | set_disassembly_style (void) |
bc90b915 FN |
2450 | { |
2451 | const char *setname, *setdesc, **regnames; | |
2452 | int numregs, j; | |
2453 | ||
afd7eef0 | 2454 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2455 | int current = 0; |
2456 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2457 | while ((disassembly_style != setname) |
2458 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2459 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2460 | current_option = current; | |
2461 | ||
94c30b78 | 2462 | /* Fill our copy. */ |
bc90b915 FN |
2463 | for (j = 0; j < numregs; j++) |
2464 | arm_register_names[j] = (char *) regnames[j]; | |
2465 | ||
94c30b78 | 2466 | /* Adjust case. */ |
34e8f22d | 2467 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2468 | { |
34e8f22d RE |
2469 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2470 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2471 | } |
2472 | else | |
2473 | { | |
34e8f22d RE |
2474 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2475 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2476 | } |
2477 | ||
94c30b78 | 2478 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2479 | set_arm_regname_option (current); |
2480 | } | |
2481 | ||
082fc60d RE |
2482 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2483 | function. */ | |
2484 | ||
2485 | static int | |
2486 | coff_sym_is_thumb (int val) | |
2487 | { | |
2488 | return (val == C_THUMBEXT || | |
2489 | val == C_THUMBSTAT || | |
2490 | val == C_THUMBEXTFUNC || | |
2491 | val == C_THUMBSTATFUNC || | |
2492 | val == C_THUMBLABEL); | |
2493 | } | |
2494 | ||
2495 | /* arm_coff_make_msymbol_special() | |
2496 | arm_elf_make_msymbol_special() | |
2497 | ||
2498 | These functions test whether the COFF or ELF symbol corresponds to | |
2499 | an address in thumb code, and set a "special" bit in a minimal | |
2500 | symbol to indicate that it does. */ | |
2501 | ||
34e8f22d | 2502 | static void |
082fc60d RE |
2503 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2504 | { | |
2505 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2506 | STT_ARM_TFUNC). */ | |
2507 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2508 | == STT_LOPROC) | |
2509 | MSYMBOL_SET_SPECIAL (msym); | |
2510 | } | |
2511 | ||
34e8f22d | 2512 | static void |
082fc60d RE |
2513 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2514 | { | |
2515 | if (coff_sym_is_thumb (val)) | |
2516 | MSYMBOL_SET_SPECIAL (msym); | |
2517 | } | |
2518 | ||
756fe439 DJ |
2519 | static void |
2520 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2521 | { | |
2522 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2523 | ||
2524 | /* If necessary, set the T bit. */ | |
2525 | if (arm_apcs_32) | |
2526 | { | |
2527 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2528 | if (arm_pc_is_thumb (pc)) | |
2529 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2530 | else | |
2531 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2532 | } | |
2533 | } | |
97e03143 | 2534 | \f |
70f80edf JT |
2535 | static enum gdb_osabi |
2536 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2537 | { |
70f80edf JT |
2538 | unsigned int elfosabi, eflags; |
2539 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2540 | |
70f80edf | 2541 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2542 | |
70f80edf | 2543 | switch (elfosabi) |
97e03143 | 2544 | { |
70f80edf JT |
2545 | case ELFOSABI_NONE: |
2546 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2547 | file are conforming to the base specification for that machine | |
2548 | (there are no OS-specific extensions). In order to determine the | |
2549 | real OS in use we must look for OS notes that have been added. */ | |
2550 | bfd_map_over_sections (abfd, | |
2551 | generic_elf_osabi_sniff_abi_tag_sections, | |
2552 | &osabi); | |
2553 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2554 | { |
70f80edf JT |
2555 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2556 | field for more information. */ | |
2557 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2558 | switch (eflags) | |
97e03143 | 2559 | { |
70f80edf JT |
2560 | case EF_ARM_EABI_VER1: |
2561 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2562 | break; |
2563 | ||
70f80edf JT |
2564 | case EF_ARM_EABI_VER2: |
2565 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2566 | break; |
2567 | ||
70f80edf JT |
2568 | case EF_ARM_EABI_UNKNOWN: |
2569 | /* Assume GNU tools. */ | |
2570 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2571 | break; |
2572 | ||
70f80edf JT |
2573 | default: |
2574 | internal_error (__FILE__, __LINE__, | |
edefbb7c AC |
2575 | _("\ |
2576 | arm_elf_osabi_sniffer: Unknown ARM EABI version 0x%x"), | |
2577 | eflags); | |
97e03143 RE |
2578 | } |
2579 | } | |
70f80edf | 2580 | break; |
97e03143 | 2581 | |
70f80edf JT |
2582 | case ELFOSABI_ARM: |
2583 | /* GNU tools use this value. Check note sections in this case, | |
2584 | as well. */ | |
97e03143 | 2585 | bfd_map_over_sections (abfd, |
70f80edf JT |
2586 | generic_elf_osabi_sniff_abi_tag_sections, |
2587 | &osabi); | |
2588 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2589 | { |
70f80edf JT |
2590 | /* Assume APCS ABI. */ |
2591 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2592 | } |
2593 | break; | |
2594 | ||
97e03143 | 2595 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2596 | osabi = GDB_OSABI_FREEBSD_ELF; |
2597 | break; | |
97e03143 | 2598 | |
70f80edf JT |
2599 | case ELFOSABI_NETBSD: |
2600 | osabi = GDB_OSABI_NETBSD_ELF; | |
2601 | break; | |
97e03143 | 2602 | |
70f80edf JT |
2603 | case ELFOSABI_LINUX: |
2604 | osabi = GDB_OSABI_LINUX; | |
2605 | break; | |
97e03143 RE |
2606 | } |
2607 | ||
70f80edf | 2608 | return osabi; |
97e03143 RE |
2609 | } |
2610 | ||
70f80edf | 2611 | \f |
da3c6d4a MS |
2612 | /* Initialize the current architecture based on INFO. If possible, |
2613 | re-use an architecture from ARCHES, which is a list of | |
2614 | architectures already created during this debugging session. | |
97e03143 | 2615 | |
da3c6d4a MS |
2616 | Called e.g. at program startup, when reading a core file, and when |
2617 | reading a binary file. */ | |
97e03143 | 2618 | |
39bbf761 RE |
2619 | static struct gdbarch * |
2620 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2621 | { | |
97e03143 | 2622 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2623 | struct gdbarch *gdbarch; |
2624 | ||
97e03143 | 2625 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2626 | |
4be87837 | 2627 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2628 | { |
4be87837 | 2629 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2630 | { |
4be87837 DJ |
2631 | case bfd_target_aout_flavour: |
2632 | /* Assume it's an old APCS-style ABI. */ | |
2633 | info.osabi = GDB_OSABI_ARM_APCS; | |
2634 | break; | |
97e03143 | 2635 | |
4be87837 DJ |
2636 | case bfd_target_coff_flavour: |
2637 | /* Assume it's an old APCS-style ABI. */ | |
2638 | /* XXX WinCE? */ | |
2639 | info.osabi = GDB_OSABI_ARM_APCS; | |
2640 | break; | |
97e03143 | 2641 | |
4be87837 DJ |
2642 | default: |
2643 | /* Leave it as "unknown". */ | |
50ceaba5 | 2644 | break; |
97e03143 RE |
2645 | } |
2646 | } | |
2647 | ||
4be87837 DJ |
2648 | /* If there is already a candidate, use it. */ |
2649 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2650 | if (arches != NULL) | |
2651 | return arches->gdbarch; | |
97e03143 RE |
2652 | |
2653 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2654 | gdbarch = gdbarch_alloc (&info, tdep); | |
2655 | ||
fd50bc42 RE |
2656 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
2657 | now, and we now provide a way for the user to force the model. So | |
2658 | default to the most useful variant. */ | |
2659 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
08216dd7 RE |
2660 | |
2661 | /* Breakpoints. */ | |
67255d04 RE |
2662 | switch (info.byte_order) |
2663 | { | |
2664 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2665 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2666 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2667 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2668 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2669 | ||
67255d04 RE |
2670 | break; |
2671 | ||
2672 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2673 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2674 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2675 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2676 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2677 | ||
67255d04 RE |
2678 | break; |
2679 | ||
2680 | default: | |
2681 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2682 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2683 | } |
2684 | ||
d7b486e7 RE |
2685 | /* On ARM targets char defaults to unsigned. */ |
2686 | set_gdbarch_char_signed (gdbarch, 0); | |
2687 | ||
9df628e0 | 2688 | /* This should be low enough for everything. */ |
97e03143 | 2689 | tdep->lowest_pc = 0x20; |
94c30b78 | 2690 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2691 | |
2dd604e7 | 2692 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2693 | |
756fe439 DJ |
2694 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2695 | ||
148754e5 | 2696 | /* Frame handling. */ |
eb5492fa DJ |
2697 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2698 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2699 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2700 | ||
eb5492fa | 2701 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2702 | |
34e8f22d RE |
2703 | /* Address manipulation. */ |
2704 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2705 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2706 | ||
34e8f22d RE |
2707 | /* Advance PC across function entry code. */ |
2708 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2709 | ||
2710 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2711 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2712 | |
2713 | /* The stack grows downward. */ | |
2714 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2715 | ||
2716 | /* Breakpoint manipulation. */ | |
2717 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2718 | |
2719 | /* Information about registers, etc. */ | |
2720 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2721 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2722 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2723 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
9c04cab7 | 2724 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
34e8f22d | 2725 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
7a5ea0d4 | 2726 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2727 | |
26216b98 AC |
2728 | /* Internal <-> external register number maps. */ |
2729 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2730 | ||
34e8f22d | 2731 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2732 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2733 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2734 | ||
2735 | /* Returning results. */ | |
b508a996 RE |
2736 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2737 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
b5622e8d | 2738 | set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention); |
74055713 | 2739 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); |
34e8f22d RE |
2740 | |
2741 | /* Single stepping. */ | |
2742 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2743 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2744 | ||
03d48a7d RE |
2745 | /* Disassembly. */ |
2746 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2747 | ||
34e8f22d RE |
2748 | /* Minsymbol frobbing. */ |
2749 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2750 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2751 | arm_coff_make_msymbol_special); | |
2752 | ||
97e03143 | 2753 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2754 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2755 | |
eb5492fa | 2756 | /* Add some default predicates. */ |
909cf6ea | 2757 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
eb5492fa | 2758 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); |
842e1f1e | 2759 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2760 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2761 | ||
97e03143 RE |
2762 | /* Now we have tuned the configuration, set a few final things, |
2763 | based on what the OS ABI has told us. */ | |
2764 | ||
9df628e0 RE |
2765 | if (tdep->jb_pc >= 0) |
2766 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2767 | ||
08216dd7 RE |
2768 | /* Floating point sizes and format. */ |
2769 | switch (info.byte_order) | |
2770 | { | |
2771 | case BFD_ENDIAN_BIG: | |
2772 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2773 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2774 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2775 | ||
2776 | break; | |
2777 | ||
2778 | case BFD_ENDIAN_LITTLE: | |
2779 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
fd50bc42 | 2780 | arm_set_fp (gdbarch); |
08216dd7 RE |
2781 | break; |
2782 | ||
2783 | default: | |
2784 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2785 | _("arm_gdbarch_init: bad byte order for float format")); |
08216dd7 RE |
2786 | } |
2787 | ||
39bbf761 RE |
2788 | return gdbarch; |
2789 | } | |
2790 | ||
97e03143 RE |
2791 | static void |
2792 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2793 | { | |
2794 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2795 | ||
2796 | if (tdep == NULL) | |
2797 | return; | |
2798 | ||
edefbb7c | 2799 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
2800 | (unsigned long) tdep->lowest_pc); |
2801 | } | |
2802 | ||
2803 | static void | |
2804 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2805 | struct gdbarch *gdbarch) | |
2806 | { | |
2807 | /* Place-holder. */ | |
2808 | } | |
2809 | ||
2810 | static void | |
2811 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2812 | struct gdbarch *gdbarch) | |
2813 | { | |
2814 | /* Place-holder. */ | |
2815 | } | |
2816 | ||
2817 | static void | |
2818 | arm_init_abi_apcs (struct gdbarch_info info, | |
2819 | struct gdbarch *gdbarch) | |
2820 | { | |
2821 | /* Place-holder. */ | |
2822 | } | |
2823 | ||
a78f21af AC |
2824 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
2825 | ||
c906108c | 2826 | void |
ed9a39eb | 2827 | _initialize_arm_tdep (void) |
c906108c | 2828 | { |
bc90b915 FN |
2829 | struct ui_file *stb; |
2830 | long length; | |
26304000 | 2831 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
2832 | const char *setname; |
2833 | const char *setdesc; | |
2834 | const char **regnames; | |
bc90b915 FN |
2835 | int numregs, i, j; |
2836 | static char *helptext; | |
edefbb7c AC |
2837 | char regdesc[1024], *rdptr = regdesc; |
2838 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 2839 | |
42cf1509 | 2840 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 2841 | |
70f80edf JT |
2842 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2843 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2844 | bfd_target_elf_flavour, | |
2845 | arm_elf_osabi_sniffer); | |
2846 | ||
97e03143 | 2847 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 2848 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 2849 | arm_init_abi_eabi_v1); |
05816f70 | 2850 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 2851 | arm_init_abi_eabi_v2); |
05816f70 | 2852 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 2853 | arm_init_abi_apcs); |
39bbf761 | 2854 | |
94c30b78 | 2855 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
2856 | num_disassembly_options = get_arm_regname_num_options (); |
2857 | ||
2858 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
2859 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 2860 | _("Various ARM-specific commands."), |
afd7eef0 RE |
2861 | &setarmcmdlist, "set arm ", 0, &setlist); |
2862 | ||
2863 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 2864 | _("Various ARM-specific commands."), |
afd7eef0 | 2865 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 2866 | |
94c30b78 | 2867 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 2868 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2869 | |
eefe576e AC |
2870 | /* Initialize the array that will be passed to |
2871 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
2872 | valid_disassembly_styles |
2873 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
2874 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
2875 | { |
2876 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 2877 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
2878 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
2879 | rdptr += length; | |
2880 | rest -= length; | |
94c30b78 | 2881 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
2882 | if (!strcmp (setname, "std")) |
2883 | { | |
afd7eef0 | 2884 | disassembly_style = setname; |
bc90b915 FN |
2885 | current_option = i; |
2886 | for (j = 0; j < numregs; j++) | |
2887 | arm_register_names[j] = (char *) regnames[j]; | |
2888 | set_arm_regname_option (i); | |
2889 | } | |
2890 | } | |
94c30b78 | 2891 | /* Mark the end of valid options. */ |
afd7eef0 | 2892 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 2893 | |
edefbb7c AC |
2894 | /* Create the help text. */ |
2895 | stb = mem_fileopen (); | |
2896 | fprintf_unfiltered (stb, "%s%s%s", | |
2897 | _("The valid values are:\n"), | |
2898 | regdesc, | |
2899 | _("The default is \"std\".")); | |
bc90b915 FN |
2900 | helptext = ui_file_xstrdup (stb, &length); |
2901 | ui_file_delete (stb); | |
ed9a39eb | 2902 | |
edefbb7c AC |
2903 | add_setshow_enum_cmd("disassembler", no_class, |
2904 | valid_disassembly_styles, &disassembly_style, | |
2905 | _("Set the disassembly style."), | |
2906 | _("Show the disassembly style."), | |
2907 | helptext, | |
2c5b56ce | 2908 | set_disassembly_style_sfunc, |
7915a72c | 2909 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 2910 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
2911 | |
2912 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
2913 | _("Set usage of ARM 32-bit mode."), | |
2914 | _("Show usage of ARM 32-bit mode."), | |
2915 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 2916 | NULL, |
7915a72c | 2917 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 2918 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 2919 | |
fd50bc42 | 2920 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
2921 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
2922 | _("Set the floating point type."), | |
2923 | _("Show the floating point type."), | |
2924 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
2925 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
2926 | fpa - FPA co-processor (GCC compiled).\n\ | |
2927 | softvfp - Software FP with pure-endian doubles.\n\ | |
2928 | vfp - VFP co-processor."), | |
edefbb7c | 2929 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 2930 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 2931 | |
6529d2dd | 2932 | /* Debugging flag. */ |
edefbb7c AC |
2933 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
2934 | _("Set ARM debugging."), | |
2935 | _("Show ARM debugging."), | |
2936 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 2937 | NULL, |
7915a72c | 2938 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 2939 | &setdebuglist, &showdebuglist); |
c906108c | 2940 | } |