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c906108c SS |
1 | /* Target-dependent code for the Acorn Risc Machine, for GDB, the GNU Debugger. |
2 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "inferior.h" | |
24 | #include "gdbcmd.h" | |
25 | #include "gdbcore.h" | |
26 | #include "symfile.h" | |
27 | #include "gdb_string.h" | |
28 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
29 | ||
30 | /* | |
31 | The following macros are actually wrong. Neither arm nor thumb can | |
32 | or should set the lsb on addr. | |
33 | The thumb addresses are mod 2, so (addr & 2) would be a good heuristic | |
34 | to use when checking for thumb (see arm_pc_is_thumb() below). | |
35 | Unfortunately, something else depends on these (incorrect) macros, so | |
36 | fixing them actually breaks gdb. I didn't have time to investigate. Z.R. | |
37 | */ | |
38 | /* Thumb function addresses are odd (bit 0 is set). Here are some | |
39 | macros to test, set, or clear bit 0 of addresses. */ | |
40 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
41 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
42 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
43 | ||
44 | /* Macros to round N up or down to the next A boundary; A must be | |
45 | a power of two. */ | |
46 | #define ROUND_DOWN(n,a) ((n) & ~((a) - 1)) | |
47 | #define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1)) | |
48 | ||
49 | /* Should call_function allocate stack space for a struct return? */ | |
50 | /* The system C compiler uses a similar structure return convention to gcc */ | |
51 | int | |
52 | arm_use_struct_convention (gcc_p, type) | |
53 | int gcc_p; | |
54 | struct type *type; | |
55 | { | |
56 | return (TYPE_LENGTH (type) > 4); | |
57 | } | |
58 | ||
59 | int | |
60 | arm_frame_chain_valid (chain, thisframe) | |
61 | CORE_ADDR chain; | |
62 | struct frame_info *thisframe; | |
63 | { | |
64 | #define LOWEST_PC 0x20 /* the first 0x20 bytes are the trap vectors. */ | |
65 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); | |
66 | } | |
67 | ||
68 | /* Set to true if the 32-bit mode is in use. */ | |
69 | ||
70 | int arm_apcs_32 = 1; | |
71 | ||
72 | /* Flag set by arm_fix_call_dummy that tells whether the target function | |
73 | is a Thumb function. This flag is checked by arm_push_arguments. | |
74 | FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to | |
75 | pass the function address as an additional parameter. */ | |
76 | ||
77 | static int target_is_thumb; | |
78 | ||
79 | /* Flag set by arm_fix_call_dummy that tells whether the calling function | |
80 | is a Thumb function. This flag is checked by arm_pc_is_thumb | |
81 | and arm_call_dummy_breakpoint_offset. */ | |
82 | ||
83 | static int caller_is_thumb; | |
84 | ||
85 | /* Tell if the program counter value in MEMADDR is in a Thumb function. */ | |
86 | ||
87 | int | |
88 | arm_pc_is_thumb (memaddr) | |
89 | bfd_vma memaddr; | |
90 | { | |
91 | struct minimal_symbol * sym; | |
92 | CORE_ADDR sp; | |
93 | ||
94 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
95 | if (IS_THUMB_ADDR (memaddr)) | |
96 | return 1; | |
97 | ||
98 | /* Thumb function have a "special" bit set in minimal symbols */ | |
99 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
100 | if (sym) | |
101 | { | |
102 | return (MSYMBOL_IS_SPECIAL(sym)); | |
103 | } | |
104 | else | |
105 | return 0; | |
106 | } | |
107 | ||
108 | /* Tell if the program counter value in MEMADDR is in a call dummy that | |
109 | is being called from a Thumb function. */ | |
110 | ||
111 | int | |
112 | arm_pc_is_thumb_dummy (memaddr) | |
113 | bfd_vma memaddr; | |
114 | { | |
115 | CORE_ADDR sp = read_sp(); | |
116 | ||
117 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp+64)) | |
118 | return caller_is_thumb; | |
119 | else | |
120 | return 0; | |
121 | } | |
122 | ||
123 | CORE_ADDR | |
124 | arm_addr_bits_remove (val) | |
125 | CORE_ADDR val; | |
126 | { | |
127 | if (arm_pc_is_thumb (val)) | |
128 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
129 | else | |
130 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
131 | } | |
132 | ||
133 | CORE_ADDR | |
134 | arm_saved_pc_after_call (frame) | |
135 | struct frame_info *frame; | |
136 | { | |
137 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
138 | } | |
139 | ||
140 | /* A typical Thumb prologue looks like this: | |
141 | push {r7, lr} | |
142 | add sp, sp, #-28 | |
143 | add r7, sp, #12 | |
144 | Sometimes the latter instruction may be replaced by: | |
145 | mov r7, sp | |
146 | */ | |
147 | ||
148 | static CORE_ADDR | |
149 | thumb_skip_prologue (pc) | |
150 | CORE_ADDR pc; | |
151 | { | |
152 | CORE_ADDR current_pc; | |
153 | ||
154 | for (current_pc = pc; current_pc < pc + 20; current_pc += 2) | |
155 | { | |
156 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
157 | ||
158 | if ( (insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ | |
159 | && (insn & 0xff00) != 0xb000 /* add sp, #simm */ | |
160 | && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ | |
161 | && insn != 0x466f /* mov r7, sp */ | |
162 | && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ | |
163 | break; | |
164 | } | |
165 | ||
166 | return current_pc; | |
167 | } | |
168 | ||
169 | /* APCS (ARM procedure call standard) defines the following prologue: | |
170 | ||
171 | mov ip, sp | |
172 | [stmfd sp!, {a1,a2,a3,a4}] | |
173 | stmfd sp!, {...,fp,ip,lr,pc} | |
174 | [stfe f7, [sp, #-12]!] | |
175 | [stfe f6, [sp, #-12]!] | |
176 | [stfe f5, [sp, #-12]!] | |
177 | [stfe f4, [sp, #-12]!] | |
178 | sub fp, ip, #nn // nn == 20 or 4 depending on second ins | |
179 | */ | |
180 | ||
181 | CORE_ADDR | |
182 | arm_skip_prologue (pc) | |
183 | CORE_ADDR pc; | |
184 | { | |
185 | unsigned long inst; | |
186 | CORE_ADDR skip_pc; | |
187 | CORE_ADDR func_addr, func_end; | |
188 | struct symtab_and_line sal; | |
189 | ||
190 | /* See what the symbol table says. */ | |
191 | if (find_pc_partial_function (pc, NULL, & func_addr, & func_end)) | |
192 | { | |
193 | sal = find_pc_line (func_addr, 0); | |
194 | if (sal.line != 0 && sal.end < func_end) | |
195 | return sal.end; | |
196 | } | |
197 | ||
198 | /* Check if this is Thumb code. */ | |
199 | if (arm_pc_is_thumb (pc)) | |
200 | return thumb_skip_prologue (pc); | |
201 | ||
202 | /* Can't find the prologue end in the symbol table, try it the hard way | |
203 | by disassembling the instructions. */ | |
204 | skip_pc = pc; | |
205 | inst = read_memory_integer (skip_pc, 4); | |
206 | if (inst != 0xe1a0c00d) /* mov ip, sp */ | |
207 | return pc; | |
208 | ||
209 | skip_pc += 4; | |
210 | inst = read_memory_integer (skip_pc, 4); | |
211 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ | |
212 | { | |
213 | skip_pc += 4; | |
214 | inst = read_memory_integer (skip_pc, 4); | |
215 | } | |
216 | ||
217 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ | |
218 | return pc; | |
219 | ||
220 | skip_pc += 4; | |
221 | inst = read_memory_integer (skip_pc, 4); | |
222 | ||
223 | /* Any insns after this point may float into the code, if it makes | |
224 | for better instruction scheduling, so we skip them only if | |
225 | we find them, but still consdier the function to be frame-ful */ | |
226 | ||
227 | /* We may have either one sfmfd instruction here, or several stfe insns, | |
228 | depending on the version of floating point code we support. */ | |
229 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
230 | { | |
231 | skip_pc += 4; | |
232 | inst = read_memory_integer (skip_pc, 4); | |
233 | } | |
234 | else | |
235 | { | |
236 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
237 | { | |
238 | skip_pc += 4; | |
239 | inst = read_memory_integer (skip_pc, 4); | |
240 | } | |
241 | } | |
242 | ||
243 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
244 | skip_pc += 4; | |
245 | ||
246 | return skip_pc; | |
247 | } | |
248 | ||
249 | ||
250 | ||
251 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) | |
252 | This function decodes a Thumb function prologue to determine: | |
253 | 1) the size of the stack frame | |
254 | 2) which registers are saved on it | |
255 | 3) the offsets of saved regs | |
256 | 4) the offset from the stack pointer to the frame pointer | |
257 | This information is stored in the "extra" fields of the frame_info. | |
258 | ||
259 | A typical Thumb function prologue might look like this: | |
260 | push {r7, lr} | |
261 | sub sp, #28, | |
262 | add r7, sp, #12 | |
263 | Which would create this stack frame (offsets relative to FP) | |
264 | old SP -> 24 stack parameters | |
265 | 20 LR | |
266 | 16 R7 | |
267 | R7 -> 0 local variables (16 bytes) | |
268 | SP -> -12 additional stack space (12 bytes) | |
269 | The frame size would thus be 36 bytes, and the frame offset would be | |
270 | 12 bytes. The frame register is R7. */ | |
271 | ||
272 | static void | |
273 | thumb_scan_prologue (fi) | |
274 | struct frame_info * fi; | |
275 | { | |
276 | CORE_ADDR prologue_start; | |
277 | CORE_ADDR prologue_end; | |
278 | CORE_ADDR current_pc; | |
279 | int saved_reg[16]; /* which register has been copied to register n? */ | |
280 | int i; | |
281 | ||
282 | if (find_pc_partial_function (fi->pc, NULL, & prologue_start, & prologue_end)) | |
283 | { | |
284 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
285 | ||
286 | if (sal.line == 0) /* no line info, use current PC */ | |
287 | prologue_end = fi->pc; | |
288 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
289 | prologue_end = sal.end; /* (probably means no prologue) */ | |
290 | } | |
291 | else | |
292 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ | |
293 | /* 16 pushes, an add, and "mv fp,sp" */ | |
294 | ||
295 | prologue_end = min (prologue_end, fi->pc); | |
296 | ||
297 | /* Initialize the saved register map. When register H is copied to | |
298 | register L, we will put H in saved_reg[L]. */ | |
299 | for (i = 0; i < 16; i++) | |
300 | saved_reg[i] = i; | |
301 | ||
302 | /* Search the prologue looking for instructions that set up the | |
303 | frame pointer, adjust the stack pointer, and save registers. */ | |
304 | ||
305 | fi->framesize = 0; | |
306 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 2) | |
307 | { | |
308 | unsigned short insn; | |
309 | int regno; | |
310 | int offset; | |
311 | ||
312 | insn = read_memory_unsigned_integer (current_pc, 2); | |
313 | ||
314 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ | |
315 | { | |
316 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
317 | whether to save LR (R14). */ | |
318 | int mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
319 | ||
320 | /* Calculate offsets of saved R0-R7 and LR. */ | |
321 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
322 | if (mask & (1 << regno)) | |
323 | { | |
324 | fi->framesize += 4; | |
325 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); | |
326 | saved_reg[regno] = regno; /* reset saved register map */ | |
327 | } | |
328 | } | |
329 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm */ | |
330 | { | |
331 | offset = (insn & 0x7f) << 2; /* get scaled offset */ | |
332 | if (insn & 0x80) /* is it signed? */ | |
333 | offset = -offset; | |
334 | fi->framesize -= offset; | |
335 | } | |
336 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
337 | { | |
338 | fi->framereg = THUMB_FP_REGNUM; | |
339 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ | |
340 | } | |
341 | else if (insn == 0x466f) /* mov r7, sp */ | |
342 | { | |
343 | fi->framereg = THUMB_FP_REGNUM; | |
344 | fi->frameoffset = 0; | |
345 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; | |
346 | } | |
347 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
348 | { | |
349 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ | |
350 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ | |
351 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ | |
352 | } | |
353 | else | |
354 | break; /* anything else isn't prologue */ | |
355 | } | |
356 | } | |
357 | ||
358 | /* Function: check_prologue_cache | |
359 | Check if prologue for this frame's PC has already been scanned. | |
360 | If it has, copy the relevant information about that prologue and | |
361 | return non-zero. Otherwise do not copy anything and return zero. | |
362 | ||
363 | The information saved in the cache includes: | |
364 | * the frame register number; | |
365 | * the size of the stack frame; | |
366 | * the offsets of saved regs (relative to the old SP); and | |
367 | * the offset from the stack pointer to the frame pointer | |
368 | ||
369 | The cache contains only one entry, since this is adequate | |
370 | for the typical sequence of prologue scan requests we get. | |
371 | When performing a backtrace, GDB will usually ask to scan | |
372 | the same function twice in a row (once to get the frame chain, | |
373 | and once to fill in the extra frame information). | |
374 | */ | |
375 | ||
376 | static struct frame_info prologue_cache; | |
377 | ||
378 | static int | |
379 | check_prologue_cache (fi) | |
380 | struct frame_info * fi; | |
381 | { | |
382 | int i; | |
383 | ||
384 | if (fi->pc == prologue_cache.pc) | |
385 | { | |
386 | fi->framereg = prologue_cache.framereg; | |
387 | fi->framesize = prologue_cache.framesize; | |
388 | fi->frameoffset = prologue_cache.frameoffset; | |
389 | for (i = 0; i <= NUM_REGS; i++) | |
390 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; | |
391 | return 1; | |
392 | } | |
393 | else | |
394 | return 0; | |
395 | } | |
396 | ||
397 | ||
398 | /* Function: save_prologue_cache | |
399 | Copy the prologue information from fi to the prologue cache. | |
400 | */ | |
401 | ||
402 | static void | |
403 | save_prologue_cache (fi) | |
404 | struct frame_info * fi; | |
405 | { | |
406 | int i; | |
407 | ||
408 | prologue_cache.pc = fi->pc; | |
409 | prologue_cache.framereg = fi->framereg; | |
410 | prologue_cache.framesize = fi->framesize; | |
411 | prologue_cache.frameoffset = fi->frameoffset; | |
412 | ||
413 | for (i = 0; i <= NUM_REGS; i++) | |
414 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; | |
415 | } | |
416 | ||
417 | ||
418 | /* Function: arm_scan_prologue | |
419 | This function decodes an ARM function prologue to determine: | |
420 | 1) the size of the stack frame | |
421 | 2) which registers are saved on it | |
422 | 3) the offsets of saved regs | |
423 | 4) the offset from the stack pointer to the frame pointer | |
424 | This information is stored in the "extra" fields of the frame_info. | |
425 | ||
426 | A typical Arm function prologue might look like this: | |
427 | mov ip, sp | |
428 | stmfd sp!, {fp, ip, lr, pc} | |
429 | sub fp, ip, #4 | |
430 | sub sp, sp, #16 | |
431 | Which would create this stack frame (offsets relative to FP): | |
432 | IP -> 4 (caller's stack) | |
433 | FP -> 0 PC (points to address of stmfd instruction + 12 in callee) | |
434 | -4 LR (return address in caller) | |
435 | -8 IP (copy of caller's SP) | |
436 | -12 FP (caller's FP) | |
437 | SP -> -28 Local variables | |
438 | The frame size would thus be 32 bytes, and the frame offset would be | |
439 | 28 bytes. */ | |
440 | ||
441 | static void | |
442 | arm_scan_prologue (fi) | |
443 | struct frame_info * fi; | |
444 | { | |
445 | int regno, sp_offset, fp_offset; | |
446 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
447 | ||
448 | /* Check if this function is already in the cache of frame information. */ | |
449 | if (check_prologue_cache (fi)) | |
450 | return; | |
451 | ||
452 | /* Assume there is no frame until proven otherwise. */ | |
453 | fi->framereg = SP_REGNUM; | |
454 | fi->framesize = 0; | |
455 | fi->frameoffset = 0; | |
456 | ||
457 | /* Check for Thumb prologue. */ | |
458 | if (arm_pc_is_thumb (fi->pc)) | |
459 | { | |
460 | thumb_scan_prologue (fi); | |
461 | save_prologue_cache (fi); | |
462 | return; | |
463 | } | |
464 | ||
465 | /* Find the function prologue. If we can't find the function in | |
466 | the symbol table, peek in the stack frame to find the PC. */ | |
467 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
468 | { | |
469 | /* Assume the prologue is everything between the first instruction | |
470 | in the function and the first source line. */ | |
471 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
472 | ||
473 | if (sal.line == 0) /* no line info, use current PC */ | |
474 | prologue_end = fi->pc; | |
475 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
476 | prologue_end = sal.end; /* (probably means no prologue) */ | |
477 | } | |
478 | else | |
479 | { | |
480 | /* Get address of the stmfd in the prologue of the callee; the saved | |
481 | PC is the address of the stmfd + 12. */ | |
482 | prologue_start = (read_memory_integer (fi->frame, 4) & 0x03fffffc) - 12; | |
483 | prologue_end = prologue_start + 40; /* FIXME: should be big enough */ | |
484 | } | |
485 | ||
486 | /* Now search the prologue looking for instructions that set up the | |
487 | frame pointer, adjust the stack pointer, and save registers. */ | |
488 | ||
489 | sp_offset = fp_offset = 0; | |
490 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 4) | |
491 | { | |
492 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); | |
493 | ||
494 | if ((insn & 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., r7, lr} */ | |
495 | { | |
496 | int mask = insn & 0xffff; | |
497 | ||
498 | /* Calculate offsets of saved registers. */ | |
499 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
500 | if (mask & (1 << regno)) | |
501 | { | |
502 | sp_offset -= 4; | |
503 | fi->fsr.regs[regno] = sp_offset; | |
504 | } | |
505 | } | |
506 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
507 | { | |
508 | unsigned imm = insn & 0xff; /* immediate value */ | |
509 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
510 | imm = (imm >> rot) | (imm << (32-rot)); | |
511 | fp_offset = -imm; | |
512 | fi->framereg = FP_REGNUM; | |
513 | } | |
514 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
515 | { | |
516 | unsigned imm = insn & 0xff; /* immediate value */ | |
517 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
518 | imm = (imm >> rot) | (imm << (32-rot)); | |
519 | sp_offset -= imm; | |
520 | } | |
521 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
522 | { | |
523 | sp_offset -= 12; | |
524 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
525 | fi->fsr.regs[regno] = sp_offset; | |
526 | } | |
527 | else if (insn == 0xe1a0c00d) /* mov ip, sp */ | |
528 | continue; | |
529 | else | |
530 | break; /* not a recognized prologue instruction */ | |
531 | } | |
532 | ||
533 | /* The frame size is just the negative of the offset (from the original SP) | |
534 | of the last thing thing we pushed on the stack. The frame offset is | |
535 | [new FP] - [new SP]. */ | |
536 | fi->framesize = -sp_offset; | |
537 | fi->frameoffset = fp_offset - sp_offset; | |
538 | ||
539 | save_prologue_cache (fi); | |
540 | } | |
541 | ||
542 | ||
543 | /* Function: find_callers_reg | |
544 | Find REGNUM on the stack. Otherwise, it's in an active register. One thing | |
545 | we might want to do here is to check REGNUM against the clobber mask, and | |
546 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
547 | would provide a graceful failure mode when trying to get the value of | |
548 | caller-saves registers for an inner frame. */ | |
549 | ||
550 | static CORE_ADDR | |
551 | arm_find_callers_reg (fi, regnum) | |
552 | struct frame_info * fi; | |
553 | int regnum; | |
554 | { | |
555 | for (; fi; fi = fi->next) | |
556 | ||
557 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
558 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
559 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
560 | else | |
561 | #endif | |
562 | if (fi->fsr.regs[regnum] != 0) | |
563 | return read_memory_integer (fi->fsr.regs[regnum], | |
564 | REGISTER_RAW_SIZE(regnum)); | |
565 | return read_register (regnum); | |
566 | } | |
567 | ||
568 | ||
569 | /* Function: frame_chain | |
570 | Given a GDB frame, determine the address of the calling function's frame. | |
571 | This will be used to create a new GDB frame struct, and then | |
572 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
573 | For ARM, we save the frame size when we initialize the frame_info. | |
574 | ||
575 | The original definition of this function was a macro in tm-arm.h: | |
576 | { In the case of the ARM, the frame's nominal address is the FP value, | |
577 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
578 | ||
579 | #define FRAME_CHAIN(thisframe) \ | |
580 | ((thisframe)->pc >= LOWEST_PC ? \ | |
581 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
582 | 0) | |
583 | */ | |
584 | ||
585 | CORE_ADDR | |
586 | arm_frame_chain (fi) | |
587 | struct frame_info * fi; | |
588 | { | |
589 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
590 | CORE_ADDR fn_start, callers_pc, fp; | |
591 | ||
592 | /* is this a dummy frame? */ | |
593 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
594 | return fi->frame; /* dummy frame same as caller's frame */ | |
595 | ||
596 | /* is caller-of-this a dummy frame? */ | |
597 | callers_pc = FRAME_SAVED_PC(fi); /* find out who called us: */ | |
598 | fp = arm_find_callers_reg (fi, FP_REGNUM); | |
599 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) | |
600 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
601 | ||
602 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
603 | if (fn_start == entry_point_address ()) | |
604 | return 0; /* in _start fn, don't chain further */ | |
605 | #endif | |
606 | CORE_ADDR caller_pc, fn_start; | |
607 | struct frame_info caller_fi; | |
608 | int framereg = fi->framereg; | |
609 | ||
610 | if (fi->pc < LOWEST_PC) | |
611 | return 0; | |
612 | ||
613 | /* If the caller is the startup code, we're at the end of the chain. */ | |
614 | caller_pc = FRAME_SAVED_PC (fi); | |
615 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
616 | if (fn_start == entry_point_address ()) | |
617 | return 0; | |
618 | ||
619 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
620 | the frame register of the caller is different from ours. | |
621 | So we must scan the prologue of the caller to determine its | |
622 | frame register number. */ | |
623 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) | |
624 | { | |
625 | memset (& caller_fi, 0, sizeof (caller_fi)); | |
626 | caller_fi.pc = caller_pc; | |
627 | arm_scan_prologue (& caller_fi); | |
628 | framereg = caller_fi.framereg; | |
629 | } | |
630 | ||
631 | /* If the caller used a frame register, return its value. | |
632 | Otherwise, return the caller's stack pointer. */ | |
633 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
634 | return arm_find_callers_reg (fi, framereg); | |
635 | else | |
636 | return fi->frame + fi->framesize; | |
637 | } | |
638 | ||
639 | /* Function: init_extra_frame_info | |
640 | This function actually figures out the frame address for a given pc and | |
641 | sp. This is tricky because we sometimes don't use an explicit | |
642 | frame pointer, and the previous stack pointer isn't necessarily recorded | |
643 | on the stack. The only reliable way to get this info is to | |
644 | examine the prologue. */ | |
645 | ||
646 | void | |
647 | arm_init_extra_frame_info (fi) | |
648 | struct frame_info * fi; | |
649 | { | |
650 | int reg; | |
651 | ||
652 | if (fi->next) | |
653 | fi->pc = FRAME_SAVED_PC (fi->next); | |
654 | ||
655 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); | |
656 | ||
657 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
658 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
659 | { | |
660 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
661 | by assuming it's always FP. */ | |
662 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
663 | fi->framesize = 0; | |
664 | fi->frameoffset = 0; | |
665 | return; | |
666 | } | |
667 | else | |
668 | #endif | |
669 | { | |
670 | arm_scan_prologue (fi); | |
671 | ||
672 | if (!fi->next) /* this is the innermost frame? */ | |
673 | fi->frame = read_register (fi->framereg); | |
674 | else /* not the innermost frame */ | |
675 | /* If we have an FP, the callee saved it. */ | |
676 | if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) | |
677 | if (fi->next->fsr.regs[fi->framereg] != 0) | |
678 | fi->frame = read_memory_integer (fi->next->fsr.regs[fi->framereg], | |
679 | 4); | |
680 | ||
681 | /* Calculate actual addresses of saved registers using offsets determined | |
682 | by arm_scan_prologue. */ | |
683 | for (reg = 0; reg < NUM_REGS; reg++) | |
684 | if (fi->fsr.regs[reg] != 0) | |
685 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; | |
686 | } | |
687 | } | |
688 | ||
689 | ||
690 | /* Function: frame_saved_pc | |
691 | Find the caller of this frame. We do this by seeing if LR_REGNUM is saved | |
692 | in the stack anywhere, otherwise we get it from the registers. | |
693 | ||
694 | The old definition of this function was a macro: | |
695 | #define FRAME_SAVED_PC(FRAME) \ | |
696 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) | |
697 | */ | |
698 | ||
699 | CORE_ADDR | |
700 | arm_frame_saved_pc (fi) | |
701 | struct frame_info * fi; | |
702 | { | |
703 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
704 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
705 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
706 | else | |
707 | #endif | |
708 | { | |
709 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
710 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
711 | } | |
712 | } | |
713 | ||
714 | ||
715 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. | |
716 | Examine the Program Status Register to decide which state we're in. */ | |
717 | ||
718 | CORE_ADDR | |
719 | arm_target_read_fp () | |
720 | { | |
721 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
722 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
723 | else | |
724 | return read_register (FP_REGNUM); /* R11 if ARM */ | |
725 | } | |
726 | ||
727 | ||
728 | /* Calculate the frame offsets of the saved registers (ARM version). */ | |
729 | void | |
730 | arm_frame_find_saved_regs (fi, regaddr) | |
731 | struct frame_info *fi; | |
732 | struct frame_saved_regs *regaddr; | |
733 | { | |
734 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); | |
735 | } | |
736 | ||
737 | ||
738 | void | |
739 | arm_push_dummy_frame () | |
740 | { | |
741 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
742 | CORE_ADDR sp = old_sp; | |
743 | CORE_ADDR fp, prologue_start; | |
744 | int regnum; | |
745 | ||
746 | /* Push the two dummy prologue instructions in reverse order, | |
747 | so that they'll be in the correct low-to-high order in memory. */ | |
748 | /* sub fp, ip, #4 */ | |
749 | sp = push_word (sp, 0xe24cb004); | |
750 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
751 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
752 | ||
753 | /* push a pointer to the dummy prologue + 12, because when | |
754 | stm instruction stores the PC, it stores the address of the stm | |
755 | instruction itself plus 12. */ | |
756 | fp = sp = push_word (sp, prologue_start + 12); | |
757 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ | |
758 | sp = push_word (sp, old_sp); | |
759 | sp = push_word (sp, read_register (FP_REGNUM)); | |
760 | ||
761 | for (regnum = 10; regnum >= 0; regnum --) | |
762 | sp = push_word (sp, read_register (regnum)); | |
763 | ||
764 | write_register (FP_REGNUM, fp); | |
765 | write_register (THUMB_FP_REGNUM, fp); | |
766 | write_register (SP_REGNUM, sp); | |
767 | } | |
768 | ||
769 | /* Fix up the call dummy, based on whether the processor is currently | |
770 | in Thumb or ARM mode, and whether the target function is Thumb | |
771 | or ARM. There are three different situations requiring three | |
772 | different dummies: | |
773 | ||
774 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
775 | been copied into the dummy parameter to this function. | |
776 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the | |
777 | "mov pc,r4" instruction patched to be a "bx r4" instead. | |
778 | * Thumb calling anything: uses the Thumb dummy defined below, which | |
779 | works for calling both ARM and Thumb functions. | |
780 | ||
781 | All three call dummies expect to receive the target function address | |
782 | in R4, with the low bit set if it's a Thumb function. | |
783 | */ | |
784 | ||
785 | void | |
786 | arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) | |
787 | char * dummy; | |
788 | CORE_ADDR pc; | |
789 | CORE_ADDR fun; | |
790 | int nargs; | |
791 | value_ptr * args; | |
792 | struct type * type; | |
793 | int gcc_p; | |
794 | { | |
795 | static short thumb_dummy[4] = | |
796 | { | |
797 | 0xf000, 0xf801, /* bl label */ | |
798 | 0xdf18, /* swi 24 */ | |
799 | 0x4720, /* label: bx r4 */ | |
800 | }; | |
801 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
802 | ||
803 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
804 | caller_is_thumb = arm_pc_is_thumb (read_pc()); | |
805 | ||
806 | /* If the target function is Thumb, set the low bit of the function address. | |
807 | And if the CPU is currently in ARM mode, patch the second instruction | |
808 | of call dummy to use a BX instruction to switch to Thumb mode. */ | |
809 | target_is_thumb = arm_pc_is_thumb (fun); | |
810 | if (target_is_thumb) | |
811 | { | |
812 | fun |= 1; | |
813 | if (!caller_is_thumb) | |
814 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
815 | } | |
816 | ||
817 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
818 | instead of the ARM one that's already been copied. This will | |
819 | work for both Thumb and ARM target functions. */ | |
820 | if (caller_is_thumb) | |
821 | { | |
822 | int i; | |
823 | char *p = dummy; | |
824 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
825 | ||
826 | for (i = 0; i < len; i++) | |
827 | { | |
828 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
829 | p += sizeof (thumb_dummy[0]); | |
830 | } | |
831 | } | |
832 | ||
833 | /* Put the target address in r4; the call dummy will copy this to the PC. */ | |
834 | write_register (4, fun); | |
835 | } | |
836 | ||
837 | ||
838 | /* Return the offset in the call dummy of the instruction that needs | |
839 | to have a breakpoint placed on it. This is the offset of the 'swi 24' | |
840 | instruction, which is no longer actually used, but simply acts | |
841 | as a place-holder now. | |
842 | ||
843 | This implements the CALL_DUMMY_BREAK_OFFSET macro. | |
844 | */ | |
845 | ||
846 | int | |
847 | arm_call_dummy_breakpoint_offset () | |
848 | { | |
849 | if (caller_is_thumb) | |
850 | return 4; | |
851 | else | |
852 | return 8; | |
853 | } | |
854 | ||
855 | ||
856 | CORE_ADDR | |
857 | arm_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
858 | int nargs; | |
859 | value_ptr * args; | |
860 | CORE_ADDR sp; | |
861 | int struct_return; | |
862 | CORE_ADDR struct_addr; | |
863 | { | |
864 | int argreg; | |
865 | int float_argreg; | |
866 | int argnum; | |
867 | int stack_offset; | |
868 | struct stack_arg { | |
869 | char *val; | |
870 | int len; | |
871 | int offset; | |
872 | }; | |
873 | struct stack_arg *stack_args = | |
874 | (struct stack_arg*)alloca (nargs * sizeof (struct stack_arg)); | |
875 | int nstack_args = 0; | |
876 | ||
877 | ||
878 | /* Initialize the integer and float register pointers. */ | |
879 | argreg = A1_REGNUM; | |
880 | float_argreg = F0_REGNUM; | |
881 | ||
882 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
883 | if (struct_return) | |
884 | write_register (argreg++, struct_addr); | |
885 | ||
886 | /* The offset onto the stack at which we will start copying parameters | |
887 | (after the registers are used up) begins at 16 in the old ABI. | |
888 | This leaves room for the "home" area for register parameters. */ | |
889 | stack_offset = REGISTER_SIZE * 4; | |
890 | ||
891 | /* Process args from left to right. Store as many as allowed in | |
892 | registers, save the rest to be pushed on the stack */ | |
893 | for(argnum = 0; argnum < nargs; argnum++) | |
894 | { | |
895 | char * val; | |
896 | value_ptr arg = args[argnum]; | |
897 | struct type * arg_type = check_typedef (VALUE_TYPE (arg)); | |
898 | struct type * target_type = TYPE_TARGET_TYPE (arg_type); | |
899 | int len = TYPE_LENGTH (arg_type); | |
900 | enum type_code typecode = TYPE_CODE (arg_type); | |
901 | CORE_ADDR regval; | |
902 | int newarg; | |
903 | ||
904 | val = (char *) VALUE_CONTENTS (arg); | |
905 | ||
906 | /* If the argument is a pointer to a function, and it's a Thumb | |
907 | function, set the low bit of the pointer. */ | |
908 | if (typecode == TYPE_CODE_PTR | |
909 | && target_type != NULL | |
910 | && TYPE_CODE (target_type) == TYPE_CODE_FUNC) | |
911 | { | |
912 | regval = extract_address (val, len); | |
913 | if (arm_pc_is_thumb (regval)) | |
914 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
915 | } | |
916 | ||
917 | #define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */ | |
918 | #if MAPCS_FLOAT | |
919 | /* Up to four floating point arguments can be passed in floating | |
920 | point registers on ARM (not on Thumb). */ | |
921 | if (typecode == TYPE_CODE_FLT | |
922 | && float_argreg <= ARM_LAST_FP_ARG_REGNUM | |
923 | && !target_is_thumb) | |
924 | { | |
925 | /* This is a floating point value that fits entirely | |
926 | in a single register. */ | |
927 | regval = extract_address (val, len); | |
928 | write_register (float_argreg++, regval); | |
929 | } | |
930 | else | |
931 | #endif | |
932 | { | |
933 | /* Copy the argument to general registers or the stack in | |
934 | register-sized pieces. Large arguments are split between | |
935 | registers and stack. */ | |
936 | while (len > 0) | |
937 | { | |
938 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
939 | { | |
940 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; | |
941 | regval = extract_address (val, partial_len); | |
942 | ||
943 | /* It's a simple argument being passed in a general | |
944 | register. */ | |
945 | write_register (argreg, regval); | |
946 | argreg++; | |
947 | len -= partial_len; | |
948 | val += partial_len; | |
949 | } | |
950 | else | |
951 | { | |
952 | /* keep for later pushing */ | |
953 | stack_args[nstack_args].val = val; | |
954 | stack_args[nstack_args++].len = len; | |
955 | break; | |
956 | } | |
957 | } | |
958 | } | |
959 | } | |
960 | /* now do the real stack pushing, process args right to left */ | |
961 | while(nstack_args--) | |
962 | { | |
963 | sp -= stack_args[nstack_args].len; | |
964 | write_memory(sp, stack_args[nstack_args].val, | |
965 | stack_args[nstack_args].len); | |
966 | } | |
967 | ||
968 | /* Return adjusted stack pointer. */ | |
969 | return sp; | |
970 | } | |
971 | ||
972 | void | |
973 | arm_pop_frame () | |
974 | { | |
975 | struct frame_info *frame = get_current_frame(); | |
976 | int regnum; | |
977 | ||
978 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
979 | if (frame->fsr.regs[regnum] != 0) | |
980 | write_register (regnum, | |
981 | read_memory_integer (frame->fsr.regs[regnum], 4)); | |
982 | ||
983 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); | |
984 | write_register (SP_REGNUM, read_register (frame->framereg)); | |
985 | ||
986 | flush_cached_frames (); | |
987 | } | |
988 | ||
989 | static void | |
990 | print_fpu_flags (flags) | |
991 | int flags; | |
992 | { | |
993 | if (flags & (1 << 0)) fputs ("IVO ", stdout); | |
994 | if (flags & (1 << 1)) fputs ("DVZ ", stdout); | |
995 | if (flags & (1 << 2)) fputs ("OFL ", stdout); | |
996 | if (flags & (1 << 3)) fputs ("UFL ", stdout); | |
997 | if (flags & (1 << 4)) fputs ("INX ", stdout); | |
998 | putchar ('\n'); | |
999 | } | |
1000 | ||
1001 | void | |
1002 | arm_float_info () | |
1003 | { | |
1004 | register unsigned long status = read_register (FPS_REGNUM); | |
1005 | int type; | |
1006 | ||
1007 | type = (status >> 24) & 127; | |
1008 | printf ("%s FPU type %d\n", | |
1009 | (status & (1<<31)) ? "Hardware" : "Software", | |
1010 | type); | |
1011 | fputs ("mask: ", stdout); | |
1012 | print_fpu_flags (status >> 16); | |
1013 | fputs ("flags: ", stdout); | |
1014 | print_fpu_flags (status); | |
1015 | } | |
1016 | ||
1017 | static char *original_register_names[] = | |
1018 | { "a1", "a2", "a3", "a4", /* 0 1 2 3 */ | |
1019 | "v1", "v2", "v3", "v4", /* 4 5 6 7 */ | |
1020 | "v5", "v6", "sl", "fp", /* 8 9 10 11 */ | |
1021 | "ip", "sp", "lr", "pc", /* 12 13 14 15 */ | |
1022 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
1023 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
1024 | "fps","ps" } /* 24 25 */; | |
1025 | ||
1026 | /* These names are the ones which gcc emits, and | |
1027 | I find them less confusing. Toggle between them | |
1028 | using the `othernames' command. */ | |
1029 | static char *additional_register_names[] = | |
1030 | { "r0", "r1", "r2", "r3", /* 0 1 2 3 */ | |
1031 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
1032 | "r8", "r9", "sl", "fp", /* 8 9 10 11 */ | |
1033 | "ip", "sp", "lr", "pc", /* 12 13 14 15 */ | |
1034 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
1035 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
1036 | "fps","ps" } /* 24 25 */; | |
1037 | ||
1038 | char **arm_register_names = original_register_names; | |
1039 | ||
1040 | ||
1041 | static void | |
1042 | arm_othernames () | |
1043 | { | |
1044 | static int toggle; | |
1045 | arm_register_names = (toggle | |
1046 | ? additional_register_names | |
1047 | : original_register_names); | |
1048 | toggle = !toggle; | |
1049 | } | |
1050 | ||
1051 | /* FIXME: Fill in with the 'right thing', see asm | |
1052 | template in arm-convert.s */ | |
1053 | ||
1054 | void | |
1055 | convert_from_extended (ptr, dbl) | |
1056 | void * ptr; | |
1057 | double * dbl; | |
1058 | { | |
1059 | *dbl = *(double*)ptr; | |
1060 | } | |
1061 | ||
1062 | void | |
1063 | convert_to_extended (dbl, ptr) | |
1064 | void * ptr; | |
1065 | double * dbl; | |
1066 | { | |
1067 | *(double*)ptr = *dbl; | |
1068 | } | |
1069 | ||
1070 | static int | |
1071 | condition_true (cond, status_reg) | |
1072 | unsigned long cond; | |
1073 | unsigned long status_reg; | |
1074 | { | |
1075 | if (cond == INST_AL || cond == INST_NV) | |
1076 | return 1; | |
1077 | ||
1078 | switch (cond) | |
1079 | { | |
1080 | case INST_EQ: | |
1081 | return ((status_reg & FLAG_Z) != 0); | |
1082 | case INST_NE: | |
1083 | return ((status_reg & FLAG_Z) == 0); | |
1084 | case INST_CS: | |
1085 | return ((status_reg & FLAG_C) != 0); | |
1086 | case INST_CC: | |
1087 | return ((status_reg & FLAG_C) == 0); | |
1088 | case INST_MI: | |
1089 | return ((status_reg & FLAG_N) != 0); | |
1090 | case INST_PL: | |
1091 | return ((status_reg & FLAG_N) == 0); | |
1092 | case INST_VS: | |
1093 | return ((status_reg & FLAG_V) != 0); | |
1094 | case INST_VC: | |
1095 | return ((status_reg & FLAG_V) == 0); | |
1096 | case INST_HI: | |
1097 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1098 | case INST_LS: | |
1099 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1100 | case INST_GE: | |
1101 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1102 | case INST_LT: | |
1103 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1104 | case INST_GT: | |
1105 | return (((status_reg & FLAG_Z) == 0) && | |
1106 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); | |
1107 | case INST_LE: | |
1108 | return (((status_reg & FLAG_Z) != 0) || | |
1109 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); | |
1110 | } | |
1111 | return 1; | |
1112 | } | |
1113 | ||
1114 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
1115 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1116 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1117 | #define sbits(obj,st,fn) \ | |
1118 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1119 | #define BranchDest(addr,instr) \ | |
1120 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1121 | #define ARM_PC_32 1 | |
1122 | ||
1123 | static unsigned long | |
1124 | shifted_reg_val (inst, carry, pc_val, status_reg) | |
1125 | unsigned long inst; | |
1126 | int carry; | |
1127 | unsigned long pc_val; | |
1128 | unsigned long status_reg; | |
1129 | { | |
1130 | unsigned long res, shift; | |
1131 | int rm = bits (inst, 0, 3); | |
1132 | unsigned long shifttype = bits (inst, 5, 6); | |
1133 | ||
1134 | if (bit(inst, 4)) | |
1135 | { | |
1136 | int rs = bits (inst, 8, 11); | |
1137 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1138 | } | |
1139 | else | |
1140 | shift = bits (inst, 7, 11); | |
1141 | ||
1142 | res = (rm == 15 | |
1143 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) | |
1144 | + (bit (inst, 4) ? 12 : 8)) | |
1145 | : read_register (rm)); | |
1146 | ||
1147 | switch (shifttype) | |
1148 | { | |
1149 | case 0: /* LSL */ | |
1150 | res = shift >= 32 ? 0 : res << shift; | |
1151 | break; | |
1152 | ||
1153 | case 1: /* LSR */ | |
1154 | res = shift >= 32 ? 0 : res >> shift; | |
1155 | break; | |
1156 | ||
1157 | case 2: /* ASR */ | |
1158 | if (shift >= 32) shift = 31; | |
1159 | res = ((res & 0x80000000L) | |
1160 | ? ~((~res) >> shift) : res >> shift); | |
1161 | break; | |
1162 | ||
1163 | case 3: /* ROR/RRX */ | |
1164 | shift &= 31; | |
1165 | if (shift == 0) | |
1166 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1167 | else | |
1168 | res = (res >> shift) | (res << (32-shift)); | |
1169 | break; | |
1170 | } | |
1171 | ||
1172 | return res & 0xffffffff; | |
1173 | } | |
1174 | ||
1175 | ||
1176 | /* Return number of 1-bits in VAL. */ | |
1177 | ||
1178 | static int | |
1179 | bitcount (val) | |
1180 | unsigned long val; | |
1181 | { | |
1182 | int nbits; | |
1183 | for (nbits = 0; val != 0; nbits++) | |
1184 | val &= val - 1; /* delete rightmost 1-bit in val */ | |
1185 | return nbits; | |
1186 | } | |
1187 | ||
1188 | ||
1189 | static CORE_ADDR | |
1190 | thumb_get_next_pc (pc) | |
1191 | CORE_ADDR pc; | |
1192 | { | |
1193 | unsigned long pc_val = ((unsigned long)pc) + 4; /* PC after prefetch */ | |
1194 | unsigned short inst1 = read_memory_integer (pc, 2); | |
1195 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ | |
1196 | unsigned long offset; | |
1197 | ||
1198 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1199 | { | |
1200 | CORE_ADDR sp; | |
1201 | ||
1202 | /* Fetch the saved PC from the stack. It's stored above | |
1203 | all of the other registers. */ | |
1204 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1205 | sp = read_register (SP_REGNUM); | |
1206 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1207 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1208 | if (nextpc == pc) | |
1209 | error ("Infinite loop detected"); | |
1210 | } | |
1211 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1212 | { | |
1213 | unsigned long status = read_register (PS_REGNUM); | |
1214 | unsigned long cond = bits (inst1, 8, 11); | |
1215 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ | |
1216 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1217 | } | |
1218 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1219 | { | |
1220 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1221 | } | |
1222 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1223 | { | |
1224 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
1225 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); | |
1226 | nextpc = pc_val + offset; | |
1227 | } | |
1228 | ||
1229 | return nextpc; | |
1230 | } | |
1231 | ||
1232 | ||
1233 | CORE_ADDR | |
1234 | arm_get_next_pc (pc) | |
1235 | CORE_ADDR pc; | |
1236 | { | |
1237 | unsigned long pc_val; | |
1238 | unsigned long this_instr; | |
1239 | unsigned long status; | |
1240 | CORE_ADDR nextpc; | |
1241 | ||
1242 | if (arm_pc_is_thumb (pc)) | |
1243 | return thumb_get_next_pc (pc); | |
1244 | ||
1245 | pc_val = (unsigned long) pc; | |
1246 | this_instr = read_memory_integer (pc, 4); | |
1247 | status = read_register (PS_REGNUM); | |
1248 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ | |
1249 | ||
1250 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1251 | { | |
1252 | switch (bits (this_instr, 24, 27)) | |
1253 | { | |
1254 | case 0x0: case 0x1: /* data processing */ | |
1255 | case 0x2: case 0x3: | |
1256 | { | |
1257 | unsigned long operand1, operand2, result = 0; | |
1258 | unsigned long rn; | |
1259 | int c; | |
1260 | ||
1261 | if (bits (this_instr, 12, 15) != 15) | |
1262 | break; | |
1263 | ||
1264 | if (bits (this_instr, 22, 25) == 0 | |
1265 | && bits (this_instr, 4, 7) == 9) /* multiply */ | |
1266 | error ("Illegal update to pc in instruction"); | |
1267 | ||
1268 | /* Multiply into PC */ | |
1269 | c = (status & FLAG_C) ? 1 : 0; | |
1270 | rn = bits (this_instr, 16, 19); | |
1271 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1272 | ||
1273 | if (bit (this_instr, 25)) | |
1274 | { | |
1275 | unsigned long immval = bits (this_instr, 0, 7); | |
1276 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
1277 | operand2 = ((immval >> rotate) | (immval << (32-rotate))) | |
1278 | & 0xffffffff; | |
1279 | } | |
1280 | else /* operand 2 is a shifted register */ | |
1281 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); | |
1282 | ||
1283 | switch (bits (this_instr, 21, 24)) | |
1284 | { | |
1285 | case 0x0: /*and*/ | |
1286 | result = operand1 & operand2; | |
1287 | break; | |
1288 | ||
1289 | case 0x1: /*eor*/ | |
1290 | result = operand1 ^ operand2; | |
1291 | break; | |
1292 | ||
1293 | case 0x2: /*sub*/ | |
1294 | result = operand1 - operand2; | |
1295 | break; | |
1296 | ||
1297 | case 0x3: /*rsb*/ | |
1298 | result = operand2 - operand1; | |
1299 | break; | |
1300 | ||
1301 | case 0x4: /*add*/ | |
1302 | result = operand1 + operand2; | |
1303 | break; | |
1304 | ||
1305 | case 0x5: /*adc*/ | |
1306 | result = operand1 + operand2 + c; | |
1307 | break; | |
1308 | ||
1309 | case 0x6: /*sbc*/ | |
1310 | result = operand1 - operand2 + c; | |
1311 | break; | |
1312 | ||
1313 | case 0x7: /*rsc*/ | |
1314 | result = operand2 - operand1 + c; | |
1315 | break; | |
1316 | ||
1317 | case 0x8: case 0x9: case 0xa: case 0xb: /* tst, teq, cmp, cmn */ | |
1318 | result = (unsigned long) nextpc; | |
1319 | break; | |
1320 | ||
1321 | case 0xc: /*orr*/ | |
1322 | result = operand1 | operand2; | |
1323 | break; | |
1324 | ||
1325 | case 0xd: /*mov*/ | |
1326 | /* Always step into a function. */ | |
1327 | result = operand2; | |
1328 | break; | |
1329 | ||
1330 | case 0xe: /*bic*/ | |
1331 | result = operand1 & ~operand2; | |
1332 | break; | |
1333 | ||
1334 | case 0xf: /*mvn*/ | |
1335 | result = ~operand2; | |
1336 | break; | |
1337 | } | |
1338 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1339 | ||
1340 | if (nextpc == pc) | |
1341 | error ("Infinite loop detected"); | |
1342 | break; | |
1343 | } | |
1344 | ||
1345 | case 0x4: case 0x5: /* data transfer */ | |
1346 | case 0x6: case 0x7: | |
1347 | if (bit (this_instr, 20)) | |
1348 | { | |
1349 | /* load */ | |
1350 | if (bits (this_instr, 12, 15) == 15) | |
1351 | { | |
1352 | /* rd == pc */ | |
1353 | unsigned long rn; | |
1354 | unsigned long base; | |
1355 | ||
1356 | if (bit (this_instr, 22)) | |
1357 | error ("Illegal update to pc in instruction"); | |
1358 | ||
1359 | /* byte write to PC */ | |
1360 | rn = bits (this_instr, 16, 19); | |
1361 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1362 | if (bit (this_instr, 24)) | |
1363 | { | |
1364 | /* pre-indexed */ | |
1365 | int c = (status & FLAG_C) ? 1 : 0; | |
1366 | unsigned long offset = | |
1367 | (bit (this_instr, 25) | |
1368 | ? shifted_reg_val (this_instr, c, pc_val) | |
1369 | : bits (this_instr, 0, 11)); | |
1370 | ||
1371 | if (bit (this_instr, 23)) | |
1372 | base += offset; | |
1373 | else | |
1374 | base -= offset; | |
1375 | } | |
1376 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, | |
1377 | 4); | |
1378 | ||
1379 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1380 | ||
1381 | if (nextpc == pc) | |
1382 | error ("Infinite loop detected"); | |
1383 | } | |
1384 | } | |
1385 | break; | |
1386 | ||
1387 | case 0x8: case 0x9: /* block transfer */ | |
1388 | if (bit (this_instr, 20)) | |
1389 | { | |
1390 | /* LDM */ | |
1391 | if (bit (this_instr, 15)) | |
1392 | { | |
1393 | /* loading pc */ | |
1394 | int offset = 0; | |
1395 | ||
1396 | if (bit (this_instr, 23)) | |
1397 | { | |
1398 | /* up */ | |
1399 | unsigned long reglist = bits (this_instr, 0, 14); | |
1400 | offset = bitcount (reglist) * 4; | |
1401 | if (bit (this_instr, 24)) /* pre */ | |
1402 | offset += 4; | |
1403 | } | |
1404 | else if (bit (this_instr, 24)) | |
1405 | offset = -4; | |
1406 | ||
1407 | { | |
1408 | unsigned long rn_val = | |
1409 | read_register (bits (this_instr, 16, 19)); | |
1410 | nextpc = | |
1411 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
1412 | + offset), | |
1413 | 4); | |
1414 | } | |
1415 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1416 | if (nextpc == pc) | |
1417 | error ("Infinite loop detected"); | |
1418 | } | |
1419 | } | |
1420 | break; | |
1421 | ||
1422 | case 0xb: /* branch & link */ | |
1423 | case 0xa: /* branch */ | |
1424 | { | |
1425 | nextpc = BranchDest (pc, this_instr); | |
1426 | ||
1427 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1428 | if (nextpc == pc) | |
1429 | error ("Infinite loop detected"); | |
1430 | break; | |
1431 | } | |
1432 | ||
1433 | case 0xc: case 0xd: | |
1434 | case 0xe: /* coproc ops */ | |
1435 | case 0xf: /* SWI */ | |
1436 | break; | |
1437 | ||
1438 | default: | |
1439 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1440 | return (pc); | |
1441 | } | |
1442 | } | |
1443 | ||
1444 | return nextpc; | |
1445 | } | |
1446 | ||
1447 | #include "bfd-in2.h" | |
1448 | #include "libcoff.h" | |
1449 | ||
1450 | static int | |
1451 | gdb_print_insn_arm (memaddr, info) | |
1452 | bfd_vma memaddr; | |
1453 | disassemble_info * info; | |
1454 | { | |
1455 | if (arm_pc_is_thumb (memaddr)) | |
1456 | { | |
1457 | static asymbol * asym; | |
1458 | static combined_entry_type ce; | |
1459 | static struct coff_symbol_struct csym; | |
1460 | static struct _bfd fake_bfd; | |
1461 | static bfd_target fake_target; | |
1462 | ||
1463 | if (csym.native == NULL) | |
1464 | { | |
1465 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1466 | solely so that the code in print_insn_little_arm() and | |
1467 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1468 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
1469 | ||
1470 | fake_target.flavour = bfd_target_coff_flavour; | |
1471 | fake_bfd.xvec = & fake_target; | |
1472 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
1473 | csym.native = & ce; | |
1474 | csym.symbol.the_bfd = & fake_bfd; | |
1475 | csym.symbol.name = "fake"; | |
1476 | asym = (asymbol *) & csym; | |
1477 | } | |
1478 | ||
1479 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
1480 | info->symbols = & asym; | |
1481 | } | |
1482 | else | |
1483 | info->symbols = NULL; | |
1484 | ||
1485 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1486 | return print_insn_big_arm (memaddr, info); | |
1487 | else | |
1488 | return print_insn_little_arm (memaddr, info); | |
1489 | } | |
1490 | ||
1491 | /* Sequence of bytes for breakpoint instruction. */ | |
1492 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} /* Recognized illegal opcodes */ | |
1493 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
1494 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
1495 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
1496 | ||
1497 | /* The following has been superseded by BREAKPOINT_FOR_PC, but | |
1498 | is defined merely to keep mem-break.c happy. */ | |
1499 | #define LITTLE_BREAKPOINT ARM_LE_BREAKPOINT | |
1500 | #define BIG_BREAKPOINT ARM_BE_BREAKPOINT | |
1501 | ||
1502 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
1503 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
1504 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
1505 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
1506 | (if necessary) to point to the actual memory location where the | |
1507 | breakpoint should be inserted. */ | |
1508 | ||
1509 | unsigned char * | |
1510 | arm_breakpoint_from_pc (pcptr, lenptr) | |
1511 | CORE_ADDR * pcptr; | |
1512 | int * lenptr; | |
1513 | { | |
1514 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
1515 | { | |
1516 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1517 | { | |
1518 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1519 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1520 | *lenptr = sizeof (thumb_breakpoint); | |
1521 | return thumb_breakpoint; | |
1522 | } | |
1523 | else | |
1524 | { | |
1525 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1526 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1527 | *lenptr = sizeof (thumb_breakpoint); | |
1528 | return thumb_breakpoint; | |
1529 | } | |
1530 | } | |
1531 | else | |
1532 | { | |
1533 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1534 | { | |
1535 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
1536 | *lenptr = sizeof (arm_breakpoint); | |
1537 | return arm_breakpoint; | |
1538 | } | |
1539 | else | |
1540 | { | |
1541 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
1542 | *lenptr = sizeof (arm_breakpoint); | |
1543 | return arm_breakpoint; | |
1544 | } | |
1545 | } | |
1546 | } | |
1547 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
1548 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
1549 | ||
1550 | int | |
1551 | arm_in_call_stub (pc, name) | |
1552 | CORE_ADDR pc; | |
1553 | char * name; | |
1554 | { | |
1555 | CORE_ADDR start_addr; | |
1556 | ||
1557 | /* Find the starting address of the function containing the PC. If the | |
1558 | caller didn't give us a name, look it up at the same time. */ | |
1559 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
1560 | return 0; | |
1561 | ||
1562 | return strncmp (name, "_call_via_r", 11) == 0; | |
1563 | } | |
1564 | ||
1565 | ||
1566 | /* If PC is in a Thumb call or return stub, return the address of the target | |
1567 | PC, which is in a register. The thunk functions are called _called_via_xx, | |
1568 | where x is the register name. The possible names are r0-r9, sl, fp, ip, | |
1569 | sp, and lr. */ | |
1570 | ||
1571 | CORE_ADDR | |
1572 | arm_skip_stub (pc) | |
1573 | CORE_ADDR pc; | |
1574 | { | |
1575 | char * name; | |
1576 | CORE_ADDR start_addr; | |
1577 | ||
1578 | /* Find the starting address and name of the function containing the PC. */ | |
1579 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1580 | return 0; | |
1581 | ||
1582 | /* Call thunks always start with "_call_via_". */ | |
1583 | if (strncmp (name, "_call_via_", 10) == 0) | |
1584 | { | |
1585 | /* Use the name suffix to determine which register contains | |
1586 | the target PC. */ | |
1587 | static char *table[15] = | |
1588 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1589 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
1590 | }; | |
1591 | int regno; | |
1592 | ||
1593 | for (regno = 0; regno <= 14; regno++) | |
1594 | if (strcmp (&name[10], table[regno]) == 0) | |
1595 | return read_register (regno); | |
1596 | } | |
1597 | return 0; /* not a stub */ | |
1598 | } | |
1599 | ||
1600 | ||
1601 | void | |
1602 | _initialize_arm_tdep () | |
1603 | { | |
1604 | tm_print_insn = gdb_print_insn_arm; | |
1605 | ||
1606 | add_com ("othernames", class_obscure, arm_othernames, | |
1607 | "Switch to the other set of register names."); | |
1608 | ||
1609 | /* ??? Maybe this should be a boolean. */ | |
1610 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
1611 | var_zinteger, (char *)&arm_apcs_32, | |
1612 | "Set usage of ARM 32-bit mode.\n", &setlist), | |
1613 | & showlist); | |
1614 | ||
1615 | } | |
1616 | ||
1617 | /* Test whether the coff symbol specific value corresponds to a Thumb function */ | |
1618 | int | |
1619 | coff_sym_is_thumb(int val) | |
1620 | { | |
1621 | return (val == C_THUMBEXT || | |
1622 | val == C_THUMBSTAT || | |
1623 | val == C_THUMBEXTFUNC || | |
1624 | val == C_THUMBSTATFUNC || | |
1625 | val == C_THUMBLABEL); | |
1626 | } |