Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
3666a048 | 3 | Copyright (C) 1988-2021 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
82ca8957 | 41 | #include "dwarf2/frame.h" |
4de283e4 TT |
42 | #include "gdbtypes.h" |
43 | #include "prologue-value.h" | |
44 | #include "remote.h" | |
45 | #include "target-descriptions.h" | |
46 | #include "user-regs.h" | |
47 | #include "observable.h" | |
5f661e03 | 48 | #include "count-one-bits.h" |
4de283e4 | 49 | |
d55e5aa6 | 50 | #include "arch/arm.h" |
4de283e4 | 51 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 52 | #include "arm-tdep.h" |
4de283e4 TT |
53 | #include "gdb/sim-arm.h" |
54 | ||
d55e5aa6 | 55 | #include "elf-bfd.h" |
4de283e4 | 56 | #include "coff/internal.h" |
d55e5aa6 | 57 | #include "elf/arm.h" |
4de283e4 | 58 | |
4de283e4 TT |
59 | #include "record.h" |
60 | #include "record-full.h" | |
61 | #include <algorithm> | |
62 | ||
c2fd7fae AKS |
63 | #include "producer.h" |
64 | ||
b121eeb9 | 65 | #if GDB_SELF_TEST |
268a13a5 | 66 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
67 | #endif |
68 | ||
491144b5 | 69 | static bool arm_debug; |
6529d2dd | 70 | |
7cb6d92a SM |
71 | /* Print an "arm" debug statement. */ |
72 | ||
73 | #define arm_debug_printf(fmt, ...) \ | |
74 | debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__) | |
75 | ||
082fc60d RE |
76 | /* Macros for setting and testing a bit in a minimal symbol that marks |
77 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 78 | is used for this purpose. |
082fc60d RE |
79 | |
80 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 81 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 82 | |
0963b4bd | 83 | #define MSYMBOL_SET_SPECIAL(msym) \ |
b887350f | 84 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
85 | |
86 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 87 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 88 | |
60c5725c DJ |
89 | struct arm_mapping_symbol |
90 | { | |
227031b2 | 91 | CORE_ADDR value; |
60c5725c | 92 | char type; |
54cc7474 SM |
93 | |
94 | bool operator< (const arm_mapping_symbol &other) const | |
95 | { return this->value < other.value; } | |
60c5725c | 96 | }; |
54cc7474 SM |
97 | |
98 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 99 | |
bd5766ec | 100 | struct arm_per_bfd |
60c5725c | 101 | { |
bd5766ec | 102 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
103 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
104 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
105 | {} |
106 | ||
bd5766ec | 107 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
108 | |
109 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
110 | ||
111 | The format is an array of vectors of arm_mapping_symbols, there is one | |
112 | vector for each section of the objfile (the array is index by BFD section | |
113 | index). | |
114 | ||
115 | For each section, the vector of arm_mapping_symbol is sorted by | |
116 | symbol value (address). */ | |
117 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
118 | |
119 | /* For each corresponding element of section_maps above, is this vector | |
120 | sorted. */ | |
121 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
122 | }; |
123 | ||
bd5766ec LM |
124 | /* Per-bfd data used for mapping symbols. */ |
125 | static bfd_key<arm_per_bfd> arm_bfd_data_key; | |
1b7f24cd | 126 | |
afd7eef0 RE |
127 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
128 | static struct cmd_list_element *setarmcmdlist = NULL; | |
129 | static struct cmd_list_element *showarmcmdlist = NULL; | |
130 | ||
fd50bc42 RE |
131 | /* The type of floating-point to use. Keep this in sync with enum |
132 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 133 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
134 | { |
135 | "auto", | |
136 | "softfpa", | |
137 | "fpa", | |
138 | "softvfp", | |
28e97307 DJ |
139 | "vfp", |
140 | NULL | |
fd50bc42 RE |
141 | }; |
142 | ||
143 | /* A variable that can be configured by the user. */ | |
144 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
145 | static const char *current_fp_model = "auto"; | |
146 | ||
28e97307 | 147 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 148 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
149 | { |
150 | "auto", | |
151 | "APCS", | |
152 | "AAPCS", | |
153 | NULL | |
154 | }; | |
155 | ||
156 | /* A variable that can be configured by the user. */ | |
157 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
158 | static const char *arm_abi_string = "auto"; | |
159 | ||
0428b8f5 | 160 | /* The execution mode to assume. */ |
40478521 | 161 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
162 | { |
163 | "auto", | |
164 | "arm", | |
68770265 MGD |
165 | "thumb", |
166 | NULL | |
0428b8f5 DJ |
167 | }; |
168 | ||
169 | static const char *arm_fallback_mode_string = "auto"; | |
170 | static const char *arm_force_mode_string = "auto"; | |
171 | ||
f32bf4a4 YQ |
172 | /* The standard register names, and all the valid aliases for them. Note |
173 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
174 | have been added as builtin user registers in | |
175 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
176 | static const struct |
177 | { | |
178 | const char *name; | |
179 | int regnum; | |
180 | } arm_register_aliases[] = { | |
181 | /* Basic register numbers. */ | |
182 | { "r0", 0 }, | |
183 | { "r1", 1 }, | |
184 | { "r2", 2 }, | |
185 | { "r3", 3 }, | |
186 | { "r4", 4 }, | |
187 | { "r5", 5 }, | |
188 | { "r6", 6 }, | |
189 | { "r7", 7 }, | |
190 | { "r8", 8 }, | |
191 | { "r9", 9 }, | |
192 | { "r10", 10 }, | |
193 | { "r11", 11 }, | |
194 | { "r12", 12 }, | |
195 | { "r13", 13 }, | |
196 | { "r14", 14 }, | |
197 | { "r15", 15 }, | |
198 | /* Synonyms (argument and variable registers). */ | |
199 | { "a1", 0 }, | |
200 | { "a2", 1 }, | |
201 | { "a3", 2 }, | |
202 | { "a4", 3 }, | |
203 | { "v1", 4 }, | |
204 | { "v2", 5 }, | |
205 | { "v3", 6 }, | |
206 | { "v4", 7 }, | |
207 | { "v5", 8 }, | |
208 | { "v6", 9 }, | |
209 | { "v7", 10 }, | |
210 | { "v8", 11 }, | |
211 | /* Other platform-specific names for r9. */ | |
212 | { "sb", 9 }, | |
213 | { "tr", 9 }, | |
214 | /* Special names. */ | |
215 | { "ip", 12 }, | |
123dc839 | 216 | { "lr", 14 }, |
123dc839 DJ |
217 | /* Names used by GCC (not listed in the ARM EABI). */ |
218 | { "sl", 10 }, | |
123dc839 DJ |
219 | /* A special name from the older ATPCS. */ |
220 | { "wr", 7 }, | |
221 | }; | |
bc90b915 | 222 | |
123dc839 | 223 | static const char *const arm_register_names[] = |
da59e081 JM |
224 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
225 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
226 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
227 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
228 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
229 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 230 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 231 | |
65b48a81 PB |
232 | /* Holds the current set of options to be passed to the disassembler. */ |
233 | static char *arm_disassembler_options; | |
234 | ||
afd7eef0 RE |
235 | /* Valid register name styles. */ |
236 | static const char **valid_disassembly_styles; | |
ed9a39eb | 237 | |
afd7eef0 RE |
238 | /* Disassembly style to use. Default to "std" register names. */ |
239 | static const char *disassembly_style; | |
96baa820 | 240 | |
d105cce5 AH |
241 | /* All possible arm target descriptors. */ |
242 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID]; | |
243 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; | |
244 | ||
ed9a39eb | 245 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 246 | style. */ |
eb4c3f4a | 247 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 248 | struct cmd_list_element *); |
65b48a81 PB |
249 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
250 | struct cmd_list_element *, | |
251 | const char *); | |
ed9a39eb | 252 | |
05d1431c | 253 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 254 | readable_regcache *regcache, |
05d1431c | 255 | int regnum, gdb_byte *buf); |
58d6951d DJ |
256 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
257 | struct regcache *regcache, | |
258 | int regnum, const gdb_byte *buf); | |
259 | ||
e7cf25a8 | 260 | static CORE_ADDR |
553cb527 | 261 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
262 | |
263 | ||
d9311bfa AT |
264 | /* get_next_pcs operations. */ |
265 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
266 | arm_get_next_pcs_read_memory_unsigned_integer, | |
267 | arm_get_next_pcs_syscall_next_pc, | |
268 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
269 | arm_get_next_pcs_is_thumb, |
270 | NULL, | |
d9311bfa AT |
271 | }; |
272 | ||
9b8d791a | 273 | struct arm_prologue_cache |
c3b4394c | 274 | { |
eb5492fa DJ |
275 | /* The stack pointer at the time this frame was created; i.e. the |
276 | caller's stack pointer when this function was called. It is used | |
277 | to identify this frame. */ | |
278 | CORE_ADDR prev_sp; | |
279 | ||
4be43953 DJ |
280 | /* The frame base for this frame is just prev_sp - frame size. |
281 | FRAMESIZE is the distance from the frame pointer to the | |
282 | initial stack pointer. */ | |
eb5492fa | 283 | |
c3b4394c | 284 | int framesize; |
eb5492fa DJ |
285 | |
286 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 287 | int framereg; |
eb5492fa DJ |
288 | |
289 | /* Saved register offsets. */ | |
098caef4 | 290 | trad_frame_saved_reg *saved_regs; |
c3b4394c | 291 | }; |
ed9a39eb | 292 | |
9ecab40c SM |
293 | namespace { |
294 | ||
295 | /* Abstract class to read ARM instructions from memory. */ | |
296 | ||
297 | class arm_instruction_reader | |
298 | { | |
299 | public: | |
2c5b1849 | 300 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
301 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
302 | }; | |
303 | ||
304 | /* Read instructions from target memory. */ | |
305 | ||
306 | class target_arm_instruction_reader : public arm_instruction_reader | |
307 | { | |
308 | public: | |
309 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
310 | { | |
311 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
312 | } | |
313 | }; | |
314 | ||
315 | } /* namespace */ | |
316 | ||
317 | static CORE_ADDR arm_analyze_prologue | |
318 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
319 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 320 | |
cca44b1b JB |
321 | /* Architecture version for displaced stepping. This effects the behaviour of |
322 | certain instructions, and really should not be hard-wired. */ | |
323 | ||
324 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
325 | ||
c7ae7675 | 326 | /* See arm-tdep.h. */ |
c906108c | 327 | |
491144b5 | 328 | bool arm_apcs_32 = true; |
c906108c | 329 | |
9779414d DJ |
330 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
331 | ||
478fd957 | 332 | int |
9779414d DJ |
333 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
334 | { | |
335 | if (gdbarch_tdep (gdbarch)->is_m) | |
336 | return XPSR_T; | |
337 | else | |
338 | return CPSR_T; | |
339 | } | |
340 | ||
d0e59a68 AT |
341 | /* Determine if the processor is currently executing in Thumb mode. */ |
342 | ||
343 | int | |
344 | arm_is_thumb (struct regcache *regcache) | |
345 | { | |
346 | ULONGEST cpsr; | |
ac7936df | 347 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
348 | |
349 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
350 | ||
351 | return (cpsr & t_bit) != 0; | |
352 | } | |
353 | ||
b39cc962 DJ |
354 | /* Determine if FRAME is executing in Thumb mode. */ |
355 | ||
25b41d01 | 356 | int |
b39cc962 DJ |
357 | arm_frame_is_thumb (struct frame_info *frame) |
358 | { | |
359 | CORE_ADDR cpsr; | |
9779414d | 360 | ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); |
b39cc962 DJ |
361 | |
362 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
363 | directly (from a signal frame or dummy frame) or by interpreting | |
364 | the saved LR (from a prologue or DWARF frame). So consult it and | |
365 | trust the unwinders. */ | |
366 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
367 | ||
9779414d | 368 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
369 | } |
370 | ||
f9d67f43 DJ |
371 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
372 | return its type. Otherwise, return 0. If START is non-NULL, | |
373 | set *START to the location of the mapping symbol. */ | |
c906108c | 374 | |
f9d67f43 DJ |
375 | static char |
376 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 377 | { |
60c5725c | 378 | struct obj_section *sec; |
0428b8f5 | 379 | |
60c5725c DJ |
380 | /* If there are mapping symbols, consult them. */ |
381 | sec = find_pc_section (memaddr); | |
382 | if (sec != NULL) | |
383 | { | |
bd5766ec | 384 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd); |
60c5725c DJ |
385 | if (data != NULL) |
386 | { | |
4838e44c SM |
387 | unsigned int section_idx = sec->the_bfd_section->index; |
388 | arm_mapping_symbol_vec &map | |
389 | = data->section_maps[section_idx]; | |
390 | ||
391 | /* Sort the vector on first use. */ | |
392 | if (!data->section_maps_sorted[section_idx]) | |
393 | { | |
394 | std::sort (map.begin (), map.end ()); | |
395 | data->section_maps_sorted[section_idx] = true; | |
396 | } | |
397 | ||
54cc7474 SM |
398 | struct arm_mapping_symbol map_key |
399 | = { memaddr - obj_section_addr (sec), 0 }; | |
54cc7474 SM |
400 | arm_mapping_symbol_vec::const_iterator it |
401 | = std::lower_bound (map.begin (), map.end (), map_key); | |
402 | ||
403 | /* std::lower_bound finds the earliest ordered insertion | |
404 | point. If the symbol at this position starts at this exact | |
405 | address, we use that; otherwise, the preceding | |
406 | mapping symbol covers this address. */ | |
407 | if (it < map.end ()) | |
60c5725c | 408 | { |
54cc7474 | 409 | if (it->value == map_key.value) |
60c5725c | 410 | { |
f9d67f43 | 411 | if (start) |
54cc7474 SM |
412 | *start = it->value + obj_section_addr (sec); |
413 | return it->type; | |
60c5725c DJ |
414 | } |
415 | } | |
54cc7474 SM |
416 | |
417 | if (it > map.begin ()) | |
418 | { | |
419 | arm_mapping_symbol_vec::const_iterator prev_it | |
420 | = it - 1; | |
421 | ||
422 | if (start) | |
423 | *start = prev_it->value + obj_section_addr (sec); | |
424 | return prev_it->type; | |
425 | } | |
60c5725c DJ |
426 | } |
427 | } | |
428 | ||
f9d67f43 DJ |
429 | return 0; |
430 | } | |
431 | ||
432 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
433 | function. This function should be called for addresses unrelated to | |
434 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
435 | ||
e3039479 | 436 | int |
9779414d | 437 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 438 | { |
7cbd4a93 | 439 | struct bound_minimal_symbol sym; |
f9d67f43 | 440 | char type; |
187b041e SM |
441 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
442 | ||
443 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
444 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
445 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
446 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
447 | |
448 | /* If checking the mode of displaced instruction in copy area, the mode | |
449 | should be determined by instruction on the original address. */ | |
450 | if (dsc) | |
451 | { | |
136821d9 SM |
452 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
453 | (unsigned long) dsc->insn_addr, | |
454 | (unsigned long) memaddr); | |
a42244db YQ |
455 | memaddr = dsc->insn_addr; |
456 | } | |
f9d67f43 DJ |
457 | |
458 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
459 | if (IS_THUMB_ADDR (memaddr)) | |
460 | return 1; | |
461 | ||
462 | /* If the user wants to override the symbol table, let him. */ | |
463 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
464 | return 0; | |
465 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
466 | return 1; | |
467 | ||
9779414d DJ |
468 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
469 | if (gdbarch_tdep (gdbarch)->is_m) | |
470 | return 1; | |
471 | ||
f9d67f43 DJ |
472 | /* If there are mapping symbols, consult them. */ |
473 | type = arm_find_mapping_symbol (memaddr, NULL); | |
474 | if (type) | |
475 | return type == 't'; | |
476 | ||
ed9a39eb | 477 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 478 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
479 | if (sym.minsym) |
480 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
481 | |
482 | /* If the user wants to override the fallback mode, let them. */ | |
483 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
484 | return 0; | |
485 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
486 | return 1; | |
487 | ||
488 | /* If we couldn't find any symbol, but we're talking to a running | |
489 | target, then trust the current value of $cpsr. This lets | |
490 | "display/i $pc" always show the correct mode (though if there is | |
491 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 492 | displayed in the mode it will be executed). */ |
9dccd06e | 493 | if (target_has_registers ()) |
18819fa6 | 494 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
495 | |
496 | /* Otherwise we're out of luck; we assume ARM. */ | |
497 | return 0; | |
c906108c SS |
498 | } |
499 | ||
ca90e760 | 500 | /* Determine if the address specified equals any of these magic return |
55ea94da | 501 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
ca90e760 FH |
502 | architectures. |
503 | ||
504 | From ARMv6-M Reference Manual B1.5.8 | |
505 | Table B1-5 Exception return behavior | |
506 | ||
507 | EXC_RETURN Return To Return Stack | |
508 | 0xFFFFFFF1 Handler mode Main | |
509 | 0xFFFFFFF9 Thread mode Main | |
510 | 0xFFFFFFFD Thread mode Process | |
511 | ||
512 | From ARMv7-M Reference Manual B1.5.8 | |
513 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
514 | ||
515 | EXC_RETURN Return To Return Stack | |
516 | 0xFFFFFFF1 Handler mode Main | |
517 | 0xFFFFFFF9 Thread mode Main | |
518 | 0xFFFFFFFD Thread mode Process | |
519 | ||
520 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
521 | FP | |
522 | ||
523 | EXC_RETURN Return To Return Stack Frame Type | |
524 | 0xFFFFFFE1 Handler mode Main Extended | |
525 | 0xFFFFFFE9 Thread mode Main Extended | |
526 | 0xFFFFFFED Thread mode Process Extended | |
527 | 0xFFFFFFF1 Handler mode Main Basic | |
528 | 0xFFFFFFF9 Thread mode Main Basic | |
529 | 0xFFFFFFFD Thread mode Process Basic | |
530 | ||
531 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
532 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
533 | ||
534 | In the ARMv8-M Architecture Technical Reference also adds | |
535 | for implementations without the Security Extension: | |
536 | ||
537 | EXC_RETURN Condition | |
538 | 0xFFFFFFB0 Return to Handler mode. | |
539 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
540 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
541 | |
542 | static int | |
543 | arm_m_addr_is_magic (CORE_ADDR addr) | |
544 | { | |
545 | switch (addr) | |
546 | { | |
55ea94da FH |
547 | /* Values from ARMv8-M Architecture Technical Reference. */ |
548 | case 0xffffffb0: | |
549 | case 0xffffffb8: | |
550 | case 0xffffffbc: | |
ca90e760 FH |
551 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of |
552 | the exception return behavior. */ | |
553 | case 0xffffffe1: | |
554 | case 0xffffffe9: | |
555 | case 0xffffffed: | |
556 | case 0xfffffff1: | |
557 | case 0xfffffff9: | |
558 | case 0xfffffffd: | |
559 | /* Address is magic. */ | |
560 | return 1; | |
561 | ||
562 | default: | |
563 | /* Address is not magic. */ | |
564 | return 0; | |
565 | } | |
566 | } | |
567 | ||
181c1381 | 568 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 569 | static CORE_ADDR |
24568a2c | 570 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 571 | { |
2ae28aa9 YQ |
572 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
573 | (the magic exception return address). */ | |
574 | if (gdbarch_tdep (gdbarch)->is_m | |
ca90e760 | 575 | && arm_m_addr_is_magic (val)) |
2ae28aa9 YQ |
576 | return val; |
577 | ||
a3a2ee65 | 578 | if (arm_apcs_32) |
dd6be234 | 579 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 580 | else |
a3a2ee65 | 581 | return (val & 0x03fffffc); |
c906108c SS |
582 | } |
583 | ||
0d39a070 | 584 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
585 | can be safely ignored during prologue skipping. IS_THUMB is true |
586 | if the function is known to be a Thumb function due to the way it | |
587 | is being called. */ | |
0d39a070 | 588 | static int |
e0634ccf | 589 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 590 | { |
e0634ccf | 591 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 592 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
593 | |
594 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 595 | if (msym.minsym != NULL |
77e371c0 | 596 | && BMSYMBOL_VALUE_ADDRESS (msym) == pc |
c9d95fa3 | 597 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 598 | { |
c9d95fa3 | 599 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 600 | |
e0634ccf UW |
601 | /* The GNU linker's Thumb call stub to foo is named |
602 | __foo_from_thumb. */ | |
603 | if (strstr (name, "_from_thumb") != NULL) | |
604 | name += 2; | |
0d39a070 | 605 | |
e0634ccf UW |
606 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
607 | arguments to their argument types in non-prototyped | |
608 | functions. */ | |
61012eef | 609 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 610 | return 1; |
61012eef | 611 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 612 | return 1; |
0d39a070 | 613 | |
e0634ccf | 614 | /* Internal functions related to thread-local storage. */ |
61012eef | 615 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 616 | return 1; |
61012eef | 617 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
618 | return 1; |
619 | } | |
620 | else | |
621 | { | |
622 | /* If we run against a stripped glibc, we may be unable to identify | |
623 | special functions by name. Check for one important case, | |
624 | __aeabi_read_tp, by comparing the *code* against the default | |
625 | implementation (this is hand-written ARM assembler in glibc). */ | |
626 | ||
627 | if (!is_thumb | |
198cd59d | 628 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 629 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 630 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
631 | == 0xe240f01f) /* sub pc, r0, #31 */ |
632 | return 1; | |
633 | } | |
ec3d575a | 634 | |
0d39a070 DJ |
635 | return 0; |
636 | } | |
637 | ||
621c6d5b YQ |
638 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
639 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
640 | instruction. */ | |
641 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
642 | ((bits ((insn1), 0, 3) << 12) \ | |
643 | | (bits ((insn1), 10, 10) << 11) \ | |
644 | | (bits ((insn2), 12, 14) << 8) \ | |
645 | | bits ((insn2), 0, 7)) | |
646 | ||
647 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
648 | the 32-bit instruction. */ | |
649 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
650 | ((bits ((insn), 16, 19) << 12) \ | |
651 | | bits ((insn), 0, 11)) | |
652 | ||
ec3d575a UW |
653 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
654 | ||
655 | static unsigned int | |
656 | thumb_expand_immediate (unsigned int imm) | |
657 | { | |
658 | unsigned int count = imm >> 7; | |
659 | ||
660 | if (count < 8) | |
661 | switch (count / 2) | |
662 | { | |
663 | case 0: | |
664 | return imm & 0xff; | |
665 | case 1: | |
666 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
667 | case 2: | |
668 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
669 | case 3: | |
670 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
671 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
672 | } | |
673 | ||
674 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
675 | } | |
676 | ||
540314bd YQ |
677 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
678 | epilogue, 0 otherwise. */ | |
679 | ||
680 | static int | |
681 | thumb_instruction_restores_sp (unsigned short insn) | |
682 | { | |
683 | return (insn == 0x46bd /* mov sp, r7 */ | |
684 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
685 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
686 | } | |
687 | ||
29d73ae4 DJ |
688 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
689 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
690 | clobber the stack frame unexpectedly, or an unknown instruction. |
691 | Return the last address which is definitely safe to skip for an | |
692 | initial breakpoint. */ | |
c906108c SS |
693 | |
694 | static CORE_ADDR | |
29d73ae4 DJ |
695 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
696 | CORE_ADDR start, CORE_ADDR limit, | |
697 | struct arm_prologue_cache *cache) | |
c906108c | 698 | { |
0d39a070 | 699 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 700 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
701 | int i; |
702 | pv_t regs[16]; | |
29d73ae4 | 703 | CORE_ADDR offset; |
ec3d575a | 704 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 705 | |
29d73ae4 DJ |
706 | for (i = 0; i < 16; i++) |
707 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 708 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 709 | |
29d73ae4 | 710 | while (start < limit) |
c906108c | 711 | { |
29d73ae4 DJ |
712 | unsigned short insn; |
713 | ||
198cd59d | 714 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 715 | |
94c30b78 | 716 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 717 | { |
29d73ae4 DJ |
718 | int regno; |
719 | int mask; | |
4be43953 | 720 | |
f7b7ed97 | 721 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 722 | break; |
29d73ae4 DJ |
723 | |
724 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
725 | whether to save LR (R14). */ | |
726 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
727 | ||
728 | /* Calculate offsets of saved R0-R7 and LR. */ | |
729 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
730 | if (mask & (1 << regno)) | |
731 | { | |
29d73ae4 DJ |
732 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
733 | -4); | |
f7b7ed97 | 734 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 735 | } |
da59e081 | 736 | } |
1db01f22 | 737 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 738 | { |
29d73ae4 | 739 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
740 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
741 | -offset); | |
da59e081 | 742 | } |
808f7ab1 YQ |
743 | else if (thumb_instruction_restores_sp (insn)) |
744 | { | |
745 | /* Don't scan past the epilogue. */ | |
746 | break; | |
747 | } | |
0d39a070 DJ |
748 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
749 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
750 | (insn & 0xff) << 2); | |
751 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
752 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
753 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
754 | bits (insn, 6, 8)); | |
755 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
756 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
757 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
758 | bits (insn, 0, 7)); | |
759 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
760 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
761 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
762 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
763 | regs[bits (insn, 6, 8)]); | |
764 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
765 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
766 | { | |
767 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
768 | int rm = bits (insn, 3, 6); | |
769 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
770 | } | |
29d73ae4 | 771 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 772 | { |
29d73ae4 DJ |
773 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
774 | int src_reg = (insn & 0x78) >> 3; | |
775 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 776 | } |
29d73ae4 | 777 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 778 | { |
29d73ae4 DJ |
779 | /* Handle stores to the stack. Normally pushes are used, |
780 | but with GCC -mtpcs-frame, there may be other stores | |
781 | in the prologue to create the frame. */ | |
782 | int regno = (insn >> 8) & 0x7; | |
783 | pv_t addr; | |
784 | ||
785 | offset = (insn & 0xff) << 2; | |
786 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
787 | ||
f7b7ed97 | 788 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
789 | break; |
790 | ||
f7b7ed97 | 791 | stack.store (addr, 4, regs[regno]); |
da59e081 | 792 | } |
0d39a070 DJ |
793 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
794 | { | |
795 | int rd = bits (insn, 0, 2); | |
796 | int rn = bits (insn, 3, 5); | |
797 | pv_t addr; | |
798 | ||
799 | offset = bits (insn, 6, 10) << 2; | |
800 | addr = pv_add_constant (regs[rn], offset); | |
801 | ||
f7b7ed97 | 802 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
803 | break; |
804 | ||
f7b7ed97 | 805 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
806 | } |
807 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
808 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
809 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
810 | /* Ignore stores of argument registers to the stack. */ | |
811 | ; | |
812 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
813 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
814 | /* Ignore block loads from the stack, potentially copying | |
815 | parameters from memory. */ | |
816 | ; | |
817 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
818 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
819 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
820 | /* Similarly ignore single loads from the stack. */ | |
821 | ; | |
822 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
823 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
824 | /* Skip register copies, i.e. saves to another register | |
825 | instead of the stack. */ | |
826 | ; | |
827 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
828 | /* Recognize constant loads; even with small stacks these are necessary | |
829 | on Thumb. */ | |
830 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
831 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
832 | { | |
833 | /* Constant pool loads, for the same reason. */ | |
834 | unsigned int constant; | |
835 | CORE_ADDR loc; | |
836 | ||
837 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
838 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
839 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
840 | } | |
db24da6d | 841 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 842 | { |
0d39a070 DJ |
843 | unsigned short inst2; |
844 | ||
198cd59d YQ |
845 | inst2 = read_code_unsigned_integer (start + 2, 2, |
846 | byte_order_for_code); | |
0d39a070 DJ |
847 | |
848 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
849 | { | |
850 | /* BL, BLX. Allow some special function calls when | |
851 | skipping the prologue; GCC generates these before | |
852 | storing arguments to the stack. */ | |
853 | CORE_ADDR nextpc; | |
854 | int j1, j2, imm1, imm2; | |
855 | ||
856 | imm1 = sbits (insn, 0, 10); | |
857 | imm2 = bits (inst2, 0, 10); | |
858 | j1 = bit (inst2, 13); | |
859 | j2 = bit (inst2, 11); | |
860 | ||
861 | offset = ((imm1 << 12) + (imm2 << 1)); | |
862 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
863 | ||
864 | nextpc = start + 4 + offset; | |
865 | /* For BLX make sure to clear the low bits. */ | |
866 | if (bit (inst2, 12) == 0) | |
867 | nextpc = nextpc & 0xfffffffc; | |
868 | ||
e0634ccf UW |
869 | if (!skip_prologue_function (gdbarch, nextpc, |
870 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
871 | break; |
872 | } | |
ec3d575a | 873 | |
0963b4bd MS |
874 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
875 | { registers } */ | |
ec3d575a UW |
876 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
877 | { | |
878 | pv_t addr = regs[bits (insn, 0, 3)]; | |
879 | int regno; | |
880 | ||
f7b7ed97 | 881 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
882 | break; |
883 | ||
884 | /* Calculate offsets of saved registers. */ | |
885 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
886 | if (inst2 & (1 << regno)) | |
887 | { | |
888 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 889 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
890 | } |
891 | ||
892 | if (insn & 0x0020) | |
893 | regs[bits (insn, 0, 3)] = addr; | |
894 | } | |
895 | ||
0963b4bd MS |
896 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
897 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
898 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
899 | { | |
900 | int regno1 = bits (inst2, 12, 15); | |
901 | int regno2 = bits (inst2, 8, 11); | |
902 | pv_t addr = regs[bits (insn, 0, 3)]; | |
903 | ||
904 | offset = inst2 & 0xff; | |
905 | if (insn & 0x0080) | |
906 | addr = pv_add_constant (addr, offset); | |
907 | else | |
908 | addr = pv_add_constant (addr, -offset); | |
909 | ||
f7b7ed97 | 910 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
911 | break; |
912 | ||
f7b7ed97 TT |
913 | stack.store (addr, 4, regs[regno1]); |
914 | stack.store (pv_add_constant (addr, 4), | |
915 | 4, regs[regno2]); | |
ec3d575a UW |
916 | |
917 | if (insn & 0x0020) | |
918 | regs[bits (insn, 0, 3)] = addr; | |
919 | } | |
920 | ||
921 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
922 | && (inst2 & 0x0c00) == 0x0c00 | |
923 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
924 | { | |
925 | int regno = bits (inst2, 12, 15); | |
926 | pv_t addr = regs[bits (insn, 0, 3)]; | |
927 | ||
928 | offset = inst2 & 0xff; | |
929 | if (inst2 & 0x0200) | |
930 | addr = pv_add_constant (addr, offset); | |
931 | else | |
932 | addr = pv_add_constant (addr, -offset); | |
933 | ||
f7b7ed97 | 934 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
935 | break; |
936 | ||
f7b7ed97 | 937 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
938 | |
939 | if (inst2 & 0x0100) | |
940 | regs[bits (insn, 0, 3)] = addr; | |
941 | } | |
942 | ||
943 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
944 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
945 | { | |
946 | int regno = bits (inst2, 12, 15); | |
947 | pv_t addr; | |
948 | ||
949 | offset = inst2 & 0xfff; | |
950 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
951 | ||
f7b7ed97 | 952 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
953 | break; |
954 | ||
f7b7ed97 | 955 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
956 | } |
957 | ||
958 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 959 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 960 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 961 | ; |
ec3d575a UW |
962 | |
963 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
964 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 965 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 966 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 967 | ; |
ec3d575a | 968 | |
0963b4bd MS |
969 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
970 | { registers } */ | |
ec3d575a UW |
971 | && (inst2 & 0x8000) == 0x0000 |
972 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
973 | /* Ignore block loads from the stack, potentially copying | |
974 | parameters from memory. */ | |
0d39a070 | 975 | ; |
ec3d575a | 976 | |
f8c6d152 | 977 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 978 | [Rn, #+/-imm] */ |
0d39a070 | 979 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 980 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 981 | ; |
ec3d575a UW |
982 | |
983 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
984 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 985 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 986 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 987 | ; |
ec3d575a UW |
988 | |
989 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 990 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 991 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 992 | ; |
ec3d575a UW |
993 | |
994 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
995 | && (inst2 & 0x8000) == 0x0000) | |
996 | { | |
997 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
998 | | (bits (inst2, 12, 14) << 8) | |
999 | | bits (inst2, 0, 7)); | |
1000 | ||
1001 | regs[bits (inst2, 8, 11)] | |
1002 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1003 | thumb_expand_immediate (imm)); | |
1004 | } | |
1005 | ||
1006 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1007 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1008 | { |
ec3d575a UW |
1009 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1010 | | (bits (inst2, 12, 14) << 8) | |
1011 | | bits (inst2, 0, 7)); | |
1012 | ||
1013 | regs[bits (inst2, 8, 11)] | |
1014 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1015 | } | |
1016 | ||
1017 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1018 | && (inst2 & 0x8000) == 0x0000) | |
1019 | { | |
1020 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1021 | | (bits (inst2, 12, 14) << 8) | |
1022 | | bits (inst2, 0, 7)); | |
1023 | ||
1024 | regs[bits (inst2, 8, 11)] | |
1025 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1026 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1027 | } | |
1028 | ||
1029 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1030 | && (inst2 & 0x8000) == 0x0000) | |
1031 | { | |
1032 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1033 | | (bits (inst2, 12, 14) << 8) | |
1034 | | bits (inst2, 0, 7)); | |
1035 | ||
1036 | regs[bits (inst2, 8, 11)] | |
1037 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1038 | } | |
1039 | ||
1040 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1041 | { | |
1042 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1043 | | (bits (inst2, 12, 14) << 8) | |
1044 | | bits (inst2, 0, 7)); | |
1045 | ||
1046 | regs[bits (inst2, 8, 11)] | |
1047 | = pv_constant (thumb_expand_immediate (imm)); | |
1048 | } | |
1049 | ||
1050 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1051 | { | |
621c6d5b YQ |
1052 | unsigned int imm |
1053 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1054 | |
1055 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1056 | } | |
1057 | ||
1058 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1059 | && (inst2 & 0xf0f0) == 0) | |
1060 | { | |
1061 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1062 | int src_reg = inst2 & 0xf; | |
1063 | regs[dst_reg] = regs[src_reg]; | |
1064 | } | |
1065 | ||
1066 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1067 | { | |
1068 | /* Constant pool loads. */ | |
1069 | unsigned int constant; | |
1070 | CORE_ADDR loc; | |
1071 | ||
cac395ea | 1072 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1073 | if (insn & 0x0080) |
1074 | loc = start + 4 + offset; | |
1075 | else | |
1076 | loc = start + 4 - offset; | |
1077 | ||
1078 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1079 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1080 | } | |
1081 | ||
1082 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1083 | { | |
1084 | /* Constant pool loads. */ | |
1085 | unsigned int constant; | |
1086 | CORE_ADDR loc; | |
1087 | ||
cac395ea | 1088 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1089 | if (insn & 0x0080) |
1090 | loc = start + 4 + offset; | |
1091 | else | |
1092 | loc = start + 4 - offset; | |
1093 | ||
1094 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1095 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1096 | ||
1097 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1098 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1099 | } | |
1100 | ||
1101 | else if (thumb2_instruction_changes_pc (insn, inst2)) | |
1102 | { | |
1103 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1104 | break; |
1105 | } | |
ec3d575a UW |
1106 | else |
1107 | { | |
1108 | /* The optimizer might shove anything into the prologue, | |
1109 | so we just skip what we don't recognize. */ | |
1110 | unrecognized_pc = start; | |
1111 | } | |
0d39a070 DJ |
1112 | |
1113 | start += 2; | |
1114 | } | |
ec3d575a | 1115 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1116 | { |
ec3d575a | 1117 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1118 | break; |
3d74b771 | 1119 | } |
ec3d575a UW |
1120 | else |
1121 | { | |
1122 | /* The optimizer might shove anything into the prologue, | |
1123 | so we just skip what we don't recognize. */ | |
1124 | unrecognized_pc = start; | |
1125 | } | |
29d73ae4 DJ |
1126 | |
1127 | start += 2; | |
c906108c SS |
1128 | } |
1129 | ||
7cb6d92a SM |
1130 | arm_debug_printf ("Prologue scan stopped at %s", |
1131 | paddress (gdbarch, start)); | |
0d39a070 | 1132 | |
ec3d575a UW |
1133 | if (unrecognized_pc == 0) |
1134 | unrecognized_pc = start; | |
1135 | ||
29d73ae4 | 1136 | if (cache == NULL) |
f7b7ed97 | 1137 | return unrecognized_pc; |
29d73ae4 | 1138 | |
29d73ae4 DJ |
1139 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1140 | { | |
1141 | /* Frame pointer is fp. Frame size is constant. */ | |
1142 | cache->framereg = ARM_FP_REGNUM; | |
1143 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1144 | } | |
1145 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1146 | { | |
1147 | /* Frame pointer is r7. Frame size is constant. */ | |
1148 | cache->framereg = THUMB_FP_REGNUM; | |
1149 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1150 | } | |
72a2e3dc | 1151 | else |
29d73ae4 DJ |
1152 | { |
1153 | /* Try the stack pointer... this is a bit desperate. */ | |
1154 | cache->framereg = ARM_SP_REGNUM; | |
1155 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1156 | } | |
29d73ae4 DJ |
1157 | |
1158 | for (i = 0; i < 16; i++) | |
f7b7ed97 | 1159 | if (stack.find_reg (gdbarch, i, &offset)) |
098caef4 | 1160 | cache->saved_regs[i].set_addr (offset); |
29d73ae4 | 1161 | |
ec3d575a | 1162 | return unrecognized_pc; |
c906108c SS |
1163 | } |
1164 | ||
621c6d5b YQ |
1165 | |
1166 | /* Try to analyze the instructions starting from PC, which load symbol | |
1167 | __stack_chk_guard. Return the address of instruction after loading this | |
1168 | symbol, set the dest register number to *BASEREG, and set the size of | |
1169 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1170 | not recognized. */ | |
1171 | ||
1172 | static CORE_ADDR | |
1173 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1174 | unsigned int *destreg, int *offset) | |
1175 | { | |
1176 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1177 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1178 | unsigned int low, high, address; | |
1179 | ||
1180 | address = 0; | |
1181 | if (is_thumb) | |
1182 | { | |
1183 | unsigned short insn1 | |
198cd59d | 1184 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1185 | |
1186 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1187 | { | |
1188 | *destreg = bits (insn1, 8, 10); | |
1189 | *offset = 2; | |
6ae274b7 YQ |
1190 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1191 | address = read_memory_unsigned_integer (address, 4, | |
1192 | byte_order_for_code); | |
621c6d5b YQ |
1193 | } |
1194 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1195 | { | |
1196 | unsigned short insn2 | |
198cd59d | 1197 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1198 | |
1199 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1200 | ||
1201 | insn1 | |
198cd59d | 1202 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1203 | insn2 |
198cd59d | 1204 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1205 | |
1206 | /* movt Rd, #const */ | |
1207 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1208 | { | |
1209 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1210 | *destreg = bits (insn2, 8, 11); | |
1211 | *offset = 8; | |
1212 | address = (high << 16 | low); | |
1213 | } | |
1214 | } | |
1215 | } | |
1216 | else | |
1217 | { | |
2e9e421f | 1218 | unsigned int insn |
198cd59d | 1219 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1220 | |
6ae274b7 | 1221 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1222 | { |
6ae274b7 YQ |
1223 | address = bits (insn, 0, 11) + pc + 8; |
1224 | address = read_memory_unsigned_integer (address, 4, | |
1225 | byte_order_for_code); | |
1226 | ||
2e9e421f UW |
1227 | *destreg = bits (insn, 12, 15); |
1228 | *offset = 4; | |
1229 | } | |
1230 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1231 | { | |
1232 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1233 | ||
1234 | insn | |
198cd59d | 1235 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1236 | |
1237 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1238 | { | |
1239 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1240 | *destreg = bits (insn, 12, 15); | |
1241 | *offset = 8; | |
1242 | address = (high << 16 | low); | |
1243 | } | |
1244 | } | |
621c6d5b YQ |
1245 | } |
1246 | ||
1247 | return address; | |
1248 | } | |
1249 | ||
1250 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1251 | points to the first instruction of this sequence, return the address of |
1252 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1253 | |
1254 | On arm, this sequence of instructions is composed of mainly three steps, | |
1255 | Step 1: load symbol __stack_chk_guard, | |
1256 | Step 2: load from address of __stack_chk_guard, | |
1257 | Step 3: store it to somewhere else. | |
1258 | ||
1259 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1260 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1261 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1262 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1263 | they are, | |
1264 | ||
1265 | movw Rn, #:lower16:__stack_chk_guard | |
1266 | movt Rn, #:upper16:__stack_chk_guard | |
1267 | ||
1268 | On ARMv5t, it is, | |
1269 | ||
1270 | ldr Rn, .Label | |
1271 | .... | |
1272 | .Lable: | |
1273 | .word __stack_chk_guard | |
1274 | ||
1275 | Since ldr/str is a very popular instruction, we can't use them as | |
1276 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1277 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1278 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1279 | ||
1280 | static CORE_ADDR | |
1281 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1282 | { | |
1283 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1284 | unsigned int basereg; |
7cbd4a93 | 1285 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1286 | int offset; |
1287 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1288 | CORE_ADDR addr; | |
1289 | ||
1290 | /* Try to parse the instructions in Step 1. */ | |
1291 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1292 | &basereg, &offset); | |
1293 | if (!addr) | |
1294 | return pc; | |
1295 | ||
1296 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1297 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1298 | Otherwise, this sequence cannot be for stack protector. */ | |
1299 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1300 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1301 | return pc; |
1302 | ||
1303 | if (is_thumb) | |
1304 | { | |
1305 | unsigned int destreg; | |
1306 | unsigned short insn | |
198cd59d | 1307 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1308 | |
1309 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1310 | if ((insn & 0xf800) != 0x6800) | |
1311 | return pc; | |
1312 | if (bits (insn, 3, 5) != basereg) | |
1313 | return pc; | |
1314 | destreg = bits (insn, 0, 2); | |
1315 | ||
198cd59d YQ |
1316 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1317 | byte_order_for_code); | |
621c6d5b YQ |
1318 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1319 | if ((insn & 0xf800) != 0x6000) | |
1320 | return pc; | |
1321 | if (destreg != bits (insn, 0, 2)) | |
1322 | return pc; | |
1323 | } | |
1324 | else | |
1325 | { | |
1326 | unsigned int destreg; | |
1327 | unsigned int insn | |
198cd59d | 1328 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1329 | |
1330 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1331 | if ((insn & 0x0e500000) != 0x04100000) | |
1332 | return pc; | |
1333 | if (bits (insn, 16, 19) != basereg) | |
1334 | return pc; | |
1335 | destreg = bits (insn, 12, 15); | |
1336 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1337 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1338 | 4, byte_order_for_code); |
1339 | if ((insn & 0x0e500000) != 0x04000000) | |
1340 | return pc; | |
1341 | if (bits (insn, 12, 15) != destreg) | |
1342 | return pc; | |
1343 | } | |
1344 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1345 | on arm. */ | |
1346 | if (is_thumb) | |
1347 | return pc + offset + 4; | |
1348 | else | |
1349 | return pc + offset + 8; | |
1350 | } | |
1351 | ||
da3c6d4a MS |
1352 | /* Advance the PC across any function entry prologue instructions to |
1353 | reach some "real" code. | |
34e8f22d RE |
1354 | |
1355 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1356 | prologue: |
c906108c | 1357 | |
c5aa993b JM |
1358 | mov ip, sp |
1359 | [stmfd sp!, {a1,a2,a3,a4}] | |
1360 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1361 | [stfe f7, [sp, #-12]!] |
1362 | [stfe f6, [sp, #-12]!] | |
1363 | [stfe f5, [sp, #-12]!] | |
1364 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1365 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1366 | |
34e8f22d | 1367 | static CORE_ADDR |
6093d2eb | 1368 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1369 | { |
a89fea3c | 1370 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1371 | |
a89fea3c JL |
1372 | /* See if we can determine the end of the prologue via the symbol table. |
1373 | If so, then return either PC, or the PC after the prologue, whichever | |
1374 | is greater. */ | |
1375 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1376 | { |
d80b854b UW |
1377 | CORE_ADDR post_prologue_pc |
1378 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1379 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1380 | |
621c6d5b YQ |
1381 | if (post_prologue_pc) |
1382 | post_prologue_pc | |
1383 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1384 | ||
1385 | ||
0d39a070 DJ |
1386 | /* GCC always emits a line note before the prologue and another |
1387 | one after, even if the two are at the same address or on the | |
1388 | same line. Take advantage of this so that we do not need to | |
1389 | know every instruction that might appear in the prologue. We | |
1390 | will have producer information for most binaries; if it is | |
1391 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1392 | if (post_prologue_pc | |
43f3e411 DE |
1393 | && (cust == NULL |
1394 | || COMPUNIT_PRODUCER (cust) == NULL | |
61012eef | 1395 | || startswith (COMPUNIT_PRODUCER (cust), "GNU ") |
c2fd7fae | 1396 | || producer_is_llvm (COMPUNIT_PRODUCER (cust)))) |
0d39a070 DJ |
1397 | return post_prologue_pc; |
1398 | ||
a89fea3c | 1399 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1400 | { |
1401 | CORE_ADDR analyzed_limit; | |
1402 | ||
1403 | /* For non-GCC compilers, make sure the entire line is an | |
1404 | acceptable prologue; GDB will round this function's | |
1405 | return value up to the end of the following line so we | |
1406 | can not skip just part of a line (and we do not want to). | |
1407 | ||
1408 | RealView does not treat the prologue specially, but does | |
1409 | associate prologue code with the opening brace; so this | |
1410 | lets us skip the first line if we think it is the opening | |
1411 | brace. */ | |
9779414d | 1412 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1413 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1414 | post_prologue_pc, NULL); | |
1415 | else | |
9ecab40c SM |
1416 | analyzed_limit |
1417 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1418 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1419 | |
1420 | if (analyzed_limit != post_prologue_pc) | |
1421 | return func_addr; | |
1422 | ||
1423 | return post_prologue_pc; | |
1424 | } | |
c906108c SS |
1425 | } |
1426 | ||
a89fea3c JL |
1427 | /* Can't determine prologue from the symbol table, need to examine |
1428 | instructions. */ | |
c906108c | 1429 | |
a89fea3c JL |
1430 | /* Find an upper limit on the function prologue using the debug |
1431 | information. If the debug information could not be used to provide | |
1432 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1433 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1434 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1435 | if (limit_pc == 0) |
1436 | limit_pc = pc + 64; /* Magic. */ | |
1437 | ||
c906108c | 1438 | |
29d73ae4 | 1439 | /* Check if this is Thumb code. */ |
9779414d | 1440 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1441 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1442 | else |
9ecab40c SM |
1443 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1444 | target_arm_instruction_reader ()); | |
c906108c | 1445 | } |
94c30b78 | 1446 | |
c5aa993b | 1447 | /* *INDENT-OFF* */ |
c906108c SS |
1448 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1449 | This function decodes a Thumb function prologue to determine: | |
1450 | 1) the size of the stack frame | |
1451 | 2) which registers are saved on it | |
1452 | 3) the offsets of saved regs | |
1453 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1454 | |
da59e081 JM |
1455 | A typical Thumb function prologue would create this stack frame |
1456 | (offsets relative to FP) | |
c906108c SS |
1457 | old SP -> 24 stack parameters |
1458 | 20 LR | |
1459 | 16 R7 | |
1460 | R7 -> 0 local variables (16 bytes) | |
1461 | SP -> -12 additional stack space (12 bytes) | |
1462 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1463 | 12 bytes. The frame register is R7. |
da59e081 | 1464 | |
da3c6d4a MS |
1465 | The comments for thumb_skip_prolog() describe the algorithm we use |
1466 | to detect the end of the prolog. */ | |
c5aa993b JM |
1467 | /* *INDENT-ON* */ |
1468 | ||
c906108c | 1469 | static void |
be8626e0 | 1470 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1471 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1472 | { |
1473 | CORE_ADDR prologue_start; | |
1474 | CORE_ADDR prologue_end; | |
c906108c | 1475 | |
b39cc962 DJ |
1476 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1477 | &prologue_end)) | |
c906108c | 1478 | { |
ec3d575a UW |
1479 | /* See comment in arm_scan_prologue for an explanation of |
1480 | this heuristics. */ | |
1481 | if (prologue_end > prologue_start + 64) | |
1482 | { | |
1483 | prologue_end = prologue_start + 64; | |
1484 | } | |
c906108c SS |
1485 | } |
1486 | else | |
f7060f85 DJ |
1487 | /* We're in the boondocks: we have no idea where the start of the |
1488 | function is. */ | |
1489 | return; | |
c906108c | 1490 | |
325fac50 | 1491 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1492 | |
be8626e0 | 1493 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1494 | } |
1495 | ||
f303bc3e YQ |
1496 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1497 | otherwise. */ | |
1498 | ||
1499 | static int | |
1500 | arm_instruction_restores_sp (unsigned int insn) | |
1501 | { | |
1502 | if (bits (insn, 28, 31) != INST_NV) | |
1503 | { | |
1504 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1505 | /* ADD SP (register or immediate). */ | |
1506 | || (insn & 0x0df0f000) == 0x0040d000 | |
1507 | /* SUB SP (register or immediate). */ | |
1508 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1509 | /* MOV SP. */ | |
1510 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1511 | /* POP (LDMIA). */ | |
1512 | || (insn & 0x0fff0000) == 0x049d0000) | |
1513 | /* POP of a single register. */ | |
1514 | return 1; | |
1515 | } | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | ||
9ecab40c SM |
1520 | /* Implement immediate value decoding, as described in section A5.2.4 |
1521 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1522 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1523 | ||
1524 | static uint32_t | |
1525 | arm_expand_immediate (uint32_t imm) | |
1526 | { | |
1527 | /* Immediate values are 12 bits long. */ | |
1528 | gdb_assert ((imm & 0xfffff000) == 0); | |
1529 | ||
1530 | uint32_t unrotated_value = imm & 0xff; | |
1531 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1532 | ||
1533 | if (rotate_amount == 0) | |
1534 | return unrotated_value; | |
1535 | ||
1536 | return ((unrotated_value >> rotate_amount) | |
1537 | | (unrotated_value << (32 - rotate_amount))); | |
1538 | } | |
1539 | ||
0d39a070 DJ |
1540 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1541 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1542 | fill it in. Return the first address not recognized as a prologue | |
1543 | instruction. | |
eb5492fa | 1544 | |
0d39a070 DJ |
1545 | We recognize all the instructions typically found in ARM prologues, |
1546 | plus harmless instructions which can be skipped (either for analysis | |
1547 | purposes, or a more restrictive set that can be skipped when finding | |
1548 | the end of the prologue). */ | |
1549 | ||
1550 | static CORE_ADDR | |
1551 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1552 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1553 | struct arm_prologue_cache *cache, |
1554 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1555 | { |
0d39a070 DJ |
1556 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1557 | int regno; | |
1558 | CORE_ADDR offset, current_pc; | |
1559 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 DJ |
1560 | CORE_ADDR unrecognized_pc = 0; |
1561 | ||
1562 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1563 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1564 | |
96baa820 JM |
1565 | Be careful, however, and if it doesn't look like a prologue, |
1566 | don't try to scan it. If, for instance, a frameless function | |
1567 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1568 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1569 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1570 | traceback. */ |
d4473757 | 1571 | |
4be43953 DJ |
1572 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1573 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1574 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1575 | |
94c30b78 MS |
1576 | for (current_pc = prologue_start; |
1577 | current_pc < prologue_end; | |
f43845b3 | 1578 | current_pc += 4) |
96baa820 | 1579 | { |
9ecab40c | 1580 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1581 | |
94c30b78 | 1582 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1583 | { |
4be43953 | 1584 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1585 | continue; |
1586 | } | |
0d39a070 DJ |
1587 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1588 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1589 | { |
9ecab40c | 1590 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1591 | int rd = bits (insn, 12, 15); |
0d39a070 | 1592 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1593 | continue; |
1594 | } | |
0d39a070 DJ |
1595 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1596 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1597 | { |
9ecab40c | 1598 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1599 | int rd = bits (insn, 12, 15); |
0d39a070 | 1600 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1601 | continue; |
1602 | } | |
0963b4bd MS |
1603 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1604 | [sp, #-4]! */ | |
f43845b3 | 1605 | { |
f7b7ed97 | 1606 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1607 | break; |
1608 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
1609 | stack.store (regs[ARM_SP_REGNUM], 4, |
1610 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1611 | continue; |
1612 | } | |
1613 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1614 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1615 | or | |
1616 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1617 | { |
d4473757 | 1618 | int mask = insn & 0xffff; |
ed9a39eb | 1619 | |
f7b7ed97 | 1620 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1621 | break; |
1622 | ||
94c30b78 | 1623 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1624 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1625 | if (mask & (1 << regno)) |
1626 | { | |
0963b4bd MS |
1627 | regs[ARM_SP_REGNUM] |
1628 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 1629 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1630 | } |
1631 | } | |
0d39a070 DJ |
1632 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1633 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1634 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1635 | { |
1636 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1637 | continue; | |
1638 | } | |
0d39a070 DJ |
1639 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1640 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1641 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1642 | { |
1643 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1644 | continue; | |
1645 | } | |
0963b4bd MS |
1646 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1647 | { registers } */ | |
0d39a070 DJ |
1648 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1649 | { | |
1650 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1651 | continue; | |
1652 | } | |
d4473757 KB |
1653 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1654 | { | |
9ecab40c | 1655 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 1656 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1657 | } |
1658 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1659 | { | |
9ecab40c | 1660 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 1661 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1662 | } |
0963b4bd MS |
1663 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1664 | [sp, -#c]! */ | |
2af46ca0 | 1665 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 1666 | { |
f7b7ed97 | 1667 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1668 | break; |
1669 | ||
1670 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1671 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 1672 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1673 | } |
0963b4bd MS |
1674 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1675 | [sp!] */ | |
2af46ca0 | 1676 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
1677 | { |
1678 | int n_saved_fp_regs; | |
1679 | unsigned int fp_start_reg, fp_bound_reg; | |
1680 | ||
f7b7ed97 | 1681 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1682 | break; |
1683 | ||
94c30b78 | 1684 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1685 | { |
d4473757 KB |
1686 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1687 | n_saved_fp_regs = 3; | |
1688 | else | |
1689 | n_saved_fp_regs = 1; | |
96baa820 | 1690 | } |
d4473757 | 1691 | else |
96baa820 | 1692 | { |
d4473757 KB |
1693 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1694 | n_saved_fp_regs = 2; | |
1695 | else | |
1696 | n_saved_fp_regs = 4; | |
96baa820 | 1697 | } |
d4473757 | 1698 | |
34e8f22d | 1699 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1700 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1701 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1702 | { |
4be43953 | 1703 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
1704 | stack.store (regs[ARM_SP_REGNUM], 12, |
1705 | regs[fp_start_reg++]); | |
96baa820 | 1706 | } |
c906108c | 1707 | } |
0d39a070 DJ |
1708 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
1709 | { | |
1710 | /* Allow some special function calls when skipping the | |
1711 | prologue; GCC generates these before storing arguments to | |
1712 | the stack. */ | |
1713 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
1714 | ||
e0634ccf | 1715 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
1716 | continue; |
1717 | else | |
1718 | break; | |
1719 | } | |
d4473757 | 1720 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 1721 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
1722 | else if (arm_instruction_changes_pc (insn)) |
1723 | /* Don't scan past anything that might change control flow. */ | |
1724 | break; | |
f303bc3e YQ |
1725 | else if (arm_instruction_restores_sp (insn)) |
1726 | { | |
1727 | /* Don't scan past the epilogue. */ | |
1728 | break; | |
1729 | } | |
d19f7eee UW |
1730 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
1731 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1732 | /* Ignore block loads from the stack, potentially copying | |
1733 | parameters from memory. */ | |
1734 | continue; | |
1735 | else if ((insn & 0xfc500000) == 0xe4100000 | |
1736 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1737 | /* Similarly ignore single loads from the stack. */ | |
1738 | continue; | |
0d39a070 DJ |
1739 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
1740 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
1741 | register instead of the stack. */ | |
d4473757 | 1742 | continue; |
0d39a070 DJ |
1743 | else |
1744 | { | |
21daaaaf YQ |
1745 | /* The optimizer might shove anything into the prologue, if |
1746 | we build up cache (cache != NULL) from scanning prologue, | |
1747 | we just skip what we don't recognize and scan further to | |
1748 | make cache as complete as possible. However, if we skip | |
1749 | prologue, we'll stop immediately on unrecognized | |
1750 | instruction. */ | |
0d39a070 | 1751 | unrecognized_pc = current_pc; |
21daaaaf YQ |
1752 | if (cache != NULL) |
1753 | continue; | |
1754 | else | |
1755 | break; | |
0d39a070 | 1756 | } |
c906108c SS |
1757 | } |
1758 | ||
0d39a070 DJ |
1759 | if (unrecognized_pc == 0) |
1760 | unrecognized_pc = current_pc; | |
1761 | ||
0d39a070 DJ |
1762 | if (cache) |
1763 | { | |
4072f920 YQ |
1764 | int framereg, framesize; |
1765 | ||
1766 | /* The frame size is just the distance from the frame register | |
1767 | to the original stack pointer. */ | |
1768 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1769 | { | |
1770 | /* Frame pointer is fp. */ | |
1771 | framereg = ARM_FP_REGNUM; | |
1772 | framesize = -regs[ARM_FP_REGNUM].k; | |
1773 | } | |
1774 | else | |
1775 | { | |
1776 | /* Try the stack pointer... this is a bit desperate. */ | |
1777 | framereg = ARM_SP_REGNUM; | |
1778 | framesize = -regs[ARM_SP_REGNUM].k; | |
1779 | } | |
1780 | ||
0d39a070 DJ |
1781 | cache->framereg = framereg; |
1782 | cache->framesize = framesize; | |
1783 | ||
1784 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 1785 | if (stack.find_reg (gdbarch, regno, &offset)) |
098caef4 | 1786 | cache->saved_regs[regno].set_addr (offset); |
0d39a070 DJ |
1787 | } |
1788 | ||
7cb6d92a SM |
1789 | arm_debug_printf ("Prologue scan stopped at %s", |
1790 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 1791 | |
0d39a070 DJ |
1792 | return unrecognized_pc; |
1793 | } | |
1794 | ||
1795 | static void | |
1796 | arm_scan_prologue (struct frame_info *this_frame, | |
1797 | struct arm_prologue_cache *cache) | |
1798 | { | |
1799 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1800 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 1801 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
1802 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
1803 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
0d39a070 DJ |
1804 | |
1805 | /* Assume there is no frame until proven otherwise. */ | |
1806 | cache->framereg = ARM_SP_REGNUM; | |
1807 | cache->framesize = 0; | |
1808 | ||
1809 | /* Check for Thumb prologue. */ | |
1810 | if (arm_frame_is_thumb (this_frame)) | |
1811 | { | |
1812 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
1813 | return; | |
1814 | } | |
1815 | ||
1816 | /* Find the function prologue. If we can't find the function in | |
1817 | the symbol table, peek in the stack frame to find the PC. */ | |
1818 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
1819 | &prologue_end)) | |
1820 | { | |
1821 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 1822 | for unoptimized code) is to do the following: |
0d39a070 DJ |
1823 | |
1824 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
1825 | ||
1826 | if (sal.line == 0) | |
1827 | prologue_end = prev_pc; | |
1828 | else if (sal.end < prologue_end) | |
1829 | prologue_end = sal.end; | |
1830 | ||
1831 | This mechanism is very accurate so long as the optimizer | |
1832 | doesn't move any instructions from the function body into the | |
1833 | prologue. If this happens, sal.end will be the last | |
1834 | instruction in the first hunk of prologue code just before | |
1835 | the first instruction that the scheduler has moved from | |
1836 | the body to the prologue. | |
1837 | ||
1838 | In order to make sure that we scan all of the prologue | |
1839 | instructions, we use a slightly less accurate mechanism which | |
1840 | may scan more than necessary. To help compensate for this | |
1841 | lack of accuracy, the prologue scanning loop below contains | |
1842 | several clauses which'll cause the loop to terminate early if | |
1843 | an implausible prologue instruction is encountered. | |
1844 | ||
1845 | The expression | |
1846 | ||
1847 | prologue_start + 64 | |
1848 | ||
1849 | is a suitable endpoint since it accounts for the largest | |
1850 | possible prologue plus up to five instructions inserted by | |
1851 | the scheduler. */ | |
1852 | ||
1853 | if (prologue_end > prologue_start + 64) | |
1854 | { | |
1855 | prologue_end = prologue_start + 64; /* See above. */ | |
1856 | } | |
1857 | } | |
1858 | else | |
1859 | { | |
1860 | /* We have no symbol information. Our only option is to assume this | |
1861 | function has a standard stack frame and the normal frame register. | |
1862 | Then, we can find the value of our frame pointer on entrance to | |
1863 | the callee (or at the present moment if this is the innermost frame). | |
1864 | The value stored there should be the address of the stmfd + 8. */ | |
1865 | CORE_ADDR frame_loc; | |
7913a64c | 1866 | ULONGEST return_value; |
0d39a070 | 1867 | |
9e237747 MM |
1868 | /* AAPCS does not use a frame register, so we can abort here. */ |
1869 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_AAPCS) | |
dda83cd7 | 1870 | return; |
9e237747 | 1871 | |
0d39a070 | 1872 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
1873 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
1874 | &return_value)) | |
dda83cd7 | 1875 | return; |
0d39a070 | 1876 | else |
dda83cd7 SM |
1877 | { |
1878 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 1879 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
1880 | prologue_end = prologue_start + 64; /* See above. */ |
1881 | } | |
0d39a070 DJ |
1882 | } |
1883 | ||
1884 | if (prev_pc < prologue_end) | |
1885 | prologue_end = prev_pc; | |
1886 | ||
9ecab40c SM |
1887 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
1888 | target_arm_instruction_reader ()); | |
c906108c SS |
1889 | } |
1890 | ||
eb5492fa | 1891 | static struct arm_prologue_cache * |
a262aec2 | 1892 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1893 | { |
eb5492fa DJ |
1894 | int reg; |
1895 | struct arm_prologue_cache *cache; | |
1896 | CORE_ADDR unwound_fp; | |
c5aa993b | 1897 | |
35d5d4ee | 1898 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1899 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1900 | |
a262aec2 | 1901 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1902 | |
a262aec2 | 1903 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1904 | if (unwound_fp == 0) |
1905 | return cache; | |
c906108c | 1906 | |
4be43953 | 1907 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1908 | |
eb5492fa DJ |
1909 | /* Calculate actual addresses of saved registers using offsets |
1910 | determined by arm_scan_prologue. */ | |
a262aec2 | 1911 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
a9a87d35 | 1912 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
1913 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
1914 | + cache->prev_sp); | |
eb5492fa DJ |
1915 | |
1916 | return cache; | |
c906108c SS |
1917 | } |
1918 | ||
c1ee9414 LM |
1919 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
1920 | ||
1921 | static enum unwind_stop_reason | |
1922 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
1923 | void **this_cache) | |
1924 | { | |
1925 | struct arm_prologue_cache *cache; | |
1926 | CORE_ADDR pc; | |
1927 | ||
1928 | if (*this_cache == NULL) | |
1929 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 1930 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
1931 | |
1932 | /* This is meant to halt the backtrace at "_start". */ | |
1933 | pc = get_frame_pc (this_frame); | |
1934 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
1935 | return UNWIND_OUTERMOST; | |
1936 | ||
1937 | /* If we've hit a wall, stop. */ | |
1938 | if (cache->prev_sp == 0) | |
1939 | return UNWIND_OUTERMOST; | |
1940 | ||
1941 | return UNWIND_NO_REASON; | |
1942 | } | |
1943 | ||
eb5492fa DJ |
1944 | /* Our frame ID for a normal frame is the current function's starting PC |
1945 | and the caller's SP when we were called. */ | |
c906108c | 1946 | |
148754e5 | 1947 | static void |
a262aec2 | 1948 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1949 | void **this_cache, |
1950 | struct frame_id *this_id) | |
c906108c | 1951 | { |
eb5492fa DJ |
1952 | struct arm_prologue_cache *cache; |
1953 | struct frame_id id; | |
2c404490 | 1954 | CORE_ADDR pc, func; |
f079148d | 1955 | |
eb5492fa | 1956 | if (*this_cache == NULL) |
a262aec2 | 1957 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1958 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 1959 | |
0e9e9abd UW |
1960 | /* Use function start address as part of the frame ID. If we cannot |
1961 | identify the start address (due to missing symbol information), | |
1962 | fall back to just using the current PC. */ | |
c1ee9414 | 1963 | pc = get_frame_pc (this_frame); |
2c404490 | 1964 | func = get_frame_func (this_frame); |
0e9e9abd UW |
1965 | if (!func) |
1966 | func = pc; | |
1967 | ||
eb5492fa | 1968 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1969 | *this_id = id; |
c906108c SS |
1970 | } |
1971 | ||
a262aec2 DJ |
1972 | static struct value * |
1973 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1974 | void **this_cache, |
a262aec2 | 1975 | int prev_regnum) |
24de872b | 1976 | { |
24568a2c | 1977 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1978 | struct arm_prologue_cache *cache; |
1979 | ||
eb5492fa | 1980 | if (*this_cache == NULL) |
a262aec2 | 1981 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 1982 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 1983 | |
eb5492fa | 1984 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1985 | instead. The prologue may save PC, but it will point into this |
1986 | frame's prologue, not the next frame's resume location. Also | |
1987 | strip the saved T bit. A valid LR may have the low bit set, but | |
1988 | a valid PC never does. */ | |
eb5492fa | 1989 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1990 | { |
1991 | CORE_ADDR lr; | |
1992 | ||
1993 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1994 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1995 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1996 | } |
24de872b | 1997 | |
eb5492fa | 1998 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1999 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2000 | The value was already reconstructed into PREV_SP. */ |
2001 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 2002 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 2003 | |
b39cc962 DJ |
2004 | /* The CPSR may have been changed by the call instruction and by the |
2005 | called function. The only bit we can reconstruct is the T bit, | |
2006 | by checking the low bit of LR as of the call. This is a reliable | |
2007 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2008 | Thumb code, which could get away with a clear low bit as long as | |
2009 | the called function did not use bx. Guess that all other | |
2010 | bits are unchanged; the condition flags are presumably lost, | |
2011 | but the processor status is likely valid. */ | |
2012 | if (prev_regnum == ARM_PS_REGNUM) | |
2013 | { | |
2014 | CORE_ADDR lr, cpsr; | |
9779414d | 2015 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
2016 | |
2017 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
2018 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2019 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 2020 | cpsr |= t_bit; |
b39cc962 | 2021 | else |
9779414d | 2022 | cpsr &= ~t_bit; |
b39cc962 DJ |
2023 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2024 | } | |
2025 | ||
a262aec2 DJ |
2026 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2027 | prev_regnum); | |
eb5492fa DJ |
2028 | } |
2029 | ||
6bd434d6 | 2030 | static frame_unwind arm_prologue_unwind = { |
eb5492fa | 2031 | NORMAL_FRAME, |
c1ee9414 | 2032 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2033 | arm_prologue_this_id, |
a262aec2 DJ |
2034 | arm_prologue_prev_register, |
2035 | NULL, | |
2036 | default_frame_sniffer | |
eb5492fa DJ |
2037 | }; |
2038 | ||
0e9e9abd UW |
2039 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2040 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2041 | personality routines; the cache will contain only the frame unwinding | |
2042 | instructions associated with the entry (not the descriptors). */ | |
2043 | ||
0e9e9abd UW |
2044 | struct arm_exidx_entry |
2045 | { | |
227031b2 | 2046 | CORE_ADDR addr; |
0e9e9abd | 2047 | gdb_byte *entry; |
7a5d944b TT |
2048 | |
2049 | bool operator< (const arm_exidx_entry &other) const | |
2050 | { | |
2051 | return addr < other.addr; | |
2052 | } | |
0e9e9abd | 2053 | }; |
0e9e9abd UW |
2054 | |
2055 | struct arm_exidx_data | |
2056 | { | |
7a5d944b | 2057 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2058 | }; |
2059 | ||
a2726d4f LM |
2060 | /* Per-BFD key to store exception handling information. */ |
2061 | static const struct bfd_key<arm_exidx_data> arm_exidx_data_key; | |
0e9e9abd UW |
2062 | |
2063 | static struct obj_section * | |
2064 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2065 | { | |
2066 | struct obj_section *osect; | |
2067 | ||
2068 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2069 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2070 | { |
2071 | bfd_vma start, size; | |
fd361982 AM |
2072 | start = bfd_section_vma (osect->the_bfd_section); |
2073 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2074 | |
2075 | if (start <= vma && vma < start + size) | |
2076 | return osect; | |
2077 | } | |
2078 | ||
2079 | return NULL; | |
2080 | } | |
2081 | ||
2082 | /* Parse contents of exception table and exception index sections | |
2083 | of OBJFILE, and fill in the exception table entry cache. | |
2084 | ||
2085 | For each entry that refers to a standard ARM-defined personality | |
2086 | routine, extract the frame unwinding instructions (from either | |
2087 | the index or the table section). The unwinding instructions | |
2088 | are normalized by: | |
2089 | - extracting them from the rest of the table data | |
2090 | - converting to host endianness | |
2091 | - appending the implicit 0xb0 ("Finish") code | |
2092 | ||
2093 | The extracted and normalized instructions are stored for later | |
2094 | retrieval by the arm_find_exidx_entry routine. */ | |
2095 | ||
2096 | static void | |
2097 | arm_exidx_new_objfile (struct objfile *objfile) | |
2098 | { | |
0e9e9abd UW |
2099 | struct arm_exidx_data *data; |
2100 | asection *exidx, *extab; | |
2101 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2102 | LONGEST i; |
2103 | ||
2104 | /* If we've already touched this file, do nothing. */ | |
a2726d4f | 2105 | if (!objfile || arm_exidx_data_key.get (objfile->obfd) != NULL) |
0e9e9abd UW |
2106 | return; |
2107 | ||
2108 | /* Read contents of exception table and index. */ | |
a5eda10c | 2109 | exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); |
984c7238 | 2110 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2111 | if (exidx) |
2112 | { | |
fd361982 AM |
2113 | exidx_vma = bfd_section_vma (exidx); |
2114 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd UW |
2115 | |
2116 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
984c7238 TT |
2117 | exidx_data.data (), 0, |
2118 | exidx_data.size ())) | |
2119 | return; | |
0e9e9abd UW |
2120 | } |
2121 | ||
2122 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
984c7238 | 2123 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2124 | if (extab) |
2125 | { | |
fd361982 AM |
2126 | extab_vma = bfd_section_vma (extab); |
2127 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd UW |
2128 | |
2129 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
984c7238 TT |
2130 | extab_data.data (), 0, |
2131 | extab_data.size ())) | |
2132 | return; | |
0e9e9abd UW |
2133 | } |
2134 | ||
2135 | /* Allocate exception table data structure. */ | |
a2726d4f | 2136 | data = arm_exidx_data_key.emplace (objfile->obfd); |
7a5d944b | 2137 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2138 | |
2139 | /* Fill in exception table. */ | |
984c7238 | 2140 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2141 | { |
2142 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2143 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2144 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2145 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2146 | bfd_vma addr = 0, word = 0; |
2147 | int n_bytes = 0, n_words = 0; | |
2148 | struct obj_section *sec; | |
2149 | gdb_byte *entry = NULL; | |
2150 | ||
2151 | /* Extract address of start of function. */ | |
2152 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2153 | idx += exidx_vma + i * 8; | |
2154 | ||
2155 | /* Find section containing function and compute section offset. */ | |
2156 | sec = arm_obj_section_from_vma (objfile, idx); | |
2157 | if (sec == NULL) | |
2158 | continue; | |
fd361982 | 2159 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2160 | |
2161 | /* Determine address of exception table entry. */ | |
2162 | if (val == 1) | |
2163 | { | |
2164 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2165 | } | |
2166 | else if ((val & 0xff000000) == 0x80000000) | |
2167 | { | |
2168 | /* Exception table entry embedded in .ARM.exidx | |
2169 | -- must be short form. */ | |
2170 | word = val; | |
2171 | n_bytes = 3; | |
2172 | } | |
2173 | else if (!(val & 0x80000000)) | |
2174 | { | |
2175 | /* Exception table entry in .ARM.extab. */ | |
2176 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2177 | addr += exidx_vma + i * 8 + 4; | |
2178 | ||
984c7238 | 2179 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2180 | { |
2181 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2182 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2183 | addr += 4; |
2184 | ||
2185 | if ((word & 0xff000000) == 0x80000000) | |
2186 | { | |
2187 | /* Short form. */ | |
2188 | n_bytes = 3; | |
2189 | } | |
2190 | else if ((word & 0xff000000) == 0x81000000 | |
2191 | || (word & 0xff000000) == 0x82000000) | |
2192 | { | |
2193 | /* Long form. */ | |
2194 | n_bytes = 2; | |
2195 | n_words = ((word >> 16) & 0xff); | |
2196 | } | |
2197 | else if (!(word & 0x80000000)) | |
2198 | { | |
2199 | bfd_vma pers; | |
2200 | struct obj_section *pers_sec; | |
2201 | int gnu_personality = 0; | |
2202 | ||
2203 | /* Custom personality routine. */ | |
2204 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2205 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2206 | ||
2207 | /* Check whether we've got one of the variants of the | |
2208 | GNU personality routines. */ | |
2209 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2210 | if (pers_sec) | |
2211 | { | |
2212 | static const char *personality[] = | |
2213 | { | |
2214 | "__gcc_personality_v0", | |
2215 | "__gxx_personality_v0", | |
2216 | "__gcj_personality_v0", | |
2217 | "__gnu_objc_personality_v0", | |
2218 | NULL | |
2219 | }; | |
2220 | ||
2221 | CORE_ADDR pc = pers + obj_section_offset (pers_sec); | |
2222 | int k; | |
2223 | ||
2224 | for (k = 0; personality[k]; k++) | |
2225 | if (lookup_minimal_symbol_by_pc_name | |
2226 | (pc, personality[k], objfile)) | |
2227 | { | |
2228 | gnu_personality = 1; | |
2229 | break; | |
2230 | } | |
2231 | } | |
2232 | ||
2233 | /* If so, the next word contains a word count in the high | |
2234 | byte, followed by the same unwind instructions as the | |
2235 | pre-defined forms. */ | |
2236 | if (gnu_personality | |
984c7238 | 2237 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2238 | { |
2239 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2240 | (extab_data.data () |
2241 | + addr - extab_vma)); | |
0e9e9abd UW |
2242 | addr += 4; |
2243 | n_bytes = 3; | |
2244 | n_words = ((word >> 24) & 0xff); | |
2245 | } | |
2246 | } | |
2247 | } | |
2248 | } | |
2249 | ||
2250 | /* Sanity check address. */ | |
2251 | if (n_words) | |
984c7238 TT |
2252 | if (addr < extab_vma |
2253 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2254 | n_words = n_bytes = 0; |
2255 | ||
2256 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2257 | significant bytes are valid), followed by N_WORDS words in the | |
2258 | extab section starting at ADDR. */ | |
2259 | if (n_bytes || n_words) | |
2260 | { | |
224c3ddb SM |
2261 | gdb_byte *p = entry |
2262 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2263 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2264 | |
2265 | while (n_bytes--) | |
2266 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2267 | ||
2268 | while (n_words--) | |
2269 | { | |
2270 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2271 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2272 | addr += 4; |
2273 | ||
2274 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2275 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2276 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2277 | *p++ = (gdb_byte) (word & 0xff); | |
2278 | } | |
2279 | ||
2280 | /* Implied "Finish" to terminate the list. */ | |
2281 | *p++ = 0xb0; | |
2282 | } | |
2283 | ||
2284 | /* Push entry onto vector. They are guaranteed to always | |
2285 | appear in order of increasing addresses. */ | |
2286 | new_exidx_entry.addr = idx; | |
2287 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2288 | data->section_maps[sec->the_bfd_section->index].push_back |
2289 | (new_exidx_entry); | |
0e9e9abd | 2290 | } |
0e9e9abd UW |
2291 | } |
2292 | ||
2293 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2294 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2295 | set *START to the start of the region covered by this entry. */ | |
2296 | ||
2297 | static gdb_byte * | |
2298 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2299 | { | |
2300 | struct obj_section *sec; | |
2301 | ||
2302 | sec = find_pc_section (memaddr); | |
2303 | if (sec != NULL) | |
2304 | { | |
2305 | struct arm_exidx_data *data; | |
0e9e9abd | 2306 | struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 }; |
0e9e9abd | 2307 | |
a2726d4f | 2308 | data = arm_exidx_data_key.get (sec->objfile->obfd); |
0e9e9abd UW |
2309 | if (data != NULL) |
2310 | { | |
7a5d944b TT |
2311 | std::vector<arm_exidx_entry> &map |
2312 | = data->section_maps[sec->the_bfd_section->index]; | |
2313 | if (!map.empty ()) | |
0e9e9abd | 2314 | { |
7a5d944b | 2315 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2316 | |
7a5d944b | 2317 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2318 | point. If the following symbol starts at this exact |
2319 | address, we use that; otherwise, the preceding | |
2320 | exception table entry covers this address. */ | |
7a5d944b | 2321 | if (idx < map.end ()) |
0e9e9abd | 2322 | { |
7a5d944b | 2323 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2324 | { |
2325 | if (start) | |
7a5d944b TT |
2326 | *start = idx->addr + obj_section_addr (sec); |
2327 | return idx->entry; | |
0e9e9abd UW |
2328 | } |
2329 | } | |
2330 | ||
7a5d944b | 2331 | if (idx > map.begin ()) |
0e9e9abd | 2332 | { |
7a5d944b | 2333 | idx = idx - 1; |
0e9e9abd | 2334 | if (start) |
7a5d944b TT |
2335 | *start = idx->addr + obj_section_addr (sec); |
2336 | return idx->entry; | |
0e9e9abd UW |
2337 | } |
2338 | } | |
2339 | } | |
2340 | } | |
2341 | ||
2342 | return NULL; | |
2343 | } | |
2344 | ||
2345 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2346 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2347 | return a prologue cache structure describing how to unwind this frame. | |
2348 | ||
2349 | Return NULL if the unwinding instruction list contains a "spare", | |
2350 | "reserved" or "refuse to unwind" instruction as defined in section | |
2351 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2352 | for the ARM Architecture" document. */ | |
2353 | ||
2354 | static struct arm_prologue_cache * | |
2355 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2356 | { | |
2357 | CORE_ADDR vsp = 0; | |
2358 | int vsp_valid = 0; | |
2359 | ||
2360 | struct arm_prologue_cache *cache; | |
2361 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2362 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2363 | ||
2364 | for (;;) | |
2365 | { | |
2366 | gdb_byte insn; | |
2367 | ||
2368 | /* Whenever we reload SP, we actually have to retrieve its | |
2369 | actual value in the current frame. */ | |
2370 | if (!vsp_valid) | |
2371 | { | |
a9a87d35 | 2372 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
0e9e9abd | 2373 | { |
098caef4 | 2374 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2375 | vsp = get_frame_register_unsigned (this_frame, reg); |
2376 | } | |
2377 | else | |
2378 | { | |
098caef4 | 2379 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr (); |
0e9e9abd UW |
2380 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); |
2381 | } | |
2382 | ||
2383 | vsp_valid = 1; | |
2384 | } | |
2385 | ||
2386 | /* Decode next unwind instruction. */ | |
2387 | insn = *entry++; | |
2388 | ||
2389 | if ((insn & 0xc0) == 0) | |
2390 | { | |
2391 | int offset = insn & 0x3f; | |
2392 | vsp += (offset << 2) + 4; | |
2393 | } | |
2394 | else if ((insn & 0xc0) == 0x40) | |
2395 | { | |
2396 | int offset = insn & 0x3f; | |
2397 | vsp -= (offset << 2) + 4; | |
2398 | } | |
2399 | else if ((insn & 0xf0) == 0x80) | |
2400 | { | |
2401 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2402 | int i; | |
2403 | ||
2404 | /* The special case of an all-zero mask identifies | |
2405 | "Refuse to unwind". We return NULL to fall back | |
2406 | to the prologue analyzer. */ | |
2407 | if (mask == 0) | |
2408 | return NULL; | |
2409 | ||
2410 | /* Pop registers r4..r15 under mask. */ | |
2411 | for (i = 0; i < 12; i++) | |
2412 | if (mask & (1 << i)) | |
2413 | { | |
098caef4 | 2414 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2415 | vsp += 4; |
2416 | } | |
2417 | ||
2418 | /* Special-case popping SP -- we need to reload vsp. */ | |
2419 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2420 | vsp_valid = 0; | |
2421 | } | |
2422 | else if ((insn & 0xf0) == 0x90) | |
2423 | { | |
2424 | int reg = insn & 0xf; | |
2425 | ||
2426 | /* Reserved cases. */ | |
2427 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2428 | return NULL; | |
2429 | ||
2430 | /* Set SP from another register and mark VSP for reload. */ | |
2431 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2432 | vsp_valid = 0; | |
2433 | } | |
2434 | else if ((insn & 0xf0) == 0xa0) | |
2435 | { | |
2436 | int count = insn & 0x7; | |
2437 | int pop_lr = (insn & 0x8) != 0; | |
2438 | int i; | |
2439 | ||
2440 | /* Pop r4..r[4+count]. */ | |
2441 | for (i = 0; i <= count; i++) | |
2442 | { | |
098caef4 | 2443 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2444 | vsp += 4; |
2445 | } | |
2446 | ||
2447 | /* If indicated by flag, pop LR as well. */ | |
2448 | if (pop_lr) | |
2449 | { | |
098caef4 | 2450 | cache->saved_regs[ARM_LR_REGNUM].set_addr (vsp); |
0e9e9abd UW |
2451 | vsp += 4; |
2452 | } | |
2453 | } | |
2454 | else if (insn == 0xb0) | |
2455 | { | |
2456 | /* We could only have updated PC by popping into it; if so, it | |
2457 | will show up as address. Otherwise, copy LR into PC. */ | |
a9a87d35 | 2458 | if (!cache->saved_regs[ARM_PC_REGNUM].is_addr ()) |
0e9e9abd UW |
2459 | cache->saved_regs[ARM_PC_REGNUM] |
2460 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2461 | ||
2462 | /* We're done. */ | |
2463 | break; | |
2464 | } | |
2465 | else if (insn == 0xb1) | |
2466 | { | |
2467 | int mask = *entry++; | |
2468 | int i; | |
2469 | ||
2470 | /* All-zero mask and mask >= 16 is "spare". */ | |
2471 | if (mask == 0 || mask >= 16) | |
2472 | return NULL; | |
2473 | ||
2474 | /* Pop r0..r3 under mask. */ | |
2475 | for (i = 0; i < 4; i++) | |
2476 | if (mask & (1 << i)) | |
2477 | { | |
098caef4 | 2478 | cache->saved_regs[i].set_addr (vsp); |
0e9e9abd UW |
2479 | vsp += 4; |
2480 | } | |
2481 | } | |
2482 | else if (insn == 0xb2) | |
2483 | { | |
2484 | ULONGEST offset = 0; | |
2485 | unsigned shift = 0; | |
2486 | ||
2487 | do | |
2488 | { | |
2489 | offset |= (*entry & 0x7f) << shift; | |
2490 | shift += 7; | |
2491 | } | |
2492 | while (*entry++ & 0x80); | |
2493 | ||
2494 | vsp += 0x204 + (offset << 2); | |
2495 | } | |
2496 | else if (insn == 0xb3) | |
2497 | { | |
2498 | int start = *entry >> 4; | |
2499 | int count = (*entry++) & 0xf; | |
2500 | int i; | |
2501 | ||
2502 | /* Only registers D0..D15 are valid here. */ | |
2503 | if (start + count >= 16) | |
2504 | return NULL; | |
2505 | ||
2506 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2507 | for (i = 0; i <= count; i++) | |
2508 | { | |
098caef4 | 2509 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2510 | vsp += 8; |
2511 | } | |
2512 | ||
2513 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2514 | vsp += 4; | |
2515 | } | |
2516 | else if ((insn & 0xf8) == 0xb8) | |
2517 | { | |
2518 | int count = insn & 0x7; | |
2519 | int i; | |
2520 | ||
2521 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2522 | for (i = 0; i <= count; i++) | |
2523 | { | |
098caef4 | 2524 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2525 | vsp += 8; |
2526 | } | |
2527 | ||
2528 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2529 | vsp += 4; | |
2530 | } | |
2531 | else if (insn == 0xc6) | |
2532 | { | |
2533 | int start = *entry >> 4; | |
2534 | int count = (*entry++) & 0xf; | |
2535 | int i; | |
2536 | ||
2537 | /* Only registers WR0..WR15 are valid. */ | |
2538 | if (start + count >= 16) | |
2539 | return NULL; | |
2540 | ||
2541 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2542 | for (i = 0; i <= count; i++) | |
2543 | { | |
098caef4 | 2544 | cache->saved_regs[ARM_WR0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2545 | vsp += 8; |
2546 | } | |
2547 | } | |
2548 | else if (insn == 0xc7) | |
2549 | { | |
2550 | int mask = *entry++; | |
2551 | int i; | |
2552 | ||
2553 | /* All-zero mask and mask >= 16 is "spare". */ | |
2554 | if (mask == 0 || mask >= 16) | |
2555 | return NULL; | |
2556 | ||
2557 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2558 | for (i = 0; i < 4; i++) | |
2559 | if (mask & (1 << i)) | |
2560 | { | |
098caef4 | 2561 | cache->saved_regs[ARM_WCGR0_REGNUM + i].set_addr (vsp); |
0e9e9abd UW |
2562 | vsp += 4; |
2563 | } | |
2564 | } | |
2565 | else if ((insn & 0xf8) == 0xc0) | |
2566 | { | |
2567 | int count = insn & 0x7; | |
2568 | int i; | |
2569 | ||
2570 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2571 | for (i = 0; i <= count; i++) | |
2572 | { | |
098caef4 | 2573 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].set_addr (vsp); |
0e9e9abd UW |
2574 | vsp += 8; |
2575 | } | |
2576 | } | |
2577 | else if (insn == 0xc8) | |
2578 | { | |
2579 | int start = *entry >> 4; | |
2580 | int count = (*entry++) & 0xf; | |
2581 | int i; | |
2582 | ||
2583 | /* Only registers D0..D31 are valid. */ | |
2584 | if (start + count >= 16) | |
2585 | return NULL; | |
2586 | ||
2587 | /* Pop VFP double-precision registers | |
2588 | D[16+start]..D[16+start+count]. */ | |
2589 | for (i = 0; i <= count; i++) | |
2590 | { | |
098caef4 | 2591 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].set_addr (vsp); |
0e9e9abd UW |
2592 | vsp += 8; |
2593 | } | |
2594 | } | |
2595 | else if (insn == 0xc9) | |
2596 | { | |
2597 | int start = *entry >> 4; | |
2598 | int count = (*entry++) & 0xf; | |
2599 | int i; | |
2600 | ||
2601 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2602 | for (i = 0; i <= count; i++) | |
2603 | { | |
098caef4 | 2604 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2605 | vsp += 8; |
2606 | } | |
2607 | } | |
2608 | else if ((insn & 0xf8) == 0xd0) | |
2609 | { | |
2610 | int count = insn & 0x7; | |
2611 | int i; | |
2612 | ||
2613 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2614 | for (i = 0; i <= count; i++) | |
2615 | { | |
098caef4 | 2616 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2617 | vsp += 8; |
2618 | } | |
2619 | } | |
2620 | else | |
2621 | { | |
2622 | /* Everything else is "spare". */ | |
2623 | return NULL; | |
2624 | } | |
2625 | } | |
2626 | ||
2627 | /* If we restore SP from a register, assume this was the frame register. | |
2628 | Otherwise just fall back to SP as frame register. */ | |
a9a87d35 | 2629 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
098caef4 | 2630 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2631 | else |
2632 | cache->framereg = ARM_SP_REGNUM; | |
2633 | ||
2634 | /* Determine offset to previous frame. */ | |
2635 | cache->framesize | |
2636 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2637 | ||
2638 | /* We already got the previous SP. */ | |
2639 | cache->prev_sp = vsp; | |
2640 | ||
2641 | return cache; | |
2642 | } | |
2643 | ||
2644 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2645 | already computes a filled-in prologue cache, which is then used | |
2646 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2647 | routines also used for prologue-parsing based unwinding. */ | |
2648 | ||
2649 | static int | |
2650 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
2651 | struct frame_info *this_frame, | |
2652 | void **this_prologue_cache) | |
2653 | { | |
2654 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2655 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2656 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
2657 | struct arm_prologue_cache *cache; | |
2658 | gdb_byte *entry; | |
2659 | ||
2660 | /* See if we have an ARM exception table entry covering this address. */ | |
2661 | addr_in_block = get_frame_address_in_block (this_frame); | |
2662 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
2663 | if (!entry) | |
2664 | return 0; | |
2665 | ||
2666 | /* The ARM exception table does not describe unwind information | |
2667 | for arbitrary PC values, but is guaranteed to be correct only | |
2668 | at call sites. We have to decide here whether we want to use | |
2669 | ARM exception table information for this frame, or fall back | |
2670 | to using prologue parsing. (Note that if we have DWARF CFI, | |
2671 | this sniffer isn't even called -- CFI is always preferred.) | |
2672 | ||
2673 | Before we make this decision, however, we check whether we | |
2674 | actually have *symbol* information for the current frame. | |
2675 | If not, prologue parsing would not work anyway, so we might | |
2676 | as well use the exception table and hope for the best. */ | |
2677 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
2678 | { | |
2679 | int exc_valid = 0; | |
2680 | ||
2681 | /* If the next frame is "normal", we are at a call site in this | |
2682 | frame, so exception information is guaranteed to be valid. */ | |
2683 | if (get_next_frame (this_frame) | |
2684 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
2685 | exc_valid = 1; | |
2686 | ||
2687 | /* We also assume exception information is valid if we're currently | |
2688 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
2689 | ensure this, so that e.g. pthread cancellation works. */ |
2690 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 2691 | { |
7913a64c | 2692 | ULONGEST insn; |
416dc9c6 | 2693 | |
7913a64c YQ |
2694 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
2695 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
2696 | && (insn & 0xff00) == 0xdf00 /* svc */) |
2697 | exc_valid = 1; | |
0e9e9abd | 2698 | } |
d9311bfa AT |
2699 | else |
2700 | { | |
7913a64c | 2701 | ULONGEST insn; |
416dc9c6 | 2702 | |
7913a64c YQ |
2703 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
2704 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
2705 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
2706 | exc_valid = 1; | |
2707 | } | |
2708 | ||
0e9e9abd UW |
2709 | /* Bail out if we don't know that exception information is valid. */ |
2710 | if (!exc_valid) | |
2711 | return 0; | |
2712 | ||
2713 | /* The ARM exception index does not mark the *end* of the region | |
2714 | covered by the entry, and some functions will not have any entry. | |
2715 | To correctly recognize the end of the covered region, the linker | |
2716 | should have inserted dummy records with a CANTUNWIND marker. | |
2717 | ||
2718 | Unfortunately, current versions of GNU ld do not reliably do | |
2719 | this, and thus we may have found an incorrect entry above. | |
2720 | As a (temporary) sanity check, we only use the entry if it | |
2721 | lies *within* the bounds of the function. Note that this check | |
2722 | might reject perfectly valid entries that just happen to cover | |
2723 | multiple functions; therefore this check ought to be removed | |
2724 | once the linker is fixed. */ | |
2725 | if (func_start > exidx_region) | |
2726 | return 0; | |
2727 | } | |
2728 | ||
2729 | /* Decode the list of unwinding instructions into a prologue cache. | |
2730 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
2731 | cache = arm_exidx_fill_cache (this_frame, entry); | |
2732 | if (!cache) | |
2733 | return 0; | |
2734 | ||
2735 | *this_prologue_cache = cache; | |
2736 | return 1; | |
2737 | } | |
2738 | ||
2739 | struct frame_unwind arm_exidx_unwind = { | |
2740 | NORMAL_FRAME, | |
8fbca658 | 2741 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
2742 | arm_prologue_this_id, |
2743 | arm_prologue_prev_register, | |
2744 | NULL, | |
2745 | arm_exidx_unwind_sniffer | |
2746 | }; | |
2747 | ||
779aa56f YQ |
2748 | static struct arm_prologue_cache * |
2749 | arm_make_epilogue_frame_cache (struct frame_info *this_frame) | |
2750 | { | |
2751 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
2752 | int reg; |
2753 | ||
2754 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2755 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2756 | ||
2757 | /* Still rely on the offset calculated from prologue. */ | |
2758 | arm_scan_prologue (this_frame, cache); | |
2759 | ||
2760 | /* Since we are in epilogue, the SP has been restored. */ | |
2761 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
2762 | ||
2763 | /* Calculate actual addresses of saved registers using offsets | |
2764 | determined by arm_scan_prologue. */ | |
2765 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 2766 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
2767 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
2768 | + cache->prev_sp); | |
779aa56f YQ |
2769 | |
2770 | return cache; | |
2771 | } | |
2772 | ||
2773 | /* Implementation of function hook 'this_id' in | |
2774 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2775 | ||
2776 | static void | |
2777 | arm_epilogue_frame_this_id (struct frame_info *this_frame, | |
2778 | void **this_cache, | |
2779 | struct frame_id *this_id) | |
2780 | { | |
2781 | struct arm_prologue_cache *cache; | |
2782 | CORE_ADDR pc, func; | |
2783 | ||
2784 | if (*this_cache == NULL) | |
2785 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
2786 | cache = (struct arm_prologue_cache *) *this_cache; | |
2787 | ||
2788 | /* Use function start address as part of the frame ID. If we cannot | |
2789 | identify the start address (due to missing symbol information), | |
2790 | fall back to just using the current PC. */ | |
2791 | pc = get_frame_pc (this_frame); | |
2792 | func = get_frame_func (this_frame); | |
fb3f3d25 | 2793 | if (func == 0) |
779aa56f YQ |
2794 | func = pc; |
2795 | ||
2796 | (*this_id) = frame_id_build (cache->prev_sp, pc); | |
2797 | } | |
2798 | ||
2799 | /* Implementation of function hook 'prev_register' in | |
2800 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2801 | ||
2802 | static struct value * | |
2803 | arm_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2804 | void **this_cache, int regnum) | |
2805 | { | |
779aa56f YQ |
2806 | if (*this_cache == NULL) |
2807 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
2808 | |
2809 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
2810 | } | |
2811 | ||
2812 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
2813 | CORE_ADDR pc); | |
2814 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
2815 | CORE_ADDR pc); | |
2816 | ||
2817 | /* Implementation of function hook 'sniffer' in | |
2818 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2819 | ||
2820 | static int | |
2821 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2822 | struct frame_info *this_frame, | |
2823 | void **this_prologue_cache) | |
2824 | { | |
2825 | if (frame_relative_level (this_frame) == 0) | |
2826 | { | |
2827 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2828 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2829 | ||
2830 | if (arm_frame_is_thumb (this_frame)) | |
2831 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
2832 | else | |
2833 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
2834 | } | |
2835 | else | |
2836 | return 0; | |
2837 | } | |
2838 | ||
2839 | /* Frame unwinder from epilogue. */ | |
2840 | ||
2841 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
2842 | { | |
2843 | NORMAL_FRAME, | |
2844 | default_frame_unwind_stop_reason, | |
2845 | arm_epilogue_frame_this_id, | |
2846 | arm_epilogue_frame_prev_register, | |
2847 | NULL, | |
2848 | arm_epilogue_frame_sniffer, | |
2849 | }; | |
2850 | ||
80d8d390 YQ |
2851 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
2852 | trampoline, return the target PC. Otherwise return 0. | |
2853 | ||
2854 | void call0a (char c, short s, int i, long l) {} | |
2855 | ||
2856 | int main (void) | |
2857 | { | |
2858 | (*pointer_to_call0a) (c, s, i, l); | |
2859 | } | |
2860 | ||
2861 | Instead of calling a stub library function _call_via_xx (xx is | |
2862 | the register name), GCC may inline the trampoline in the object | |
2863 | file as below (register r2 has the address of call0a). | |
2864 | ||
2865 | .global main | |
2866 | .type main, %function | |
2867 | ... | |
2868 | bl .L1 | |
2869 | ... | |
2870 | .size main, .-main | |
2871 | ||
2872 | .L1: | |
2873 | bx r2 | |
2874 | ||
2875 | The trampoline 'bx r2' doesn't belong to main. */ | |
2876 | ||
2877 | static CORE_ADDR | |
2878 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
2879 | { | |
2880 | /* The heuristics of recognizing such trampoline is that FRAME is | |
2881 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
2882 | if (arm_frame_is_thumb (frame)) | |
2883 | { | |
2884 | gdb_byte buf[2]; | |
2885 | ||
2886 | if (target_read_memory (pc, buf, 2) == 0) | |
2887 | { | |
2888 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2889 | enum bfd_endian byte_order_for_code | |
2890 | = gdbarch_byte_order_for_code (gdbarch); | |
2891 | uint16_t insn | |
2892 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
2893 | ||
2894 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
2895 | { | |
2896 | CORE_ADDR dest | |
2897 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
2898 | ||
2899 | /* Clear the LSB so that gdb core sets step-resume | |
2900 | breakpoint at the right address. */ | |
2901 | return UNMAKE_THUMB_ADDR (dest); | |
2902 | } | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | return 0; | |
2907 | } | |
2908 | ||
909cf6ea | 2909 | static struct arm_prologue_cache * |
a262aec2 | 2910 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 2911 | { |
909cf6ea | 2912 | struct arm_prologue_cache *cache; |
909cf6ea | 2913 | |
35d5d4ee | 2914 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 2915 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 2916 | |
a262aec2 | 2917 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
2918 | |
2919 | return cache; | |
2920 | } | |
2921 | ||
2922 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
2923 | ||
2924 | static void | |
a262aec2 | 2925 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
2926 | void **this_cache, |
2927 | struct frame_id *this_id) | |
2928 | { | |
2929 | struct arm_prologue_cache *cache; | |
2930 | ||
2931 | if (*this_cache == NULL) | |
a262aec2 | 2932 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 2933 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 2934 | |
a262aec2 | 2935 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
2936 | } |
2937 | ||
a262aec2 DJ |
2938 | static int |
2939 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
2940 | struct frame_info *this_frame, | |
2941 | void **this_prologue_cache) | |
909cf6ea | 2942 | { |
93d42b30 | 2943 | CORE_ADDR addr_in_block; |
948f8e3d | 2944 | gdb_byte dummy[4]; |
18d18ac8 YQ |
2945 | CORE_ADDR pc, start_addr; |
2946 | const char *name; | |
909cf6ea | 2947 | |
a262aec2 | 2948 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 2949 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 2950 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
2951 | /* We also use the stub winder if the target memory is unreadable |
2952 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
2953 | || target_read_memory (pc, dummy, 4) != 0) |
2954 | return 1; | |
2955 | ||
2956 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
2957 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 2958 | return 1; |
909cf6ea | 2959 | |
a262aec2 | 2960 | return 0; |
909cf6ea DJ |
2961 | } |
2962 | ||
a262aec2 DJ |
2963 | struct frame_unwind arm_stub_unwind = { |
2964 | NORMAL_FRAME, | |
8fbca658 | 2965 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
2966 | arm_stub_this_id, |
2967 | arm_prologue_prev_register, | |
2968 | NULL, | |
2969 | arm_stub_unwind_sniffer | |
2970 | }; | |
2971 | ||
2ae28aa9 YQ |
2972 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
2973 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
2974 | returned. */ | |
2975 | ||
2976 | static struct arm_prologue_cache * | |
2977 | arm_m_exception_cache (struct frame_info *this_frame) | |
2978 | { | |
2979 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2980 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2981 | struct arm_prologue_cache *cache; | |
55ea94da FH |
2982 | CORE_ADDR lr; |
2983 | CORE_ADDR sp; | |
2ae28aa9 YQ |
2984 | CORE_ADDR unwound_sp; |
2985 | LONGEST xpsr; | |
55ea94da FH |
2986 | uint32_t exc_return; |
2987 | uint32_t process_stack_used; | |
2988 | uint32_t extended_frame_used; | |
2989 | uint32_t secure_stack_used; | |
2ae28aa9 YQ |
2990 | |
2991 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2992 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2993 | ||
55ea94da FH |
2994 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
2995 | describes which bits in LR that define which stack was used prior | |
2996 | to the exception and if FPU is used (causing extended stack frame). */ | |
2997 | ||
2998 | lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2999 | sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
3000 | ||
3001 | /* Check EXC_RETURN indicator bits. */ | |
3002 | exc_return = (((lr >> 28) & 0xf) == 0xf); | |
3003 | ||
3004 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ | |
3005 | process_stack_used = ((lr & (1 << 2)) != 0); | |
3006 | if (exc_return && process_stack_used) | |
3007 | { | |
3008 | /* Thread (process) stack used. | |
dda83cd7 SM |
3009 | Potentially this could be other register defined by target, but PSP |
3010 | can be considered a standard name for the "Process Stack Pointer". | |
3011 | To be fully aware of system registers like MSP and PSP, these could | |
3012 | be added to a separate XML arm-m-system-profile that is valid for | |
3013 | ARMv6-M and ARMv7-M architectures. Also to be able to debug eg a | |
3014 | corefile off-line, then these registers must be defined by GDB, | |
3015 | and also be included in the corefile regsets. */ | |
55ea94da FH |
3016 | |
3017 | int psp_regnum = user_reg_map_name_to_regnum (gdbarch, "psp", -1); | |
3018 | if (psp_regnum == -1) | |
dda83cd7 SM |
3019 | { |
3020 | /* Thread (process) stack could not be fetched, | |
3021 | give warning and exit. */ | |
55ea94da | 3022 | |
dda83cd7 | 3023 | warning (_("no PSP thread stack unwinding supported.")); |
55ea94da | 3024 | |
dda83cd7 SM |
3025 | /* Terminate any further stack unwinding by refer to self. */ |
3026 | cache->prev_sp = sp; | |
3027 | return cache; | |
3028 | } | |
55ea94da | 3029 | else |
dda83cd7 SM |
3030 | { |
3031 | /* Thread (process) stack used, use PSP as SP. */ | |
3032 | unwound_sp = get_frame_register_unsigned (this_frame, psp_regnum); | |
3033 | } | |
55ea94da FH |
3034 | } |
3035 | else | |
3036 | { | |
3037 | /* Main stack used, use MSP as SP. */ | |
3038 | unwound_sp = sp; | |
3039 | } | |
2ae28aa9 YQ |
3040 | |
3041 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3042 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3043 | "B1.5.6 Exception entry behavior" in | |
3044 | "ARMv7-M Architecture Reference Manual". */ | |
098caef4 LM |
3045 | cache->saved_regs[0].set_addr (unwound_sp); |
3046 | cache->saved_regs[1].set_addr (unwound_sp + 4); | |
3047 | cache->saved_regs[2].set_addr (unwound_sp + 8); | |
3048 | cache->saved_regs[3].set_addr (unwound_sp + 12); | |
3049 | cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + 16); | |
3050 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 20); | |
3051 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 24); | |
3052 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 28); | |
2ae28aa9 | 3053 | |
55ea94da FH |
3054 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) |
3055 | type used. */ | |
3056 | extended_frame_used = ((lr & (1 << 4)) == 0); | |
3057 | if (exc_return && extended_frame_used) | |
3058 | { | |
3059 | int i; | |
3060 | int fpu_regs_stack_offset; | |
3061 | ||
3062 | /* This code does not take into account the lazy stacking, see "Lazy | |
dda83cd7 SM |
3063 | context save of FP state", in B1.5.7, also ARM AN298, supported |
3064 | by Cortex-M4F architecture. | |
3065 | To fully handle this the FPCCR register (Floating-point Context | |
3066 | Control Register) needs to be read out and the bits ASPEN and LSPEN | |
3067 | could be checked to setup correct lazy stacked FP registers. | |
3068 | This register is located at address 0xE000EF34. */ | |
55ea94da FH |
3069 | |
3070 | /* Extended stack frame type used. */ | |
3071 | fpu_regs_stack_offset = unwound_sp + 0x20; | |
3072 | for (i = 0; i < 16; i++) | |
dda83cd7 | 3073 | { |
098caef4 | 3074 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); |
dda83cd7 SM |
3075 | fpu_regs_stack_offset += 4; |
3076 | } | |
098caef4 | 3077 | cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + 0x60); |
55ea94da FH |
3078 | |
3079 | /* Offset 0x64 is reserved. */ | |
3080 | cache->prev_sp = unwound_sp + 0x68; | |
3081 | } | |
3082 | else | |
3083 | { | |
3084 | /* Standard stack frame type used. */ | |
3085 | cache->prev_sp = unwound_sp + 0x20; | |
3086 | } | |
3087 | ||
3088 | /* Check EXC_RETURN bit S if Secure or Non-secure stack used. */ | |
3089 | secure_stack_used = ((lr & (1 << 6)) != 0); | |
3090 | if (exc_return && secure_stack_used) | |
3091 | { | |
3092 | /* ARMv8-M Exception and interrupt handling is not considered here. | |
3093 | In the ARMv8-M architecture also EXC_RETURN bit S is controlling if | |
3094 | the Secure or Non-secure stack was used. To separate Secure and | |
3095 | Non-secure stacks, processors that are based on the ARMv8-M | |
3096 | architecture support 4 stack pointers: MSP_S, PSP_S, MSP_NS, PSP_NS. | |
3097 | In addition, a stack limit feature is provided using stack limit | |
3098 | registers (accessible using MSR and MRS instructions) in Privileged | |
3099 | level. */ | |
3100 | } | |
3101 | ||
2ae28aa9 YQ |
3102 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3103 | aligner between the top of the 32-byte stack frame and the | |
3104 | previous context's stack pointer. */ | |
2ae28aa9 YQ |
3105 | if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) |
3106 | && (xpsr & (1 << 9)) != 0) | |
3107 | cache->prev_sp += 4; | |
3108 | ||
3109 | return cache; | |
3110 | } | |
3111 | ||
3112 | /* Implementation of function hook 'this_id' in | |
3113 | 'struct frame_uwnind'. */ | |
3114 | ||
3115 | static void | |
3116 | arm_m_exception_this_id (struct frame_info *this_frame, | |
3117 | void **this_cache, | |
3118 | struct frame_id *this_id) | |
3119 | { | |
3120 | struct arm_prologue_cache *cache; | |
3121 | ||
3122 | if (*this_cache == NULL) | |
3123 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3124 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3125 | |
3126 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3127 | *this_id = frame_id_build (cache->prev_sp, | |
3128 | get_frame_pc (this_frame)); | |
3129 | } | |
3130 | ||
3131 | /* Implementation of function hook 'prev_register' in | |
3132 | 'struct frame_uwnind'. */ | |
3133 | ||
3134 | static struct value * | |
3135 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
3136 | void **this_cache, | |
3137 | int prev_regnum) | |
3138 | { | |
2ae28aa9 YQ |
3139 | struct arm_prologue_cache *cache; |
3140 | ||
3141 | if (*this_cache == NULL) | |
3142 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3143 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3144 | |
3145 | /* The value was already reconstructed into PREV_SP. */ | |
3146 | if (prev_regnum == ARM_SP_REGNUM) | |
3147 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3148 | cache->prev_sp); | |
3149 | ||
3150 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3151 | prev_regnum); | |
3152 | } | |
3153 | ||
3154 | /* Implementation of function hook 'sniffer' in | |
3155 | 'struct frame_uwnind'. */ | |
3156 | ||
3157 | static int | |
3158 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
3159 | struct frame_info *this_frame, | |
3160 | void **this_prologue_cache) | |
3161 | { | |
3162 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
3163 | ||
3164 | /* No need to check is_m; this sniffer is only registered for | |
3165 | M-profile architectures. */ | |
3166 | ||
ca90e760 FH |
3167 | /* Check if exception frame returns to a magic PC value. */ |
3168 | return arm_m_addr_is_magic (this_pc); | |
2ae28aa9 YQ |
3169 | } |
3170 | ||
3171 | /* Frame unwinder for M-profile exceptions. */ | |
3172 | ||
3173 | struct frame_unwind arm_m_exception_unwind = | |
3174 | { | |
3175 | SIGTRAMP_FRAME, | |
3176 | default_frame_unwind_stop_reason, | |
3177 | arm_m_exception_this_id, | |
3178 | arm_m_exception_prev_register, | |
3179 | NULL, | |
3180 | arm_m_exception_unwind_sniffer | |
3181 | }; | |
3182 | ||
24de872b | 3183 | static CORE_ADDR |
a262aec2 | 3184 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
3185 | { |
3186 | struct arm_prologue_cache *cache; | |
3187 | ||
eb5492fa | 3188 | if (*this_cache == NULL) |
a262aec2 | 3189 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3190 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3191 | |
4be43953 | 3192 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
3193 | } |
3194 | ||
eb5492fa DJ |
3195 | struct frame_base arm_normal_base = { |
3196 | &arm_prologue_unwind, | |
3197 | arm_normal_frame_base, | |
3198 | arm_normal_frame_base, | |
3199 | arm_normal_frame_base | |
3200 | }; | |
3201 | ||
b39cc962 DJ |
3202 | static struct value * |
3203 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
3204 | int regnum) | |
3205 | { | |
24568a2c | 3206 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 | 3207 | CORE_ADDR lr, cpsr; |
9779414d | 3208 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
3209 | |
3210 | switch (regnum) | |
3211 | { | |
3212 | case ARM_PC_REGNUM: | |
3213 | /* The PC is normally copied from the return column, which | |
3214 | describes saves of LR. However, that version may have an | |
3215 | extra bit set to indicate Thumb state. The bit is not | |
3216 | part of the PC. */ | |
3217 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
3218 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3219 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
3220 | |
3221 | case ARM_PS_REGNUM: | |
3222 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 3223 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
3224 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3225 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 3226 | cpsr |= t_bit; |
b39cc962 | 3227 | else |
9779414d | 3228 | cpsr &= ~t_bit; |
ca38c58e | 3229 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3230 | |
3231 | default: | |
3232 | internal_error (__FILE__, __LINE__, | |
3233 | _("Unexpected register %d"), regnum); | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | static void | |
3238 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3239 | struct dwarf2_frame_state_reg *reg, | |
3240 | struct frame_info *this_frame) | |
3241 | { | |
3242 | switch (regnum) | |
3243 | { | |
3244 | case ARM_PC_REGNUM: | |
3245 | case ARM_PS_REGNUM: | |
3246 | reg->how = DWARF2_FRAME_REG_FN; | |
3247 | reg->loc.fn = arm_dwarf2_prev_register; | |
3248 | break; | |
3249 | case ARM_SP_REGNUM: | |
3250 | reg->how = DWARF2_FRAME_REG_CFA; | |
3251 | break; | |
3252 | } | |
3253 | } | |
3254 | ||
c9cf6e20 | 3255 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3256 | |
3257 | static int | |
c9cf6e20 | 3258 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3259 | { |
3260 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3261 | unsigned int insn, insn2; | |
3262 | int found_return = 0, found_stack_adjust = 0; | |
3263 | CORE_ADDR func_start, func_end; | |
3264 | CORE_ADDR scan_pc; | |
3265 | gdb_byte buf[4]; | |
3266 | ||
3267 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3268 | return 0; | |
3269 | ||
3270 | /* The epilogue is a sequence of instructions along the following lines: | |
3271 | ||
3272 | - add stack frame size to SP or FP | |
3273 | - [if frame pointer used] restore SP from FP | |
3274 | - restore registers from SP [may include PC] | |
3275 | - a return-type instruction [if PC wasn't already restored] | |
3276 | ||
3277 | In a first pass, we scan forward from the current PC and verify the | |
3278 | instructions we find as compatible with this sequence, ending in a | |
3279 | return instruction. | |
3280 | ||
3281 | However, this is not sufficient to distinguish indirect function calls | |
3282 | within a function from indirect tail calls in the epilogue in some cases. | |
3283 | Therefore, if we didn't already find any SP-changing instruction during | |
3284 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3285 | are in the epilogue. */ | |
3286 | ||
3287 | scan_pc = pc; | |
3288 | while (scan_pc < func_end && !found_return) | |
3289 | { | |
3290 | if (target_read_memory (scan_pc, buf, 2)) | |
3291 | break; | |
3292 | ||
3293 | scan_pc += 2; | |
3294 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3295 | ||
3296 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3297 | found_return = 1; | |
3298 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3299 | found_return = 1; | |
540314bd | 3300 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3301 | { |
b7576e5c | 3302 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3303 | found_return = 1; |
3304 | } | |
db24da6d | 3305 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3306 | { |
3307 | if (target_read_memory (scan_pc, buf, 2)) | |
3308 | break; | |
3309 | ||
3310 | scan_pc += 2; | |
3311 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3312 | ||
3313 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3314 | { | |
4024ca99 UW |
3315 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3316 | found_return = 1; | |
3317 | } | |
3318 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3319 | && (insn2 & 0x0fff) == 0x0b04) | |
3320 | { | |
4024ca99 UW |
3321 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3322 | found_return = 1; | |
3323 | } | |
3324 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3325 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3326 | ; |
4024ca99 UW |
3327 | else |
3328 | break; | |
3329 | } | |
3330 | else | |
3331 | break; | |
3332 | } | |
3333 | ||
3334 | if (!found_return) | |
3335 | return 0; | |
3336 | ||
3337 | /* Since any instruction in the epilogue sequence, with the possible | |
3338 | exception of return itself, updates the stack pointer, we need to | |
3339 | scan backwards for at most one instruction. Try either a 16-bit or | |
3340 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3341 | too much about false positives. */ |
4024ca99 | 3342 | |
6b65d1b6 YQ |
3343 | if (pc - 4 < func_start) |
3344 | return 0; | |
3345 | if (target_read_memory (pc - 4, buf, 4)) | |
3346 | return 0; | |
4024ca99 | 3347 | |
6b65d1b6 YQ |
3348 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3349 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3350 | ||
3351 | if (thumb_instruction_restores_sp (insn2)) | |
3352 | found_stack_adjust = 1; | |
3353 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3354 | found_stack_adjust = 1; | |
3355 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3356 | && (insn2 & 0x0fff) == 0x0b04) | |
3357 | found_stack_adjust = 1; | |
3358 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3359 | && (insn2 & 0x0e00) == 0x0a00) | |
3360 | found_stack_adjust = 1; | |
4024ca99 UW |
3361 | |
3362 | return found_stack_adjust; | |
3363 | } | |
3364 | ||
4024ca99 | 3365 | static int |
c58b006a | 3366 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3367 | { |
3368 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3369 | unsigned int insn; | |
f303bc3e | 3370 | int found_return; |
4024ca99 UW |
3371 | CORE_ADDR func_start, func_end; |
3372 | ||
4024ca99 UW |
3373 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
3374 | return 0; | |
3375 | ||
3376 | /* We are in the epilogue if the previous instruction was a stack | |
3377 | adjustment and the next instruction is a possible return (bx, mov | |
3378 | pc, or pop). We could have to scan backwards to find the stack | |
3379 | adjustment, or forwards to find the return, but this is a decent | |
3380 | approximation. First scan forwards. */ | |
3381 | ||
3382 | found_return = 0; | |
3383 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3384 | if (bits (insn, 28, 31) != INST_NV) | |
3385 | { | |
3386 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3387 | /* BX. */ | |
3388 | found_return = 1; | |
3389 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3390 | /* MOV PC. */ | |
3391 | found_return = 1; | |
3392 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3393 | && (insn & 0x0000c000) != 0) | |
3394 | /* POP (LDMIA), including PC or LR. */ | |
3395 | found_return = 1; | |
3396 | } | |
3397 | ||
3398 | if (!found_return) | |
3399 | return 0; | |
3400 | ||
3401 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3402 | false positives from mode changes. */ | |
3403 | ||
3404 | if (pc < func_start + 4) | |
3405 | return 0; | |
3406 | ||
3407 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3408 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3409 | return 1; |
3410 | ||
3411 | return 0; | |
3412 | } | |
3413 | ||
c58b006a YQ |
3414 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3415 | ||
3416 | static int | |
3417 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3418 | { | |
3419 | if (arm_pc_is_thumb (gdbarch, pc)) | |
3420 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3421 | else | |
3422 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3423 | } | |
4024ca99 | 3424 | |
2dd604e7 RE |
3425 | /* When arguments must be pushed onto the stack, they go on in reverse |
3426 | order. The code below implements a FILO (stack) to do this. */ | |
3427 | ||
3428 | struct stack_item | |
3429 | { | |
3430 | int len; | |
3431 | struct stack_item *prev; | |
7c543f7b | 3432 | gdb_byte *data; |
2dd604e7 RE |
3433 | }; |
3434 | ||
3435 | static struct stack_item * | |
df3b6708 | 3436 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2dd604e7 RE |
3437 | { |
3438 | struct stack_item *si; | |
8d749320 | 3439 | si = XNEW (struct stack_item); |
7c543f7b | 3440 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
3441 | si->len = len; |
3442 | si->prev = prev; | |
3443 | memcpy (si->data, contents, len); | |
3444 | return si; | |
3445 | } | |
3446 | ||
3447 | static struct stack_item * | |
3448 | pop_stack_item (struct stack_item *si) | |
3449 | { | |
3450 | struct stack_item *dead = si; | |
3451 | si = si->prev; | |
3452 | xfree (dead->data); | |
3453 | xfree (dead); | |
3454 | return si; | |
3455 | } | |
3456 | ||
030197b4 AB |
3457 | /* Implement the gdbarch type alignment method, overrides the generic |
3458 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 3459 | |
030197b4 AB |
3460 | static ULONGEST |
3461 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 3462 | { |
2af48f68 | 3463 | t = check_typedef (t); |
bd63c870 | 3464 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 3465 | { |
030197b4 AB |
3466 | /* Use the natural alignment for vector types (the same for |
3467 | scalar type), but the maximum alignment is 64-bit. */ | |
3468 | if (TYPE_LENGTH (t) > 8) | |
3469 | return 8; | |
c4312b19 | 3470 | else |
030197b4 | 3471 | return TYPE_LENGTH (t); |
2af48f68 | 3472 | } |
030197b4 AB |
3473 | |
3474 | /* Allow the common code to calculate the alignment. */ | |
3475 | return 0; | |
2af48f68 PB |
3476 | } |
3477 | ||
90445bd3 DJ |
3478 | /* Possible base types for a candidate for passing and returning in |
3479 | VFP registers. */ | |
3480 | ||
3481 | enum arm_vfp_cprc_base_type | |
3482 | { | |
3483 | VFP_CPRC_UNKNOWN, | |
3484 | VFP_CPRC_SINGLE, | |
3485 | VFP_CPRC_DOUBLE, | |
3486 | VFP_CPRC_VEC64, | |
3487 | VFP_CPRC_VEC128 | |
3488 | }; | |
3489 | ||
3490 | /* The length of one element of base type B. */ | |
3491 | ||
3492 | static unsigned | |
3493 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
3494 | { | |
3495 | switch (b) | |
3496 | { | |
3497 | case VFP_CPRC_SINGLE: | |
3498 | return 4; | |
3499 | case VFP_CPRC_DOUBLE: | |
3500 | return 8; | |
3501 | case VFP_CPRC_VEC64: | |
3502 | return 8; | |
3503 | case VFP_CPRC_VEC128: | |
3504 | return 16; | |
3505 | default: | |
3506 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3507 | (int) b); | |
3508 | } | |
3509 | } | |
3510 | ||
3511 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
3512 | for passing base type B. */ | |
3513 | ||
3514 | static int | |
3515 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
3516 | { | |
3517 | switch (b) | |
3518 | { | |
3519 | case VFP_CPRC_SINGLE: | |
3520 | return 's'; | |
3521 | case VFP_CPRC_DOUBLE: | |
3522 | return 'd'; | |
3523 | case VFP_CPRC_VEC64: | |
3524 | return 'd'; | |
3525 | case VFP_CPRC_VEC128: | |
3526 | return 'q'; | |
3527 | default: | |
3528 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3529 | (int) b); | |
3530 | } | |
3531 | } | |
3532 | ||
3533 | /* Determine whether T may be part of a candidate for passing and | |
3534 | returning in VFP registers, ignoring the limit on the total number | |
3535 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
3536 | classification of the first valid component found; if it is not | |
3537 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
3538 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
3539 | for passing and returning in VFP registers, a type differently | |
3540 | classified from *BASE_TYPE, or two types differently classified | |
3541 | from each other, return -1, otherwise return the total number of | |
3542 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
3543 | array). Vector types are not currently supported, matching the |
3544 | generic AAPCS support. */ | |
90445bd3 DJ |
3545 | |
3546 | static int | |
3547 | arm_vfp_cprc_sub_candidate (struct type *t, | |
3548 | enum arm_vfp_cprc_base_type *base_type) | |
3549 | { | |
3550 | t = check_typedef (t); | |
78134374 | 3551 | switch (t->code ()) |
90445bd3 DJ |
3552 | { |
3553 | case TYPE_CODE_FLT: | |
3554 | switch (TYPE_LENGTH (t)) | |
3555 | { | |
3556 | case 4: | |
3557 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3558 | *base_type = VFP_CPRC_SINGLE; | |
3559 | else if (*base_type != VFP_CPRC_SINGLE) | |
3560 | return -1; | |
3561 | return 1; | |
3562 | ||
3563 | case 8: | |
3564 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3565 | *base_type = VFP_CPRC_DOUBLE; | |
3566 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3567 | return -1; | |
3568 | return 1; | |
3569 | ||
3570 | default: | |
3571 | return -1; | |
3572 | } | |
3573 | break; | |
3574 | ||
817e0957 YQ |
3575 | case TYPE_CODE_COMPLEX: |
3576 | /* Arguments of complex T where T is one of the types float or | |
3577 | double get treated as if they are implemented as: | |
3578 | ||
3579 | struct complexT | |
3580 | { | |
3581 | T real; | |
3582 | T imag; | |
5f52445b YQ |
3583 | }; |
3584 | ||
3585 | */ | |
817e0957 YQ |
3586 | switch (TYPE_LENGTH (t)) |
3587 | { | |
3588 | case 8: | |
3589 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3590 | *base_type = VFP_CPRC_SINGLE; | |
3591 | else if (*base_type != VFP_CPRC_SINGLE) | |
3592 | return -1; | |
3593 | return 2; | |
3594 | ||
3595 | case 16: | |
3596 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3597 | *base_type = VFP_CPRC_DOUBLE; | |
3598 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3599 | return -1; | |
3600 | return 2; | |
3601 | ||
3602 | default: | |
3603 | return -1; | |
3604 | } | |
3605 | break; | |
3606 | ||
90445bd3 DJ |
3607 | case TYPE_CODE_ARRAY: |
3608 | { | |
bd63c870 | 3609 | if (t->is_vector ()) |
90445bd3 | 3610 | { |
c4312b19 YQ |
3611 | /* A 64-bit or 128-bit containerized vector type are VFP |
3612 | CPRCs. */ | |
3613 | switch (TYPE_LENGTH (t)) | |
3614 | { | |
3615 | case 8: | |
3616 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3617 | *base_type = VFP_CPRC_VEC64; | |
3618 | return 1; | |
3619 | case 16: | |
3620 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3621 | *base_type = VFP_CPRC_VEC128; | |
3622 | return 1; | |
3623 | default: | |
3624 | return -1; | |
3625 | } | |
3626 | } | |
3627 | else | |
3628 | { | |
3629 | int count; | |
3630 | unsigned unitlen; | |
3631 | ||
3632 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), | |
3633 | base_type); | |
3634 | if (count == -1) | |
3635 | return -1; | |
3636 | if (TYPE_LENGTH (t) == 0) | |
3637 | { | |
3638 | gdb_assert (count == 0); | |
3639 | return 0; | |
3640 | } | |
3641 | else if (count == 0) | |
3642 | return -1; | |
3643 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3644 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
3645 | return TYPE_LENGTH (t) / unitlen; | |
90445bd3 | 3646 | } |
90445bd3 DJ |
3647 | } |
3648 | break; | |
3649 | ||
3650 | case TYPE_CODE_STRUCT: | |
3651 | { | |
3652 | int count = 0; | |
3653 | unsigned unitlen; | |
3654 | int i; | |
1f704f76 | 3655 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3656 | { |
1040b979 YQ |
3657 | int sub_count = 0; |
3658 | ||
ceacbf6e | 3659 | if (!field_is_static (&t->field (i))) |
940da03e | 3660 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 3661 | base_type); |
90445bd3 DJ |
3662 | if (sub_count == -1) |
3663 | return -1; | |
3664 | count += sub_count; | |
3665 | } | |
3666 | if (TYPE_LENGTH (t) == 0) | |
3667 | { | |
3668 | gdb_assert (count == 0); | |
3669 | return 0; | |
3670 | } | |
3671 | else if (count == 0) | |
3672 | return -1; | |
3673 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3674 | if (TYPE_LENGTH (t) != unitlen * count) | |
3675 | return -1; | |
3676 | return count; | |
3677 | } | |
3678 | ||
3679 | case TYPE_CODE_UNION: | |
3680 | { | |
3681 | int count = 0; | |
3682 | unsigned unitlen; | |
3683 | int i; | |
1f704f76 | 3684 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3685 | { |
940da03e | 3686 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
3687 | base_type); |
3688 | if (sub_count == -1) | |
3689 | return -1; | |
3690 | count = (count > sub_count ? count : sub_count); | |
3691 | } | |
3692 | if (TYPE_LENGTH (t) == 0) | |
3693 | { | |
3694 | gdb_assert (count == 0); | |
3695 | return 0; | |
3696 | } | |
3697 | else if (count == 0) | |
3698 | return -1; | |
3699 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3700 | if (TYPE_LENGTH (t) != unitlen * count) | |
3701 | return -1; | |
3702 | return count; | |
3703 | } | |
3704 | ||
3705 | default: | |
3706 | break; | |
3707 | } | |
3708 | ||
3709 | return -1; | |
3710 | } | |
3711 | ||
3712 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
3713 | if passed to or returned from a non-variadic function with the VFP | |
3714 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
3715 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
3716 | elements of that base type before returning. */ | |
3717 | ||
3718 | static int | |
3719 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
3720 | int *count) | |
3721 | { | |
3722 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
3723 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
3724 | if (c <= 0 || c > 4) | |
3725 | return 0; | |
3726 | *base_type = b; | |
3727 | *count = c; | |
3728 | return 1; | |
3729 | } | |
3730 | ||
3731 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
3732 | returning values from a function of type FUNC_TYPE, 0 | |
3733 | otherwise. */ | |
3734 | ||
3735 | static int | |
3736 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
3737 | { | |
3738 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3739 | /* Variadic functions always use the base ABI. Assume that functions | |
3740 | without debug info are not variadic. */ | |
a409645d | 3741 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 DJ |
3742 | return 0; |
3743 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
3744 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
3745 | return 0; | |
3746 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
3747 | } | |
3748 | ||
3749 | /* We currently only support passing parameters in integer registers, which | |
3750 | conforms with GCC's default model, and VFP argument passing following | |
3751 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
3752 | we should probably support some of them based on the selected ABI. */ |
3753 | ||
3754 | static CORE_ADDR | |
7d9b040b | 3755 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 3756 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
3757 | struct value **args, CORE_ADDR sp, |
3758 | function_call_return_method return_method, | |
6a65450a | 3759 | CORE_ADDR struct_addr) |
2dd604e7 | 3760 | { |
e17a4113 | 3761 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
3762 | int argnum; |
3763 | int argreg; | |
3764 | int nstack; | |
3765 | struct stack_item *si = NULL; | |
90445bd3 DJ |
3766 | int use_vfp_abi; |
3767 | struct type *ftype; | |
3768 | unsigned vfp_regs_free = (1 << 16) - 1; | |
3769 | ||
3770 | /* Determine the type of this function and whether the VFP ABI | |
3771 | applies. */ | |
3772 | ftype = check_typedef (value_type (function)); | |
78134374 | 3773 | if (ftype->code () == TYPE_CODE_PTR) |
90445bd3 DJ |
3774 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
3775 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 3776 | |
6a65450a AC |
3777 | /* Set the return address. For the ARM, the return breakpoint is |
3778 | always at BP_ADDR. */ | |
9779414d | 3779 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 3780 | bp_addr |= 1; |
6a65450a | 3781 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
3782 | |
3783 | /* Walk through the list of args and determine how large a temporary | |
3784 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 3785 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
3786 | nstack = 0; |
3787 | ||
3788 | argreg = ARM_A1_REGNUM; | |
3789 | nstack = 0; | |
3790 | ||
2dd604e7 RE |
3791 | /* The struct_return pointer occupies the first parameter |
3792 | passing register. */ | |
cf84fa6b | 3793 | if (return_method == return_method_struct) |
2dd604e7 | 3794 | { |
7cb6d92a SM |
3795 | arm_debug_printf ("struct return in %s = %s", |
3796 | gdbarch_register_name (gdbarch, argreg), | |
3797 | paddress (gdbarch, struct_addr)); | |
3798 | ||
2dd604e7 RE |
3799 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
3800 | argreg++; | |
3801 | } | |
3802 | ||
3803 | for (argnum = 0; argnum < nargs; argnum++) | |
3804 | { | |
3805 | int len; | |
3806 | struct type *arg_type; | |
3807 | struct type *target_type; | |
3808 | enum type_code typecode; | |
8c6363cf | 3809 | const bfd_byte *val; |
2af48f68 | 3810 | int align; |
90445bd3 DJ |
3811 | enum arm_vfp_cprc_base_type vfp_base_type; |
3812 | int vfp_base_count; | |
3813 | int may_use_core_reg = 1; | |
2dd604e7 | 3814 | |
df407dfe | 3815 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
3816 | len = TYPE_LENGTH (arg_type); |
3817 | target_type = TYPE_TARGET_TYPE (arg_type); | |
78134374 | 3818 | typecode = arg_type->code (); |
8c6363cf | 3819 | val = value_contents (args[argnum]); |
2dd604e7 | 3820 | |
030197b4 | 3821 | align = type_align (arg_type); |
2af48f68 | 3822 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
3823 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
3824 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 PB |
3825 | /* Different ABIs have different maximum alignments. */ |
3826 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
3827 | { | |
3828 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 3829 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
3830 | } |
3831 | else | |
3832 | { | |
3833 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
3834 | if (align > ARM_INT_REGISTER_SIZE * 2) |
3835 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
3836 | } |
3837 | ||
90445bd3 DJ |
3838 | if (use_vfp_abi |
3839 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
3840 | &vfp_base_count)) | |
3841 | { | |
3842 | int regno; | |
3843 | int unit_length; | |
3844 | int shift; | |
3845 | unsigned mask; | |
3846 | ||
3847 | /* Because this is a CPRC it cannot go in a core register or | |
3848 | cause a core register to be skipped for alignment. | |
3849 | Either it goes in VFP registers and the rest of this loop | |
3850 | iteration is skipped for this argument, or it goes on the | |
3851 | stack (and the stack alignment code is correct for this | |
3852 | case). */ | |
3853 | may_use_core_reg = 0; | |
3854 | ||
3855 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3856 | shift = unit_length / 4; | |
3857 | mask = (1 << (shift * vfp_base_count)) - 1; | |
3858 | for (regno = 0; regno < 16; regno += shift) | |
3859 | if (((vfp_regs_free >> regno) & mask) == mask) | |
3860 | break; | |
3861 | ||
3862 | if (regno < 16) | |
3863 | { | |
3864 | int reg_char; | |
3865 | int reg_scaled; | |
3866 | int i; | |
3867 | ||
3868 | vfp_regs_free &= ~(mask << regno); | |
3869 | reg_scaled = regno / shift; | |
3870 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3871 | for (i = 0; i < vfp_base_count; i++) | |
3872 | { | |
3873 | char name_buf[4]; | |
3874 | int regnum; | |
58d6951d DJ |
3875 | if (reg_char == 'q') |
3876 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 3877 | val + i * unit_length); |
58d6951d DJ |
3878 | else |
3879 | { | |
8c042590 PM |
3880 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
3881 | reg_char, reg_scaled + i); | |
58d6951d DJ |
3882 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
3883 | strlen (name_buf)); | |
b66f5587 | 3884 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 3885 | } |
90445bd3 DJ |
3886 | } |
3887 | continue; | |
3888 | } | |
3889 | else | |
3890 | { | |
3891 | /* This CPRC could not go in VFP registers, so all VFP | |
3892 | registers are now marked as used. */ | |
3893 | vfp_regs_free = 0; | |
3894 | } | |
3895 | } | |
3896 | ||
85102364 | 3897 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
3898 | if (nstack & (align - 1)) |
3899 | { | |
f0452268 AH |
3900 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
3901 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
3902 | } |
3903 | ||
3904 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
3905 | if (may_use_core_reg |
3906 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 3907 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
3908 | && argreg & 1) |
3909 | argreg++; | |
3910 | ||
2dd604e7 RE |
3911 | /* If the argument is a pointer to a function, and it is a |
3912 | Thumb function, create a LOCAL copy of the value and set | |
3913 | the THUMB bit in it. */ | |
3914 | if (TYPE_CODE_PTR == typecode | |
3915 | && target_type != NULL | |
78134374 | 3916 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 3917 | { |
e17a4113 | 3918 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 3919 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 3920 | { |
224c3ddb | 3921 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 3922 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 3923 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 3924 | val = copy; |
2dd604e7 RE |
3925 | } |
3926 | } | |
3927 | ||
3928 | /* Copy the argument to general registers or the stack in | |
3929 | register-sized pieces. Large arguments are split between | |
3930 | registers and stack. */ | |
3931 | while (len > 0) | |
3932 | { | |
f0452268 AH |
3933 | int partial_len = len < ARM_INT_REGISTER_SIZE |
3934 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
3935 | CORE_ADDR regval |
3936 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 3937 | |
90445bd3 | 3938 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
3939 | { |
3940 | /* The argument is being passed in a general purpose | |
3941 | register. */ | |
e17a4113 | 3942 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 3943 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
7cb6d92a SM |
3944 | |
3945 | arm_debug_printf ("arg %d in %s = 0x%s", argnum, | |
3946 | gdbarch_register_name (gdbarch, argreg), | |
3947 | phex (regval, ARM_INT_REGISTER_SIZE)); | |
3948 | ||
2dd604e7 RE |
3949 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
3950 | argreg++; | |
3951 | } | |
3952 | else | |
3953 | { | |
f0452268 | 3954 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
3955 | |
3956 | memset (buf, 0, sizeof (buf)); | |
3957 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
3958 | ||
2dd604e7 | 3959 | /* Push the arguments onto the stack. */ |
7cb6d92a | 3960 | arm_debug_printf ("arg %d @ sp + %d", argnum, nstack); |
f0452268 AH |
3961 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
3962 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
3963 | } |
3964 | ||
3965 | len -= partial_len; | |
3966 | val += partial_len; | |
3967 | } | |
3968 | } | |
3969 | /* If we have an odd number of words to push, then decrement the stack | |
3970 | by one word now, so first stack argument will be dword aligned. */ | |
3971 | if (nstack & 4) | |
3972 | sp -= 4; | |
3973 | ||
3974 | while (si) | |
3975 | { | |
3976 | sp -= si->len; | |
3977 | write_memory (sp, si->data, si->len); | |
3978 | si = pop_stack_item (si); | |
3979 | } | |
3980 | ||
3981 | /* Finally, update teh SP register. */ | |
3982 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
3983 | ||
3984 | return sp; | |
3985 | } | |
3986 | ||
f53f0d0b PB |
3987 | |
3988 | /* Always align the frame to an 8-byte boundary. This is required on | |
3989 | some platforms and harmless on the rest. */ | |
3990 | ||
3991 | static CORE_ADDR | |
3992 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
3993 | { | |
3994 | /* Align the stack to eight bytes. */ | |
3995 | return sp & ~ (CORE_ADDR) 7; | |
3996 | } | |
3997 | ||
c906108c | 3998 | static void |
12b27276 | 3999 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 4000 | { |
c5aa993b | 4001 | if (flags & (1 << 0)) |
12b27276 | 4002 | fputs_filtered ("IVO ", file); |
c5aa993b | 4003 | if (flags & (1 << 1)) |
12b27276 | 4004 | fputs_filtered ("DVZ ", file); |
c5aa993b | 4005 | if (flags & (1 << 2)) |
12b27276 | 4006 | fputs_filtered ("OFL ", file); |
c5aa993b | 4007 | if (flags & (1 << 3)) |
12b27276 | 4008 | fputs_filtered ("UFL ", file); |
c5aa993b | 4009 | if (flags & (1 << 4)) |
12b27276 WN |
4010 | fputs_filtered ("INX ", file); |
4011 | fputc_filtered ('\n', file); | |
c906108c SS |
4012 | } |
4013 | ||
5e74b15c RE |
4014 | /* Print interesting information about the floating point processor |
4015 | (if present) or emulator. */ | |
34e8f22d | 4016 | static void |
d855c300 | 4017 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 4018 | struct frame_info *frame, const char *args) |
c906108c | 4019 | { |
9c9acae0 | 4020 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4021 | int type; |
4022 | ||
4023 | type = (status >> 24) & 127; | |
edefbb7c | 4024 | if (status & (1 << 31)) |
12b27276 | 4025 | fprintf_filtered (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4026 | else |
12b27276 | 4027 | fprintf_filtered (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4028 | /* i18n: [floating point unit] mask */ |
12b27276 WN |
4029 | fputs_filtered (_("mask: "), file); |
4030 | print_fpu_flags (file, status >> 16); | |
edefbb7c | 4031 | /* i18n: [floating point unit] flags */ |
12b27276 WN |
4032 | fputs_filtered (_("flags: "), file); |
4033 | print_fpu_flags (file, status); | |
c906108c SS |
4034 | } |
4035 | ||
27067745 UW |
4036 | /* Construct the ARM extended floating point type. */ |
4037 | static struct type * | |
4038 | arm_ext_type (struct gdbarch *gdbarch) | |
4039 | { | |
4040 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4041 | ||
4042 | if (!tdep->arm_ext_type) | |
4043 | tdep->arm_ext_type | |
e9bb382b | 4044 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4045 | floatformats_arm_ext); |
4046 | ||
4047 | return tdep->arm_ext_type; | |
4048 | } | |
4049 | ||
58d6951d DJ |
4050 | static struct type * |
4051 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4052 | { | |
4053 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4054 | ||
4055 | if (tdep->neon_double_type == NULL) | |
4056 | { | |
4057 | struct type *t, *elem; | |
4058 | ||
4059 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4060 | TYPE_CODE_UNION); | |
4061 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4062 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4063 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4064 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4065 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4066 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4067 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4068 | append_composite_type_field (t, "u64", elem); | |
4069 | elem = builtin_type (gdbarch)->builtin_float; | |
4070 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4071 | elem = builtin_type (gdbarch)->builtin_double; | |
4072 | append_composite_type_field (t, "f64", elem); | |
4073 | ||
2062087b | 4074 | t->set_is_vector (true); |
d0e39ea2 | 4075 | t->set_name ("neon_d"); |
58d6951d DJ |
4076 | tdep->neon_double_type = t; |
4077 | } | |
4078 | ||
4079 | return tdep->neon_double_type; | |
4080 | } | |
4081 | ||
4082 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4083 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4084 | bits of d0 - regardless of what unit size is being held in d0. So | |
4085 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4086 | first float is 4. This code works as-is for little-endian | |
4087 | targets. */ | |
4088 | ||
4089 | static struct type * | |
4090 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4091 | { | |
4092 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4093 | ||
4094 | if (tdep->neon_quad_type == NULL) | |
4095 | { | |
4096 | struct type *t, *elem; | |
4097 | ||
4098 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4099 | TYPE_CODE_UNION); | |
4100 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4101 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4102 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4103 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4104 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4105 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4106 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4107 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4108 | elem = builtin_type (gdbarch)->builtin_float; | |
4109 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4110 | elem = builtin_type (gdbarch)->builtin_double; | |
4111 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4112 | ||
2062087b | 4113 | t->set_is_vector (true); |
d0e39ea2 | 4114 | t->set_name ("neon_q"); |
58d6951d DJ |
4115 | tdep->neon_quad_type = t; |
4116 | } | |
4117 | ||
4118 | return tdep->neon_quad_type; | |
4119 | } | |
4120 | ||
34e8f22d RE |
4121 | /* Return the GDB type object for the "standard" data type of data in |
4122 | register N. */ | |
4123 | ||
4124 | static struct type * | |
7a5ea0d4 | 4125 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4126 | { |
58d6951d DJ |
4127 | int num_regs = gdbarch_num_regs (gdbarch); |
4128 | ||
4129 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
4130 | && regnum >= num_regs && regnum < num_regs + 32) | |
4131 | return builtin_type (gdbarch)->builtin_float; | |
4132 | ||
4133 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
4134 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
4135 | return arm_neon_quad_type (gdbarch); | |
4136 | ||
4137 | /* If the target description has register information, we are only | |
4138 | in this function so that we can override the types of | |
4139 | double-precision registers for NEON. */ | |
4140 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4141 | { | |
4142 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4143 | ||
4144 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 4145 | && t->code () == TYPE_CODE_FLT |
58d6951d DJ |
4146 | && gdbarch_tdep (gdbarch)->have_neon) |
4147 | return arm_neon_double_type (gdbarch); | |
4148 | else | |
4149 | return t; | |
4150 | } | |
4151 | ||
34e8f22d | 4152 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
4153 | { |
4154 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
4155 | return builtin_type (gdbarch)->builtin_void; | |
4156 | ||
4157 | return arm_ext_type (gdbarch); | |
4158 | } | |
e4c16157 | 4159 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4160 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4161 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4162 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4163 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4164 | /* These registers are only supported on targets which supply | |
4165 | an XML description. */ | |
df4df182 | 4166 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4167 | else |
df4df182 | 4168 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4169 | } |
4170 | ||
ff6f572f DJ |
4171 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4172 | number. */ | |
4173 | ||
4174 | static int | |
d3f73121 | 4175 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4176 | { |
4177 | /* Core integer regs. */ | |
4178 | if (reg >= 0 && reg <= 15) | |
4179 | return reg; | |
4180 | ||
4181 | /* Legacy FPA encoding. These were once used in a way which | |
4182 | overlapped with VFP register numbering, so their use is | |
4183 | discouraged, but GDB doesn't support the ARM toolchain | |
4184 | which used them for VFP. */ | |
4185 | if (reg >= 16 && reg <= 23) | |
4186 | return ARM_F0_REGNUM + reg - 16; | |
4187 | ||
4188 | /* New assignments for the FPA registers. */ | |
4189 | if (reg >= 96 && reg <= 103) | |
4190 | return ARM_F0_REGNUM + reg - 96; | |
4191 | ||
4192 | /* WMMX register assignments. */ | |
4193 | if (reg >= 104 && reg <= 111) | |
4194 | return ARM_WCGR0_REGNUM + reg - 104; | |
4195 | ||
4196 | if (reg >= 112 && reg <= 127) | |
4197 | return ARM_WR0_REGNUM + reg - 112; | |
4198 | ||
4199 | if (reg >= 192 && reg <= 199) | |
4200 | return ARM_WC0_REGNUM + reg - 192; | |
4201 | ||
58d6951d DJ |
4202 | /* VFP v2 registers. A double precision value is actually |
4203 | in d1 rather than s2, but the ABI only defines numbering | |
4204 | for the single precision registers. This will "just work" | |
4205 | in GDB for little endian targets (we'll read eight bytes, | |
4206 | starting in s0 and then progressing to s1), but will be | |
4207 | reversed on big endian targets with VFP. This won't | |
4208 | be a problem for the new Neon quad registers; you're supposed | |
4209 | to use DW_OP_piece for those. */ | |
4210 | if (reg >= 64 && reg <= 95) | |
4211 | { | |
4212 | char name_buf[4]; | |
4213 | ||
8c042590 | 4214 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4215 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4216 | strlen (name_buf)); | |
4217 | } | |
4218 | ||
4219 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4220 | registers, except that it now describes d0 instead of s0. */ | |
4221 | if (reg >= 256 && reg <= 287) | |
4222 | { | |
4223 | char name_buf[4]; | |
4224 | ||
8c042590 | 4225 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4226 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4227 | strlen (name_buf)); | |
4228 | } | |
4229 | ||
ff6f572f DJ |
4230 | return -1; |
4231 | } | |
4232 | ||
26216b98 AC |
4233 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4234 | static int | |
e7faf938 | 4235 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4236 | { |
4237 | int reg = regnum; | |
e7faf938 | 4238 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4239 | |
ff6f572f DJ |
4240 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4241 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4242 | ||
4243 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4244 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4245 | ||
4246 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4247 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4248 | ||
26216b98 AC |
4249 | if (reg < NUM_GREGS) |
4250 | return SIM_ARM_R0_REGNUM + reg; | |
4251 | reg -= NUM_GREGS; | |
4252 | ||
4253 | if (reg < NUM_FREGS) | |
4254 | return SIM_ARM_FP0_REGNUM + reg; | |
4255 | reg -= NUM_FREGS; | |
4256 | ||
4257 | if (reg < NUM_SREGS) | |
4258 | return SIM_ARM_FPS_REGNUM + reg; | |
4259 | reg -= NUM_SREGS; | |
4260 | ||
edefbb7c | 4261 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4262 | } |
34e8f22d | 4263 | |
d9311bfa AT |
4264 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
4265 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
4266 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 4267 | |
d9311bfa AT |
4268 | static gdb_byte * |
4269 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
4270 | int old_len, int new_len) | |
4271 | { | |
4272 | gdb_byte *new_buf; | |
4273 | int bytes_to_read = new_len - old_len; | |
c906108c | 4274 | |
d9311bfa AT |
4275 | new_buf = (gdb_byte *) xmalloc (new_len); |
4276 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
4277 | xfree (buf); | |
198cd59d | 4278 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
4279 | { |
4280 | xfree (new_buf); | |
4281 | return NULL; | |
c906108c | 4282 | } |
d9311bfa | 4283 | return new_buf; |
c906108c SS |
4284 | } |
4285 | ||
d9311bfa AT |
4286 | /* An IT block is at most the 2-byte IT instruction followed by |
4287 | four 4-byte instructions. The furthest back we must search to | |
4288 | find an IT block that affects the current instruction is thus | |
4289 | 2 + 3 * 4 == 14 bytes. */ | |
4290 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 4291 | |
d9311bfa AT |
4292 | /* Use a quick scan if there are more than this many bytes of |
4293 | code. */ | |
4294 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 4295 | |
d9311bfa AT |
4296 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
4297 | A breakpoint in an IT block may not be hit, depending on the | |
4298 | condition flags. */ | |
ad527d2e | 4299 | static CORE_ADDR |
d9311bfa | 4300 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 4301 | { |
d9311bfa AT |
4302 | gdb_byte *buf; |
4303 | char map_type; | |
4304 | CORE_ADDR boundary, func_start; | |
4305 | int buf_len; | |
4306 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
4307 | int i, any, last_it, last_it_count; | |
177321bd | 4308 | |
d9311bfa AT |
4309 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
4310 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) | |
4311 | return bpaddr; | |
177321bd | 4312 | |
d9311bfa AT |
4313 | /* ARM mode does not have this problem. */ |
4314 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
4315 | return bpaddr; | |
177321bd | 4316 | |
d9311bfa AT |
4317 | /* We are setting a breakpoint in Thumb code that could potentially |
4318 | contain an IT block. The first step is to find how much Thumb | |
4319 | code there is; we do not need to read outside of known Thumb | |
4320 | sequences. */ | |
4321 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
4322 | if (map_type == 0) | |
4323 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
4324 | return bpaddr; | |
9dca5578 | 4325 | |
d9311bfa | 4326 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 4327 | |
d9311bfa AT |
4328 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
4329 | && func_start > boundary) | |
4330 | boundary = func_start; | |
9dca5578 | 4331 | |
d9311bfa AT |
4332 | /* Search for a candidate IT instruction. We have to do some fancy |
4333 | footwork to distinguish a real IT instruction from the second | |
4334 | half of a 32-bit instruction, but there is no need for that if | |
4335 | there's no candidate. */ | |
325fac50 | 4336 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
4337 | if (buf_len == 0) |
4338 | /* No room for an IT instruction. */ | |
4339 | return bpaddr; | |
c906108c | 4340 | |
d9311bfa | 4341 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 4342 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
4343 | return bpaddr; |
4344 | any = 0; | |
4345 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 4346 | { |
d9311bfa AT |
4347 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
4348 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 4349 | { |
d9311bfa AT |
4350 | any = 1; |
4351 | break; | |
25b41d01 | 4352 | } |
c906108c | 4353 | } |
d9311bfa AT |
4354 | |
4355 | if (any == 0) | |
c906108c | 4356 | { |
d9311bfa AT |
4357 | xfree (buf); |
4358 | return bpaddr; | |
f9d67f43 DJ |
4359 | } |
4360 | ||
4361 | /* OK, the code bytes before this instruction contain at least one | |
4362 | halfword which resembles an IT instruction. We know that it's | |
4363 | Thumb code, but there are still two possibilities. Either the | |
4364 | halfword really is an IT instruction, or it is the second half of | |
4365 | a 32-bit Thumb instruction. The only way we can tell is to | |
4366 | scan forwards from a known instruction boundary. */ | |
4367 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
4368 | { | |
4369 | int definite; | |
4370 | ||
4371 | /* There's a lot of code before this instruction. Start with an | |
4372 | optimistic search; it's easy to recognize halfwords that can | |
4373 | not be the start of a 32-bit instruction, and use that to | |
4374 | lock on to the instruction boundaries. */ | |
4375 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
4376 | if (buf == NULL) | |
4377 | return bpaddr; | |
4378 | buf_len = IT_SCAN_THRESHOLD; | |
4379 | ||
4380 | definite = 0; | |
4381 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
4382 | { | |
4383 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4384 | if (thumb_insn_size (inst1) == 2) | |
4385 | { | |
4386 | definite = 1; | |
4387 | break; | |
4388 | } | |
4389 | } | |
4390 | ||
4391 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
4392 | are sure that we know the instruction boundaries, and it is far | |
4393 | enough from BPADDR that we could not miss an IT instruction | |
4394 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
4395 | known boundary. */ | |
4396 | if (! definite) | |
4397 | { | |
0963b4bd MS |
4398 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
4399 | bpaddr - boundary); | |
f9d67f43 DJ |
4400 | if (buf == NULL) |
4401 | return bpaddr; | |
4402 | buf_len = bpaddr - boundary; | |
4403 | i = 0; | |
4404 | } | |
4405 | } | |
4406 | else | |
4407 | { | |
4408 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
4409 | if (buf == NULL) | |
4410 | return bpaddr; | |
4411 | buf_len = bpaddr - boundary; | |
4412 | i = 0; | |
4413 | } | |
4414 | ||
4415 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
4416 | last_it = -1; | |
4417 | last_it_count = 0; | |
4418 | while (i < buf_len) | |
4419 | { | |
4420 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4421 | last_it_count--; | |
4422 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
4423 | { | |
4424 | last_it = i; | |
4425 | if (inst1 & 0x0001) | |
4426 | last_it_count = 4; | |
4427 | else if (inst1 & 0x0002) | |
4428 | last_it_count = 3; | |
4429 | else if (inst1 & 0x0004) | |
4430 | last_it_count = 2; | |
4431 | else | |
4432 | last_it_count = 1; | |
4433 | } | |
4434 | i += thumb_insn_size (inst1); | |
4435 | } | |
4436 | ||
4437 | xfree (buf); | |
4438 | ||
4439 | if (last_it == -1) | |
4440 | /* There wasn't really an IT instruction after all. */ | |
4441 | return bpaddr; | |
4442 | ||
4443 | if (last_it_count < 1) | |
4444 | /* It was too far away. */ | |
4445 | return bpaddr; | |
4446 | ||
4447 | /* This really is a trouble spot. Move the breakpoint to the IT | |
4448 | instruction. */ | |
4449 | return bpaddr - buf_len + last_it; | |
4450 | } | |
4451 | ||
cca44b1b | 4452 | /* ARM displaced stepping support. |
c906108c | 4453 | |
cca44b1b | 4454 | Generally ARM displaced stepping works as follows: |
c906108c | 4455 | |
cca44b1b | 4456 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
4457 | arm_process_displaced_insn. Depending on the type of instruction, it is |
4458 | then copied to a scratch location, possibly in a modified form. The | |
4459 | copy_* set of functions performs such modification, as necessary. A | |
4460 | breakpoint is placed after the modified instruction in the scratch space | |
4461 | to return control to GDB. Note in particular that instructions which | |
4462 | modify the PC will no longer do so after modification. | |
c5aa993b | 4463 | |
cca44b1b JB |
4464 | 2. The instruction is single-stepped, by setting the PC to the scratch |
4465 | location address, and resuming. Control returns to GDB when the | |
4466 | breakpoint is hit. | |
c5aa993b | 4467 | |
cca44b1b JB |
4468 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
4469 | function used for the current instruction. This function's job is to | |
4470 | put the CPU/memory state back to what it would have been if the | |
4471 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 4472 | |
cca44b1b JB |
4473 | /* NOP instruction (mov r0, r0). */ |
4474 | #define ARM_NOP 0xe1a00000 | |
34518530 | 4475 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
4476 | |
4477 | /* Helper for register reads for displaced stepping. In particular, this | |
4478 | returns the PC as it would be seen by the instruction at its original | |
4479 | location. */ | |
4480 | ||
4481 | ULONGEST | |
1152d984 | 4482 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4483 | int regno) |
cca44b1b JB |
4484 | { |
4485 | ULONGEST ret; | |
36073a92 | 4486 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 4487 | |
bf9f652a | 4488 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 4489 | { |
4db71c0b YQ |
4490 | /* Compute pipeline offset: |
4491 | - When executing an ARM instruction, PC reads as the address of the | |
4492 | current instruction plus 8. | |
4493 | - When executing a Thumb instruction, PC reads as the address of the | |
4494 | current instruction plus 4. */ | |
4495 | ||
36073a92 | 4496 | if (!dsc->is_thumb) |
4db71c0b YQ |
4497 | from += 8; |
4498 | else | |
4499 | from += 4; | |
4500 | ||
136821d9 SM |
4501 | displaced_debug_printf ("read pc value %.8lx", |
4502 | (unsigned long) from); | |
4db71c0b | 4503 | return (ULONGEST) from; |
cca44b1b | 4504 | } |
c906108c | 4505 | else |
cca44b1b JB |
4506 | { |
4507 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
4508 | |
4509 | displaced_debug_printf ("read r%d value %.8lx", | |
4510 | regno, (unsigned long) ret); | |
4511 | ||
cca44b1b JB |
4512 | return ret; |
4513 | } | |
c906108c SS |
4514 | } |
4515 | ||
cca44b1b JB |
4516 | static int |
4517 | displaced_in_arm_mode (struct regcache *regs) | |
4518 | { | |
4519 | ULONGEST ps; | |
ac7936df | 4520 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 4521 | |
cca44b1b | 4522 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 4523 | |
9779414d | 4524 | return (ps & t_bit) == 0; |
cca44b1b | 4525 | } |
66e810cd | 4526 | |
cca44b1b | 4527 | /* Write to the PC as from a branch instruction. */ |
c906108c | 4528 | |
cca44b1b | 4529 | static void |
1152d984 | 4530 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4531 | ULONGEST val) |
c906108c | 4532 | { |
36073a92 | 4533 | if (!dsc->is_thumb) |
cca44b1b JB |
4534 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
4535 | architecture versions < 6. */ | |
0963b4bd MS |
4536 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4537 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 4538 | else |
0963b4bd MS |
4539 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4540 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 4541 | } |
66e810cd | 4542 | |
cca44b1b JB |
4543 | /* Write to the PC as from a branch-exchange instruction. */ |
4544 | ||
4545 | static void | |
4546 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
4547 | { | |
4548 | ULONGEST ps; | |
ac7936df | 4549 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
4550 | |
4551 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
4552 | ||
4553 | if ((val & 1) == 1) | |
c906108c | 4554 | { |
9779414d | 4555 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
4556 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
4557 | } | |
4558 | else if ((val & 2) == 0) | |
4559 | { | |
9779414d | 4560 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4561 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
4562 | } |
4563 | else | |
4564 | { | |
cca44b1b JB |
4565 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
4566 | mode, align dest to 4 bytes). */ | |
4567 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 4568 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4569 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
4570 | } |
4571 | } | |
ed9a39eb | 4572 | |
cca44b1b | 4573 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 4574 | |
34e8f22d | 4575 | static void |
1152d984 | 4576 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4577 | ULONGEST val) |
ed9a39eb | 4578 | { |
cca44b1b JB |
4579 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
4580 | bx_write_pc (regs, val); | |
4581 | else | |
36073a92 | 4582 | branch_write_pc (regs, dsc, val); |
cca44b1b | 4583 | } |
be8626e0 | 4584 | |
cca44b1b JB |
4585 | /* Write to the PC as if from an ALU instruction. */ |
4586 | ||
4587 | static void | |
1152d984 | 4588 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4589 | ULONGEST val) |
cca44b1b | 4590 | { |
36073a92 | 4591 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
4592 | bx_write_pc (regs, val); |
4593 | else | |
36073a92 | 4594 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
4595 | } |
4596 | ||
4597 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
4598 | has a varying effects depending on the instruction which does the write: | |
4599 | this is controlled by the WRITE_PC argument. */ | |
4600 | ||
4601 | void | |
1152d984 | 4602 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
4603 | int regno, ULONGEST val, enum pc_write_style write_pc) |
4604 | { | |
bf9f652a | 4605 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 4606 | { |
136821d9 SM |
4607 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
4608 | ||
cca44b1b | 4609 | switch (write_pc) |
08216dd7 | 4610 | { |
cca44b1b | 4611 | case BRANCH_WRITE_PC: |
36073a92 | 4612 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
4613 | break; |
4614 | ||
cca44b1b JB |
4615 | case BX_WRITE_PC: |
4616 | bx_write_pc (regs, val); | |
4617 | break; | |
4618 | ||
4619 | case LOAD_WRITE_PC: | |
36073a92 | 4620 | load_write_pc (regs, dsc, val); |
cca44b1b JB |
4621 | break; |
4622 | ||
4623 | case ALU_WRITE_PC: | |
36073a92 | 4624 | alu_write_pc (regs, dsc, val); |
cca44b1b JB |
4625 | break; |
4626 | ||
4627 | case CANNOT_WRITE_PC: | |
4628 | warning (_("Instruction wrote to PC in an unexpected way when " | |
4629 | "single-stepping")); | |
08216dd7 RE |
4630 | break; |
4631 | ||
4632 | default: | |
97b9747c JB |
4633 | internal_error (__FILE__, __LINE__, |
4634 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 4635 | } |
b508a996 | 4636 | |
cca44b1b | 4637 | dsc->wrote_to_pc = 1; |
b508a996 | 4638 | } |
ed9a39eb | 4639 | else |
b508a996 | 4640 | { |
136821d9 SM |
4641 | displaced_debug_printf ("writing r%d value %.8lx", |
4642 | regno, (unsigned long) val); | |
cca44b1b | 4643 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 4644 | } |
34e8f22d RE |
4645 | } |
4646 | ||
cca44b1b JB |
4647 | /* This function is used to concisely determine if an instruction INSN |
4648 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
4649 | corresponding fields of BITMASK set to 0b1111. The function |
4650 | returns return 1 if any of these fields in INSN reference the PC | |
4651 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
4652 | |
4653 | static int | |
cca44b1b | 4654 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 4655 | { |
cca44b1b | 4656 | uint32_t lowbit = 1; |
67255d04 | 4657 | |
cca44b1b JB |
4658 | while (bitmask != 0) |
4659 | { | |
4660 | uint32_t mask; | |
44e1a9eb | 4661 | |
cca44b1b JB |
4662 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
4663 | ; | |
67255d04 | 4664 | |
cca44b1b JB |
4665 | if (!lowbit) |
4666 | break; | |
67255d04 | 4667 | |
cca44b1b | 4668 | mask = lowbit * 0xf; |
67255d04 | 4669 | |
cca44b1b JB |
4670 | if ((insn & mask) == mask) |
4671 | return 1; | |
4672 | ||
4673 | bitmask &= ~mask; | |
67255d04 RE |
4674 | } |
4675 | ||
cca44b1b JB |
4676 | return 0; |
4677 | } | |
2af48f68 | 4678 | |
cca44b1b JB |
4679 | /* The simplest copy function. Many instructions have the same effect no |
4680 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 4681 | |
cca44b1b | 4682 | static int |
1152d984 SM |
4683 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
4684 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 4685 | { |
136821d9 SM |
4686 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
4687 | (unsigned long) insn, iname); | |
67255d04 | 4688 | |
cca44b1b | 4689 | dsc->modinsn[0] = insn; |
67255d04 | 4690 | |
cca44b1b JB |
4691 | return 0; |
4692 | } | |
4693 | ||
34518530 YQ |
4694 | static int |
4695 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
4696 | uint16_t insn2, const char *iname, | |
1152d984 | 4697 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4698 | { |
136821d9 SM |
4699 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
4700 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
4701 | |
4702 | dsc->modinsn[0] = insn1; | |
4703 | dsc->modinsn[1] = insn2; | |
4704 | dsc->numinsns = 2; | |
4705 | ||
4706 | return 0; | |
4707 | } | |
4708 | ||
4709 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
4710 | modification. */ | |
4711 | static int | |
615234c1 | 4712 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 4713 | const char *iname, |
1152d984 | 4714 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4715 | { |
136821d9 SM |
4716 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
4717 | insn, iname); | |
34518530 YQ |
4718 | |
4719 | dsc->modinsn[0] = insn; | |
4720 | ||
4721 | return 0; | |
4722 | } | |
4723 | ||
cca44b1b JB |
4724 | /* Preload instructions with immediate offset. */ |
4725 | ||
4726 | static void | |
1152d984 SM |
4727 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
4728 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
4729 | { |
4730 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4731 | if (!dsc->u.preload.immed) | |
4732 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
4733 | } | |
4734 | ||
7ff120b4 YQ |
4735 | static void |
4736 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4737 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 4738 | { |
cca44b1b | 4739 | ULONGEST rn_val; |
cca44b1b JB |
4740 | /* Preload instructions: |
4741 | ||
4742 | {pli/pld} [rn, #+/-imm] | |
4743 | -> | |
4744 | {pli/pld} [r0, #+/-imm]. */ | |
4745 | ||
36073a92 YQ |
4746 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4747 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 4748 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
4749 | dsc->u.preload.immed = 1; |
4750 | ||
cca44b1b | 4751 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
4752 | } |
4753 | ||
cca44b1b | 4754 | static int |
7ff120b4 | 4755 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 4756 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
4757 | { |
4758 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 4759 | |
7ff120b4 YQ |
4760 | if (!insn_references_pc (insn, 0x000f0000ul)) |
4761 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 4762 | |
136821d9 | 4763 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 4764 | |
7ff120b4 YQ |
4765 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4766 | ||
4767 | install_preload (gdbarch, regs, dsc, rn); | |
4768 | ||
4769 | return 0; | |
4770 | } | |
4771 | ||
34518530 YQ |
4772 | static int |
4773 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 4774 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
4775 | { |
4776 | unsigned int rn = bits (insn1, 0, 3); | |
4777 | unsigned int u_bit = bit (insn1, 7); | |
4778 | int imm12 = bits (insn2, 0, 11); | |
4779 | ULONGEST pc_val; | |
4780 | ||
4781 | if (rn != ARM_PC_REGNUM) | |
4782 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
4783 | ||
4784 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
4785 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
4786 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
4787 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
4788 | imm12); | |
34518530 YQ |
4789 | |
4790 | if (!u_bit) | |
4791 | imm12 = -1 * imm12; | |
4792 | ||
4793 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
4794 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
4795 | ||
4796 | {pli/pld} [r0, r1] | |
4797 | ||
4798 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
4799 | ||
4800 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
4801 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4802 | ||
4803 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
4804 | ||
4805 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
4806 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
4807 | dsc->u.preload.immed = 0; | |
4808 | ||
4809 | /* {pli/pld} [r0, r1] */ | |
4810 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4811 | dsc->modinsn[1] = 0xf001; | |
4812 | dsc->numinsns = 2; | |
4813 | ||
4814 | dsc->cleanup = &cleanup_preload; | |
4815 | return 0; | |
4816 | } | |
4817 | ||
7ff120b4 YQ |
4818 | /* Preload instructions with register offset. */ |
4819 | ||
4820 | static void | |
4821 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4822 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
4823 | unsigned int rm) |
4824 | { | |
4825 | ULONGEST rn_val, rm_val; | |
4826 | ||
cca44b1b JB |
4827 | /* Preload register-offset instructions: |
4828 | ||
4829 | {pli/pld} [rn, rm {, shift}] | |
4830 | -> | |
4831 | {pli/pld} [r0, r1 {, shift}]. */ | |
4832 | ||
36073a92 YQ |
4833 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4834 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
4835 | rn_val = displaced_read_reg (regs, dsc, rn); | |
4836 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
4837 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4838 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
4839 | dsc->u.preload.immed = 0; |
4840 | ||
cca44b1b | 4841 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
4842 | } |
4843 | ||
4844 | static int | |
4845 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
4846 | struct regcache *regs, | |
1152d984 | 4847 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
4848 | { |
4849 | unsigned int rn = bits (insn, 16, 19); | |
4850 | unsigned int rm = bits (insn, 0, 3); | |
4851 | ||
4852 | ||
4853 | if (!insn_references_pc (insn, 0x000f000ful)) | |
4854 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
4855 | ||
136821d9 SM |
4856 | displaced_debug_printf ("copying preload insn %.8lx", |
4857 | (unsigned long) insn); | |
7ff120b4 YQ |
4858 | |
4859 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 4860 | |
7ff120b4 | 4861 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
4862 | return 0; |
4863 | } | |
4864 | ||
4865 | /* Copy/cleanup coprocessor load and store instructions. */ | |
4866 | ||
4867 | static void | |
6e39997a | 4868 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 4869 | struct regcache *regs, |
1152d984 | 4870 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 4871 | { |
36073a92 | 4872 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
4873 | |
4874 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4875 | ||
4876 | if (dsc->u.ldst.writeback) | |
4877 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
4878 | } | |
4879 | ||
7ff120b4 YQ |
4880 | static void |
4881 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4882 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 4883 | int writeback, unsigned int rn) |
cca44b1b | 4884 | { |
cca44b1b | 4885 | ULONGEST rn_val; |
cca44b1b | 4886 | |
cca44b1b JB |
4887 | /* Coprocessor load/store instructions: |
4888 | ||
4889 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
4890 | -> | |
4891 | {stc/stc2} [r0, #+/-imm]. | |
4892 | ||
4893 | ldc/ldc2 are handled identically. */ | |
4894 | ||
36073a92 YQ |
4895 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4896 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
4897 | /* PC should be 4-byte aligned. */ |
4898 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
4899 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
4900 | ||
7ff120b4 | 4901 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
4902 | dsc->u.ldst.rn = rn; |
4903 | ||
7ff120b4 YQ |
4904 | dsc->cleanup = &cleanup_copro_load_store; |
4905 | } | |
4906 | ||
4907 | static int | |
4908 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
4909 | struct regcache *regs, | |
1152d984 | 4910 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
4911 | { |
4912 | unsigned int rn = bits (insn, 16, 19); | |
4913 | ||
4914 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
4915 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
4916 | ||
136821d9 SM |
4917 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
4918 | (unsigned long) insn); | |
7ff120b4 | 4919 | |
cca44b1b JB |
4920 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4921 | ||
7ff120b4 | 4922 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
4923 | |
4924 | return 0; | |
4925 | } | |
4926 | ||
34518530 YQ |
4927 | static int |
4928 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
4929 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 4930 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
4931 | { |
4932 | unsigned int rn = bits (insn1, 0, 3); | |
4933 | ||
4934 | if (rn != ARM_PC_REGNUM) | |
4935 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
4936 | "copro load/store", dsc); | |
4937 | ||
136821d9 SM |
4938 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
4939 | insn1, insn2); | |
34518530 YQ |
4940 | |
4941 | dsc->modinsn[0] = insn1 & 0xfff0; | |
4942 | dsc->modinsn[1] = insn2; | |
4943 | dsc->numinsns = 2; | |
4944 | ||
4945 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
4946 | doesn't support writeback, so pass 0. */ | |
4947 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
4948 | ||
4949 | return 0; | |
4950 | } | |
4951 | ||
cca44b1b JB |
4952 | /* Clean up branch instructions (actually perform the branch, by setting |
4953 | PC). */ | |
4954 | ||
4955 | static void | |
6e39997a | 4956 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 4957 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 4958 | { |
36073a92 | 4959 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
4960 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
4961 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
4962 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
4963 | ||
4964 | if (!branch_taken) | |
4965 | return; | |
4966 | ||
4967 | if (dsc->u.branch.link) | |
4968 | { | |
8c8dba6d | 4969 | /* The value of LR should be the next insn of current one. In order |
85102364 | 4970 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
4971 | is Thumb, the bit 0 of LR value should be set to 1. */ |
4972 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
4973 | ||
4974 | if (dsc->is_thumb) | |
4975 | next_insn_addr |= 0x1; | |
4976 | ||
4977 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
4978 | CANNOT_WRITE_PC); | |
cca44b1b JB |
4979 | } |
4980 | ||
bf9f652a | 4981 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
4982 | } |
4983 | ||
4984 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
4985 | ||
7ff120b4 YQ |
4986 | static void |
4987 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4988 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
4989 | unsigned int cond, int exchange, int link, long offset) |
4990 | { | |
4991 | /* Implement "BL<cond> <label>" as: | |
4992 | ||
4993 | Preparation: cond <- instruction condition | |
4994 | Insn: mov r0, r0 (nop) | |
4995 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
4996 | ||
4997 | B<cond> similar, but don't set r14 in cleanup. */ | |
4998 | ||
4999 | dsc->u.branch.cond = cond; | |
5000 | dsc->u.branch.link = link; | |
5001 | dsc->u.branch.exchange = exchange; | |
5002 | ||
2b16b2e3 YQ |
5003 | dsc->u.branch.dest = dsc->insn_addr; |
5004 | if (link && exchange) | |
5005 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5006 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5007 | ||
7ff120b4 | 5008 | if (dsc->is_thumb) |
2b16b2e3 | 5009 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5010 | else |
2b16b2e3 | 5011 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5012 | |
5013 | dsc->cleanup = &cleanup_branch; | |
5014 | } | |
cca44b1b | 5015 | static int |
7ff120b4 | 5016 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5017 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5018 | { |
5019 | unsigned int cond = bits (insn, 28, 31); | |
5020 | int exchange = (cond == 0xf); | |
5021 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5022 | long offset; |
5023 | ||
136821d9 SM |
5024 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5025 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5026 | (unsigned long) insn); | |
cca44b1b JB |
5027 | if (exchange) |
5028 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5029 | then arrange the switch into Thumb mode. */ | |
5030 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5031 | else | |
5032 | offset = bits (insn, 0, 23) << 2; | |
5033 | ||
5034 | if (bit (offset, 25)) | |
5035 | offset = offset | ~0x3ffffff; | |
5036 | ||
cca44b1b JB |
5037 | dsc->modinsn[0] = ARM_NOP; |
5038 | ||
7ff120b4 | 5039 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5040 | return 0; |
5041 | } | |
5042 | ||
34518530 YQ |
5043 | static int |
5044 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5045 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5046 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5047 | { |
5048 | int link = bit (insn2, 14); | |
5049 | int exchange = link && !bit (insn2, 12); | |
5050 | int cond = INST_AL; | |
5051 | long offset = 0; | |
5052 | int j1 = bit (insn2, 13); | |
5053 | int j2 = bit (insn2, 11); | |
5054 | int s = sbits (insn1, 10, 10); | |
5055 | int i1 = !(j1 ^ bit (insn1, 10)); | |
5056 | int i2 = !(j2 ^ bit (insn1, 10)); | |
5057 | ||
5058 | if (!link && !exchange) /* B */ | |
5059 | { | |
5060 | offset = (bits (insn2, 0, 10) << 1); | |
5061 | if (bit (insn2, 12)) /* Encoding T4 */ | |
5062 | { | |
5063 | offset |= (bits (insn1, 0, 9) << 12) | |
5064 | | (i2 << 22) | |
5065 | | (i1 << 23) | |
5066 | | (s << 24); | |
5067 | cond = INST_AL; | |
5068 | } | |
5069 | else /* Encoding T3 */ | |
5070 | { | |
5071 | offset |= (bits (insn1, 0, 5) << 12) | |
5072 | | (j1 << 18) | |
5073 | | (j2 << 19) | |
5074 | | (s << 20); | |
5075 | cond = bits (insn1, 6, 9); | |
5076 | } | |
5077 | } | |
5078 | else | |
5079 | { | |
5080 | offset = (bits (insn1, 0, 9) << 12); | |
5081 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
5082 | offset |= exchange ? | |
5083 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
5084 | } | |
5085 | ||
136821d9 SM |
5086 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
5087 | link ? (exchange) ? "blx" : "bl" : "b", | |
5088 | insn1, insn2, offset); | |
34518530 YQ |
5089 | |
5090 | dsc->modinsn[0] = THUMB_NOP; | |
5091 | ||
5092 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
5093 | return 0; | |
5094 | } | |
5095 | ||
5096 | /* Copy B Thumb instructions. */ | |
5097 | static int | |
615234c1 | 5098 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 5099 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5100 | { |
5101 | unsigned int cond = 0; | |
5102 | int offset = 0; | |
5103 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
5104 | CORE_ADDR from = dsc->insn_addr; | |
5105 | ||
5106 | if (bit_12_15 == 0xd) | |
5107 | { | |
5108 | /* offset = SignExtend (imm8:0, 32) */ | |
5109 | offset = sbits ((insn << 1), 0, 8); | |
5110 | cond = bits (insn, 8, 11); | |
5111 | } | |
5112 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
5113 | { | |
5114 | offset = sbits ((insn << 1), 0, 11); | |
5115 | cond = INST_AL; | |
5116 | } | |
5117 | ||
136821d9 SM |
5118 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
5119 | insn, offset); | |
34518530 YQ |
5120 | |
5121 | dsc->u.branch.cond = cond; | |
5122 | dsc->u.branch.link = 0; | |
5123 | dsc->u.branch.exchange = 0; | |
5124 | dsc->u.branch.dest = from + 4 + offset; | |
5125 | ||
5126 | dsc->modinsn[0] = THUMB_NOP; | |
5127 | ||
5128 | dsc->cleanup = &cleanup_branch; | |
5129 | ||
5130 | return 0; | |
5131 | } | |
5132 | ||
cca44b1b JB |
5133 | /* Copy BX/BLX with register-specified destinations. */ |
5134 | ||
7ff120b4 YQ |
5135 | static void |
5136 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5137 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 5138 | unsigned int cond, unsigned int rm) |
cca44b1b | 5139 | { |
cca44b1b JB |
5140 | /* Implement {BX,BLX}<cond> <reg>" as: |
5141 | ||
5142 | Preparation: cond <- instruction condition | |
5143 | Insn: mov r0, r0 (nop) | |
5144 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5145 | ||
5146 | Don't set r14 in cleanup for BX. */ | |
5147 | ||
36073a92 | 5148 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5149 | |
5150 | dsc->u.branch.cond = cond; | |
5151 | dsc->u.branch.link = link; | |
cca44b1b | 5152 | |
7ff120b4 | 5153 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
5154 | |
5155 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 5156 | } |
cca44b1b | 5157 | |
7ff120b4 YQ |
5158 | static int |
5159 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 5160 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5161 | { |
5162 | unsigned int cond = bits (insn, 28, 31); | |
5163 | /* BX: x12xxx1x | |
5164 | BLX: x12xxx3x. */ | |
5165 | int link = bit (insn, 5); | |
5166 | unsigned int rm = bits (insn, 0, 3); | |
5167 | ||
136821d9 | 5168 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
5169 | |
5170 | dsc->modinsn[0] = ARM_NOP; | |
5171 | ||
5172 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
5173 | return 0; |
5174 | } | |
5175 | ||
34518530 YQ |
5176 | static int |
5177 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5178 | struct regcache *regs, | |
1152d984 | 5179 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5180 | { |
5181 | int link = bit (insn, 7); | |
5182 | unsigned int rm = bits (insn, 3, 6); | |
5183 | ||
136821d9 | 5184 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
5185 | |
5186 | dsc->modinsn[0] = THUMB_NOP; | |
5187 | ||
5188 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
5189 | ||
5190 | return 0; | |
5191 | } | |
5192 | ||
5193 | ||
0963b4bd | 5194 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
5195 | |
5196 | static void | |
6e39997a | 5197 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 5198 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5199 | { |
36073a92 | 5200 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5201 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
5202 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5203 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5204 | } | |
5205 | ||
5206 | static int | |
7ff120b4 | 5207 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5208 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5209 | { |
5210 | unsigned int rn = bits (insn, 16, 19); | |
5211 | unsigned int rd = bits (insn, 12, 15); | |
5212 | unsigned int op = bits (insn, 21, 24); | |
5213 | int is_mov = (op == 0xd); | |
5214 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
5215 | |
5216 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 5217 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 5218 | |
136821d9 SM |
5219 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
5220 | is_mov ? "move" : "ALU", | |
5221 | (unsigned long) insn); | |
cca44b1b JB |
5222 | |
5223 | /* Instruction is of form: | |
5224 | ||
5225 | <op><cond> rd, [rn,] #imm | |
5226 | ||
5227 | Rewrite as: | |
5228 | ||
5229 | Preparation: tmp1, tmp2 <- r0, r1; | |
5230 | r0, r1 <- rd, rn | |
5231 | Insn: <op><cond> r0, r1, #imm | |
5232 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5233 | */ | |
5234 | ||
36073a92 YQ |
5235 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5236 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5237 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5238 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
5239 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5240 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5241 | dsc->rd = rd; | |
5242 | ||
5243 | if (is_mov) | |
5244 | dsc->modinsn[0] = insn & 0xfff00fff; | |
5245 | else | |
5246 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
5247 | ||
5248 | dsc->cleanup = &cleanup_alu_imm; | |
5249 | ||
5250 | return 0; | |
5251 | } | |
5252 | ||
34518530 YQ |
5253 | static int |
5254 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5255 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5256 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5257 | { |
5258 | unsigned int op = bits (insn1, 5, 8); | |
5259 | unsigned int rn, rm, rd; | |
5260 | ULONGEST rd_val, rn_val; | |
5261 | ||
5262 | rn = bits (insn1, 0, 3); /* Rn */ | |
5263 | rm = bits (insn2, 0, 3); /* Rm */ | |
5264 | rd = bits (insn2, 8, 11); /* Rd */ | |
5265 | ||
5266 | /* This routine is only called for instruction MOV. */ | |
5267 | gdb_assert (op == 0x2 && rn == 0xf); | |
5268 | ||
5269 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
5270 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
5271 | ||
136821d9 | 5272 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
5273 | |
5274 | /* Instruction is of form: | |
5275 | ||
5276 | <op><cond> rd, [rn,] #imm | |
5277 | ||
5278 | Rewrite as: | |
5279 | ||
5280 | Preparation: tmp1, tmp2 <- r0, r1; | |
5281 | r0, r1 <- rd, rn | |
5282 | Insn: <op><cond> r0, r1, #imm | |
5283 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5284 | */ | |
5285 | ||
5286 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5287 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5288 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5289 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5290 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
5291 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5292 | dsc->rd = rd; | |
5293 | ||
5294 | dsc->modinsn[0] = insn1; | |
5295 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
5296 | dsc->numinsns = 2; | |
5297 | ||
5298 | dsc->cleanup = &cleanup_alu_imm; | |
5299 | ||
5300 | return 0; | |
5301 | } | |
5302 | ||
cca44b1b JB |
5303 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
5304 | ||
5305 | static void | |
6e39997a | 5306 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 5307 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5308 | { |
5309 | ULONGEST rd_val; | |
5310 | int i; | |
5311 | ||
36073a92 | 5312 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5313 | |
5314 | for (i = 0; i < 3; i++) | |
5315 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5316 | ||
5317 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5318 | } | |
5319 | ||
7ff120b4 YQ |
5320 | static void |
5321 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5322 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5323 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 5324 | { |
cca44b1b | 5325 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 5326 | |
cca44b1b JB |
5327 | /* Instruction is of form: |
5328 | ||
5329 | <op><cond> rd, [rn,] rm [, <shift>] | |
5330 | ||
5331 | Rewrite as: | |
5332 | ||
5333 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
5334 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 5335 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
5336 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
5337 | */ | |
5338 | ||
36073a92 YQ |
5339 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5340 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5341 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5342 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5343 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5344 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5345 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5346 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5347 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5348 | dsc->rd = rd; | |
5349 | ||
7ff120b4 YQ |
5350 | dsc->cleanup = &cleanup_alu_reg; |
5351 | } | |
5352 | ||
5353 | static int | |
5354 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 5355 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5356 | { |
5357 | unsigned int op = bits (insn, 21, 24); | |
5358 | int is_mov = (op == 0xd); | |
5359 | ||
5360 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5361 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
5362 | ||
136821d9 SM |
5363 | displaced_debug_printf ("copying reg %s insn %.8lx", |
5364 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 5365 | |
cca44b1b JB |
5366 | if (is_mov) |
5367 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
5368 | else | |
5369 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
5370 | ||
7ff120b4 YQ |
5371 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
5372 | bits (insn, 0, 3)); | |
cca44b1b JB |
5373 | return 0; |
5374 | } | |
5375 | ||
34518530 YQ |
5376 | static int |
5377 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5378 | struct regcache *regs, | |
1152d984 | 5379 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5380 | { |
ef713951 | 5381 | unsigned rm, rd; |
34518530 | 5382 | |
ef713951 YQ |
5383 | rm = bits (insn, 3, 6); |
5384 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 5385 | |
ef713951 | 5386 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
5387 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
5388 | ||
136821d9 | 5389 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 5390 | |
ef713951 | 5391 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 5392 | |
ef713951 | 5393 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
5394 | |
5395 | return 0; | |
5396 | } | |
5397 | ||
cca44b1b JB |
5398 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
5399 | ||
5400 | static void | |
6e39997a | 5401 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 5402 | struct regcache *regs, |
1152d984 | 5403 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5404 | { |
36073a92 | 5405 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5406 | int i; |
5407 | ||
5408 | for (i = 0; i < 4; i++) | |
5409 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5410 | ||
5411 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5412 | } | |
5413 | ||
7ff120b4 YQ |
5414 | static void |
5415 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5416 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5417 | unsigned int rd, unsigned int rn, unsigned int rm, |
5418 | unsigned rs) | |
cca44b1b | 5419 | { |
7ff120b4 | 5420 | int i; |
cca44b1b | 5421 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 5422 | |
cca44b1b JB |
5423 | /* Instruction is of form: |
5424 | ||
5425 | <op><cond> rd, [rn,] rm, <shift> rs | |
5426 | ||
5427 | Rewrite as: | |
5428 | ||
5429 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
5430 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
5431 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
5432 | Cleanup: tmp5 <- r0 | |
5433 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
5434 | rd <- tmp5 | |
5435 | */ | |
5436 | ||
5437 | for (i = 0; i < 4; i++) | |
36073a92 | 5438 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 5439 | |
36073a92 YQ |
5440 | rd_val = displaced_read_reg (regs, dsc, rd); |
5441 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5442 | rm_val = displaced_read_reg (regs, dsc, rm); | |
5443 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
5444 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5445 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5446 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5447 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
5448 | dsc->rd = rd; | |
7ff120b4 YQ |
5449 | dsc->cleanup = &cleanup_alu_shifted_reg; |
5450 | } | |
5451 | ||
5452 | static int | |
5453 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5454 | struct regcache *regs, | |
1152d984 | 5455 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5456 | { |
5457 | unsigned int op = bits (insn, 21, 24); | |
5458 | int is_mov = (op == 0xd); | |
5459 | unsigned int rd, rn, rm, rs; | |
5460 | ||
5461 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
5462 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
5463 | ||
136821d9 SM |
5464 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
5465 | is_mov ? "move" : "ALU", | |
5466 | (unsigned long) insn); | |
7ff120b4 YQ |
5467 | |
5468 | rn = bits (insn, 16, 19); | |
5469 | rm = bits (insn, 0, 3); | |
5470 | rs = bits (insn, 8, 11); | |
5471 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
5472 | |
5473 | if (is_mov) | |
5474 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
5475 | else | |
5476 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
5477 | ||
7ff120b4 | 5478 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
5479 | |
5480 | return 0; | |
5481 | } | |
5482 | ||
5483 | /* Clean up load instructions. */ | |
5484 | ||
5485 | static void | |
6e39997a | 5486 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5487 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5488 | { |
5489 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 5490 | |
36073a92 | 5491 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 5492 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
5493 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
5494 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
5495 | |
5496 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5497 | if (dsc->u.ldst.xfersize > 4) | |
5498 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5499 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5500 | if (!dsc->u.ldst.immed) | |
5501 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5502 | ||
5503 | /* Handle register writeback. */ | |
5504 | if (dsc->u.ldst.writeback) | |
5505 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5506 | /* Put result in right place. */ | |
5507 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
5508 | if (dsc->u.ldst.xfersize == 8) | |
5509 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
5510 | } | |
5511 | ||
5512 | /* Clean up store instructions. */ | |
5513 | ||
5514 | static void | |
6e39997a | 5515 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5516 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5517 | { |
36073a92 | 5518 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
5519 | |
5520 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5521 | if (dsc->u.ldst.xfersize > 4) | |
5522 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5523 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5524 | if (!dsc->u.ldst.immed) | |
5525 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5526 | if (!dsc->u.ldst.restore_r4) | |
5527 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
5528 | ||
5529 | /* Writeback. */ | |
5530 | if (dsc->u.ldst.writeback) | |
5531 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5532 | } | |
5533 | ||
5534 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
5535 | transfers, which have a different encoding to byte/word transfers. */ | |
5536 | ||
5537 | static int | |
550dc4e2 | 5538 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 5539 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5540 | { |
5541 | unsigned int op1 = bits (insn, 20, 24); | |
5542 | unsigned int op2 = bits (insn, 5, 6); | |
5543 | unsigned int rt = bits (insn, 12, 15); | |
5544 | unsigned int rn = bits (insn, 16, 19); | |
5545 | unsigned int rm = bits (insn, 0, 3); | |
5546 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
5547 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
5548 | int immed = (op1 & 0x4) != 0; | |
5549 | int opcode; | |
5550 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
5551 | |
5552 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 5553 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 5554 | |
136821d9 SM |
5555 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
5556 | unprivileged ? "unprivileged " : "", | |
5557 | (unsigned long) insn); | |
cca44b1b JB |
5558 | |
5559 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
5560 | ||
5561 | if (opcode < 0) | |
5562 | internal_error (__FILE__, __LINE__, | |
5563 | _("copy_extra_ld_st: instruction decode error")); | |
5564 | ||
36073a92 YQ |
5565 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5566 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5567 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5568 | if (!immed) |
36073a92 | 5569 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5570 | |
36073a92 | 5571 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 5572 | if (bytesize[opcode] == 8) |
36073a92 YQ |
5573 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
5574 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5575 | if (!immed) |
36073a92 | 5576 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5577 | |
5578 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5579 | if (bytesize[opcode] == 8) | |
5580 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
5581 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5582 | if (!immed) | |
5583 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
5584 | ||
5585 | dsc->rd = rt; | |
5586 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
5587 | dsc->u.ldst.rn = rn; | |
5588 | dsc->u.ldst.immed = immed; | |
5589 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
5590 | dsc->u.ldst.restore_r4 = 0; | |
5591 | ||
5592 | if (immed) | |
5593 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
5594 | -> | |
5595 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
5596 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5597 | else | |
5598 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
5599 | -> | |
5600 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
5601 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5602 | ||
5603 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
5604 | ||
5605 | return 0; | |
5606 | } | |
5607 | ||
0f6f04ba | 5608 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 5609 | |
7ff120b4 | 5610 | static void |
0f6f04ba | 5611 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5612 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
5613 | int immed, int writeback, int size, int usermode, |
5614 | int rt, int rm, int rn) | |
cca44b1b | 5615 | { |
cca44b1b | 5616 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 5617 | |
36073a92 YQ |
5618 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5619 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5620 | if (!immed) |
36073a92 | 5621 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5622 | if (!load) |
36073a92 | 5623 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 5624 | |
36073a92 YQ |
5625 | rt_val = displaced_read_reg (regs, dsc, rt); |
5626 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5627 | if (!immed) |
36073a92 | 5628 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5629 | |
5630 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5631 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5632 | if (!immed) | |
5633 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 5634 | dsc->rd = rt; |
0f6f04ba | 5635 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
5636 | dsc->u.ldst.rn = rn; |
5637 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 5638 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5639 | |
5640 | /* To write PC we can do: | |
5641 | ||
494e194e YQ |
5642 | Before this sequence of instructions: |
5643 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 5644 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
5645 | |
5646 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
5647 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
5648 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
5649 | = addr(Insn1) + offset - addr(Insn3) - 8 |
5650 | = offset - 16 | |
494e194e YQ |
5651 | Insn4: add r4, r4, #8 r4 = offset - 8 |
5652 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 5653 | = from + offset |
494e194e | 5654 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
5655 | |
5656 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
5657 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
5658 | of this can be found in Section "Saving from r15" in | |
5659 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 5660 | |
7ff120b4 YQ |
5661 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
5662 | } | |
5663 | ||
34518530 YQ |
5664 | |
5665 | static int | |
5666 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
5667 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5668 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
5669 | { |
5670 | unsigned int u_bit = bit (insn1, 7); | |
5671 | unsigned int rt = bits (insn2, 12, 15); | |
5672 | int imm12 = bits (insn2, 0, 11); | |
5673 | ULONGEST pc_val; | |
5674 | ||
136821d9 SM |
5675 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
5676 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
5677 | imm12); | |
34518530 YQ |
5678 | |
5679 | if (!u_bit) | |
5680 | imm12 = -1 * imm12; | |
5681 | ||
5682 | /* Rewrite instruction LDR Rt imm12 into: | |
5683 | ||
5684 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
5685 | ||
5686 | LDR R0, R2, R3, | |
5687 | ||
5688 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
5689 | ||
5690 | ||
5691 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5692 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5693 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
5694 | ||
5695 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5696 | ||
5697 | pc_val = pc_val & 0xfffffffc; | |
5698 | ||
5699 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
5700 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
5701 | ||
5702 | dsc->rd = rt; | |
5703 | ||
5704 | dsc->u.ldst.xfersize = size; | |
5705 | dsc->u.ldst.immed = 0; | |
5706 | dsc->u.ldst.writeback = 0; | |
5707 | dsc->u.ldst.restore_r4 = 0; | |
5708 | ||
5709 | /* LDR R0, R2, R3 */ | |
5710 | dsc->modinsn[0] = 0xf852; | |
5711 | dsc->modinsn[1] = 0x3; | |
5712 | dsc->numinsns = 2; | |
5713 | ||
5714 | dsc->cleanup = &cleanup_load; | |
5715 | ||
5716 | return 0; | |
5717 | } | |
5718 | ||
5719 | static int | |
5720 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5721 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5722 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
5723 | int writeback, int immed) |
5724 | { | |
5725 | unsigned int rt = bits (insn2, 12, 15); | |
5726 | unsigned int rn = bits (insn1, 0, 3); | |
5727 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
5728 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
5729 | be PC, so we don't have to check it. */ | |
5730 | ||
5731 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
5732 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
5733 | dsc); | |
5734 | ||
136821d9 SM |
5735 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
5736 | rt, rn, insn1, insn2); | |
34518530 YQ |
5737 | |
5738 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
5739 | 0, rt, rm, rn); | |
5740 | ||
5741 | dsc->u.ldst.restore_r4 = 0; | |
5742 | ||
5743 | if (immed) | |
5744 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
5745 | -> | |
5746 | ldr[b]<cond> r0, [r2, #imm]. */ | |
5747 | { | |
5748 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5749 | dsc->modinsn[1] = insn2 & 0x0fff; | |
5750 | } | |
5751 | else | |
5752 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
5753 | -> | |
5754 | ldr[b]<cond> r0, [r2, r3]. */ | |
5755 | { | |
5756 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5757 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
5758 | } | |
5759 | ||
5760 | dsc->numinsns = 2; | |
5761 | ||
5762 | return 0; | |
5763 | } | |
5764 | ||
5765 | ||
7ff120b4 YQ |
5766 | static int |
5767 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
5768 | struct regcache *regs, | |
1152d984 | 5769 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 5770 | int load, int size, int usermode) |
7ff120b4 YQ |
5771 | { |
5772 | int immed = !bit (insn, 25); | |
5773 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
5774 | unsigned int rt = bits (insn, 12, 15); | |
5775 | unsigned int rn = bits (insn, 16, 19); | |
5776 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
5777 | ||
5778 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5779 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
5780 | ||
136821d9 SM |
5781 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
5782 | load ? (size == 1 ? "ldrb" : "ldr") | |
5783 | : (size == 1 ? "strb" : "str"), | |
5784 | usermode ? "t" : "", | |
5785 | rt, rn, | |
5786 | (unsigned long) insn); | |
7ff120b4 | 5787 | |
0f6f04ba YQ |
5788 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
5789 | usermode, rt, rm, rn); | |
7ff120b4 | 5790 | |
bf9f652a | 5791 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
5792 | { |
5793 | dsc->u.ldst.restore_r4 = 0; | |
5794 | ||
5795 | if (immed) | |
5796 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
5797 | -> | |
5798 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
5799 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5800 | else | |
5801 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
5802 | -> | |
5803 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
5804 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5805 | } | |
5806 | else | |
5807 | { | |
5808 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
5809 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
5810 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
5811 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
5812 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
5813 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
5814 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
5815 | ||
5816 | /* As above. */ | |
5817 | if (immed) | |
5818 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
5819 | else | |
5820 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
5821 | ||
cca44b1b JB |
5822 | dsc->numinsns = 6; |
5823 | } | |
5824 | ||
5825 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
5826 | ||
5827 | return 0; | |
5828 | } | |
5829 | ||
5830 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
5831 | unfortunate corner case: it's impossible to implement correctly by modifying | |
5832 | the instruction. The issue is as follows: we have an instruction, | |
5833 | ||
5834 | ldm rN, {r0-r15} | |
5835 | ||
5836 | which we must rewrite to avoid loading PC. A possible solution would be to | |
5837 | do the load in two halves, something like (with suitable cleanup | |
5838 | afterwards): | |
5839 | ||
5840 | mov r8, rN | |
5841 | ldm[id][ab] r8!, {r0-r7} | |
5842 | str r7, <temp> | |
5843 | ldm[id][ab] r8, {r7-r14} | |
5844 | <bkpt> | |
5845 | ||
5846 | but at present there's no suitable place for <temp>, since the scratch space | |
5847 | is overwritten before the cleanup routine is called. For now, we simply | |
5848 | emulate the instruction. */ | |
5849 | ||
5850 | static void | |
5851 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5852 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5853 | { |
cca44b1b JB |
5854 | int inc = dsc->u.block.increment; |
5855 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
5856 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
5857 | uint32_t regmask = dsc->u.block.regmask; | |
5858 | int regno = inc ? 0 : 15; | |
5859 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
5860 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
5861 | && (regmask & 0x8000) != 0; | |
36073a92 | 5862 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5863 | int do_transfer = condition_true (dsc->u.block.cond, status); |
5864 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5865 | ||
5866 | if (!do_transfer) | |
5867 | return; | |
5868 | ||
5869 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
5870 | sensible we can do here. Complain loudly. */ | |
5871 | if (exception_return) | |
5872 | error (_("Cannot single-step exception return")); | |
5873 | ||
5874 | /* We don't handle any stores here for now. */ | |
5875 | gdb_assert (dsc->u.block.load != 0); | |
5876 | ||
136821d9 SM |
5877 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
5878 | dsc->u.block.load ? "ldm" : "stm", | |
5879 | dsc->u.block.increment ? "inc" : "dec", | |
5880 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
5881 | |
5882 | while (regmask) | |
5883 | { | |
5884 | uint32_t memword; | |
5885 | ||
5886 | if (inc) | |
bf9f652a | 5887 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
5888 | regno++; |
5889 | else | |
5890 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
5891 | regno--; | |
5892 | ||
5893 | xfer_addr += bump_before; | |
5894 | ||
5895 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
5896 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
5897 | ||
5898 | xfer_addr += bump_after; | |
5899 | ||
5900 | regmask &= ~(1 << regno); | |
5901 | } | |
5902 | ||
5903 | if (dsc->u.block.writeback) | |
5904 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
5905 | CANNOT_WRITE_PC); | |
5906 | } | |
5907 | ||
5908 | /* Clean up an STM which included the PC in the register list. */ | |
5909 | ||
5910 | static void | |
5911 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5912 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5913 | { |
36073a92 | 5914 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 5915 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
5916 | CORE_ADDR pc_stored_at, transferred_regs |
5917 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
5918 | CORE_ADDR stm_insn_addr; |
5919 | uint32_t pc_val; | |
5920 | long offset; | |
5921 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5922 | ||
5923 | /* If condition code fails, there's nothing else to do. */ | |
5924 | if (!store_executed) | |
5925 | return; | |
5926 | ||
5927 | if (dsc->u.block.increment) | |
5928 | { | |
5929 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
5930 | ||
5931 | if (dsc->u.block.before) | |
5932 | pc_stored_at += 4; | |
5933 | } | |
5934 | else | |
5935 | { | |
5936 | pc_stored_at = dsc->u.block.xfer_addr; | |
5937 | ||
5938 | if (dsc->u.block.before) | |
5939 | pc_stored_at -= 4; | |
5940 | } | |
5941 | ||
5942 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
5943 | stm_insn_addr = dsc->scratch_base; | |
5944 | offset = pc_val - stm_insn_addr; | |
5945 | ||
136821d9 SM |
5946 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
5947 | offset); | |
cca44b1b JB |
5948 | |
5949 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
5950 | instruction. */ | |
5951 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
5952 | dsc->insn_addr + offset); | |
5953 | } | |
5954 | ||
5955 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
5956 | the registers in the transferred list into a contiguous range r0...rX (to | |
5957 | avoid loading PC directly and losing control of the debugged program), so we | |
5958 | must undo that here. */ | |
5959 | ||
5960 | static void | |
6e39997a | 5961 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 5962 | struct regcache *regs, |
1152d984 | 5963 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5964 | { |
36073a92 | 5965 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 5966 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 5967 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 5968 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
5969 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
5970 | ||
5971 | /* The method employed here will fail if the register list is fully populated | |
5972 | (we need to avoid loading PC directly). */ | |
5973 | gdb_assert (num_to_shuffle < 16); | |
5974 | ||
5975 | if (!load_executed) | |
5976 | return; | |
5977 | ||
5978 | clobbered = (1 << num_to_shuffle) - 1; | |
5979 | ||
5980 | while (num_to_shuffle > 0) | |
5981 | { | |
5982 | if ((mask & (1 << write_reg)) != 0) | |
5983 | { | |
5984 | unsigned int read_reg = num_to_shuffle - 1; | |
5985 | ||
5986 | if (read_reg != write_reg) | |
5987 | { | |
36073a92 | 5988 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 5989 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
5990 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
5991 | read_reg, write_reg); | |
cca44b1b | 5992 | } |
136821d9 SM |
5993 | else |
5994 | displaced_debug_printf ("LDM: register r%d already in the right " | |
5995 | "place", write_reg); | |
cca44b1b JB |
5996 | |
5997 | clobbered &= ~(1 << write_reg); | |
5998 | ||
5999 | num_to_shuffle--; | |
6000 | } | |
6001 | ||
6002 | write_reg--; | |
6003 | } | |
6004 | ||
6005 | /* Restore any registers we scribbled over. */ | |
6006 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6007 | { | |
6008 | if ((clobbered & (1 << write_reg)) != 0) | |
6009 | { | |
6010 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6011 | CANNOT_WRITE_PC); | |
136821d9 SM |
6012 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6013 | write_reg); | |
cca44b1b JB |
6014 | clobbered &= ~(1 << write_reg); |
6015 | } | |
6016 | } | |
6017 | ||
6018 | /* Perform register writeback manually. */ | |
6019 | if (dsc->u.block.writeback) | |
6020 | { | |
6021 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6022 | ||
6023 | if (dsc->u.block.increment) | |
6024 | new_rn_val += regs_loaded * 4; | |
6025 | else | |
6026 | new_rn_val -= regs_loaded * 4; | |
6027 | ||
6028 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6029 | CANNOT_WRITE_PC); | |
6030 | } | |
6031 | } | |
6032 | ||
6033 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6034 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6035 | ||
6036 | static int | |
7ff120b4 YQ |
6037 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6038 | struct regcache *regs, | |
1152d984 | 6039 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6040 | { |
6041 | int load = bit (insn, 20); | |
6042 | int user = bit (insn, 22); | |
6043 | int increment = bit (insn, 23); | |
6044 | int before = bit (insn, 24); | |
6045 | int writeback = bit (insn, 21); | |
6046 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6047 | |
0963b4bd MS |
6048 | /* Block transfers which don't mention PC can be run directly |
6049 | out-of-line. */ | |
bf9f652a | 6050 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 6051 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 6052 | |
bf9f652a | 6053 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 6054 | { |
0963b4bd MS |
6055 | warning (_("displaced: Unpredictable LDM or STM with " |
6056 | "base register r15")); | |
7ff120b4 | 6057 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
6058 | } |
6059 | ||
136821d9 SM |
6060 | displaced_debug_printf ("copying block transfer insn %.8lx", |
6061 | (unsigned long) insn); | |
cca44b1b | 6062 | |
36073a92 | 6063 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
6064 | dsc->u.block.rn = rn; |
6065 | ||
6066 | dsc->u.block.load = load; | |
6067 | dsc->u.block.user = user; | |
6068 | dsc->u.block.increment = increment; | |
6069 | dsc->u.block.before = before; | |
6070 | dsc->u.block.writeback = writeback; | |
6071 | dsc->u.block.cond = bits (insn, 28, 31); | |
6072 | ||
6073 | dsc->u.block.regmask = insn & 0xffff; | |
6074 | ||
6075 | if (load) | |
6076 | { | |
6077 | if ((insn & 0xffff) == 0xffff) | |
6078 | { | |
6079 | /* LDM with a fully-populated register list. This case is | |
6080 | particularly tricky. Implement for now by fully emulating the | |
6081 | instruction (which might not behave perfectly in all cases, but | |
6082 | these instructions should be rare enough for that not to matter | |
6083 | too much). */ | |
6084 | dsc->modinsn[0] = ARM_NOP; | |
6085 | ||
6086 | dsc->cleanup = &cleanup_block_load_all; | |
6087 | } | |
6088 | else | |
6089 | { | |
6090 | /* LDM of a list of registers which includes PC. Implement by | |
6091 | rewriting the list of registers to be transferred into a | |
6092 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
6093 | registers into the correct places in the cleanup routine. */ | |
6094 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 6095 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6096 | unsigned int i; |
cca44b1b JB |
6097 | |
6098 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 6099 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
6100 | |
6101 | /* Writeback makes things complicated. We need to avoid clobbering | |
6102 | the base register with one of the registers in our modified | |
6103 | register list, but just using a different register can't work in | |
6104 | all cases, e.g.: | |
6105 | ||
6106 | ldm r14!, {r0-r13,pc} | |
6107 | ||
6108 | which would need to be rewritten as: | |
6109 | ||
6110 | ldm rN!, {r0-r14} | |
6111 | ||
6112 | but that can't work, because there's no free register for N. | |
6113 | ||
6114 | Solve this by turning off the writeback bit, and emulating | |
6115 | writeback manually in the cleanup routine. */ | |
6116 | ||
6117 | if (writeback) | |
6118 | insn &= ~(1 << 21); | |
6119 | ||
6120 | new_regmask = (1 << num_in_list) - 1; | |
6121 | ||
136821d9 SM |
6122 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6123 | "%.4x, modified list %.4x", | |
6124 | rn, writeback ? "!" : "", | |
6125 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
6126 | |
6127 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6128 | ||
6129 | dsc->cleanup = &cleanup_block_load_pc; | |
6130 | } | |
6131 | } | |
6132 | else | |
6133 | { | |
6134 | /* STM of a list of registers which includes PC. Run the instruction | |
6135 | as-is, but out of line: this will store the wrong value for the PC, | |
6136 | so we must manually fix up the memory in the cleanup routine. | |
6137 | Doing things this way has the advantage that we can auto-detect | |
6138 | the offset of the PC write (which is architecture-dependent) in | |
6139 | the cleanup routine. */ | |
6140 | dsc->modinsn[0] = insn; | |
6141 | ||
6142 | dsc->cleanup = &cleanup_block_store_pc; | |
6143 | } | |
6144 | ||
6145 | return 0; | |
6146 | } | |
6147 | ||
34518530 YQ |
6148 | static int |
6149 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6150 | struct regcache *regs, | |
1152d984 | 6151 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6152 | { |
34518530 YQ |
6153 | int rn = bits (insn1, 0, 3); |
6154 | int load = bit (insn1, 4); | |
6155 | int writeback = bit (insn1, 5); | |
cca44b1b | 6156 | |
34518530 YQ |
6157 | /* Block transfers which don't mention PC can be run directly |
6158 | out-of-line. */ | |
6159 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
6160 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 6161 | |
34518530 YQ |
6162 | if (rn == ARM_PC_REGNUM) |
6163 | { | |
6164 | warning (_("displaced: Unpredictable LDM or STM with " | |
6165 | "base register r15")); | |
6166 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6167 | "unpredictable ldm/stm", dsc); | |
6168 | } | |
cca44b1b | 6169 | |
136821d9 SM |
6170 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
6171 | insn1, insn2); | |
cca44b1b | 6172 | |
34518530 YQ |
6173 | /* Clear bit 13, since it should be always zero. */ |
6174 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
6175 | dsc->u.block.rn = rn; | |
cca44b1b | 6176 | |
34518530 YQ |
6177 | dsc->u.block.load = load; |
6178 | dsc->u.block.user = 0; | |
6179 | dsc->u.block.increment = bit (insn1, 7); | |
6180 | dsc->u.block.before = bit (insn1, 8); | |
6181 | dsc->u.block.writeback = writeback; | |
6182 | dsc->u.block.cond = INST_AL; | |
6183 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6184 | |
34518530 YQ |
6185 | if (load) |
6186 | { | |
6187 | if (dsc->u.block.regmask == 0xffff) | |
6188 | { | |
6189 | /* This branch is impossible to happen. */ | |
6190 | gdb_assert (0); | |
6191 | } | |
6192 | else | |
6193 | { | |
6194 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 6195 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6196 | unsigned int i; |
34518530 YQ |
6197 | |
6198 | for (i = 0; i < num_in_list; i++) | |
6199 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
6200 | ||
6201 | if (writeback) | |
6202 | insn1 &= ~(1 << 5); | |
6203 | ||
6204 | new_regmask = (1 << num_in_list) - 1; | |
6205 | ||
136821d9 SM |
6206 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6207 | "%.4x, modified list %.4x", | |
6208 | rn, writeback ? "!" : "", | |
6209 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
6210 | |
6211 | dsc->modinsn[0] = insn1; | |
6212 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
6213 | dsc->numinsns = 2; | |
6214 | ||
6215 | dsc->cleanup = &cleanup_block_load_pc; | |
6216 | } | |
6217 | } | |
6218 | else | |
6219 | { | |
6220 | dsc->modinsn[0] = insn1; | |
6221 | dsc->modinsn[1] = insn2; | |
6222 | dsc->numinsns = 2; | |
6223 | dsc->cleanup = &cleanup_block_store_pc; | |
6224 | } | |
6225 | return 0; | |
6226 | } | |
6227 | ||
d9311bfa AT |
6228 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
6229 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
6230 | ||
6231 | ULONGEST | |
6232 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
6233 | int byte_order) | |
6234 | { | |
5f2dfcfd AT |
6235 | return read_memory_unsigned_integer (memaddr, len, |
6236 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
6237 | } |
6238 | ||
6239 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
6240 | ||
6241 | CORE_ADDR | |
6242 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
6243 | CORE_ADDR val) | |
6244 | { | |
ac7936df | 6245 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
6246 | } |
6247 | ||
6248 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
6249 | ||
e7cf25a8 | 6250 | static CORE_ADDR |
553cb527 | 6251 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 6252 | { |
d9311bfa AT |
6253 | return 0; |
6254 | } | |
6255 | ||
6256 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
6257 | ||
6258 | int | |
6259 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
6260 | { | |
6261 | return arm_is_thumb (self->regcache); | |
6262 | } | |
6263 | ||
6264 | /* single_step() is called just before we want to resume the inferior, | |
6265 | if we want to single-step it but there is no hardware or kernel | |
6266 | single-step support. We find the target of the coming instructions | |
6267 | and breakpoint them. */ | |
6268 | ||
a0ff9e1a | 6269 | std::vector<CORE_ADDR> |
f5ea389a | 6270 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 6271 | { |
ac7936df | 6272 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 6273 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
6274 | |
6275 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
6276 | &arm_get_next_pcs_ops, | |
6277 | gdbarch_byte_order (gdbarch), | |
6278 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 6279 | 0, |
d9311bfa AT |
6280 | regcache); |
6281 | ||
a0ff9e1a | 6282 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 6283 | |
a0ff9e1a SM |
6284 | for (CORE_ADDR &pc_ref : next_pcs) |
6285 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 6286 | |
93f9a11f | 6287 | return next_pcs; |
d9311bfa AT |
6288 | } |
6289 | ||
34518530 YQ |
6290 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
6291 | for Linux, where some SVC instructions must be treated specially. */ | |
6292 | ||
6293 | static void | |
6294 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6295 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6296 | { |
6297 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
6298 | ||
136821d9 SM |
6299 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
6300 | (unsigned long) resume_addr); | |
34518530 YQ |
6301 | |
6302 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
6303 | } | |
6304 | ||
6305 | ||
85102364 | 6306 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
6307 | |
6308 | static int | |
6309 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6310 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6311 | { |
6312 | /* Preparation: none. | |
6313 | Insn: unmodified svc. | |
6314 | Cleanup: pc <- insn_addr + insn_size. */ | |
6315 | ||
6316 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
6317 | instruction. */ | |
6318 | dsc->wrote_to_pc = 1; | |
6319 | ||
6320 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
6321 | if (dsc->u.svc.copy_svc_os) |
6322 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
6323 | else | |
6324 | { | |
6325 | dsc->cleanup = &cleanup_svc; | |
6326 | return 0; | |
6327 | } | |
34518530 YQ |
6328 | } |
6329 | ||
6330 | static int | |
6331 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 6332 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6333 | { |
6334 | ||
136821d9 SM |
6335 | displaced_debug_printf ("copying svc insn %.8lx", |
6336 | (unsigned long) insn); | |
34518530 YQ |
6337 | |
6338 | dsc->modinsn[0] = insn; | |
6339 | ||
6340 | return install_svc (gdbarch, regs, dsc); | |
6341 | } | |
6342 | ||
6343 | static int | |
6344 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 6345 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6346 | { |
6347 | ||
136821d9 | 6348 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 6349 | |
34518530 YQ |
6350 | dsc->modinsn[0] = insn; |
6351 | ||
6352 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
6353 | } |
6354 | ||
6355 | /* Copy undefined instructions. */ | |
6356 | ||
6357 | static int | |
7ff120b4 | 6358 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6359 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6360 | { |
136821d9 SM |
6361 | displaced_debug_printf ("copying undefined insn %.8lx", |
6362 | (unsigned long) insn); | |
cca44b1b JB |
6363 | |
6364 | dsc->modinsn[0] = insn; | |
6365 | ||
6366 | return 0; | |
6367 | } | |
6368 | ||
34518530 YQ |
6369 | static int |
6370 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 6371 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6372 | { |
6373 | ||
136821d9 SM |
6374 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
6375 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
6376 | |
6377 | dsc->modinsn[0] = insn1; | |
6378 | dsc->modinsn[1] = insn2; | |
6379 | dsc->numinsns = 2; | |
6380 | ||
6381 | return 0; | |
6382 | } | |
6383 | ||
cca44b1b JB |
6384 | /* Copy unpredictable instructions. */ |
6385 | ||
6386 | static int | |
7ff120b4 | 6387 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6388 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6389 | { |
136821d9 SM |
6390 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
6391 | (unsigned long) insn); | |
cca44b1b JB |
6392 | |
6393 | dsc->modinsn[0] = insn; | |
6394 | ||
6395 | return 0; | |
6396 | } | |
6397 | ||
6398 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
6399 | the presentation in the ARM ARM. */ | |
6400 | ||
6401 | static int | |
7ff120b4 YQ |
6402 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
6403 | struct regcache *regs, | |
1152d984 | 6404 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6405 | { |
6406 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
6407 | unsigned int rn = bits (insn, 16, 19); | |
6408 | ||
2f924de6 | 6409 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 6410 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 6411 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 6412 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 6413 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 6414 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 6415 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
6416 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
6417 | dsc); | |
cca44b1b | 6418 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 6419 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6420 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 6421 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
6422 | else if ((op1 & 0x77) == 0x51) |
6423 | { | |
6424 | if (rn != 0xf) | |
7ff120b4 | 6425 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 6426 | else |
7ff120b4 | 6427 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6428 | } |
6429 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 6430 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
6431 | else if (op1 == 0x57) |
6432 | switch (op2) | |
6433 | { | |
7ff120b4 YQ |
6434 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
6435 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
6436 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
6437 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
6438 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
6439 | } |
6440 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 6441 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6442 | else if ((op2 & 0x1) == 0x0) |
6443 | switch (op1 & ~0x80) | |
6444 | { | |
6445 | case 0x61: | |
7ff120b4 | 6446 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6447 | case 0x65: |
7ff120b4 | 6448 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 6449 | case 0x71: case 0x75: |
dda83cd7 | 6450 | /* pld/pldw reg. */ |
7ff120b4 | 6451 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6452 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 6453 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 6454 | default: |
7ff120b4 | 6455 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6456 | } |
6457 | else | |
7ff120b4 | 6458 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
6459 | } |
6460 | ||
6461 | static int | |
7ff120b4 YQ |
6462 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
6463 | struct regcache *regs, | |
1152d984 | 6464 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6465 | { |
6466 | if (bit (insn, 27) == 0) | |
7ff120b4 | 6467 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6468 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
6469 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
6470 | { | |
6471 | case 0x0: case 0x2: | |
7ff120b4 | 6472 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
6473 | |
6474 | case 0x1: case 0x3: | |
7ff120b4 | 6475 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
6476 | |
6477 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 6478 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6479 | |
6480 | case 0x8: | |
6481 | switch ((insn & 0xe00000) >> 21) | |
6482 | { | |
6483 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
6484 | /* stc/stc2. */ | |
7ff120b4 | 6485 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6486 | |
6487 | case 0x2: | |
7ff120b4 | 6488 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
6489 | |
6490 | default: | |
7ff120b4 | 6491 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6492 | } |
6493 | ||
6494 | case 0x9: | |
6495 | { | |
6496 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
6497 | switch ((insn & 0xe00000) >> 21) | |
6498 | { | |
6499 | case 0x1: case 0x3: | |
6500 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
6501 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
6502 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
6503 | |
6504 | case 0x2: | |
7ff120b4 | 6505 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6506 | |
6507 | case 0x4: case 0x5: case 0x6: case 0x7: | |
6508 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
6509 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
6510 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
6511 | |
6512 | default: | |
7ff120b4 | 6513 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6514 | } |
6515 | } | |
6516 | ||
6517 | case 0xa: | |
7ff120b4 | 6518 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
6519 | |
6520 | case 0xb: | |
6521 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 6522 | /* ldc/ldc2 lit. */ |
7ff120b4 | 6523 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6524 | else |
7ff120b4 | 6525 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6526 | |
6527 | case 0xc: | |
6528 | if (bit (insn, 4)) | |
7ff120b4 | 6529 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6530 | else |
7ff120b4 | 6531 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6532 | |
6533 | case 0xd: | |
6534 | if (bit (insn, 4)) | |
7ff120b4 | 6535 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6536 | else |
7ff120b4 | 6537 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6538 | |
6539 | default: | |
7ff120b4 | 6540 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6541 | } |
6542 | } | |
6543 | ||
6544 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
6545 | ||
6546 | static int | |
7ff120b4 YQ |
6547 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
6548 | struct regcache *regs, | |
1152d984 | 6549 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6550 | { |
6551 | unsigned int op2 = bits (insn, 4, 6); | |
6552 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
6553 | |
6554 | switch (op2) | |
6555 | { | |
6556 | case 0x0: | |
7ff120b4 | 6557 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
6558 | |
6559 | case 0x1: | |
6560 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 6561 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6562 | else if (op == 0x3) |
7ff120b4 | 6563 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 6564 | else |
7ff120b4 | 6565 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6566 | |
6567 | case 0x2: | |
6568 | if (op == 0x1) | |
dda83cd7 | 6569 | /* Not really supported. */ |
7ff120b4 | 6570 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 6571 | else |
7ff120b4 | 6572 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6573 | |
6574 | case 0x3: | |
6575 | if (op == 0x1) | |
7ff120b4 | 6576 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 6577 | regs, dsc); /* blx register. */ |
cca44b1b | 6578 | else |
7ff120b4 | 6579 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6580 | |
6581 | case 0x5: | |
7ff120b4 | 6582 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
6583 | |
6584 | case 0x7: | |
6585 | if (op == 0x1) | |
7ff120b4 | 6586 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 6587 | else if (op == 0x3) |
dda83cd7 | 6588 | /* Not really supported. */ |
7ff120b4 | 6589 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 6590 | /* Fall through. */ |
cca44b1b JB |
6591 | |
6592 | default: | |
7ff120b4 | 6593 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6594 | } |
6595 | } | |
6596 | ||
6597 | static int | |
7ff120b4 YQ |
6598 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
6599 | struct regcache *regs, | |
1152d984 | 6600 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6601 | { |
6602 | if (bit (insn, 25)) | |
6603 | switch (bits (insn, 20, 24)) | |
6604 | { | |
6605 | case 0x10: | |
7ff120b4 | 6606 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
6607 | |
6608 | case 0x14: | |
7ff120b4 | 6609 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
6610 | |
6611 | case 0x12: case 0x16: | |
7ff120b4 | 6612 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
6613 | |
6614 | default: | |
7ff120b4 | 6615 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6616 | } |
6617 | else | |
6618 | { | |
6619 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
6620 | ||
6621 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 6622 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6623 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 6624 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6625 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 6626 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 6627 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 6628 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 6629 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 6630 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 6631 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 6632 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 6633 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 6634 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
6635 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
6636 | dsc); | |
cca44b1b JB |
6637 | } |
6638 | ||
6639 | /* Should be unreachable. */ | |
6640 | return 1; | |
6641 | } | |
6642 | ||
6643 | static int | |
7ff120b4 YQ |
6644 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
6645 | struct regcache *regs, | |
1152d984 | 6646 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6647 | { |
6648 | int a = bit (insn, 25), b = bit (insn, 4); | |
6649 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
6650 | |
6651 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
6652 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 6653 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
6654 | else if ((!a && (op1 & 0x17) == 0x02) |
6655 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 6656 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
6657 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
6658 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 6659 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
6660 | else if ((!a && (op1 & 0x17) == 0x03) |
6661 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 6662 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
6663 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
6664 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 6665 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
6666 | else if ((!a && (op1 & 0x17) == 0x06) |
6667 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 6668 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
6669 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
6670 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 6671 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
6672 | else if ((!a && (op1 & 0x17) == 0x07) |
6673 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 6674 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
6675 | |
6676 | /* Should be unreachable. */ | |
6677 | return 1; | |
6678 | } | |
6679 | ||
6680 | static int | |
7ff120b4 | 6681 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6682 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6683 | { |
6684 | switch (bits (insn, 20, 24)) | |
6685 | { | |
6686 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 6687 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
6688 | |
6689 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 6690 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
6691 | |
6692 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
6693 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 6694 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
6695 | "decode/pack/unpack/saturate/reverse", dsc); |
6696 | ||
6697 | case 0x18: | |
6698 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
6699 | { | |
6700 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 6701 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 6702 | else |
7ff120b4 | 6703 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
6704 | } |
6705 | else | |
7ff120b4 | 6706 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6707 | |
6708 | case 0x1a: case 0x1b: | |
6709 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6710 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 6711 | else |
7ff120b4 | 6712 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6713 | |
6714 | case 0x1c: case 0x1d: | |
6715 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
6716 | { | |
6717 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 6718 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 6719 | else |
7ff120b4 | 6720 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
6721 | } |
6722 | else | |
7ff120b4 | 6723 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6724 | |
6725 | case 0x1e: case 0x1f: | |
6726 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6727 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 6728 | else |
7ff120b4 | 6729 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6730 | } |
6731 | ||
6732 | /* Should be unreachable. */ | |
6733 | return 1; | |
6734 | } | |
6735 | ||
6736 | static int | |
615234c1 | 6737 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 6738 | struct regcache *regs, |
1152d984 | 6739 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6740 | { |
6741 | if (bit (insn, 25)) | |
7ff120b4 | 6742 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 6743 | else |
7ff120b4 | 6744 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6745 | } |
6746 | ||
6747 | static int | |
7ff120b4 YQ |
6748 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
6749 | struct regcache *regs, | |
1152d984 | 6750 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6751 | { |
6752 | unsigned int opcode = bits (insn, 20, 24); | |
6753 | ||
6754 | switch (opcode) | |
6755 | { | |
6756 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 6757 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
6758 | |
6759 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
6760 | case 0x12: case 0x16: | |
7ff120b4 | 6761 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
6762 | |
6763 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
6764 | case 0x13: case 0x17: | |
7ff120b4 | 6765 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
6766 | |
6767 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6768 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6769 | /* Note: no writeback for these instructions. Bit 25 will always be | |
6770 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 6771 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6772 | } |
6773 | ||
6774 | /* Should be unreachable. */ | |
6775 | return 1; | |
6776 | } | |
6777 | ||
34518530 YQ |
6778 | /* Decode shifted register instructions. */ |
6779 | ||
6780 | static int | |
6781 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
6782 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6783 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6784 | { |
6785 | /* PC is only allowed to be used in instruction MOV. */ | |
6786 | ||
6787 | unsigned int op = bits (insn1, 5, 8); | |
6788 | unsigned int rn = bits (insn1, 0, 3); | |
6789 | ||
6790 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
6791 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
6792 | else | |
6793 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6794 | "dp (shift reg)", dsc); | |
6795 | } | |
6796 | ||
6797 | ||
6798 | /* Decode extension register load/store. Exactly the same as | |
6799 | arm_decode_ext_reg_ld_st. */ | |
6800 | ||
6801 | static int | |
6802 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
6803 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6804 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6805 | { |
6806 | unsigned int opcode = bits (insn1, 4, 8); | |
6807 | ||
6808 | switch (opcode) | |
6809 | { | |
6810 | case 0x04: case 0x05: | |
6811 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6812 | "vfp/neon vmov", dsc); | |
6813 | ||
6814 | case 0x08: case 0x0c: /* 01x00 */ | |
6815 | case 0x0a: case 0x0e: /* 01x10 */ | |
6816 | case 0x12: case 0x16: /* 10x10 */ | |
6817 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6818 | "vfp/neon vstm/vpush", dsc); | |
6819 | ||
6820 | case 0x09: case 0x0d: /* 01x01 */ | |
6821 | case 0x0b: case 0x0f: /* 01x11 */ | |
6822 | case 0x13: case 0x17: /* 10x11 */ | |
6823 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6824 | "vfp/neon vldm/vpop", dsc); | |
6825 | ||
6826 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6827 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6828 | "vstr", dsc); | |
6829 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6830 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
6831 | } | |
6832 | ||
6833 | /* Should be unreachable. */ | |
6834 | return 1; | |
6835 | } | |
6836 | ||
cca44b1b | 6837 | static int |
12545665 | 6838 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6839 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6840 | { |
6841 | unsigned int op1 = bits (insn, 20, 25); | |
6842 | int op = bit (insn, 4); | |
6843 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
6844 | |
6845 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 6846 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6847 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
6848 | && (coproc & 0xe) != 0xa) | |
6849 | /* stc/stc2. */ | |
7ff120b4 | 6850 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6851 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
6852 | && (coproc & 0xe) != 0xa) | |
6853 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 6854 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6855 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 6856 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 6857 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 6858 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 6859 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6860 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 6861 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 6862 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6863 | else if ((op1 & 0x30) == 0x20 && !op) |
6864 | { | |
6865 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 6866 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 6867 | else |
7ff120b4 | 6868 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6869 | } |
6870 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 6871 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 6872 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6873 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6874 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 6875 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6876 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 6877 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 6878 | else |
7ff120b4 | 6879 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
6880 | } |
6881 | ||
34518530 YQ |
6882 | static int |
6883 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
6884 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6885 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6886 | { |
6887 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
6888 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
6889 | unsigned int bit_9 = bit (insn1, 9); | |
6890 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
6891 | |
6892 | if (bit_9 == 0) | |
6893 | { | |
6894 | if (bit_5_8 == 2) | |
6895 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6896 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
6897 | dsc); | |
6898 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
6899 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
6900 | else | |
6901 | { | |
6902 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
6903 | if ((coproc & 0xe) == 0xa) | |
6904 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
6905 | dsc); | |
6906 | else /* coproc is not 101x. */ | |
6907 | { | |
6908 | if (bit_4 == 0) /* STC/STC2. */ | |
6909 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6910 | "stc/stc2", dsc); | |
405feb71 | 6911 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
6912 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
6913 | regs, dsc); | |
6914 | } | |
6915 | } | |
6916 | } | |
6917 | else | |
6918 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
6919 | ||
6920 | return 0; | |
6921 | } | |
6922 | ||
6923 | static void | |
6924 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6925 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
6926 | { |
6927 | /* ADR Rd, #imm | |
6928 | ||
6929 | Rewrite as: | |
6930 | ||
6931 | Preparation: Rd <- PC | |
6932 | Insn: ADD Rd, #imm | |
6933 | Cleanup: Null. | |
6934 | */ | |
6935 | ||
6936 | /* Rd <- PC */ | |
6937 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6938 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
6939 | } | |
6940 | ||
6941 | static int | |
6942 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6943 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
6944 | int rd, unsigned int imm) |
6945 | { | |
6946 | ||
6947 | /* Encoding T2: ADDS Rd, #imm */ | |
6948 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
6949 | ||
6950 | install_pc_relative (gdbarch, regs, dsc, rd); | |
6951 | ||
6952 | return 0; | |
6953 | } | |
6954 | ||
6955 | static int | |
6956 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
6957 | struct regcache *regs, | |
1152d984 | 6958 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6959 | { |
6960 | unsigned int rd = bits (insn, 8, 10); | |
6961 | unsigned int imm8 = bits (insn, 0, 7); | |
6962 | ||
136821d9 SM |
6963 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
6964 | rd, imm8, insn); | |
34518530 YQ |
6965 | |
6966 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
6967 | } | |
6968 | ||
6969 | static int | |
6970 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
6971 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6972 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6973 | { |
6974 | unsigned int rd = bits (insn2, 8, 11); | |
6975 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
6976 | extract raw immediate encoding rather than computing immediate. When | |
6977 | generating ADD or SUB instruction, we can simply perform OR operation to | |
6978 | set immediate into ADD. */ | |
6979 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
6980 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
6981 | ||
136821d9 SM |
6982 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
6983 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
6984 | |
6985 | if (bit (insn1, 7)) /* Encoding T2 */ | |
6986 | { | |
6987 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
6988 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
6989 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6990 | } | |
6991 | else /* Encoding T3 */ | |
6992 | { | |
6993 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
6994 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
6995 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
6996 | } | |
6997 | dsc->numinsns = 2; | |
6998 | ||
6999 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7000 | ||
7001 | return 0; | |
7002 | } | |
7003 | ||
7004 | static int | |
615234c1 | 7005 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7006 | struct regcache *regs, |
1152d984 | 7007 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7008 | { |
7009 | unsigned int rt = bits (insn1, 8, 10); | |
7010 | unsigned int pc; | |
7011 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7012 | |
7013 | /* LDR Rd, #imm8 | |
7014 | ||
7015 | Rwrite as: | |
7016 | ||
7017 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7018 | ||
7019 | Insn: LDR R0, [R2, R3]; | |
7020 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7021 | ||
136821d9 | 7022 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7023 | |
7024 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7025 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7026 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7027 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7028 | /* The assembler calculates the required value of the offset from the | |
7029 | Align(PC,4) value of this instruction to the label. */ | |
7030 | pc = pc & 0xfffffffc; | |
7031 | ||
7032 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7033 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7034 | ||
7035 | dsc->rd = rt; | |
7036 | dsc->u.ldst.xfersize = 4; | |
7037 | dsc->u.ldst.rn = 0; | |
7038 | dsc->u.ldst.immed = 0; | |
7039 | dsc->u.ldst.writeback = 0; | |
7040 | dsc->u.ldst.restore_r4 = 0; | |
7041 | ||
7042 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7043 | ||
7044 | dsc->cleanup = &cleanup_load; | |
7045 | ||
7046 | return 0; | |
7047 | } | |
7048 | ||
405feb71 | 7049 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
7050 | |
7051 | static int | |
7052 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
7053 | struct regcache *regs, | |
1152d984 | 7054 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7055 | { |
7056 | int non_zero = bit (insn1, 11); | |
7057 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
7058 | CORE_ADDR from = dsc->insn_addr; | |
7059 | int rn = bits (insn1, 0, 2); | |
7060 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
7061 | ||
7062 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
7063 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
7064 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
7065 | condition is false, let it be, cleanup_branch will do nothing. */ | |
7066 | if (dsc->u.branch.cond) | |
7067 | { | |
7068 | dsc->u.branch.cond = INST_AL; | |
7069 | dsc->u.branch.dest = from + 4 + imm5; | |
7070 | } | |
7071 | else | |
7072 | dsc->u.branch.dest = from + 2; | |
7073 | ||
7074 | dsc->u.branch.link = 0; | |
7075 | dsc->u.branch.exchange = 0; | |
7076 | ||
136821d9 SM |
7077 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
7078 | non_zero ? "cbnz" : "cbz", | |
7079 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
7080 | |
7081 | dsc->modinsn[0] = THUMB_NOP; | |
7082 | ||
7083 | dsc->cleanup = &cleanup_branch; | |
7084 | return 0; | |
7085 | } | |
7086 | ||
7087 | /* Copy Table Branch Byte/Halfword */ | |
7088 | static int | |
7089 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7090 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7091 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7092 | { |
7093 | ULONGEST rn_val, rm_val; | |
7094 | int is_tbh = bit (insn2, 4); | |
7095 | CORE_ADDR halfwords = 0; | |
7096 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7097 | ||
7098 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7099 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7100 | ||
7101 | if (is_tbh) | |
7102 | { | |
7103 | gdb_byte buf[2]; | |
7104 | ||
7105 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7106 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7107 | } | |
7108 | else | |
7109 | { | |
7110 | gdb_byte buf[1]; | |
7111 | ||
7112 | target_read_memory (rn_val + rm_val, buf, 1); | |
7113 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7114 | } | |
7115 | ||
136821d9 SM |
7116 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
7117 | is_tbh ? "tbh" : "tbb", | |
7118 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7119 | (unsigned int) halfwords); | |
34518530 YQ |
7120 | |
7121 | dsc->u.branch.cond = INST_AL; | |
7122 | dsc->u.branch.link = 0; | |
7123 | dsc->u.branch.exchange = 0; | |
7124 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7125 | ||
7126 | dsc->cleanup = &cleanup_branch; | |
7127 | ||
7128 | return 0; | |
7129 | } | |
7130 | ||
7131 | static void | |
7132 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7133 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7134 | { |
7135 | /* PC <- r7 */ | |
7136 | int val = displaced_read_reg (regs, dsc, 7); | |
7137 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7138 | ||
7139 | /* r7 <- r8 */ | |
7140 | val = displaced_read_reg (regs, dsc, 8); | |
7141 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7142 | ||
7143 | /* r8 <- tmp[0] */ | |
7144 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7145 | ||
7146 | } | |
7147 | ||
7148 | static int | |
615234c1 | 7149 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7150 | struct regcache *regs, |
1152d984 | 7151 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7152 | { |
7153 | dsc->u.block.regmask = insn1 & 0x00ff; | |
7154 | ||
7155 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
7156 | to : | |
7157 | ||
7158 | (1) register list is full, that is, r0-r7 are used. | |
7159 | Prepare: tmp[0] <- r8 | |
7160 | ||
7161 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
7162 | MOV r8, r7; Move value of r7 to r8; | |
7163 | POP {r7}; Store PC value into r7. | |
7164 | ||
7165 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
7166 | ||
7167 | (2) register list is not full, supposing there are N registers in | |
7168 | register list (except PC, 0 <= N <= 7). | |
7169 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
7170 | ||
7171 | POP {r0, r1, ...., rN}; | |
7172 | ||
7173 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
7174 | from tmp[] properly. | |
7175 | */ | |
136821d9 SM |
7176 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
7177 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
7178 | |
7179 | if (dsc->u.block.regmask == 0xff) | |
7180 | { | |
7181 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
7182 | ||
7183 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
7184 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
7185 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
7186 | ||
7187 | dsc->numinsns = 3; | |
7188 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
7189 | } | |
7190 | else | |
7191 | { | |
5f661e03 | 7192 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
7193 | unsigned int i; |
7194 | unsigned int new_regmask; | |
34518530 YQ |
7195 | |
7196 | for (i = 0; i < num_in_list + 1; i++) | |
7197 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7198 | ||
7199 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
7200 | ||
136821d9 SM |
7201 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
7202 | "modified list %.4x", | |
7203 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7204 | |
7205 | dsc->u.block.regmask |= 0x8000; | |
7206 | dsc->u.block.writeback = 0; | |
7207 | dsc->u.block.cond = INST_AL; | |
7208 | ||
7209 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
7210 | ||
7211 | dsc->cleanup = &cleanup_block_load_pc; | |
7212 | } | |
7213 | ||
7214 | return 0; | |
7215 | } | |
7216 | ||
7217 | static void | |
7218 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7219 | struct regcache *regs, | |
1152d984 | 7220 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7221 | { |
7222 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
7223 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
7224 | int err = 0; | |
7225 | ||
7226 | /* 16-bit thumb instructions. */ | |
7227 | switch (op_bit_12_15) | |
7228 | { | |
7229 | /* Shift (imme), add, subtract, move and compare. */ | |
7230 | case 0: case 1: case 2: case 3: | |
7231 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7232 | "shift/add/sub/mov/cmp", | |
7233 | dsc); | |
7234 | break; | |
7235 | case 4: | |
7236 | switch (op_bit_10_11) | |
7237 | { | |
7238 | case 0: /* Data-processing */ | |
7239 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7240 | "data-processing", | |
7241 | dsc); | |
7242 | break; | |
7243 | case 1: /* Special data instructions and branch and exchange. */ | |
7244 | { | |
7245 | unsigned short op = bits (insn1, 7, 9); | |
7246 | if (op == 6 || op == 7) /* BX or BLX */ | |
7247 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
7248 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
7249 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
7250 | else | |
7251 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
7252 | dsc); | |
7253 | } | |
7254 | break; | |
7255 | default: /* LDR (literal) */ | |
7256 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
7257 | } | |
7258 | break; | |
7259 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
7260 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
7261 | break; | |
7262 | case 10: | |
7263 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
7264 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
7265 | else /* Generate SP-relative address */ | |
7266 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
7267 | break; | |
7268 | case 11: /* Misc 16-bit instructions */ | |
7269 | { | |
7270 | switch (bits (insn1, 8, 11)) | |
7271 | { | |
7272 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
7273 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
7274 | break; | |
7275 | case 12: case 13: /* POP */ | |
7276 | if (bit (insn1, 8)) /* PC is in register list. */ | |
7277 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
7278 | else | |
7279 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
7280 | break; | |
7281 | case 15: /* If-Then, and hints */ | |
7282 | if (bits (insn1, 0, 3)) | |
7283 | /* If-Then makes up to four following instructions conditional. | |
7284 | IT instruction itself is not conditional, so handle it as a | |
7285 | common unmodified instruction. */ | |
7286 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
7287 | dsc); | |
7288 | else | |
7289 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
7290 | break; | |
7291 | default: | |
7292 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
7293 | } | |
7294 | } | |
7295 | break; | |
7296 | case 12: | |
7297 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
7298 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
7299 | else /* Load multiple registers */ | |
7300 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
7301 | break; | |
7302 | case 13: /* Conditional branch and supervisor call */ | |
7303 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
7304 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7305 | else | |
7306 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
7307 | break; | |
7308 | case 14: /* Unconditional branch */ | |
7309 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7310 | break; | |
7311 | default: | |
7312 | err = 1; | |
7313 | } | |
7314 | ||
7315 | if (err) | |
7316 | internal_error (__FILE__, __LINE__, | |
7317 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
7318 | } | |
7319 | ||
7320 | static int | |
7321 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
7322 | uint16_t insn1, uint16_t insn2, | |
7323 | struct regcache *regs, | |
1152d984 | 7324 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7325 | { |
7326 | int rt = bits (insn2, 12, 15); | |
7327 | int rn = bits (insn1, 0, 3); | |
7328 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
7329 | |
7330 | switch (bits (insn1, 5, 6)) | |
7331 | { | |
7332 | case 0: /* Load byte and memory hints */ | |
7333 | if (rt == 0xf) /* PLD/PLI */ | |
7334 | { | |
7335 | if (rn == 0xf) | |
7336 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
7337 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
7338 | else | |
7339 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7340 | "pli/pld", dsc); | |
7341 | } | |
7342 | else | |
7343 | { | |
7344 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
7345 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7346 | 1); | |
7347 | else | |
7348 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7349 | "ldrb{reg, immediate}/ldrbt", | |
7350 | dsc); | |
7351 | } | |
7352 | ||
7353 | break; | |
7354 | case 1: /* Load halfword and memory hints. */ | |
7355 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
7356 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7357 | "pld/unalloc memhint", dsc); | |
7358 | else | |
7359 | { | |
7360 | if (rn == 0xf) | |
7361 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7362 | 2); | |
7363 | else | |
7364 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7365 | "ldrh/ldrht", dsc); | |
7366 | } | |
7367 | break; | |
7368 | case 2: /* Load word */ | |
7369 | { | |
7370 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
7371 | ||
7372 | if (rn == 0xf) | |
7373 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
7374 | else if (op1 == 0x1) /* Encoding T3 */ | |
7375 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
7376 | 0, 1); | |
7377 | else /* op1 == 0x0 */ | |
7378 | { | |
7379 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
7380 | /* LDR (immediate) */ | |
7381 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7382 | dsc, bit (insn2, 8), 1); | |
7383 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
7384 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7385 | "ldrt", dsc); | |
7386 | else | |
7387 | /* LDR (register) */ | |
7388 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7389 | dsc, 0, 0); | |
7390 | } | |
7391 | break; | |
7392 | } | |
7393 | default: | |
7394 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7395 | break; | |
7396 | } | |
7397 | return 0; | |
7398 | } | |
7399 | ||
7400 | static void | |
7401 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7402 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7403 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7404 | { |
7405 | int err = 0; | |
7406 | unsigned short op = bit (insn2, 15); | |
7407 | unsigned int op1 = bits (insn1, 11, 12); | |
7408 | ||
7409 | switch (op1) | |
7410 | { | |
7411 | case 1: | |
7412 | { | |
7413 | switch (bits (insn1, 9, 10)) | |
7414 | { | |
7415 | case 0: | |
7416 | if (bit (insn1, 6)) | |
7417 | { | |
405feb71 | 7418 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
7419 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
7420 | && bits (insn2, 5, 7) == 0) | |
7421 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
7422 | dsc); | |
7423 | else | |
7424 | /* PC is not allowed to use in load/store {dual, exclusive} | |
7425 | instructions. */ | |
7426 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7427 | "load/store dual/ex", dsc); | |
7428 | } | |
7429 | else /* load/store multiple */ | |
7430 | { | |
7431 | switch (bits (insn1, 7, 8)) | |
7432 | { | |
7433 | case 0: case 3: /* SRS, RFE */ | |
7434 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7435 | "srs/rfe", dsc); | |
7436 | break; | |
7437 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
7438 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
7439 | break; | |
7440 | } | |
7441 | } | |
7442 | break; | |
7443 | ||
7444 | case 1: | |
7445 | /* Data-processing (shift register). */ | |
7446 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
7447 | dsc); | |
7448 | break; | |
7449 | default: /* Coprocessor instructions. */ | |
7450 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7451 | break; | |
7452 | } | |
7453 | break; | |
7454 | } | |
7455 | case 2: /* op1 = 2 */ | |
7456 | if (op) /* Branch and misc control. */ | |
7457 | { | |
7458 | if (bit (insn2, 14) /* BLX/BL */ | |
7459 | || bit (insn2, 12) /* Unconditional branch */ | |
7460 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
7461 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
7462 | else | |
7463 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7464 | "misc ctrl", dsc); | |
7465 | } | |
7466 | else | |
7467 | { | |
7468 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
7469 | { | |
b926417a | 7470 | int dp_op = bits (insn1, 4, 8); |
34518530 | 7471 | int rn = bits (insn1, 0, 3); |
b926417a | 7472 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
7473 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
7474 | regs, dsc); | |
7475 | else | |
7476 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7477 | "dp/pb", dsc); | |
7478 | } | |
405feb71 | 7479 | else /* Data processing (modified immediate) */ |
34518530 YQ |
7480 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
7481 | "dp/mi", dsc); | |
7482 | } | |
7483 | break; | |
7484 | case 3: /* op1 = 3 */ | |
7485 | switch (bits (insn1, 9, 10)) | |
7486 | { | |
7487 | case 0: | |
7488 | if (bit (insn1, 4)) | |
7489 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
7490 | regs, dsc); | |
7491 | else /* NEON Load/Store and Store single data item */ | |
7492 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7493 | "neon elt/struct load/store", | |
7494 | dsc); | |
7495 | break; | |
7496 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
7497 | switch (bits (insn1, 7, 8)) | |
7498 | { | |
7499 | case 0: case 1: /* Data processing (register) */ | |
7500 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7501 | "dp(reg)", dsc); | |
7502 | break; | |
7503 | case 2: /* Multiply and absolute difference */ | |
7504 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7505 | "mul/mua/diff", dsc); | |
7506 | break; | |
7507 | case 3: /* Long multiply and divide */ | |
7508 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7509 | "lmul/lmua", dsc); | |
7510 | break; | |
7511 | } | |
7512 | break; | |
7513 | default: /* Coprocessor instructions */ | |
7514 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7515 | break; | |
7516 | } | |
7517 | break; | |
7518 | default: | |
7519 | err = 1; | |
7520 | } | |
7521 | ||
7522 | if (err) | |
7523 | internal_error (__FILE__, __LINE__, | |
7524 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
7525 | ||
7526 | } | |
7527 | ||
b434a28f YQ |
7528 | static void |
7529 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 7530 | struct regcache *regs, |
1152d984 | 7531 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 7532 | { |
34518530 YQ |
7533 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7534 | uint16_t insn1 | |
7535 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
7536 | ||
136821d9 SM |
7537 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
7538 | insn1, (unsigned long) from); | |
34518530 YQ |
7539 | |
7540 | dsc->is_thumb = 1; | |
7541 | dsc->insn_size = thumb_insn_size (insn1); | |
7542 | if (thumb_insn_size (insn1) == 4) | |
7543 | { | |
7544 | uint16_t insn2 | |
7545 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
7546 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
7547 | } | |
7548 | else | |
7549 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
7550 | } |
7551 | ||
cca44b1b | 7552 | void |
b434a28f YQ |
7553 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
7554 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 7555 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7556 | { |
7557 | int err = 0; | |
b434a28f YQ |
7558 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7559 | uint32_t insn; | |
cca44b1b JB |
7560 | |
7561 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
7562 | here and override below if/when necessary. */ | |
7563 | dsc->numinsns = 1; | |
7564 | dsc->insn_addr = from; | |
7565 | dsc->scratch_base = to; | |
7566 | dsc->cleanup = NULL; | |
7567 | dsc->wrote_to_pc = 0; | |
7568 | ||
b434a28f | 7569 | if (!displaced_in_arm_mode (regs)) |
12545665 | 7570 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 7571 | |
4db71c0b YQ |
7572 | dsc->is_thumb = 0; |
7573 | dsc->insn_size = 4; | |
b434a28f | 7574 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
7575 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
7576 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 7577 | |
cca44b1b | 7578 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 7579 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7580 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
7581 | { | |
7582 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 7583 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7584 | break; |
7585 | ||
7586 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 7587 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7588 | break; |
7589 | ||
7590 | case 0x7: | |
7ff120b4 | 7591 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
7592 | break; |
7593 | ||
7594 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 7595 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7596 | break; |
7597 | ||
7598 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 7599 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7600 | break; |
7601 | } | |
7602 | ||
7603 | if (err) | |
7604 | internal_error (__FILE__, __LINE__, | |
7605 | _("arm_process_displaced_insn: Instruction decode error")); | |
7606 | } | |
7607 | ||
7608 | /* Actually set up the scratch space for a displaced instruction. */ | |
7609 | ||
7610 | void | |
7611 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
7612 | CORE_ADDR to, |
7613 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
7614 | { |
7615 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4db71c0b | 7616 | unsigned int i, len, offset; |
cca44b1b | 7617 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 7618 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 7619 | const gdb_byte *bkp_insn; |
cca44b1b | 7620 | |
4db71c0b | 7621 | offset = 0; |
cca44b1b JB |
7622 | /* Poke modified instruction(s). */ |
7623 | for (i = 0; i < dsc->numinsns; i++) | |
7624 | { | |
136821d9 SM |
7625 | if (size == 4) |
7626 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
7627 | dsc->modinsn[i], (unsigned long) to + offset); | |
7628 | else if (size == 2) | |
7629 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
7630 | (unsigned short) dsc->modinsn[i], | |
7631 | (unsigned long) to + offset); | |
4db71c0b | 7632 | |
4db71c0b YQ |
7633 | write_memory_unsigned_integer (to + offset, size, |
7634 | byte_order_for_code, | |
cca44b1b | 7635 | dsc->modinsn[i]); |
4db71c0b YQ |
7636 | offset += size; |
7637 | } | |
7638 | ||
7639 | /* Choose the correct breakpoint instruction. */ | |
7640 | if (dsc->is_thumb) | |
7641 | { | |
7642 | bkp_insn = tdep->thumb_breakpoint; | |
7643 | len = tdep->thumb_breakpoint_size; | |
7644 | } | |
7645 | else | |
7646 | { | |
7647 | bkp_insn = tdep->arm_breakpoint; | |
7648 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
7649 | } |
7650 | ||
7651 | /* Put breakpoint afterwards. */ | |
4db71c0b | 7652 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 7653 | |
136821d9 SM |
7654 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
7655 | paddress (gdbarch, to)); | |
cca44b1b JB |
7656 | } |
7657 | ||
cca44b1b JB |
7658 | /* Entry point for cleaning things up after a displaced instruction has been |
7659 | single-stepped. */ | |
7660 | ||
7661 | void | |
7662 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 7663 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
7664 | CORE_ADDR from, CORE_ADDR to, |
7665 | struct regcache *regs) | |
7666 | { | |
1152d984 SM |
7667 | arm_displaced_step_copy_insn_closure *dsc |
7668 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 7669 | |
cca44b1b JB |
7670 | if (dsc->cleanup) |
7671 | dsc->cleanup (gdbarch, regs, dsc); | |
7672 | ||
7673 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
7674 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
7675 | dsc->insn_addr + dsc->insn_size); | |
7676 | ||
cca44b1b JB |
7677 | } |
7678 | ||
7679 | #include "bfd-in2.h" | |
7680 | #include "libcoff.h" | |
7681 | ||
7682 | static int | |
7683 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
7684 | { | |
e47ad6c0 YQ |
7685 | gdb_disassembler *di |
7686 | = static_cast<gdb_disassembler *>(info->application_data); | |
7687 | struct gdbarch *gdbarch = di->arch (); | |
9779414d DJ |
7688 | |
7689 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
7690 | { |
7691 | static asymbol *asym; | |
7692 | static combined_entry_type ce; | |
7693 | static struct coff_symbol_struct csym; | |
7694 | static struct bfd fake_bfd; | |
7695 | static bfd_target fake_target; | |
7696 | ||
7697 | if (csym.native == NULL) | |
7698 | { | |
7699 | /* Create a fake symbol vector containing a Thumb symbol. | |
7700 | This is solely so that the code in print_insn_little_arm() | |
7701 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
7702 | the presence of a Thumb symbol and switch to decoding | |
7703 | Thumb instructions. */ | |
7704 | ||
7705 | fake_target.flavour = bfd_target_coff_flavour; | |
7706 | fake_bfd.xvec = &fake_target; | |
7707 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
7708 | csym.native = &ce; | |
7709 | csym.symbol.the_bfd = &fake_bfd; | |
7710 | csym.symbol.name = "fake"; | |
7711 | asym = (asymbol *) & csym; | |
7712 | } | |
7713 | ||
7714 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
7715 | info->symbols = &asym; | |
7716 | } | |
7717 | else | |
7718 | info->symbols = NULL; | |
7719 | ||
e60eb288 YQ |
7720 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
7721 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
7722 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
7723 | the assert on the mismatch of info->mach and |
7724 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
7725 | default_print_insn. */ | |
7726 | if (current_program_space->exec_bfd () != NULL) | |
e60eb288 YQ |
7727 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
7728 | ||
6394c606 | 7729 | return default_print_insn (memaddr, info); |
cca44b1b JB |
7730 | } |
7731 | ||
7732 | /* The following define instruction sequences that will cause ARM | |
7733 | cpu's to take an undefined instruction trap. These are used to | |
7734 | signal a breakpoint to GDB. | |
7735 | ||
7736 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
7737 | modes. A different instruction is required for each mode. The ARM | |
7738 | cpu's can also be big or little endian. Thus four different | |
7739 | instructions are needed to support all cases. | |
7740 | ||
7741 | Note: ARMv4 defines several new instructions that will take the | |
7742 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
7743 | not in fact add the new instructions. The new undefined | |
7744 | instructions in ARMv4 are all instructions that had no defined | |
7745 | behaviour in earlier chips. There is no guarantee that they will | |
7746 | raise an exception, but may be treated as NOP's. In practice, it | |
7747 | may only safe to rely on instructions matching: | |
7748 | ||
7749 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
7750 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
7751 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
7752 | ||
0963b4bd | 7753 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
7754 | following use a condition predicate of ALWAYS so it is always TRUE. |
7755 | ||
7756 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
7757 | and NetBSD all use a software interrupt rather than an undefined | |
7758 | instruction to force a trap. This can be handled by by the | |
7759 | abi-specific code during establishment of the gdbarch vector. */ | |
7760 | ||
7761 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
7762 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
7763 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
7764 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
7765 | ||
948f8e3d PA |
7766 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
7767 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
7768 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
7769 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 7770 | |
cd6c3b4f YQ |
7771 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7772 | ||
d19280ad YQ |
7773 | static int |
7774 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b JB |
7775 | { |
7776 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
177321bd | 7777 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 7778 | |
9779414d | 7779 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
7780 | { |
7781 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
7782 | |
7783 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
7784 | check whether we are replacing a 32-bit instruction. */ | |
7785 | if (tdep->thumb2_breakpoint != NULL) | |
7786 | { | |
7787 | gdb_byte buf[2]; | |
d19280ad | 7788 | |
177321bd DJ |
7789 | if (target_read_memory (*pcptr, buf, 2) == 0) |
7790 | { | |
7791 | unsigned short inst1; | |
d19280ad | 7792 | |
177321bd | 7793 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 7794 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 7795 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
7796 | } |
7797 | } | |
7798 | ||
d19280ad | 7799 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
7800 | } |
7801 | else | |
d19280ad YQ |
7802 | return ARM_BP_KIND_ARM; |
7803 | ||
7804 | } | |
7805 | ||
cd6c3b4f YQ |
7806 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7807 | ||
d19280ad YQ |
7808 | static const gdb_byte * |
7809 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7810 | { | |
7811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7812 | ||
7813 | switch (kind) | |
cca44b1b | 7814 | { |
d19280ad YQ |
7815 | case ARM_BP_KIND_ARM: |
7816 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 7817 | return tdep->arm_breakpoint; |
d19280ad YQ |
7818 | case ARM_BP_KIND_THUMB: |
7819 | *size = tdep->thumb_breakpoint_size; | |
7820 | return tdep->thumb_breakpoint; | |
7821 | case ARM_BP_KIND_THUMB2: | |
7822 | *size = tdep->thumb2_breakpoint_size; | |
7823 | return tdep->thumb2_breakpoint; | |
7824 | default: | |
7825 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
7826 | } |
7827 | } | |
7828 | ||
833b7ab5 YQ |
7829 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
7830 | ||
7831 | static int | |
7832 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
7833 | struct regcache *regcache, | |
7834 | CORE_ADDR *pcptr) | |
7835 | { | |
7836 | gdb_byte buf[4]; | |
7837 | ||
7838 | /* Check the memory pointed by PC is readable. */ | |
7839 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
7840 | { | |
7841 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
7842 | |
7843 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
7844 | &arm_get_next_pcs_ops, | |
7845 | gdbarch_byte_order (gdbarch), | |
7846 | gdbarch_byte_order_for_code (gdbarch), | |
7847 | 0, | |
7848 | regcache); | |
7849 | ||
a0ff9e1a | 7850 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
7851 | |
7852 | /* If MEMADDR is the next instruction of current pc, do the | |
7853 | software single step computation, and get the thumb mode by | |
7854 | the destination address. */ | |
a0ff9e1a | 7855 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
7856 | { |
7857 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
7858 | { | |
833b7ab5 YQ |
7859 | if (IS_THUMB_ADDR (pc)) |
7860 | { | |
7861 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
7862 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
7863 | } | |
7864 | else | |
7865 | return ARM_BP_KIND_ARM; | |
7866 | } | |
7867 | } | |
833b7ab5 YQ |
7868 | } |
7869 | ||
7870 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
7871 | } | |
7872 | ||
cca44b1b JB |
7873 | /* Extract from an array REGBUF containing the (raw) register state a |
7874 | function return value of type TYPE, and copy that, in virtual | |
7875 | format, into VALBUF. */ | |
7876 | ||
7877 | static void | |
7878 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
7879 | gdb_byte *valbuf) | |
7880 | { | |
ac7936df | 7881 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b JB |
7882 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7883 | ||
78134374 | 7884 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b JB |
7885 | { |
7886 | switch (gdbarch_tdep (gdbarch)->fp_model) | |
7887 | { | |
7888 | case ARM_FLOAT_FPA: | |
7889 | { | |
7890 | /* The value is in register F0 in internal format. We need to | |
7891 | extract the raw value and then convert it to the desired | |
7892 | internal type. */ | |
f0452268 | 7893 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 7894 | |
dca08e1f | 7895 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
7896 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
7897 | valbuf, type); | |
cca44b1b JB |
7898 | } |
7899 | break; | |
7900 | ||
7901 | case ARM_FLOAT_SOFT_FPA: | |
7902 | case ARM_FLOAT_SOFT_VFP: | |
7903 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
7904 | not using the VFP ABI code. */ | |
7905 | case ARM_FLOAT_VFP: | |
dca08e1f | 7906 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
cca44b1b | 7907 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
7908 | regs->cooked_read (ARM_A1_REGNUM + 1, |
7909 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
7910 | break; |
7911 | ||
7912 | default: | |
0963b4bd MS |
7913 | internal_error (__FILE__, __LINE__, |
7914 | _("arm_extract_return_value: " | |
7915 | "Floating point model not supported")); | |
cca44b1b JB |
7916 | break; |
7917 | } | |
7918 | } | |
78134374 SM |
7919 | else if (type->code () == TYPE_CODE_INT |
7920 | || type->code () == TYPE_CODE_CHAR | |
7921 | || type->code () == TYPE_CODE_BOOL | |
7922 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 7923 | || TYPE_IS_REFERENCE (type) |
78134374 | 7924 | || type->code () == TYPE_CODE_ENUM) |
cca44b1b | 7925 | { |
b021a221 MS |
7926 | /* If the type is a plain integer, then the access is |
7927 | straight-forward. Otherwise we have to play around a bit | |
7928 | more. */ | |
cca44b1b JB |
7929 | int len = TYPE_LENGTH (type); |
7930 | int regno = ARM_A1_REGNUM; | |
7931 | ULONGEST tmp; | |
7932 | ||
7933 | while (len > 0) | |
7934 | { | |
7935 | /* By using store_unsigned_integer we avoid having to do | |
7936 | anything special for small big-endian values. */ | |
7937 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
7938 | store_unsigned_integer (valbuf, | |
f0452268 AH |
7939 | (len > ARM_INT_REGISTER_SIZE |
7940 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 7941 | byte_order, tmp); |
f0452268 AH |
7942 | len -= ARM_INT_REGISTER_SIZE; |
7943 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
7944 | } |
7945 | } | |
7946 | else | |
7947 | { | |
7948 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
7949 | been stored to word-aligned memory and then loaded into |
7950 | registers with 32-bit load instruction(s). */ | |
cca44b1b JB |
7951 | int len = TYPE_LENGTH (type); |
7952 | int regno = ARM_A1_REGNUM; | |
f0452268 | 7953 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
7954 | |
7955 | while (len > 0) | |
7956 | { | |
dca08e1f | 7957 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 7958 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
7959 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
7960 | len -= ARM_INT_REGISTER_SIZE; | |
7961 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
7962 | } |
7963 | } | |
7964 | } | |
7965 | ||
7966 | ||
7967 | /* Will a function return an aggregate type in memory or in a | |
7968 | register? Return 0 if an aggregate type can be returned in a | |
7969 | register, 1 if it must be returned in memory. */ | |
7970 | ||
7971 | static int | |
7972 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
7973 | { | |
cca44b1b JB |
7974 | enum type_code code; |
7975 | ||
f168693b | 7976 | type = check_typedef (type); |
cca44b1b | 7977 | |
b13c8ab2 YQ |
7978 | /* Simple, non-aggregate types (ie not including vectors and |
7979 | complex) are always returned in a register (or registers). */ | |
78134374 | 7980 | code = type->code (); |
b13c8ab2 YQ |
7981 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
7982 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
7983 | return 0; | |
cca44b1b | 7984 | |
bd63c870 | 7985 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
7986 | { |
7987 | /* Vector values should be returned using ARM registers if they | |
7988 | are not over 16 bytes. */ | |
7989 | return (TYPE_LENGTH (type) > 16); | |
7990 | } | |
7991 | ||
b13c8ab2 | 7992 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
cca44b1b | 7993 | { |
b13c8ab2 YQ |
7994 | /* The AAPCS says all aggregates not larger than a word are returned |
7995 | in a register. */ | |
f0452268 | 7996 | if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE) |
b13c8ab2 YQ |
7997 | return 0; |
7998 | ||
cca44b1b JB |
7999 | return 1; |
8000 | } | |
b13c8ab2 YQ |
8001 | else |
8002 | { | |
8003 | int nRc; | |
cca44b1b | 8004 | |
b13c8ab2 YQ |
8005 | /* All aggregate types that won't fit in a register must be returned |
8006 | in memory. */ | |
f0452268 | 8007 | if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE) |
b13c8ab2 | 8008 | return 1; |
cca44b1b | 8009 | |
b13c8ab2 YQ |
8010 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8011 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8012 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8013 | offset of each addressable subfield must be zero. Note that bit |
8014 | fields are not addressable, and all addressable subfields of | |
8015 | unions always start at offset zero. | |
cca44b1b | 8016 | |
b13c8ab2 YQ |
8017 | This function is based on the behaviour of GCC 2.95.1. |
8018 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8019 | |
b13c8ab2 YQ |
8020 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8021 | parameters correctly for a function returning the following | |
8022 | structure: struct { float f;}; This should be returned in memory, | |
8023 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8024 | know of any way to detect if a function like the above has been | |
8025 | compiled with the correct calling convention. */ | |
8026 | ||
8027 | /* Assume all other aggregate types can be returned in a register. | |
8028 | Run a check for structures, unions and arrays. */ | |
8029 | nRc = 0; | |
67255d04 | 8030 | |
b13c8ab2 YQ |
8031 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8032 | { | |
8033 | int i; | |
8034 | /* Need to check if this struct/union is "integer" like. For | |
8035 | this to be true, its size must be less than or equal to | |
f0452268 | 8036 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8037 | subfield must be zero. Note that bit fields are not |
8038 | addressable, and unions always start at offset zero. If any | |
8039 | of the subfields is a floating point type, the struct/union | |
8040 | cannot be an integer type. */ | |
8041 | ||
8042 | /* For each field in the object, check: | |
8043 | 1) Is it FP? --> yes, nRc = 1; | |
8044 | 2) Is it addressable (bitpos != 0) and | |
8045 | not packed (bitsize == 0)? | |
8046 | --> yes, nRc = 1 | |
8047 | */ | |
8048 | ||
1f704f76 | 8049 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 8050 | { |
b13c8ab2 YQ |
8051 | enum type_code field_type_code; |
8052 | ||
8053 | field_type_code | |
940da03e | 8054 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
8055 | |
8056 | /* Is it a floating point type field? */ | |
8057 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
8058 | { |
8059 | nRc = 1; | |
8060 | break; | |
8061 | } | |
b13c8ab2 YQ |
8062 | |
8063 | /* If bitpos != 0, then we have to care about it. */ | |
8064 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
8065 | { | |
8066 | /* Bitfields are not addressable. If the field bitsize is | |
8067 | zero, then the field is not packed. Hence it cannot be | |
8068 | a bitfield or any other packed type. */ | |
8069 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
8070 | { | |
8071 | nRc = 1; | |
8072 | break; | |
8073 | } | |
8074 | } | |
67255d04 RE |
8075 | } |
8076 | } | |
67255d04 | 8077 | |
b13c8ab2 YQ |
8078 | return nRc; |
8079 | } | |
67255d04 RE |
8080 | } |
8081 | ||
34e8f22d RE |
8082 | /* Write into appropriate registers a function return value of type |
8083 | TYPE, given in virtual format. */ | |
8084 | ||
8085 | static void | |
b508a996 | 8086 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 8087 | const gdb_byte *valbuf) |
34e8f22d | 8088 | { |
ac7936df | 8089 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 8090 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 8091 | |
78134374 | 8092 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 8093 | { |
f0452268 | 8094 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
34e8f22d | 8095 | |
be8626e0 | 8096 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
8097 | { |
8098 | case ARM_FLOAT_FPA: | |
8099 | ||
3b2ca824 | 8100 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 8101 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
8102 | break; |
8103 | ||
fd50bc42 | 8104 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8105 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8106 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8107 | not using the VFP ABI code. */ | |
8108 | case ARM_FLOAT_VFP: | |
b66f5587 | 8109 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
b508a996 | 8110 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8111 | regs->cooked_write (ARM_A1_REGNUM + 1, |
8112 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
8113 | break; |
8114 | ||
8115 | default: | |
9b20d036 MS |
8116 | internal_error (__FILE__, __LINE__, |
8117 | _("arm_store_return_value: Floating " | |
8118 | "point model not supported")); | |
08216dd7 RE |
8119 | break; |
8120 | } | |
34e8f22d | 8121 | } |
78134374 SM |
8122 | else if (type->code () == TYPE_CODE_INT |
8123 | || type->code () == TYPE_CODE_CHAR | |
8124 | || type->code () == TYPE_CODE_BOOL | |
8125 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8126 | || TYPE_IS_REFERENCE (type) |
78134374 | 8127 | || type->code () == TYPE_CODE_ENUM) |
b508a996 RE |
8128 | { |
8129 | if (TYPE_LENGTH (type) <= 4) | |
8130 | { | |
8131 | /* Values of one word or less are zero/sign-extended and | |
8132 | returned in r0. */ | |
f0452268 | 8133 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8134 | LONGEST val = unpack_long (type, valbuf); |
8135 | ||
f0452268 | 8136 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 8137 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
8138 | } |
8139 | else | |
8140 | { | |
8141 | /* Integral values greater than one word are stored in consecutive | |
8142 | registers starting with r0. This will always be a multiple of | |
8143 | the regiser size. */ | |
8144 | int len = TYPE_LENGTH (type); | |
8145 | int regno = ARM_A1_REGNUM; | |
8146 | ||
8147 | while (len > 0) | |
8148 | { | |
b66f5587 | 8149 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
8150 | len -= ARM_INT_REGISTER_SIZE; |
8151 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8152 | } |
8153 | } | |
8154 | } | |
34e8f22d | 8155 | else |
b508a996 RE |
8156 | { |
8157 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8158 | been stored to word-aligned memory and then loaded into |
8159 | registers with 32-bit load instruction(s). */ | |
b508a996 RE |
8160 | int len = TYPE_LENGTH (type); |
8161 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8162 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8163 | |
8164 | while (len > 0) | |
8165 | { | |
8166 | memcpy (tmpbuf, valbuf, | |
f0452268 | 8167 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 8168 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
8169 | len -= ARM_INT_REGISTER_SIZE; |
8170 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8171 | } |
8172 | } | |
34e8f22d RE |
8173 | } |
8174 | ||
2af48f68 PB |
8175 | |
8176 | /* Handle function return values. */ | |
8177 | ||
8178 | static enum return_value_convention | |
6a3a010b | 8179 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
8180 | struct type *valtype, struct regcache *regcache, |
8181 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 8182 | { |
7c00367c | 8183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 8184 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
8185 | enum arm_vfp_cprc_base_type vfp_base_type; |
8186 | int vfp_base_count; | |
8187 | ||
8188 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
8189 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
8190 | { | |
8191 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
8192 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
8193 | int i; | |
8194 | for (i = 0; i < vfp_base_count; i++) | |
8195 | { | |
58d6951d DJ |
8196 | if (reg_char == 'q') |
8197 | { | |
8198 | if (writebuf) | |
8199 | arm_neon_quad_write (gdbarch, regcache, i, | |
8200 | writebuf + i * unit_length); | |
8201 | ||
8202 | if (readbuf) | |
8203 | arm_neon_quad_read (gdbarch, regcache, i, | |
8204 | readbuf + i * unit_length); | |
8205 | } | |
8206 | else | |
8207 | { | |
8208 | char name_buf[4]; | |
8209 | int regnum; | |
8210 | ||
8c042590 | 8211 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
8212 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8213 | strlen (name_buf)); | |
8214 | if (writebuf) | |
b66f5587 | 8215 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 8216 | if (readbuf) |
dca08e1f | 8217 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 8218 | } |
90445bd3 DJ |
8219 | } |
8220 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8221 | } | |
7c00367c | 8222 | |
78134374 SM |
8223 | if (valtype->code () == TYPE_CODE_STRUCT |
8224 | || valtype->code () == TYPE_CODE_UNION | |
8225 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 8226 | { |
7c00367c MK |
8227 | if (tdep->struct_return == pcc_struct_return |
8228 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
8229 | return RETURN_VALUE_STRUCT_CONVENTION; |
8230 | } | |
78134374 | 8231 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
8232 | { |
8233 | if (arm_return_in_memory (gdbarch, valtype)) | |
8234 | return RETURN_VALUE_STRUCT_CONVENTION; | |
8235 | } | |
7052e42c | 8236 | |
2af48f68 PB |
8237 | if (writebuf) |
8238 | arm_store_return_value (valtype, regcache, writebuf); | |
8239 | ||
8240 | if (readbuf) | |
8241 | arm_extract_return_value (valtype, regcache, readbuf); | |
8242 | ||
8243 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8244 | } | |
8245 | ||
8246 | ||
9df628e0 | 8247 | static int |
60ade65d | 8248 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 8249 | { |
e17a4113 UW |
8250 | struct gdbarch *gdbarch = get_frame_arch (frame); |
8251 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8252 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 8253 | CORE_ADDR jb_addr; |
f0452268 | 8254 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 8255 | |
60ade65d | 8256 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
8257 | |
8258 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 8259 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
8260 | return 0; |
8261 | ||
f0452268 | 8262 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
8263 | return 1; |
8264 | } | |
40eadf04 SP |
8265 | /* A call to cmse secure entry function "foo" at "a" is modified by |
8266 | GNU ld as "b". | |
8267 | a) bl xxxx <foo> | |
8268 | ||
8269 | <foo> | |
8270 | xxxx: | |
8271 | ||
8272 | b) bl yyyy <__acle_se_foo> | |
8273 | ||
8274 | section .gnu.sgstubs: | |
8275 | <foo> | |
8276 | yyyy: sg // secure gateway | |
8277 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
8278 | ||
8279 | <__acle_se_foo> | |
8280 | xxxx: | |
8281 | ||
8282 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
8283 | trampoline and does not exist in source code. This function returns the | |
8284 | target pc "xxxx". For more details please refer to section 5.4 | |
8285 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
8286 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
8287 | document on www.developer.arm.com. */ | |
8288 | ||
8289 | static CORE_ADDR | |
8290 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
8291 | { | |
8292 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
8293 | char *target_name = (char *) alloca (target_len); | |
8294 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
8295 | ||
8296 | struct bound_minimal_symbol minsym | |
8297 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
8298 | ||
8299 | if (minsym.minsym != nullptr) | |
8300 | return BMSYMBOL_VALUE_ADDRESS (minsym); | |
8301 | ||
8302 | return 0; | |
8303 | } | |
8304 | ||
8305 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
8306 | ||
8307 | static bool | |
8308 | arm_is_sgstubs_section (struct obj_section *sec) | |
8309 | { | |
8310 | return (sec != nullptr | |
8311 | && sec->the_bfd_section != nullptr | |
8312 | && sec->the_bfd_section->name != nullptr | |
8313 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
8314 | } | |
9df628e0 | 8315 | |
faa95490 DJ |
8316 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
8317 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
8318 | |
8319 | CORE_ADDR | |
52f729a7 | 8320 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 8321 | { |
2c02bd72 | 8322 | const char *name; |
faa95490 | 8323 | int namelen; |
c906108c SS |
8324 | CORE_ADDR start_addr; |
8325 | ||
8326 | /* Find the starting address and name of the function containing the PC. */ | |
8327 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
8328 | { |
8329 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
8330 | check here. */ | |
8331 | start_addr = arm_skip_bx_reg (frame, pc); | |
8332 | if (start_addr != 0) | |
8333 | return start_addr; | |
8334 | ||
8335 | return 0; | |
8336 | } | |
c906108c | 8337 | |
faa95490 DJ |
8338 | /* If PC is in a Thumb call or return stub, return the address of the |
8339 | target PC, which is in a register. The thunk functions are called | |
8340 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
8341 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
8342 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
8343 | if (startswith (name, "_call_via_") |
8344 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 8345 | { |
ed9a39eb | 8346 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 8347 | target PC. */ |
a121b7c1 | 8348 | static const char *table[15] = |
c5aa993b JM |
8349 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
8350 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
8351 | }; | |
c906108c | 8352 | int regno; |
faa95490 | 8353 | int offset = strlen (name) - 2; |
c906108c SS |
8354 | |
8355 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 8356 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 8357 | return get_frame_register_unsigned (frame, regno); |
c906108c | 8358 | } |
ed9a39eb | 8359 | |
faa95490 DJ |
8360 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
8361 | non-interworking calls to foo. We could decode the stubs | |
8362 | to find the target but it's easier to use the symbol table. */ | |
8363 | namelen = strlen (name); | |
8364 | if (name[0] == '_' && name[1] == '_' | |
8365 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 8366 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 8367 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 8368 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
8369 | { |
8370 | char *target_name; | |
8371 | int target_len = namelen - 2; | |
3b7344d5 | 8372 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
8373 | struct objfile *objfile; |
8374 | struct obj_section *sec; | |
8375 | ||
8376 | if (name[namelen - 1] == 'b') | |
8377 | target_len -= strlen ("_from_thumb"); | |
8378 | else | |
8379 | target_len -= strlen ("_from_arm"); | |
8380 | ||
224c3ddb | 8381 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
8382 | memcpy (target_name, name + 2, target_len); |
8383 | target_name[target_len] = '\0'; | |
8384 | ||
8385 | sec = find_pc_section (pc); | |
8386 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
8387 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 8388 | if (minsym.minsym != NULL) |
77e371c0 | 8389 | return BMSYMBOL_VALUE_ADDRESS (minsym); |
faa95490 DJ |
8390 | else |
8391 | return 0; | |
8392 | } | |
8393 | ||
40eadf04 SP |
8394 | struct obj_section *section = find_pc_section (pc); |
8395 | ||
8396 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
8397 | if (arm_is_sgstubs_section (section)) | |
8398 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
8399 | ||
c5aa993b | 8400 | return 0; /* not a stub */ |
c906108c SS |
8401 | } |
8402 | ||
28e97307 DJ |
8403 | static void |
8404 | arm_update_current_architecture (void) | |
fd50bc42 | 8405 | { |
28e97307 | 8406 | struct gdbarch_info info; |
fd50bc42 | 8407 | |
28e97307 | 8408 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 8409 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 8410 | return; |
fd50bc42 | 8411 | |
28e97307 DJ |
8412 | /* Update the architecture. */ |
8413 | gdbarch_info_init (&info); | |
fd50bc42 | 8414 | |
28e97307 | 8415 | if (!gdbarch_update_p (info)) |
9b20d036 | 8416 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
8417 | } |
8418 | ||
8419 | static void | |
eb4c3f4a | 8420 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
8421 | struct cmd_list_element *c) |
8422 | { | |
570dc176 | 8423 | int fp_model; |
fd50bc42 RE |
8424 | |
8425 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
8426 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
8427 | { | |
aead7601 | 8428 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
8429 | break; |
8430 | } | |
8431 | ||
8432 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 8433 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
8434 | current_fp_model); |
8435 | ||
28e97307 | 8436 | arm_update_current_architecture (); |
fd50bc42 RE |
8437 | } |
8438 | ||
8439 | static void | |
08546159 AC |
8440 | show_fp_model (struct ui_file *file, int from_tty, |
8441 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 8442 | { |
f5656ead | 8443 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
fd50bc42 | 8444 | |
28e97307 | 8445 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 8446 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8447 | fprintf_filtered (file, _("\ |
8448 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
8449 | fp_model_strings[tdep->fp_model]); | |
8450 | else | |
8451 | fprintf_filtered (file, _("\ | |
8452 | The current ARM floating point model is \"%s\".\n"), | |
8453 | fp_model_strings[arm_fp_model]); | |
8454 | } | |
8455 | ||
8456 | static void | |
eb4c3f4a | 8457 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
8458 | struct cmd_list_element *c) |
8459 | { | |
570dc176 | 8460 | int arm_abi; |
28e97307 DJ |
8461 | |
8462 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
8463 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
8464 | { | |
aead7601 | 8465 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
8466 | break; |
8467 | } | |
8468 | ||
8469 | if (arm_abi == ARM_ABI_LAST) | |
8470 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
8471 | arm_abi_string); | |
8472 | ||
8473 | arm_update_current_architecture (); | |
8474 | } | |
8475 | ||
8476 | static void | |
8477 | arm_show_abi (struct ui_file *file, int from_tty, | |
8478 | struct cmd_list_element *c, const char *value) | |
8479 | { | |
f5656ead | 8480 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
28e97307 DJ |
8481 | |
8482 | if (arm_abi_global == ARM_ABI_AUTO | |
f5656ead | 8483 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
28e97307 DJ |
8484 | fprintf_filtered (file, _("\ |
8485 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
8486 | arm_abi_strings[tdep->arm_abi]); | |
8487 | else | |
8488 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
8489 | arm_abi_string); | |
fd50bc42 RE |
8490 | } |
8491 | ||
0428b8f5 DJ |
8492 | static void |
8493 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
8494 | struct cmd_list_element *c, const char *value) | |
8495 | { | |
0963b4bd MS |
8496 | fprintf_filtered (file, |
8497 | _("The current execution mode assumed " | |
8498 | "(when symbols are unavailable) is \"%s\".\n"), | |
0428b8f5 DJ |
8499 | arm_fallback_mode_string); |
8500 | } | |
8501 | ||
8502 | static void | |
8503 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
8504 | struct cmd_list_element *c, const char *value) | |
8505 | { | |
0963b4bd MS |
8506 | fprintf_filtered (file, |
8507 | _("The current execution mode assumed " | |
8508 | "(even when symbols are available) is \"%s\".\n"), | |
0428b8f5 DJ |
8509 | arm_force_mode_string); |
8510 | } | |
8511 | ||
afd7eef0 RE |
8512 | /* If the user changes the register disassembly style used for info |
8513 | register and other commands, we have to also switch the style used | |
8514 | in opcodes for disassembly output. This function is run in the "set | |
8515 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
8516 | |
8517 | static void | |
eb4c3f4a | 8518 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 8519 | struct cmd_list_element *c) |
bc90b915 | 8520 | { |
65b48a81 PB |
8521 | /* Convert the short style name into the long style name (eg, reg-names-*) |
8522 | before calling the generic set_disassembler_options() function. */ | |
8523 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
8524 | set_disassembler_options (&long_name[0]); | |
8525 | } | |
8526 | ||
8527 | static void | |
8528 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
8529 | struct cmd_list_element *c, const char *value) | |
8530 | { | |
8531 | struct gdbarch *gdbarch = get_current_arch (); | |
8532 | char *options = get_disassembler_options (gdbarch); | |
8533 | const char *style = ""; | |
8534 | int len = 0; | |
f995bbe8 | 8535 | const char *opt; |
65b48a81 PB |
8536 | |
8537 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
8538 | if (CONST_STRNEQ (opt, "reg-names-")) | |
8539 | { | |
8540 | style = &opt[strlen ("reg-names-")]; | |
8541 | len = strcspn (style, ","); | |
8542 | } | |
8543 | ||
8544 | fprintf_unfiltered (file, "The disassembly style is \"%.*s\".\n", len, style); | |
bc90b915 FN |
8545 | } |
8546 | \f | |
966fbf70 | 8547 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 8548 | static const char * |
d93859e2 | 8549 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 8550 | { |
58d6951d DJ |
8551 | const int num_regs = gdbarch_num_regs (gdbarch); |
8552 | ||
8553 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
8554 | && i >= num_regs && i < num_regs + 32) | |
8555 | { | |
8556 | static const char *const vfp_pseudo_names[] = { | |
8557 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
8558 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
8559 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
8560 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
8561 | }; | |
8562 | ||
8563 | return vfp_pseudo_names[i - num_regs]; | |
8564 | } | |
8565 | ||
8566 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
8567 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
8568 | { | |
8569 | static const char *const neon_pseudo_names[] = { | |
8570 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
8571 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
8572 | }; | |
8573 | ||
8574 | return neon_pseudo_names[i - num_regs - 32]; | |
8575 | } | |
8576 | ||
ff6f572f DJ |
8577 | if (i >= ARRAY_SIZE (arm_register_names)) |
8578 | /* These registers are only supported on targets which supply | |
8579 | an XML description. */ | |
8580 | return ""; | |
8581 | ||
966fbf70 RE |
8582 | return arm_register_names[i]; |
8583 | } | |
8584 | ||
082fc60d RE |
8585 | /* Test whether the coff symbol specific value corresponds to a Thumb |
8586 | function. */ | |
8587 | ||
8588 | static int | |
8589 | coff_sym_is_thumb (int val) | |
8590 | { | |
f8bf5763 PM |
8591 | return (val == C_THUMBEXT |
8592 | || val == C_THUMBSTAT | |
8593 | || val == C_THUMBEXTFUNC | |
8594 | || val == C_THUMBSTATFUNC | |
8595 | || val == C_THUMBLABEL); | |
082fc60d RE |
8596 | } |
8597 | ||
8598 | /* arm_coff_make_msymbol_special() | |
8599 | arm_elf_make_msymbol_special() | |
8600 | ||
8601 | These functions test whether the COFF or ELF symbol corresponds to | |
8602 | an address in thumb code, and set a "special" bit in a minimal | |
8603 | symbol to indicate that it does. */ | |
8604 | ||
34e8f22d | 8605 | static void |
082fc60d RE |
8606 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
8607 | { | |
39d911fc TP |
8608 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
8609 | ||
8610 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 8611 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
8612 | MSYMBOL_SET_SPECIAL (msym); |
8613 | } | |
8614 | ||
34e8f22d | 8615 | static void |
082fc60d RE |
8616 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
8617 | { | |
8618 | if (coff_sym_is_thumb (val)) | |
8619 | MSYMBOL_SET_SPECIAL (msym); | |
8620 | } | |
8621 | ||
60c5725c DJ |
8622 | static void |
8623 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
8624 | asymbol *sym) | |
8625 | { | |
8626 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 8627 | struct arm_per_bfd *data; |
60c5725c DJ |
8628 | struct arm_mapping_symbol new_map_sym; |
8629 | ||
8630 | gdb_assert (name[0] == '$'); | |
8631 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
8632 | return; | |
8633 | ||
bd5766ec | 8634 | data = arm_bfd_data_key.get (objfile->obfd); |
60c5725c | 8635 | if (data == NULL) |
bd5766ec LM |
8636 | data = arm_bfd_data_key.emplace (objfile->obfd, |
8637 | objfile->obfd->section_count); | |
54cc7474 | 8638 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 8639 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
8640 | |
8641 | new_map_sym.value = sym->value; | |
8642 | new_map_sym.type = name[1]; | |
8643 | ||
4838e44c SM |
8644 | /* Insert at the end, the vector will be sorted on first use. */ |
8645 | map.push_back (new_map_sym); | |
60c5725c DJ |
8646 | } |
8647 | ||
756fe439 | 8648 | static void |
61a1198a | 8649 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 8650 | { |
ac7936df | 8651 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 8652 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
8653 | |
8654 | /* If necessary, set the T bit. */ | |
8655 | if (arm_apcs_32) | |
8656 | { | |
9779414d | 8657 | ULONGEST val, t_bit; |
61a1198a | 8658 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
8659 | t_bit = arm_psr_thumb_bit (gdbarch); |
8660 | if (arm_pc_is_thumb (gdbarch, pc)) | |
8661 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
8662 | val | t_bit); | |
756fe439 | 8663 | else |
61a1198a | 8664 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 8665 | val & ~t_bit); |
756fe439 DJ |
8666 | } |
8667 | } | |
123dc839 | 8668 | |
58d6951d DJ |
8669 | /* Read the contents of a NEON quad register, by reading from two |
8670 | double registers. This is used to implement the quad pseudo | |
8671 | registers, and for argument passing in case the quad registers are | |
8672 | missing; vectors are passed in quad registers when using the VFP | |
8673 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
8674 | the quad register, in [0, 15]. */ | |
8675 | ||
05d1431c | 8676 | static enum register_status |
849d0ba8 | 8677 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8678 | int regnum, gdb_byte *buf) |
8679 | { | |
8680 | char name_buf[4]; | |
8681 | gdb_byte reg_buf[8]; | |
8682 | int offset, double_regnum; | |
05d1431c | 8683 | enum register_status status; |
58d6951d | 8684 | |
8c042590 | 8685 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8686 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8687 | strlen (name_buf)); | |
8688 | ||
8689 | /* d0 is always the least significant half of q0. */ | |
8690 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8691 | offset = 8; | |
8692 | else | |
8693 | offset = 0; | |
8694 | ||
03f50fc8 | 8695 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
8696 | if (status != REG_VALID) |
8697 | return status; | |
58d6951d DJ |
8698 | memcpy (buf + offset, reg_buf, 8); |
8699 | ||
8700 | offset = 8 - offset; | |
03f50fc8 | 8701 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
8702 | if (status != REG_VALID) |
8703 | return status; | |
58d6951d | 8704 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
8705 | |
8706 | return REG_VALID; | |
58d6951d DJ |
8707 | } |
8708 | ||
05d1431c | 8709 | static enum register_status |
849d0ba8 | 8710 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8711 | int regnum, gdb_byte *buf) |
8712 | { | |
8713 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8714 | char name_buf[4]; | |
8715 | gdb_byte reg_buf[8]; | |
8716 | int offset, double_regnum; | |
8717 | ||
8718 | gdb_assert (regnum >= num_regs); | |
8719 | regnum -= num_regs; | |
8720 | ||
8721 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8722 | /* Quad-precision register. */ | |
05d1431c | 8723 | return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); |
58d6951d DJ |
8724 | else |
8725 | { | |
05d1431c PA |
8726 | enum register_status status; |
8727 | ||
58d6951d DJ |
8728 | /* Single-precision register. */ |
8729 | gdb_assert (regnum < 32); | |
8730 | ||
8731 | /* s0 is always the least significant half of d0. */ | |
8732 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8733 | offset = (regnum & 1) ? 0 : 4; | |
8734 | else | |
8735 | offset = (regnum & 1) ? 4 : 0; | |
8736 | ||
8c042590 | 8737 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8738 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8739 | strlen (name_buf)); | |
8740 | ||
03f50fc8 | 8741 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
8742 | if (status == REG_VALID) |
8743 | memcpy (buf, reg_buf + offset, 4); | |
8744 | return status; | |
58d6951d DJ |
8745 | } |
8746 | } | |
8747 | ||
8748 | /* Store the contents of BUF to a NEON quad register, by writing to | |
8749 | two double registers. This is used to implement the quad pseudo | |
8750 | registers, and for argument passing in case the quad registers are | |
8751 | missing; vectors are passed in quad registers when using the VFP | |
8752 | ABI, even if a NEON unit is not present. REGNUM is the index | |
8753 | of the quad register, in [0, 15]. */ | |
8754 | ||
8755 | static void | |
8756 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8757 | int regnum, const gdb_byte *buf) | |
8758 | { | |
8759 | char name_buf[4]; | |
58d6951d DJ |
8760 | int offset, double_regnum; |
8761 | ||
8c042590 | 8762 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8763 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8764 | strlen (name_buf)); | |
8765 | ||
8766 | /* d0 is always the least significant half of q0. */ | |
8767 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8768 | offset = 8; | |
8769 | else | |
8770 | offset = 0; | |
8771 | ||
10eaee5f | 8772 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 8773 | offset = 8 - offset; |
10eaee5f | 8774 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
8775 | } |
8776 | ||
8777 | static void | |
8778 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
8779 | int regnum, const gdb_byte *buf) | |
8780 | { | |
8781 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8782 | char name_buf[4]; | |
8783 | gdb_byte reg_buf[8]; | |
8784 | int offset, double_regnum; | |
8785 | ||
8786 | gdb_assert (regnum >= num_regs); | |
8787 | regnum -= num_regs; | |
8788 | ||
8789 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
8790 | /* Quad-precision register. */ | |
8791 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
8792 | else | |
8793 | { | |
8794 | /* Single-precision register. */ | |
8795 | gdb_assert (regnum < 32); | |
8796 | ||
8797 | /* s0 is always the least significant half of d0. */ | |
8798 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8799 | offset = (regnum & 1) ? 0 : 4; | |
8800 | else | |
8801 | offset = (regnum & 1) ? 4 : 0; | |
8802 | ||
8c042590 | 8803 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
8804 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8805 | strlen (name_buf)); | |
8806 | ||
0b883586 | 8807 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 8808 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 8809 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
8810 | } |
8811 | } | |
8812 | ||
123dc839 DJ |
8813 | static struct value * |
8814 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
8815 | { | |
9a3c8263 | 8816 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
8817 | return value_of_register (*reg_p, frame); |
8818 | } | |
97e03143 | 8819 | \f |
70f80edf JT |
8820 | static enum gdb_osabi |
8821 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 8822 | { |
2af48f68 | 8823 | unsigned int elfosabi; |
70f80edf | 8824 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 8825 | |
70f80edf | 8826 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 8827 | |
28e97307 DJ |
8828 | if (elfosabi == ELFOSABI_ARM) |
8829 | /* GNU tools use this value. Check note sections in this case, | |
8830 | as well. */ | |
b35c1d1c TT |
8831 | { |
8832 | for (asection *sect : gdb_bfd_sections (abfd)) | |
8833 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
8834 | } | |
97e03143 | 8835 | |
28e97307 | 8836 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 8837 | return osabi; |
97e03143 RE |
8838 | } |
8839 | ||
54483882 YQ |
8840 | static int |
8841 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
8842 | struct reggroup *group) | |
8843 | { | |
2c291032 YQ |
8844 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
8845 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
8846 | all_reggroup, of course. */ | |
54483882 | 8847 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
8848 | return (group == float_reggroup |
8849 | || group == save_reggroup | |
8850 | || group == restore_reggroup | |
8851 | || group == all_reggroup); | |
54483882 YQ |
8852 | else |
8853 | return default_register_reggroup_p (gdbarch, regnum, group); | |
8854 | } | |
8855 | ||
25f8c692 JL |
8856 | /* For backward-compatibility we allow two 'g' packet lengths with |
8857 | the remote protocol depending on whether FPA registers are | |
8858 | supplied. M-profile targets do not have FPA registers, but some | |
8859 | stubs already exist in the wild which use a 'g' packet which | |
8860 | supplies them albeit with dummy values. The packet format which | |
8861 | includes FPA registers should be considered deprecated for | |
8862 | M-profile targets. */ | |
8863 | ||
8864 | static void | |
8865 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8866 | { | |
8867 | if (gdbarch_tdep (gdbarch)->is_m) | |
8868 | { | |
d105cce5 AH |
8869 | const target_desc *tdesc; |
8870 | ||
25f8c692 JL |
8871 | /* If we know from the executable this is an M-profile target, |
8872 | cater for remote targets whose register set layout is the | |
8873 | same as the FPA layout. */ | |
d105cce5 | 8874 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 8875 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 8876 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 8877 | tdesc); |
25f8c692 JL |
8878 | |
8879 | /* The regular M-profile layout. */ | |
d105cce5 | 8880 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 8881 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 8882 | tdesc); |
3184d3f9 JL |
8883 | |
8884 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 8885 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 8886 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 8887 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 8888 | tdesc); |
25f8c692 JL |
8889 | } |
8890 | ||
8891 | /* Otherwise we don't have a useful guess. */ | |
8892 | } | |
8893 | ||
7eb89530 YQ |
8894 | /* Implement the code_of_frame_writable gdbarch method. */ |
8895 | ||
8896 | static int | |
8897 | arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame) | |
8898 | { | |
8899 | if (gdbarch_tdep (gdbarch)->is_m | |
8900 | && get_frame_type (frame) == SIGTRAMP_FRAME) | |
8901 | { | |
8902 | /* M-profile exception frames return to some magic PCs, where | |
8903 | isn't writable at all. */ | |
8904 | return 0; | |
8905 | } | |
8906 | else | |
8907 | return 1; | |
8908 | } | |
8909 | ||
3426ae57 AH |
8910 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
8911 | to be postfixed by a version (eg armv7hl). */ | |
8912 | ||
8913 | static const char * | |
8914 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
8915 | { | |
8916 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
8917 | return "arm(v[^- ]*)?"; | |
8918 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
8919 | } | |
8920 | ||
da3c6d4a MS |
8921 | /* Initialize the current architecture based on INFO. If possible, |
8922 | re-use an architecture from ARCHES, which is a list of | |
8923 | architectures already created during this debugging session. | |
97e03143 | 8924 | |
da3c6d4a MS |
8925 | Called e.g. at program startup, when reading a core file, and when |
8926 | reading a binary file. */ | |
97e03143 | 8927 | |
39bbf761 RE |
8928 | static struct gdbarch * |
8929 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8930 | { | |
97e03143 | 8931 | struct gdbarch_tdep *tdep; |
39bbf761 | 8932 | struct gdbarch *gdbarch; |
28e97307 DJ |
8933 | struct gdbarch_list *best_arch; |
8934 | enum arm_abi_kind arm_abi = arm_abi_global; | |
8935 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 8936 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
8937 | int i; |
8938 | bool is_m = false; | |
8939 | int vfp_register_count = 0; | |
8940 | bool have_vfp_pseudos = false, have_neon_pseudos = false; | |
8941 | bool have_wmmx_registers = false; | |
8942 | bool have_neon = false; | |
8943 | bool have_fpa_registers = true; | |
9779414d DJ |
8944 | const struct target_desc *tdesc = info.target_desc; |
8945 | ||
8946 | /* If we have an object to base this architecture on, try to determine | |
8947 | its ABI. */ | |
8948 | ||
8949 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
8950 | { | |
8951 | int ei_osabi, e_flags; | |
8952 | ||
8953 | switch (bfd_get_flavour (info.abfd)) | |
8954 | { | |
9779414d DJ |
8955 | case bfd_target_coff_flavour: |
8956 | /* Assume it's an old APCS-style ABI. */ | |
8957 | /* XXX WinCE? */ | |
8958 | arm_abi = ARM_ABI_APCS; | |
8959 | break; | |
8960 | ||
8961 | case bfd_target_elf_flavour: | |
8962 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
8963 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
8964 | ||
8965 | if (ei_osabi == ELFOSABI_ARM) | |
8966 | { | |
8967 | /* GNU tools used to use this value, but do not for EABI | |
8968 | objects. There's nowhere to tag an EABI version | |
8969 | anyway, so assume APCS. */ | |
8970 | arm_abi = ARM_ABI_APCS; | |
8971 | } | |
d403db27 | 8972 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
8973 | { |
8974 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
8975 | |
8976 | switch (eabi_ver) | |
8977 | { | |
8978 | case EF_ARM_EABI_UNKNOWN: | |
8979 | /* Assume GNU tools. */ | |
8980 | arm_abi = ARM_ABI_APCS; | |
8981 | break; | |
8982 | ||
8983 | case EF_ARM_EABI_VER4: | |
8984 | case EF_ARM_EABI_VER5: | |
8985 | arm_abi = ARM_ABI_AAPCS; | |
8986 | /* EABI binaries default to VFP float ordering. | |
8987 | They may also contain build attributes that can | |
8988 | be used to identify if the VFP argument-passing | |
8989 | ABI is in use. */ | |
8990 | if (fp_model == ARM_FLOAT_AUTO) | |
8991 | { | |
8992 | #ifdef HAVE_ELF | |
8993 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
8994 | OBJ_ATTR_PROC, | |
8995 | Tag_ABI_VFP_args)) | |
8996 | { | |
b35b0298 | 8997 | case AEABI_VFP_args_base: |
9779414d DJ |
8998 | /* "The user intended FP parameter/result |
8999 | passing to conform to AAPCS, base | |
9000 | variant". */ | |
9001 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9002 | break; | |
b35b0298 | 9003 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9004 | /* "The user intended FP parameter/result |
9005 | passing to conform to AAPCS, VFP | |
9006 | variant". */ | |
9007 | fp_model = ARM_FLOAT_VFP; | |
9008 | break; | |
b35b0298 | 9009 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9010 | /* "The user intended FP parameter/result |
9011 | passing to conform to tool chain-specific | |
9012 | conventions" - we don't know any such | |
9013 | conventions, so leave it as "auto". */ | |
9014 | break; | |
b35b0298 | 9015 | case AEABI_VFP_args_compatible: |
5c294fee TG |
9016 | /* "Code is compatible with both the base |
9017 | and VFP variants; the user did not permit | |
9018 | non-variadic functions to pass FP | |
9019 | parameters/results" - leave it as | |
9020 | "auto". */ | |
9021 | break; | |
9779414d DJ |
9022 | default: |
9023 | /* Attribute value not mentioned in the | |
5c294fee | 9024 | November 2012 ABI, so leave it as |
9779414d DJ |
9025 | "auto". */ |
9026 | break; | |
9027 | } | |
9028 | #else | |
9029 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9030 | #endif | |
9031 | } | |
9032 | break; | |
9033 | ||
9034 | default: | |
9035 | /* Leave it as "auto". */ | |
9036 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
9037 | break; | |
9038 | } | |
9039 | ||
9040 | #ifdef HAVE_ELF | |
9041 | /* Detect M-profile programs. This only works if the | |
9042 | executable file includes build attributes; GCC does | |
9043 | copy them to the executable, but e.g. RealView does | |
9044 | not. */ | |
17cbafdb SM |
9045 | int attr_arch |
9046 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9047 | Tag_CPU_arch); | |
9048 | int attr_profile | |
9049 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9050 | Tag_CPU_arch_profile); | |
9051 | ||
9779414d DJ |
9052 | /* GCC specifies the profile for v6-M; RealView only |
9053 | specifies the profile for architectures starting with | |
9054 | V7 (as opposed to architectures with a tag | |
9055 | numerically greater than TAG_CPU_ARCH_V7). */ | |
9056 | if (!tdesc_has_registers (tdesc) | |
9057 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
9058 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
9059 | || attr_profile == 'M')) | |
7559c217 | 9060 | is_m = true; |
9779414d DJ |
9061 | #endif |
9062 | } | |
9063 | ||
9064 | if (fp_model == ARM_FLOAT_AUTO) | |
9065 | { | |
9779414d DJ |
9066 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
9067 | { | |
9068 | case 0: | |
9069 | /* Leave it as "auto". Strictly speaking this case | |
9070 | means FPA, but almost nobody uses that now, and | |
9071 | many toolchains fail to set the appropriate bits | |
9072 | for the floating-point model they use. */ | |
9073 | break; | |
9074 | case EF_ARM_SOFT_FLOAT: | |
9075 | fp_model = ARM_FLOAT_SOFT_FPA; | |
9076 | break; | |
9077 | case EF_ARM_VFP_FLOAT: | |
9078 | fp_model = ARM_FLOAT_VFP; | |
9079 | break; | |
9080 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
9081 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9082 | break; | |
9083 | } | |
9084 | } | |
9085 | ||
9086 | if (e_flags & EF_ARM_BE8) | |
9087 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
9088 | ||
9089 | break; | |
9090 | ||
9091 | default: | |
9092 | /* Leave it as "auto". */ | |
9093 | break; | |
9094 | } | |
9095 | } | |
123dc839 DJ |
9096 | |
9097 | /* Check any target description for validity. */ | |
9779414d | 9098 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
9099 | { |
9100 | /* For most registers we require GDB's default names; but also allow | |
9101 | the numeric names for sp / lr / pc, as a convenience. */ | |
9102 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
9103 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
9104 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
9105 | ||
9106 | const struct tdesc_feature *feature; | |
58d6951d | 9107 | int valid_p; |
123dc839 | 9108 | |
9779414d | 9109 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9110 | "org.gnu.gdb.arm.core"); |
9111 | if (feature == NULL) | |
9779414d DJ |
9112 | { |
9113 | feature = tdesc_find_feature (tdesc, | |
9114 | "org.gnu.gdb.arm.m-profile"); | |
9115 | if (feature == NULL) | |
9116 | return NULL; | |
9117 | else | |
7559c217 | 9118 | is_m = true; |
9779414d | 9119 | } |
123dc839 DJ |
9120 | |
9121 | tdesc_data = tdesc_data_alloc (); | |
9122 | ||
9123 | valid_p = 1; | |
9124 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 9125 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 9126 | arm_register_names[i]); |
c1e1314d | 9127 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9128 | ARM_SP_REGNUM, |
9129 | arm_sp_names); | |
c1e1314d | 9130 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9131 | ARM_LR_REGNUM, |
9132 | arm_lr_names); | |
c1e1314d | 9133 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9134 | ARM_PC_REGNUM, |
9135 | arm_pc_names); | |
9779414d | 9136 | if (is_m) |
c1e1314d | 9137 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
9138 | ARM_PS_REGNUM, "xpsr"); |
9139 | else | |
c1e1314d | 9140 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 9141 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
9142 | |
9143 | if (!valid_p) | |
c1e1314d | 9144 | return NULL; |
123dc839 | 9145 | |
9779414d | 9146 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9147 | "org.gnu.gdb.arm.fpa"); |
9148 | if (feature != NULL) | |
9149 | { | |
9150 | valid_p = 1; | |
9151 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 9152 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
9153 | arm_register_names[i]); |
9154 | if (!valid_p) | |
c1e1314d | 9155 | return NULL; |
123dc839 | 9156 | } |
ff6f572f | 9157 | else |
7559c217 | 9158 | have_fpa_registers = false; |
ff6f572f | 9159 | |
9779414d | 9160 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
9161 | "org.gnu.gdb.xscale.iwmmxt"); |
9162 | if (feature != NULL) | |
9163 | { | |
9164 | static const char *const iwmmxt_names[] = { | |
9165 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
9166 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
9167 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
9168 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
9169 | }; | |
9170 | ||
9171 | valid_p = 1; | |
9172 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
9173 | valid_p | |
c1e1314d | 9174 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9175 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9176 | ||
9177 | /* Check for the control registers, but do not fail if they | |
9178 | are missing. */ | |
9179 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 9180 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9181 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9182 | ||
9183 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
9184 | valid_p | |
c1e1314d | 9185 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9186 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9187 | ||
9188 | if (!valid_p) | |
c1e1314d | 9189 | return NULL; |
a56cc1ce | 9190 | |
7559c217 | 9191 | have_wmmx_registers = true; |
ff6f572f | 9192 | } |
58d6951d DJ |
9193 | |
9194 | /* If we have a VFP unit, check whether the single precision registers | |
9195 | are present. If not, then we will synthesize them as pseudo | |
9196 | registers. */ | |
9779414d | 9197 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9198 | "org.gnu.gdb.arm.vfp"); |
9199 | if (feature != NULL) | |
9200 | { | |
9201 | static const char *const vfp_double_names[] = { | |
9202 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
9203 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
9204 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
9205 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
9206 | }; | |
9207 | ||
9208 | /* Require the double precision registers. There must be either | |
9209 | 16 or 32. */ | |
9210 | valid_p = 1; | |
9211 | for (i = 0; i < 32; i++) | |
9212 | { | |
c1e1314d | 9213 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
9214 | ARM_D0_REGNUM + i, |
9215 | vfp_double_names[i]); | |
9216 | if (!valid_p) | |
9217 | break; | |
9218 | } | |
2b9e5ea6 UW |
9219 | if (!valid_p && i == 16) |
9220 | valid_p = 1; | |
58d6951d | 9221 | |
2b9e5ea6 | 9222 | /* Also require FPSCR. */ |
c1e1314d | 9223 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
9224 | ARM_FPSCR_REGNUM, "fpscr"); |
9225 | if (!valid_p) | |
c1e1314d | 9226 | return NULL; |
58d6951d DJ |
9227 | |
9228 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
7559c217 | 9229 | have_vfp_pseudos = true; |
58d6951d | 9230 | |
330c6ca9 | 9231 | vfp_register_count = i; |
58d6951d DJ |
9232 | |
9233 | /* If we have VFP, also check for NEON. The architecture allows | |
9234 | NEON without VFP (integer vector operations only), but GDB | |
9235 | does not support that. */ | |
9779414d | 9236 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9237 | "org.gnu.gdb.arm.neon"); |
9238 | if (feature != NULL) | |
9239 | { | |
9240 | /* NEON requires 32 double-precision registers. */ | |
9241 | if (i != 32) | |
c1e1314d | 9242 | return NULL; |
58d6951d DJ |
9243 | |
9244 | /* If there are quad registers defined by the stub, use | |
9245 | their type; otherwise (normally) provide them with | |
9246 | the default type. */ | |
9247 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
7559c217 | 9248 | have_neon_pseudos = true; |
58d6951d | 9249 | |
7559c217 | 9250 | have_neon = true; |
58d6951d DJ |
9251 | } |
9252 | } | |
123dc839 | 9253 | } |
39bbf761 | 9254 | |
28e97307 DJ |
9255 | /* If there is already a candidate, use it. */ |
9256 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
9257 | best_arch != NULL; | |
9258 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
9259 | { | |
b8926edc DJ |
9260 | if (arm_abi != ARM_ABI_AUTO |
9261 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
9262 | continue; |
9263 | ||
b8926edc DJ |
9264 | if (fp_model != ARM_FLOAT_AUTO |
9265 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
9266 | continue; |
9267 | ||
58d6951d DJ |
9268 | /* There are various other properties in tdep that we do not |
9269 | need to check here: those derived from a target description, | |
9270 | since gdbarches with a different target description are | |
9271 | automatically disqualified. */ | |
9272 | ||
9779414d DJ |
9273 | /* Do check is_m, though, since it might come from the binary. */ |
9274 | if (is_m != gdbarch_tdep (best_arch->gdbarch)->is_m) | |
9275 | continue; | |
9276 | ||
28e97307 DJ |
9277 | /* Found a match. */ |
9278 | break; | |
9279 | } | |
97e03143 | 9280 | |
28e97307 | 9281 | if (best_arch != NULL) |
c1e1314d | 9282 | return best_arch->gdbarch; |
28e97307 | 9283 | |
8d749320 | 9284 | tdep = XCNEW (struct gdbarch_tdep); |
97e03143 RE |
9285 | gdbarch = gdbarch_alloc (&info, tdep); |
9286 | ||
28e97307 DJ |
9287 | /* Record additional information about the architecture we are defining. |
9288 | These are gdbarch discriminators, like the OSABI. */ | |
9289 | tdep->arm_abi = arm_abi; | |
9290 | tdep->fp_model = fp_model; | |
9779414d | 9291 | tdep->is_m = is_m; |
ff6f572f | 9292 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 9293 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
9294 | gdb_assert (vfp_register_count == 0 |
9295 | || vfp_register_count == 16 | |
9296 | || vfp_register_count == 32); | |
9297 | tdep->vfp_register_count = vfp_register_count; | |
58d6951d DJ |
9298 | tdep->have_vfp_pseudos = have_vfp_pseudos; |
9299 | tdep->have_neon_pseudos = have_neon_pseudos; | |
9300 | tdep->have_neon = have_neon; | |
08216dd7 | 9301 | |
25f8c692 JL |
9302 | arm_register_g_packet_guesses (gdbarch); |
9303 | ||
08216dd7 | 9304 | /* Breakpoints. */ |
9d4fde75 | 9305 | switch (info.byte_order_for_code) |
67255d04 RE |
9306 | { |
9307 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
9308 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
9309 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
9310 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
9311 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
9312 | ||
67255d04 RE |
9313 | break; |
9314 | ||
9315 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
9316 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
9317 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
9318 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
9319 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
9320 | ||
67255d04 RE |
9321 | break; |
9322 | ||
9323 | default: | |
9324 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 9325 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
9326 | } |
9327 | ||
d7b486e7 RE |
9328 | /* On ARM targets char defaults to unsigned. */ |
9329 | set_gdbarch_char_signed (gdbarch, 0); | |
9330 | ||
53375380 PA |
9331 | /* wchar_t is unsigned under the AAPCS. */ |
9332 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
9333 | set_gdbarch_wchar_signed (gdbarch, 0); | |
9334 | else | |
9335 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 9336 | |
030197b4 AB |
9337 | /* Compute type alignment. */ |
9338 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
9339 | ||
cca44b1b JB |
9340 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
9341 | of additional scratch space. This setting isn't used for anything beside | |
9342 | displaced stepping at present. */ | |
e935475c | 9343 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 9344 | |
9df628e0 | 9345 | /* This should be low enough for everything. */ |
97e03143 | 9346 | tdep->lowest_pc = 0x20; |
94c30b78 | 9347 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 9348 | |
7c00367c MK |
9349 | /* The default, for both APCS and AAPCS, is to return small |
9350 | structures in registers. */ | |
9351 | tdep->struct_return = reg_struct_return; | |
9352 | ||
2dd604e7 | 9353 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 9354 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 9355 | |
7eb89530 YQ |
9356 | if (is_m) |
9357 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
9358 | ||
756fe439 DJ |
9359 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
9360 | ||
eb5492fa | 9361 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 9362 | |
34e8f22d | 9363 | /* Address manipulation. */ |
34e8f22d RE |
9364 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
9365 | ||
34e8f22d RE |
9366 | /* Advance PC across function entry code. */ |
9367 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
9368 | ||
c9cf6e20 MG |
9369 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
9370 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 9371 | |
190dce09 UW |
9372 | /* Skip trampolines. */ |
9373 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
9374 | ||
34e8f22d RE |
9375 | /* The stack grows downward. */ |
9376 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
9377 | ||
9378 | /* Breakpoint manipulation. */ | |
04180708 YQ |
9379 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
9380 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
9381 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
9382 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
9383 | |
9384 | /* Information about registers, etc. */ | |
34e8f22d RE |
9385 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
9386 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 9387 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 9388 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 9389 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 9390 | |
ff6f572f DJ |
9391 | /* This "info float" is FPA-specific. Use the generic version if we |
9392 | do not have FPA. */ | |
9393 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
9394 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
9395 | ||
26216b98 | 9396 | /* Internal <-> external register number maps. */ |
ff6f572f | 9397 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
9398 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
9399 | ||
34e8f22d RE |
9400 | set_gdbarch_register_name (gdbarch, arm_register_name); |
9401 | ||
9402 | /* Returning results. */ | |
2af48f68 | 9403 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 9404 | |
03d48a7d RE |
9405 | /* Disassembly. */ |
9406 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
9407 | ||
34e8f22d RE |
9408 | /* Minsymbol frobbing. */ |
9409 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
9410 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
9411 | arm_coff_make_msymbol_special); | |
60c5725c | 9412 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 9413 | |
f9d67f43 DJ |
9414 | /* Thumb-2 IT block support. */ |
9415 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
9416 | arm_adjust_breakpoint_address); | |
9417 | ||
0d5de010 DJ |
9418 | /* Virtual tables. */ |
9419 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
9420 | ||
97e03143 | 9421 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 9422 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 9423 | |
b39cc962 DJ |
9424 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
9425 | ||
eb5492fa | 9426 | /* Add some default predicates. */ |
2ae28aa9 YQ |
9427 | if (is_m) |
9428 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
9429 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
9430 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 9431 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 9432 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 9433 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 9434 | |
97e03143 RE |
9435 | /* Now we have tuned the configuration, set a few final things, |
9436 | based on what the OS ABI has told us. */ | |
9437 | ||
b8926edc DJ |
9438 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
9439 | binaries are always marked. */ | |
9440 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
9441 | tdep->arm_abi = ARM_ABI_APCS; | |
9442 | ||
e3039479 UW |
9443 | /* Watchpoints are not steppable. */ |
9444 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
9445 | ||
b8926edc DJ |
9446 | /* We used to default to FPA for generic ARM, but almost nobody |
9447 | uses that now, and we now provide a way for the user to force | |
9448 | the model. So default to the most useful variant. */ | |
9449 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
9450 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
9451 | ||
9df628e0 RE |
9452 | if (tdep->jb_pc >= 0) |
9453 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
9454 | ||
08216dd7 | 9455 | /* Floating point sizes and format. */ |
8da61cc4 | 9456 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 9457 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 9458 | { |
8da61cc4 DJ |
9459 | set_gdbarch_double_format |
9460 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9461 | set_gdbarch_long_double_format | |
9462 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9463 | } | |
9464 | else | |
9465 | { | |
9466 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
9467 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
9468 | } |
9469 | ||
58d6951d DJ |
9470 | if (have_vfp_pseudos) |
9471 | { | |
9472 | /* NOTE: These are the only pseudo registers used by | |
9473 | the ARM target at the moment. If more are added, a | |
9474 | little more care in numbering will be needed. */ | |
9475 | ||
9476 | int num_pseudos = 32; | |
9477 | if (have_neon_pseudos) | |
9478 | num_pseudos += 16; | |
9479 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
9480 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
9481 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
9482 | } | |
9483 | ||
c1e1314d | 9484 | if (tdesc_data != nullptr) |
58d6951d DJ |
9485 | { |
9486 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
9487 | ||
c1e1314d | 9488 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
58d6951d DJ |
9489 | |
9490 | /* Override tdesc_register_type to adjust the types of VFP | |
9491 | registers for NEON. */ | |
9492 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
9493 | } | |
123dc839 DJ |
9494 | |
9495 | /* Add standard register aliases. We add aliases even for those | |
85102364 | 9496 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
9497 | and does no harm, since nothing ever lists user registers. */ |
9498 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
9499 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
9500 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
9501 | ||
65b48a81 PB |
9502 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
9503 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
9504 | ||
3426ae57 AH |
9505 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
9506 | ||
39bbf761 RE |
9507 | return gdbarch; |
9508 | } | |
9509 | ||
97e03143 | 9510 | static void |
2af46ca0 | 9511 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 9512 | { |
2af46ca0 | 9513 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
9514 | |
9515 | if (tdep == NULL) | |
9516 | return; | |
9517 | ||
aeefc73c CB |
9518 | fprintf_unfiltered (file, _("arm_dump_tdep: fp_model = %i\n"), |
9519 | (int) tdep->fp_model); | |
9520 | fprintf_unfiltered (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
9521 | (int) tdep->have_fpa_registers); | |
9522 | fprintf_unfiltered (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
9523 | (int) tdep->have_wmmx_registers); | |
9524 | fprintf_unfiltered (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
9525 | (int) tdep->vfp_register_count); | |
9526 | fprintf_unfiltered (file, _("arm_dump_tdep: have_vfp_pseudos = %i\n"), | |
9527 | (int) tdep->have_vfp_pseudos); | |
9528 | fprintf_unfiltered (file, _("arm_dump_tdep: have_neon_pseudos = %i\n"), | |
9529 | (int) tdep->have_neon_pseudos); | |
9530 | fprintf_unfiltered (file, _("arm_dump_tdep: have_neon = %i\n"), | |
9531 | (int) tdep->have_neon); | |
754e1564 | 9532 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), |
97e03143 RE |
9533 | (unsigned long) tdep->lowest_pc); |
9534 | } | |
9535 | ||
0d4c07af | 9536 | #if GDB_SELF_TEST |
b121eeb9 YQ |
9537 | namespace selftests |
9538 | { | |
9539 | static void arm_record_test (void); | |
9ecab40c | 9540 | static void arm_analyze_prologue_test (); |
b121eeb9 | 9541 | } |
0d4c07af | 9542 | #endif |
b121eeb9 | 9543 | |
6c265988 | 9544 | void _initialize_arm_tdep (); |
c906108c | 9545 | void |
6c265988 | 9546 | _initialize_arm_tdep () |
c906108c | 9547 | { |
bc90b915 | 9548 | long length; |
65b48a81 | 9549 | int i, j; |
edefbb7c AC |
9550 | char regdesc[1024], *rdptr = regdesc; |
9551 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 9552 | |
42cf1509 | 9553 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 9554 | |
0e9e9abd | 9555 | /* Add ourselves to objfile event chain. */ |
76727919 | 9556 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile); |
0e9e9abd | 9557 | |
70f80edf JT |
9558 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
9559 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
9560 | bfd_target_elf_flavour, | |
9561 | arm_elf_osabi_sniffer); | |
9562 | ||
afd7eef0 | 9563 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
0743fc83 TT |
9564 | add_basic_prefix_cmd ("arm", no_class, |
9565 | _("Various ARM-specific commands."), | |
9566 | &setarmcmdlist, "set arm ", 0, &setlist); | |
afd7eef0 | 9567 | |
0743fc83 TT |
9568 | add_show_prefix_cmd ("arm", no_class, |
9569 | _("Various ARM-specific commands."), | |
9570 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 9571 | |
c5aa993b | 9572 | |
65b48a81 | 9573 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
9574 | const disasm_options_t *disasm_options |
9575 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
9576 | int num_disassembly_styles = 0; |
9577 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
9578 | if (CONST_STRNEQ (disasm_options->name[i], "reg-names-")) | |
9579 | num_disassembly_styles++; | |
9580 | ||
9581 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 9582 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
9583 | num_disassembly_styles + 1); |
9584 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
9585 | if (CONST_STRNEQ (disasm_options->name[i], "reg-names-")) | |
9586 | { | |
9587 | size_t offset = strlen ("reg-names-"); | |
9588 | const char *style = disasm_options->name[i]; | |
9589 | valid_disassembly_styles[j++] = &style[offset]; | |
9590 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], | |
9591 | disasm_options->description[i]); | |
9592 | rdptr += length; | |
9593 | rest -= length; | |
9594 | } | |
94c30b78 | 9595 | /* Mark the end of valid options. */ |
65b48a81 | 9596 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 9597 | |
edefbb7c | 9598 | /* Create the help text. */ |
d7e74731 PA |
9599 | std::string helptext = string_printf ("%s%s%s", |
9600 | _("The valid values are:\n"), | |
9601 | regdesc, | |
9602 | _("The default is \"std\".")); | |
ed9a39eb | 9603 | |
edefbb7c AC |
9604 | add_setshow_enum_cmd("disassembler", no_class, |
9605 | valid_disassembly_styles, &disassembly_style, | |
9606 | _("Set the disassembly style."), | |
9607 | _("Show the disassembly style."), | |
09b0e4b0 | 9608 | helptext.c_str (), |
2c5b56ce | 9609 | set_disassembly_style_sfunc, |
65b48a81 | 9610 | show_disassembly_style_sfunc, |
7376b4c2 | 9611 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
9612 | |
9613 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
9614 | _("Set usage of ARM 32-bit mode."), | |
9615 | _("Show usage of ARM 32-bit mode."), | |
9616 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 9617 | NULL, |
0963b4bd MS |
9618 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
9619 | mode is %s. */ | |
26304000 | 9620 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 9621 | |
fd50bc42 | 9622 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
9623 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
9624 | _("Set the floating point type."), | |
9625 | _("Show the floating point type."), | |
9626 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
9627 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
9628 | fpa - FPA co-processor (GCC compiled).\n\ | |
9629 | softvfp - Software FP with pure-endian doubles.\n\ | |
9630 | vfp - VFP co-processor."), | |
edefbb7c | 9631 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 9632 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 9633 | |
28e97307 DJ |
9634 | /* Add a command to allow the user to force the ABI. */ |
9635 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
9636 | _("Set the ABI."), | |
9637 | _("Show the ABI."), | |
9638 | NULL, arm_set_abi, arm_show_abi, | |
9639 | &setarmcmdlist, &showarmcmdlist); | |
9640 | ||
0428b8f5 DJ |
9641 | /* Add two commands to allow the user to force the assumed |
9642 | execution mode. */ | |
9643 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
9644 | arm_mode_strings, &arm_fallback_mode_string, | |
9645 | _("Set the mode assumed when symbols are unavailable."), | |
9646 | _("Show the mode assumed when symbols are unavailable."), | |
9647 | NULL, NULL, arm_show_fallback_mode, | |
9648 | &setarmcmdlist, &showarmcmdlist); | |
9649 | add_setshow_enum_cmd ("force-mode", class_support, | |
9650 | arm_mode_strings, &arm_force_mode_string, | |
9651 | _("Set the mode assumed even when symbols are available."), | |
9652 | _("Show the mode assumed even when symbols are available."), | |
9653 | NULL, NULL, arm_show_force_mode, | |
9654 | &setarmcmdlist, &showarmcmdlist); | |
9655 | ||
6529d2dd | 9656 | /* Debugging flag. */ |
edefbb7c AC |
9657 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
9658 | _("Set ARM debugging."), | |
9659 | _("Show ARM debugging."), | |
9660 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 9661 | NULL, |
7915a72c | 9662 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 9663 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
9664 | |
9665 | #if GDB_SELF_TEST | |
1526853e | 9666 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 9667 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
9668 | #endif |
9669 | ||
c906108c | 9670 | } |
72508ac0 PO |
9671 | |
9672 | /* ARM-reversible process record data structures. */ | |
9673 | ||
9674 | #define ARM_INSN_SIZE_BYTES 4 | |
9675 | #define THUMB_INSN_SIZE_BYTES 2 | |
9676 | #define THUMB2_INSN_SIZE_BYTES 4 | |
9677 | ||
9678 | ||
71e396f9 LM |
9679 | /* Position of the bit within a 32-bit ARM instruction |
9680 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
9681 | #define INSN_S_L_BIT_NUM 20 |
9682 | ||
9683 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
9684 | do \ |
9685 | { \ | |
9686 | unsigned int reg_len = LENGTH; \ | |
9687 | if (reg_len) \ | |
9688 | { \ | |
9689 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
9690 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
9691 | } \ | |
9692 | } \ | |
9693 | while (0) | |
72508ac0 PO |
9694 | |
9695 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
9696 | do \ |
9697 | { \ | |
9698 | unsigned int mem_len = LENGTH; \ | |
9699 | if (mem_len) \ | |
9700 | { \ | |
9701 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
9702 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
9703 | sizeof(struct arm_mem_r) * LENGTH); \ | |
9704 | } \ | |
9705 | } \ | |
9706 | while (0) | |
72508ac0 PO |
9707 | |
9708 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
9709 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 9710 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
9711 | |
9712 | /* ARM memory record structure. */ | |
9713 | struct arm_mem_r | |
9714 | { | |
9715 | uint32_t len; /* Record length. */ | |
bfbbec00 | 9716 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
9717 | }; |
9718 | ||
9719 | /* ARM instruction record contains opcode of current insn | |
9720 | and execution state (before entry to decode_insn()), | |
9721 | contains list of to-be-modified registers and | |
9722 | memory blocks (on return from decode_insn()). */ | |
9723 | ||
9724 | typedef struct insn_decode_record_t | |
9725 | { | |
9726 | struct gdbarch *gdbarch; | |
9727 | struct regcache *regcache; | |
9728 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
9729 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
9730 | uint32_t cond; /* Condition code. */ | |
9731 | uint32_t opcode; /* Insn opcode. */ | |
9732 | uint32_t decode; /* Insn decode bits. */ | |
9733 | uint32_t mem_rec_count; /* No of mem records. */ | |
9734 | uint32_t reg_rec_count; /* No of reg records. */ | |
9735 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
9736 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
9737 | } insn_decode_record; | |
9738 | ||
9739 | ||
9740 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
9741 | ||
9742 | static int | |
9743 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
9744 | { | |
9745 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
9746 | ||
9747 | if (!len) | |
9748 | return 1; | |
9749 | ||
9750 | if (!sbo) | |
9751 | ones = ~ones; | |
9752 | ||
9753 | while (ones) | |
9754 | { | |
9755 | if (!(ones & sbo)) | |
dda83cd7 SM |
9756 | { |
9757 | return 0; | |
9758 | } | |
72508ac0 PO |
9759 | ones = ones >> 1; |
9760 | } | |
9761 | return 1; | |
9762 | } | |
9763 | ||
c6ec2b30 OJ |
9764 | enum arm_record_result |
9765 | { | |
9766 | ARM_RECORD_SUCCESS = 0, | |
9767 | ARM_RECORD_FAILURE = 1 | |
9768 | }; | |
9769 | ||
72508ac0 PO |
9770 | typedef enum |
9771 | { | |
9772 | ARM_RECORD_STRH=1, | |
9773 | ARM_RECORD_STRD | |
9774 | } arm_record_strx_t; | |
9775 | ||
9776 | typedef enum | |
9777 | { | |
9778 | ARM_RECORD=1, | |
9779 | THUMB_RECORD, | |
9780 | THUMB2_RECORD | |
9781 | } record_type_t; | |
9782 | ||
9783 | ||
9784 | static int | |
9785 | arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, | |
dda83cd7 | 9786 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
9787 | { |
9788 | ||
9789 | struct regcache *reg_cache = arm_insn_r->regcache; | |
9790 | ULONGEST u_regval[2]= {0}; | |
9791 | ||
9792 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
9793 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
9794 | |
9795 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
9796 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
9797 | |
9798 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
9799 | { | |
9800 | /* 1) Handle misc store, immediate offset. */ | |
9801 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9802 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9803 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9804 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 9805 | &u_regval[0]); |
72508ac0 | 9806 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
9807 | { |
9808 | /* If R15 was used as Rn, hence current PC+8. */ | |
9809 | u_regval[0] = u_regval[0] + 8; | |
9810 | } | |
72508ac0 PO |
9811 | offset_8 = (immed_high << 4) | immed_low; |
9812 | /* Calculate target store address. */ | |
9813 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
9814 | { |
9815 | tgt_mem_addr = u_regval[0] + offset_8; | |
9816 | } | |
72508ac0 | 9817 | else |
dda83cd7 SM |
9818 | { |
9819 | tgt_mem_addr = u_regval[0] - offset_8; | |
9820 | } | |
72508ac0 | 9821 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9822 | { |
9823 | record_buf_mem[0] = 2; | |
9824 | record_buf_mem[1] = tgt_mem_addr; | |
9825 | arm_insn_r->mem_rec_count = 1; | |
9826 | } | |
72508ac0 | 9827 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9828 | { |
9829 | record_buf_mem[0] = 4; | |
9830 | record_buf_mem[1] = tgt_mem_addr; | |
9831 | record_buf_mem[2] = 4; | |
9832 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9833 | arm_insn_r->mem_rec_count = 2; | |
9834 | } | |
72508ac0 PO |
9835 | } |
9836 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
9837 | { | |
9838 | /* 2) Store, register offset. */ | |
9839 | /* Get Rm. */ | |
9840 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9841 | /* Get Rn. */ | |
9842 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9843 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9844 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9845 | if (15 == reg_src2) | |
dda83cd7 SM |
9846 | { |
9847 | /* If R15 was used as Rn, hence current PC+8. */ | |
9848 | u_regval[0] = u_regval[0] + 8; | |
9849 | } | |
72508ac0 PO |
9850 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
9851 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
9852 | { |
9853 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9854 | } | |
72508ac0 | 9855 | else |
dda83cd7 SM |
9856 | { |
9857 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9858 | } | |
72508ac0 | 9859 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9860 | { |
9861 | record_buf_mem[0] = 2; | |
9862 | record_buf_mem[1] = tgt_mem_addr; | |
9863 | arm_insn_r->mem_rec_count = 1; | |
9864 | } | |
72508ac0 | 9865 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9866 | { |
9867 | record_buf_mem[0] = 4; | |
9868 | record_buf_mem[1] = tgt_mem_addr; | |
9869 | record_buf_mem[2] = 4; | |
9870 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9871 | arm_insn_r->mem_rec_count = 2; | |
9872 | } | |
72508ac0 PO |
9873 | } |
9874 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 9875 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
9876 | { |
9877 | /* 3) Store, immediate pre-indexed. */ | |
9878 | /* 5) Store, immediate post-indexed. */ | |
9879 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
9880 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
9881 | offset_8 = (immed_high << 4) | immed_low; | |
9882 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
9883 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9884 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9885 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
9886 | { |
9887 | tgt_mem_addr = u_regval[0] + offset_8; | |
9888 | } | |
72508ac0 | 9889 | else |
dda83cd7 SM |
9890 | { |
9891 | tgt_mem_addr = u_regval[0] - offset_8; | |
9892 | } | |
72508ac0 | 9893 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9894 | { |
9895 | record_buf_mem[0] = 2; | |
9896 | record_buf_mem[1] = tgt_mem_addr; | |
9897 | arm_insn_r->mem_rec_count = 1; | |
9898 | } | |
72508ac0 | 9899 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9900 | { |
9901 | record_buf_mem[0] = 4; | |
9902 | record_buf_mem[1] = tgt_mem_addr; | |
9903 | record_buf_mem[2] = 4; | |
9904 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9905 | arm_insn_r->mem_rec_count = 2; | |
9906 | } | |
72508ac0 PO |
9907 | /* Record Rn also as it changes. */ |
9908 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9909 | arm_insn_r->reg_rec_count = 1; | |
9910 | } | |
9911 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 9912 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
9913 | { |
9914 | /* 4) Store, register pre-indexed. */ | |
9915 | /* 6) Store, register post -indexed. */ | |
9916 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
9917 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
9918 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
9919 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
9920 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
9921 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
9922 | { |
9923 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
9924 | } | |
72508ac0 | 9925 | else |
dda83cd7 SM |
9926 | { |
9927 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
9928 | } | |
72508ac0 | 9929 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
9930 | { |
9931 | record_buf_mem[0] = 2; | |
9932 | record_buf_mem[1] = tgt_mem_addr; | |
9933 | arm_insn_r->mem_rec_count = 1; | |
9934 | } | |
72508ac0 | 9935 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
9936 | { |
9937 | record_buf_mem[0] = 4; | |
9938 | record_buf_mem[1] = tgt_mem_addr; | |
9939 | record_buf_mem[2] = 4; | |
9940 | record_buf_mem[3] = tgt_mem_addr + 4; | |
9941 | arm_insn_r->mem_rec_count = 2; | |
9942 | } | |
72508ac0 PO |
9943 | /* Record Rn also as it changes. */ |
9944 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
9945 | arm_insn_r->reg_rec_count = 1; | |
9946 | } | |
9947 | return 0; | |
9948 | } | |
9949 | ||
9950 | /* Handling ARM extension space insns. */ | |
9951 | ||
9952 | static int | |
9953 | arm_record_extension_space (insn_decode_record *arm_insn_r) | |
9954 | { | |
df95a9cf | 9955 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
9956 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
9957 | uint32_t record_buf[8], record_buf_mem[8]; | |
9958 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
9959 | struct regcache *reg_cache = arm_insn_r->regcache; |
9960 | ULONGEST u_regval = 0; | |
9961 | ||
9962 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
9963 | /* Handle unconditional insn extension space. */ | |
9964 | ||
9965 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
9966 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9967 | if (arm_insn_r->cond) | |
9968 | { | |
9969 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 9970 | the caches. */ |
72508ac0 | 9971 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
9972 | { |
9973 | /* BLX(1) */ | |
9974 | record_buf[0] = ARM_PS_REGNUM; | |
9975 | record_buf[1] = ARM_LR_REGNUM; | |
9976 | arm_insn_r->reg_rec_count = 2; | |
9977 | } | |
72508ac0 PO |
9978 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
9979 | } | |
9980 | ||
9981 | ||
9982 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
9983 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
9984 | { | |
9985 | ret = -1; | |
9986 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 9987 | versions define it. */ |
72508ac0 PO |
9988 | } |
9989 | ||
9990 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
9991 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
9992 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
9993 | ||
9994 | /* Handle arithmetic insn extension space. */ | |
9995 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
9996 | && !INSN_RECORDED(arm_insn_r)) | |
9997 | { | |
9998 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 9999 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
72508ac0 | 10000 | { |
dda83cd7 SM |
10001 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10002 | record_buf[1] = ARM_PS_REGNUM; | |
10003 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 10004 | } |
b020ff80 | 10005 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
72508ac0 | 10006 | { |
dda83cd7 SM |
10007 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ |
10008 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10009 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10010 | record_buf[2] = ARM_PS_REGNUM; | |
10011 | arm_insn_r->reg_rec_count = 3; | |
72508ac0 PO |
10012 | } |
10013 | } | |
10014 | ||
10015 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
10016 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
10017 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
10018 | ||
10019 | /* Handle control insn extension space. */ | |
10020 | ||
10021 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
10022 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
10023 | { | |
10024 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
10025 | { |
10026 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
10027 | { | |
10028 | if ((0 == insn_op1) || (2 == insn_op1)) | |
10029 | { | |
10030 | /* MRS. */ | |
10031 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10032 | arm_insn_r->reg_rec_count = 1; | |
10033 | } | |
10034 | else if (1 == insn_op1) | |
10035 | { | |
10036 | /* CSPR is going to be changed. */ | |
10037 | record_buf[0] = ARM_PS_REGNUM; | |
10038 | arm_insn_r->reg_rec_count = 1; | |
10039 | } | |
10040 | else if (3 == insn_op1) | |
10041 | { | |
10042 | /* SPSR is going to be changed. */ | |
10043 | /* We need to get SPSR value, which is yet to be done. */ | |
10044 | return -1; | |
10045 | } | |
10046 | } | |
10047 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10048 | { | |
10049 | if (1 == insn_op1) | |
10050 | { | |
10051 | /* BX. */ | |
10052 | record_buf[0] = ARM_PS_REGNUM; | |
10053 | arm_insn_r->reg_rec_count = 1; | |
10054 | } | |
10055 | else if (3 == insn_op1) | |
10056 | { | |
10057 | /* CLZ. */ | |
10058 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10059 | arm_insn_r->reg_rec_count = 1; | |
10060 | } | |
10061 | } | |
10062 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10063 | { | |
10064 | /* BLX. */ | |
10065 | record_buf[0] = ARM_PS_REGNUM; | |
10066 | record_buf[1] = ARM_LR_REGNUM; | |
10067 | arm_insn_r->reg_rec_count = 2; | |
10068 | } | |
10069 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10070 | { | |
10071 | /* QADD, QSUB, QDADD, QDSUB */ | |
10072 | record_buf[0] = ARM_PS_REGNUM; | |
10073 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10074 | arm_insn_r->reg_rec_count = 2; | |
10075 | } | |
10076 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10077 | { | |
10078 | /* BKPT. */ | |
10079 | record_buf[0] = ARM_PS_REGNUM; | |
10080 | record_buf[1] = ARM_LR_REGNUM; | |
10081 | arm_insn_r->reg_rec_count = 2; | |
10082 | ||
10083 | /* Save SPSR also;how? */ | |
10084 | return -1; | |
10085 | } | |
10086 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
10087 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
10088 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
10089 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
10090 | ) | |
10091 | { | |
10092 | if (0 == insn_op1 || 1 == insn_op1) | |
10093 | { | |
10094 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
10095 | /* We dont do optimization for SMULW<y> where we | |
10096 | need only Rd. */ | |
10097 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10098 | record_buf[1] = ARM_PS_REGNUM; | |
10099 | arm_insn_r->reg_rec_count = 2; | |
10100 | } | |
10101 | else if (2 == insn_op1) | |
10102 | { | |
10103 | /* SMLAL<x><y>. */ | |
10104 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10105 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
10106 | arm_insn_r->reg_rec_count = 2; | |
10107 | } | |
10108 | else if (3 == insn_op1) | |
10109 | { | |
10110 | /* SMUL<x><y>. */ | |
10111 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10112 | arm_insn_r->reg_rec_count = 1; | |
10113 | } | |
10114 | } | |
10115 | } | |
72508ac0 | 10116 | else |
dda83cd7 SM |
10117 | { |
10118 | /* MSR : immediate form. */ | |
10119 | if (1 == insn_op1) | |
10120 | { | |
10121 | /* CSPR is going to be changed. */ | |
10122 | record_buf[0] = ARM_PS_REGNUM; | |
10123 | arm_insn_r->reg_rec_count = 1; | |
10124 | } | |
10125 | else if (3 == insn_op1) | |
10126 | { | |
10127 | /* SPSR is going to be changed. */ | |
10128 | /* we need to get SPSR value, which is yet to be done */ | |
10129 | return -1; | |
10130 | } | |
10131 | } | |
72508ac0 PO |
10132 | } |
10133 | ||
10134 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10135 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
10136 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
10137 | ||
10138 | /* Handle load/store insn extension space. */ | |
10139 | ||
10140 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
10141 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
10142 | && !INSN_RECORDED(arm_insn_r)) | |
10143 | { | |
10144 | /* SWP/SWPB. */ | |
10145 | if (0 == insn_op1) | |
dda83cd7 SM |
10146 | { |
10147 | /* These insn, changes register and memory as well. */ | |
10148 | /* SWP or SWPB insn. */ | |
10149 | /* Get memory address given by Rn. */ | |
10150 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10151 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
10152 | /* SWP insn ?, swaps word. */ | |
10153 | if (8 == arm_insn_r->opcode) | |
10154 | { | |
10155 | record_buf_mem[0] = 4; | |
10156 | } | |
10157 | else | |
10158 | { | |
10159 | /* SWPB insn, swaps only byte. */ | |
10160 | record_buf_mem[0] = 1; | |
10161 | } | |
10162 | record_buf_mem[1] = u_regval; | |
10163 | arm_insn_r->mem_rec_count = 1; | |
10164 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10165 | arm_insn_r->reg_rec_count = 1; | |
10166 | } | |
72508ac0 | 10167 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10168 | { |
10169 | /* STRH. */ | |
10170 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10171 | ARM_RECORD_STRH); | |
10172 | } | |
72508ac0 | 10173 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10174 | { |
10175 | /* LDRD. */ | |
10176 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10177 | record_buf[1] = record_buf[0] + 1; | |
10178 | arm_insn_r->reg_rec_count = 2; | |
10179 | } | |
72508ac0 | 10180 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10181 | { |
10182 | /* STRD. */ | |
10183 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10184 | ARM_RECORD_STRD); | |
10185 | } | |
72508ac0 | 10186 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
10187 | { |
10188 | /* LDRH, LDRSB, LDRSH. */ | |
10189 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10190 | arm_insn_r->reg_rec_count = 1; | |
10191 | } | |
72508ac0 PO |
10192 | |
10193 | } | |
10194 | ||
10195 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
10196 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
10197 | && !INSN_RECORDED(arm_insn_r)) | |
10198 | { | |
10199 | ret = -1; | |
10200 | /* Handle coprocessor insn extension space. */ | |
10201 | } | |
10202 | ||
10203 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
10204 | if (-1 == ret) | |
ca92db2d | 10205 | return ret; |
72508ac0 PO |
10206 | |
10207 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10208 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10209 | ||
10210 | return ret; | |
10211 | } | |
10212 | ||
10213 | /* Handling opcode 000 insns. */ | |
10214 | ||
10215 | static int | |
10216 | arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) | |
10217 | { | |
10218 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10219 | uint32_t record_buf[8], record_buf_mem[8]; | |
10220 | ULONGEST u_regval[2] = {0}; | |
10221 | ||
8d49165d | 10222 | uint32_t reg_src1 = 0; |
72508ac0 PO |
10223 | uint32_t opcode1 = 0; |
10224 | ||
10225 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10226 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10227 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
10228 | ||
2d9e6acb | 10229 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10230 | { |
2d9e6acb YQ |
10231 | /* Data-processing (register) and Data-processing (register-shifted |
10232 | register */ | |
10233 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
10234 | register, which is specified by 13-16 decode. */ | |
10235 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10236 | record_buf[1] = ARM_PS_REGNUM; | |
10237 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 10238 | } |
2d9e6acb | 10239 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10240 | { |
2d9e6acb YQ |
10241 | /* Miscellaneous instructions */ |
10242 | ||
10243 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
10244 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10245 | { | |
10246 | /* Handle BLX, branch and link/exchange. */ | |
10247 | if (9 == arm_insn_r->opcode) | |
10248 | { | |
10249 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
10250 | and R14 stores the return address. */ | |
10251 | record_buf[0] = ARM_PS_REGNUM; | |
10252 | record_buf[1] = ARM_LR_REGNUM; | |
10253 | arm_insn_r->reg_rec_count = 2; | |
10254 | } | |
10255 | } | |
10256 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
10257 | { | |
10258 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
10259 | /* CPSR is changed to be executed in ARM state, disabling normal | |
10260 | interrupts, entering abort mode. */ | |
10261 | /* According to high vector configuration PC is set. */ | |
10262 | /* user hit breakpoint and type reverse, in | |
10263 | that case, we need to go back with previous CPSR and | |
10264 | Program Counter. */ | |
10265 | record_buf[0] = ARM_PS_REGNUM; | |
10266 | record_buf[1] = ARM_LR_REGNUM; | |
10267 | arm_insn_r->reg_rec_count = 2; | |
10268 | ||
10269 | /* Save SPSR also; how? */ | |
10270 | return -1; | |
10271 | } | |
10272 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
10273 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10274 | { | |
10275 | /* Handle BX, branch and link/exchange. */ | |
10276 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
10277 | record_buf[0] = ARM_PS_REGNUM; | |
10278 | arm_insn_r->reg_rec_count = 1; | |
10279 | } | |
10280 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
10281 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
10282 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
10283 | { | |
10284 | /* Count leading zeros: CLZ. */ | |
10285 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10286 | arm_insn_r->reg_rec_count = 1; | |
10287 | } | |
10288 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
10289 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10290 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
10291 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
10292 | { | |
10293 | /* Handle MRS insn. */ | |
10294 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10295 | arm_insn_r->reg_rec_count = 1; | |
10296 | } | |
72508ac0 | 10297 | } |
2d9e6acb | 10298 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 10299 | { |
2d9e6acb YQ |
10300 | /* Multiply and multiply-accumulate */ |
10301 | ||
10302 | /* Handle multiply instructions. */ | |
10303 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
10304 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
10305 | { | |
10306 | /* Handle MLA and MUL. */ | |
10307 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10308 | record_buf[1] = ARM_PS_REGNUM; | |
10309 | arm_insn_r->reg_rec_count = 2; | |
10310 | } | |
10311 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
10312 | { | |
10313 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
10314 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10315 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10316 | record_buf[2] = ARM_PS_REGNUM; | |
10317 | arm_insn_r->reg_rec_count = 3; | |
10318 | } | |
10319 | } | |
10320 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
10321 | { | |
10322 | /* Synchronization primitives */ | |
10323 | ||
72508ac0 PO |
10324 | /* Handling SWP, SWPB. */ |
10325 | /* These insn, changes register and memory as well. */ | |
10326 | /* SWP or SWPB insn. */ | |
10327 | ||
10328 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10329 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10330 | /* SWP insn ?, swaps word. */ | |
10331 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
10332 | { |
10333 | record_buf_mem[0] = 4; | |
10334 | } | |
10335 | else | |
10336 | { | |
10337 | /* SWPB insn, swaps only byte. */ | |
10338 | record_buf_mem[0] = 1; | |
10339 | } | |
72508ac0 PO |
10340 | record_buf_mem[1] = u_regval[0]; |
10341 | arm_insn_r->mem_rec_count = 1; | |
10342 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10343 | arm_insn_r->reg_rec_count = 1; | |
10344 | } | |
2d9e6acb YQ |
10345 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
10346 | || 15 == arm_insn_r->decode) | |
72508ac0 | 10347 | { |
2d9e6acb YQ |
10348 | if ((opcode1 & 0x12) == 2) |
10349 | { | |
10350 | /* Extra load/store (unprivileged) */ | |
10351 | return -1; | |
10352 | } | |
10353 | else | |
10354 | { | |
10355 | /* Extra load/store */ | |
10356 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
10357 | { | |
10358 | case 1: | |
10359 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
10360 | { | |
10361 | /* STRH (register), STRH (immediate) */ | |
10362 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10363 | &record_buf_mem[0], ARM_RECORD_STRH); | |
10364 | } | |
10365 | else if ((opcode1 & 0x05) == 0x1) | |
10366 | { | |
10367 | /* LDRH (register) */ | |
10368 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10369 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 10370 | |
2d9e6acb YQ |
10371 | if (bit (arm_insn_r->arm_insn, 21)) |
10372 | { | |
10373 | /* Write back to Rn. */ | |
10374 | record_buf[arm_insn_r->reg_rec_count++] | |
10375 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10376 | } | |
10377 | } | |
10378 | else if ((opcode1 & 0x05) == 0x5) | |
10379 | { | |
10380 | /* LDRH (immediate), LDRH (literal) */ | |
10381 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 10382 | |
2d9e6acb YQ |
10383 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10384 | arm_insn_r->reg_rec_count = 1; | |
10385 | ||
10386 | if (rn != 15) | |
10387 | { | |
10388 | /*LDRH (immediate) */ | |
10389 | if (bit (arm_insn_r->arm_insn, 21)) | |
10390 | { | |
10391 | /* Write back to Rn. */ | |
10392 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10393 | } | |
10394 | } | |
10395 | } | |
10396 | else | |
10397 | return -1; | |
10398 | break; | |
10399 | case 2: | |
10400 | if ((opcode1 & 0x05) == 0x0) | |
10401 | { | |
10402 | /* LDRD (register) */ | |
10403 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10404 | record_buf[1] = record_buf[0] + 1; | |
10405 | arm_insn_r->reg_rec_count = 2; | |
10406 | ||
10407 | if (bit (arm_insn_r->arm_insn, 21)) | |
10408 | { | |
10409 | /* Write back to Rn. */ | |
10410 | record_buf[arm_insn_r->reg_rec_count++] | |
10411 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10412 | } | |
10413 | } | |
10414 | else if ((opcode1 & 0x05) == 0x1) | |
10415 | { | |
10416 | /* LDRSB (register) */ | |
10417 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10418 | arm_insn_r->reg_rec_count = 1; | |
10419 | ||
10420 | if (bit (arm_insn_r->arm_insn, 21)) | |
10421 | { | |
10422 | /* Write back to Rn. */ | |
10423 | record_buf[arm_insn_r->reg_rec_count++] | |
10424 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10425 | } | |
10426 | } | |
10427 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
10428 | { | |
10429 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
10430 | LDRSB (literal) */ | |
10431 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
10432 | ||
10433 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10434 | arm_insn_r->reg_rec_count = 1; | |
10435 | ||
10436 | if (rn != 15) | |
10437 | { | |
10438 | /*LDRD (immediate), LDRSB (immediate) */ | |
10439 | if (bit (arm_insn_r->arm_insn, 21)) | |
10440 | { | |
10441 | /* Write back to Rn. */ | |
10442 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10443 | } | |
10444 | } | |
10445 | } | |
10446 | else | |
10447 | return -1; | |
10448 | break; | |
10449 | case 3: | |
10450 | if ((opcode1 & 0x05) == 0x0) | |
10451 | { | |
10452 | /* STRD (register) */ | |
10453 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10454 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10455 | } | |
10456 | else if ((opcode1 & 0x05) == 0x1) | |
10457 | { | |
10458 | /* LDRSH (register) */ | |
10459 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10460 | arm_insn_r->reg_rec_count = 1; | |
10461 | ||
10462 | if (bit (arm_insn_r->arm_insn, 21)) | |
10463 | { | |
10464 | /* Write back to Rn. */ | |
10465 | record_buf[arm_insn_r->reg_rec_count++] | |
10466 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10467 | } | |
10468 | } | |
10469 | else if ((opcode1 & 0x05) == 0x4) | |
10470 | { | |
10471 | /* STRD (immediate) */ | |
10472 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10473 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10474 | } | |
10475 | else if ((opcode1 & 0x05) == 0x5) | |
10476 | { | |
10477 | /* LDRSH (immediate), LDRSH (literal) */ | |
10478 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10479 | arm_insn_r->reg_rec_count = 1; | |
10480 | ||
10481 | if (bit (arm_insn_r->arm_insn, 21)) | |
10482 | { | |
10483 | /* Write back to Rn. */ | |
10484 | record_buf[arm_insn_r->reg_rec_count++] | |
10485 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10486 | } | |
10487 | } | |
10488 | else | |
10489 | return -1; | |
10490 | break; | |
10491 | default: | |
10492 | return -1; | |
10493 | } | |
10494 | } | |
72508ac0 PO |
10495 | } |
10496 | else | |
10497 | { | |
10498 | return -1; | |
10499 | } | |
10500 | ||
10501 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10502 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10503 | return 0; | |
10504 | } | |
10505 | ||
10506 | /* Handling opcode 001 insns. */ | |
10507 | ||
10508 | static int | |
10509 | arm_record_data_proc_imm (insn_decode_record *arm_insn_r) | |
10510 | { | |
10511 | uint32_t record_buf[8], record_buf_mem[8]; | |
10512 | ||
10513 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10514 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10515 | ||
10516 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
10517 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
10518 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
10519 | ) | |
10520 | { | |
10521 | /* Handle MSR insn. */ | |
10522 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
10523 | { |
10524 | /* CSPR is going to be changed. */ | |
10525 | record_buf[0] = ARM_PS_REGNUM; | |
10526 | arm_insn_r->reg_rec_count = 1; | |
10527 | } | |
72508ac0 | 10528 | else |
dda83cd7 SM |
10529 | { |
10530 | /* SPSR is going to be changed. */ | |
10531 | } | |
72508ac0 PO |
10532 | } |
10533 | else if (arm_insn_r->opcode <= 15) | |
10534 | { | |
10535 | /* Normal data processing insns. */ | |
10536 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 10537 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
10538 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10539 | record_buf[1] = ARM_PS_REGNUM; | |
10540 | arm_insn_r->reg_rec_count = 2; | |
10541 | } | |
10542 | else | |
10543 | { | |
10544 | return -1; | |
10545 | } | |
10546 | ||
10547 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10548 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10549 | return 0; | |
10550 | } | |
10551 | ||
c55978a6 YQ |
10552 | static int |
10553 | arm_record_media (insn_decode_record *arm_insn_r) | |
10554 | { | |
10555 | uint32_t record_buf[8]; | |
10556 | ||
10557 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
10558 | { | |
10559 | case 0: | |
10560 | /* Parallel addition and subtraction, signed */ | |
10561 | case 1: | |
10562 | /* Parallel addition and subtraction, unsigned */ | |
10563 | case 2: | |
10564 | case 3: | |
10565 | /* Packing, unpacking, saturation and reversal */ | |
10566 | { | |
10567 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
10568 | ||
10569 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
10570 | } | |
10571 | break; | |
10572 | ||
10573 | case 4: | |
10574 | case 5: | |
10575 | /* Signed multiplies */ | |
10576 | { | |
10577 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
10578 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
10579 | ||
10580 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
10581 | if (op1 == 0x0) | |
10582 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
10583 | else if (op1 == 0x4) | |
10584 | record_buf[arm_insn_r->reg_rec_count++] | |
10585 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10586 | } | |
10587 | break; | |
10588 | ||
10589 | case 6: | |
10590 | { | |
10591 | if (bit (arm_insn_r->arm_insn, 21) | |
10592 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
10593 | { | |
10594 | /* SBFX */ | |
10595 | record_buf[arm_insn_r->reg_rec_count++] | |
10596 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10597 | } | |
10598 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
10599 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
10600 | { | |
10601 | /* USAD8 and USADA8 */ | |
10602 | record_buf[arm_insn_r->reg_rec_count++] | |
10603 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10604 | } | |
10605 | } | |
10606 | break; | |
10607 | ||
10608 | case 7: | |
10609 | { | |
10610 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
10611 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
10612 | { | |
10613 | /* Permanently UNDEFINED */ | |
10614 | return -1; | |
10615 | } | |
10616 | else | |
10617 | { | |
10618 | /* BFC, BFI and UBFX */ | |
10619 | record_buf[arm_insn_r->reg_rec_count++] | |
10620 | = bits (arm_insn_r->arm_insn, 12, 15); | |
10621 | } | |
10622 | } | |
10623 | break; | |
10624 | ||
10625 | default: | |
10626 | return -1; | |
10627 | } | |
10628 | ||
10629 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10630 | ||
10631 | return 0; | |
10632 | } | |
10633 | ||
71e396f9 | 10634 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
10635 | |
10636 | static int | |
10637 | arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) | |
10638 | { | |
10639 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10640 | ||
71e396f9 LM |
10641 | uint32_t reg_base , reg_dest; |
10642 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 10643 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
10644 | unsigned char wback; |
10645 | ULONGEST u_regval; | |
72508ac0 | 10646 | |
71e396f9 LM |
10647 | /* Calculate wback. */ |
10648 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
10649 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 10650 | |
71e396f9 LM |
10651 | arm_insn_r->reg_rec_count = 0; |
10652 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
10653 | |
10654 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10655 | { | |
71e396f9 LM |
10656 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
10657 | and LDRT. */ | |
10658 | ||
72508ac0 | 10659 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
10660 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
10661 | ||
10662 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
10663 | preceeds a LDR instruction having R15 as reg_base, it | |
10664 | emulates a branch and link instruction, and hence we need to save | |
10665 | CPSR and PC as well. */ | |
10666 | if (ARM_PC_REGNUM == reg_dest) | |
10667 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
10668 | ||
10669 | /* If wback is true, also save the base register, which is going to be | |
10670 | written to. */ | |
10671 | if (wback) | |
10672 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10673 | } |
10674 | else | |
10675 | { | |
71e396f9 LM |
10676 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
10677 | ||
72508ac0 | 10678 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
10679 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
10680 | ||
10681 | /* Handle bit U. */ | |
72508ac0 | 10682 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
10683 | { |
10684 | /* U == 1: Add the offset. */ | |
10685 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
10686 | } | |
72508ac0 | 10687 | else |
71e396f9 LM |
10688 | { |
10689 | /* U == 0: subtract the offset. */ | |
10690 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
10691 | } | |
10692 | ||
10693 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
10694 | bytes. */ | |
10695 | if (bit (arm_insn_r->arm_insn, 22)) | |
10696 | { | |
10697 | /* STRB and STRBT: 1 byte. */ | |
10698 | record_buf_mem[0] = 1; | |
10699 | } | |
10700 | else | |
10701 | { | |
10702 | /* STR and STRT: 4 bytes. */ | |
10703 | record_buf_mem[0] = 4; | |
10704 | } | |
10705 | ||
10706 | /* Handle bit P. */ | |
10707 | if (bit (arm_insn_r->arm_insn, 24)) | |
10708 | record_buf_mem[1] = tgt_mem_addr; | |
10709 | else | |
10710 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 10711 | |
72508ac0 PO |
10712 | arm_insn_r->mem_rec_count = 1; |
10713 | ||
71e396f9 LM |
10714 | /* If wback is true, also save the base register, which is going to be |
10715 | written to. */ | |
10716 | if (wback) | |
10717 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
10718 | } |
10719 | ||
10720 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10721 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10722 | return 0; | |
10723 | } | |
10724 | ||
10725 | /* Handling opcode 011 insns. */ | |
10726 | ||
10727 | static int | |
10728 | arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) | |
10729 | { | |
10730 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10731 | ||
10732 | uint32_t shift_imm = 0; | |
10733 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
10734 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
10735 | uint32_t record_buf[8], record_buf_mem[8]; | |
10736 | ||
10737 | LONGEST s_word; | |
10738 | ULONGEST u_regval[2]; | |
10739 | ||
c55978a6 YQ |
10740 | if (bit (arm_insn_r->arm_insn, 4)) |
10741 | return arm_record_media (arm_insn_r); | |
10742 | ||
72508ac0 PO |
10743 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
10744 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10745 | ||
10746 | /* Handle enhanced store insns and LDRD DSP insn, | |
10747 | order begins according to addressing modes for store insns | |
10748 | STRH insn. */ | |
10749 | ||
10750 | /* LDR or STR? */ | |
10751 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
10752 | { | |
10753 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
10754 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
10755 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
10756 | in that case, it emulates branch and link insn, and hence we | |
10757 | need to save CSPR and PC as well. */ | |
72508ac0 | 10758 | if (15 != reg_dest) |
dda83cd7 SM |
10759 | { |
10760 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10761 | arm_insn_r->reg_rec_count = 1; | |
10762 | } | |
72508ac0 | 10763 | else |
dda83cd7 SM |
10764 | { |
10765 | record_buf[0] = reg_dest; | |
10766 | record_buf[1] = ARM_PS_REGNUM; | |
10767 | arm_insn_r->reg_rec_count = 2; | |
10768 | } | |
72508ac0 PO |
10769 | } |
10770 | else | |
10771 | { | |
10772 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
10773 | { |
10774 | /* Store insn, register offset and register pre-indexed, | |
10775 | register post-indexed. */ | |
10776 | /* Get Rm. */ | |
10777 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10778 | /* Get Rn. */ | |
10779 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10780 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
10781 | , &u_regval[0]); | |
10782 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
10783 | , &u_regval[1]); | |
10784 | if (15 == reg_src2) | |
10785 | { | |
10786 | /* If R15 was used as Rn, hence current PC+8. */ | |
10787 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
10788 | u_regval[0] = u_regval[0] + 8; | |
10789 | } | |
10790 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10791 | /* U == 1. */ | |
10792 | if (bit (arm_insn_r->arm_insn, 23)) | |
10793 | { | |
10794 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10795 | } | |
10796 | else | |
10797 | { | |
10798 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10799 | } | |
10800 | ||
10801 | switch (arm_insn_r->opcode) | |
10802 | { | |
10803 | /* STR. */ | |
10804 | case 8: | |
10805 | case 12: | |
10806 | /* STR. */ | |
10807 | case 9: | |
10808 | case 13: | |
10809 | /* STRT. */ | |
10810 | case 1: | |
10811 | case 5: | |
10812 | /* STR. */ | |
10813 | case 0: | |
10814 | case 4: | |
10815 | record_buf_mem[0] = 4; | |
10816 | break; | |
10817 | ||
10818 | /* STRB. */ | |
10819 | case 10: | |
10820 | case 14: | |
10821 | /* STRB. */ | |
10822 | case 11: | |
10823 | case 15: | |
10824 | /* STRBT. */ | |
10825 | case 3: | |
10826 | case 7: | |
10827 | /* STRB. */ | |
10828 | case 2: | |
10829 | case 6: | |
10830 | record_buf_mem[0] = 1; | |
10831 | break; | |
10832 | ||
10833 | default: | |
10834 | gdb_assert_not_reached ("no decoding pattern found"); | |
10835 | break; | |
10836 | } | |
10837 | record_buf_mem[1] = tgt_mem_addr; | |
10838 | arm_insn_r->mem_rec_count = 1; | |
10839 | ||
10840 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10841 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10842 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10843 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10844 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10845 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10846 | ) | |
10847 | { | |
10848 | /* Rn is going to be changed in pre-indexed mode and | |
10849 | post-indexed mode as well. */ | |
10850 | record_buf[0] = reg_src2; | |
10851 | arm_insn_r->reg_rec_count = 1; | |
10852 | } | |
10853 | } | |
72508ac0 | 10854 | else |
dda83cd7 SM |
10855 | { |
10856 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
10857 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
10858 | /* Get Rm. */ | |
10859 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10860 | /* Get Rn. */ | |
10861 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10862 | /* Get shift_imm. */ | |
10863 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
10864 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10865 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
10866 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10867 | /* Offset_12 used as shift. */ | |
10868 | switch (offset_12) | |
10869 | { | |
10870 | case 0: | |
10871 | /* Offset_12 used as index. */ | |
10872 | offset_12 = u_regval[0] << shift_imm; | |
10873 | break; | |
10874 | ||
10875 | case 1: | |
10876 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
10877 | break; | |
10878 | ||
10879 | case 2: | |
10880 | if (!shift_imm) | |
10881 | { | |
10882 | if (bit (u_regval[0], 31)) | |
10883 | { | |
10884 | offset_12 = 0xFFFFFFFF; | |
10885 | } | |
10886 | else | |
10887 | { | |
10888 | offset_12 = 0; | |
10889 | } | |
10890 | } | |
10891 | else | |
10892 | { | |
10893 | /* This is arithmetic shift. */ | |
10894 | offset_12 = s_word >> shift_imm; | |
10895 | } | |
10896 | break; | |
10897 | ||
10898 | case 3: | |
10899 | if (!shift_imm) | |
10900 | { | |
10901 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
10902 | &u_regval[1]); | |
10903 | /* Get C flag value and shift it by 31. */ | |
10904 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
10905 | | (u_regval[0]) >> 1); | |
10906 | } | |
10907 | else | |
10908 | { | |
10909 | offset_12 = (u_regval[0] >> shift_imm) \ | |
10910 | | (u_regval[0] << | |
10911 | (sizeof(uint32_t) - shift_imm)); | |
10912 | } | |
10913 | break; | |
10914 | ||
10915 | default: | |
10916 | gdb_assert_not_reached ("no decoding pattern found"); | |
10917 | break; | |
10918 | } | |
10919 | ||
10920 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10921 | /* bit U set. */ | |
10922 | if (bit (arm_insn_r->arm_insn, 23)) | |
10923 | { | |
10924 | tgt_mem_addr = u_regval[1] + offset_12; | |
10925 | } | |
10926 | else | |
10927 | { | |
10928 | tgt_mem_addr = u_regval[1] - offset_12; | |
10929 | } | |
10930 | ||
10931 | switch (arm_insn_r->opcode) | |
10932 | { | |
10933 | /* STR. */ | |
10934 | case 8: | |
10935 | case 12: | |
10936 | /* STR. */ | |
10937 | case 9: | |
10938 | case 13: | |
10939 | /* STRT. */ | |
10940 | case 1: | |
10941 | case 5: | |
10942 | /* STR. */ | |
10943 | case 0: | |
10944 | case 4: | |
10945 | record_buf_mem[0] = 4; | |
10946 | break; | |
10947 | ||
10948 | /* STRB. */ | |
10949 | case 10: | |
10950 | case 14: | |
10951 | /* STRB. */ | |
10952 | case 11: | |
10953 | case 15: | |
10954 | /* STRBT. */ | |
10955 | case 3: | |
10956 | case 7: | |
10957 | /* STRB. */ | |
10958 | case 2: | |
10959 | case 6: | |
10960 | record_buf_mem[0] = 1; | |
10961 | break; | |
10962 | ||
10963 | default: | |
10964 | gdb_assert_not_reached ("no decoding pattern found"); | |
10965 | break; | |
10966 | } | |
10967 | record_buf_mem[1] = tgt_mem_addr; | |
10968 | arm_insn_r->mem_rec_count = 1; | |
10969 | ||
10970 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
10971 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
10972 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
10973 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
10974 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
10975 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
10976 | ) | |
10977 | { | |
10978 | /* Rn is going to be changed in register scaled pre-indexed | |
10979 | mode,and scaled post indexed mode. */ | |
10980 | record_buf[0] = reg_src2; | |
10981 | arm_insn_r->reg_rec_count = 1; | |
10982 | } | |
10983 | } | |
72508ac0 PO |
10984 | } |
10985 | ||
10986 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10987 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10988 | return 0; | |
10989 | } | |
10990 | ||
71e396f9 | 10991 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
10992 | |
10993 | static int | |
10994 | arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) | |
10995 | { | |
10996 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
10997 | uint32_t register_count = 0, register_bits; |
10998 | uint32_t reg_base, addr_mode; | |
72508ac0 | 10999 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
11000 | uint32_t wback; |
11001 | ULONGEST u_regval; | |
72508ac0 | 11002 | |
71e396f9 LM |
11003 | /* Fetch the list of registers. */ |
11004 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
11005 | arm_insn_r->reg_rec_count = 0; | |
11006 | ||
11007 | /* Fetch the base register that contains the address we are loading data | |
11008 | to. */ | |
11009 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11010 | |
71e396f9 LM |
11011 | /* Calculate wback. */ |
11012 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
11013 | |
11014 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11015 | { | |
71e396f9 | 11016 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 11017 | |
71e396f9 | 11018 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 11019 | while (register_bits) |
71e396f9 LM |
11020 | { |
11021 | if (register_bits & 0x00000001) | |
11022 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
11023 | register_bits = register_bits >> 1; | |
11024 | register_count++; | |
11025 | } | |
72508ac0 | 11026 | |
71e396f9 LM |
11027 | |
11028 | /* If wback is true, also save the base register, which is going to be | |
11029 | written to. */ | |
11030 | if (wback) | |
11031 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
11032 | ||
11033 | /* Save the CPSR register. */ | |
11034 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
11035 | } |
11036 | else | |
11037 | { | |
71e396f9 | 11038 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 11039 | |
71e396f9 LM |
11040 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
11041 | ||
11042 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
11043 | ||
11044 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 11045 | while (register_bits) |
71e396f9 LM |
11046 | { |
11047 | if (register_bits & 0x00000001) | |
11048 | register_count++; | |
11049 | register_bits = register_bits >> 1; | |
11050 | } | |
72508ac0 PO |
11051 | |
11052 | switch (addr_mode) | |
71e396f9 LM |
11053 | { |
11054 | /* STMDA (STMED): Decrement after. */ | |
11055 | case 0: | |
11056 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11057 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
11058 | break; |
11059 | /* STM (STMIA, STMEA): Increment after. */ | |
11060 | case 1: | |
11061 | record_buf_mem[1] = (uint32_t) u_regval; | |
11062 | break; | |
11063 | /* STMDB (STMFD): Decrement before. */ | |
11064 | case 2: | |
11065 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11066 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11067 | break; |
11068 | /* STMIB (STMFA): Increment before. */ | |
11069 | case 3: | |
f0452268 | 11070 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11071 | break; |
11072 | default: | |
11073 | gdb_assert_not_reached ("no decoding pattern found"); | |
11074 | break; | |
11075 | } | |
72508ac0 | 11076 | |
f0452268 | 11077 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11078 | arm_insn_r->mem_rec_count = 1; |
11079 | ||
11080 | /* If wback is true, also save the base register, which is going to be | |
11081 | written to. */ | |
11082 | if (wback) | |
11083 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11084 | } |
11085 | ||
11086 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11087 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11088 | return 0; | |
11089 | } | |
11090 | ||
11091 | /* Handling opcode 101 insns. */ | |
11092 | ||
11093 | static int | |
11094 | arm_record_b_bl (insn_decode_record *arm_insn_r) | |
11095 | { | |
11096 | uint32_t record_buf[8]; | |
11097 | ||
11098 | /* Handle B, BL, BLX(1) insns. */ | |
11099 | /* B simply branches so we do nothing here. */ | |
11100 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
11101 | extension space. */ | |
11102 | if (bit (arm_insn_r->arm_insn, 24)) | |
11103 | { | |
11104 | record_buf[0] = ARM_LR_REGNUM; | |
11105 | arm_insn_r->reg_rec_count = 1; | |
11106 | } | |
11107 | ||
11108 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11109 | ||
11110 | return 0; | |
11111 | } | |
11112 | ||
72508ac0 | 11113 | static int |
c6ec2b30 | 11114 | arm_record_unsupported_insn (insn_decode_record *arm_insn_r) |
72508ac0 PO |
11115 | { |
11116 | printf_unfiltered (_("Process record does not support instruction " | |
01e57735 YQ |
11117 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, |
11118 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
11119 | |
11120 | return -1; | |
11121 | } | |
11122 | ||
5a578da5 OJ |
11123 | /* Record handler for vector data transfer instructions. */ |
11124 | ||
11125 | static int | |
11126 | arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) | |
11127 | { | |
11128 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
11129 | uint32_t record_buf[4]; | |
11130 | ||
5a578da5 OJ |
11131 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
11132 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
11133 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
11134 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
11135 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
11136 | ||
11137 | /* Handle VMOV instruction. */ | |
11138 | if (bit_l && bit_c) | |
11139 | { | |
11140 | record_buf[0] = reg_t; | |
11141 | arm_insn_r->reg_rec_count = 1; | |
11142 | } | |
11143 | else if (bit_l && !bit_c) | |
11144 | { | |
11145 | /* Handle VMOV instruction. */ | |
11146 | if (bits_a == 0x00) | |
dda83cd7 | 11147 | { |
f1771dce | 11148 | record_buf[0] = reg_t; |
dda83cd7 SM |
11149 | arm_insn_r->reg_rec_count = 1; |
11150 | } | |
5a578da5 OJ |
11151 | /* Handle VMRS instruction. */ |
11152 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11153 | { |
11154 | if (reg_t == 15) | |
11155 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 11156 | |
dda83cd7 SM |
11157 | record_buf[0] = reg_t; |
11158 | arm_insn_r->reg_rec_count = 1; | |
11159 | } | |
5a578da5 OJ |
11160 | } |
11161 | else if (!bit_l && !bit_c) | |
11162 | { | |
11163 | /* Handle VMOV instruction. */ | |
11164 | if (bits_a == 0x00) | |
dda83cd7 | 11165 | { |
f1771dce | 11166 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 11167 | |
dda83cd7 SM |
11168 | arm_insn_r->reg_rec_count = 1; |
11169 | } | |
5a578da5 OJ |
11170 | /* Handle VMSR instruction. */ |
11171 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11172 | { |
11173 | record_buf[0] = ARM_FPSCR_REGNUM; | |
11174 | arm_insn_r->reg_rec_count = 1; | |
11175 | } | |
5a578da5 OJ |
11176 | } |
11177 | else if (!bit_l && bit_c) | |
11178 | { | |
11179 | /* Handle VMOV instruction. */ | |
11180 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
11181 | { |
11182 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
11183 | + ARM_D0_REGNUM; | |
11184 | arm_insn_r->reg_rec_count = 1; | |
11185 | } | |
5a578da5 OJ |
11186 | /* Handle VDUP instruction. */ |
11187 | else | |
dda83cd7 SM |
11188 | { |
11189 | if (bit (arm_insn_r->arm_insn, 21)) | |
11190 | { | |
11191 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11192 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11193 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
11194 | arm_insn_r->reg_rec_count = 2; | |
11195 | } | |
11196 | else | |
11197 | { | |
11198 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11199 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11200 | arm_insn_r->reg_rec_count = 1; | |
11201 | } | |
11202 | } | |
11203 | } | |
11204 | ||
11205 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11206 | return 0; | |
11207 | } | |
11208 | ||
f20f80dd OJ |
11209 | /* Record handler for extension register load/store instructions. */ |
11210 | ||
11211 | static int | |
11212 | arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) | |
11213 | { | |
11214 | uint32_t opcode, single_reg; | |
11215 | uint8_t op_vldm_vstm; | |
11216 | uint32_t record_buf[8], record_buf_mem[128]; | |
11217 | ULONGEST u_regval = 0; | |
11218 | ||
11219 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
11220 | |
11221 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 11222 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
11223 | op_vldm_vstm = opcode & 0x1b; |
11224 | ||
11225 | /* Handle VMOV instructions. */ | |
11226 | if ((opcode & 0x1e) == 0x04) | |
11227 | { | |
9fde51ed | 11228 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
11229 | { |
11230 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11231 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11232 | arm_insn_r->reg_rec_count = 2; | |
11233 | } | |
f20f80dd | 11234 | else |
01e57735 | 11235 | { |
9fde51ed YQ |
11236 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
11237 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 11238 | |
9fde51ed | 11239 | if (single_reg) |
01e57735 | 11240 | { |
9fde51ed YQ |
11241 | /* The first S register number m is REG_M:M (M is bit 5), |
11242 | the corresponding D register number is REG_M:M / 2, which | |
11243 | is REG_M. */ | |
11244 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
11245 | /* The second S register number is REG_M:M + 1, the | |
11246 | corresponding D register number is (REG_M:M + 1) / 2. | |
11247 | IOW, if bit M is 1, the first and second S registers | |
11248 | are mapped to different D registers, otherwise, they are | |
11249 | in the same D register. */ | |
11250 | if (bit_m) | |
11251 | { | |
11252 | record_buf[arm_insn_r->reg_rec_count++] | |
11253 | = ARM_D0_REGNUM + reg_m + 1; | |
11254 | } | |
01e57735 YQ |
11255 | } |
11256 | else | |
11257 | { | |
9fde51ed | 11258 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
11259 | arm_insn_r->reg_rec_count = 1; |
11260 | } | |
11261 | } | |
f20f80dd OJ |
11262 | } |
11263 | /* Handle VSTM and VPUSH instructions. */ | |
11264 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 11265 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
11266 | { |
11267 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
11268 | uint32_t memory_index = 0; | |
11269 | ||
11270 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11271 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11272 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11273 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11274 | memory_count = imm_off8; |
11275 | ||
11276 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11277 | start_address = u_regval; |
f20f80dd | 11278 | else |
01e57735 | 11279 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11280 | |
11281 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
11282 | { |
11283 | record_buf[0] = reg_rn; | |
11284 | arm_insn_r->reg_rec_count = 1; | |
11285 | } | |
f20f80dd OJ |
11286 | |
11287 | while (memory_count > 0) | |
01e57735 | 11288 | { |
9fde51ed | 11289 | if (single_reg) |
01e57735 | 11290 | { |
9fde51ed YQ |
11291 | record_buf_mem[memory_index] = 4; |
11292 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11293 | start_address = start_address + 4; |
11294 | memory_index = memory_index + 2; | |
11295 | } | |
11296 | else | |
11297 | { | |
9fde51ed YQ |
11298 | record_buf_mem[memory_index] = 4; |
11299 | record_buf_mem[memory_index + 1] = start_address; | |
11300 | record_buf_mem[memory_index + 2] = 4; | |
11301 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11302 | start_address = start_address + 8; |
11303 | memory_index = memory_index + 4; | |
11304 | } | |
11305 | memory_count--; | |
11306 | } | |
f20f80dd OJ |
11307 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
11308 | } | |
11309 | /* Handle VLDM instructions. */ | |
11310 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 11311 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
11312 | { |
11313 | uint32_t reg_count, reg_vd; | |
11314 | uint32_t reg_index = 0; | |
9fde51ed | 11315 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
11316 | |
11317 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11318 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
11319 | ||
9fde51ed YQ |
11320 | /* REG_VD is the first D register number. If the instruction |
11321 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
11322 | number is (REG_VD << 1 | bit D), so the corresponding D | |
11323 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
11324 | if (!single_reg) | |
11325 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 11326 | |
9fde51ed | 11327 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 11328 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 11329 | |
9fde51ed YQ |
11330 | /* If the instruction loads memory to D register, REG_COUNT should |
11331 | be divided by 2, according to the ARM Architecture Reference | |
11332 | Manual. If the instruction loads memory to S register, divide by | |
11333 | 2 as well because two S registers are mapped to D register. */ | |
11334 | reg_count = reg_count / 2; | |
11335 | if (single_reg && bit_d) | |
01e57735 | 11336 | { |
9fde51ed YQ |
11337 | /* Increase the register count if S register list starts from |
11338 | an odd number (bit d is one). */ | |
11339 | reg_count++; | |
11340 | } | |
f20f80dd | 11341 | |
9fde51ed YQ |
11342 | while (reg_count > 0) |
11343 | { | |
11344 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
11345 | reg_count--; |
11346 | } | |
f20f80dd OJ |
11347 | arm_insn_r->reg_rec_count = reg_index; |
11348 | } | |
11349 | /* VSTR Vector store register. */ | |
11350 | else if ((opcode & 0x13) == 0x10) | |
11351 | { | |
bec2ab5a | 11352 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
11353 | uint32_t memory_index = 0; |
11354 | ||
11355 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11356 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11357 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11358 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11359 | |
11360 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11361 | start_address = u_regval + imm_off32; |
f20f80dd | 11362 | else |
01e57735 | 11363 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11364 | |
11365 | if (single_reg) | |
01e57735 | 11366 | { |
9fde51ed YQ |
11367 | record_buf_mem[memory_index] = 4; |
11368 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11369 | arm_insn_r->mem_rec_count = 1; |
11370 | } | |
f20f80dd | 11371 | else |
01e57735 | 11372 | { |
9fde51ed YQ |
11373 | record_buf_mem[memory_index] = 4; |
11374 | record_buf_mem[memory_index + 1] = start_address; | |
11375 | record_buf_mem[memory_index + 2] = 4; | |
11376 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11377 | arm_insn_r->mem_rec_count = 2; |
11378 | } | |
f20f80dd OJ |
11379 | } |
11380 | /* VLDR Vector load register. */ | |
11381 | else if ((opcode & 0x13) == 0x11) | |
11382 | { | |
11383 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11384 | ||
11385 | if (!single_reg) | |
01e57735 YQ |
11386 | { |
11387 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
11388 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
11389 | } | |
f20f80dd | 11390 | else |
01e57735 YQ |
11391 | { |
11392 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
11393 | /* Record register D rather than pseudo register S. */ |
11394 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 11395 | } |
f20f80dd OJ |
11396 | arm_insn_r->reg_rec_count = 1; |
11397 | } | |
11398 | ||
11399 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11400 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11401 | return 0; | |
11402 | } | |
11403 | ||
851f26ae OJ |
11404 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
11405 | ||
11406 | static int | |
11407 | arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) | |
11408 | { | |
11409 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
11410 | uint32_t record_buf[4]; | |
11411 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
11412 | enum insn_types curr_insn_type = INSN_INV; | |
11413 | ||
11414 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11415 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11416 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11417 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
11418 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
11419 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
11420 | /* Mask off the "D" bit. */ |
11421 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
11422 | |
11423 | /* Handle VMLA, VMLS. */ | |
11424 | if (opc1 == 0x00) | |
11425 | { | |
11426 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11427 | { |
11428 | if (bit (arm_insn_r->arm_insn, 6)) | |
11429 | curr_insn_type = INSN_T0; | |
11430 | else | |
11431 | curr_insn_type = INSN_T1; | |
11432 | } | |
851f26ae | 11433 | else |
dda83cd7 SM |
11434 | { |
11435 | if (dp_op_sz) | |
11436 | curr_insn_type = INSN_T1; | |
11437 | else | |
11438 | curr_insn_type = INSN_T2; | |
11439 | } | |
851f26ae OJ |
11440 | } |
11441 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
11442 | else if (opc1 == 0x01) | |
11443 | { | |
11444 | if (dp_op_sz) | |
dda83cd7 | 11445 | curr_insn_type = INSN_T1; |
851f26ae | 11446 | else |
dda83cd7 | 11447 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11448 | } |
11449 | /* Handle VMUL. */ | |
11450 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
11451 | { | |
11452 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11453 | { |
11454 | if (bit (arm_insn_r->arm_insn, 6)) | |
11455 | curr_insn_type = INSN_T0; | |
11456 | else | |
11457 | curr_insn_type = INSN_T1; | |
11458 | } | |
851f26ae | 11459 | else |
dda83cd7 SM |
11460 | { |
11461 | if (dp_op_sz) | |
11462 | curr_insn_type = INSN_T1; | |
11463 | else | |
11464 | curr_insn_type = INSN_T2; | |
11465 | } | |
851f26ae OJ |
11466 | } |
11467 | /* Handle VADD, VSUB. */ | |
11468 | else if (opc1 == 0x03) | |
11469 | { | |
11470 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
11471 | { |
11472 | if (bit (arm_insn_r->arm_insn, 6)) | |
11473 | curr_insn_type = INSN_T0; | |
11474 | else | |
11475 | curr_insn_type = INSN_T1; | |
11476 | } | |
851f26ae | 11477 | else |
dda83cd7 SM |
11478 | { |
11479 | if (dp_op_sz) | |
11480 | curr_insn_type = INSN_T1; | |
11481 | else | |
11482 | curr_insn_type = INSN_T2; | |
11483 | } | |
851f26ae OJ |
11484 | } |
11485 | /* Handle VDIV. */ | |
ce887586 | 11486 | else if (opc1 == 0x08) |
851f26ae OJ |
11487 | { |
11488 | if (dp_op_sz) | |
dda83cd7 | 11489 | curr_insn_type = INSN_T1; |
851f26ae | 11490 | else |
dda83cd7 | 11491 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11492 | } |
11493 | /* Handle all other vfp data processing instructions. */ | |
11494 | else if (opc1 == 0x0b) | |
11495 | { | |
11496 | /* Handle VMOV. */ | |
11497 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
11498 | { |
11499 | if (bit (arm_insn_r->arm_insn, 4)) | |
11500 | { | |
11501 | if (bit (arm_insn_r->arm_insn, 6)) | |
11502 | curr_insn_type = INSN_T0; | |
11503 | else | |
11504 | curr_insn_type = INSN_T1; | |
11505 | } | |
11506 | else | |
11507 | { | |
11508 | if (dp_op_sz) | |
11509 | curr_insn_type = INSN_T1; | |
11510 | else | |
11511 | curr_insn_type = INSN_T2; | |
11512 | } | |
11513 | } | |
851f26ae OJ |
11514 | /* Handle VNEG and VABS. */ |
11515 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
11516 | || (opc2 == 0x00 && opc3 == 0x03)) |
11517 | { | |
11518 | if (!bit (arm_insn_r->arm_insn, 11)) | |
11519 | { | |
11520 | if (bit (arm_insn_r->arm_insn, 6)) | |
11521 | curr_insn_type = INSN_T0; | |
11522 | else | |
11523 | curr_insn_type = INSN_T1; | |
11524 | } | |
11525 | else | |
11526 | { | |
11527 | if (dp_op_sz) | |
11528 | curr_insn_type = INSN_T1; | |
11529 | else | |
11530 | curr_insn_type = INSN_T2; | |
11531 | } | |
11532 | } | |
851f26ae OJ |
11533 | /* Handle VSQRT. */ |
11534 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
11535 | { |
11536 | if (dp_op_sz) | |
11537 | curr_insn_type = INSN_T1; | |
11538 | else | |
11539 | curr_insn_type = INSN_T2; | |
11540 | } | |
851f26ae OJ |
11541 | /* Handle VCVT. */ |
11542 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
11543 | { |
11544 | if (!dp_op_sz) | |
11545 | curr_insn_type = INSN_T1; | |
11546 | else | |
11547 | curr_insn_type = INSN_T2; | |
11548 | } | |
851f26ae | 11549 | else if (opc3 & 0x01) |
dda83cd7 SM |
11550 | { |
11551 | /* Handle VCVT. */ | |
11552 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
11553 | { | |
11554 | if (!bit (arm_insn_r->arm_insn, 18)) | |
11555 | curr_insn_type = INSN_T2; | |
11556 | else | |
11557 | { | |
11558 | if (dp_op_sz) | |
11559 | curr_insn_type = INSN_T1; | |
11560 | else | |
11561 | curr_insn_type = INSN_T2; | |
11562 | } | |
11563 | } | |
11564 | /* Handle VCVT. */ | |
11565 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
11566 | { | |
11567 | if (dp_op_sz) | |
11568 | curr_insn_type = INSN_T1; | |
11569 | else | |
11570 | curr_insn_type = INSN_T2; | |
11571 | } | |
11572 | /* Handle VCVTB, VCVTT. */ | |
11573 | else if ((opc2 & 0x0e) == 0x02) | |
11574 | curr_insn_type = INSN_T2; | |
11575 | /* Handle VCMP, VCMPE. */ | |
11576 | else if ((opc2 & 0x0e) == 0x04) | |
11577 | curr_insn_type = INSN_T3; | |
11578 | } | |
851f26ae OJ |
11579 | } |
11580 | ||
11581 | switch (curr_insn_type) | |
11582 | { | |
11583 | case INSN_T0: | |
dda83cd7 SM |
11584 | reg_vd = reg_vd | (bit_d << 4); |
11585 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11586 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
11587 | arm_insn_r->reg_rec_count = 2; | |
11588 | break; | |
851f26ae OJ |
11589 | |
11590 | case INSN_T1: | |
dda83cd7 SM |
11591 | reg_vd = reg_vd | (bit_d << 4); |
11592 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11593 | arm_insn_r->reg_rec_count = 1; | |
11594 | break; | |
851f26ae OJ |
11595 | |
11596 | case INSN_T2: | |
dda83cd7 SM |
11597 | reg_vd = (reg_vd << 1) | bit_d; |
11598 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
11599 | arm_insn_r->reg_rec_count = 1; | |
11600 | break; | |
851f26ae OJ |
11601 | |
11602 | case INSN_T3: | |
dda83cd7 SM |
11603 | record_buf[0] = ARM_FPSCR_REGNUM; |
11604 | arm_insn_r->reg_rec_count = 1; | |
11605 | break; | |
851f26ae OJ |
11606 | |
11607 | default: | |
dda83cd7 SM |
11608 | gdb_assert_not_reached ("no decoding pattern found"); |
11609 | break; | |
851f26ae OJ |
11610 | } |
11611 | ||
11612 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11613 | return 0; | |
11614 | } | |
11615 | ||
60cc5e93 OJ |
11616 | /* Handling opcode 110 insns. */ |
11617 | ||
11618 | static int | |
11619 | arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) | |
11620 | { | |
bec2ab5a | 11621 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
11622 | |
11623 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
11624 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
11625 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
11626 | ||
11627 | if ((coproc & 0x0e) == 0x0a) | |
11628 | { | |
11629 | /* Handle extension register ld/st instructions. */ | |
11630 | if (!(op1 & 0x20)) | |
dda83cd7 | 11631 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11632 | |
11633 | /* 64-bit transfers between arm core and extension registers. */ | |
11634 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 11635 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
11636 | } |
11637 | else | |
11638 | { | |
11639 | /* Handle coprocessor ld/st instructions. */ | |
11640 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
11641 | { |
11642 | /* Store. */ | |
11643 | if (!op1_ebit) | |
11644 | return arm_record_unsupported_insn (arm_insn_r); | |
11645 | else | |
11646 | /* Load. */ | |
11647 | return arm_record_unsupported_insn (arm_insn_r); | |
11648 | } | |
60cc5e93 OJ |
11649 | |
11650 | /* Move to coprocessor from two arm core registers. */ | |
11651 | if (op1 == 0x4) | |
dda83cd7 | 11652 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
11653 | |
11654 | /* Move to two arm core registers from coprocessor. */ | |
11655 | if (op1 == 0x5) | |
dda83cd7 SM |
11656 | { |
11657 | uint32_t reg_t[2]; | |
60cc5e93 | 11658 | |
dda83cd7 SM |
11659 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11660 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11661 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 11662 | |
dda83cd7 SM |
11663 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
11664 | return 0; | |
60cc5e93 OJ |
11665 | } |
11666 | } | |
11667 | return arm_record_unsupported_insn (arm_insn_r); | |
11668 | } | |
11669 | ||
72508ac0 PO |
11670 | /* Handling opcode 111 insns. */ |
11671 | ||
11672 | static int | |
11673 | arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) | |
11674 | { | |
2d9e6acb | 11675 | uint32_t op, op1_ebit, coproc, bits_24_25; |
72508ac0 PO |
11676 | struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); |
11677 | struct regcache *reg_cache = arm_insn_r->regcache; | |
72508ac0 PO |
11678 | |
11679 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 11680 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
11681 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
11682 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 11683 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
11684 | |
11685 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 11686 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
11687 | { |
11688 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
11689 | { |
11690 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 11691 | |
dda83cd7 | 11692 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 11693 | |
dda83cd7 SM |
11694 | if (svc_operand) /* OABI. */ |
11695 | svc_number = svc_operand - 0x900000; | |
11696 | else /* EABI. */ | |
11697 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 11698 | |
dda83cd7 SM |
11699 | return tdep->arm_syscall_record (reg_cache, svc_number); |
11700 | } | |
97dfe206 | 11701 | else |
dda83cd7 SM |
11702 | { |
11703 | printf_unfiltered (_("no syscall record support\n")); | |
11704 | return -1; | |
11705 | } | |
97dfe206 | 11706 | } |
2d9e6acb | 11707 | else if (bits_24_25 == 0x02) |
60cc5e93 | 11708 | { |
2d9e6acb YQ |
11709 | if (op) |
11710 | { | |
11711 | if ((coproc & 0x0e) == 0x0a) | |
11712 | { | |
11713 | /* 8, 16, and 32-bit transfer */ | |
11714 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
11715 | } | |
11716 | else | |
11717 | { | |
11718 | if (op1_ebit) | |
11719 | { | |
11720 | /* MRC, MRC2 */ | |
11721 | uint32_t record_buf[1]; | |
11722 | ||
11723 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11724 | if (record_buf[0] == 15) | |
11725 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 11726 | |
2d9e6acb YQ |
11727 | arm_insn_r->reg_rec_count = 1; |
11728 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
11729 | record_buf); | |
11730 | return 0; | |
11731 | } | |
11732 | else | |
11733 | { | |
11734 | /* MCR, MCR2 */ | |
11735 | return -1; | |
11736 | } | |
11737 | } | |
11738 | } | |
11739 | else | |
11740 | { | |
11741 | if ((coproc & 0x0e) == 0x0a) | |
11742 | { | |
11743 | /* VFP data-processing instructions. */ | |
11744 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
11745 | } | |
11746 | else | |
11747 | { | |
11748 | /* CDP, CDP2 */ | |
11749 | return -1; | |
11750 | } | |
11751 | } | |
60cc5e93 | 11752 | } |
97dfe206 OJ |
11753 | else |
11754 | { | |
2d9e6acb | 11755 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 11756 | |
2d9e6acb YQ |
11757 | if (op1 == 5) |
11758 | { | |
11759 | if ((coproc & 0x0e) != 0x0a) | |
11760 | { | |
11761 | /* MRRC, MRRC2 */ | |
11762 | return -1; | |
11763 | } | |
11764 | } | |
11765 | else if (op1 == 4 || op1 == 5) | |
11766 | { | |
11767 | if ((coproc & 0x0e) == 0x0a) | |
11768 | { | |
11769 | /* 64-bit transfers between ARM core and extension */ | |
11770 | return -1; | |
11771 | } | |
11772 | else if (op1 == 4) | |
11773 | { | |
11774 | /* MCRR, MCRR2 */ | |
11775 | return -1; | |
11776 | } | |
11777 | } | |
11778 | else if (op1 == 0 || op1 == 1) | |
11779 | { | |
11780 | /* UNDEFINED */ | |
11781 | return -1; | |
11782 | } | |
11783 | else | |
11784 | { | |
11785 | if ((coproc & 0x0e) == 0x0a) | |
11786 | { | |
11787 | /* Extension register load/store */ | |
11788 | } | |
11789 | else | |
11790 | { | |
11791 | /* STC, STC2, LDC, LDC2 */ | |
11792 | } | |
11793 | return -1; | |
11794 | } | |
97dfe206 | 11795 | } |
72508ac0 | 11796 | |
2d9e6acb | 11797 | return -1; |
72508ac0 PO |
11798 | } |
11799 | ||
11800 | /* Handling opcode 000 insns. */ | |
11801 | ||
11802 | static int | |
11803 | thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) | |
11804 | { | |
11805 | uint32_t record_buf[8]; | |
11806 | uint32_t reg_src1 = 0; | |
11807 | ||
11808 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11809 | ||
11810 | record_buf[0] = ARM_PS_REGNUM; | |
11811 | record_buf[1] = reg_src1; | |
11812 | thumb_insn_r->reg_rec_count = 2; | |
11813 | ||
11814 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11815 | ||
11816 | return 0; | |
11817 | } | |
11818 | ||
11819 | ||
11820 | /* Handling opcode 001 insns. */ | |
11821 | ||
11822 | static int | |
11823 | thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) | |
11824 | { | |
11825 | uint32_t record_buf[8]; | |
11826 | uint32_t reg_src1 = 0; | |
11827 | ||
11828 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11829 | ||
11830 | record_buf[0] = ARM_PS_REGNUM; | |
11831 | record_buf[1] = reg_src1; | |
11832 | thumb_insn_r->reg_rec_count = 2; | |
11833 | ||
11834 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11835 | ||
11836 | return 0; | |
11837 | } | |
11838 | ||
11839 | /* Handling opcode 010 insns. */ | |
11840 | ||
11841 | static int | |
11842 | thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) | |
11843 | { | |
11844 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11845 | uint32_t record_buf[8], record_buf_mem[8]; | |
11846 | ||
11847 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
11848 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
11849 | ||
11850 | ULONGEST u_regval[2] = {0}; | |
11851 | ||
11852 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
11853 | ||
11854 | if (bit (thumb_insn_r->arm_insn, 12)) | |
11855 | { | |
11856 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
11857 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
11858 | ||
b020ff80 | 11859 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
11860 | { |
11861 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
11862 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
11863 | record_buf[0] = reg_src1; | |
11864 | thumb_insn_r->reg_rec_count = 1; | |
11865 | } | |
b020ff80 | 11866 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
11867 | { |
11868 | /* STR(2), STRB(2), STRH(2) . */ | |
11869 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11870 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
11871 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11872 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11873 | if (0 == opB) | |
11874 | record_buf_mem[0] = 4; /* STR (2). */ | |
11875 | else if (2 == opB) | |
11876 | record_buf_mem[0] = 1; /* STRB (2). */ | |
11877 | else if (1 == opB) | |
11878 | record_buf_mem[0] = 2; /* STRH (2). */ | |
11879 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
11880 | thumb_insn_r->mem_rec_count = 1; | |
11881 | } | |
72508ac0 PO |
11882 | } |
11883 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
11884 | { | |
11885 | /* Handle load from literal pool. */ | |
11886 | /* LDR(3). */ | |
11887 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11888 | record_buf[0] = reg_src1; | |
11889 | thumb_insn_r->reg_rec_count = 1; | |
11890 | } | |
11891 | else if (opcode1) | |
11892 | { | |
b121eeb9 | 11893 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
11894 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
11895 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11896 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
11897 | { |
11898 | /* Branch with exchange. */ | |
11899 | record_buf[0] = ARM_PS_REGNUM; | |
11900 | thumb_insn_r->reg_rec_count = 1; | |
11901 | } | |
72508ac0 | 11902 | else |
dda83cd7 | 11903 | { |
1f33efec YQ |
11904 | /* Format 8; special data processing insns. */ |
11905 | record_buf[0] = ARM_PS_REGNUM; | |
11906 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
11907 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
11908 | thumb_insn_r->reg_rec_count = 2; |
11909 | } | |
72508ac0 PO |
11910 | } |
11911 | else | |
11912 | { | |
11913 | /* Format 5; data processing insns. */ | |
11914 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11915 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
11916 | { |
11917 | reg_src1 = reg_src1 + 8; | |
11918 | } | |
72508ac0 PO |
11919 | record_buf[0] = ARM_PS_REGNUM; |
11920 | record_buf[1] = reg_src1; | |
11921 | thumb_insn_r->reg_rec_count = 2; | |
11922 | } | |
11923 | ||
11924 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11925 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 11926 | record_buf_mem); |
72508ac0 PO |
11927 | |
11928 | return 0; | |
11929 | } | |
11930 | ||
11931 | /* Handling opcode 001 insns. */ | |
11932 | ||
11933 | static int | |
11934 | thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) | |
11935 | { | |
11936 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11937 | uint32_t record_buf[8], record_buf_mem[8]; | |
11938 | ||
11939 | uint32_t reg_src1 = 0; | |
11940 | uint32_t opcode = 0, immed_5 = 0; | |
11941 | ||
11942 | ULONGEST u_regval = 0; | |
11943 | ||
11944 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11945 | ||
11946 | if (opcode) | |
11947 | { | |
11948 | /* LDR(1). */ | |
11949 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11950 | record_buf[0] = reg_src1; | |
11951 | thumb_insn_r->reg_rec_count = 1; | |
11952 | } | |
11953 | else | |
11954 | { | |
11955 | /* STR(1). */ | |
11956 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
11957 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
11958 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11959 | record_buf_mem[0] = 4; | |
11960 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
11961 | thumb_insn_r->mem_rec_count = 1; | |
11962 | } | |
11963 | ||
11964 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
11965 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 11966 | record_buf_mem); |
72508ac0 PO |
11967 | |
11968 | return 0; | |
11969 | } | |
11970 | ||
11971 | /* Handling opcode 100 insns. */ | |
11972 | ||
11973 | static int | |
11974 | thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) | |
11975 | { | |
11976 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
11977 | uint32_t record_buf[8], record_buf_mem[8]; | |
11978 | ||
11979 | uint32_t reg_src1 = 0; | |
11980 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
11981 | ||
11982 | ULONGEST u_regval = 0; | |
11983 | ||
11984 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
11985 | ||
11986 | if (3 == opcode) | |
11987 | { | |
11988 | /* LDR(4). */ | |
11989 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
11990 | record_buf[0] = reg_src1; | |
11991 | thumb_insn_r->reg_rec_count = 1; | |
11992 | } | |
11993 | else if (1 == opcode) | |
11994 | { | |
11995 | /* LDRH(1). */ | |
11996 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
11997 | record_buf[0] = reg_src1; | |
11998 | thumb_insn_r->reg_rec_count = 1; | |
11999 | } | |
12000 | else if (2 == opcode) | |
12001 | { | |
12002 | /* STR(3). */ | |
12003 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
12004 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12005 | record_buf_mem[0] = 4; | |
12006 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
12007 | thumb_insn_r->mem_rec_count = 1; | |
12008 | } | |
12009 | else if (0 == opcode) | |
12010 | { | |
12011 | /* STRH(1). */ | |
12012 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12013 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12014 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12015 | record_buf_mem[0] = 2; | |
12016 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
12017 | thumb_insn_r->mem_rec_count = 1; | |
12018 | } | |
12019 | ||
12020 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12021 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12022 | record_buf_mem); |
72508ac0 PO |
12023 | |
12024 | return 0; | |
12025 | } | |
12026 | ||
12027 | /* Handling opcode 101 insns. */ | |
12028 | ||
12029 | static int | |
12030 | thumb_record_misc (insn_decode_record *thumb_insn_r) | |
12031 | { | |
12032 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12033 | ||
b121eeb9 | 12034 | uint32_t opcode = 0; |
72508ac0 | 12035 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 12036 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12037 | uint32_t record_buf[24], record_buf_mem[48]; |
12038 | uint32_t reg_src1; | |
12039 | ||
12040 | ULONGEST u_regval = 0; | |
12041 | ||
12042 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 12043 | |
b121eeb9 | 12044 | if (opcode == 0 || opcode == 1) |
72508ac0 | 12045 | { |
b121eeb9 YQ |
12046 | /* ADR and ADD (SP plus immediate) */ |
12047 | ||
72508ac0 PO |
12048 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
12049 | record_buf[0] = reg_src1; | |
12050 | thumb_insn_r->reg_rec_count = 1; | |
12051 | } | |
b121eeb9 | 12052 | else |
72508ac0 | 12053 | { |
b121eeb9 YQ |
12054 | /* Miscellaneous 16-bit instructions */ |
12055 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
12056 | ||
12057 | switch (opcode2) | |
12058 | { | |
12059 | case 6: | |
12060 | /* SETEND and CPS */ | |
12061 | break; | |
12062 | case 0: | |
12063 | /* ADD/SUB (SP plus immediate) */ | |
12064 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12065 | record_buf[0] = ARM_SP_REGNUM; | |
12066 | thumb_insn_r->reg_rec_count = 1; | |
12067 | break; | |
12068 | case 1: /* fall through */ | |
12069 | case 3: /* fall through */ | |
12070 | case 9: /* fall through */ | |
12071 | case 11: | |
12072 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
12073 | break; |
12074 | case 2: | |
12075 | /* SXTH, SXTB, UXTH, UXTB */ | |
12076 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
12077 | thumb_insn_r->reg_rec_count = 1; | |
12078 | break; | |
12079 | case 4: /* fall through */ | |
12080 | case 5: | |
12081 | /* PUSH. */ | |
12082 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12083 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12084 | while (register_bits) | |
12085 | { | |
12086 | if (register_bits & 0x00000001) | |
12087 | register_count++; | |
12088 | register_bits = register_bits >> 1; | |
12089 | } | |
12090 | start_address = u_regval - \ | |
12091 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
12092 | thumb_insn_r->mem_rec_count = register_count; | |
12093 | while (register_count) | |
12094 | { | |
12095 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12096 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12097 | start_address = start_address + 4; | |
12098 | register_count--; | |
12099 | } | |
12100 | record_buf[0] = ARM_SP_REGNUM; | |
12101 | thumb_insn_r->reg_rec_count = 1; | |
12102 | break; | |
12103 | case 10: | |
12104 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
12105 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
12106 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
12107 | break; |
12108 | case 12: /* fall through */ | |
12109 | case 13: | |
12110 | /* POP. */ | |
12111 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12112 | while (register_bits) | |
12113 | { | |
12114 | if (register_bits & 0x00000001) | |
12115 | record_buf[index++] = register_count; | |
12116 | register_bits = register_bits >> 1; | |
12117 | register_count++; | |
12118 | } | |
12119 | record_buf[index++] = ARM_PS_REGNUM; | |
12120 | record_buf[index++] = ARM_SP_REGNUM; | |
12121 | thumb_insn_r->reg_rec_count = index; | |
12122 | break; | |
12123 | case 0xe: | |
12124 | /* BKPT insn. */ | |
12125 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
12126 | /* CPSR is changed to be executed in ARM state, disabling normal | |
12127 | interrupts, entering abort mode. */ | |
12128 | /* According to high vector configuration PC is set. */ | |
12129 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
12130 | previous CPSR and Program Counter. */ | |
12131 | record_buf[0] = ARM_PS_REGNUM; | |
12132 | record_buf[1] = ARM_LR_REGNUM; | |
12133 | thumb_insn_r->reg_rec_count = 2; | |
12134 | /* We need to save SPSR value, which is not yet done. */ | |
12135 | printf_unfiltered (_("Process record does not support instruction " | |
12136 | "0x%0x at address %s.\n"), | |
12137 | thumb_insn_r->arm_insn, | |
12138 | paddress (thumb_insn_r->gdbarch, | |
12139 | thumb_insn_r->this_addr)); | |
12140 | return -1; | |
12141 | ||
12142 | case 0xf: | |
12143 | /* If-Then, and hints */ | |
12144 | break; | |
12145 | default: | |
12146 | return -1; | |
12147 | }; | |
72508ac0 PO |
12148 | } |
12149 | ||
12150 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12151 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12152 | record_buf_mem); |
72508ac0 PO |
12153 | |
12154 | return 0; | |
12155 | } | |
12156 | ||
12157 | /* Handling opcode 110 insns. */ | |
12158 | ||
12159 | static int | |
12160 | thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) | |
12161 | { | |
12162 | struct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch); | |
12163 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12164 | ||
12165 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
12166 | uint32_t reg_src1 = 0; | |
12167 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 12168 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12169 | uint32_t record_buf[24], record_buf_mem[48]; |
12170 | ||
12171 | ULONGEST u_regval = 0; | |
12172 | ||
12173 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
12174 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
12175 | ||
12176 | if (1 == opcode2) | |
12177 | { | |
12178 | ||
12179 | /* LDMIA. */ | |
12180 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12181 | /* Get Rn. */ | |
12182 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12183 | while (register_bits) | |
dda83cd7 SM |
12184 | { |
12185 | if (register_bits & 0x00000001) | |
12186 | record_buf[index++] = register_count; | |
12187 | register_bits = register_bits >> 1; | |
12188 | register_count++; | |
12189 | } | |
f969241e OJ |
12190 | record_buf[index++] = reg_src1; |
12191 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
12192 | } |
12193 | else if (0 == opcode2) | |
12194 | { | |
12195 | /* It handles both STMIA. */ | |
12196 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12197 | /* Get Rn. */ | |
12198 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12199 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12200 | while (register_bits) | |
dda83cd7 SM |
12201 | { |
12202 | if (register_bits & 0x00000001) | |
12203 | register_count++; | |
12204 | register_bits = register_bits >> 1; | |
12205 | } | |
72508ac0 PO |
12206 | start_address = u_regval; |
12207 | thumb_insn_r->mem_rec_count = register_count; | |
12208 | while (register_count) | |
dda83cd7 SM |
12209 | { |
12210 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12211 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12212 | start_address = start_address + 4; | |
12213 | register_count--; | |
12214 | } | |
72508ac0 PO |
12215 | } |
12216 | else if (0x1F == opcode1) | |
12217 | { | |
dda83cd7 SM |
12218 | /* Handle arm syscall insn. */ |
12219 | if (tdep->arm_syscall_record != NULL) | |
12220 | { | |
12221 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
12222 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
12223 | } | |
12224 | else | |
12225 | { | |
12226 | printf_unfiltered (_("no syscall record support\n")); | |
12227 | return -1; | |
12228 | } | |
72508ac0 PO |
12229 | } |
12230 | ||
12231 | /* B (1), conditional branch is automatically taken care in process_record, | |
12232 | as PC is saved there. */ | |
12233 | ||
12234 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12235 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12236 | record_buf_mem); |
72508ac0 PO |
12237 | |
12238 | return ret; | |
12239 | } | |
12240 | ||
12241 | /* Handling opcode 111 insns. */ | |
12242 | ||
12243 | static int | |
12244 | thumb_record_branch (insn_decode_record *thumb_insn_r) | |
12245 | { | |
12246 | uint32_t record_buf[8]; | |
12247 | uint32_t bits_h = 0; | |
12248 | ||
12249 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
12250 | ||
12251 | if (2 == bits_h || 3 == bits_h) | |
12252 | { | |
12253 | /* BL */ | |
12254 | record_buf[0] = ARM_LR_REGNUM; | |
12255 | thumb_insn_r->reg_rec_count = 1; | |
12256 | } | |
12257 | else if (1 == bits_h) | |
12258 | { | |
12259 | /* BLX(1). */ | |
12260 | record_buf[0] = ARM_PS_REGNUM; | |
12261 | record_buf[1] = ARM_LR_REGNUM; | |
12262 | thumb_insn_r->reg_rec_count = 2; | |
12263 | } | |
12264 | ||
12265 | /* B(2) is automatically taken care in process_record, as PC is | |
12266 | saved there. */ | |
12267 | ||
12268 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12269 | ||
12270 | return 0; | |
12271 | } | |
12272 | ||
c6ec2b30 OJ |
12273 | /* Handler for thumb2 load/store multiple instructions. */ |
12274 | ||
12275 | static int | |
12276 | thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) | |
12277 | { | |
12278 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12279 | ||
12280 | uint32_t reg_rn, op; | |
12281 | uint32_t register_bits = 0, register_count = 0; | |
12282 | uint32_t index = 0, start_address = 0; | |
12283 | uint32_t record_buf[24], record_buf_mem[48]; | |
12284 | ||
12285 | ULONGEST u_regval = 0; | |
12286 | ||
12287 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12288 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12289 | ||
12290 | if (0 == op || 3 == op) | |
12291 | { | |
12292 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12293 | { |
12294 | /* Handle RFE instruction. */ | |
12295 | record_buf[0] = ARM_PS_REGNUM; | |
12296 | thumb2_insn_r->reg_rec_count = 1; | |
12297 | } | |
c6ec2b30 | 12298 | else |
dda83cd7 SM |
12299 | { |
12300 | /* Handle SRS instruction after reading banked SP. */ | |
12301 | return arm_record_unsupported_insn (thumb2_insn_r); | |
12302 | } | |
c6ec2b30 OJ |
12303 | } |
12304 | else if (1 == op || 2 == op) | |
12305 | { | |
12306 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12307 | { |
12308 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
12309 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12310 | while (register_bits) | |
12311 | { | |
12312 | if (register_bits & 0x00000001) | |
12313 | record_buf[index++] = register_count; | |
12314 | ||
12315 | register_count++; | |
12316 | register_bits = register_bits >> 1; | |
12317 | } | |
12318 | record_buf[index++] = reg_rn; | |
12319 | record_buf[index++] = ARM_PS_REGNUM; | |
12320 | thumb2_insn_r->reg_rec_count = index; | |
12321 | } | |
c6ec2b30 | 12322 | else |
dda83cd7 SM |
12323 | { |
12324 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
12325 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12326 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12327 | while (register_bits) | |
12328 | { | |
12329 | if (register_bits & 0x00000001) | |
12330 | register_count++; | |
12331 | ||
12332 | register_bits = register_bits >> 1; | |
12333 | } | |
12334 | ||
12335 | if (1 == op) | |
12336 | { | |
12337 | /* Start address calculation for LDMDB/LDMEA. */ | |
12338 | start_address = u_regval; | |
12339 | } | |
12340 | else if (2 == op) | |
12341 | { | |
12342 | /* Start address calculation for LDMDB/LDMEA. */ | |
12343 | start_address = u_regval - register_count * 4; | |
12344 | } | |
12345 | ||
12346 | thumb2_insn_r->mem_rec_count = register_count; | |
12347 | while (register_count) | |
12348 | { | |
12349 | record_buf_mem[register_count * 2 - 1] = start_address; | |
12350 | record_buf_mem[register_count * 2 - 2] = 4; | |
12351 | start_address = start_address + 4; | |
12352 | register_count--; | |
12353 | } | |
12354 | record_buf[0] = reg_rn; | |
12355 | record_buf[1] = ARM_PS_REGNUM; | |
12356 | thumb2_insn_r->reg_rec_count = 2; | |
12357 | } | |
c6ec2b30 OJ |
12358 | } |
12359 | ||
12360 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 12361 | record_buf_mem); |
c6ec2b30 | 12362 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 12363 | record_buf); |
c6ec2b30 OJ |
12364 | return ARM_RECORD_SUCCESS; |
12365 | } | |
12366 | ||
12367 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
12368 | instructions. */ | |
12369 | ||
12370 | static int | |
12371 | thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) | |
12372 | { | |
12373 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12374 | ||
12375 | uint32_t reg_rd, reg_rn, offset_imm; | |
12376 | uint32_t reg_dest1, reg_dest2; | |
12377 | uint32_t address, offset_addr; | |
12378 | uint32_t record_buf[8], record_buf_mem[8]; | |
12379 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
12380 | |
12381 | ULONGEST u_regval[2]; | |
12382 | ||
12383 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12384 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
12385 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12386 | ||
12387 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12388 | { | |
12389 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
12390 | { |
12391 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12392 | record_buf[0] = reg_dest1; | |
12393 | record_buf[1] = ARM_PS_REGNUM; | |
12394 | thumb2_insn_r->reg_rec_count = 2; | |
12395 | } | |
c6ec2b30 OJ |
12396 | |
12397 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
12398 | { |
12399 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12400 | record_buf[2] = reg_dest2; | |
12401 | thumb2_insn_r->reg_rec_count = 3; | |
12402 | } | |
c6ec2b30 OJ |
12403 | } |
12404 | else | |
12405 | { | |
12406 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12407 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12408 | ||
12409 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
12410 | { |
12411 | /* Handle STREX. */ | |
12412 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12413 | address = u_regval[0] + (offset_imm * 4); | |
12414 | record_buf_mem[0] = 4; | |
12415 | record_buf_mem[1] = address; | |
12416 | thumb2_insn_r->mem_rec_count = 1; | |
12417 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12418 | record_buf[0] = reg_rd; | |
12419 | thumb2_insn_r->reg_rec_count = 1; | |
12420 | } | |
c6ec2b30 | 12421 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
12422 | { |
12423 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12424 | record_buf[0] = reg_rd; | |
12425 | thumb2_insn_r->reg_rec_count = 1; | |
12426 | address = u_regval[0]; | |
12427 | record_buf_mem[1] = address; | |
12428 | ||
12429 | if (4 == op3) | |
12430 | { | |
12431 | /* Handle STREXB. */ | |
12432 | record_buf_mem[0] = 1; | |
12433 | thumb2_insn_r->mem_rec_count = 1; | |
12434 | } | |
12435 | else if (5 == op3) | |
12436 | { | |
12437 | /* Handle STREXH. */ | |
12438 | record_buf_mem[0] = 2 ; | |
12439 | thumb2_insn_r->mem_rec_count = 1; | |
12440 | } | |
12441 | else if (7 == op3) | |
12442 | { | |
12443 | /* Handle STREXD. */ | |
12444 | address = u_regval[0]; | |
12445 | record_buf_mem[0] = 4; | |
12446 | record_buf_mem[2] = 4; | |
12447 | record_buf_mem[3] = address + 4; | |
12448 | thumb2_insn_r->mem_rec_count = 2; | |
12449 | } | |
12450 | } | |
c6ec2b30 | 12451 | else |
dda83cd7 SM |
12452 | { |
12453 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12454 | ||
12455 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
12456 | { | |
12457 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12458 | offset_addr = u_regval[0] + (offset_imm * 4); | |
12459 | else | |
12460 | offset_addr = u_regval[0] - (offset_imm * 4); | |
12461 | ||
12462 | address = offset_addr; | |
12463 | } | |
12464 | else | |
12465 | address = u_regval[0]; | |
12466 | ||
12467 | record_buf_mem[0] = 4; | |
12468 | record_buf_mem[1] = address; | |
12469 | record_buf_mem[2] = 4; | |
12470 | record_buf_mem[3] = address + 4; | |
12471 | thumb2_insn_r->mem_rec_count = 2; | |
12472 | record_buf[0] = reg_rn; | |
12473 | thumb2_insn_r->reg_rec_count = 1; | |
12474 | } | |
c6ec2b30 OJ |
12475 | } |
12476 | ||
12477 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12478 | record_buf); |
c6ec2b30 | 12479 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12480 | record_buf_mem); |
c6ec2b30 OJ |
12481 | return ARM_RECORD_SUCCESS; |
12482 | } | |
12483 | ||
12484 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
12485 | instructions. */ | |
12486 | ||
12487 | static int | |
12488 | thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) | |
12489 | { | |
12490 | uint32_t reg_rd, op; | |
12491 | uint32_t record_buf[8]; | |
12492 | ||
12493 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
12494 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12495 | ||
12496 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
12497 | { | |
12498 | record_buf[0] = ARM_PS_REGNUM; | |
12499 | thumb2_insn_r->reg_rec_count = 1; | |
12500 | } | |
12501 | else | |
12502 | { | |
12503 | record_buf[0] = reg_rd; | |
12504 | record_buf[1] = ARM_PS_REGNUM; | |
12505 | thumb2_insn_r->reg_rec_count = 2; | |
12506 | } | |
12507 | ||
12508 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12509 | record_buf); |
c6ec2b30 OJ |
12510 | return ARM_RECORD_SUCCESS; |
12511 | } | |
12512 | ||
12513 | /* Generic handler for thumb2 instructions which effect destination and PS | |
12514 | registers. */ | |
12515 | ||
12516 | static int | |
12517 | thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) | |
12518 | { | |
12519 | uint32_t reg_rd; | |
12520 | uint32_t record_buf[8]; | |
12521 | ||
12522 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12523 | ||
12524 | record_buf[0] = reg_rd; | |
12525 | record_buf[1] = ARM_PS_REGNUM; | |
12526 | thumb2_insn_r->reg_rec_count = 2; | |
12527 | ||
12528 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12529 | record_buf); |
c6ec2b30 OJ |
12530 | return ARM_RECORD_SUCCESS; |
12531 | } | |
12532 | ||
12533 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
12534 | ||
12535 | static int | |
12536 | thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) | |
12537 | { | |
12538 | uint32_t op, op1, op2; | |
12539 | uint32_t record_buf[8]; | |
12540 | ||
12541 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12542 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
12543 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12544 | ||
12545 | /* Handle MSR insn. */ | |
12546 | if (!(op1 & 0x2) && 0x38 == op) | |
12547 | { | |
12548 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
12549 | { |
12550 | /* CPSR is going to be changed. */ | |
12551 | record_buf[0] = ARM_PS_REGNUM; | |
12552 | thumb2_insn_r->reg_rec_count = 1; | |
12553 | } | |
c6ec2b30 | 12554 | else |
dda83cd7 SM |
12555 | { |
12556 | arm_record_unsupported_insn(thumb2_insn_r); | |
12557 | return -1; | |
12558 | } | |
c6ec2b30 OJ |
12559 | } |
12560 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
12561 | { | |
12562 | /* BLX. */ | |
12563 | record_buf[0] = ARM_PS_REGNUM; | |
12564 | record_buf[1] = ARM_LR_REGNUM; | |
12565 | thumb2_insn_r->reg_rec_count = 2; | |
12566 | } | |
12567 | ||
12568 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12569 | record_buf); |
c6ec2b30 OJ |
12570 | return ARM_RECORD_SUCCESS; |
12571 | } | |
12572 | ||
12573 | /* Handler for thumb2 store single data item instructions. */ | |
12574 | ||
12575 | static int | |
12576 | thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) | |
12577 | { | |
12578 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12579 | ||
12580 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
12581 | uint32_t address, offset_addr; | |
12582 | uint32_t record_buf[8], record_buf_mem[8]; | |
12583 | uint32_t op1, op2; | |
12584 | ||
12585 | ULONGEST u_regval[2]; | |
12586 | ||
12587 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
12588 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
12589 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12590 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12591 | ||
12592 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12593 | { | |
12594 | /* T2 encoding. */ | |
12595 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
12596 | offset_addr = u_regval[0] + offset_imm; | |
12597 | address = offset_addr; | |
12598 | } | |
12599 | else | |
12600 | { | |
12601 | /* T3 encoding. */ | |
12602 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
12603 | { |
12604 | /* Handle STRB (register). */ | |
12605 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12606 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
12607 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
12608 | offset_addr = u_regval[1] << shift_imm; | |
12609 | address = u_regval[0] + offset_addr; | |
12610 | } | |
c6ec2b30 | 12611 | else |
dda83cd7 SM |
12612 | { |
12613 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12614 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
12615 | { | |
12616 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
12617 | offset_addr = u_regval[0] + offset_imm; | |
12618 | else | |
12619 | offset_addr = u_regval[0] - offset_imm; | |
12620 | ||
12621 | address = offset_addr; | |
12622 | } | |
12623 | else | |
12624 | address = u_regval[0]; | |
12625 | } | |
c6ec2b30 OJ |
12626 | } |
12627 | ||
12628 | switch (op1) | |
12629 | { | |
12630 | /* Store byte instructions. */ | |
12631 | case 4: | |
12632 | case 0: | |
dda83cd7 SM |
12633 | record_buf_mem[0] = 1; |
12634 | break; | |
c6ec2b30 OJ |
12635 | /* Store half word instructions. */ |
12636 | case 1: | |
12637 | case 5: | |
dda83cd7 SM |
12638 | record_buf_mem[0] = 2; |
12639 | break; | |
c6ec2b30 OJ |
12640 | /* Store word instructions. */ |
12641 | case 2: | |
12642 | case 6: | |
dda83cd7 SM |
12643 | record_buf_mem[0] = 4; |
12644 | break; | |
c6ec2b30 OJ |
12645 | |
12646 | default: | |
dda83cd7 SM |
12647 | gdb_assert_not_reached ("no decoding pattern found"); |
12648 | break; | |
c6ec2b30 OJ |
12649 | } |
12650 | ||
12651 | record_buf_mem[1] = address; | |
12652 | thumb2_insn_r->mem_rec_count = 1; | |
12653 | record_buf[0] = reg_rn; | |
12654 | thumb2_insn_r->reg_rec_count = 1; | |
12655 | ||
12656 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12657 | record_buf); |
c6ec2b30 | 12658 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12659 | record_buf_mem); |
c6ec2b30 OJ |
12660 | return ARM_RECORD_SUCCESS; |
12661 | } | |
12662 | ||
12663 | /* Handler for thumb2 load memory hints instructions. */ | |
12664 | ||
12665 | static int | |
12666 | thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) | |
12667 | { | |
12668 | uint32_t record_buf[8]; | |
12669 | uint32_t reg_rt, reg_rn; | |
12670 | ||
12671 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12672 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12673 | ||
12674 | if (ARM_PC_REGNUM != reg_rt) | |
12675 | { | |
12676 | record_buf[0] = reg_rt; | |
12677 | record_buf[1] = reg_rn; | |
12678 | record_buf[2] = ARM_PS_REGNUM; | |
12679 | thumb2_insn_r->reg_rec_count = 3; | |
12680 | ||
12681 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12682 | record_buf); |
c6ec2b30 OJ |
12683 | return ARM_RECORD_SUCCESS; |
12684 | } | |
12685 | ||
12686 | return ARM_RECORD_FAILURE; | |
12687 | } | |
12688 | ||
12689 | /* Handler for thumb2 load word instructions. */ | |
12690 | ||
12691 | static int | |
12692 | thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) | |
12693 | { | |
c6ec2b30 OJ |
12694 | uint32_t record_buf[8]; |
12695 | ||
12696 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12697 | record_buf[1] = ARM_PS_REGNUM; | |
12698 | thumb2_insn_r->reg_rec_count = 2; | |
12699 | ||
12700 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12701 | record_buf); |
c6ec2b30 OJ |
12702 | return ARM_RECORD_SUCCESS; |
12703 | } | |
12704 | ||
12705 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
12706 | divide instructions. */ | |
12707 | ||
12708 | static int | |
12709 | thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) | |
12710 | { | |
12711 | uint32_t opcode1 = 0, opcode2 = 0; | |
12712 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
12713 | |
12714 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
12715 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12716 | ||
12717 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
12718 | { | |
12719 | /* Handle SMULL, UMULL, SMULAL. */ | |
12720 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
12721 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12722 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12723 | record_buf[2] = ARM_PS_REGNUM; | |
12724 | thumb2_insn_r->reg_rec_count = 3; | |
12725 | } | |
12726 | else if (1 == opcode1 || 3 == opcode2) | |
12727 | { | |
12728 | /* Handle SDIV and UDIV. */ | |
12729 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12730 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12731 | record_buf[2] = ARM_PS_REGNUM; | |
12732 | thumb2_insn_r->reg_rec_count = 3; | |
12733 | } | |
12734 | else | |
12735 | return ARM_RECORD_FAILURE; | |
12736 | ||
12737 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12738 | record_buf); |
c6ec2b30 OJ |
12739 | return ARM_RECORD_SUCCESS; |
12740 | } | |
12741 | ||
60cc5e93 OJ |
12742 | /* Record handler for thumb32 coprocessor instructions. */ |
12743 | ||
12744 | static int | |
12745 | thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) | |
12746 | { | |
12747 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
12748 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
12749 | else | |
12750 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
12751 | } | |
12752 | ||
1e1b6563 OJ |
12753 | /* Record handler for advance SIMD structure load/store instructions. */ |
12754 | ||
12755 | static int | |
12756 | thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) | |
12757 | { | |
12758 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12759 | uint32_t l_bit, a_bit, b_bits; | |
12760 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 12761 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
12762 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
12763 | uint8_t f_ebytes; | |
12764 | ||
12765 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
12766 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
12767 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12768 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12769 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12770 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
12771 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
12772 | f_elem = 8 / f_ebytes; |
12773 | ||
12774 | if (!l_bit) | |
12775 | { | |
12776 | ULONGEST u_regval = 0; | |
12777 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12778 | address = u_regval; | |
12779 | ||
12780 | if (!a_bit) | |
dda83cd7 SM |
12781 | { |
12782 | /* Handle VST1. */ | |
12783 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12784 | { | |
12785 | if (b_bits == 0x07) | |
12786 | bf_regs = 1; | |
12787 | else if (b_bits == 0x0a) | |
12788 | bf_regs = 2; | |
12789 | else if (b_bits == 0x06) | |
12790 | bf_regs = 3; | |
12791 | else if (b_bits == 0x02) | |
12792 | bf_regs = 4; | |
12793 | else | |
12794 | bf_regs = 0; | |
12795 | ||
12796 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12797 | { | |
12798 | for (index_e = 0; index_e < f_elem; index_e++) | |
12799 | { | |
12800 | record_buf_mem[index_m++] = f_ebytes; | |
12801 | record_buf_mem[index_m++] = address; | |
12802 | address = address + f_ebytes; | |
12803 | thumb2_insn_r->mem_rec_count += 1; | |
12804 | } | |
12805 | } | |
12806 | } | |
12807 | /* Handle VST2. */ | |
12808 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12809 | { | |
12810 | if (b_bits == 0x09 || b_bits == 0x08) | |
12811 | bf_regs = 1; | |
12812 | else if (b_bits == 0x03) | |
12813 | bf_regs = 2; | |
12814 | else | |
12815 | bf_regs = 0; | |
12816 | ||
12817 | for (index_r = 0; index_r < bf_regs; index_r++) | |
12818 | for (index_e = 0; index_e < f_elem; index_e++) | |
12819 | { | |
12820 | for (loop_t = 0; loop_t < 2; loop_t++) | |
12821 | { | |
12822 | record_buf_mem[index_m++] = f_ebytes; | |
12823 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12824 | thumb2_insn_r->mem_rec_count += 1; | |
12825 | } | |
12826 | address = address + (2 * f_ebytes); | |
12827 | } | |
12828 | } | |
12829 | /* Handle VST3. */ | |
12830 | else if ((b_bits & 0x0e) == 0x04) | |
12831 | { | |
12832 | for (index_e = 0; index_e < f_elem; index_e++) | |
12833 | { | |
12834 | for (loop_t = 0; loop_t < 3; loop_t++) | |
12835 | { | |
12836 | record_buf_mem[index_m++] = f_ebytes; | |
12837 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12838 | thumb2_insn_r->mem_rec_count += 1; | |
12839 | } | |
12840 | address = address + (3 * f_ebytes); | |
12841 | } | |
12842 | } | |
12843 | /* Handle VST4. */ | |
12844 | else if (!(b_bits & 0x0e)) | |
12845 | { | |
12846 | for (index_e = 0; index_e < f_elem; index_e++) | |
12847 | { | |
12848 | for (loop_t = 0; loop_t < 4; loop_t++) | |
12849 | { | |
12850 | record_buf_mem[index_m++] = f_ebytes; | |
12851 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
12852 | thumb2_insn_r->mem_rec_count += 1; | |
12853 | } | |
12854 | address = address + (4 * f_ebytes); | |
12855 | } | |
12856 | } | |
12857 | } | |
1e1b6563 | 12858 | else |
dda83cd7 SM |
12859 | { |
12860 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
12861 | ||
12862 | if (bft_size == 0x00) | |
12863 | f_ebytes = 1; | |
12864 | else if (bft_size == 0x01) | |
12865 | f_ebytes = 2; | |
12866 | else if (bft_size == 0x02) | |
12867 | f_ebytes = 4; | |
12868 | else | |
12869 | f_ebytes = 0; | |
12870 | ||
12871 | /* Handle VST1. */ | |
12872 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
12873 | thumb2_insn_r->mem_rec_count = 1; | |
12874 | /* Handle VST2. */ | |
12875 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
12876 | thumb2_insn_r->mem_rec_count = 2; | |
12877 | /* Handle VST3. */ | |
12878 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
12879 | thumb2_insn_r->mem_rec_count = 3; | |
12880 | /* Handle VST4. */ | |
12881 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
12882 | thumb2_insn_r->mem_rec_count = 4; | |
12883 | ||
12884 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
12885 | { | |
12886 | record_buf_mem[index_m] = f_ebytes; | |
12887 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
12888 | } | |
12889 | } | |
1e1b6563 OJ |
12890 | } |
12891 | else | |
12892 | { | |
12893 | if (!a_bit) | |
dda83cd7 SM |
12894 | { |
12895 | /* Handle VLD1. */ | |
12896 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
12897 | thumb2_insn_r->reg_rec_count = 1; | |
12898 | /* Handle VLD2. */ | |
12899 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
12900 | thumb2_insn_r->reg_rec_count = 2; | |
12901 | /* Handle VLD3. */ | |
12902 | else if ((b_bits & 0x0e) == 0x04) | |
12903 | thumb2_insn_r->reg_rec_count = 3; | |
12904 | /* Handle VLD4. */ | |
12905 | else if (!(b_bits & 0x0e)) | |
12906 | thumb2_insn_r->reg_rec_count = 4; | |
12907 | } | |
1e1b6563 | 12908 | else |
dda83cd7 SM |
12909 | { |
12910 | /* Handle VLD1. */ | |
12911 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
12912 | thumb2_insn_r->reg_rec_count = 1; | |
12913 | /* Handle VLD2. */ | |
12914 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
12915 | thumb2_insn_r->reg_rec_count = 2; | |
12916 | /* Handle VLD3. */ | |
12917 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
12918 | thumb2_insn_r->reg_rec_count = 3; | |
12919 | /* Handle VLD4. */ | |
12920 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
12921 | thumb2_insn_r->reg_rec_count = 4; | |
12922 | ||
12923 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
12924 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
12925 | } | |
1e1b6563 OJ |
12926 | } |
12927 | ||
12928 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
12929 | { | |
12930 | record_buf[index_r] = reg_rn; | |
12931 | thumb2_insn_r->reg_rec_count += 1; | |
12932 | } | |
12933 | ||
12934 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12935 | record_buf); |
1e1b6563 | 12936 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12937 | record_buf_mem); |
1e1b6563 OJ |
12938 | return 0; |
12939 | } | |
12940 | ||
c6ec2b30 OJ |
12941 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
12942 | ||
12943 | static unsigned int | |
12944 | thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) | |
12945 | { | |
12946 | uint32_t op, op1, op2; | |
12947 | ||
12948 | op = bit (thumb2_insn_r->arm_insn, 15); | |
12949 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
12950 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
12951 | ||
12952 | if (op1 == 0x01) | |
12953 | { | |
12954 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
12955 | { |
12956 | /* Load/store multiple instruction. */ | |
12957 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
12958 | } | |
b121eeb9 | 12959 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
12960 | { |
12961 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
12962 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
12963 | } | |
b121eeb9 | 12964 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
12965 | { |
12966 | /* Data-processing (shifted register). */ | |
12967 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12968 | } | |
c6ec2b30 | 12969 | else if (op2 & 0x40) |
dda83cd7 SM |
12970 | { |
12971 | /* Co-processor instructions. */ | |
12972 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
12973 | } | |
c6ec2b30 OJ |
12974 | } |
12975 | else if (op1 == 0x02) | |
12976 | { | |
12977 | if (op) | |
dda83cd7 SM |
12978 | { |
12979 | /* Branches and miscellaneous control instructions. */ | |
12980 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
12981 | } | |
c6ec2b30 | 12982 | else if (op2 & 0x20) |
dda83cd7 SM |
12983 | { |
12984 | /* Data-processing (plain binary immediate) instruction. */ | |
12985 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
12986 | } | |
c6ec2b30 | 12987 | else |
dda83cd7 SM |
12988 | { |
12989 | /* Data-processing (modified immediate). */ | |
12990 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
12991 | } | |
c6ec2b30 OJ |
12992 | } |
12993 | else if (op1 == 0x03) | |
12994 | { | |
12995 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
12996 | { |
12997 | /* Store single data item. */ | |
12998 | return thumb2_record_str_single_data (thumb2_insn_r); | |
12999 | } | |
c6ec2b30 | 13000 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
13001 | { |
13002 | /* Advanced SIMD or structure load/store instructions. */ | |
13003 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
13004 | } | |
c6ec2b30 | 13005 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
13006 | { |
13007 | /* Load byte, memory hints instruction. */ | |
13008 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13009 | } | |
c6ec2b30 | 13010 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
13011 | { |
13012 | /* Load halfword, memory hints instruction. */ | |
13013 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13014 | } | |
c6ec2b30 | 13015 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
13016 | { |
13017 | /* Load word instruction. */ | |
13018 | return thumb2_record_ld_word (thumb2_insn_r); | |
13019 | } | |
c6ec2b30 | 13020 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
13021 | { |
13022 | /* Data-processing (register) instruction. */ | |
13023 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13024 | } | |
c6ec2b30 | 13025 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
13026 | { |
13027 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
13028 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13029 | } | |
c6ec2b30 | 13030 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
13031 | { |
13032 | /* Long multiply, long multiply accumulate, and divide. */ | |
13033 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
13034 | } | |
c6ec2b30 | 13035 | else if (op2 & 0x40) |
dda83cd7 SM |
13036 | { |
13037 | /* Co-processor instructions. */ | |
13038 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
13039 | } | |
c6ec2b30 OJ |
13040 | } |
13041 | ||
13042 | return -1; | |
13043 | } | |
72508ac0 | 13044 | |
ffdbe864 | 13045 | namespace { |
728a7913 YQ |
13046 | /* Abstract memory reader. */ |
13047 | ||
13048 | class abstract_memory_reader | |
13049 | { | |
13050 | public: | |
13051 | /* Read LEN bytes of target memory at address MEMADDR, placing the | |
13052 | results in GDB's memory at BUF. Return true on success. */ | |
13053 | ||
13054 | virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0; | |
13055 | }; | |
13056 | ||
13057 | /* Instruction reader from real target. */ | |
13058 | ||
13059 | class instruction_reader : public abstract_memory_reader | |
13060 | { | |
13061 | public: | |
632e107b | 13062 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
728a7913 YQ |
13063 | { |
13064 | if (target_read_memory (memaddr, buf, len)) | |
13065 | return false; | |
13066 | else | |
13067 | return true; | |
13068 | } | |
13069 | }; | |
13070 | ||
ffdbe864 YQ |
13071 | } // namespace |
13072 | ||
72508ac0 | 13073 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success |
85102364 | 13074 | and positive val on failure. */ |
72508ac0 PO |
13075 | |
13076 | static int | |
728a7913 YQ |
13077 | extract_arm_insn (abstract_memory_reader& reader, |
13078 | insn_decode_record *insn_record, uint32_t insn_size) | |
72508ac0 PO |
13079 | { |
13080 | gdb_byte buf[insn_size]; | |
13081 | ||
13082 | memset (&buf[0], 0, insn_size); | |
13083 | ||
728a7913 | 13084 | if (!reader.read (insn_record->this_addr, buf, insn_size)) |
72508ac0 PO |
13085 | return 1; |
13086 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
dda83cd7 | 13087 | insn_size, |
2959fed9 | 13088 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
13089 | return 0; |
13090 | } | |
13091 | ||
13092 | typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); | |
13093 | ||
13094 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
13095 | dispatch it. */ | |
13096 | ||
13097 | static int | |
728a7913 YQ |
13098 | decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record, |
13099 | record_type_t record_type, uint32_t insn_size) | |
72508ac0 PO |
13100 | { |
13101 | ||
01e57735 YQ |
13102 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
13103 | instruction. */ | |
0fa9c223 | 13104 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
13105 | { |
13106 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
13107 | arm_record_data_proc_imm, /* 001. */ | |
13108 | arm_record_ld_st_imm_offset, /* 010. */ | |
13109 | arm_record_ld_st_reg_offset, /* 011. */ | |
13110 | arm_record_ld_st_multiple, /* 100. */ | |
13111 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 13112 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
13113 | arm_record_coproc_data_proc /* 111. */ |
13114 | }; | |
13115 | ||
01e57735 YQ |
13116 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
13117 | instruction. */ | |
0fa9c223 | 13118 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
13119 | { \ |
13120 | thumb_record_shift_add_sub, /* 000. */ | |
13121 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
13122 | thumb_record_ld_st_reg_offset, /* 010. */ | |
13123 | thumb_record_ld_st_imm_offset, /* 011. */ | |
13124 | thumb_record_ld_st_stack, /* 100. */ | |
13125 | thumb_record_misc, /* 101. */ | |
13126 | thumb_record_ldm_stm_swi, /* 110. */ | |
13127 | thumb_record_branch /* 111. */ | |
13128 | }; | |
13129 | ||
13130 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
13131 | uint32_t insn_id = 0; | |
13132 | ||
728a7913 | 13133 | if (extract_arm_insn (reader, arm_record, insn_size)) |
72508ac0 PO |
13134 | { |
13135 | if (record_debug) | |
01e57735 YQ |
13136 | { |
13137 | printf_unfiltered (_("Process record: error reading memory at " | |
13138 | "addr %s len = %d.\n"), | |
13139 | paddress (arm_record->gdbarch, | |
13140 | arm_record->this_addr), insn_size); | |
13141 | } | |
72508ac0 PO |
13142 | return -1; |
13143 | } | |
13144 | else if (ARM_RECORD == record_type) | |
13145 | { | |
13146 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
13147 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
13148 | |
13149 | if (arm_record->cond == 0xf) | |
13150 | ret = arm_record_extension_space (arm_record); | |
13151 | else | |
01e57735 | 13152 | { |
ca92db2d YQ |
13153 | /* If this insn has fallen into extension space |
13154 | then we need not decode it anymore. */ | |
01e57735 YQ |
13155 | ret = arm_handle_insn[insn_id] (arm_record); |
13156 | } | |
ca92db2d YQ |
13157 | if (ret != ARM_RECORD_SUCCESS) |
13158 | { | |
13159 | arm_record_unsupported_insn (arm_record); | |
13160 | ret = -1; | |
13161 | } | |
72508ac0 PO |
13162 | } |
13163 | else if (THUMB_RECORD == record_type) | |
13164 | { | |
13165 | /* As thumb does not have condition codes, we set negative. */ | |
13166 | arm_record->cond = -1; | |
13167 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
13168 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
13169 | if (ret != ARM_RECORD_SUCCESS) |
13170 | { | |
13171 | arm_record_unsupported_insn (arm_record); | |
13172 | ret = -1; | |
13173 | } | |
72508ac0 PO |
13174 | } |
13175 | else if (THUMB2_RECORD == record_type) | |
13176 | { | |
c6ec2b30 OJ |
13177 | /* As thumb does not have condition codes, we set negative. */ |
13178 | arm_record->cond = -1; | |
13179 | ||
13180 | /* Swap first half of 32bit thumb instruction with second half. */ | |
13181 | arm_record->arm_insn | |
01e57735 | 13182 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 13183 | |
ca92db2d | 13184 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 13185 | |
ca92db2d | 13186 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
13187 | { |
13188 | arm_record_unsupported_insn (arm_record); | |
13189 | ret = -1; | |
13190 | } | |
72508ac0 PO |
13191 | } |
13192 | else | |
13193 | { | |
13194 | /* Throw assertion. */ | |
13195 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
13196 | } | |
13197 | ||
13198 | return ret; | |
13199 | } | |
13200 | ||
b121eeb9 YQ |
13201 | #if GDB_SELF_TEST |
13202 | namespace selftests { | |
13203 | ||
13204 | /* Provide both 16-bit and 32-bit thumb instructions. */ | |
13205 | ||
13206 | class instruction_reader_thumb : public abstract_memory_reader | |
13207 | { | |
13208 | public: | |
13209 | template<size_t SIZE> | |
13210 | instruction_reader_thumb (enum bfd_endian endian, | |
13211 | const uint16_t (&insns)[SIZE]) | |
13212 | : m_endian (endian), m_insns (insns), m_insns_size (SIZE) | |
13213 | {} | |
13214 | ||
632e107b | 13215 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
b121eeb9 YQ |
13216 | { |
13217 | SELF_CHECK (len == 4 || len == 2); | |
13218 | SELF_CHECK (memaddr % 2 == 0); | |
13219 | SELF_CHECK ((memaddr / 2) < m_insns_size); | |
13220 | ||
13221 | store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]); | |
13222 | if (len == 4) | |
13223 | { | |
13224 | store_unsigned_integer (&buf[2], 2, m_endian, | |
13225 | m_insns[memaddr / 2 + 1]); | |
13226 | } | |
13227 | return true; | |
13228 | } | |
13229 | ||
13230 | private: | |
13231 | enum bfd_endian m_endian; | |
13232 | const uint16_t *m_insns; | |
13233 | size_t m_insns_size; | |
13234 | }; | |
13235 | ||
13236 | static void | |
13237 | arm_record_test (void) | |
13238 | { | |
13239 | struct gdbarch_info info; | |
13240 | gdbarch_info_init (&info); | |
13241 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
13242 | ||
13243 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13244 | ||
13245 | SELF_CHECK (gdbarch != NULL); | |
13246 | ||
13247 | /* 16-bit Thumb instructions. */ | |
13248 | { | |
13249 | insn_decode_record arm_record; | |
13250 | ||
13251 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13252 | arm_record.gdbarch = gdbarch; | |
13253 | ||
13254 | static const uint16_t insns[] = { | |
13255 | /* db b2 uxtb r3, r3 */ | |
13256 | 0xb2db, | |
13257 | /* cd 58 ldr r5, [r1, r3] */ | |
13258 | 0x58cd, | |
13259 | }; | |
13260 | ||
13261 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13262 | instruction_reader_thumb reader (endian, insns); | |
13263 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13264 | THUMB_INSN_SIZE_BYTES); | |
13265 | ||
13266 | SELF_CHECK (ret == 0); | |
13267 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13268 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13269 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
13270 | ||
13271 | arm_record.this_addr += 2; | |
13272 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13273 | THUMB_INSN_SIZE_BYTES); | |
13274 | ||
13275 | SELF_CHECK (ret == 0); | |
13276 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13277 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13278 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
13279 | } | |
13280 | ||
13281 | /* 32-bit Thumb-2 instructions. */ | |
13282 | { | |
13283 | insn_decode_record arm_record; | |
13284 | ||
13285 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13286 | arm_record.gdbarch = gdbarch; | |
13287 | ||
13288 | static const uint16_t insns[] = { | |
13289 | /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ | |
13290 | 0xee1d, 0x7f70, | |
13291 | }; | |
13292 | ||
13293 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13294 | instruction_reader_thumb reader (endian, insns); | |
13295 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, | |
13296 | THUMB2_INSN_SIZE_BYTES); | |
13297 | ||
13298 | SELF_CHECK (ret == 0); | |
13299 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13300 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13301 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
13302 | } | |
13303 | } | |
9ecab40c SM |
13304 | |
13305 | /* Instruction reader from manually cooked instruction sequences. */ | |
13306 | ||
13307 | class test_arm_instruction_reader : public arm_instruction_reader | |
13308 | { | |
13309 | public: | |
13310 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
13311 | : m_insns (insns) | |
13312 | {} | |
13313 | ||
13314 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
13315 | { | |
13316 | SELF_CHECK (memaddr % 4 == 0); | |
13317 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
13318 | ||
13319 | return m_insns[memaddr / 4]; | |
13320 | } | |
13321 | ||
13322 | private: | |
13323 | const gdb::array_view<const uint32_t> m_insns; | |
13324 | }; | |
13325 | ||
13326 | static void | |
13327 | arm_analyze_prologue_test () | |
13328 | { | |
13329 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
13330 | { | |
13331 | struct gdbarch_info info; | |
13332 | gdbarch_info_init (&info); | |
13333 | info.byte_order = endianness; | |
13334 | info.byte_order_for_code = endianness; | |
13335 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
13336 | ||
13337 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13338 | ||
13339 | SELF_CHECK (gdbarch != NULL); | |
13340 | ||
13341 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
13342 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
13343 | UBSan. */ | |
13344 | const uint32_t insns[] = { | |
13345 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
13346 | 0xe1a05000, /* mov r5, r0 */ | |
13347 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
13348 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
13349 | }; | |
13350 | ||
13351 | test_arm_instruction_reader mem_reader (insns); | |
13352 | arm_prologue_cache cache; | |
13353 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
13354 | ||
13355 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
13356 | } | |
13357 | } | |
13358 | ||
b121eeb9 YQ |
13359 | } // namespace selftests |
13360 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
13361 | |
13362 | /* Cleans up local record registers and memory allocations. */ | |
13363 | ||
13364 | static void | |
13365 | deallocate_reg_mem (insn_decode_record *record) | |
13366 | { | |
13367 | xfree (record->arm_regs); | |
13368 | xfree (record->arm_mems); | |
13369 | } | |
13370 | ||
13371 | ||
01e57735 | 13372 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
13373 | memory that will be changed in current instruction to record_arch_list". |
13374 | Return -1 if something is wrong. */ | |
13375 | ||
13376 | int | |
01e57735 YQ |
13377 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
13378 | CORE_ADDR insn_addr) | |
72508ac0 PO |
13379 | { |
13380 | ||
72508ac0 PO |
13381 | uint32_t no_of_rec = 0; |
13382 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
13383 | ULONGEST t_bit = 0, insn_id = 0; | |
13384 | ||
13385 | ULONGEST u_regval = 0; | |
13386 | ||
13387 | insn_decode_record arm_record; | |
13388 | ||
13389 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13390 | arm_record.regcache = regcache; | |
13391 | arm_record.this_addr = insn_addr; | |
13392 | arm_record.gdbarch = gdbarch; | |
13393 | ||
13394 | ||
13395 | if (record_debug > 1) | |
13396 | { | |
13397 | fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " | |
01e57735 | 13398 | "addr = %s\n", |
72508ac0 PO |
13399 | paddress (gdbarch, arm_record.this_addr)); |
13400 | } | |
13401 | ||
728a7913 YQ |
13402 | instruction_reader reader; |
13403 | if (extract_arm_insn (reader, &arm_record, 2)) | |
72508ac0 PO |
13404 | { |
13405 | if (record_debug) | |
01e57735 YQ |
13406 | { |
13407 | printf_unfiltered (_("Process record: error reading memory at " | |
13408 | "addr %s len = %d.\n"), | |
13409 | paddress (arm_record.gdbarch, | |
13410 | arm_record.this_addr), 2); | |
13411 | } | |
72508ac0 PO |
13412 | return -1; |
13413 | } | |
13414 | ||
13415 | /* Check the insn, whether it is thumb or arm one. */ | |
13416 | ||
13417 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
13418 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
13419 | ||
13420 | ||
13421 | if (!(u_regval & t_bit)) | |
13422 | { | |
13423 | /* We are decoding arm insn. */ | |
728a7913 | 13424 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
13425 | } |
13426 | else | |
13427 | { | |
13428 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
13429 | /* is it thumb2 insn? */ | |
13430 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 13431 | { |
728a7913 | 13432 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
13433 | THUMB2_INSN_SIZE_BYTES); |
13434 | } | |
72508ac0 | 13435 | else |
01e57735 YQ |
13436 | { |
13437 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
13438 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
13439 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 13440 | } |
72508ac0 PO |
13441 | } |
13442 | ||
13443 | if (0 == ret) | |
13444 | { | |
13445 | /* Record registers. */ | |
25ea693b | 13446 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 13447 | if (arm_record.arm_regs) |
01e57735 YQ |
13448 | { |
13449 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
13450 | { | |
13451 | if (record_full_arch_list_add_reg | |
25ea693b | 13452 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
13453 | ret = -1; |
13454 | } | |
13455 | } | |
72508ac0 PO |
13456 | /* Record memories. */ |
13457 | if (arm_record.arm_mems) | |
01e57735 YQ |
13458 | { |
13459 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
13460 | { | |
13461 | if (record_full_arch_list_add_mem | |
13462 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 13463 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
13464 | ret = -1; |
13465 | } | |
13466 | } | |
72508ac0 | 13467 | |
25ea693b | 13468 | if (record_full_arch_list_add_end ()) |
01e57735 | 13469 | ret = -1; |
72508ac0 PO |
13470 | } |
13471 | ||
13472 | ||
13473 | deallocate_reg_mem (&arm_record); | |
13474 | ||
13475 | return ret; | |
13476 | } | |
d105cce5 AH |
13477 | |
13478 | /* See arm-tdep.h. */ | |
13479 | ||
13480 | const target_desc * | |
13481 | arm_read_description (arm_fp_type fp_type) | |
13482 | { | |
13483 | struct target_desc *tdesc = tdesc_arm_list[fp_type]; | |
13484 | ||
13485 | if (tdesc == nullptr) | |
13486 | { | |
13487 | tdesc = arm_create_target_description (fp_type); | |
13488 | tdesc_arm_list[fp_type] = tdesc; | |
13489 | } | |
13490 | ||
13491 | return tdesc; | |
13492 | } | |
13493 | ||
13494 | /* See arm-tdep.h. */ | |
13495 | ||
13496 | const target_desc * | |
13497 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
13498 | { | |
13499 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
13500 | ||
13501 | if (tdesc == nullptr) | |
13502 | { | |
13503 | tdesc = arm_create_mprofile_target_description (m_type); | |
13504 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
13505 | } | |
13506 | ||
13507 | return tdesc; | |
13508 | } |