Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
0fb0cc75 | 4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
9b254dd1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
123dc839 DJ |
43 | #include "target-descriptions.h" |
44 | #include "user-regs.h" | |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 | 53 | #include "gdb_assert.h" |
60c5725c | 54 | #include "vec.h" |
26216b98 | 55 | |
6529d2dd AC |
56 | static int arm_debug; |
57 | ||
082fc60d RE |
58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
59 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 60 | is used for this purpose. |
082fc60d RE |
61 | |
62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
64 | |
65 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
b887350f | 66 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
67 | |
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 69 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 70 | |
60c5725c DJ |
71 | /* Per-objfile data used for mapping symbols. */ |
72 | static const struct objfile_data *arm_objfile_data_key; | |
73 | ||
74 | struct arm_mapping_symbol | |
75 | { | |
76 | bfd_vma value; | |
77 | char type; | |
78 | }; | |
79 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; | |
80 | DEF_VEC_O(arm_mapping_symbol_s); | |
81 | ||
82 | struct arm_per_objfile | |
83 | { | |
84 | VEC(arm_mapping_symbol_s) **section_maps; | |
85 | }; | |
86 | ||
afd7eef0 RE |
87 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
88 | static struct cmd_list_element *setarmcmdlist = NULL; | |
89 | static struct cmd_list_element *showarmcmdlist = NULL; | |
90 | ||
fd50bc42 RE |
91 | /* The type of floating-point to use. Keep this in sync with enum |
92 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
93 | static const char *fp_model_strings[] = | |
94 | { | |
95 | "auto", | |
96 | "softfpa", | |
97 | "fpa", | |
98 | "softvfp", | |
28e97307 DJ |
99 | "vfp", |
100 | NULL | |
fd50bc42 RE |
101 | }; |
102 | ||
103 | /* A variable that can be configured by the user. */ | |
104 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
105 | static const char *current_fp_model = "auto"; | |
106 | ||
28e97307 DJ |
107 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
108 | static const char *arm_abi_strings[] = | |
109 | { | |
110 | "auto", | |
111 | "APCS", | |
112 | "AAPCS", | |
113 | NULL | |
114 | }; | |
115 | ||
116 | /* A variable that can be configured by the user. */ | |
117 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
118 | static const char *arm_abi_string = "auto"; | |
119 | ||
0428b8f5 DJ |
120 | /* The execution mode to assume. */ |
121 | static const char *arm_mode_strings[] = | |
122 | { | |
123 | "auto", | |
124 | "arm", | |
125 | "thumb" | |
126 | }; | |
127 | ||
128 | static const char *arm_fallback_mode_string = "auto"; | |
129 | static const char *arm_force_mode_string = "auto"; | |
130 | ||
94c30b78 | 131 | /* Number of different reg name sets (options). */ |
afd7eef0 | 132 | static int num_disassembly_options; |
bc90b915 | 133 | |
123dc839 DJ |
134 | /* The standard register names, and all the valid aliases for them. */ |
135 | static const struct | |
136 | { | |
137 | const char *name; | |
138 | int regnum; | |
139 | } arm_register_aliases[] = { | |
140 | /* Basic register numbers. */ | |
141 | { "r0", 0 }, | |
142 | { "r1", 1 }, | |
143 | { "r2", 2 }, | |
144 | { "r3", 3 }, | |
145 | { "r4", 4 }, | |
146 | { "r5", 5 }, | |
147 | { "r6", 6 }, | |
148 | { "r7", 7 }, | |
149 | { "r8", 8 }, | |
150 | { "r9", 9 }, | |
151 | { "r10", 10 }, | |
152 | { "r11", 11 }, | |
153 | { "r12", 12 }, | |
154 | { "r13", 13 }, | |
155 | { "r14", 14 }, | |
156 | { "r15", 15 }, | |
157 | /* Synonyms (argument and variable registers). */ | |
158 | { "a1", 0 }, | |
159 | { "a2", 1 }, | |
160 | { "a3", 2 }, | |
161 | { "a4", 3 }, | |
162 | { "v1", 4 }, | |
163 | { "v2", 5 }, | |
164 | { "v3", 6 }, | |
165 | { "v4", 7 }, | |
166 | { "v5", 8 }, | |
167 | { "v6", 9 }, | |
168 | { "v7", 10 }, | |
169 | { "v8", 11 }, | |
170 | /* Other platform-specific names for r9. */ | |
171 | { "sb", 9 }, | |
172 | { "tr", 9 }, | |
173 | /* Special names. */ | |
174 | { "ip", 12 }, | |
175 | { "sp", 13 }, | |
176 | { "lr", 14 }, | |
177 | { "pc", 15 }, | |
178 | /* Names used by GCC (not listed in the ARM EABI). */ | |
179 | { "sl", 10 }, | |
180 | { "fp", 11 }, | |
181 | /* A special name from the older ATPCS. */ | |
182 | { "wr", 7 }, | |
183 | }; | |
bc90b915 | 184 | |
123dc839 | 185 | static const char *const arm_register_names[] = |
da59e081 JM |
186 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
187 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
188 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
189 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
190 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
191 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 192 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 193 | |
afd7eef0 RE |
194 | /* Valid register name styles. */ |
195 | static const char **valid_disassembly_styles; | |
ed9a39eb | 196 | |
afd7eef0 RE |
197 | /* Disassembly style to use. Default to "std" register names. */ |
198 | static const char *disassembly_style; | |
96baa820 | 199 | |
ed9a39eb | 200 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
201 | style. */ |
202 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 203 | struct cmd_list_element *); |
afd7eef0 | 204 | static void set_disassembly_style (void); |
ed9a39eb | 205 | |
b508a996 | 206 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 207 | void *, int); |
b508a996 | 208 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 209 | const void *, int); |
ed9a39eb | 210 | |
58d6951d DJ |
211 | static void arm_neon_quad_read (struct gdbarch *gdbarch, |
212 | struct regcache *regcache, | |
213 | int regnum, gdb_byte *buf); | |
214 | static void arm_neon_quad_write (struct gdbarch *gdbarch, | |
215 | struct regcache *regcache, | |
216 | int regnum, const gdb_byte *buf); | |
217 | ||
9b8d791a | 218 | struct arm_prologue_cache |
c3b4394c | 219 | { |
eb5492fa DJ |
220 | /* The stack pointer at the time this frame was created; i.e. the |
221 | caller's stack pointer when this function was called. It is used | |
222 | to identify this frame. */ | |
223 | CORE_ADDR prev_sp; | |
224 | ||
4be43953 DJ |
225 | /* The frame base for this frame is just prev_sp - frame size. |
226 | FRAMESIZE is the distance from the frame pointer to the | |
227 | initial stack pointer. */ | |
eb5492fa | 228 | |
c3b4394c | 229 | int framesize; |
eb5492fa DJ |
230 | |
231 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 232 | int framereg; |
eb5492fa DJ |
233 | |
234 | /* Saved register offsets. */ | |
235 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 236 | }; |
ed9a39eb | 237 | |
bc90b915 FN |
238 | /* Addresses for calling Thumb functions have the bit 0 set. |
239 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
240 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
241 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
242 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
243 | ||
94c30b78 | 244 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
245 | |
246 | int arm_apcs_32 = 1; | |
247 | ||
b39cc962 DJ |
248 | /* Determine if FRAME is executing in Thumb mode. */ |
249 | ||
250 | static int | |
251 | arm_frame_is_thumb (struct frame_info *frame) | |
252 | { | |
253 | CORE_ADDR cpsr; | |
254 | ||
255 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
256 | directly (from a signal frame or dummy frame) or by interpreting | |
257 | the saved LR (from a prologue or DWARF frame). So consult it and | |
258 | trust the unwinders. */ | |
259 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
260 | ||
261 | return (cpsr & CPSR_T) != 0; | |
262 | } | |
263 | ||
60c5725c DJ |
264 | /* Callback for VEC_lower_bound. */ |
265 | ||
266 | static inline int | |
267 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, | |
268 | const struct arm_mapping_symbol *rhs) | |
269 | { | |
270 | return lhs->value < rhs->value; | |
271 | } | |
272 | ||
ed9a39eb | 273 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
b39cc962 DJ |
274 | function. This function should be called for addresses unrelated to |
275 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
c906108c | 276 | |
ad527d2e | 277 | static int |
2a451106 | 278 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 279 | { |
60c5725c | 280 | struct obj_section *sec; |
c5aa993b | 281 | struct minimal_symbol *sym; |
c906108c | 282 | |
ed9a39eb | 283 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
284 | if (IS_THUMB_ADDR (memaddr)) |
285 | return 1; | |
286 | ||
0428b8f5 DJ |
287 | /* If the user wants to override the symbol table, let him. */ |
288 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
289 | return 0; | |
290 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
291 | return 1; | |
292 | ||
60c5725c DJ |
293 | /* If there are mapping symbols, consult them. */ |
294 | sec = find_pc_section (memaddr); | |
295 | if (sec != NULL) | |
296 | { | |
297 | struct arm_per_objfile *data; | |
298 | VEC(arm_mapping_symbol_s) *map; | |
aded6f54 PA |
299 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
300 | 0 }; | |
60c5725c DJ |
301 | unsigned int idx; |
302 | ||
303 | data = objfile_data (sec->objfile, arm_objfile_data_key); | |
304 | if (data != NULL) | |
305 | { | |
306 | map = data->section_maps[sec->the_bfd_section->index]; | |
307 | if (!VEC_empty (arm_mapping_symbol_s, map)) | |
308 | { | |
309 | struct arm_mapping_symbol *map_sym; | |
310 | ||
311 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, | |
312 | arm_compare_mapping_symbols); | |
313 | ||
314 | /* VEC_lower_bound finds the earliest ordered insertion | |
315 | point. If the following symbol starts at this exact | |
316 | address, we use that; otherwise, the preceding | |
317 | mapping symbol covers this address. */ | |
318 | if (idx < VEC_length (arm_mapping_symbol_s, map)) | |
319 | { | |
320 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); | |
321 | if (map_sym->value == map_key.value) | |
322 | return map_sym->type == 't'; | |
323 | } | |
324 | ||
325 | if (idx > 0) | |
326 | { | |
327 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); | |
328 | return map_sym->type == 't'; | |
329 | } | |
330 | } | |
331 | } | |
332 | } | |
333 | ||
ed9a39eb | 334 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
335 | sym = lookup_minimal_symbol_by_pc (memaddr); |
336 | if (sym) | |
0428b8f5 DJ |
337 | return (MSYMBOL_IS_SPECIAL (sym)); |
338 | ||
339 | /* If the user wants to override the fallback mode, let them. */ | |
340 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
341 | return 0; | |
342 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
343 | return 1; | |
344 | ||
345 | /* If we couldn't find any symbol, but we're talking to a running | |
346 | target, then trust the current value of $cpsr. This lets | |
347 | "display/i $pc" always show the correct mode (though if there is | |
348 | a symbol table we will not reach here, so it still may not be | |
349 | displayed in the mode it will be executed). */ | |
350 | if (target_has_registers) | |
351 | return arm_frame_is_thumb (get_current_frame ()); | |
352 | ||
353 | /* Otherwise we're out of luck; we assume ARM. */ | |
354 | return 0; | |
c906108c SS |
355 | } |
356 | ||
181c1381 | 357 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 358 | static CORE_ADDR |
24568a2c | 359 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 360 | { |
a3a2ee65 | 361 | if (arm_apcs_32) |
dd6be234 | 362 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 363 | else |
a3a2ee65 | 364 | return (val & 0x03fffffc); |
c906108c SS |
365 | } |
366 | ||
181c1381 RE |
367 | /* When reading symbols, we need to zap the low bit of the address, |
368 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 369 | static CORE_ADDR |
24568a2c | 370 | arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) |
181c1381 RE |
371 | { |
372 | return val & ~1; | |
373 | } | |
374 | ||
29d73ae4 DJ |
375 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
376 | and frame pointer. Scan until we encounter a store that could | |
377 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
378 | |
379 | static CORE_ADDR | |
29d73ae4 DJ |
380 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
381 | CORE_ADDR start, CORE_ADDR limit, | |
382 | struct arm_prologue_cache *cache) | |
c906108c | 383 | { |
e17a4113 | 384 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
385 | int i; |
386 | pv_t regs[16]; | |
387 | struct pv_area *stack; | |
388 | struct cleanup *back_to; | |
389 | CORE_ADDR offset; | |
da3c6d4a | 390 | |
29d73ae4 DJ |
391 | for (i = 0; i < 16; i++) |
392 | regs[i] = pv_register (i, 0); | |
55f960e1 | 393 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 DJ |
394 | back_to = make_cleanup_free_pv_area (stack); |
395 | ||
29d73ae4 | 396 | while (start < limit) |
c906108c | 397 | { |
29d73ae4 DJ |
398 | unsigned short insn; |
399 | ||
e17a4113 | 400 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 401 | |
94c30b78 | 402 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 403 | { |
29d73ae4 DJ |
404 | int regno; |
405 | int mask; | |
4be43953 DJ |
406 | |
407 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
408 | break; | |
29d73ae4 DJ |
409 | |
410 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
411 | whether to save LR (R14). */ | |
412 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
413 | ||
414 | /* Calculate offsets of saved R0-R7 and LR. */ | |
415 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
416 | if (mask & (1 << regno)) | |
417 | { | |
29d73ae4 DJ |
418 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
419 | -4); | |
420 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
421 | } | |
da59e081 | 422 | } |
da3c6d4a MS |
423 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
424 | sub sp, #simm */ | |
da59e081 | 425 | { |
29d73ae4 DJ |
426 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
427 | if (insn & 0x80) /* Check for SUB. */ | |
428 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
429 | -offset); | |
da59e081 | 430 | else |
29d73ae4 DJ |
431 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
432 | offset); | |
da59e081 JM |
433 | } |
434 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
435 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
436 | (insn & 0xff) << 2); | |
437 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 438 | { |
29d73ae4 DJ |
439 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
440 | int src_reg = (insn & 0x78) >> 3; | |
441 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 442 | } |
29d73ae4 | 443 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 444 | { |
29d73ae4 DJ |
445 | /* Handle stores to the stack. Normally pushes are used, |
446 | but with GCC -mtpcs-frame, there may be other stores | |
447 | in the prologue to create the frame. */ | |
448 | int regno = (insn >> 8) & 0x7; | |
449 | pv_t addr; | |
450 | ||
451 | offset = (insn & 0xff) << 2; | |
452 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
453 | ||
454 | if (pv_area_store_would_trash (stack, addr)) | |
455 | break; | |
456 | ||
457 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 458 | } |
29d73ae4 | 459 | else |
3d74b771 | 460 | { |
29d73ae4 DJ |
461 | /* We don't know what this instruction is. We're finished |
462 | scanning. NOTE: Recognizing more safe-to-ignore | |
463 | instructions here will improve support for optimized | |
464 | code. */ | |
da3c6d4a | 465 | break; |
3d74b771 | 466 | } |
29d73ae4 DJ |
467 | |
468 | start += 2; | |
c906108c SS |
469 | } |
470 | ||
29d73ae4 DJ |
471 | if (cache == NULL) |
472 | { | |
473 | do_cleanups (back_to); | |
474 | return start; | |
475 | } | |
476 | ||
29d73ae4 DJ |
477 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
478 | { | |
479 | /* Frame pointer is fp. Frame size is constant. */ | |
480 | cache->framereg = ARM_FP_REGNUM; | |
481 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
482 | } | |
483 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
484 | { | |
485 | /* Frame pointer is r7. Frame size is constant. */ | |
486 | cache->framereg = THUMB_FP_REGNUM; | |
487 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
488 | } | |
489 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
490 | { | |
491 | /* Try the stack pointer... this is a bit desperate. */ | |
492 | cache->framereg = ARM_SP_REGNUM; | |
493 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
494 | } | |
495 | else | |
496 | { | |
497 | /* We're just out of luck. We don't know where the frame is. */ | |
498 | cache->framereg = -1; | |
499 | cache->framesize = 0; | |
500 | } | |
501 | ||
502 | for (i = 0; i < 16; i++) | |
503 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
504 | cache->saved_regs[i].addr = offset; | |
505 | ||
506 | do_cleanups (back_to); | |
507 | return start; | |
c906108c SS |
508 | } |
509 | ||
da3c6d4a MS |
510 | /* Advance the PC across any function entry prologue instructions to |
511 | reach some "real" code. | |
34e8f22d RE |
512 | |
513 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 514 | prologue: |
c906108c | 515 | |
c5aa993b JM |
516 | mov ip, sp |
517 | [stmfd sp!, {a1,a2,a3,a4}] | |
518 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
519 | [stfe f7, [sp, #-12]!] |
520 | [stfe f6, [sp, #-12]!] | |
521 | [stfe f5, [sp, #-12]!] | |
522 | [stfe f4, [sp, #-12]!] | |
523 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 524 | |
34e8f22d | 525 | static CORE_ADDR |
6093d2eb | 526 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 527 | { |
e17a4113 | 528 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
c906108c SS |
529 | unsigned long inst; |
530 | CORE_ADDR skip_pc; | |
a89fea3c | 531 | CORE_ADDR func_addr, limit_pc; |
c906108c SS |
532 | struct symtab_and_line sal; |
533 | ||
848cfffb | 534 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
d80b854b | 535 | if (deprecated_pc_in_call_dummy (gdbarch, pc)) |
848cfffb AC |
536 | return pc; |
537 | ||
a89fea3c JL |
538 | /* See if we can determine the end of the prologue via the symbol table. |
539 | If so, then return either PC, or the PC after the prologue, whichever | |
540 | is greater. */ | |
541 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 542 | { |
d80b854b UW |
543 | CORE_ADDR post_prologue_pc |
544 | = skip_prologue_using_sal (gdbarch, func_addr); | |
a89fea3c JL |
545 | if (post_prologue_pc != 0) |
546 | return max (pc, post_prologue_pc); | |
c906108c SS |
547 | } |
548 | ||
a89fea3c JL |
549 | /* Can't determine prologue from the symbol table, need to examine |
550 | instructions. */ | |
c906108c | 551 | |
a89fea3c JL |
552 | /* Find an upper limit on the function prologue using the debug |
553 | information. If the debug information could not be used to provide | |
554 | that bound, then use an arbitrary large number as the upper bound. */ | |
b8d5e71d | 555 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 556 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
557 | if (limit_pc == 0) |
558 | limit_pc = pc + 64; /* Magic. */ | |
559 | ||
c906108c | 560 | |
29d73ae4 DJ |
561 | /* Check if this is Thumb code. */ |
562 | if (arm_pc_is_thumb (pc)) | |
a89fea3c | 563 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
29d73ae4 | 564 | |
a89fea3c | 565 | for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) |
f43845b3 | 566 | { |
e17a4113 | 567 | inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); |
9d4fde75 | 568 | |
b8d5e71d MS |
569 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
570 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
571 | continue; | |
c906108c | 572 | |
28cd8767 JG |
573 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
574 | continue; | |
575 | ||
576 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
577 | continue; | |
578 | ||
b8d5e71d MS |
579 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
580 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
581 | continue; | |
c906108c | 582 | |
b8d5e71d MS |
583 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
584 | continue; | |
c906108c | 585 | |
b8d5e71d MS |
586 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
587 | continue; | |
11d3b27d | 588 | |
b8d5e71d MS |
589 | /* Any insns after this point may float into the code, if it makes |
590 | for better instruction scheduling, so we skip them only if we | |
591 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 592 | |
b8d5e71d MS |
593 | /* We may have either one sfmfd instruction here, or several stfe |
594 | insns, depending on the version of floating point code we | |
595 | support. */ | |
596 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
597 | continue; | |
598 | ||
599 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
600 | continue; | |
601 | ||
602 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
603 | continue; | |
604 | ||
605 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
606 | continue; | |
607 | ||
608 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
609 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
610 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
611 | continue; | |
612 | ||
613 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
614 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
615 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
616 | continue; | |
617 | ||
618 | /* Un-recognized instruction; stop scanning. */ | |
619 | break; | |
f43845b3 | 620 | } |
c906108c | 621 | |
b8d5e71d | 622 | return skip_pc; /* End of prologue */ |
c906108c | 623 | } |
94c30b78 | 624 | |
c5aa993b | 625 | /* *INDENT-OFF* */ |
c906108c SS |
626 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
627 | This function decodes a Thumb function prologue to determine: | |
628 | 1) the size of the stack frame | |
629 | 2) which registers are saved on it | |
630 | 3) the offsets of saved regs | |
631 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 632 | |
da59e081 JM |
633 | A typical Thumb function prologue would create this stack frame |
634 | (offsets relative to FP) | |
c906108c SS |
635 | old SP -> 24 stack parameters |
636 | 20 LR | |
637 | 16 R7 | |
638 | R7 -> 0 local variables (16 bytes) | |
639 | SP -> -12 additional stack space (12 bytes) | |
640 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
641 | 12 bytes. The frame register is R7. |
642 | ||
da3c6d4a MS |
643 | The comments for thumb_skip_prolog() describe the algorithm we use |
644 | to detect the end of the prolog. */ | |
c5aa993b JM |
645 | /* *INDENT-ON* */ |
646 | ||
c906108c | 647 | static void |
be8626e0 | 648 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 649 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
650 | { |
651 | CORE_ADDR prologue_start; | |
652 | CORE_ADDR prologue_end; | |
653 | CORE_ADDR current_pc; | |
c906108c | 654 | |
b39cc962 DJ |
655 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
656 | &prologue_end)) | |
c906108c SS |
657 | { |
658 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
659 | ||
94c30b78 | 660 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 661 | prologue_end = prev_pc; |
c906108c | 662 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 663 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
664 | } |
665 | else | |
f7060f85 DJ |
666 | /* We're in the boondocks: we have no idea where the start of the |
667 | function is. */ | |
668 | return; | |
c906108c | 669 | |
eb5492fa | 670 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 671 | |
be8626e0 | 672 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
673 | } |
674 | ||
ed9a39eb | 675 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
676 | 1) the size of the stack frame |
677 | 2) which registers are saved on it | |
678 | 3) the offsets of saved regs | |
679 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
680 | This information is stored in the "extra" fields of the frame_info. |
681 | ||
96baa820 JM |
682 | There are two basic forms for the ARM prologue. The fixed argument |
683 | function call will look like: | |
ed9a39eb JM |
684 | |
685 | mov ip, sp | |
686 | stmfd sp!, {fp, ip, lr, pc} | |
687 | sub fp, ip, #4 | |
688 | [sub sp, sp, #4] | |
96baa820 | 689 | |
c906108c | 690 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
691 | IP -> 4 (caller's stack) |
692 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
693 | -4 LR (return address in caller) | |
694 | -8 IP (copy of caller's SP) | |
695 | -12 FP (caller's FP) | |
696 | SP -> -28 Local variables | |
697 | ||
c906108c | 698 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
699 | 28 bytes. The stmfd call can also save any of the vN registers it |
700 | plans to use, which increases the frame size accordingly. | |
701 | ||
702 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
703 | because the ARM Store instructions always store PC + 8 when you read | |
704 | the PC register. | |
ed9a39eb | 705 | |
96baa820 JM |
706 | A variable argument function call will look like: |
707 | ||
ed9a39eb JM |
708 | mov ip, sp |
709 | stmfd sp!, {a1, a2, a3, a4} | |
710 | stmfd sp!, {fp, ip, lr, pc} | |
711 | sub fp, ip, #20 | |
712 | ||
96baa820 | 713 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
714 | IP -> 20 (caller's stack) |
715 | 16 A4 | |
716 | 12 A3 | |
717 | 8 A2 | |
718 | 4 A1 | |
719 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
720 | -4 LR (return address in caller) | |
721 | -8 IP (copy of caller's SP) | |
722 | -12 FP (caller's FP) | |
723 | SP -> -28 Local variables | |
96baa820 JM |
724 | |
725 | The frame size would thus be 48 bytes, and the frame offset would be | |
726 | 28 bytes. | |
727 | ||
728 | There is another potential complication, which is that the optimizer | |
729 | will try to separate the store of fp in the "stmfd" instruction from | |
730 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
731 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
732 | ||
733 | Also, note, the original version of the ARM toolchain claimed that there | |
734 | should be an | |
735 | ||
736 | instruction at the end of the prologue. I have never seen GCC produce | |
737 | this, and the ARM docs don't mention it. We still test for it below in | |
738 | case it happens... | |
ed9a39eb JM |
739 | |
740 | */ | |
c906108c SS |
741 | |
742 | static void | |
a262aec2 | 743 | arm_scan_prologue (struct frame_info *this_frame, |
2af46ca0 | 744 | struct arm_prologue_cache *cache) |
c906108c | 745 | { |
a262aec2 | 746 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
747 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
748 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4be43953 | 749 | int regno; |
c906108c | 750 | CORE_ADDR prologue_start, prologue_end, current_pc; |
a262aec2 | 751 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
b39cc962 | 752 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
4be43953 DJ |
753 | pv_t regs[ARM_FPS_REGNUM]; |
754 | struct pv_area *stack; | |
755 | struct cleanup *back_to; | |
756 | CORE_ADDR offset; | |
c906108c | 757 | |
c906108c | 758 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
759 | cache->framereg = ARM_SP_REGNUM; |
760 | cache->framesize = 0; | |
c906108c SS |
761 | |
762 | /* Check for Thumb prologue. */ | |
b39cc962 | 763 | if (arm_frame_is_thumb (this_frame)) |
c906108c | 764 | { |
b39cc962 | 765 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
c906108c SS |
766 | return; |
767 | } | |
768 | ||
769 | /* Find the function prologue. If we can't find the function in | |
770 | the symbol table, peek in the stack frame to find the PC. */ | |
b39cc962 DJ |
771 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
772 | &prologue_end)) | |
c906108c | 773 | { |
2a451106 KB |
774 | /* One way to find the end of the prologue (which works well |
775 | for unoptimized code) is to do the following: | |
776 | ||
777 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
778 | ||
779 | if (sal.line == 0) | |
eb5492fa | 780 | prologue_end = prev_pc; |
2a451106 KB |
781 | else if (sal.end < prologue_end) |
782 | prologue_end = sal.end; | |
783 | ||
784 | This mechanism is very accurate so long as the optimizer | |
785 | doesn't move any instructions from the function body into the | |
786 | prologue. If this happens, sal.end will be the last | |
787 | instruction in the first hunk of prologue code just before | |
788 | the first instruction that the scheduler has moved from | |
789 | the body to the prologue. | |
790 | ||
791 | In order to make sure that we scan all of the prologue | |
792 | instructions, we use a slightly less accurate mechanism which | |
793 | may scan more than necessary. To help compensate for this | |
794 | lack of accuracy, the prologue scanning loop below contains | |
795 | several clauses which'll cause the loop to terminate early if | |
796 | an implausible prologue instruction is encountered. | |
797 | ||
798 | The expression | |
799 | ||
800 | prologue_start + 64 | |
801 | ||
802 | is a suitable endpoint since it accounts for the largest | |
803 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 804 | the scheduler. */ |
2a451106 KB |
805 | |
806 | if (prologue_end > prologue_start + 64) | |
807 | { | |
94c30b78 | 808 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 809 | } |
c906108c SS |
810 | } |
811 | else | |
812 | { | |
eb5492fa DJ |
813 | /* We have no symbol information. Our only option is to assume this |
814 | function has a standard stack frame and the normal frame register. | |
815 | Then, we can find the value of our frame pointer on entrance to | |
816 | the callee (or at the present moment if this is the innermost frame). | |
817 | The value stored there should be the address of the stmfd + 8. */ | |
818 | CORE_ADDR frame_loc; | |
819 | LONGEST return_value; | |
820 | ||
a262aec2 | 821 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
e17a4113 | 822 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) |
16a0f3e7 EZ |
823 | return; |
824 | else | |
825 | { | |
bf6ae464 | 826 | prologue_start = gdbarch_addr_bits_remove |
2af46ca0 | 827 | (gdbarch, return_value) - 8; |
94c30b78 | 828 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 829 | } |
c906108c SS |
830 | } |
831 | ||
eb5492fa DJ |
832 | if (prev_pc < prologue_end) |
833 | prologue_end = prev_pc; | |
834 | ||
c906108c | 835 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 836 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 837 | |
96baa820 JM |
838 | Be careful, however, and if it doesn't look like a prologue, |
839 | don't try to scan it. If, for instance, a frameless function | |
840 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 841 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
842 | and other operations that rely on a knowledge of the stack |
843 | traceback. | |
844 | ||
845 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 846 | if we don't see this as the first insn, we will stop. |
c906108c | 847 | |
f43845b3 MS |
848 | [Note: This doesn't seem to be true any longer, so it's now an |
849 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 850 | |
f43845b3 MS |
851 | [Note further: The "mov ip,sp" only seems to be missing in |
852 | frameless functions at optimization level "-O2" or above, | |
853 | in which case it is often (but not always) replaced by | |
b8d5e71d | 854 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 855 | |
4be43953 DJ |
856 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
857 | regs[regno] = pv_register (regno, 0); | |
55f960e1 | 858 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 DJ |
859 | back_to = make_cleanup_free_pv_area (stack); |
860 | ||
94c30b78 MS |
861 | for (current_pc = prologue_start; |
862 | current_pc < prologue_end; | |
f43845b3 | 863 | current_pc += 4) |
96baa820 | 864 | { |
e17a4113 UW |
865 | unsigned int insn |
866 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); | |
9d4fde75 | 867 | |
94c30b78 | 868 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 869 | { |
4be43953 | 870 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
871 | continue; |
872 | } | |
873 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
874 | { | |
875 | unsigned imm = insn & 0xff; /* immediate value */ | |
876 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
877 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 878 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
28cd8767 JG |
879 | continue; |
880 | } | |
881 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
882 | { | |
883 | unsigned imm = insn & 0xff; /* immediate value */ | |
884 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
885 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 886 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
f43845b3 MS |
887 | continue; |
888 | } | |
94c30b78 | 889 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 890 | { |
4be43953 DJ |
891 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
892 | break; | |
893 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
894 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); | |
f43845b3 MS |
895 | continue; |
896 | } | |
897 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
898 | /* stmfd sp!, {..., fp, ip, lr, pc} |
899 | or | |
900 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 901 | { |
d4473757 | 902 | int mask = insn & 0xffff; |
ed9a39eb | 903 | |
4be43953 DJ |
904 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
905 | break; | |
906 | ||
94c30b78 | 907 | /* Calculate offsets of saved registers. */ |
34e8f22d | 908 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
909 | if (mask & (1 << regno)) |
910 | { | |
4be43953 DJ |
911 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
912 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
d4473757 KB |
913 | } |
914 | } | |
b8d5e71d MS |
915 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
916 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
917 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
918 | { | |
919 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
920 | continue; | |
921 | } | |
922 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
923 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
924 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
925 | { |
926 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
927 | continue; | |
928 | } | |
d4473757 KB |
929 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
930 | { | |
94c30b78 MS |
931 | unsigned imm = insn & 0xff; /* immediate value */ |
932 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 933 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 934 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
935 | } |
936 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
937 | { | |
94c30b78 MS |
938 | unsigned imm = insn & 0xff; /* immediate value */ |
939 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 940 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 941 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 942 | } |
ff6f572f | 943 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
2af46ca0 | 944 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 945 | { |
4be43953 DJ |
946 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
947 | break; | |
948 | ||
949 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 950 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 951 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 952 | } |
ff6f572f | 953 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
2af46ca0 | 954 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
955 | { |
956 | int n_saved_fp_regs; | |
957 | unsigned int fp_start_reg, fp_bound_reg; | |
958 | ||
4be43953 DJ |
959 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
960 | break; | |
961 | ||
94c30b78 | 962 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 963 | { |
d4473757 KB |
964 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
965 | n_saved_fp_regs = 3; | |
966 | else | |
967 | n_saved_fp_regs = 1; | |
96baa820 | 968 | } |
d4473757 | 969 | else |
96baa820 | 970 | { |
d4473757 KB |
971 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
972 | n_saved_fp_regs = 2; | |
973 | else | |
974 | n_saved_fp_regs = 4; | |
96baa820 | 975 | } |
d4473757 | 976 | |
34e8f22d | 977 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
978 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
979 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 980 | { |
4be43953 DJ |
981 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
982 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
983 | regs[fp_start_reg++]); | |
96baa820 | 984 | } |
c906108c | 985 | } |
d4473757 | 986 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 987 | break; /* Condition not true, exit early */ |
b8d5e71d | 988 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 989 | break; /* Don't scan past a block load */ |
d4473757 KB |
990 | else |
991 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 992 | so we just skip what we don't recognize. */ |
d4473757 | 993 | continue; |
c906108c SS |
994 | } |
995 | ||
4be43953 DJ |
996 | /* The frame size is just the distance from the frame register |
997 | to the original stack pointer. */ | |
998 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
999 | { | |
1000 | /* Frame pointer is fp. */ | |
1001 | cache->framereg = ARM_FP_REGNUM; | |
1002 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1003 | } | |
1004 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
1005 | { | |
1006 | /* Try the stack pointer... this is a bit desperate. */ | |
1007 | cache->framereg = ARM_SP_REGNUM; | |
1008 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1009 | } | |
d4473757 | 1010 | else |
4be43953 DJ |
1011 | { |
1012 | /* We're just out of luck. We don't know where the frame is. */ | |
1013 | cache->framereg = -1; | |
1014 | cache->framesize = 0; | |
1015 | } | |
1016 | ||
1017 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
1018 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
1019 | cache->saved_regs[regno].addr = offset; | |
1020 | ||
1021 | do_cleanups (back_to); | |
c906108c SS |
1022 | } |
1023 | ||
eb5492fa | 1024 | static struct arm_prologue_cache * |
a262aec2 | 1025 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1026 | { |
eb5492fa DJ |
1027 | int reg; |
1028 | struct arm_prologue_cache *cache; | |
1029 | CORE_ADDR unwound_fp; | |
c5aa993b | 1030 | |
35d5d4ee | 1031 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1032 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1033 | |
a262aec2 | 1034 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1035 | |
a262aec2 | 1036 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1037 | if (unwound_fp == 0) |
1038 | return cache; | |
c906108c | 1039 | |
4be43953 | 1040 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1041 | |
eb5492fa DJ |
1042 | /* Calculate actual addresses of saved registers using offsets |
1043 | determined by arm_scan_prologue. */ | |
a262aec2 | 1044 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 1045 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
1046 | cache->saved_regs[reg].addr += cache->prev_sp; |
1047 | ||
1048 | return cache; | |
c906108c SS |
1049 | } |
1050 | ||
eb5492fa DJ |
1051 | /* Our frame ID for a normal frame is the current function's starting PC |
1052 | and the caller's SP when we were called. */ | |
c906108c | 1053 | |
148754e5 | 1054 | static void |
a262aec2 | 1055 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1056 | void **this_cache, |
1057 | struct frame_id *this_id) | |
c906108c | 1058 | { |
eb5492fa DJ |
1059 | struct arm_prologue_cache *cache; |
1060 | struct frame_id id; | |
2c404490 | 1061 | CORE_ADDR pc, func; |
f079148d | 1062 | |
eb5492fa | 1063 | if (*this_cache == NULL) |
a262aec2 | 1064 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1065 | cache = *this_cache; |
2a451106 | 1066 | |
2c404490 DJ |
1067 | /* This is meant to halt the backtrace at "_start". */ |
1068 | pc = get_frame_pc (this_frame); | |
1069 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
eb5492fa | 1070 | return; |
5a203e44 | 1071 | |
eb5492fa DJ |
1072 | /* If we've hit a wall, stop. */ |
1073 | if (cache->prev_sp == 0) | |
1074 | return; | |
24de872b | 1075 | |
2c404490 | 1076 | func = get_frame_func (this_frame); |
eb5492fa | 1077 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1078 | *this_id = id; |
c906108c SS |
1079 | } |
1080 | ||
a262aec2 DJ |
1081 | static struct value * |
1082 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1083 | void **this_cache, |
a262aec2 | 1084 | int prev_regnum) |
24de872b | 1085 | { |
24568a2c | 1086 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1087 | struct arm_prologue_cache *cache; |
1088 | ||
eb5492fa | 1089 | if (*this_cache == NULL) |
a262aec2 | 1090 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1091 | cache = *this_cache; |
24de872b | 1092 | |
eb5492fa | 1093 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1094 | instead. The prologue may save PC, but it will point into this |
1095 | frame's prologue, not the next frame's resume location. Also | |
1096 | strip the saved T bit. A valid LR may have the low bit set, but | |
1097 | a valid PC never does. */ | |
eb5492fa | 1098 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1099 | { |
1100 | CORE_ADDR lr; | |
1101 | ||
1102 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1103 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1104 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1105 | } |
24de872b | 1106 | |
eb5492fa | 1107 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1108 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1109 | The value was already reconstructed into PREV_SP. */ |
1110 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1111 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1112 | |
b39cc962 DJ |
1113 | /* The CPSR may have been changed by the call instruction and by the |
1114 | called function. The only bit we can reconstruct is the T bit, | |
1115 | by checking the low bit of LR as of the call. This is a reliable | |
1116 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
1117 | Thumb code, which could get away with a clear low bit as long as | |
1118 | the called function did not use bx. Guess that all other | |
1119 | bits are unchanged; the condition flags are presumably lost, | |
1120 | but the processor status is likely valid. */ | |
1121 | if (prev_regnum == ARM_PS_REGNUM) | |
1122 | { | |
1123 | CORE_ADDR lr, cpsr; | |
1124 | ||
1125 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
1126 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1127 | if (IS_THUMB_ADDR (lr)) | |
1128 | cpsr |= CPSR_T; | |
1129 | else | |
1130 | cpsr &= ~CPSR_T; | |
1131 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); | |
1132 | } | |
1133 | ||
a262aec2 DJ |
1134 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
1135 | prev_regnum); | |
eb5492fa DJ |
1136 | } |
1137 | ||
1138 | struct frame_unwind arm_prologue_unwind = { | |
1139 | NORMAL_FRAME, | |
1140 | arm_prologue_this_id, | |
a262aec2 DJ |
1141 | arm_prologue_prev_register, |
1142 | NULL, | |
1143 | default_frame_sniffer | |
eb5492fa DJ |
1144 | }; |
1145 | ||
909cf6ea | 1146 | static struct arm_prologue_cache * |
a262aec2 | 1147 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea DJ |
1148 | { |
1149 | int reg; | |
1150 | struct arm_prologue_cache *cache; | |
1151 | CORE_ADDR unwound_fp; | |
1152 | ||
35d5d4ee | 1153 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1154 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 1155 | |
a262aec2 | 1156 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
1157 | |
1158 | return cache; | |
1159 | } | |
1160 | ||
1161 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1162 | ||
1163 | static void | |
a262aec2 | 1164 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
1165 | void **this_cache, |
1166 | struct frame_id *this_id) | |
1167 | { | |
1168 | struct arm_prologue_cache *cache; | |
1169 | ||
1170 | if (*this_cache == NULL) | |
a262aec2 | 1171 | *this_cache = arm_make_stub_cache (this_frame); |
909cf6ea DJ |
1172 | cache = *this_cache; |
1173 | ||
a262aec2 | 1174 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
1175 | } |
1176 | ||
a262aec2 DJ |
1177 | static int |
1178 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
1179 | struct frame_info *this_frame, | |
1180 | void **this_prologue_cache) | |
909cf6ea | 1181 | { |
93d42b30 | 1182 | CORE_ADDR addr_in_block; |
909cf6ea DJ |
1183 | char dummy[4]; |
1184 | ||
a262aec2 | 1185 | addr_in_block = get_frame_address_in_block (this_frame); |
93d42b30 | 1186 | if (in_plt_section (addr_in_block, NULL) |
a262aec2 DJ |
1187 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
1188 | return 1; | |
909cf6ea | 1189 | |
a262aec2 | 1190 | return 0; |
909cf6ea DJ |
1191 | } |
1192 | ||
a262aec2 DJ |
1193 | struct frame_unwind arm_stub_unwind = { |
1194 | NORMAL_FRAME, | |
1195 | arm_stub_this_id, | |
1196 | arm_prologue_prev_register, | |
1197 | NULL, | |
1198 | arm_stub_unwind_sniffer | |
1199 | }; | |
1200 | ||
24de872b | 1201 | static CORE_ADDR |
a262aec2 | 1202 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
1203 | { |
1204 | struct arm_prologue_cache *cache; | |
1205 | ||
eb5492fa | 1206 | if (*this_cache == NULL) |
a262aec2 | 1207 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa DJ |
1208 | cache = *this_cache; |
1209 | ||
4be43953 | 1210 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
1211 | } |
1212 | ||
eb5492fa DJ |
1213 | struct frame_base arm_normal_base = { |
1214 | &arm_prologue_unwind, | |
1215 | arm_normal_frame_base, | |
1216 | arm_normal_frame_base, | |
1217 | arm_normal_frame_base | |
1218 | }; | |
1219 | ||
a262aec2 | 1220 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
1221 | dummy frame. The frame ID's base needs to match the TOS value |
1222 | saved by save_dummy_frame_tos() and returned from | |
1223 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1224 | breakpoint. */ | |
c906108c | 1225 | |
eb5492fa | 1226 | static struct frame_id |
a262aec2 | 1227 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 1228 | { |
a262aec2 DJ |
1229 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
1230 | get_frame_pc (this_frame)); | |
eb5492fa | 1231 | } |
c3b4394c | 1232 | |
eb5492fa DJ |
1233 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1234 | be used to construct the previous frame's ID, after looking up the | |
1235 | containing function). */ | |
c3b4394c | 1236 | |
eb5492fa DJ |
1237 | static CORE_ADDR |
1238 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1239 | { | |
1240 | CORE_ADDR pc; | |
1241 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
24568a2c | 1242 | return arm_addr_bits_remove (gdbarch, pc); |
eb5492fa DJ |
1243 | } |
1244 | ||
1245 | static CORE_ADDR | |
1246 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1247 | { | |
1248 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1249 | } |
1250 | ||
b39cc962 DJ |
1251 | static struct value * |
1252 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
1253 | int regnum) | |
1254 | { | |
24568a2c | 1255 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 DJ |
1256 | CORE_ADDR lr, cpsr; |
1257 | ||
1258 | switch (regnum) | |
1259 | { | |
1260 | case ARM_PC_REGNUM: | |
1261 | /* The PC is normally copied from the return column, which | |
1262 | describes saves of LR. However, that version may have an | |
1263 | extra bit set to indicate Thumb state. The bit is not | |
1264 | part of the PC. */ | |
1265 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1266 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 1267 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
1268 | |
1269 | case ARM_PS_REGNUM: | |
1270 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 1271 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
1272 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
1273 | if (IS_THUMB_ADDR (lr)) | |
1274 | cpsr |= CPSR_T; | |
1275 | else | |
1276 | cpsr &= ~CPSR_T; | |
ca38c58e | 1277 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
1278 | |
1279 | default: | |
1280 | internal_error (__FILE__, __LINE__, | |
1281 | _("Unexpected register %d"), regnum); | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | static void | |
1286 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1287 | struct dwarf2_frame_state_reg *reg, | |
1288 | struct frame_info *this_frame) | |
1289 | { | |
1290 | switch (regnum) | |
1291 | { | |
1292 | case ARM_PC_REGNUM: | |
1293 | case ARM_PS_REGNUM: | |
1294 | reg->how = DWARF2_FRAME_REG_FN; | |
1295 | reg->loc.fn = arm_dwarf2_prev_register; | |
1296 | break; | |
1297 | case ARM_SP_REGNUM: | |
1298 | reg->how = DWARF2_FRAME_REG_CFA; | |
1299 | break; | |
1300 | } | |
1301 | } | |
1302 | ||
2dd604e7 RE |
1303 | /* When arguments must be pushed onto the stack, they go on in reverse |
1304 | order. The code below implements a FILO (stack) to do this. */ | |
1305 | ||
1306 | struct stack_item | |
1307 | { | |
1308 | int len; | |
1309 | struct stack_item *prev; | |
1310 | void *data; | |
1311 | }; | |
1312 | ||
1313 | static struct stack_item * | |
1314 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1315 | { | |
1316 | struct stack_item *si; | |
1317 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1318 | si->data = xmalloc (len); |
2dd604e7 RE |
1319 | si->len = len; |
1320 | si->prev = prev; | |
1321 | memcpy (si->data, contents, len); | |
1322 | return si; | |
1323 | } | |
1324 | ||
1325 | static struct stack_item * | |
1326 | pop_stack_item (struct stack_item *si) | |
1327 | { | |
1328 | struct stack_item *dead = si; | |
1329 | si = si->prev; | |
1330 | xfree (dead->data); | |
1331 | xfree (dead); | |
1332 | return si; | |
1333 | } | |
1334 | ||
2af48f68 PB |
1335 | |
1336 | /* Return the alignment (in bytes) of the given type. */ | |
1337 | ||
1338 | static int | |
1339 | arm_type_align (struct type *t) | |
1340 | { | |
1341 | int n; | |
1342 | int align; | |
1343 | int falign; | |
1344 | ||
1345 | t = check_typedef (t); | |
1346 | switch (TYPE_CODE (t)) | |
1347 | { | |
1348 | default: | |
1349 | /* Should never happen. */ | |
1350 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1351 | return 4; | |
1352 | ||
1353 | case TYPE_CODE_PTR: | |
1354 | case TYPE_CODE_ENUM: | |
1355 | case TYPE_CODE_INT: | |
1356 | case TYPE_CODE_FLT: | |
1357 | case TYPE_CODE_SET: | |
1358 | case TYPE_CODE_RANGE: | |
1359 | case TYPE_CODE_BITSTRING: | |
1360 | case TYPE_CODE_REF: | |
1361 | case TYPE_CODE_CHAR: | |
1362 | case TYPE_CODE_BOOL: | |
1363 | return TYPE_LENGTH (t); | |
1364 | ||
1365 | case TYPE_CODE_ARRAY: | |
1366 | case TYPE_CODE_COMPLEX: | |
1367 | /* TODO: What about vector types? */ | |
1368 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1369 | ||
1370 | case TYPE_CODE_STRUCT: | |
1371 | case TYPE_CODE_UNION: | |
1372 | align = 1; | |
1373 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1374 | { | |
1375 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1376 | if (falign > align) | |
1377 | align = falign; | |
1378 | } | |
1379 | return align; | |
1380 | } | |
1381 | } | |
1382 | ||
90445bd3 DJ |
1383 | /* Possible base types for a candidate for passing and returning in |
1384 | VFP registers. */ | |
1385 | ||
1386 | enum arm_vfp_cprc_base_type | |
1387 | { | |
1388 | VFP_CPRC_UNKNOWN, | |
1389 | VFP_CPRC_SINGLE, | |
1390 | VFP_CPRC_DOUBLE, | |
1391 | VFP_CPRC_VEC64, | |
1392 | VFP_CPRC_VEC128 | |
1393 | }; | |
1394 | ||
1395 | /* The length of one element of base type B. */ | |
1396 | ||
1397 | static unsigned | |
1398 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
1399 | { | |
1400 | switch (b) | |
1401 | { | |
1402 | case VFP_CPRC_SINGLE: | |
1403 | return 4; | |
1404 | case VFP_CPRC_DOUBLE: | |
1405 | return 8; | |
1406 | case VFP_CPRC_VEC64: | |
1407 | return 8; | |
1408 | case VFP_CPRC_VEC128: | |
1409 | return 16; | |
1410 | default: | |
1411 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
1412 | (int) b); | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
1417 | for passing base type B. */ | |
1418 | ||
1419 | static int | |
1420 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
1421 | { | |
1422 | switch (b) | |
1423 | { | |
1424 | case VFP_CPRC_SINGLE: | |
1425 | return 's'; | |
1426 | case VFP_CPRC_DOUBLE: | |
1427 | return 'd'; | |
1428 | case VFP_CPRC_VEC64: | |
1429 | return 'd'; | |
1430 | case VFP_CPRC_VEC128: | |
1431 | return 'q'; | |
1432 | default: | |
1433 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
1434 | (int) b); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | /* Determine whether T may be part of a candidate for passing and | |
1439 | returning in VFP registers, ignoring the limit on the total number | |
1440 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
1441 | classification of the first valid component found; if it is not | |
1442 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
1443 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
1444 | for passing and returning in VFP registers, a type differently | |
1445 | classified from *BASE_TYPE, or two types differently classified | |
1446 | from each other, return -1, otherwise return the total number of | |
1447 | base-type elements found (possibly 0 in an empty structure or | |
1448 | array). Vectors and complex types are not currently supported, | |
1449 | matching the generic AAPCS support. */ | |
1450 | ||
1451 | static int | |
1452 | arm_vfp_cprc_sub_candidate (struct type *t, | |
1453 | enum arm_vfp_cprc_base_type *base_type) | |
1454 | { | |
1455 | t = check_typedef (t); | |
1456 | switch (TYPE_CODE (t)) | |
1457 | { | |
1458 | case TYPE_CODE_FLT: | |
1459 | switch (TYPE_LENGTH (t)) | |
1460 | { | |
1461 | case 4: | |
1462 | if (*base_type == VFP_CPRC_UNKNOWN) | |
1463 | *base_type = VFP_CPRC_SINGLE; | |
1464 | else if (*base_type != VFP_CPRC_SINGLE) | |
1465 | return -1; | |
1466 | return 1; | |
1467 | ||
1468 | case 8: | |
1469 | if (*base_type == VFP_CPRC_UNKNOWN) | |
1470 | *base_type = VFP_CPRC_DOUBLE; | |
1471 | else if (*base_type != VFP_CPRC_DOUBLE) | |
1472 | return -1; | |
1473 | return 1; | |
1474 | ||
1475 | default: | |
1476 | return -1; | |
1477 | } | |
1478 | break; | |
1479 | ||
1480 | case TYPE_CODE_ARRAY: | |
1481 | { | |
1482 | int count; | |
1483 | unsigned unitlen; | |
1484 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); | |
1485 | if (count == -1) | |
1486 | return -1; | |
1487 | if (TYPE_LENGTH (t) == 0) | |
1488 | { | |
1489 | gdb_assert (count == 0); | |
1490 | return 0; | |
1491 | } | |
1492 | else if (count == 0) | |
1493 | return -1; | |
1494 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1495 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
1496 | return TYPE_LENGTH (t) / unitlen; | |
1497 | } | |
1498 | break; | |
1499 | ||
1500 | case TYPE_CODE_STRUCT: | |
1501 | { | |
1502 | int count = 0; | |
1503 | unsigned unitlen; | |
1504 | int i; | |
1505 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
1506 | { | |
1507 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
1508 | base_type); | |
1509 | if (sub_count == -1) | |
1510 | return -1; | |
1511 | count += sub_count; | |
1512 | } | |
1513 | if (TYPE_LENGTH (t) == 0) | |
1514 | { | |
1515 | gdb_assert (count == 0); | |
1516 | return 0; | |
1517 | } | |
1518 | else if (count == 0) | |
1519 | return -1; | |
1520 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1521 | if (TYPE_LENGTH (t) != unitlen * count) | |
1522 | return -1; | |
1523 | return count; | |
1524 | } | |
1525 | ||
1526 | case TYPE_CODE_UNION: | |
1527 | { | |
1528 | int count = 0; | |
1529 | unsigned unitlen; | |
1530 | int i; | |
1531 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
1532 | { | |
1533 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
1534 | base_type); | |
1535 | if (sub_count == -1) | |
1536 | return -1; | |
1537 | count = (count > sub_count ? count : sub_count); | |
1538 | } | |
1539 | if (TYPE_LENGTH (t) == 0) | |
1540 | { | |
1541 | gdb_assert (count == 0); | |
1542 | return 0; | |
1543 | } | |
1544 | else if (count == 0) | |
1545 | return -1; | |
1546 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1547 | if (TYPE_LENGTH (t) != unitlen * count) | |
1548 | return -1; | |
1549 | return count; | |
1550 | } | |
1551 | ||
1552 | default: | |
1553 | break; | |
1554 | } | |
1555 | ||
1556 | return -1; | |
1557 | } | |
1558 | ||
1559 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
1560 | if passed to or returned from a non-variadic function with the VFP | |
1561 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
1562 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
1563 | elements of that base type before returning. */ | |
1564 | ||
1565 | static int | |
1566 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
1567 | int *count) | |
1568 | { | |
1569 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
1570 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
1571 | if (c <= 0 || c > 4) | |
1572 | return 0; | |
1573 | *base_type = b; | |
1574 | *count = c; | |
1575 | return 1; | |
1576 | } | |
1577 | ||
1578 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
1579 | returning values from a function of type FUNC_TYPE, 0 | |
1580 | otherwise. */ | |
1581 | ||
1582 | static int | |
1583 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
1584 | { | |
1585 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1586 | /* Variadic functions always use the base ABI. Assume that functions | |
1587 | without debug info are not variadic. */ | |
1588 | if (func_type && TYPE_VARARGS (check_typedef (func_type))) | |
1589 | return 0; | |
1590 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
1591 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
1592 | return 0; | |
1593 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
1594 | } | |
1595 | ||
1596 | /* We currently only support passing parameters in integer registers, which | |
1597 | conforms with GCC's default model, and VFP argument passing following | |
1598 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
1599 | we should probably support some of them based on the selected ABI. */ |
1600 | ||
1601 | static CORE_ADDR | |
7d9b040b | 1602 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1603 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1604 | struct value **args, CORE_ADDR sp, int struct_return, | |
1605 | CORE_ADDR struct_addr) | |
2dd604e7 | 1606 | { |
e17a4113 | 1607 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
1608 | int argnum; |
1609 | int argreg; | |
1610 | int nstack; | |
1611 | struct stack_item *si = NULL; | |
90445bd3 DJ |
1612 | int use_vfp_abi; |
1613 | struct type *ftype; | |
1614 | unsigned vfp_regs_free = (1 << 16) - 1; | |
1615 | ||
1616 | /* Determine the type of this function and whether the VFP ABI | |
1617 | applies. */ | |
1618 | ftype = check_typedef (value_type (function)); | |
1619 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) | |
1620 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); | |
1621 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 1622 | |
6a65450a AC |
1623 | /* Set the return address. For the ARM, the return breakpoint is |
1624 | always at BP_ADDR. */ | |
2dd604e7 | 1625 | /* XXX Fix for Thumb. */ |
6a65450a | 1626 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1627 | |
1628 | /* Walk through the list of args and determine how large a temporary | |
1629 | stack is required. Need to take care here as structs may be | |
1630 | passed on the stack, and we have to to push them. */ | |
1631 | nstack = 0; | |
1632 | ||
1633 | argreg = ARM_A1_REGNUM; | |
1634 | nstack = 0; | |
1635 | ||
2dd604e7 RE |
1636 | /* The struct_return pointer occupies the first parameter |
1637 | passing register. */ | |
1638 | if (struct_return) | |
1639 | { | |
1640 | if (arm_debug) | |
5af949e3 | 1641 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 1642 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 1643 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
1644 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
1645 | argreg++; | |
1646 | } | |
1647 | ||
1648 | for (argnum = 0; argnum < nargs; argnum++) | |
1649 | { | |
1650 | int len; | |
1651 | struct type *arg_type; | |
1652 | struct type *target_type; | |
1653 | enum type_code typecode; | |
0fd88904 | 1654 | bfd_byte *val; |
2af48f68 | 1655 | int align; |
90445bd3 DJ |
1656 | enum arm_vfp_cprc_base_type vfp_base_type; |
1657 | int vfp_base_count; | |
1658 | int may_use_core_reg = 1; | |
2dd604e7 | 1659 | |
df407dfe | 1660 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1661 | len = TYPE_LENGTH (arg_type); |
1662 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1663 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1664 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1665 | |
2af48f68 PB |
1666 | align = arm_type_align (arg_type); |
1667 | /* Round alignment up to a whole number of words. */ | |
1668 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1669 | /* Different ABIs have different maximum alignments. */ | |
1670 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1671 | { | |
1672 | /* The APCS ABI only requires word alignment. */ | |
1673 | align = INT_REGISTER_SIZE; | |
1674 | } | |
1675 | else | |
1676 | { | |
1677 | /* The AAPCS requires at most doubleword alignment. */ | |
1678 | if (align > INT_REGISTER_SIZE * 2) | |
1679 | align = INT_REGISTER_SIZE * 2; | |
1680 | } | |
1681 | ||
90445bd3 DJ |
1682 | if (use_vfp_abi |
1683 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
1684 | &vfp_base_count)) | |
1685 | { | |
1686 | int regno; | |
1687 | int unit_length; | |
1688 | int shift; | |
1689 | unsigned mask; | |
1690 | ||
1691 | /* Because this is a CPRC it cannot go in a core register or | |
1692 | cause a core register to be skipped for alignment. | |
1693 | Either it goes in VFP registers and the rest of this loop | |
1694 | iteration is skipped for this argument, or it goes on the | |
1695 | stack (and the stack alignment code is correct for this | |
1696 | case). */ | |
1697 | may_use_core_reg = 0; | |
1698 | ||
1699 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
1700 | shift = unit_length / 4; | |
1701 | mask = (1 << (shift * vfp_base_count)) - 1; | |
1702 | for (regno = 0; regno < 16; regno += shift) | |
1703 | if (((vfp_regs_free >> regno) & mask) == mask) | |
1704 | break; | |
1705 | ||
1706 | if (regno < 16) | |
1707 | { | |
1708 | int reg_char; | |
1709 | int reg_scaled; | |
1710 | int i; | |
1711 | ||
1712 | vfp_regs_free &= ~(mask << regno); | |
1713 | reg_scaled = regno / shift; | |
1714 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
1715 | for (i = 0; i < vfp_base_count; i++) | |
1716 | { | |
1717 | char name_buf[4]; | |
1718 | int regnum; | |
58d6951d DJ |
1719 | if (reg_char == 'q') |
1720 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 1721 | val + i * unit_length); |
58d6951d DJ |
1722 | else |
1723 | { | |
1724 | sprintf (name_buf, "%c%d", reg_char, reg_scaled + i); | |
1725 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
1726 | strlen (name_buf)); | |
1727 | regcache_cooked_write (regcache, regnum, | |
1728 | val + i * unit_length); | |
1729 | } | |
90445bd3 DJ |
1730 | } |
1731 | continue; | |
1732 | } | |
1733 | else | |
1734 | { | |
1735 | /* This CPRC could not go in VFP registers, so all VFP | |
1736 | registers are now marked as used. */ | |
1737 | vfp_regs_free = 0; | |
1738 | } | |
1739 | } | |
1740 | ||
2af48f68 PB |
1741 | /* Push stack padding for dowubleword alignment. */ |
1742 | if (nstack & (align - 1)) | |
1743 | { | |
1744 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1745 | nstack += INT_REGISTER_SIZE; | |
1746 | } | |
1747 | ||
1748 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
1749 | if (may_use_core_reg |
1750 | && argreg <= ARM_LAST_ARG_REGNUM | |
2af48f68 PB |
1751 | && align > INT_REGISTER_SIZE |
1752 | && argreg & 1) | |
1753 | argreg++; | |
1754 | ||
2dd604e7 RE |
1755 | /* If the argument is a pointer to a function, and it is a |
1756 | Thumb function, create a LOCAL copy of the value and set | |
1757 | the THUMB bit in it. */ | |
1758 | if (TYPE_CODE_PTR == typecode | |
1759 | && target_type != NULL | |
1760 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1761 | { | |
e17a4113 | 1762 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
2dd604e7 RE |
1763 | if (arm_pc_is_thumb (regval)) |
1764 | { | |
1765 | val = alloca (len); | |
e17a4113 UW |
1766 | store_unsigned_integer (val, len, byte_order, |
1767 | MAKE_THUMB_ADDR (regval)); | |
2dd604e7 RE |
1768 | } |
1769 | } | |
1770 | ||
1771 | /* Copy the argument to general registers or the stack in | |
1772 | register-sized pieces. Large arguments are split between | |
1773 | registers and stack. */ | |
1774 | while (len > 0) | |
1775 | { | |
f0c9063c | 1776 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 | 1777 | |
90445bd3 | 1778 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
1779 | { |
1780 | /* The argument is being passed in a general purpose | |
1781 | register. */ | |
e17a4113 UW |
1782 | CORE_ADDR regval |
1783 | = extract_unsigned_integer (val, partial_len, byte_order); | |
1784 | if (byte_order == BFD_ENDIAN_BIG) | |
8bf8793c | 1785 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
1786 | if (arm_debug) |
1787 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
1788 | argnum, |
1789 | gdbarch_register_name | |
2af46ca0 | 1790 | (gdbarch, argreg), |
f0c9063c | 1791 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
1792 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1793 | argreg++; | |
1794 | } | |
1795 | else | |
1796 | { | |
1797 | /* Push the arguments onto the stack. */ | |
1798 | if (arm_debug) | |
1799 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1800 | argnum, nstack); | |
f0c9063c UW |
1801 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
1802 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
1803 | } |
1804 | ||
1805 | len -= partial_len; | |
1806 | val += partial_len; | |
1807 | } | |
1808 | } | |
1809 | /* If we have an odd number of words to push, then decrement the stack | |
1810 | by one word now, so first stack argument will be dword aligned. */ | |
1811 | if (nstack & 4) | |
1812 | sp -= 4; | |
1813 | ||
1814 | while (si) | |
1815 | { | |
1816 | sp -= si->len; | |
1817 | write_memory (sp, si->data, si->len); | |
1818 | si = pop_stack_item (si); | |
1819 | } | |
1820 | ||
1821 | /* Finally, update teh SP register. */ | |
1822 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1823 | ||
1824 | return sp; | |
1825 | } | |
1826 | ||
f53f0d0b PB |
1827 | |
1828 | /* Always align the frame to an 8-byte boundary. This is required on | |
1829 | some platforms and harmless on the rest. */ | |
1830 | ||
1831 | static CORE_ADDR | |
1832 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1833 | { | |
1834 | /* Align the stack to eight bytes. */ | |
1835 | return sp & ~ (CORE_ADDR) 7; | |
1836 | } | |
1837 | ||
c906108c | 1838 | static void |
ed9a39eb | 1839 | print_fpu_flags (int flags) |
c906108c | 1840 | { |
c5aa993b JM |
1841 | if (flags & (1 << 0)) |
1842 | fputs ("IVO ", stdout); | |
1843 | if (flags & (1 << 1)) | |
1844 | fputs ("DVZ ", stdout); | |
1845 | if (flags & (1 << 2)) | |
1846 | fputs ("OFL ", stdout); | |
1847 | if (flags & (1 << 3)) | |
1848 | fputs ("UFL ", stdout); | |
1849 | if (flags & (1 << 4)) | |
1850 | fputs ("INX ", stdout); | |
1851 | putchar ('\n'); | |
c906108c SS |
1852 | } |
1853 | ||
5e74b15c RE |
1854 | /* Print interesting information about the floating point processor |
1855 | (if present) or emulator. */ | |
34e8f22d | 1856 | static void |
d855c300 | 1857 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1858 | struct frame_info *frame, const char *args) |
c906108c | 1859 | { |
9c9acae0 | 1860 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
1861 | int type; |
1862 | ||
1863 | type = (status >> 24) & 127; | |
edefbb7c AC |
1864 | if (status & (1 << 31)) |
1865 | printf (_("Hardware FPU type %d\n"), type); | |
1866 | else | |
1867 | printf (_("Software FPU type %d\n"), type); | |
1868 | /* i18n: [floating point unit] mask */ | |
1869 | fputs (_("mask: "), stdout); | |
c5aa993b | 1870 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1871 | /* i18n: [floating point unit] flags */ |
1872 | fputs (_("flags: "), stdout); | |
c5aa993b | 1873 | print_fpu_flags (status); |
c906108c SS |
1874 | } |
1875 | ||
27067745 UW |
1876 | /* Construct the ARM extended floating point type. */ |
1877 | static struct type * | |
1878 | arm_ext_type (struct gdbarch *gdbarch) | |
1879 | { | |
1880 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1881 | ||
1882 | if (!tdep->arm_ext_type) | |
1883 | tdep->arm_ext_type | |
e9bb382b | 1884 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
1885 | floatformats_arm_ext); |
1886 | ||
1887 | return tdep->arm_ext_type; | |
1888 | } | |
1889 | ||
58d6951d DJ |
1890 | static struct type * |
1891 | arm_neon_double_type (struct gdbarch *gdbarch) | |
1892 | { | |
1893 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1894 | ||
1895 | if (tdep->neon_double_type == NULL) | |
1896 | { | |
1897 | struct type *t, *elem; | |
1898 | ||
1899 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
1900 | TYPE_CODE_UNION); | |
1901 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1902 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
1903 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1904 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
1905 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1906 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
1907 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1908 | append_composite_type_field (t, "u64", elem); | |
1909 | elem = builtin_type (gdbarch)->builtin_float; | |
1910 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
1911 | elem = builtin_type (gdbarch)->builtin_double; | |
1912 | append_composite_type_field (t, "f64", elem); | |
1913 | ||
1914 | TYPE_VECTOR (t) = 1; | |
1915 | TYPE_NAME (t) = "neon_d"; | |
1916 | tdep->neon_double_type = t; | |
1917 | } | |
1918 | ||
1919 | return tdep->neon_double_type; | |
1920 | } | |
1921 | ||
1922 | /* FIXME: The vector types are not correctly ordered on big-endian | |
1923 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
1924 | bits of d0 - regardless of what unit size is being held in d0. So | |
1925 | the offset of the first uint8 in d0 is 7, but the offset of the | |
1926 | first float is 4. This code works as-is for little-endian | |
1927 | targets. */ | |
1928 | ||
1929 | static struct type * | |
1930 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
1931 | { | |
1932 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1933 | ||
1934 | if (tdep->neon_quad_type == NULL) | |
1935 | { | |
1936 | struct type *t, *elem; | |
1937 | ||
1938 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
1939 | TYPE_CODE_UNION); | |
1940 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1941 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
1942 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1943 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
1944 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1945 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
1946 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1947 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
1948 | elem = builtin_type (gdbarch)->builtin_float; | |
1949 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
1950 | elem = builtin_type (gdbarch)->builtin_double; | |
1951 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
1952 | ||
1953 | TYPE_VECTOR (t) = 1; | |
1954 | TYPE_NAME (t) = "neon_q"; | |
1955 | tdep->neon_quad_type = t; | |
1956 | } | |
1957 | ||
1958 | return tdep->neon_quad_type; | |
1959 | } | |
1960 | ||
34e8f22d RE |
1961 | /* Return the GDB type object for the "standard" data type of data in |
1962 | register N. */ | |
1963 | ||
1964 | static struct type * | |
7a5ea0d4 | 1965 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1966 | { |
58d6951d DJ |
1967 | int num_regs = gdbarch_num_regs (gdbarch); |
1968 | ||
1969 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
1970 | && regnum >= num_regs && regnum < num_regs + 32) | |
1971 | return builtin_type (gdbarch)->builtin_float; | |
1972 | ||
1973 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
1974 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
1975 | return arm_neon_quad_type (gdbarch); | |
1976 | ||
1977 | /* If the target description has register information, we are only | |
1978 | in this function so that we can override the types of | |
1979 | double-precision registers for NEON. */ | |
1980 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1981 | { | |
1982 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
1983 | ||
1984 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
1985 | && TYPE_CODE (t) == TYPE_CODE_FLT | |
1986 | && gdbarch_tdep (gdbarch)->have_neon) | |
1987 | return arm_neon_double_type (gdbarch); | |
1988 | else | |
1989 | return t; | |
1990 | } | |
1991 | ||
34e8f22d | 1992 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
1993 | { |
1994 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
1995 | return builtin_type (gdbarch)->builtin_void; | |
1996 | ||
1997 | return arm_ext_type (gdbarch); | |
1998 | } | |
e4c16157 | 1999 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 2000 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 2001 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 2002 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
2003 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
2004 | /* These registers are only supported on targets which supply | |
2005 | an XML description. */ | |
df4df182 | 2006 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 2007 | else |
df4df182 | 2008 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
2009 | } |
2010 | ||
ff6f572f DJ |
2011 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
2012 | number. */ | |
2013 | ||
2014 | static int | |
d3f73121 | 2015 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
2016 | { |
2017 | /* Core integer regs. */ | |
2018 | if (reg >= 0 && reg <= 15) | |
2019 | return reg; | |
2020 | ||
2021 | /* Legacy FPA encoding. These were once used in a way which | |
2022 | overlapped with VFP register numbering, so their use is | |
2023 | discouraged, but GDB doesn't support the ARM toolchain | |
2024 | which used them for VFP. */ | |
2025 | if (reg >= 16 && reg <= 23) | |
2026 | return ARM_F0_REGNUM + reg - 16; | |
2027 | ||
2028 | /* New assignments for the FPA registers. */ | |
2029 | if (reg >= 96 && reg <= 103) | |
2030 | return ARM_F0_REGNUM + reg - 96; | |
2031 | ||
2032 | /* WMMX register assignments. */ | |
2033 | if (reg >= 104 && reg <= 111) | |
2034 | return ARM_WCGR0_REGNUM + reg - 104; | |
2035 | ||
2036 | if (reg >= 112 && reg <= 127) | |
2037 | return ARM_WR0_REGNUM + reg - 112; | |
2038 | ||
2039 | if (reg >= 192 && reg <= 199) | |
2040 | return ARM_WC0_REGNUM + reg - 192; | |
2041 | ||
58d6951d DJ |
2042 | /* VFP v2 registers. A double precision value is actually |
2043 | in d1 rather than s2, but the ABI only defines numbering | |
2044 | for the single precision registers. This will "just work" | |
2045 | in GDB for little endian targets (we'll read eight bytes, | |
2046 | starting in s0 and then progressing to s1), but will be | |
2047 | reversed on big endian targets with VFP. This won't | |
2048 | be a problem for the new Neon quad registers; you're supposed | |
2049 | to use DW_OP_piece for those. */ | |
2050 | if (reg >= 64 && reg <= 95) | |
2051 | { | |
2052 | char name_buf[4]; | |
2053 | ||
2054 | sprintf (name_buf, "s%d", reg - 64); | |
2055 | return user_reg_map_name_to_regnum (gdbarch, name_buf, | |
2056 | strlen (name_buf)); | |
2057 | } | |
2058 | ||
2059 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
2060 | registers, except that it now describes d0 instead of s0. */ | |
2061 | if (reg >= 256 && reg <= 287) | |
2062 | { | |
2063 | char name_buf[4]; | |
2064 | ||
2065 | sprintf (name_buf, "d%d", reg - 256); | |
2066 | return user_reg_map_name_to_regnum (gdbarch, name_buf, | |
2067 | strlen (name_buf)); | |
2068 | } | |
2069 | ||
ff6f572f DJ |
2070 | return -1; |
2071 | } | |
2072 | ||
26216b98 AC |
2073 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
2074 | static int | |
e7faf938 | 2075 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
2076 | { |
2077 | int reg = regnum; | |
e7faf938 | 2078 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 2079 | |
ff6f572f DJ |
2080 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
2081 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
2082 | ||
2083 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
2084 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
2085 | ||
2086 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
2087 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
2088 | ||
26216b98 AC |
2089 | if (reg < NUM_GREGS) |
2090 | return SIM_ARM_R0_REGNUM + reg; | |
2091 | reg -= NUM_GREGS; | |
2092 | ||
2093 | if (reg < NUM_FREGS) | |
2094 | return SIM_ARM_FP0_REGNUM + reg; | |
2095 | reg -= NUM_FREGS; | |
2096 | ||
2097 | if (reg < NUM_SREGS) | |
2098 | return SIM_ARM_FPS_REGNUM + reg; | |
2099 | reg -= NUM_SREGS; | |
2100 | ||
edefbb7c | 2101 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 2102 | } |
34e8f22d | 2103 | |
a37b3cc0 AC |
2104 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
2105 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
2106 | It is thought that this is is the floating-point register format on | |
2107 | little-endian systems. */ | |
c906108c | 2108 | |
ed9a39eb | 2109 | static void |
b508a996 | 2110 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 2111 | void *dbl, int endianess) |
c906108c | 2112 | { |
a37b3cc0 | 2113 | DOUBLEST d; |
be8626e0 MD |
2114 | |
2115 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
2116 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
2117 | else | |
2118 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
2119 | ptr, &d); | |
b508a996 | 2120 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
2121 | } |
2122 | ||
34e8f22d | 2123 | static void |
be8626e0 MD |
2124 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
2125 | int endianess) | |
c906108c | 2126 | { |
a37b3cc0 | 2127 | DOUBLEST d; |
be8626e0 | 2128 | |
b508a996 | 2129 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 2130 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
2131 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
2132 | else | |
2133 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
2134 | &d, dbl); | |
c906108c | 2135 | } |
ed9a39eb | 2136 | |
c906108c | 2137 | static int |
ed9a39eb | 2138 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
2139 | { |
2140 | if (cond == INST_AL || cond == INST_NV) | |
2141 | return 1; | |
2142 | ||
2143 | switch (cond) | |
2144 | { | |
2145 | case INST_EQ: | |
2146 | return ((status_reg & FLAG_Z) != 0); | |
2147 | case INST_NE: | |
2148 | return ((status_reg & FLAG_Z) == 0); | |
2149 | case INST_CS: | |
2150 | return ((status_reg & FLAG_C) != 0); | |
2151 | case INST_CC: | |
2152 | return ((status_reg & FLAG_C) == 0); | |
2153 | case INST_MI: | |
2154 | return ((status_reg & FLAG_N) != 0); | |
2155 | case INST_PL: | |
2156 | return ((status_reg & FLAG_N) == 0); | |
2157 | case INST_VS: | |
2158 | return ((status_reg & FLAG_V) != 0); | |
2159 | case INST_VC: | |
2160 | return ((status_reg & FLAG_V) == 0); | |
2161 | case INST_HI: | |
2162 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
2163 | case INST_LS: | |
2164 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
2165 | case INST_GE: | |
2166 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
2167 | case INST_LT: | |
2168 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
2169 | case INST_GT: | |
2170 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 2171 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
2172 | case INST_LE: |
2173 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 2174 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
2175 | } |
2176 | return 1; | |
2177 | } | |
2178 | ||
9512d7fd | 2179 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
2180 | #define submask(x) ((1L << ((x) + 1)) - 1) |
2181 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
2182 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
2183 | #define sbits(obj,st,fn) \ | |
2184 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
2185 | #define BranchDest(addr,instr) \ | |
2186 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
2187 | #define ARM_PC_32 1 | |
2188 | ||
2189 | static unsigned long | |
0b1b3e42 UW |
2190 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
2191 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
2192 | { |
2193 | unsigned long res, shift; | |
2194 | int rm = bits (inst, 0, 3); | |
2195 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
2196 | |
2197 | if (bit (inst, 4)) | |
c906108c SS |
2198 | { |
2199 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
2200 | shift = (rs == 15 ? pc_val + 8 |
2201 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
2202 | } |
2203 | else | |
2204 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
2205 | |
2206 | res = (rm == 15 | |
c906108c | 2207 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 2208 | + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 2209 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
2210 | |
2211 | switch (shifttype) | |
2212 | { | |
c5aa993b | 2213 | case 0: /* LSL */ |
c906108c SS |
2214 | res = shift >= 32 ? 0 : res << shift; |
2215 | break; | |
c5aa993b JM |
2216 | |
2217 | case 1: /* LSR */ | |
c906108c SS |
2218 | res = shift >= 32 ? 0 : res >> shift; |
2219 | break; | |
2220 | ||
c5aa993b JM |
2221 | case 2: /* ASR */ |
2222 | if (shift >= 32) | |
2223 | shift = 31; | |
c906108c SS |
2224 | res = ((res & 0x80000000L) |
2225 | ? ~((~res) >> shift) : res >> shift); | |
2226 | break; | |
2227 | ||
c5aa993b | 2228 | case 3: /* ROR/RRX */ |
c906108c SS |
2229 | shift &= 31; |
2230 | if (shift == 0) | |
2231 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
2232 | else | |
c5aa993b | 2233 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
2234 | break; |
2235 | } | |
2236 | ||
2237 | return res & 0xffffffff; | |
2238 | } | |
2239 | ||
c906108c SS |
2240 | /* Return number of 1-bits in VAL. */ |
2241 | ||
2242 | static int | |
ed9a39eb | 2243 | bitcount (unsigned long val) |
c906108c SS |
2244 | { |
2245 | int nbits; | |
2246 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 2247 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
2248 | return nbits; |
2249 | } | |
2250 | ||
ad527d2e | 2251 | static CORE_ADDR |
0b1b3e42 | 2252 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2253 | { |
2af46ca0 | 2254 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
2255 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2256 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c5aa993b | 2257 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
e17a4113 | 2258 | unsigned short inst1; |
94c30b78 | 2259 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
2260 | unsigned long offset; |
2261 | ||
e17a4113 | 2262 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); |
9d4fde75 | 2263 | |
c906108c SS |
2264 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
2265 | { | |
2266 | CORE_ADDR sp; | |
2267 | ||
2268 | /* Fetch the saved PC from the stack. It's stored above | |
2269 | all of the other registers. */ | |
f0c9063c | 2270 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 2271 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
e17a4113 | 2272 | nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); |
2af46ca0 | 2273 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 2274 | if (nextpc == pc) |
edefbb7c | 2275 | error (_("Infinite loop detected")); |
c906108c SS |
2276 | } |
2277 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
2278 | { | |
0b1b3e42 | 2279 | unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 2280 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 2281 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
2282 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
2283 | } | |
2284 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
2285 | { | |
2286 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
2287 | } | |
aa17d93e | 2288 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 2289 | { |
e17a4113 UW |
2290 | unsigned short inst2; |
2291 | inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
c5aa993b | 2292 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 2293 | nextpc = pc_val + offset; |
aa17d93e DJ |
2294 | /* For BLX make sure to clear the low bits. */ |
2295 | if (bits (inst2, 11, 12) == 1) | |
2296 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 2297 | } |
aa17d93e | 2298 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
2299 | { |
2300 | if (bits (inst1, 3, 6) == 0x0f) | |
2301 | nextpc = pc_val; | |
2302 | else | |
0b1b3e42 | 2303 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 2304 | |
2af46ca0 | 2305 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
9498281f | 2306 | if (nextpc == pc) |
edefbb7c | 2307 | error (_("Infinite loop detected")); |
9498281f | 2308 | } |
c906108c SS |
2309 | |
2310 | return nextpc; | |
2311 | } | |
2312 | ||
daddc3c1 | 2313 | CORE_ADDR |
0b1b3e42 | 2314 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2315 | { |
2af46ca0 | 2316 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
2317 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2318 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c906108c SS |
2319 | unsigned long pc_val; |
2320 | unsigned long this_instr; | |
2321 | unsigned long status; | |
2322 | CORE_ADDR nextpc; | |
2323 | ||
b39cc962 | 2324 | if (arm_frame_is_thumb (frame)) |
0b1b3e42 | 2325 | return thumb_get_next_pc (frame, pc); |
c906108c SS |
2326 | |
2327 | pc_val = (unsigned long) pc; | |
e17a4113 | 2328 | this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); |
9d4fde75 | 2329 | |
0b1b3e42 | 2330 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 2331 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 2332 | |
daddc3c1 DJ |
2333 | if (bits (this_instr, 28, 31) == INST_NV) |
2334 | switch (bits (this_instr, 24, 27)) | |
2335 | { | |
2336 | case 0xa: | |
2337 | case 0xb: | |
2338 | { | |
2339 | /* Branch with Link and change to Thumb. */ | |
2340 | nextpc = BranchDest (pc, this_instr); | |
2341 | nextpc |= bit (this_instr, 24) << 1; | |
2342 | ||
e1e01acd | 2343 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
daddc3c1 DJ |
2344 | if (nextpc == pc) |
2345 | error (_("Infinite loop detected")); | |
2346 | break; | |
2347 | } | |
2348 | case 0xc: | |
2349 | case 0xd: | |
2350 | case 0xe: | |
2351 | /* Coprocessor register transfer. */ | |
2352 | if (bits (this_instr, 12, 15) == 15) | |
2353 | error (_("Invalid update to pc in instruction")); | |
2354 | break; | |
2355 | } | |
2356 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
2357 | { |
2358 | switch (bits (this_instr, 24, 27)) | |
2359 | { | |
c5aa993b | 2360 | case 0x0: |
94c30b78 | 2361 | case 0x1: /* data processing */ |
c5aa993b JM |
2362 | case 0x2: |
2363 | case 0x3: | |
c906108c SS |
2364 | { |
2365 | unsigned long operand1, operand2, result = 0; | |
2366 | unsigned long rn; | |
2367 | int c; | |
c5aa993b | 2368 | |
c906108c SS |
2369 | if (bits (this_instr, 12, 15) != 15) |
2370 | break; | |
2371 | ||
2372 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 2373 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 2374 | error (_("Invalid update to pc in instruction")); |
c906108c | 2375 | |
9498281f | 2376 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
2377 | if (bits (this_instr, 4, 27) == 0x12fff1 |
2378 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
2379 | { |
2380 | rn = bits (this_instr, 0, 3); | |
0b1b3e42 UW |
2381 | result = (rn == 15) ? pc_val + 8 |
2382 | : get_frame_register_unsigned (frame, rn); | |
bf6ae464 | 2383 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 2384 | (gdbarch, result); |
9498281f DJ |
2385 | |
2386 | if (nextpc == pc) | |
edefbb7c | 2387 | error (_("Infinite loop detected")); |
9498281f DJ |
2388 | |
2389 | return nextpc; | |
2390 | } | |
2391 | ||
c906108c SS |
2392 | /* Multiply into PC */ |
2393 | c = (status & FLAG_C) ? 1 : 0; | |
2394 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
2395 | operand1 = (rn == 15) ? pc_val + 8 |
2396 | : get_frame_register_unsigned (frame, rn); | |
c5aa993b | 2397 | |
c906108c SS |
2398 | if (bit (this_instr, 25)) |
2399 | { | |
2400 | unsigned long immval = bits (this_instr, 0, 7); | |
2401 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
2402 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
2403 | & 0xffffffff; | |
c906108c | 2404 | } |
c5aa993b | 2405 | else /* operand 2 is a shifted register */ |
0b1b3e42 | 2406 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
c5aa993b | 2407 | |
c906108c SS |
2408 | switch (bits (this_instr, 21, 24)) |
2409 | { | |
c5aa993b | 2410 | case 0x0: /*and */ |
c906108c SS |
2411 | result = operand1 & operand2; |
2412 | break; | |
2413 | ||
c5aa993b | 2414 | case 0x1: /*eor */ |
c906108c SS |
2415 | result = operand1 ^ operand2; |
2416 | break; | |
2417 | ||
c5aa993b | 2418 | case 0x2: /*sub */ |
c906108c SS |
2419 | result = operand1 - operand2; |
2420 | break; | |
2421 | ||
c5aa993b | 2422 | case 0x3: /*rsb */ |
c906108c SS |
2423 | result = operand2 - operand1; |
2424 | break; | |
2425 | ||
c5aa993b | 2426 | case 0x4: /*add */ |
c906108c SS |
2427 | result = operand1 + operand2; |
2428 | break; | |
2429 | ||
c5aa993b | 2430 | case 0x5: /*adc */ |
c906108c SS |
2431 | result = operand1 + operand2 + c; |
2432 | break; | |
2433 | ||
c5aa993b | 2434 | case 0x6: /*sbc */ |
c906108c SS |
2435 | result = operand1 - operand2 + c; |
2436 | break; | |
2437 | ||
c5aa993b | 2438 | case 0x7: /*rsc */ |
c906108c SS |
2439 | result = operand2 - operand1 + c; |
2440 | break; | |
2441 | ||
c5aa993b JM |
2442 | case 0x8: |
2443 | case 0x9: | |
2444 | case 0xa: | |
2445 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
2446 | result = (unsigned long) nextpc; |
2447 | break; | |
2448 | ||
c5aa993b | 2449 | case 0xc: /*orr */ |
c906108c SS |
2450 | result = operand1 | operand2; |
2451 | break; | |
2452 | ||
c5aa993b | 2453 | case 0xd: /*mov */ |
c906108c SS |
2454 | /* Always step into a function. */ |
2455 | result = operand2; | |
c5aa993b | 2456 | break; |
c906108c | 2457 | |
c5aa993b | 2458 | case 0xe: /*bic */ |
c906108c SS |
2459 | result = operand1 & ~operand2; |
2460 | break; | |
2461 | ||
c5aa993b | 2462 | case 0xf: /*mvn */ |
c906108c SS |
2463 | result = ~operand2; |
2464 | break; | |
2465 | } | |
bf6ae464 | 2466 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 2467 | (gdbarch, result); |
c906108c SS |
2468 | |
2469 | if (nextpc == pc) | |
edefbb7c | 2470 | error (_("Infinite loop detected")); |
c906108c SS |
2471 | break; |
2472 | } | |
c5aa993b JM |
2473 | |
2474 | case 0x4: | |
2475 | case 0x5: /* data transfer */ | |
2476 | case 0x6: | |
2477 | case 0x7: | |
c906108c SS |
2478 | if (bit (this_instr, 20)) |
2479 | { | |
2480 | /* load */ | |
2481 | if (bits (this_instr, 12, 15) == 15) | |
2482 | { | |
2483 | /* rd == pc */ | |
c5aa993b | 2484 | unsigned long rn; |
c906108c | 2485 | unsigned long base; |
c5aa993b | 2486 | |
c906108c | 2487 | if (bit (this_instr, 22)) |
edefbb7c | 2488 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
2489 | |
2490 | /* byte write to PC */ | |
2491 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
2492 | base = (rn == 15) ? pc_val + 8 |
2493 | : get_frame_register_unsigned (frame, rn); | |
c906108c SS |
2494 | if (bit (this_instr, 24)) |
2495 | { | |
2496 | /* pre-indexed */ | |
2497 | int c = (status & FLAG_C) ? 1 : 0; | |
2498 | unsigned long offset = | |
c5aa993b | 2499 | (bit (this_instr, 25) |
0b1b3e42 | 2500 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 2501 | : bits (this_instr, 0, 11)); |
c906108c SS |
2502 | |
2503 | if (bit (this_instr, 23)) | |
2504 | base += offset; | |
2505 | else | |
2506 | base -= offset; | |
2507 | } | |
c5aa993b | 2508 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
e17a4113 | 2509 | 4, byte_order); |
c5aa993b | 2510 | |
2af46ca0 | 2511 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c SS |
2512 | |
2513 | if (nextpc == pc) | |
edefbb7c | 2514 | error (_("Infinite loop detected")); |
c906108c SS |
2515 | } |
2516 | } | |
2517 | break; | |
c5aa993b JM |
2518 | |
2519 | case 0x8: | |
2520 | case 0x9: /* block transfer */ | |
c906108c SS |
2521 | if (bit (this_instr, 20)) |
2522 | { | |
2523 | /* LDM */ | |
2524 | if (bit (this_instr, 15)) | |
2525 | { | |
2526 | /* loading pc */ | |
2527 | int offset = 0; | |
2528 | ||
2529 | if (bit (this_instr, 23)) | |
2530 | { | |
2531 | /* up */ | |
2532 | unsigned long reglist = bits (this_instr, 0, 14); | |
2533 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2534 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2535 | offset += 4; |
2536 | } | |
2537 | else if (bit (this_instr, 24)) | |
2538 | offset = -4; | |
c5aa993b | 2539 | |
c906108c | 2540 | { |
c5aa993b | 2541 | unsigned long rn_val = |
0b1b3e42 UW |
2542 | get_frame_register_unsigned (frame, |
2543 | bits (this_instr, 16, 19)); | |
c906108c SS |
2544 | nextpc = |
2545 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2546 | + offset), |
e17a4113 | 2547 | 4, byte_order); |
c906108c | 2548 | } |
bf6ae464 | 2549 | nextpc = gdbarch_addr_bits_remove |
2af46ca0 | 2550 | (gdbarch, nextpc); |
c906108c | 2551 | if (nextpc == pc) |
edefbb7c | 2552 | error (_("Infinite loop detected")); |
c906108c SS |
2553 | } |
2554 | } | |
2555 | break; | |
c5aa993b JM |
2556 | |
2557 | case 0xb: /* branch & link */ | |
2558 | case 0xa: /* branch */ | |
c906108c SS |
2559 | { |
2560 | nextpc = BranchDest (pc, this_instr); | |
2561 | ||
2af46ca0 | 2562 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 2563 | if (nextpc == pc) |
edefbb7c | 2564 | error (_("Infinite loop detected")); |
c906108c SS |
2565 | break; |
2566 | } | |
c5aa993b JM |
2567 | |
2568 | case 0xc: | |
2569 | case 0xd: | |
2570 | case 0xe: /* coproc ops */ | |
2571 | case 0xf: /* SWI */ | |
c906108c SS |
2572 | break; |
2573 | ||
2574 | default: | |
edefbb7c | 2575 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
2576 | return (pc); |
2577 | } | |
2578 | } | |
2579 | ||
2580 | return nextpc; | |
2581 | } | |
2582 | ||
9512d7fd FN |
2583 | /* single_step() is called just before we want to resume the inferior, |
2584 | if we want to single-step it but there is no hardware or kernel | |
2585 | single-step support. We find the target of the coming instruction | |
e0cd558a | 2586 | and breakpoint it. */ |
9512d7fd | 2587 | |
190dce09 | 2588 | int |
0b1b3e42 | 2589 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 2590 | { |
a6d9a66e UW |
2591 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2592 | ||
8181d85f DJ |
2593 | /* NOTE: This may insert the wrong breakpoint instruction when |
2594 | single-stepping over a mode-changing instruction, if the | |
2595 | CPSR heuristics are used. */ | |
9512d7fd | 2596 | |
0b1b3e42 | 2597 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
a6d9a66e | 2598 | insert_single_step_breakpoint (gdbarch, next_pc); |
e6590a1b UW |
2599 | |
2600 | return 1; | |
9512d7fd | 2601 | } |
9512d7fd | 2602 | |
c906108c SS |
2603 | #include "bfd-in2.h" |
2604 | #include "libcoff.h" | |
2605 | ||
2606 | static int | |
ed9a39eb | 2607 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2608 | { |
2609 | if (arm_pc_is_thumb (memaddr)) | |
2610 | { | |
c5aa993b JM |
2611 | static asymbol *asym; |
2612 | static combined_entry_type ce; | |
2613 | static struct coff_symbol_struct csym; | |
27cddce2 | 2614 | static struct bfd fake_bfd; |
c5aa993b | 2615 | static bfd_target fake_target; |
c906108c SS |
2616 | |
2617 | if (csym.native == NULL) | |
2618 | { | |
da3c6d4a MS |
2619 | /* Create a fake symbol vector containing a Thumb symbol. |
2620 | This is solely so that the code in print_insn_little_arm() | |
2621 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2622 | the presence of a Thumb symbol and switch to decoding | |
2623 | Thumb instructions. */ | |
c5aa993b JM |
2624 | |
2625 | fake_target.flavour = bfd_target_coff_flavour; | |
2626 | fake_bfd.xvec = &fake_target; | |
c906108c | 2627 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2628 | csym.native = &ce; |
2629 | csym.symbol.the_bfd = &fake_bfd; | |
2630 | csym.symbol.name = "fake"; | |
2631 | asym = (asymbol *) & csym; | |
c906108c | 2632 | } |
c5aa993b | 2633 | |
c906108c | 2634 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2635 | info->symbols = &asym; |
c906108c SS |
2636 | } |
2637 | else | |
2638 | info->symbols = NULL; | |
c5aa993b | 2639 | |
40887e1a | 2640 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
2641 | return print_insn_big_arm (memaddr, info); |
2642 | else | |
2643 | return print_insn_little_arm (memaddr, info); | |
2644 | } | |
2645 | ||
66e810cd RE |
2646 | /* The following define instruction sequences that will cause ARM |
2647 | cpu's to take an undefined instruction trap. These are used to | |
2648 | signal a breakpoint to GDB. | |
2649 | ||
2650 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2651 | modes. A different instruction is required for each mode. The ARM | |
2652 | cpu's can also be big or little endian. Thus four different | |
2653 | instructions are needed to support all cases. | |
2654 | ||
2655 | Note: ARMv4 defines several new instructions that will take the | |
2656 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2657 | not in fact add the new instructions. The new undefined | |
2658 | instructions in ARMv4 are all instructions that had no defined | |
2659 | behaviour in earlier chips. There is no guarantee that they will | |
2660 | raise an exception, but may be treated as NOP's. In practice, it | |
2661 | may only safe to rely on instructions matching: | |
2662 | ||
2663 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2664 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2665 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2666 | ||
2667 | Even this may only true if the condition predicate is true. The | |
2668 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2669 | ||
2670 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2671 | and NetBSD all use a software interrupt rather than an undefined | |
2672 | instruction to force a trap. This can be handled by by the | |
2673 | abi-specific code during establishment of the gdbarch vector. */ | |
2674 | ||
66e810cd | 2675 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
66e810cd | 2676 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
190dce09 UW |
2677 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
2678 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
66e810cd RE |
2679 | |
2680 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2681 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2682 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2683 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2684 | ||
34e8f22d RE |
2685 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2686 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2687 | breakpoint should be used. It returns a pointer to a string of |
2688 | bytes that encode a breakpoint instruction, stores the length of | |
2689 | the string to *lenptr, and adjusts the program counter (if | |
2690 | necessary) to point to the actual memory location where the | |
c906108c SS |
2691 | breakpoint should be inserted. */ |
2692 | ||
ab89facf | 2693 | static const unsigned char * |
67d57894 | 2694 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2695 | { |
67d57894 | 2696 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
66e810cd | 2697 | |
4bf7064c | 2698 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 2699 | { |
66e810cd RE |
2700 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2701 | *lenptr = tdep->thumb_breakpoint_size; | |
2702 | return tdep->thumb_breakpoint; | |
c906108c SS |
2703 | } |
2704 | else | |
2705 | { | |
66e810cd RE |
2706 | *lenptr = tdep->arm_breakpoint_size; |
2707 | return tdep->arm_breakpoint; | |
c906108c SS |
2708 | } |
2709 | } | |
ed9a39eb JM |
2710 | |
2711 | /* Extract from an array REGBUF containing the (raw) register state a | |
2712 | function return value of type TYPE, and copy that, in virtual | |
2713 | format, into VALBUF. */ | |
2714 | ||
34e8f22d | 2715 | static void |
5238cf52 MK |
2716 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2717 | gdb_byte *valbuf) | |
ed9a39eb | 2718 | { |
be8626e0 | 2719 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 2720 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 2721 | |
ed9a39eb | 2722 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2723 | { |
be8626e0 | 2724 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2725 | { |
2726 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2727 | { |
2728 | /* The value is in register F0 in internal format. We need to | |
2729 | extract the raw value and then convert it to the desired | |
2730 | internal type. */ | |
7a5ea0d4 | 2731 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2732 | |
2733 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2734 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
be8626e0 | 2735 | valbuf, gdbarch_byte_order (gdbarch)); |
b508a996 | 2736 | } |
08216dd7 RE |
2737 | break; |
2738 | ||
fd50bc42 | 2739 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2740 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
2741 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
2742 | not using the VFP ABI code. */ | |
2743 | case ARM_FLOAT_VFP: | |
b508a996 RE |
2744 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2745 | if (TYPE_LENGTH (type) > 4) | |
2746 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2747 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2748 | break; |
2749 | ||
2750 | default: | |
2751 | internal_error | |
2752 | (__FILE__, __LINE__, | |
edefbb7c | 2753 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2754 | break; |
2755 | } | |
2756 | } | |
b508a996 RE |
2757 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2758 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2759 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2760 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2761 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2762 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2763 | { | |
2764 | /* If the the type is a plain integer, then the access is | |
2765 | straight-forward. Otherwise we have to play around a bit more. */ | |
2766 | int len = TYPE_LENGTH (type); | |
2767 | int regno = ARM_A1_REGNUM; | |
2768 | ULONGEST tmp; | |
2769 | ||
2770 | while (len > 0) | |
2771 | { | |
2772 | /* By using store_unsigned_integer we avoid having to do | |
2773 | anything special for small big-endian values. */ | |
2774 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2775 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2776 | (len > INT_REGISTER_SIZE |
2777 | ? INT_REGISTER_SIZE : len), | |
e17a4113 | 2778 | byte_order, tmp); |
7a5ea0d4 DJ |
2779 | len -= INT_REGISTER_SIZE; |
2780 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2781 | } |
2782 | } | |
ed9a39eb | 2783 | else |
b508a996 RE |
2784 | { |
2785 | /* For a structure or union the behaviour is as if the value had | |
2786 | been stored to word-aligned memory and then loaded into | |
2787 | registers with 32-bit load instruction(s). */ | |
2788 | int len = TYPE_LENGTH (type); | |
2789 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2790 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2791 | |
2792 | while (len > 0) | |
2793 | { | |
2794 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2795 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2796 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2797 | len -= INT_REGISTER_SIZE; | |
2798 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2799 | } |
2800 | } | |
34e8f22d RE |
2801 | } |
2802 | ||
67255d04 RE |
2803 | |
2804 | /* Will a function return an aggregate type in memory or in a | |
2805 | register? Return 0 if an aggregate type can be returned in a | |
2806 | register, 1 if it must be returned in memory. */ | |
2807 | ||
2808 | static int | |
2af48f68 | 2809 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2810 | { |
2811 | int nRc; | |
52f0bd74 | 2812 | enum type_code code; |
67255d04 | 2813 | |
44e1a9eb DJ |
2814 | CHECK_TYPEDEF (type); |
2815 | ||
67255d04 RE |
2816 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2817 | registers. For an aggregate type to be integer like, its size | |
f0c9063c | 2818 | must be less than or equal to INT_REGISTER_SIZE and the |
b1e29e33 AC |
2819 | offset of each addressable subfield must be zero. Note that bit |
2820 | fields are not addressable, and all addressable subfields of | |
2821 | unions always start at offset zero. | |
67255d04 RE |
2822 | |
2823 | This function is based on the behaviour of GCC 2.95.1. | |
2824 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2825 | ||
2826 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2827 | parameters correctly for a function returning the following | |
2828 | structure: struct { float f;}; This should be returned in memory, | |
2829 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2830 | know of any way to detect if a function like the above has been | |
2831 | compiled with the correct calling convention. */ | |
2832 | ||
2833 | /* All aggregate types that won't fit in a register must be returned | |
2834 | in memory. */ | |
f0c9063c | 2835 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
67255d04 RE |
2836 | { |
2837 | return 1; | |
2838 | } | |
2839 | ||
2af48f68 PB |
2840 | /* The AAPCS says all aggregates not larger than a word are returned |
2841 | in a register. */ | |
2842 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2843 | return 0; | |
2844 | ||
67255d04 RE |
2845 | /* The only aggregate types that can be returned in a register are |
2846 | structs and unions. Arrays must be returned in memory. */ | |
2847 | code = TYPE_CODE (type); | |
2848 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2849 | { | |
2850 | return 1; | |
2851 | } | |
2852 | ||
2853 | /* Assume all other aggregate types can be returned in a register. | |
2854 | Run a check for structures, unions and arrays. */ | |
2855 | nRc = 0; | |
2856 | ||
2857 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2858 | { | |
2859 | int i; | |
2860 | /* Need to check if this struct/union is "integer" like. For | |
2861 | this to be true, its size must be less than or equal to | |
f0c9063c | 2862 | INT_REGISTER_SIZE and the offset of each addressable |
b1e29e33 AC |
2863 | subfield must be zero. Note that bit fields are not |
2864 | addressable, and unions always start at offset zero. If any | |
2865 | of the subfields is a floating point type, the struct/union | |
2866 | cannot be an integer type. */ | |
67255d04 RE |
2867 | |
2868 | /* For each field in the object, check: | |
2869 | 1) Is it FP? --> yes, nRc = 1; | |
2870 | 2) Is it addressable (bitpos != 0) and | |
2871 | not packed (bitsize == 0)? | |
2872 | --> yes, nRc = 1 | |
2873 | */ | |
2874 | ||
2875 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2876 | { | |
2877 | enum type_code field_type_code; | |
44e1a9eb | 2878 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2879 | |
2880 | /* Is it a floating point type field? */ | |
2881 | if (field_type_code == TYPE_CODE_FLT) | |
2882 | { | |
2883 | nRc = 1; | |
2884 | break; | |
2885 | } | |
2886 | ||
2887 | /* If bitpos != 0, then we have to care about it. */ | |
2888 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2889 | { | |
2890 | /* Bitfields are not addressable. If the field bitsize is | |
2891 | zero, then the field is not packed. Hence it cannot be | |
2892 | a bitfield or any other packed type. */ | |
2893 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2894 | { | |
2895 | nRc = 1; | |
2896 | break; | |
2897 | } | |
2898 | } | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | return nRc; | |
2903 | } | |
2904 | ||
34e8f22d RE |
2905 | /* Write into appropriate registers a function return value of type |
2906 | TYPE, given in virtual format. */ | |
2907 | ||
2908 | static void | |
b508a996 | 2909 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2910 | const gdb_byte *valbuf) |
34e8f22d | 2911 | { |
be8626e0 | 2912 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 2913 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 2914 | |
34e8f22d RE |
2915 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2916 | { | |
7a5ea0d4 | 2917 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2918 | |
be8626e0 | 2919 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2920 | { |
2921 | case ARM_FLOAT_FPA: | |
2922 | ||
be8626e0 MD |
2923 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
2924 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 2925 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
2926 | break; |
2927 | ||
fd50bc42 | 2928 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2929 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
2930 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
2931 | not using the VFP ABI code. */ | |
2932 | case ARM_FLOAT_VFP: | |
b508a996 RE |
2933 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2934 | if (TYPE_LENGTH (type) > 4) | |
2935 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2936 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2937 | break; |
2938 | ||
2939 | default: | |
2940 | internal_error | |
2941 | (__FILE__, __LINE__, | |
edefbb7c | 2942 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2943 | break; |
2944 | } | |
34e8f22d | 2945 | } |
b508a996 RE |
2946 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2947 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2948 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2949 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2950 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2951 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2952 | { | |
2953 | if (TYPE_LENGTH (type) <= 4) | |
2954 | { | |
2955 | /* Values of one word or less are zero/sign-extended and | |
2956 | returned in r0. */ | |
7a5ea0d4 | 2957 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2958 | LONGEST val = unpack_long (type, valbuf); |
2959 | ||
e17a4113 | 2960 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
b508a996 RE |
2961 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2962 | } | |
2963 | else | |
2964 | { | |
2965 | /* Integral values greater than one word are stored in consecutive | |
2966 | registers starting with r0. This will always be a multiple of | |
2967 | the regiser size. */ | |
2968 | int len = TYPE_LENGTH (type); | |
2969 | int regno = ARM_A1_REGNUM; | |
2970 | ||
2971 | while (len > 0) | |
2972 | { | |
2973 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2974 | len -= INT_REGISTER_SIZE; |
2975 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2976 | } |
2977 | } | |
2978 | } | |
34e8f22d | 2979 | else |
b508a996 RE |
2980 | { |
2981 | /* For a structure or union the behaviour is as if the value had | |
2982 | been stored to word-aligned memory and then loaded into | |
2983 | registers with 32-bit load instruction(s). */ | |
2984 | int len = TYPE_LENGTH (type); | |
2985 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2986 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2987 | |
2988 | while (len > 0) | |
2989 | { | |
2990 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2991 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2992 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2993 | len -= INT_REGISTER_SIZE; |
2994 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2995 | } |
2996 | } | |
34e8f22d RE |
2997 | } |
2998 | ||
2af48f68 PB |
2999 | |
3000 | /* Handle function return values. */ | |
3001 | ||
3002 | static enum return_value_convention | |
c055b101 CV |
3003 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3004 | struct type *valtype, struct regcache *regcache, | |
3005 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 3006 | { |
7c00367c | 3007 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
90445bd3 DJ |
3008 | enum arm_vfp_cprc_base_type vfp_base_type; |
3009 | int vfp_base_count; | |
3010 | ||
3011 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
3012 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
3013 | { | |
3014 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3015 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3016 | int i; | |
3017 | for (i = 0; i < vfp_base_count; i++) | |
3018 | { | |
58d6951d DJ |
3019 | if (reg_char == 'q') |
3020 | { | |
3021 | if (writebuf) | |
3022 | arm_neon_quad_write (gdbarch, regcache, i, | |
3023 | writebuf + i * unit_length); | |
3024 | ||
3025 | if (readbuf) | |
3026 | arm_neon_quad_read (gdbarch, regcache, i, | |
3027 | readbuf + i * unit_length); | |
3028 | } | |
3029 | else | |
3030 | { | |
3031 | char name_buf[4]; | |
3032 | int regnum; | |
3033 | ||
3034 | sprintf (name_buf, "%c%d", reg_char, i); | |
3035 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
3036 | strlen (name_buf)); | |
3037 | if (writebuf) | |
3038 | regcache_cooked_write (regcache, regnum, | |
3039 | writebuf + i * unit_length); | |
3040 | if (readbuf) | |
3041 | regcache_cooked_read (regcache, regnum, | |
3042 | readbuf + i * unit_length); | |
3043 | } | |
90445bd3 DJ |
3044 | } |
3045 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3046 | } | |
7c00367c | 3047 | |
2af48f68 PB |
3048 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
3049 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
3050 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
3051 | { | |
7c00367c MK |
3052 | if (tdep->struct_return == pcc_struct_return |
3053 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
3054 | return RETURN_VALUE_STRUCT_CONVENTION; |
3055 | } | |
3056 | ||
3057 | if (writebuf) | |
3058 | arm_store_return_value (valtype, regcache, writebuf); | |
3059 | ||
3060 | if (readbuf) | |
3061 | arm_extract_return_value (valtype, regcache, readbuf); | |
3062 | ||
3063 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3064 | } | |
3065 | ||
3066 | ||
9df628e0 | 3067 | static int |
60ade65d | 3068 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 3069 | { |
e17a4113 UW |
3070 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3071 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3072 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 3073 | CORE_ADDR jb_addr; |
7a5ea0d4 | 3074 | char buf[INT_REGISTER_SIZE]; |
9df628e0 | 3075 | |
60ade65d | 3076 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
3077 | |
3078 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 3079 | INT_REGISTER_SIZE)) |
9df628e0 RE |
3080 | return 0; |
3081 | ||
e17a4113 | 3082 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
3083 | return 1; |
3084 | } | |
3085 | ||
faa95490 DJ |
3086 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
3087 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
3088 | |
3089 | CORE_ADDR | |
52f729a7 | 3090 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 3091 | { |
c5aa993b | 3092 | char *name; |
faa95490 | 3093 | int namelen; |
c906108c SS |
3094 | CORE_ADDR start_addr; |
3095 | ||
3096 | /* Find the starting address and name of the function containing the PC. */ | |
3097 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3098 | return 0; | |
3099 | ||
faa95490 DJ |
3100 | /* If PC is in a Thumb call or return stub, return the address of the |
3101 | target PC, which is in a register. The thunk functions are called | |
3102 | _call_via_xx, where x is the register name. The possible names | |
3103 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
3104 | if (strncmp (name, "_call_via_", 10) == 0) |
3105 | { | |
ed9a39eb JM |
3106 | /* Use the name suffix to determine which register contains the |
3107 | target PC. */ | |
c5aa993b JM |
3108 | static char *table[15] = |
3109 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
3110 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
3111 | }; | |
c906108c | 3112 | int regno; |
faa95490 | 3113 | int offset = strlen (name) - 2; |
c906108c SS |
3114 | |
3115 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 3116 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 3117 | return get_frame_register_unsigned (frame, regno); |
c906108c | 3118 | } |
ed9a39eb | 3119 | |
faa95490 DJ |
3120 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
3121 | non-interworking calls to foo. We could decode the stubs | |
3122 | to find the target but it's easier to use the symbol table. */ | |
3123 | namelen = strlen (name); | |
3124 | if (name[0] == '_' && name[1] == '_' | |
3125 | && ((namelen > 2 + strlen ("_from_thumb") | |
3126 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", | |
3127 | strlen ("_from_thumb")) == 0) | |
3128 | || (namelen > 2 + strlen ("_from_arm") | |
3129 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", | |
3130 | strlen ("_from_arm")) == 0))) | |
3131 | { | |
3132 | char *target_name; | |
3133 | int target_len = namelen - 2; | |
3134 | struct minimal_symbol *minsym; | |
3135 | struct objfile *objfile; | |
3136 | struct obj_section *sec; | |
3137 | ||
3138 | if (name[namelen - 1] == 'b') | |
3139 | target_len -= strlen ("_from_thumb"); | |
3140 | else | |
3141 | target_len -= strlen ("_from_arm"); | |
3142 | ||
3143 | target_name = alloca (target_len + 1); | |
3144 | memcpy (target_name, name + 2, target_len); | |
3145 | target_name[target_len] = '\0'; | |
3146 | ||
3147 | sec = find_pc_section (pc); | |
3148 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
3149 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3150 | if (minsym != NULL) | |
3151 | return SYMBOL_VALUE_ADDRESS (minsym); | |
3152 | else | |
3153 | return 0; | |
3154 | } | |
3155 | ||
c5aa993b | 3156 | return 0; /* not a stub */ |
c906108c SS |
3157 | } |
3158 | ||
afd7eef0 RE |
3159 | static void |
3160 | set_arm_command (char *args, int from_tty) | |
3161 | { | |
edefbb7c AC |
3162 | printf_unfiltered (_("\ |
3163 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
3164 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
3165 | } | |
3166 | ||
3167 | static void | |
3168 | show_arm_command (char *args, int from_tty) | |
3169 | { | |
26304000 | 3170 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
3171 | } |
3172 | ||
28e97307 DJ |
3173 | static void |
3174 | arm_update_current_architecture (void) | |
fd50bc42 | 3175 | { |
28e97307 | 3176 | struct gdbarch_info info; |
fd50bc42 | 3177 | |
28e97307 | 3178 | /* If the current architecture is not ARM, we have nothing to do. */ |
1cf3db46 | 3179 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm) |
28e97307 | 3180 | return; |
fd50bc42 | 3181 | |
28e97307 DJ |
3182 | /* Update the architecture. */ |
3183 | gdbarch_info_init (&info); | |
fd50bc42 | 3184 | |
28e97307 DJ |
3185 | if (!gdbarch_update_p (info)) |
3186 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
3187 | } |
3188 | ||
3189 | static void | |
3190 | set_fp_model_sfunc (char *args, int from_tty, | |
3191 | struct cmd_list_element *c) | |
3192 | { | |
3193 | enum arm_float_model fp_model; | |
3194 | ||
3195 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
3196 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
3197 | { | |
3198 | arm_fp_model = fp_model; | |
3199 | break; | |
3200 | } | |
3201 | ||
3202 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 3203 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
3204 | current_fp_model); |
3205 | ||
28e97307 | 3206 | arm_update_current_architecture (); |
fd50bc42 RE |
3207 | } |
3208 | ||
3209 | static void | |
08546159 AC |
3210 | show_fp_model (struct ui_file *file, int from_tty, |
3211 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 3212 | { |
1cf3db46 | 3213 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
fd50bc42 | 3214 | |
28e97307 | 3215 | if (arm_fp_model == ARM_FLOAT_AUTO |
1cf3db46 | 3216 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
3217 | fprintf_filtered (file, _("\ |
3218 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
3219 | fp_model_strings[tdep->fp_model]); | |
3220 | else | |
3221 | fprintf_filtered (file, _("\ | |
3222 | The current ARM floating point model is \"%s\".\n"), | |
3223 | fp_model_strings[arm_fp_model]); | |
3224 | } | |
3225 | ||
3226 | static void | |
3227 | arm_set_abi (char *args, int from_tty, | |
3228 | struct cmd_list_element *c) | |
3229 | { | |
3230 | enum arm_abi_kind arm_abi; | |
3231 | ||
3232 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
3233 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
3234 | { | |
3235 | arm_abi_global = arm_abi; | |
3236 | break; | |
3237 | } | |
3238 | ||
3239 | if (arm_abi == ARM_ABI_LAST) | |
3240 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
3241 | arm_abi_string); | |
3242 | ||
3243 | arm_update_current_architecture (); | |
3244 | } | |
3245 | ||
3246 | static void | |
3247 | arm_show_abi (struct ui_file *file, int from_tty, | |
3248 | struct cmd_list_element *c, const char *value) | |
3249 | { | |
1cf3db46 | 3250 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
28e97307 DJ |
3251 | |
3252 | if (arm_abi_global == ARM_ABI_AUTO | |
1cf3db46 | 3253 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
3254 | fprintf_filtered (file, _("\ |
3255 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
3256 | arm_abi_strings[tdep->arm_abi]); | |
3257 | else | |
3258 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
3259 | arm_abi_string); | |
fd50bc42 RE |
3260 | } |
3261 | ||
0428b8f5 DJ |
3262 | static void |
3263 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
3264 | struct cmd_list_element *c, const char *value) | |
3265 | { | |
1cf3db46 | 3266 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
3267 | |
3268 | fprintf_filtered (file, _("\ | |
3269 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), | |
3270 | arm_fallback_mode_string); | |
3271 | } | |
3272 | ||
3273 | static void | |
3274 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
3275 | struct cmd_list_element *c, const char *value) | |
3276 | { | |
1cf3db46 | 3277 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
3278 | |
3279 | fprintf_filtered (file, _("\ | |
3280 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), | |
3281 | arm_force_mode_string); | |
3282 | } | |
3283 | ||
afd7eef0 RE |
3284 | /* If the user changes the register disassembly style used for info |
3285 | register and other commands, we have to also switch the style used | |
3286 | in opcodes for disassembly output. This function is run in the "set | |
3287 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
3288 | |
3289 | static void | |
afd7eef0 | 3290 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
3291 | struct cmd_list_element *c) |
3292 | { | |
afd7eef0 | 3293 | set_disassembly_style (); |
bc90b915 FN |
3294 | } |
3295 | \f | |
966fbf70 | 3296 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 3297 | static const char * |
d93859e2 | 3298 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 3299 | { |
58d6951d DJ |
3300 | const int num_regs = gdbarch_num_regs (gdbarch); |
3301 | ||
3302 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
3303 | && i >= num_regs && i < num_regs + 32) | |
3304 | { | |
3305 | static const char *const vfp_pseudo_names[] = { | |
3306 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
3307 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
3308 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
3309 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
3310 | }; | |
3311 | ||
3312 | return vfp_pseudo_names[i - num_regs]; | |
3313 | } | |
3314 | ||
3315 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
3316 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
3317 | { | |
3318 | static const char *const neon_pseudo_names[] = { | |
3319 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
3320 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
3321 | }; | |
3322 | ||
3323 | return neon_pseudo_names[i - num_regs - 32]; | |
3324 | } | |
3325 | ||
ff6f572f DJ |
3326 | if (i >= ARRAY_SIZE (arm_register_names)) |
3327 | /* These registers are only supported on targets which supply | |
3328 | an XML description. */ | |
3329 | return ""; | |
3330 | ||
966fbf70 RE |
3331 | return arm_register_names[i]; |
3332 | } | |
3333 | ||
bc90b915 | 3334 | static void |
afd7eef0 | 3335 | set_disassembly_style (void) |
bc90b915 | 3336 | { |
123dc839 | 3337 | int current; |
bc90b915 | 3338 | |
123dc839 DJ |
3339 | /* Find the style that the user wants. */ |
3340 | for (current = 0; current < num_disassembly_options; current++) | |
3341 | if (disassembly_style == valid_disassembly_styles[current]) | |
3342 | break; | |
3343 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 3344 | |
94c30b78 | 3345 | /* Synchronize the disassembler. */ |
bc90b915 FN |
3346 | set_arm_regname_option (current); |
3347 | } | |
3348 | ||
082fc60d RE |
3349 | /* Test whether the coff symbol specific value corresponds to a Thumb |
3350 | function. */ | |
3351 | ||
3352 | static int | |
3353 | coff_sym_is_thumb (int val) | |
3354 | { | |
3355 | return (val == C_THUMBEXT || | |
3356 | val == C_THUMBSTAT || | |
3357 | val == C_THUMBEXTFUNC || | |
3358 | val == C_THUMBSTATFUNC || | |
3359 | val == C_THUMBLABEL); | |
3360 | } | |
3361 | ||
3362 | /* arm_coff_make_msymbol_special() | |
3363 | arm_elf_make_msymbol_special() | |
3364 | ||
3365 | These functions test whether the COFF or ELF symbol corresponds to | |
3366 | an address in thumb code, and set a "special" bit in a minimal | |
3367 | symbol to indicate that it does. */ | |
3368 | ||
34e8f22d | 3369 | static void |
082fc60d RE |
3370 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
3371 | { | |
3372 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
3373 | STT_ARM_TFUNC). */ | |
3374 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
3375 | == STT_LOPROC) | |
3376 | MSYMBOL_SET_SPECIAL (msym); | |
3377 | } | |
3378 | ||
34e8f22d | 3379 | static void |
082fc60d RE |
3380 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
3381 | { | |
3382 | if (coff_sym_is_thumb (val)) | |
3383 | MSYMBOL_SET_SPECIAL (msym); | |
3384 | } | |
3385 | ||
60c5725c DJ |
3386 | static void |
3387 | arm_objfile_data_cleanup (struct objfile *objfile, void *arg) | |
3388 | { | |
3389 | struct arm_per_objfile *data = arg; | |
3390 | unsigned int i; | |
3391 | ||
3392 | for (i = 0; i < objfile->obfd->section_count; i++) | |
3393 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); | |
3394 | } | |
3395 | ||
3396 | static void | |
3397 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
3398 | asymbol *sym) | |
3399 | { | |
3400 | const char *name = bfd_asymbol_name (sym); | |
3401 | struct arm_per_objfile *data; | |
3402 | VEC(arm_mapping_symbol_s) **map_p; | |
3403 | struct arm_mapping_symbol new_map_sym; | |
3404 | ||
3405 | gdb_assert (name[0] == '$'); | |
3406 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
3407 | return; | |
3408 | ||
3409 | data = objfile_data (objfile, arm_objfile_data_key); | |
3410 | if (data == NULL) | |
3411 | { | |
3412 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, | |
3413 | struct arm_per_objfile); | |
3414 | set_objfile_data (objfile, arm_objfile_data_key, data); | |
3415 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
3416 | objfile->obfd->section_count, | |
3417 | VEC(arm_mapping_symbol_s) *); | |
3418 | } | |
3419 | map_p = &data->section_maps[bfd_get_section (sym)->index]; | |
3420 | ||
3421 | new_map_sym.value = sym->value; | |
3422 | new_map_sym.type = name[1]; | |
3423 | ||
3424 | /* Assume that most mapping symbols appear in order of increasing | |
3425 | value. If they were randomly distributed, it would be faster to | |
3426 | always push here and then sort at first use. */ | |
3427 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) | |
3428 | { | |
3429 | struct arm_mapping_symbol *prev_map_sym; | |
3430 | ||
3431 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); | |
3432 | if (prev_map_sym->value >= sym->value) | |
3433 | { | |
3434 | unsigned int idx; | |
3435 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, | |
3436 | arm_compare_mapping_symbols); | |
3437 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); | |
3438 | return; | |
3439 | } | |
3440 | } | |
3441 | ||
3442 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); | |
3443 | } | |
3444 | ||
756fe439 | 3445 | static void |
61a1198a | 3446 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 3447 | { |
61a1198a | 3448 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
3449 | |
3450 | /* If necessary, set the T bit. */ | |
3451 | if (arm_apcs_32) | |
3452 | { | |
61a1198a UW |
3453 | ULONGEST val; |
3454 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); | |
756fe439 | 3455 | if (arm_pc_is_thumb (pc)) |
b39cc962 | 3456 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
756fe439 | 3457 | else |
61a1198a | 3458 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
b39cc962 | 3459 | val & ~(ULONGEST) CPSR_T); |
756fe439 DJ |
3460 | } |
3461 | } | |
123dc839 | 3462 | |
58d6951d DJ |
3463 | /* Read the contents of a NEON quad register, by reading from two |
3464 | double registers. This is used to implement the quad pseudo | |
3465 | registers, and for argument passing in case the quad registers are | |
3466 | missing; vectors are passed in quad registers when using the VFP | |
3467 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
3468 | the quad register, in [0, 15]. */ | |
3469 | ||
3470 | static void | |
3471 | arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
3472 | int regnum, gdb_byte *buf) | |
3473 | { | |
3474 | char name_buf[4]; | |
3475 | gdb_byte reg_buf[8]; | |
3476 | int offset, double_regnum; | |
3477 | ||
3478 | sprintf (name_buf, "d%d", regnum << 1); | |
3479 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
3480 | strlen (name_buf)); | |
3481 | ||
3482 | /* d0 is always the least significant half of q0. */ | |
3483 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
3484 | offset = 8; | |
3485 | else | |
3486 | offset = 0; | |
3487 | ||
3488 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
3489 | memcpy (buf + offset, reg_buf, 8); | |
3490 | ||
3491 | offset = 8 - offset; | |
3492 | regcache_raw_read (regcache, double_regnum + 1, reg_buf); | |
3493 | memcpy (buf + offset, reg_buf, 8); | |
3494 | } | |
3495 | ||
3496 | static void | |
3497 | arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
3498 | int regnum, gdb_byte *buf) | |
3499 | { | |
3500 | const int num_regs = gdbarch_num_regs (gdbarch); | |
3501 | char name_buf[4]; | |
3502 | gdb_byte reg_buf[8]; | |
3503 | int offset, double_regnum; | |
3504 | ||
3505 | gdb_assert (regnum >= num_regs); | |
3506 | regnum -= num_regs; | |
3507 | ||
3508 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
3509 | /* Quad-precision register. */ | |
3510 | arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); | |
3511 | else | |
3512 | { | |
3513 | /* Single-precision register. */ | |
3514 | gdb_assert (regnum < 32); | |
3515 | ||
3516 | /* s0 is always the least significant half of d0. */ | |
3517 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
3518 | offset = (regnum & 1) ? 0 : 4; | |
3519 | else | |
3520 | offset = (regnum & 1) ? 4 : 0; | |
3521 | ||
3522 | sprintf (name_buf, "d%d", regnum >> 1); | |
3523 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
3524 | strlen (name_buf)); | |
3525 | ||
3526 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
3527 | memcpy (buf, reg_buf + offset, 4); | |
3528 | } | |
3529 | } | |
3530 | ||
3531 | /* Store the contents of BUF to a NEON quad register, by writing to | |
3532 | two double registers. This is used to implement the quad pseudo | |
3533 | registers, and for argument passing in case the quad registers are | |
3534 | missing; vectors are passed in quad registers when using the VFP | |
3535 | ABI, even if a NEON unit is not present. REGNUM is the index | |
3536 | of the quad register, in [0, 15]. */ | |
3537 | ||
3538 | static void | |
3539 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
3540 | int regnum, const gdb_byte *buf) | |
3541 | { | |
3542 | char name_buf[4]; | |
3543 | gdb_byte reg_buf[8]; | |
3544 | int offset, double_regnum; | |
3545 | ||
3546 | sprintf (name_buf, "d%d", regnum << 1); | |
3547 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
3548 | strlen (name_buf)); | |
3549 | ||
3550 | /* d0 is always the least significant half of q0. */ | |
3551 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
3552 | offset = 8; | |
3553 | else | |
3554 | offset = 0; | |
3555 | ||
3556 | regcache_raw_write (regcache, double_regnum, buf + offset); | |
3557 | offset = 8 - offset; | |
3558 | regcache_raw_write (regcache, double_regnum + 1, buf + offset); | |
3559 | } | |
3560 | ||
3561 | static void | |
3562 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
3563 | int regnum, const gdb_byte *buf) | |
3564 | { | |
3565 | const int num_regs = gdbarch_num_regs (gdbarch); | |
3566 | char name_buf[4]; | |
3567 | gdb_byte reg_buf[8]; | |
3568 | int offset, double_regnum; | |
3569 | ||
3570 | gdb_assert (regnum >= num_regs); | |
3571 | regnum -= num_regs; | |
3572 | ||
3573 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
3574 | /* Quad-precision register. */ | |
3575 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
3576 | else | |
3577 | { | |
3578 | /* Single-precision register. */ | |
3579 | gdb_assert (regnum < 32); | |
3580 | ||
3581 | /* s0 is always the least significant half of d0. */ | |
3582 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
3583 | offset = (regnum & 1) ? 0 : 4; | |
3584 | else | |
3585 | offset = (regnum & 1) ? 4 : 0; | |
3586 | ||
3587 | sprintf (name_buf, "d%d", regnum >> 1); | |
3588 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
3589 | strlen (name_buf)); | |
3590 | ||
3591 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
3592 | memcpy (reg_buf + offset, buf, 4); | |
3593 | regcache_raw_write (regcache, double_regnum, reg_buf); | |
3594 | } | |
3595 | } | |
3596 | ||
123dc839 DJ |
3597 | static struct value * |
3598 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
3599 | { | |
3600 | const int *reg_p = baton; | |
3601 | return value_of_register (*reg_p, frame); | |
3602 | } | |
97e03143 | 3603 | \f |
70f80edf JT |
3604 | static enum gdb_osabi |
3605 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 3606 | { |
2af48f68 | 3607 | unsigned int elfosabi; |
70f80edf | 3608 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 3609 | |
70f80edf | 3610 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 3611 | |
28e97307 DJ |
3612 | if (elfosabi == ELFOSABI_ARM) |
3613 | /* GNU tools use this value. Check note sections in this case, | |
3614 | as well. */ | |
3615 | bfd_map_over_sections (abfd, | |
3616 | generic_elf_osabi_sniff_abi_tag_sections, | |
3617 | &osabi); | |
97e03143 | 3618 | |
28e97307 | 3619 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 3620 | return osabi; |
97e03143 RE |
3621 | } |
3622 | ||
70f80edf | 3623 | \f |
da3c6d4a MS |
3624 | /* Initialize the current architecture based on INFO. If possible, |
3625 | re-use an architecture from ARCHES, which is a list of | |
3626 | architectures already created during this debugging session. | |
97e03143 | 3627 | |
da3c6d4a MS |
3628 | Called e.g. at program startup, when reading a core file, and when |
3629 | reading a binary file. */ | |
97e03143 | 3630 | |
39bbf761 RE |
3631 | static struct gdbarch * |
3632 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3633 | { | |
97e03143 | 3634 | struct gdbarch_tdep *tdep; |
39bbf761 | 3635 | struct gdbarch *gdbarch; |
28e97307 DJ |
3636 | struct gdbarch_list *best_arch; |
3637 | enum arm_abi_kind arm_abi = arm_abi_global; | |
3638 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
3639 | struct tdesc_arch_data *tdesc_data = NULL; |
3640 | int i; | |
58d6951d DJ |
3641 | int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; |
3642 | int have_neon = 0; | |
ff6f572f | 3643 | int have_fpa_registers = 1; |
123dc839 DJ |
3644 | |
3645 | /* Check any target description for validity. */ | |
3646 | if (tdesc_has_registers (info.target_desc)) | |
3647 | { | |
3648 | /* For most registers we require GDB's default names; but also allow | |
3649 | the numeric names for sp / lr / pc, as a convenience. */ | |
3650 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
3651 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
3652 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
3653 | ||
3654 | const struct tdesc_feature *feature; | |
58d6951d | 3655 | int valid_p; |
123dc839 DJ |
3656 | |
3657 | feature = tdesc_find_feature (info.target_desc, | |
3658 | "org.gnu.gdb.arm.core"); | |
3659 | if (feature == NULL) | |
3660 | return NULL; | |
3661 | ||
3662 | tdesc_data = tdesc_data_alloc (); | |
3663 | ||
3664 | valid_p = 1; | |
3665 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
3666 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
3667 | arm_register_names[i]); | |
3668 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3669 | ARM_SP_REGNUM, | |
3670 | arm_sp_names); | |
3671 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3672 | ARM_LR_REGNUM, | |
3673 | arm_lr_names); | |
3674 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3675 | ARM_PC_REGNUM, | |
3676 | arm_pc_names); | |
3677 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3678 | ARM_PS_REGNUM, "cpsr"); | |
3679 | ||
3680 | if (!valid_p) | |
3681 | { | |
3682 | tdesc_data_cleanup (tdesc_data); | |
3683 | return NULL; | |
3684 | } | |
3685 | ||
3686 | feature = tdesc_find_feature (info.target_desc, | |
3687 | "org.gnu.gdb.arm.fpa"); | |
3688 | if (feature != NULL) | |
3689 | { | |
3690 | valid_p = 1; | |
3691 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
3692 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
3693 | arm_register_names[i]); | |
3694 | if (!valid_p) | |
3695 | { | |
3696 | tdesc_data_cleanup (tdesc_data); | |
3697 | return NULL; | |
3698 | } | |
3699 | } | |
ff6f572f DJ |
3700 | else |
3701 | have_fpa_registers = 0; | |
3702 | ||
3703 | feature = tdesc_find_feature (info.target_desc, | |
3704 | "org.gnu.gdb.xscale.iwmmxt"); | |
3705 | if (feature != NULL) | |
3706 | { | |
3707 | static const char *const iwmmxt_names[] = { | |
3708 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
3709 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
3710 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
3711 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
3712 | }; | |
3713 | ||
3714 | valid_p = 1; | |
3715 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
3716 | valid_p | |
3717 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
3718 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3719 | ||
3720 | /* Check for the control registers, but do not fail if they | |
3721 | are missing. */ | |
3722 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
3723 | tdesc_numbered_register (feature, tdesc_data, i, | |
3724 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3725 | ||
3726 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
3727 | valid_p | |
3728 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
3729 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3730 | ||
3731 | if (!valid_p) | |
3732 | { | |
3733 | tdesc_data_cleanup (tdesc_data); | |
3734 | return NULL; | |
3735 | } | |
3736 | } | |
58d6951d DJ |
3737 | |
3738 | /* If we have a VFP unit, check whether the single precision registers | |
3739 | are present. If not, then we will synthesize them as pseudo | |
3740 | registers. */ | |
3741 | feature = tdesc_find_feature (info.target_desc, | |
3742 | "org.gnu.gdb.arm.vfp"); | |
3743 | if (feature != NULL) | |
3744 | { | |
3745 | static const char *const vfp_double_names[] = { | |
3746 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
3747 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
3748 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
3749 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
3750 | }; | |
3751 | ||
3752 | /* Require the double precision registers. There must be either | |
3753 | 16 or 32. */ | |
3754 | valid_p = 1; | |
3755 | for (i = 0; i < 32; i++) | |
3756 | { | |
3757 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3758 | ARM_D0_REGNUM + i, | |
3759 | vfp_double_names[i]); | |
3760 | if (!valid_p) | |
3761 | break; | |
3762 | } | |
3763 | ||
3764 | if (!valid_p && i != 16) | |
3765 | { | |
3766 | tdesc_data_cleanup (tdesc_data); | |
3767 | return NULL; | |
3768 | } | |
3769 | ||
3770 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
3771 | have_vfp_pseudos = 1; | |
3772 | ||
3773 | have_vfp_registers = 1; | |
3774 | ||
3775 | /* If we have VFP, also check for NEON. The architecture allows | |
3776 | NEON without VFP (integer vector operations only), but GDB | |
3777 | does not support that. */ | |
3778 | feature = tdesc_find_feature (info.target_desc, | |
3779 | "org.gnu.gdb.arm.neon"); | |
3780 | if (feature != NULL) | |
3781 | { | |
3782 | /* NEON requires 32 double-precision registers. */ | |
3783 | if (i != 32) | |
3784 | { | |
3785 | tdesc_data_cleanup (tdesc_data); | |
3786 | return NULL; | |
3787 | } | |
3788 | ||
3789 | /* If there are quad registers defined by the stub, use | |
3790 | their type; otherwise (normally) provide them with | |
3791 | the default type. */ | |
3792 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
3793 | have_neon_pseudos = 1; | |
3794 | ||
3795 | have_neon = 1; | |
3796 | } | |
3797 | } | |
123dc839 | 3798 | } |
39bbf761 | 3799 | |
28e97307 DJ |
3800 | /* If we have an object to base this architecture on, try to determine |
3801 | its ABI. */ | |
39bbf761 | 3802 | |
28e97307 | 3803 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 3804 | { |
6b26d61a | 3805 | int ei_osabi, e_flags; |
28e97307 | 3806 | |
4be87837 | 3807 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 3808 | { |
4be87837 DJ |
3809 | case bfd_target_aout_flavour: |
3810 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 3811 | arm_abi = ARM_ABI_APCS; |
4be87837 | 3812 | break; |
97e03143 | 3813 | |
4be87837 DJ |
3814 | case bfd_target_coff_flavour: |
3815 | /* Assume it's an old APCS-style ABI. */ | |
3816 | /* XXX WinCE? */ | |
28e97307 DJ |
3817 | arm_abi = ARM_ABI_APCS; |
3818 | break; | |
3819 | ||
3820 | case bfd_target_elf_flavour: | |
3821 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
3822 | e_flags = elf_elfheader (info.abfd)->e_flags; |
3823 | ||
28e97307 DJ |
3824 | if (ei_osabi == ELFOSABI_ARM) |
3825 | { | |
3826 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
3827 | objects. There's nowhere to tag an EABI version |
3828 | anyway, so assume APCS. */ | |
28e97307 DJ |
3829 | arm_abi = ARM_ABI_APCS; |
3830 | } | |
3831 | else if (ei_osabi == ELFOSABI_NONE) | |
3832 | { | |
6b26d61a | 3833 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
3834 | |
3835 | switch (eabi_ver) | |
3836 | { | |
3837 | case EF_ARM_EABI_UNKNOWN: | |
3838 | /* Assume GNU tools. */ | |
3839 | arm_abi = ARM_ABI_APCS; | |
3840 | break; | |
3841 | ||
3842 | case EF_ARM_EABI_VER4: | |
625b5003 | 3843 | case EF_ARM_EABI_VER5: |
28e97307 | 3844 | arm_abi = ARM_ABI_AAPCS; |
90445bd3 DJ |
3845 | /* EABI binaries default to VFP float ordering. |
3846 | They may also contain build attributes that can | |
3847 | be used to identify if the VFP argument-passing | |
3848 | ABI is in use. */ | |
2af48f68 | 3849 | if (fp_model == ARM_FLOAT_AUTO) |
90445bd3 DJ |
3850 | { |
3851 | #ifdef HAVE_ELF | |
3852 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
3853 | OBJ_ATTR_PROC, | |
3854 | Tag_ABI_VFP_args)) | |
3855 | { | |
3856 | case 0: | |
3857 | /* "The user intended FP parameter/result | |
3858 | passing to conform to AAPCS, base | |
3859 | variant". */ | |
3860 | fp_model = ARM_FLOAT_SOFT_VFP; | |
3861 | break; | |
3862 | case 1: | |
3863 | /* "The user intended FP parameter/result | |
3864 | passing to conform to AAPCS, VFP | |
3865 | variant". */ | |
3866 | fp_model = ARM_FLOAT_VFP; | |
3867 | break; | |
3868 | case 2: | |
3869 | /* "The user intended FP parameter/result | |
3870 | passing to conform to tool chain-specific | |
3871 | conventions" - we don't know any such | |
3872 | conventions, so leave it as "auto". */ | |
3873 | break; | |
3874 | default: | |
3875 | /* Attribute value not mentioned in the | |
3876 | October 2008 ABI, so leave it as | |
3877 | "auto". */ | |
3878 | break; | |
3879 | } | |
3880 | #else | |
3881 | fp_model = ARM_FLOAT_SOFT_VFP; | |
3882 | #endif | |
3883 | } | |
28e97307 DJ |
3884 | break; |
3885 | ||
3886 | default: | |
6b26d61a | 3887 | /* Leave it as "auto". */ |
28e97307 | 3888 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
3889 | break; |
3890 | } | |
3891 | } | |
3892 | ||
3893 | if (fp_model == ARM_FLOAT_AUTO) | |
3894 | { | |
3895 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
3896 | ||
3897 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
3898 | { | |
3899 | case 0: | |
3900 | /* Leave it as "auto". Strictly speaking this case | |
3901 | means FPA, but almost nobody uses that now, and | |
3902 | many toolchains fail to set the appropriate bits | |
3903 | for the floating-point model they use. */ | |
3904 | break; | |
3905 | case EF_ARM_SOFT_FLOAT: | |
3906 | fp_model = ARM_FLOAT_SOFT_FPA; | |
3907 | break; | |
3908 | case EF_ARM_VFP_FLOAT: | |
3909 | fp_model = ARM_FLOAT_VFP; | |
3910 | break; | |
3911 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
3912 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
3913 | break; |
3914 | } | |
3915 | } | |
9d4fde75 SS |
3916 | |
3917 | if (e_flags & EF_ARM_BE8) | |
3918 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
3919 | ||
4be87837 | 3920 | break; |
97e03143 | 3921 | |
4be87837 | 3922 | default: |
28e97307 | 3923 | /* Leave it as "auto". */ |
50ceaba5 | 3924 | break; |
97e03143 RE |
3925 | } |
3926 | } | |
3927 | ||
28e97307 DJ |
3928 | /* If there is already a candidate, use it. */ |
3929 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3930 | best_arch != NULL; | |
3931 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3932 | { | |
b8926edc DJ |
3933 | if (arm_abi != ARM_ABI_AUTO |
3934 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
3935 | continue; |
3936 | ||
b8926edc DJ |
3937 | if (fp_model != ARM_FLOAT_AUTO |
3938 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
3939 | continue; |
3940 | ||
58d6951d DJ |
3941 | /* There are various other properties in tdep that we do not |
3942 | need to check here: those derived from a target description, | |
3943 | since gdbarches with a different target description are | |
3944 | automatically disqualified. */ | |
3945 | ||
28e97307 DJ |
3946 | /* Found a match. */ |
3947 | break; | |
3948 | } | |
97e03143 | 3949 | |
28e97307 | 3950 | if (best_arch != NULL) |
123dc839 DJ |
3951 | { |
3952 | if (tdesc_data != NULL) | |
3953 | tdesc_data_cleanup (tdesc_data); | |
3954 | return best_arch->gdbarch; | |
3955 | } | |
28e97307 DJ |
3956 | |
3957 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
3958 | gdbarch = gdbarch_alloc (&info, tdep); |
3959 | ||
28e97307 DJ |
3960 | /* Record additional information about the architecture we are defining. |
3961 | These are gdbarch discriminators, like the OSABI. */ | |
3962 | tdep->arm_abi = arm_abi; | |
3963 | tdep->fp_model = fp_model; | |
ff6f572f | 3964 | tdep->have_fpa_registers = have_fpa_registers; |
58d6951d DJ |
3965 | tdep->have_vfp_registers = have_vfp_registers; |
3966 | tdep->have_vfp_pseudos = have_vfp_pseudos; | |
3967 | tdep->have_neon_pseudos = have_neon_pseudos; | |
3968 | tdep->have_neon = have_neon; | |
08216dd7 RE |
3969 | |
3970 | /* Breakpoints. */ | |
9d4fde75 | 3971 | switch (info.byte_order_for_code) |
67255d04 RE |
3972 | { |
3973 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
3974 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
3975 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
3976 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
3977 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
3978 | ||
67255d04 RE |
3979 | break; |
3980 | ||
3981 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
3982 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
3983 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
3984 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
3985 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
3986 | ||
67255d04 RE |
3987 | break; |
3988 | ||
3989 | default: | |
3990 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 3991 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
3992 | } |
3993 | ||
d7b486e7 RE |
3994 | /* On ARM targets char defaults to unsigned. */ |
3995 | set_gdbarch_char_signed (gdbarch, 0); | |
3996 | ||
9df628e0 | 3997 | /* This should be low enough for everything. */ |
97e03143 | 3998 | tdep->lowest_pc = 0x20; |
94c30b78 | 3999 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 4000 | |
7c00367c MK |
4001 | /* The default, for both APCS and AAPCS, is to return small |
4002 | structures in registers. */ | |
4003 | tdep->struct_return = reg_struct_return; | |
4004 | ||
2dd604e7 | 4005 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 4006 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 4007 | |
756fe439 DJ |
4008 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
4009 | ||
148754e5 | 4010 | /* Frame handling. */ |
a262aec2 | 4011 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
4012 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
4013 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
4014 | ||
eb5492fa | 4015 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 4016 | |
34e8f22d RE |
4017 | /* Address manipulation. */ |
4018 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
4019 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
4020 | ||
34e8f22d RE |
4021 | /* Advance PC across function entry code. */ |
4022 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
4023 | ||
190dce09 UW |
4024 | /* Skip trampolines. */ |
4025 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
4026 | ||
34e8f22d RE |
4027 | /* The stack grows downward. */ |
4028 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4029 | ||
4030 | /* Breakpoint manipulation. */ | |
4031 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
4032 | |
4033 | /* Information about registers, etc. */ | |
0ba6dca9 | 4034 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
4035 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
4036 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 4037 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 4038 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 4039 | |
ff6f572f DJ |
4040 | /* This "info float" is FPA-specific. Use the generic version if we |
4041 | do not have FPA. */ | |
4042 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
4043 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
4044 | ||
26216b98 | 4045 | /* Internal <-> external register number maps. */ |
ff6f572f | 4046 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
4047 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
4048 | ||
34e8f22d RE |
4049 | set_gdbarch_register_name (gdbarch, arm_register_name); |
4050 | ||
4051 | /* Returning results. */ | |
2af48f68 | 4052 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 4053 | |
03d48a7d RE |
4054 | /* Disassembly. */ |
4055 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
4056 | ||
34e8f22d RE |
4057 | /* Minsymbol frobbing. */ |
4058 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
4059 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
4060 | arm_coff_make_msymbol_special); | |
60c5725c | 4061 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 4062 | |
0d5de010 DJ |
4063 | /* Virtual tables. */ |
4064 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
4065 | ||
97e03143 | 4066 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 4067 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 4068 | |
b39cc962 DJ |
4069 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
4070 | ||
eb5492fa | 4071 | /* Add some default predicates. */ |
a262aec2 DJ |
4072 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
4073 | dwarf2_append_unwinders (gdbarch); | |
4074 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); | |
eb5492fa | 4075 | |
97e03143 RE |
4076 | /* Now we have tuned the configuration, set a few final things, |
4077 | based on what the OS ABI has told us. */ | |
4078 | ||
b8926edc DJ |
4079 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
4080 | binaries are always marked. */ | |
4081 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
4082 | tdep->arm_abi = ARM_ABI_APCS; | |
4083 | ||
4084 | /* We used to default to FPA for generic ARM, but almost nobody | |
4085 | uses that now, and we now provide a way for the user to force | |
4086 | the model. So default to the most useful variant. */ | |
4087 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
4088 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
4089 | ||
9df628e0 RE |
4090 | if (tdep->jb_pc >= 0) |
4091 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
4092 | ||
08216dd7 | 4093 | /* Floating point sizes and format. */ |
8da61cc4 | 4094 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 4095 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 4096 | { |
8da61cc4 DJ |
4097 | set_gdbarch_double_format |
4098 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
4099 | set_gdbarch_long_double_format | |
4100 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
4101 | } | |
4102 | else | |
4103 | { | |
4104 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
4105 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
4106 | } |
4107 | ||
58d6951d DJ |
4108 | if (have_vfp_pseudos) |
4109 | { | |
4110 | /* NOTE: These are the only pseudo registers used by | |
4111 | the ARM target at the moment. If more are added, a | |
4112 | little more care in numbering will be needed. */ | |
4113 | ||
4114 | int num_pseudos = 32; | |
4115 | if (have_neon_pseudos) | |
4116 | num_pseudos += 16; | |
4117 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
4118 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
4119 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
4120 | } | |
4121 | ||
123dc839 | 4122 | if (tdesc_data) |
58d6951d DJ |
4123 | { |
4124 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
4125 | ||
4126 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); | |
4127 | ||
4128 | /* Override tdesc_register_type to adjust the types of VFP | |
4129 | registers for NEON. */ | |
4130 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
4131 | } | |
123dc839 DJ |
4132 | |
4133 | /* Add standard register aliases. We add aliases even for those | |
4134 | nanes which are used by the current architecture - it's simpler, | |
4135 | and does no harm, since nothing ever lists user registers. */ | |
4136 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
4137 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
4138 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
4139 | ||
39bbf761 RE |
4140 | return gdbarch; |
4141 | } | |
4142 | ||
97e03143 | 4143 | static void |
2af46ca0 | 4144 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 4145 | { |
2af46ca0 | 4146 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
4147 | |
4148 | if (tdep == NULL) | |
4149 | return; | |
4150 | ||
edefbb7c | 4151 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
4152 | (unsigned long) tdep->lowest_pc); |
4153 | } | |
4154 | ||
a78f21af AC |
4155 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
4156 | ||
c906108c | 4157 | void |
ed9a39eb | 4158 | _initialize_arm_tdep (void) |
c906108c | 4159 | { |
bc90b915 FN |
4160 | struct ui_file *stb; |
4161 | long length; | |
26304000 | 4162 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
4163 | const char *setname; |
4164 | const char *setdesc; | |
4bd7b427 | 4165 | const char *const *regnames; |
bc90b915 FN |
4166 | int numregs, i, j; |
4167 | static char *helptext; | |
edefbb7c AC |
4168 | char regdesc[1024], *rdptr = regdesc; |
4169 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 4170 | |
42cf1509 | 4171 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 4172 | |
60c5725c DJ |
4173 | arm_objfile_data_key |
4174 | = register_objfile_data_with_cleanup (arm_objfile_data_cleanup); | |
4175 | ||
70f80edf JT |
4176 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
4177 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
4178 | bfd_target_elf_flavour, | |
4179 | arm_elf_osabi_sniffer); | |
4180 | ||
94c30b78 | 4181 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
4182 | num_disassembly_options = get_arm_regname_num_options (); |
4183 | ||
4184 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
4185 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 4186 | _("Various ARM-specific commands."), |
afd7eef0 RE |
4187 | &setarmcmdlist, "set arm ", 0, &setlist); |
4188 | ||
4189 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 4190 | _("Various ARM-specific commands."), |
afd7eef0 | 4191 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 4192 | |
94c30b78 | 4193 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 4194 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 4195 | |
eefe576e AC |
4196 | /* Initialize the array that will be passed to |
4197 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
4198 | valid_disassembly_styles |
4199 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
4200 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
4201 | { |
4202 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 4203 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
4204 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
4205 | rdptr += length; | |
4206 | rest -= length; | |
123dc839 DJ |
4207 | /* When we find the default names, tell the disassembler to use |
4208 | them. */ | |
bc90b915 FN |
4209 | if (!strcmp (setname, "std")) |
4210 | { | |
afd7eef0 | 4211 | disassembly_style = setname; |
bc90b915 FN |
4212 | set_arm_regname_option (i); |
4213 | } | |
4214 | } | |
94c30b78 | 4215 | /* Mark the end of valid options. */ |
afd7eef0 | 4216 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 4217 | |
edefbb7c AC |
4218 | /* Create the help text. */ |
4219 | stb = mem_fileopen (); | |
4220 | fprintf_unfiltered (stb, "%s%s%s", | |
4221 | _("The valid values are:\n"), | |
4222 | regdesc, | |
4223 | _("The default is \"std\".")); | |
bc90b915 FN |
4224 | helptext = ui_file_xstrdup (stb, &length); |
4225 | ui_file_delete (stb); | |
ed9a39eb | 4226 | |
edefbb7c AC |
4227 | add_setshow_enum_cmd("disassembler", no_class, |
4228 | valid_disassembly_styles, &disassembly_style, | |
4229 | _("Set the disassembly style."), | |
4230 | _("Show the disassembly style."), | |
4231 | helptext, | |
2c5b56ce | 4232 | set_disassembly_style_sfunc, |
7915a72c | 4233 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 4234 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
4235 | |
4236 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
4237 | _("Set usage of ARM 32-bit mode."), | |
4238 | _("Show usage of ARM 32-bit mode."), | |
4239 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 4240 | NULL, |
7915a72c | 4241 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 4242 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 4243 | |
fd50bc42 | 4244 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
4245 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
4246 | _("Set the floating point type."), | |
4247 | _("Show the floating point type."), | |
4248 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
4249 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
4250 | fpa - FPA co-processor (GCC compiled).\n\ | |
4251 | softvfp - Software FP with pure-endian doubles.\n\ | |
4252 | vfp - VFP co-processor."), | |
edefbb7c | 4253 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 4254 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 4255 | |
28e97307 DJ |
4256 | /* Add a command to allow the user to force the ABI. */ |
4257 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
4258 | _("Set the ABI."), | |
4259 | _("Show the ABI."), | |
4260 | NULL, arm_set_abi, arm_show_abi, | |
4261 | &setarmcmdlist, &showarmcmdlist); | |
4262 | ||
0428b8f5 DJ |
4263 | /* Add two commands to allow the user to force the assumed |
4264 | execution mode. */ | |
4265 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
4266 | arm_mode_strings, &arm_fallback_mode_string, | |
4267 | _("Set the mode assumed when symbols are unavailable."), | |
4268 | _("Show the mode assumed when symbols are unavailable."), | |
4269 | NULL, NULL, arm_show_fallback_mode, | |
4270 | &setarmcmdlist, &showarmcmdlist); | |
4271 | add_setshow_enum_cmd ("force-mode", class_support, | |
4272 | arm_mode_strings, &arm_force_mode_string, | |
4273 | _("Set the mode assumed even when symbols are available."), | |
4274 | _("Show the mode assumed even when symbols are available."), | |
4275 | NULL, NULL, arm_show_force_mode, | |
4276 | &setarmcmdlist, &showarmcmdlist); | |
4277 | ||
6529d2dd | 4278 | /* Debugging flag. */ |
edefbb7c AC |
4279 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
4280 | _("Set ARM debugging."), | |
4281 | _("Show ARM debugging."), | |
4282 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 4283 | NULL, |
7915a72c | 4284 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 4285 | &setdebuglist, &showdebuglist); |
c906108c | 4286 | } |