Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
4c38e0a4 | 4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
9b254dd1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
123dc839 DJ |
43 | #include "target-descriptions.h" |
44 | #include "user-regs.h" | |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 | 53 | #include "gdb_assert.h" |
60c5725c | 54 | #include "vec.h" |
26216b98 | 55 | |
6529d2dd AC |
56 | static int arm_debug; |
57 | ||
082fc60d RE |
58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
59 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 60 | is used for this purpose. |
082fc60d RE |
61 | |
62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
64 | |
65 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
b887350f | 66 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
67 | |
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 69 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 70 | |
60c5725c DJ |
71 | /* Per-objfile data used for mapping symbols. */ |
72 | static const struct objfile_data *arm_objfile_data_key; | |
73 | ||
74 | struct arm_mapping_symbol | |
75 | { | |
76 | bfd_vma value; | |
77 | char type; | |
78 | }; | |
79 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; | |
80 | DEF_VEC_O(arm_mapping_symbol_s); | |
81 | ||
82 | struct arm_per_objfile | |
83 | { | |
84 | VEC(arm_mapping_symbol_s) **section_maps; | |
85 | }; | |
86 | ||
afd7eef0 RE |
87 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
88 | static struct cmd_list_element *setarmcmdlist = NULL; | |
89 | static struct cmd_list_element *showarmcmdlist = NULL; | |
90 | ||
fd50bc42 RE |
91 | /* The type of floating-point to use. Keep this in sync with enum |
92 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
93 | static const char *fp_model_strings[] = | |
94 | { | |
95 | "auto", | |
96 | "softfpa", | |
97 | "fpa", | |
98 | "softvfp", | |
28e97307 DJ |
99 | "vfp", |
100 | NULL | |
fd50bc42 RE |
101 | }; |
102 | ||
103 | /* A variable that can be configured by the user. */ | |
104 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
105 | static const char *current_fp_model = "auto"; | |
106 | ||
28e97307 DJ |
107 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
108 | static const char *arm_abi_strings[] = | |
109 | { | |
110 | "auto", | |
111 | "APCS", | |
112 | "AAPCS", | |
113 | NULL | |
114 | }; | |
115 | ||
116 | /* A variable that can be configured by the user. */ | |
117 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
118 | static const char *arm_abi_string = "auto"; | |
119 | ||
0428b8f5 DJ |
120 | /* The execution mode to assume. */ |
121 | static const char *arm_mode_strings[] = | |
122 | { | |
123 | "auto", | |
124 | "arm", | |
125 | "thumb" | |
126 | }; | |
127 | ||
128 | static const char *arm_fallback_mode_string = "auto"; | |
129 | static const char *arm_force_mode_string = "auto"; | |
130 | ||
94c30b78 | 131 | /* Number of different reg name sets (options). */ |
afd7eef0 | 132 | static int num_disassembly_options; |
bc90b915 | 133 | |
123dc839 DJ |
134 | /* The standard register names, and all the valid aliases for them. */ |
135 | static const struct | |
136 | { | |
137 | const char *name; | |
138 | int regnum; | |
139 | } arm_register_aliases[] = { | |
140 | /* Basic register numbers. */ | |
141 | { "r0", 0 }, | |
142 | { "r1", 1 }, | |
143 | { "r2", 2 }, | |
144 | { "r3", 3 }, | |
145 | { "r4", 4 }, | |
146 | { "r5", 5 }, | |
147 | { "r6", 6 }, | |
148 | { "r7", 7 }, | |
149 | { "r8", 8 }, | |
150 | { "r9", 9 }, | |
151 | { "r10", 10 }, | |
152 | { "r11", 11 }, | |
153 | { "r12", 12 }, | |
154 | { "r13", 13 }, | |
155 | { "r14", 14 }, | |
156 | { "r15", 15 }, | |
157 | /* Synonyms (argument and variable registers). */ | |
158 | { "a1", 0 }, | |
159 | { "a2", 1 }, | |
160 | { "a3", 2 }, | |
161 | { "a4", 3 }, | |
162 | { "v1", 4 }, | |
163 | { "v2", 5 }, | |
164 | { "v3", 6 }, | |
165 | { "v4", 7 }, | |
166 | { "v5", 8 }, | |
167 | { "v6", 9 }, | |
168 | { "v7", 10 }, | |
169 | { "v8", 11 }, | |
170 | /* Other platform-specific names for r9. */ | |
171 | { "sb", 9 }, | |
172 | { "tr", 9 }, | |
173 | /* Special names. */ | |
174 | { "ip", 12 }, | |
175 | { "sp", 13 }, | |
176 | { "lr", 14 }, | |
177 | { "pc", 15 }, | |
178 | /* Names used by GCC (not listed in the ARM EABI). */ | |
179 | { "sl", 10 }, | |
180 | { "fp", 11 }, | |
181 | /* A special name from the older ATPCS. */ | |
182 | { "wr", 7 }, | |
183 | }; | |
bc90b915 | 184 | |
123dc839 | 185 | static const char *const arm_register_names[] = |
da59e081 JM |
186 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
187 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
188 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
189 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
190 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
191 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 192 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 193 | |
afd7eef0 RE |
194 | /* Valid register name styles. */ |
195 | static const char **valid_disassembly_styles; | |
ed9a39eb | 196 | |
afd7eef0 RE |
197 | /* Disassembly style to use. Default to "std" register names. */ |
198 | static const char *disassembly_style; | |
96baa820 | 199 | |
ed9a39eb | 200 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
201 | style. */ |
202 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 203 | struct cmd_list_element *); |
afd7eef0 | 204 | static void set_disassembly_style (void); |
ed9a39eb | 205 | |
b508a996 | 206 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 207 | void *, int); |
b508a996 | 208 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 209 | const void *, int); |
ed9a39eb | 210 | |
58d6951d DJ |
211 | static void arm_neon_quad_read (struct gdbarch *gdbarch, |
212 | struct regcache *regcache, | |
213 | int regnum, gdb_byte *buf); | |
214 | static void arm_neon_quad_write (struct gdbarch *gdbarch, | |
215 | struct regcache *regcache, | |
216 | int regnum, const gdb_byte *buf); | |
217 | ||
9b8d791a | 218 | struct arm_prologue_cache |
c3b4394c | 219 | { |
eb5492fa DJ |
220 | /* The stack pointer at the time this frame was created; i.e. the |
221 | caller's stack pointer when this function was called. It is used | |
222 | to identify this frame. */ | |
223 | CORE_ADDR prev_sp; | |
224 | ||
4be43953 DJ |
225 | /* The frame base for this frame is just prev_sp - frame size. |
226 | FRAMESIZE is the distance from the frame pointer to the | |
227 | initial stack pointer. */ | |
eb5492fa | 228 | |
c3b4394c | 229 | int framesize; |
eb5492fa DJ |
230 | |
231 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 232 | int framereg; |
eb5492fa DJ |
233 | |
234 | /* Saved register offsets. */ | |
235 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 236 | }; |
ed9a39eb | 237 | |
cca44b1b JB |
238 | /* Architecture version for displaced stepping. This effects the behaviour of |
239 | certain instructions, and really should not be hard-wired. */ | |
240 | ||
241 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
242 | ||
bc90b915 FN |
243 | /* Addresses for calling Thumb functions have the bit 0 set. |
244 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
245 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
246 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
247 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
248 | ||
94c30b78 | 249 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
250 | |
251 | int arm_apcs_32 = 1; | |
252 | ||
b39cc962 DJ |
253 | /* Determine if FRAME is executing in Thumb mode. */ |
254 | ||
255 | static int | |
256 | arm_frame_is_thumb (struct frame_info *frame) | |
257 | { | |
258 | CORE_ADDR cpsr; | |
259 | ||
260 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
261 | directly (from a signal frame or dummy frame) or by interpreting | |
262 | the saved LR (from a prologue or DWARF frame). So consult it and | |
263 | trust the unwinders. */ | |
264 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
265 | ||
266 | return (cpsr & CPSR_T) != 0; | |
267 | } | |
268 | ||
60c5725c DJ |
269 | /* Callback for VEC_lower_bound. */ |
270 | ||
271 | static inline int | |
272 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, | |
273 | const struct arm_mapping_symbol *rhs) | |
274 | { | |
275 | return lhs->value < rhs->value; | |
276 | } | |
277 | ||
f9d67f43 DJ |
278 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
279 | return its type. Otherwise, return 0. If START is non-NULL, | |
280 | set *START to the location of the mapping symbol. */ | |
c906108c | 281 | |
f9d67f43 DJ |
282 | static char |
283 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 284 | { |
60c5725c | 285 | struct obj_section *sec; |
0428b8f5 | 286 | |
60c5725c DJ |
287 | /* If there are mapping symbols, consult them. */ |
288 | sec = find_pc_section (memaddr); | |
289 | if (sec != NULL) | |
290 | { | |
291 | struct arm_per_objfile *data; | |
292 | VEC(arm_mapping_symbol_s) *map; | |
aded6f54 PA |
293 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
294 | 0 }; | |
60c5725c DJ |
295 | unsigned int idx; |
296 | ||
297 | data = objfile_data (sec->objfile, arm_objfile_data_key); | |
298 | if (data != NULL) | |
299 | { | |
300 | map = data->section_maps[sec->the_bfd_section->index]; | |
301 | if (!VEC_empty (arm_mapping_symbol_s, map)) | |
302 | { | |
303 | struct arm_mapping_symbol *map_sym; | |
304 | ||
305 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, | |
306 | arm_compare_mapping_symbols); | |
307 | ||
308 | /* VEC_lower_bound finds the earliest ordered insertion | |
309 | point. If the following symbol starts at this exact | |
310 | address, we use that; otherwise, the preceding | |
311 | mapping symbol covers this address. */ | |
312 | if (idx < VEC_length (arm_mapping_symbol_s, map)) | |
313 | { | |
314 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); | |
315 | if (map_sym->value == map_key.value) | |
f9d67f43 DJ |
316 | { |
317 | if (start) | |
318 | *start = map_sym->value + obj_section_addr (sec); | |
319 | return map_sym->type; | |
320 | } | |
60c5725c DJ |
321 | } |
322 | ||
323 | if (idx > 0) | |
324 | { | |
325 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); | |
f9d67f43 DJ |
326 | if (start) |
327 | *start = map_sym->value + obj_section_addr (sec); | |
328 | return map_sym->type; | |
60c5725c DJ |
329 | } |
330 | } | |
331 | } | |
332 | } | |
333 | ||
f9d67f43 DJ |
334 | return 0; |
335 | } | |
336 | ||
50e98be4 DJ |
337 | static CORE_ADDR arm_get_next_pc_raw (struct frame_info *frame, |
338 | CORE_ADDR pc, int insert_bkpt); | |
339 | ||
f9d67f43 DJ |
340 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
341 | function. This function should be called for addresses unrelated to | |
342 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
343 | ||
344 | static int | |
345 | arm_pc_is_thumb (CORE_ADDR memaddr) | |
346 | { | |
347 | struct obj_section *sec; | |
348 | struct minimal_symbol *sym; | |
349 | char type; | |
350 | ||
351 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
352 | if (IS_THUMB_ADDR (memaddr)) | |
353 | return 1; | |
354 | ||
355 | /* If the user wants to override the symbol table, let him. */ | |
356 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
357 | return 0; | |
358 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
359 | return 1; | |
360 | ||
361 | /* If there are mapping symbols, consult them. */ | |
362 | type = arm_find_mapping_symbol (memaddr, NULL); | |
363 | if (type) | |
364 | return type == 't'; | |
365 | ||
ed9a39eb | 366 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
367 | sym = lookup_minimal_symbol_by_pc (memaddr); |
368 | if (sym) | |
0428b8f5 DJ |
369 | return (MSYMBOL_IS_SPECIAL (sym)); |
370 | ||
371 | /* If the user wants to override the fallback mode, let them. */ | |
372 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
373 | return 0; | |
374 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
375 | return 1; | |
376 | ||
377 | /* If we couldn't find any symbol, but we're talking to a running | |
378 | target, then trust the current value of $cpsr. This lets | |
379 | "display/i $pc" always show the correct mode (though if there is | |
380 | a symbol table we will not reach here, so it still may not be | |
50e98be4 DJ |
381 | displayed in the mode it will be executed). |
382 | ||
383 | As a further heuristic if we detect that we are doing a single-step we | |
384 | see what state executing the current instruction ends up with us being | |
385 | in. */ | |
0428b8f5 | 386 | if (target_has_registers) |
50e98be4 DJ |
387 | { |
388 | struct frame_info *current_frame = get_current_frame (); | |
389 | CORE_ADDR current_pc = get_frame_pc (current_frame); | |
390 | int is_thumb = arm_frame_is_thumb (current_frame); | |
391 | CORE_ADDR next_pc; | |
392 | if (memaddr == current_pc) | |
393 | return is_thumb; | |
394 | else | |
395 | { | |
396 | struct gdbarch *gdbarch = get_frame_arch (current_frame); | |
397 | next_pc = arm_get_next_pc_raw (current_frame, current_pc, FALSE); | |
398 | if (memaddr == gdbarch_addr_bits_remove (gdbarch, next_pc)) | |
399 | return IS_THUMB_ADDR (next_pc); | |
400 | else | |
401 | return is_thumb; | |
402 | } | |
403 | } | |
0428b8f5 DJ |
404 | |
405 | /* Otherwise we're out of luck; we assume ARM. */ | |
406 | return 0; | |
c906108c SS |
407 | } |
408 | ||
181c1381 | 409 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 410 | static CORE_ADDR |
24568a2c | 411 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 412 | { |
a3a2ee65 | 413 | if (arm_apcs_32) |
dd6be234 | 414 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 415 | else |
a3a2ee65 | 416 | return (val & 0x03fffffc); |
c906108c SS |
417 | } |
418 | ||
181c1381 RE |
419 | /* When reading symbols, we need to zap the low bit of the address, |
420 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 421 | static CORE_ADDR |
24568a2c | 422 | arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) |
181c1381 RE |
423 | { |
424 | return val & ~1; | |
425 | } | |
426 | ||
29d73ae4 DJ |
427 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
428 | and frame pointer. Scan until we encounter a store that could | |
429 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
430 | |
431 | static CORE_ADDR | |
29d73ae4 DJ |
432 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
433 | CORE_ADDR start, CORE_ADDR limit, | |
434 | struct arm_prologue_cache *cache) | |
c906108c | 435 | { |
e17a4113 | 436 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
437 | int i; |
438 | pv_t regs[16]; | |
439 | struct pv_area *stack; | |
440 | struct cleanup *back_to; | |
441 | CORE_ADDR offset; | |
da3c6d4a | 442 | |
29d73ae4 DJ |
443 | for (i = 0; i < 16; i++) |
444 | regs[i] = pv_register (i, 0); | |
55f960e1 | 445 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 DJ |
446 | back_to = make_cleanup_free_pv_area (stack); |
447 | ||
29d73ae4 | 448 | while (start < limit) |
c906108c | 449 | { |
29d73ae4 DJ |
450 | unsigned short insn; |
451 | ||
e17a4113 | 452 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 453 | |
94c30b78 | 454 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 455 | { |
29d73ae4 DJ |
456 | int regno; |
457 | int mask; | |
4be43953 DJ |
458 | |
459 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
460 | break; | |
29d73ae4 DJ |
461 | |
462 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
463 | whether to save LR (R14). */ | |
464 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
465 | ||
466 | /* Calculate offsets of saved R0-R7 and LR. */ | |
467 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
468 | if (mask & (1 << regno)) | |
469 | { | |
29d73ae4 DJ |
470 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
471 | -4); | |
472 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
473 | } | |
da59e081 | 474 | } |
da3c6d4a MS |
475 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
476 | sub sp, #simm */ | |
da59e081 | 477 | { |
29d73ae4 DJ |
478 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
479 | if (insn & 0x80) /* Check for SUB. */ | |
480 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
481 | -offset); | |
da59e081 | 482 | else |
29d73ae4 DJ |
483 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
484 | offset); | |
da59e081 JM |
485 | } |
486 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
487 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
488 | (insn & 0xff) << 2); | |
489 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 490 | { |
29d73ae4 DJ |
491 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
492 | int src_reg = (insn & 0x78) >> 3; | |
493 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 494 | } |
29d73ae4 | 495 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 496 | { |
29d73ae4 DJ |
497 | /* Handle stores to the stack. Normally pushes are used, |
498 | but with GCC -mtpcs-frame, there may be other stores | |
499 | in the prologue to create the frame. */ | |
500 | int regno = (insn >> 8) & 0x7; | |
501 | pv_t addr; | |
502 | ||
503 | offset = (insn & 0xff) << 2; | |
504 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
505 | ||
506 | if (pv_area_store_would_trash (stack, addr)) | |
507 | break; | |
508 | ||
509 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 510 | } |
29d73ae4 | 511 | else |
3d74b771 | 512 | { |
29d73ae4 DJ |
513 | /* We don't know what this instruction is. We're finished |
514 | scanning. NOTE: Recognizing more safe-to-ignore | |
515 | instructions here will improve support for optimized | |
516 | code. */ | |
da3c6d4a | 517 | break; |
3d74b771 | 518 | } |
29d73ae4 DJ |
519 | |
520 | start += 2; | |
c906108c SS |
521 | } |
522 | ||
29d73ae4 DJ |
523 | if (cache == NULL) |
524 | { | |
525 | do_cleanups (back_to); | |
526 | return start; | |
527 | } | |
528 | ||
29d73ae4 DJ |
529 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
530 | { | |
531 | /* Frame pointer is fp. Frame size is constant. */ | |
532 | cache->framereg = ARM_FP_REGNUM; | |
533 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
534 | } | |
535 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
536 | { | |
537 | /* Frame pointer is r7. Frame size is constant. */ | |
538 | cache->framereg = THUMB_FP_REGNUM; | |
539 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
540 | } | |
541 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
542 | { | |
543 | /* Try the stack pointer... this is a bit desperate. */ | |
544 | cache->framereg = ARM_SP_REGNUM; | |
545 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
546 | } | |
547 | else | |
548 | { | |
549 | /* We're just out of luck. We don't know where the frame is. */ | |
550 | cache->framereg = -1; | |
551 | cache->framesize = 0; | |
552 | } | |
553 | ||
554 | for (i = 0; i < 16; i++) | |
555 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
556 | cache->saved_regs[i].addr = offset; | |
557 | ||
558 | do_cleanups (back_to); | |
559 | return start; | |
c906108c SS |
560 | } |
561 | ||
da3c6d4a MS |
562 | /* Advance the PC across any function entry prologue instructions to |
563 | reach some "real" code. | |
34e8f22d RE |
564 | |
565 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 566 | prologue: |
c906108c | 567 | |
c5aa993b JM |
568 | mov ip, sp |
569 | [stmfd sp!, {a1,a2,a3,a4}] | |
570 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
571 | [stfe f7, [sp, #-12]!] |
572 | [stfe f6, [sp, #-12]!] | |
573 | [stfe f5, [sp, #-12]!] | |
574 | [stfe f4, [sp, #-12]!] | |
575 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 576 | |
34e8f22d | 577 | static CORE_ADDR |
6093d2eb | 578 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 579 | { |
e17a4113 | 580 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
c906108c SS |
581 | unsigned long inst; |
582 | CORE_ADDR skip_pc; | |
a89fea3c | 583 | CORE_ADDR func_addr, limit_pc; |
c906108c SS |
584 | struct symtab_and_line sal; |
585 | ||
848cfffb | 586 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
d80b854b | 587 | if (deprecated_pc_in_call_dummy (gdbarch, pc)) |
848cfffb AC |
588 | return pc; |
589 | ||
a89fea3c JL |
590 | /* See if we can determine the end of the prologue via the symbol table. |
591 | If so, then return either PC, or the PC after the prologue, whichever | |
592 | is greater. */ | |
593 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 594 | { |
d80b854b UW |
595 | CORE_ADDR post_prologue_pc |
596 | = skip_prologue_using_sal (gdbarch, func_addr); | |
a89fea3c JL |
597 | if (post_prologue_pc != 0) |
598 | return max (pc, post_prologue_pc); | |
c906108c SS |
599 | } |
600 | ||
a89fea3c JL |
601 | /* Can't determine prologue from the symbol table, need to examine |
602 | instructions. */ | |
c906108c | 603 | |
a89fea3c JL |
604 | /* Find an upper limit on the function prologue using the debug |
605 | information. If the debug information could not be used to provide | |
606 | that bound, then use an arbitrary large number as the upper bound. */ | |
b8d5e71d | 607 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 608 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
609 | if (limit_pc == 0) |
610 | limit_pc = pc + 64; /* Magic. */ | |
611 | ||
c906108c | 612 | |
29d73ae4 DJ |
613 | /* Check if this is Thumb code. */ |
614 | if (arm_pc_is_thumb (pc)) | |
a89fea3c | 615 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
29d73ae4 | 616 | |
a89fea3c | 617 | for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) |
f43845b3 | 618 | { |
e17a4113 | 619 | inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); |
9d4fde75 | 620 | |
b8d5e71d MS |
621 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
622 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
623 | continue; | |
c906108c | 624 | |
28cd8767 JG |
625 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
626 | continue; | |
627 | ||
628 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
629 | continue; | |
630 | ||
b8d5e71d MS |
631 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
632 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
633 | continue; | |
c906108c | 634 | |
b8d5e71d MS |
635 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
636 | continue; | |
c906108c | 637 | |
b8d5e71d MS |
638 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
639 | continue; | |
11d3b27d | 640 | |
b8d5e71d MS |
641 | /* Any insns after this point may float into the code, if it makes |
642 | for better instruction scheduling, so we skip them only if we | |
643 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 644 | |
b8d5e71d MS |
645 | /* We may have either one sfmfd instruction here, or several stfe |
646 | insns, depending on the version of floating point code we | |
647 | support. */ | |
648 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
649 | continue; | |
650 | ||
651 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
652 | continue; | |
653 | ||
654 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
655 | continue; | |
656 | ||
657 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
658 | continue; | |
659 | ||
f8bf5763 PM |
660 | if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */ |
661 | || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */ | |
662 | || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
b8d5e71d MS |
663 | continue; |
664 | ||
f8bf5763 PM |
665 | if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */ |
666 | || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */ | |
667 | || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
b8d5e71d MS |
668 | continue; |
669 | ||
670 | /* Un-recognized instruction; stop scanning. */ | |
671 | break; | |
f43845b3 | 672 | } |
c906108c | 673 | |
b8d5e71d | 674 | return skip_pc; /* End of prologue */ |
c906108c | 675 | } |
94c30b78 | 676 | |
c5aa993b | 677 | /* *INDENT-OFF* */ |
c906108c SS |
678 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
679 | This function decodes a Thumb function prologue to determine: | |
680 | 1) the size of the stack frame | |
681 | 2) which registers are saved on it | |
682 | 3) the offsets of saved regs | |
683 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 684 | |
da59e081 JM |
685 | A typical Thumb function prologue would create this stack frame |
686 | (offsets relative to FP) | |
c906108c SS |
687 | old SP -> 24 stack parameters |
688 | 20 LR | |
689 | 16 R7 | |
690 | R7 -> 0 local variables (16 bytes) | |
691 | SP -> -12 additional stack space (12 bytes) | |
692 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
693 | 12 bytes. The frame register is R7. |
694 | ||
da3c6d4a MS |
695 | The comments for thumb_skip_prolog() describe the algorithm we use |
696 | to detect the end of the prolog. */ | |
c5aa993b JM |
697 | /* *INDENT-ON* */ |
698 | ||
c906108c | 699 | static void |
be8626e0 | 700 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 701 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
702 | { |
703 | CORE_ADDR prologue_start; | |
704 | CORE_ADDR prologue_end; | |
705 | CORE_ADDR current_pc; | |
c906108c | 706 | |
b39cc962 DJ |
707 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
708 | &prologue_end)) | |
c906108c SS |
709 | { |
710 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
711 | ||
94c30b78 | 712 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 713 | prologue_end = prev_pc; |
c906108c | 714 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 715 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
716 | } |
717 | else | |
f7060f85 DJ |
718 | /* We're in the boondocks: we have no idea where the start of the |
719 | function is. */ | |
720 | return; | |
c906108c | 721 | |
eb5492fa | 722 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 723 | |
be8626e0 | 724 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
725 | } |
726 | ||
ed9a39eb | 727 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
728 | 1) the size of the stack frame |
729 | 2) which registers are saved on it | |
730 | 3) the offsets of saved regs | |
731 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
732 | This information is stored in the "extra" fields of the frame_info. |
733 | ||
96baa820 JM |
734 | There are two basic forms for the ARM prologue. The fixed argument |
735 | function call will look like: | |
ed9a39eb JM |
736 | |
737 | mov ip, sp | |
738 | stmfd sp!, {fp, ip, lr, pc} | |
739 | sub fp, ip, #4 | |
740 | [sub sp, sp, #4] | |
96baa820 | 741 | |
c906108c | 742 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
743 | IP -> 4 (caller's stack) |
744 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
745 | -4 LR (return address in caller) | |
746 | -8 IP (copy of caller's SP) | |
747 | -12 FP (caller's FP) | |
748 | SP -> -28 Local variables | |
749 | ||
c906108c | 750 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
751 | 28 bytes. The stmfd call can also save any of the vN registers it |
752 | plans to use, which increases the frame size accordingly. | |
753 | ||
754 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
755 | because the ARM Store instructions always store PC + 8 when you read | |
756 | the PC register. | |
ed9a39eb | 757 | |
96baa820 JM |
758 | A variable argument function call will look like: |
759 | ||
ed9a39eb JM |
760 | mov ip, sp |
761 | stmfd sp!, {a1, a2, a3, a4} | |
762 | stmfd sp!, {fp, ip, lr, pc} | |
763 | sub fp, ip, #20 | |
764 | ||
96baa820 | 765 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
766 | IP -> 20 (caller's stack) |
767 | 16 A4 | |
768 | 12 A3 | |
769 | 8 A2 | |
770 | 4 A1 | |
771 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
772 | -4 LR (return address in caller) | |
773 | -8 IP (copy of caller's SP) | |
774 | -12 FP (caller's FP) | |
775 | SP -> -28 Local variables | |
96baa820 JM |
776 | |
777 | The frame size would thus be 48 bytes, and the frame offset would be | |
778 | 28 bytes. | |
779 | ||
780 | There is another potential complication, which is that the optimizer | |
781 | will try to separate the store of fp in the "stmfd" instruction from | |
782 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
783 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
784 | ||
785 | Also, note, the original version of the ARM toolchain claimed that there | |
786 | should be an | |
787 | ||
788 | instruction at the end of the prologue. I have never seen GCC produce | |
789 | this, and the ARM docs don't mention it. We still test for it below in | |
790 | case it happens... | |
ed9a39eb JM |
791 | |
792 | */ | |
c906108c SS |
793 | |
794 | static void | |
a262aec2 | 795 | arm_scan_prologue (struct frame_info *this_frame, |
2af46ca0 | 796 | struct arm_prologue_cache *cache) |
c906108c | 797 | { |
a262aec2 | 798 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
799 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
800 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4be43953 | 801 | int regno; |
c906108c | 802 | CORE_ADDR prologue_start, prologue_end, current_pc; |
a262aec2 | 803 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
b39cc962 | 804 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
4be43953 DJ |
805 | pv_t regs[ARM_FPS_REGNUM]; |
806 | struct pv_area *stack; | |
807 | struct cleanup *back_to; | |
808 | CORE_ADDR offset; | |
c906108c | 809 | |
c906108c | 810 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
811 | cache->framereg = ARM_SP_REGNUM; |
812 | cache->framesize = 0; | |
c906108c SS |
813 | |
814 | /* Check for Thumb prologue. */ | |
b39cc962 | 815 | if (arm_frame_is_thumb (this_frame)) |
c906108c | 816 | { |
b39cc962 | 817 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
c906108c SS |
818 | return; |
819 | } | |
820 | ||
821 | /* Find the function prologue. If we can't find the function in | |
822 | the symbol table, peek in the stack frame to find the PC. */ | |
b39cc962 DJ |
823 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
824 | &prologue_end)) | |
c906108c | 825 | { |
2a451106 KB |
826 | /* One way to find the end of the prologue (which works well |
827 | for unoptimized code) is to do the following: | |
828 | ||
829 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
830 | ||
831 | if (sal.line == 0) | |
eb5492fa | 832 | prologue_end = prev_pc; |
2a451106 KB |
833 | else if (sal.end < prologue_end) |
834 | prologue_end = sal.end; | |
835 | ||
836 | This mechanism is very accurate so long as the optimizer | |
837 | doesn't move any instructions from the function body into the | |
838 | prologue. If this happens, sal.end will be the last | |
839 | instruction in the first hunk of prologue code just before | |
840 | the first instruction that the scheduler has moved from | |
841 | the body to the prologue. | |
842 | ||
843 | In order to make sure that we scan all of the prologue | |
844 | instructions, we use a slightly less accurate mechanism which | |
845 | may scan more than necessary. To help compensate for this | |
846 | lack of accuracy, the prologue scanning loop below contains | |
847 | several clauses which'll cause the loop to terminate early if | |
848 | an implausible prologue instruction is encountered. | |
849 | ||
850 | The expression | |
851 | ||
852 | prologue_start + 64 | |
853 | ||
854 | is a suitable endpoint since it accounts for the largest | |
855 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 856 | the scheduler. */ |
2a451106 KB |
857 | |
858 | if (prologue_end > prologue_start + 64) | |
859 | { | |
94c30b78 | 860 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 861 | } |
c906108c SS |
862 | } |
863 | else | |
864 | { | |
eb5492fa DJ |
865 | /* We have no symbol information. Our only option is to assume this |
866 | function has a standard stack frame and the normal frame register. | |
867 | Then, we can find the value of our frame pointer on entrance to | |
868 | the callee (or at the present moment if this is the innermost frame). | |
869 | The value stored there should be the address of the stmfd + 8. */ | |
870 | CORE_ADDR frame_loc; | |
871 | LONGEST return_value; | |
872 | ||
a262aec2 | 873 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
e17a4113 | 874 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) |
16a0f3e7 EZ |
875 | return; |
876 | else | |
877 | { | |
bf6ae464 | 878 | prologue_start = gdbarch_addr_bits_remove |
2af46ca0 | 879 | (gdbarch, return_value) - 8; |
94c30b78 | 880 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 881 | } |
c906108c SS |
882 | } |
883 | ||
eb5492fa DJ |
884 | if (prev_pc < prologue_end) |
885 | prologue_end = prev_pc; | |
886 | ||
c906108c | 887 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 888 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 889 | |
96baa820 JM |
890 | Be careful, however, and if it doesn't look like a prologue, |
891 | don't try to scan it. If, for instance, a frameless function | |
892 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 893 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
894 | and other operations that rely on a knowledge of the stack |
895 | traceback. | |
896 | ||
897 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 898 | if we don't see this as the first insn, we will stop. |
c906108c | 899 | |
f43845b3 MS |
900 | [Note: This doesn't seem to be true any longer, so it's now an |
901 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 902 | |
f43845b3 MS |
903 | [Note further: The "mov ip,sp" only seems to be missing in |
904 | frameless functions at optimization level "-O2" or above, | |
905 | in which case it is often (but not always) replaced by | |
b8d5e71d | 906 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 907 | |
4be43953 DJ |
908 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
909 | regs[regno] = pv_register (regno, 0); | |
55f960e1 | 910 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 DJ |
911 | back_to = make_cleanup_free_pv_area (stack); |
912 | ||
94c30b78 MS |
913 | for (current_pc = prologue_start; |
914 | current_pc < prologue_end; | |
f43845b3 | 915 | current_pc += 4) |
96baa820 | 916 | { |
e17a4113 UW |
917 | unsigned int insn |
918 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); | |
9d4fde75 | 919 | |
94c30b78 | 920 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 921 | { |
4be43953 | 922 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
923 | continue; |
924 | } | |
925 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
926 | { | |
927 | unsigned imm = insn & 0xff; /* immediate value */ | |
928 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
929 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 930 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
28cd8767 JG |
931 | continue; |
932 | } | |
933 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
934 | { | |
935 | unsigned imm = insn & 0xff; /* immediate value */ | |
936 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
937 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 938 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
f43845b3 MS |
939 | continue; |
940 | } | |
94c30b78 | 941 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 942 | { |
4be43953 DJ |
943 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
944 | break; | |
945 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
946 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); | |
f43845b3 MS |
947 | continue; |
948 | } | |
949 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
950 | /* stmfd sp!, {..., fp, ip, lr, pc} |
951 | or | |
952 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 953 | { |
d4473757 | 954 | int mask = insn & 0xffff; |
ed9a39eb | 955 | |
4be43953 DJ |
956 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
957 | break; | |
958 | ||
94c30b78 | 959 | /* Calculate offsets of saved registers. */ |
34e8f22d | 960 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
961 | if (mask & (1 << regno)) |
962 | { | |
4be43953 DJ |
963 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
964 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
d4473757 KB |
965 | } |
966 | } | |
f8bf5763 PM |
967 | else if ((insn & 0xffffc000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
968 | || (insn & 0xffffc0f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
969 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
b8d5e71d MS |
970 | { |
971 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
972 | continue; | |
973 | } | |
f8bf5763 PM |
974 | else if ((insn & 0xffffc000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
975 | || (insn & 0xffffc0f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
976 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
977 | { |
978 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
979 | continue; | |
980 | } | |
d4473757 KB |
981 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
982 | { | |
94c30b78 MS |
983 | unsigned imm = insn & 0xff; /* immediate value */ |
984 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 985 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 986 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
987 | } |
988 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
989 | { | |
94c30b78 MS |
990 | unsigned imm = insn & 0xff; /* immediate value */ |
991 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 992 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 993 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 994 | } |
ff6f572f | 995 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
2af46ca0 | 996 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 997 | { |
4be43953 DJ |
998 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
999 | break; | |
1000 | ||
1001 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1002 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 1003 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1004 | } |
ff6f572f | 1005 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
2af46ca0 | 1006 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
1007 | { |
1008 | int n_saved_fp_regs; | |
1009 | unsigned int fp_start_reg, fp_bound_reg; | |
1010 | ||
4be43953 DJ |
1011 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
1012 | break; | |
1013 | ||
94c30b78 | 1014 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1015 | { |
d4473757 KB |
1016 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1017 | n_saved_fp_regs = 3; | |
1018 | else | |
1019 | n_saved_fp_regs = 1; | |
96baa820 | 1020 | } |
d4473757 | 1021 | else |
96baa820 | 1022 | { |
d4473757 KB |
1023 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1024 | n_saved_fp_regs = 2; | |
1025 | else | |
1026 | n_saved_fp_regs = 4; | |
96baa820 | 1027 | } |
d4473757 | 1028 | |
34e8f22d | 1029 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1030 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1031 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1032 | { |
4be43953 DJ |
1033 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
1034 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
1035 | regs[fp_start_reg++]); | |
96baa820 | 1036 | } |
c906108c | 1037 | } |
d4473757 | 1038 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 1039 | break; /* Condition not true, exit early */ |
b8d5e71d | 1040 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 1041 | break; /* Don't scan past a block load */ |
d4473757 KB |
1042 | else |
1043 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 1044 | so we just skip what we don't recognize. */ |
d4473757 | 1045 | continue; |
c906108c SS |
1046 | } |
1047 | ||
4be43953 DJ |
1048 | /* The frame size is just the distance from the frame register |
1049 | to the original stack pointer. */ | |
1050 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1051 | { | |
1052 | /* Frame pointer is fp. */ | |
1053 | cache->framereg = ARM_FP_REGNUM; | |
1054 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1055 | } | |
1056 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
1057 | { | |
1058 | /* Try the stack pointer... this is a bit desperate. */ | |
1059 | cache->framereg = ARM_SP_REGNUM; | |
1060 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1061 | } | |
d4473757 | 1062 | else |
4be43953 DJ |
1063 | { |
1064 | /* We're just out of luck. We don't know where the frame is. */ | |
1065 | cache->framereg = -1; | |
1066 | cache->framesize = 0; | |
1067 | } | |
1068 | ||
1069 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
1070 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
1071 | cache->saved_regs[regno].addr = offset; | |
1072 | ||
1073 | do_cleanups (back_to); | |
c906108c SS |
1074 | } |
1075 | ||
eb5492fa | 1076 | static struct arm_prologue_cache * |
a262aec2 | 1077 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1078 | { |
eb5492fa DJ |
1079 | int reg; |
1080 | struct arm_prologue_cache *cache; | |
1081 | CORE_ADDR unwound_fp; | |
c5aa993b | 1082 | |
35d5d4ee | 1083 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1084 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1085 | |
a262aec2 | 1086 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1087 | |
a262aec2 | 1088 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1089 | if (unwound_fp == 0) |
1090 | return cache; | |
c906108c | 1091 | |
4be43953 | 1092 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1093 | |
eb5492fa DJ |
1094 | /* Calculate actual addresses of saved registers using offsets |
1095 | determined by arm_scan_prologue. */ | |
a262aec2 | 1096 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 1097 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
1098 | cache->saved_regs[reg].addr += cache->prev_sp; |
1099 | ||
1100 | return cache; | |
c906108c SS |
1101 | } |
1102 | ||
eb5492fa DJ |
1103 | /* Our frame ID for a normal frame is the current function's starting PC |
1104 | and the caller's SP when we were called. */ | |
c906108c | 1105 | |
148754e5 | 1106 | static void |
a262aec2 | 1107 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1108 | void **this_cache, |
1109 | struct frame_id *this_id) | |
c906108c | 1110 | { |
eb5492fa DJ |
1111 | struct arm_prologue_cache *cache; |
1112 | struct frame_id id; | |
2c404490 | 1113 | CORE_ADDR pc, func; |
f079148d | 1114 | |
eb5492fa | 1115 | if (*this_cache == NULL) |
a262aec2 | 1116 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1117 | cache = *this_cache; |
2a451106 | 1118 | |
2c404490 DJ |
1119 | /* This is meant to halt the backtrace at "_start". */ |
1120 | pc = get_frame_pc (this_frame); | |
1121 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
eb5492fa | 1122 | return; |
5a203e44 | 1123 | |
eb5492fa DJ |
1124 | /* If we've hit a wall, stop. */ |
1125 | if (cache->prev_sp == 0) | |
1126 | return; | |
24de872b | 1127 | |
2c404490 | 1128 | func = get_frame_func (this_frame); |
eb5492fa | 1129 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1130 | *this_id = id; |
c906108c SS |
1131 | } |
1132 | ||
a262aec2 DJ |
1133 | static struct value * |
1134 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1135 | void **this_cache, |
a262aec2 | 1136 | int prev_regnum) |
24de872b | 1137 | { |
24568a2c | 1138 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1139 | struct arm_prologue_cache *cache; |
1140 | ||
eb5492fa | 1141 | if (*this_cache == NULL) |
a262aec2 | 1142 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1143 | cache = *this_cache; |
24de872b | 1144 | |
eb5492fa | 1145 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1146 | instead. The prologue may save PC, but it will point into this |
1147 | frame's prologue, not the next frame's resume location. Also | |
1148 | strip the saved T bit. A valid LR may have the low bit set, but | |
1149 | a valid PC never does. */ | |
eb5492fa | 1150 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1151 | { |
1152 | CORE_ADDR lr; | |
1153 | ||
1154 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1155 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1156 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1157 | } |
24de872b | 1158 | |
eb5492fa | 1159 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1160 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1161 | The value was already reconstructed into PREV_SP. */ |
1162 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1163 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1164 | |
b39cc962 DJ |
1165 | /* The CPSR may have been changed by the call instruction and by the |
1166 | called function. The only bit we can reconstruct is the T bit, | |
1167 | by checking the low bit of LR as of the call. This is a reliable | |
1168 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
1169 | Thumb code, which could get away with a clear low bit as long as | |
1170 | the called function did not use bx. Guess that all other | |
1171 | bits are unchanged; the condition flags are presumably lost, | |
1172 | but the processor status is likely valid. */ | |
1173 | if (prev_regnum == ARM_PS_REGNUM) | |
1174 | { | |
1175 | CORE_ADDR lr, cpsr; | |
1176 | ||
1177 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
1178 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1179 | if (IS_THUMB_ADDR (lr)) | |
1180 | cpsr |= CPSR_T; | |
1181 | else | |
1182 | cpsr &= ~CPSR_T; | |
1183 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); | |
1184 | } | |
1185 | ||
a262aec2 DJ |
1186 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
1187 | prev_regnum); | |
eb5492fa DJ |
1188 | } |
1189 | ||
1190 | struct frame_unwind arm_prologue_unwind = { | |
1191 | NORMAL_FRAME, | |
1192 | arm_prologue_this_id, | |
a262aec2 DJ |
1193 | arm_prologue_prev_register, |
1194 | NULL, | |
1195 | default_frame_sniffer | |
eb5492fa DJ |
1196 | }; |
1197 | ||
909cf6ea | 1198 | static struct arm_prologue_cache * |
a262aec2 | 1199 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea DJ |
1200 | { |
1201 | int reg; | |
1202 | struct arm_prologue_cache *cache; | |
1203 | CORE_ADDR unwound_fp; | |
1204 | ||
35d5d4ee | 1205 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1206 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 1207 | |
a262aec2 | 1208 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
1209 | |
1210 | return cache; | |
1211 | } | |
1212 | ||
1213 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1214 | ||
1215 | static void | |
a262aec2 | 1216 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
1217 | void **this_cache, |
1218 | struct frame_id *this_id) | |
1219 | { | |
1220 | struct arm_prologue_cache *cache; | |
1221 | ||
1222 | if (*this_cache == NULL) | |
a262aec2 | 1223 | *this_cache = arm_make_stub_cache (this_frame); |
909cf6ea DJ |
1224 | cache = *this_cache; |
1225 | ||
a262aec2 | 1226 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
1227 | } |
1228 | ||
a262aec2 DJ |
1229 | static int |
1230 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
1231 | struct frame_info *this_frame, | |
1232 | void **this_prologue_cache) | |
909cf6ea | 1233 | { |
93d42b30 | 1234 | CORE_ADDR addr_in_block; |
909cf6ea DJ |
1235 | char dummy[4]; |
1236 | ||
a262aec2 | 1237 | addr_in_block = get_frame_address_in_block (this_frame); |
93d42b30 | 1238 | if (in_plt_section (addr_in_block, NULL) |
a262aec2 DJ |
1239 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
1240 | return 1; | |
909cf6ea | 1241 | |
a262aec2 | 1242 | return 0; |
909cf6ea DJ |
1243 | } |
1244 | ||
a262aec2 DJ |
1245 | struct frame_unwind arm_stub_unwind = { |
1246 | NORMAL_FRAME, | |
1247 | arm_stub_this_id, | |
1248 | arm_prologue_prev_register, | |
1249 | NULL, | |
1250 | arm_stub_unwind_sniffer | |
1251 | }; | |
1252 | ||
24de872b | 1253 | static CORE_ADDR |
a262aec2 | 1254 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
1255 | { |
1256 | struct arm_prologue_cache *cache; | |
1257 | ||
eb5492fa | 1258 | if (*this_cache == NULL) |
a262aec2 | 1259 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa DJ |
1260 | cache = *this_cache; |
1261 | ||
4be43953 | 1262 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
1263 | } |
1264 | ||
eb5492fa DJ |
1265 | struct frame_base arm_normal_base = { |
1266 | &arm_prologue_unwind, | |
1267 | arm_normal_frame_base, | |
1268 | arm_normal_frame_base, | |
1269 | arm_normal_frame_base | |
1270 | }; | |
1271 | ||
a262aec2 | 1272 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
1273 | dummy frame. The frame ID's base needs to match the TOS value |
1274 | saved by save_dummy_frame_tos() and returned from | |
1275 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1276 | breakpoint. */ | |
c906108c | 1277 | |
eb5492fa | 1278 | static struct frame_id |
a262aec2 | 1279 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 1280 | { |
a262aec2 DJ |
1281 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
1282 | get_frame_pc (this_frame)); | |
eb5492fa | 1283 | } |
c3b4394c | 1284 | |
eb5492fa DJ |
1285 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1286 | be used to construct the previous frame's ID, after looking up the | |
1287 | containing function). */ | |
c3b4394c | 1288 | |
eb5492fa DJ |
1289 | static CORE_ADDR |
1290 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1291 | { | |
1292 | CORE_ADDR pc; | |
1293 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
24568a2c | 1294 | return arm_addr_bits_remove (gdbarch, pc); |
eb5492fa DJ |
1295 | } |
1296 | ||
1297 | static CORE_ADDR | |
1298 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1299 | { | |
1300 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1301 | } |
1302 | ||
b39cc962 DJ |
1303 | static struct value * |
1304 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
1305 | int regnum) | |
1306 | { | |
24568a2c | 1307 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 DJ |
1308 | CORE_ADDR lr, cpsr; |
1309 | ||
1310 | switch (regnum) | |
1311 | { | |
1312 | case ARM_PC_REGNUM: | |
1313 | /* The PC is normally copied from the return column, which | |
1314 | describes saves of LR. However, that version may have an | |
1315 | extra bit set to indicate Thumb state. The bit is not | |
1316 | part of the PC. */ | |
1317 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1318 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 1319 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
1320 | |
1321 | case ARM_PS_REGNUM: | |
1322 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 1323 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
1324 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
1325 | if (IS_THUMB_ADDR (lr)) | |
1326 | cpsr |= CPSR_T; | |
1327 | else | |
1328 | cpsr &= ~CPSR_T; | |
ca38c58e | 1329 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
1330 | |
1331 | default: | |
1332 | internal_error (__FILE__, __LINE__, | |
1333 | _("Unexpected register %d"), regnum); | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | static void | |
1338 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1339 | struct dwarf2_frame_state_reg *reg, | |
1340 | struct frame_info *this_frame) | |
1341 | { | |
1342 | switch (regnum) | |
1343 | { | |
1344 | case ARM_PC_REGNUM: | |
1345 | case ARM_PS_REGNUM: | |
1346 | reg->how = DWARF2_FRAME_REG_FN; | |
1347 | reg->loc.fn = arm_dwarf2_prev_register; | |
1348 | break; | |
1349 | case ARM_SP_REGNUM: | |
1350 | reg->how = DWARF2_FRAME_REG_CFA; | |
1351 | break; | |
1352 | } | |
1353 | } | |
1354 | ||
2dd604e7 RE |
1355 | /* When arguments must be pushed onto the stack, they go on in reverse |
1356 | order. The code below implements a FILO (stack) to do this. */ | |
1357 | ||
1358 | struct stack_item | |
1359 | { | |
1360 | int len; | |
1361 | struct stack_item *prev; | |
1362 | void *data; | |
1363 | }; | |
1364 | ||
1365 | static struct stack_item * | |
1366 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1367 | { | |
1368 | struct stack_item *si; | |
1369 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1370 | si->data = xmalloc (len); |
2dd604e7 RE |
1371 | si->len = len; |
1372 | si->prev = prev; | |
1373 | memcpy (si->data, contents, len); | |
1374 | return si; | |
1375 | } | |
1376 | ||
1377 | static struct stack_item * | |
1378 | pop_stack_item (struct stack_item *si) | |
1379 | { | |
1380 | struct stack_item *dead = si; | |
1381 | si = si->prev; | |
1382 | xfree (dead->data); | |
1383 | xfree (dead); | |
1384 | return si; | |
1385 | } | |
1386 | ||
2af48f68 PB |
1387 | |
1388 | /* Return the alignment (in bytes) of the given type. */ | |
1389 | ||
1390 | static int | |
1391 | arm_type_align (struct type *t) | |
1392 | { | |
1393 | int n; | |
1394 | int align; | |
1395 | int falign; | |
1396 | ||
1397 | t = check_typedef (t); | |
1398 | switch (TYPE_CODE (t)) | |
1399 | { | |
1400 | default: | |
1401 | /* Should never happen. */ | |
1402 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1403 | return 4; | |
1404 | ||
1405 | case TYPE_CODE_PTR: | |
1406 | case TYPE_CODE_ENUM: | |
1407 | case TYPE_CODE_INT: | |
1408 | case TYPE_CODE_FLT: | |
1409 | case TYPE_CODE_SET: | |
1410 | case TYPE_CODE_RANGE: | |
1411 | case TYPE_CODE_BITSTRING: | |
1412 | case TYPE_CODE_REF: | |
1413 | case TYPE_CODE_CHAR: | |
1414 | case TYPE_CODE_BOOL: | |
1415 | return TYPE_LENGTH (t); | |
1416 | ||
1417 | case TYPE_CODE_ARRAY: | |
1418 | case TYPE_CODE_COMPLEX: | |
1419 | /* TODO: What about vector types? */ | |
1420 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1421 | ||
1422 | case TYPE_CODE_STRUCT: | |
1423 | case TYPE_CODE_UNION: | |
1424 | align = 1; | |
1425 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1426 | { | |
1427 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1428 | if (falign > align) | |
1429 | align = falign; | |
1430 | } | |
1431 | return align; | |
1432 | } | |
1433 | } | |
1434 | ||
90445bd3 DJ |
1435 | /* Possible base types for a candidate for passing and returning in |
1436 | VFP registers. */ | |
1437 | ||
1438 | enum arm_vfp_cprc_base_type | |
1439 | { | |
1440 | VFP_CPRC_UNKNOWN, | |
1441 | VFP_CPRC_SINGLE, | |
1442 | VFP_CPRC_DOUBLE, | |
1443 | VFP_CPRC_VEC64, | |
1444 | VFP_CPRC_VEC128 | |
1445 | }; | |
1446 | ||
1447 | /* The length of one element of base type B. */ | |
1448 | ||
1449 | static unsigned | |
1450 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
1451 | { | |
1452 | switch (b) | |
1453 | { | |
1454 | case VFP_CPRC_SINGLE: | |
1455 | return 4; | |
1456 | case VFP_CPRC_DOUBLE: | |
1457 | return 8; | |
1458 | case VFP_CPRC_VEC64: | |
1459 | return 8; | |
1460 | case VFP_CPRC_VEC128: | |
1461 | return 16; | |
1462 | default: | |
1463 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
1464 | (int) b); | |
1465 | } | |
1466 | } | |
1467 | ||
1468 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
1469 | for passing base type B. */ | |
1470 | ||
1471 | static int | |
1472 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
1473 | { | |
1474 | switch (b) | |
1475 | { | |
1476 | case VFP_CPRC_SINGLE: | |
1477 | return 's'; | |
1478 | case VFP_CPRC_DOUBLE: | |
1479 | return 'd'; | |
1480 | case VFP_CPRC_VEC64: | |
1481 | return 'd'; | |
1482 | case VFP_CPRC_VEC128: | |
1483 | return 'q'; | |
1484 | default: | |
1485 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
1486 | (int) b); | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | /* Determine whether T may be part of a candidate for passing and | |
1491 | returning in VFP registers, ignoring the limit on the total number | |
1492 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
1493 | classification of the first valid component found; if it is not | |
1494 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
1495 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
1496 | for passing and returning in VFP registers, a type differently | |
1497 | classified from *BASE_TYPE, or two types differently classified | |
1498 | from each other, return -1, otherwise return the total number of | |
1499 | base-type elements found (possibly 0 in an empty structure or | |
1500 | array). Vectors and complex types are not currently supported, | |
1501 | matching the generic AAPCS support. */ | |
1502 | ||
1503 | static int | |
1504 | arm_vfp_cprc_sub_candidate (struct type *t, | |
1505 | enum arm_vfp_cprc_base_type *base_type) | |
1506 | { | |
1507 | t = check_typedef (t); | |
1508 | switch (TYPE_CODE (t)) | |
1509 | { | |
1510 | case TYPE_CODE_FLT: | |
1511 | switch (TYPE_LENGTH (t)) | |
1512 | { | |
1513 | case 4: | |
1514 | if (*base_type == VFP_CPRC_UNKNOWN) | |
1515 | *base_type = VFP_CPRC_SINGLE; | |
1516 | else if (*base_type != VFP_CPRC_SINGLE) | |
1517 | return -1; | |
1518 | return 1; | |
1519 | ||
1520 | case 8: | |
1521 | if (*base_type == VFP_CPRC_UNKNOWN) | |
1522 | *base_type = VFP_CPRC_DOUBLE; | |
1523 | else if (*base_type != VFP_CPRC_DOUBLE) | |
1524 | return -1; | |
1525 | return 1; | |
1526 | ||
1527 | default: | |
1528 | return -1; | |
1529 | } | |
1530 | break; | |
1531 | ||
1532 | case TYPE_CODE_ARRAY: | |
1533 | { | |
1534 | int count; | |
1535 | unsigned unitlen; | |
1536 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); | |
1537 | if (count == -1) | |
1538 | return -1; | |
1539 | if (TYPE_LENGTH (t) == 0) | |
1540 | { | |
1541 | gdb_assert (count == 0); | |
1542 | return 0; | |
1543 | } | |
1544 | else if (count == 0) | |
1545 | return -1; | |
1546 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1547 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
1548 | return TYPE_LENGTH (t) / unitlen; | |
1549 | } | |
1550 | break; | |
1551 | ||
1552 | case TYPE_CODE_STRUCT: | |
1553 | { | |
1554 | int count = 0; | |
1555 | unsigned unitlen; | |
1556 | int i; | |
1557 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
1558 | { | |
1559 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
1560 | base_type); | |
1561 | if (sub_count == -1) | |
1562 | return -1; | |
1563 | count += sub_count; | |
1564 | } | |
1565 | if (TYPE_LENGTH (t) == 0) | |
1566 | { | |
1567 | gdb_assert (count == 0); | |
1568 | return 0; | |
1569 | } | |
1570 | else if (count == 0) | |
1571 | return -1; | |
1572 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1573 | if (TYPE_LENGTH (t) != unitlen * count) | |
1574 | return -1; | |
1575 | return count; | |
1576 | } | |
1577 | ||
1578 | case TYPE_CODE_UNION: | |
1579 | { | |
1580 | int count = 0; | |
1581 | unsigned unitlen; | |
1582 | int i; | |
1583 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
1584 | { | |
1585 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), | |
1586 | base_type); | |
1587 | if (sub_count == -1) | |
1588 | return -1; | |
1589 | count = (count > sub_count ? count : sub_count); | |
1590 | } | |
1591 | if (TYPE_LENGTH (t) == 0) | |
1592 | { | |
1593 | gdb_assert (count == 0); | |
1594 | return 0; | |
1595 | } | |
1596 | else if (count == 0) | |
1597 | return -1; | |
1598 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
1599 | if (TYPE_LENGTH (t) != unitlen * count) | |
1600 | return -1; | |
1601 | return count; | |
1602 | } | |
1603 | ||
1604 | default: | |
1605 | break; | |
1606 | } | |
1607 | ||
1608 | return -1; | |
1609 | } | |
1610 | ||
1611 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
1612 | if passed to or returned from a non-variadic function with the VFP | |
1613 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
1614 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
1615 | elements of that base type before returning. */ | |
1616 | ||
1617 | static int | |
1618 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
1619 | int *count) | |
1620 | { | |
1621 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
1622 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
1623 | if (c <= 0 || c > 4) | |
1624 | return 0; | |
1625 | *base_type = b; | |
1626 | *count = c; | |
1627 | return 1; | |
1628 | } | |
1629 | ||
1630 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
1631 | returning values from a function of type FUNC_TYPE, 0 | |
1632 | otherwise. */ | |
1633 | ||
1634 | static int | |
1635 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
1636 | { | |
1637 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1638 | /* Variadic functions always use the base ABI. Assume that functions | |
1639 | without debug info are not variadic. */ | |
1640 | if (func_type && TYPE_VARARGS (check_typedef (func_type))) | |
1641 | return 0; | |
1642 | /* The VFP ABI is only supported as a variant of AAPCS. */ | |
1643 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
1644 | return 0; | |
1645 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; | |
1646 | } | |
1647 | ||
1648 | /* We currently only support passing parameters in integer registers, which | |
1649 | conforms with GCC's default model, and VFP argument passing following | |
1650 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
1651 | we should probably support some of them based on the selected ABI. */ |
1652 | ||
1653 | static CORE_ADDR | |
7d9b040b | 1654 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1655 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1656 | struct value **args, CORE_ADDR sp, int struct_return, | |
1657 | CORE_ADDR struct_addr) | |
2dd604e7 | 1658 | { |
e17a4113 | 1659 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
1660 | int argnum; |
1661 | int argreg; | |
1662 | int nstack; | |
1663 | struct stack_item *si = NULL; | |
90445bd3 DJ |
1664 | int use_vfp_abi; |
1665 | struct type *ftype; | |
1666 | unsigned vfp_regs_free = (1 << 16) - 1; | |
1667 | ||
1668 | /* Determine the type of this function and whether the VFP ABI | |
1669 | applies. */ | |
1670 | ftype = check_typedef (value_type (function)); | |
1671 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) | |
1672 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); | |
1673 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 1674 | |
6a65450a AC |
1675 | /* Set the return address. For the ARM, the return breakpoint is |
1676 | always at BP_ADDR. */ | |
9dca5578 DJ |
1677 | if (arm_pc_is_thumb (bp_addr)) |
1678 | bp_addr |= 1; | |
6a65450a | 1679 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1680 | |
1681 | /* Walk through the list of args and determine how large a temporary | |
1682 | stack is required. Need to take care here as structs may be | |
1683 | passed on the stack, and we have to to push them. */ | |
1684 | nstack = 0; | |
1685 | ||
1686 | argreg = ARM_A1_REGNUM; | |
1687 | nstack = 0; | |
1688 | ||
2dd604e7 RE |
1689 | /* The struct_return pointer occupies the first parameter |
1690 | passing register. */ | |
1691 | if (struct_return) | |
1692 | { | |
1693 | if (arm_debug) | |
5af949e3 | 1694 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 1695 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 1696 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
1697 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
1698 | argreg++; | |
1699 | } | |
1700 | ||
1701 | for (argnum = 0; argnum < nargs; argnum++) | |
1702 | { | |
1703 | int len; | |
1704 | struct type *arg_type; | |
1705 | struct type *target_type; | |
1706 | enum type_code typecode; | |
0fd88904 | 1707 | bfd_byte *val; |
2af48f68 | 1708 | int align; |
90445bd3 DJ |
1709 | enum arm_vfp_cprc_base_type vfp_base_type; |
1710 | int vfp_base_count; | |
1711 | int may_use_core_reg = 1; | |
2dd604e7 | 1712 | |
df407dfe | 1713 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1714 | len = TYPE_LENGTH (arg_type); |
1715 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1716 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1717 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1718 | |
2af48f68 PB |
1719 | align = arm_type_align (arg_type); |
1720 | /* Round alignment up to a whole number of words. */ | |
1721 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1722 | /* Different ABIs have different maximum alignments. */ | |
1723 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1724 | { | |
1725 | /* The APCS ABI only requires word alignment. */ | |
1726 | align = INT_REGISTER_SIZE; | |
1727 | } | |
1728 | else | |
1729 | { | |
1730 | /* The AAPCS requires at most doubleword alignment. */ | |
1731 | if (align > INT_REGISTER_SIZE * 2) | |
1732 | align = INT_REGISTER_SIZE * 2; | |
1733 | } | |
1734 | ||
90445bd3 DJ |
1735 | if (use_vfp_abi |
1736 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
1737 | &vfp_base_count)) | |
1738 | { | |
1739 | int regno; | |
1740 | int unit_length; | |
1741 | int shift; | |
1742 | unsigned mask; | |
1743 | ||
1744 | /* Because this is a CPRC it cannot go in a core register or | |
1745 | cause a core register to be skipped for alignment. | |
1746 | Either it goes in VFP registers and the rest of this loop | |
1747 | iteration is skipped for this argument, or it goes on the | |
1748 | stack (and the stack alignment code is correct for this | |
1749 | case). */ | |
1750 | may_use_core_reg = 0; | |
1751 | ||
1752 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
1753 | shift = unit_length / 4; | |
1754 | mask = (1 << (shift * vfp_base_count)) - 1; | |
1755 | for (regno = 0; regno < 16; regno += shift) | |
1756 | if (((vfp_regs_free >> regno) & mask) == mask) | |
1757 | break; | |
1758 | ||
1759 | if (regno < 16) | |
1760 | { | |
1761 | int reg_char; | |
1762 | int reg_scaled; | |
1763 | int i; | |
1764 | ||
1765 | vfp_regs_free &= ~(mask << regno); | |
1766 | reg_scaled = regno / shift; | |
1767 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
1768 | for (i = 0; i < vfp_base_count; i++) | |
1769 | { | |
1770 | char name_buf[4]; | |
1771 | int regnum; | |
58d6951d DJ |
1772 | if (reg_char == 'q') |
1773 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 1774 | val + i * unit_length); |
58d6951d DJ |
1775 | else |
1776 | { | |
1777 | sprintf (name_buf, "%c%d", reg_char, reg_scaled + i); | |
1778 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
1779 | strlen (name_buf)); | |
1780 | regcache_cooked_write (regcache, regnum, | |
1781 | val + i * unit_length); | |
1782 | } | |
90445bd3 DJ |
1783 | } |
1784 | continue; | |
1785 | } | |
1786 | else | |
1787 | { | |
1788 | /* This CPRC could not go in VFP registers, so all VFP | |
1789 | registers are now marked as used. */ | |
1790 | vfp_regs_free = 0; | |
1791 | } | |
1792 | } | |
1793 | ||
2af48f68 PB |
1794 | /* Push stack padding for dowubleword alignment. */ |
1795 | if (nstack & (align - 1)) | |
1796 | { | |
1797 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1798 | nstack += INT_REGISTER_SIZE; | |
1799 | } | |
1800 | ||
1801 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
1802 | if (may_use_core_reg |
1803 | && argreg <= ARM_LAST_ARG_REGNUM | |
2af48f68 PB |
1804 | && align > INT_REGISTER_SIZE |
1805 | && argreg & 1) | |
1806 | argreg++; | |
1807 | ||
2dd604e7 RE |
1808 | /* If the argument is a pointer to a function, and it is a |
1809 | Thumb function, create a LOCAL copy of the value and set | |
1810 | the THUMB bit in it. */ | |
1811 | if (TYPE_CODE_PTR == typecode | |
1812 | && target_type != NULL | |
1813 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1814 | { | |
e17a4113 | 1815 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
2dd604e7 RE |
1816 | if (arm_pc_is_thumb (regval)) |
1817 | { | |
1818 | val = alloca (len); | |
e17a4113 UW |
1819 | store_unsigned_integer (val, len, byte_order, |
1820 | MAKE_THUMB_ADDR (regval)); | |
2dd604e7 RE |
1821 | } |
1822 | } | |
1823 | ||
1824 | /* Copy the argument to general registers or the stack in | |
1825 | register-sized pieces. Large arguments are split between | |
1826 | registers and stack. */ | |
1827 | while (len > 0) | |
1828 | { | |
f0c9063c | 1829 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 | 1830 | |
90445bd3 | 1831 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
1832 | { |
1833 | /* The argument is being passed in a general purpose | |
1834 | register. */ | |
e17a4113 UW |
1835 | CORE_ADDR regval |
1836 | = extract_unsigned_integer (val, partial_len, byte_order); | |
1837 | if (byte_order == BFD_ENDIAN_BIG) | |
8bf8793c | 1838 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
1839 | if (arm_debug) |
1840 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
1841 | argnum, |
1842 | gdbarch_register_name | |
2af46ca0 | 1843 | (gdbarch, argreg), |
f0c9063c | 1844 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
1845 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1846 | argreg++; | |
1847 | } | |
1848 | else | |
1849 | { | |
1850 | /* Push the arguments onto the stack. */ | |
1851 | if (arm_debug) | |
1852 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1853 | argnum, nstack); | |
f0c9063c UW |
1854 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
1855 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
1856 | } |
1857 | ||
1858 | len -= partial_len; | |
1859 | val += partial_len; | |
1860 | } | |
1861 | } | |
1862 | /* If we have an odd number of words to push, then decrement the stack | |
1863 | by one word now, so first stack argument will be dword aligned. */ | |
1864 | if (nstack & 4) | |
1865 | sp -= 4; | |
1866 | ||
1867 | while (si) | |
1868 | { | |
1869 | sp -= si->len; | |
1870 | write_memory (sp, si->data, si->len); | |
1871 | si = pop_stack_item (si); | |
1872 | } | |
1873 | ||
1874 | /* Finally, update teh SP register. */ | |
1875 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1876 | ||
1877 | return sp; | |
1878 | } | |
1879 | ||
f53f0d0b PB |
1880 | |
1881 | /* Always align the frame to an 8-byte boundary. This is required on | |
1882 | some platforms and harmless on the rest. */ | |
1883 | ||
1884 | static CORE_ADDR | |
1885 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1886 | { | |
1887 | /* Align the stack to eight bytes. */ | |
1888 | return sp & ~ (CORE_ADDR) 7; | |
1889 | } | |
1890 | ||
c906108c | 1891 | static void |
ed9a39eb | 1892 | print_fpu_flags (int flags) |
c906108c | 1893 | { |
c5aa993b JM |
1894 | if (flags & (1 << 0)) |
1895 | fputs ("IVO ", stdout); | |
1896 | if (flags & (1 << 1)) | |
1897 | fputs ("DVZ ", stdout); | |
1898 | if (flags & (1 << 2)) | |
1899 | fputs ("OFL ", stdout); | |
1900 | if (flags & (1 << 3)) | |
1901 | fputs ("UFL ", stdout); | |
1902 | if (flags & (1 << 4)) | |
1903 | fputs ("INX ", stdout); | |
1904 | putchar ('\n'); | |
c906108c SS |
1905 | } |
1906 | ||
5e74b15c RE |
1907 | /* Print interesting information about the floating point processor |
1908 | (if present) or emulator. */ | |
34e8f22d | 1909 | static void |
d855c300 | 1910 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1911 | struct frame_info *frame, const char *args) |
c906108c | 1912 | { |
9c9acae0 | 1913 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
1914 | int type; |
1915 | ||
1916 | type = (status >> 24) & 127; | |
edefbb7c AC |
1917 | if (status & (1 << 31)) |
1918 | printf (_("Hardware FPU type %d\n"), type); | |
1919 | else | |
1920 | printf (_("Software FPU type %d\n"), type); | |
1921 | /* i18n: [floating point unit] mask */ | |
1922 | fputs (_("mask: "), stdout); | |
c5aa993b | 1923 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1924 | /* i18n: [floating point unit] flags */ |
1925 | fputs (_("flags: "), stdout); | |
c5aa993b | 1926 | print_fpu_flags (status); |
c906108c SS |
1927 | } |
1928 | ||
27067745 UW |
1929 | /* Construct the ARM extended floating point type. */ |
1930 | static struct type * | |
1931 | arm_ext_type (struct gdbarch *gdbarch) | |
1932 | { | |
1933 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1934 | ||
1935 | if (!tdep->arm_ext_type) | |
1936 | tdep->arm_ext_type | |
e9bb382b | 1937 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
1938 | floatformats_arm_ext); |
1939 | ||
1940 | return tdep->arm_ext_type; | |
1941 | } | |
1942 | ||
58d6951d DJ |
1943 | static struct type * |
1944 | arm_neon_double_type (struct gdbarch *gdbarch) | |
1945 | { | |
1946 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1947 | ||
1948 | if (tdep->neon_double_type == NULL) | |
1949 | { | |
1950 | struct type *t, *elem; | |
1951 | ||
1952 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
1953 | TYPE_CODE_UNION); | |
1954 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1955 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
1956 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1957 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
1958 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1959 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
1960 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1961 | append_composite_type_field (t, "u64", elem); | |
1962 | elem = builtin_type (gdbarch)->builtin_float; | |
1963 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
1964 | elem = builtin_type (gdbarch)->builtin_double; | |
1965 | append_composite_type_field (t, "f64", elem); | |
1966 | ||
1967 | TYPE_VECTOR (t) = 1; | |
1968 | TYPE_NAME (t) = "neon_d"; | |
1969 | tdep->neon_double_type = t; | |
1970 | } | |
1971 | ||
1972 | return tdep->neon_double_type; | |
1973 | } | |
1974 | ||
1975 | /* FIXME: The vector types are not correctly ordered on big-endian | |
1976 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
1977 | bits of d0 - regardless of what unit size is being held in d0. So | |
1978 | the offset of the first uint8 in d0 is 7, but the offset of the | |
1979 | first float is 4. This code works as-is for little-endian | |
1980 | targets. */ | |
1981 | ||
1982 | static struct type * | |
1983 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
1984 | { | |
1985 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1986 | ||
1987 | if (tdep->neon_quad_type == NULL) | |
1988 | { | |
1989 | struct type *t, *elem; | |
1990 | ||
1991 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
1992 | TYPE_CODE_UNION); | |
1993 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1994 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
1995 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1996 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
1997 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1998 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
1999 | elem = builtin_type (gdbarch)->builtin_uint64; | |
2000 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
2001 | elem = builtin_type (gdbarch)->builtin_float; | |
2002 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
2003 | elem = builtin_type (gdbarch)->builtin_double; | |
2004 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
2005 | ||
2006 | TYPE_VECTOR (t) = 1; | |
2007 | TYPE_NAME (t) = "neon_q"; | |
2008 | tdep->neon_quad_type = t; | |
2009 | } | |
2010 | ||
2011 | return tdep->neon_quad_type; | |
2012 | } | |
2013 | ||
34e8f22d RE |
2014 | /* Return the GDB type object for the "standard" data type of data in |
2015 | register N. */ | |
2016 | ||
2017 | static struct type * | |
7a5ea0d4 | 2018 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 2019 | { |
58d6951d DJ |
2020 | int num_regs = gdbarch_num_regs (gdbarch); |
2021 | ||
2022 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
2023 | && regnum >= num_regs && regnum < num_regs + 32) | |
2024 | return builtin_type (gdbarch)->builtin_float; | |
2025 | ||
2026 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
2027 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) | |
2028 | return arm_neon_quad_type (gdbarch); | |
2029 | ||
2030 | /* If the target description has register information, we are only | |
2031 | in this function so that we can override the types of | |
2032 | double-precision registers for NEON. */ | |
2033 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
2034 | { | |
2035 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
2036 | ||
2037 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
2038 | && TYPE_CODE (t) == TYPE_CODE_FLT | |
2039 | && gdbarch_tdep (gdbarch)->have_neon) | |
2040 | return arm_neon_double_type (gdbarch); | |
2041 | else | |
2042 | return t; | |
2043 | } | |
2044 | ||
34e8f22d | 2045 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d DJ |
2046 | { |
2047 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) | |
2048 | return builtin_type (gdbarch)->builtin_void; | |
2049 | ||
2050 | return arm_ext_type (gdbarch); | |
2051 | } | |
e4c16157 | 2052 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 2053 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 2054 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 2055 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
2056 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
2057 | /* These registers are only supported on targets which supply | |
2058 | an XML description. */ | |
df4df182 | 2059 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 2060 | else |
df4df182 | 2061 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
2062 | } |
2063 | ||
ff6f572f DJ |
2064 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
2065 | number. */ | |
2066 | ||
2067 | static int | |
d3f73121 | 2068 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
2069 | { |
2070 | /* Core integer regs. */ | |
2071 | if (reg >= 0 && reg <= 15) | |
2072 | return reg; | |
2073 | ||
2074 | /* Legacy FPA encoding. These were once used in a way which | |
2075 | overlapped with VFP register numbering, so their use is | |
2076 | discouraged, but GDB doesn't support the ARM toolchain | |
2077 | which used them for VFP. */ | |
2078 | if (reg >= 16 && reg <= 23) | |
2079 | return ARM_F0_REGNUM + reg - 16; | |
2080 | ||
2081 | /* New assignments for the FPA registers. */ | |
2082 | if (reg >= 96 && reg <= 103) | |
2083 | return ARM_F0_REGNUM + reg - 96; | |
2084 | ||
2085 | /* WMMX register assignments. */ | |
2086 | if (reg >= 104 && reg <= 111) | |
2087 | return ARM_WCGR0_REGNUM + reg - 104; | |
2088 | ||
2089 | if (reg >= 112 && reg <= 127) | |
2090 | return ARM_WR0_REGNUM + reg - 112; | |
2091 | ||
2092 | if (reg >= 192 && reg <= 199) | |
2093 | return ARM_WC0_REGNUM + reg - 192; | |
2094 | ||
58d6951d DJ |
2095 | /* VFP v2 registers. A double precision value is actually |
2096 | in d1 rather than s2, but the ABI only defines numbering | |
2097 | for the single precision registers. This will "just work" | |
2098 | in GDB for little endian targets (we'll read eight bytes, | |
2099 | starting in s0 and then progressing to s1), but will be | |
2100 | reversed on big endian targets with VFP. This won't | |
2101 | be a problem for the new Neon quad registers; you're supposed | |
2102 | to use DW_OP_piece for those. */ | |
2103 | if (reg >= 64 && reg <= 95) | |
2104 | { | |
2105 | char name_buf[4]; | |
2106 | ||
2107 | sprintf (name_buf, "s%d", reg - 64); | |
2108 | return user_reg_map_name_to_regnum (gdbarch, name_buf, | |
2109 | strlen (name_buf)); | |
2110 | } | |
2111 | ||
2112 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
2113 | registers, except that it now describes d0 instead of s0. */ | |
2114 | if (reg >= 256 && reg <= 287) | |
2115 | { | |
2116 | char name_buf[4]; | |
2117 | ||
2118 | sprintf (name_buf, "d%d", reg - 256); | |
2119 | return user_reg_map_name_to_regnum (gdbarch, name_buf, | |
2120 | strlen (name_buf)); | |
2121 | } | |
2122 | ||
ff6f572f DJ |
2123 | return -1; |
2124 | } | |
2125 | ||
26216b98 AC |
2126 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
2127 | static int | |
e7faf938 | 2128 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
2129 | { |
2130 | int reg = regnum; | |
e7faf938 | 2131 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 2132 | |
ff6f572f DJ |
2133 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
2134 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
2135 | ||
2136 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
2137 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
2138 | ||
2139 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
2140 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
2141 | ||
26216b98 AC |
2142 | if (reg < NUM_GREGS) |
2143 | return SIM_ARM_R0_REGNUM + reg; | |
2144 | reg -= NUM_GREGS; | |
2145 | ||
2146 | if (reg < NUM_FREGS) | |
2147 | return SIM_ARM_FP0_REGNUM + reg; | |
2148 | reg -= NUM_FREGS; | |
2149 | ||
2150 | if (reg < NUM_SREGS) | |
2151 | return SIM_ARM_FPS_REGNUM + reg; | |
2152 | reg -= NUM_SREGS; | |
2153 | ||
edefbb7c | 2154 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 2155 | } |
34e8f22d | 2156 | |
a37b3cc0 AC |
2157 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
2158 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
2159 | It is thought that this is is the floating-point register format on | |
2160 | little-endian systems. */ | |
c906108c | 2161 | |
ed9a39eb | 2162 | static void |
b508a996 | 2163 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 2164 | void *dbl, int endianess) |
c906108c | 2165 | { |
a37b3cc0 | 2166 | DOUBLEST d; |
be8626e0 MD |
2167 | |
2168 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
2169 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
2170 | else | |
2171 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
2172 | ptr, &d); | |
b508a996 | 2173 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
2174 | } |
2175 | ||
34e8f22d | 2176 | static void |
be8626e0 MD |
2177 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
2178 | int endianess) | |
c906108c | 2179 | { |
a37b3cc0 | 2180 | DOUBLEST d; |
be8626e0 | 2181 | |
b508a996 | 2182 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 2183 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
2184 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
2185 | else | |
2186 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
2187 | &d, dbl); | |
c906108c | 2188 | } |
ed9a39eb | 2189 | |
c906108c | 2190 | static int |
ed9a39eb | 2191 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
2192 | { |
2193 | if (cond == INST_AL || cond == INST_NV) | |
2194 | return 1; | |
2195 | ||
2196 | switch (cond) | |
2197 | { | |
2198 | case INST_EQ: | |
2199 | return ((status_reg & FLAG_Z) != 0); | |
2200 | case INST_NE: | |
2201 | return ((status_reg & FLAG_Z) == 0); | |
2202 | case INST_CS: | |
2203 | return ((status_reg & FLAG_C) != 0); | |
2204 | case INST_CC: | |
2205 | return ((status_reg & FLAG_C) == 0); | |
2206 | case INST_MI: | |
2207 | return ((status_reg & FLAG_N) != 0); | |
2208 | case INST_PL: | |
2209 | return ((status_reg & FLAG_N) == 0); | |
2210 | case INST_VS: | |
2211 | return ((status_reg & FLAG_V) != 0); | |
2212 | case INST_VC: | |
2213 | return ((status_reg & FLAG_V) == 0); | |
2214 | case INST_HI: | |
2215 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
2216 | case INST_LS: | |
2217 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
2218 | case INST_GE: | |
2219 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
2220 | case INST_LT: | |
2221 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
2222 | case INST_GT: | |
f8bf5763 PM |
2223 | return (((status_reg & FLAG_Z) == 0) |
2224 | && (((status_reg & FLAG_N) == 0) | |
2225 | == ((status_reg & FLAG_V) == 0))); | |
c906108c | 2226 | case INST_LE: |
f8bf5763 PM |
2227 | return (((status_reg & FLAG_Z) != 0) |
2228 | || (((status_reg & FLAG_N) == 0) | |
2229 | != ((status_reg & FLAG_V) == 0))); | |
c906108c SS |
2230 | } |
2231 | return 1; | |
2232 | } | |
2233 | ||
9512d7fd | 2234 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
2235 | #define submask(x) ((1L << ((x) + 1)) - 1) |
2236 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
2237 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
2238 | #define sbits(obj,st,fn) \ | |
2239 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
2240 | #define BranchDest(addr,instr) \ | |
2241 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
2242 | #define ARM_PC_32 1 | |
2243 | ||
2244 | static unsigned long | |
0b1b3e42 UW |
2245 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
2246 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
2247 | { |
2248 | unsigned long res, shift; | |
2249 | int rm = bits (inst, 0, 3); | |
2250 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
2251 | |
2252 | if (bit (inst, 4)) | |
c906108c SS |
2253 | { |
2254 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
2255 | shift = (rs == 15 ? pc_val + 8 |
2256 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
2257 | } |
2258 | else | |
2259 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
2260 | |
2261 | res = (rm == 15 | |
c906108c | 2262 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 2263 | + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 2264 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
2265 | |
2266 | switch (shifttype) | |
2267 | { | |
c5aa993b | 2268 | case 0: /* LSL */ |
c906108c SS |
2269 | res = shift >= 32 ? 0 : res << shift; |
2270 | break; | |
c5aa993b JM |
2271 | |
2272 | case 1: /* LSR */ | |
c906108c SS |
2273 | res = shift >= 32 ? 0 : res >> shift; |
2274 | break; | |
2275 | ||
c5aa993b JM |
2276 | case 2: /* ASR */ |
2277 | if (shift >= 32) | |
2278 | shift = 31; | |
c906108c SS |
2279 | res = ((res & 0x80000000L) |
2280 | ? ~((~res) >> shift) : res >> shift); | |
2281 | break; | |
2282 | ||
c5aa993b | 2283 | case 3: /* ROR/RRX */ |
c906108c SS |
2284 | shift &= 31; |
2285 | if (shift == 0) | |
2286 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
2287 | else | |
c5aa993b | 2288 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
2289 | break; |
2290 | } | |
2291 | ||
2292 | return res & 0xffffffff; | |
2293 | } | |
2294 | ||
c906108c SS |
2295 | /* Return number of 1-bits in VAL. */ |
2296 | ||
2297 | static int | |
ed9a39eb | 2298 | bitcount (unsigned long val) |
c906108c SS |
2299 | { |
2300 | int nbits; | |
2301 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 2302 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
2303 | return nbits; |
2304 | } | |
2305 | ||
177321bd DJ |
2306 | /* Return the size in bytes of the complete Thumb instruction whose |
2307 | first halfword is INST1. */ | |
2308 | ||
2309 | static int | |
2310 | thumb_insn_size (unsigned short inst1) | |
2311 | { | |
2312 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) | |
2313 | return 4; | |
2314 | else | |
2315 | return 2; | |
2316 | } | |
2317 | ||
2318 | static int | |
2319 | thumb_advance_itstate (unsigned int itstate) | |
2320 | { | |
2321 | /* Preserve IT[7:5], the first three bits of the condition. Shift | |
2322 | the upcoming condition flags left by one bit. */ | |
2323 | itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f); | |
2324 | ||
2325 | /* If we have finished the IT block, clear the state. */ | |
2326 | if ((itstate & 0x0f) == 0) | |
2327 | itstate = 0; | |
2328 | ||
2329 | return itstate; | |
2330 | } | |
2331 | ||
2332 | /* Find the next PC after the current instruction executes. In some | |
2333 | cases we can not statically determine the answer (see the IT state | |
2334 | handling in this function); in that case, a breakpoint may be | |
2335 | inserted in addition to the returned PC, which will be used to set | |
2336 | another breakpoint by our caller. */ | |
2337 | ||
ad527d2e | 2338 | static CORE_ADDR |
50e98be4 | 2339 | thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt) |
c906108c | 2340 | { |
2af46ca0 | 2341 | struct gdbarch *gdbarch = get_frame_arch (frame); |
177321bd | 2342 | struct address_space *aspace = get_frame_address_space (frame); |
e17a4113 UW |
2343 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2344 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c5aa993b | 2345 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
e17a4113 | 2346 | unsigned short inst1; |
94c30b78 | 2347 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c | 2348 | unsigned long offset; |
177321bd | 2349 | ULONGEST status, itstate; |
c906108c | 2350 | |
50e98be4 DJ |
2351 | nextpc = MAKE_THUMB_ADDR (nextpc); |
2352 | pc_val = MAKE_THUMB_ADDR (pc_val); | |
2353 | ||
e17a4113 | 2354 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); |
9d4fde75 | 2355 | |
9dca5578 DJ |
2356 | /* Thumb-2 conditional execution support. There are eight bits in |
2357 | the CPSR which describe conditional execution state. Once | |
2358 | reconstructed (they're in a funny order), the low five bits | |
2359 | describe the low bit of the condition for each instruction and | |
2360 | how many instructions remain. The high three bits describe the | |
2361 | base condition. One of the low four bits will be set if an IT | |
2362 | block is active. These bits read as zero on earlier | |
2363 | processors. */ | |
2364 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
177321bd | 2365 | itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); |
9dca5578 | 2366 | |
177321bd DJ |
2367 | /* If-Then handling. On GNU/Linux, where this routine is used, we |
2368 | use an undefined instruction as a breakpoint. Unlike BKPT, IT | |
2369 | can disable execution of the undefined instruction. So we might | |
2370 | miss the breakpoint if we set it on a skipped conditional | |
2371 | instruction. Because conditional instructions can change the | |
2372 | flags, affecting the execution of further instructions, we may | |
2373 | need to set two breakpoints. */ | |
9dca5578 | 2374 | |
177321bd DJ |
2375 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL) |
2376 | { | |
2377 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
2378 | { | |
2379 | /* An IT instruction. Because this instruction does not | |
2380 | modify the flags, we can accurately predict the next | |
2381 | executed instruction. */ | |
2382 | itstate = inst1 & 0x00ff; | |
2383 | pc += thumb_insn_size (inst1); | |
2384 | ||
2385 | while (itstate != 0 && ! condition_true (itstate >> 4, status)) | |
2386 | { | |
2387 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); | |
2388 | pc += thumb_insn_size (inst1); | |
2389 | itstate = thumb_advance_itstate (itstate); | |
2390 | } | |
2391 | ||
50e98be4 | 2392 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
2393 | } |
2394 | else if (itstate != 0) | |
2395 | { | |
2396 | /* We are in a conditional block. Check the condition. */ | |
2397 | if (! condition_true (itstate >> 4, status)) | |
2398 | { | |
2399 | /* Advance to the next executed instruction. */ | |
2400 | pc += thumb_insn_size (inst1); | |
2401 | itstate = thumb_advance_itstate (itstate); | |
2402 | ||
2403 | while (itstate != 0 && ! condition_true (itstate >> 4, status)) | |
2404 | { | |
2405 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); | |
2406 | pc += thumb_insn_size (inst1); | |
2407 | itstate = thumb_advance_itstate (itstate); | |
2408 | } | |
2409 | ||
50e98be4 | 2410 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
2411 | } |
2412 | else if ((itstate & 0x0f) == 0x08) | |
2413 | { | |
2414 | /* This is the last instruction of the conditional | |
2415 | block, and it is executed. We can handle it normally | |
2416 | because the following instruction is not conditional, | |
2417 | and we must handle it normally because it is | |
2418 | permitted to branch. Fall through. */ | |
2419 | } | |
2420 | else | |
2421 | { | |
2422 | int cond_negated; | |
2423 | ||
2424 | /* There are conditional instructions after this one. | |
2425 | If this instruction modifies the flags, then we can | |
2426 | not predict what the next executed instruction will | |
2427 | be. Fortunately, this instruction is architecturally | |
2428 | forbidden to branch; we know it will fall through. | |
2429 | Start by skipping past it. */ | |
2430 | pc += thumb_insn_size (inst1); | |
2431 | itstate = thumb_advance_itstate (itstate); | |
2432 | ||
2433 | /* Set a breakpoint on the following instruction. */ | |
2434 | gdb_assert ((itstate & 0x0f) != 0); | |
50e98be4 DJ |
2435 | if (insert_bkpt) |
2436 | insert_single_step_breakpoint (gdbarch, aspace, pc); | |
177321bd DJ |
2437 | cond_negated = (itstate >> 4) & 1; |
2438 | ||
2439 | /* Skip all following instructions with the same | |
2440 | condition. If there is a later instruction in the IT | |
2441 | block with the opposite condition, set the other | |
2442 | breakpoint there. If not, then set a breakpoint on | |
2443 | the instruction after the IT block. */ | |
2444 | do | |
2445 | { | |
2446 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); | |
2447 | pc += thumb_insn_size (inst1); | |
2448 | itstate = thumb_advance_itstate (itstate); | |
2449 | } | |
2450 | while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated); | |
2451 | ||
50e98be4 | 2452 | return MAKE_THUMB_ADDR (pc); |
177321bd DJ |
2453 | } |
2454 | } | |
2455 | } | |
2456 | else if (itstate & 0x0f) | |
9dca5578 DJ |
2457 | { |
2458 | /* We are in a conditional block. Check the condition. */ | |
177321bd | 2459 | int cond = itstate >> 4; |
9dca5578 DJ |
2460 | |
2461 | if (! condition_true (cond, status)) | |
2462 | { | |
2463 | /* Advance to the next instruction. All the 32-bit | |
2464 | instructions share a common prefix. */ | |
2465 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) | |
50e98be4 | 2466 | return MAKE_THUMB_ADDR (pc + 4); |
9dca5578 | 2467 | else |
50e98be4 | 2468 | return MAKE_THUMB_ADDR (pc + 2); |
9dca5578 | 2469 | } |
177321bd DJ |
2470 | |
2471 | /* Otherwise, handle the instruction normally. */ | |
9dca5578 DJ |
2472 | } |
2473 | ||
c906108c SS |
2474 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
2475 | { | |
2476 | CORE_ADDR sp; | |
2477 | ||
2478 | /* Fetch the saved PC from the stack. It's stored above | |
2479 | all of the other registers. */ | |
f0c9063c | 2480 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 2481 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
e17a4113 | 2482 | nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); |
c906108c SS |
2483 | } |
2484 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
2485 | { | |
c5aa993b | 2486 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 2487 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
2488 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
2489 | } | |
2490 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
2491 | { | |
2492 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
2493 | } | |
9dca5578 | 2494 | else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */ |
c906108c | 2495 | { |
e17a4113 UW |
2496 | unsigned short inst2; |
2497 | inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
9dca5578 DJ |
2498 | |
2499 | /* Default to the next instruction. */ | |
2500 | nextpc = pc + 4; | |
50e98be4 | 2501 | nextpc = MAKE_THUMB_ADDR (nextpc); |
9dca5578 DJ |
2502 | |
2503 | if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) | |
2504 | { | |
2505 | /* Branches and miscellaneous control instructions. */ | |
2506 | ||
2507 | if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) | |
2508 | { | |
2509 | /* B, BL, BLX. */ | |
2510 | int j1, j2, imm1, imm2; | |
2511 | ||
2512 | imm1 = sbits (inst1, 0, 10); | |
2513 | imm2 = bits (inst2, 0, 10); | |
2514 | j1 = bit (inst2, 13); | |
2515 | j2 = bit (inst2, 11); | |
2516 | ||
2517 | offset = ((imm1 << 12) + (imm2 << 1)); | |
2518 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
2519 | ||
2520 | nextpc = pc_val + offset; | |
2521 | /* For BLX make sure to clear the low bits. */ | |
2522 | if (bit (inst2, 12) == 0) | |
2523 | nextpc = nextpc & 0xfffffffc; | |
2524 | } | |
2525 | else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) | |
2526 | { | |
2527 | /* SUBS PC, LR, #imm8. */ | |
2528 | nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM); | |
2529 | nextpc -= inst2 & 0x00ff; | |
2530 | } | |
4069ebbe | 2531 | else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) |
9dca5578 DJ |
2532 | { |
2533 | /* Conditional branch. */ | |
2534 | if (condition_true (bits (inst1, 6, 9), status)) | |
2535 | { | |
2536 | int sign, j1, j2, imm1, imm2; | |
2537 | ||
2538 | sign = sbits (inst1, 10, 10); | |
2539 | imm1 = bits (inst1, 0, 5); | |
2540 | imm2 = bits (inst2, 0, 10); | |
2541 | j1 = bit (inst2, 13); | |
2542 | j2 = bit (inst2, 11); | |
2543 | ||
2544 | offset = (sign << 20) + (j2 << 19) + (j1 << 18); | |
2545 | offset += (imm1 << 12) + (imm2 << 1); | |
2546 | ||
2547 | nextpc = pc_val + offset; | |
2548 | } | |
2549 | } | |
2550 | } | |
2551 | else if ((inst1 & 0xfe50) == 0xe810) | |
2552 | { | |
2553 | /* Load multiple or RFE. */ | |
2554 | int rn, offset, load_pc = 1; | |
2555 | ||
2556 | rn = bits (inst1, 0, 3); | |
2557 | if (bit (inst1, 7) && !bit (inst1, 8)) | |
2558 | { | |
2559 | /* LDMIA or POP */ | |
2560 | if (!bit (inst2, 15)) | |
2561 | load_pc = 0; | |
2562 | offset = bitcount (inst2) * 4 - 4; | |
2563 | } | |
2564 | else if (!bit (inst1, 7) && bit (inst1, 8)) | |
2565 | { | |
2566 | /* LDMDB */ | |
2567 | if (!bit (inst2, 15)) | |
2568 | load_pc = 0; | |
2569 | offset = -4; | |
2570 | } | |
2571 | else if (bit (inst1, 7) && bit (inst1, 8)) | |
2572 | { | |
2573 | /* RFEIA */ | |
2574 | offset = 0; | |
2575 | } | |
2576 | else if (!bit (inst1, 7) && !bit (inst1, 8)) | |
2577 | { | |
2578 | /* RFEDB */ | |
2579 | offset = -8; | |
2580 | } | |
2581 | else | |
2582 | load_pc = 0; | |
2583 | ||
2584 | if (load_pc) | |
2585 | { | |
2586 | CORE_ADDR addr = get_frame_register_unsigned (frame, rn); | |
2587 | nextpc = get_frame_memory_unsigned (frame, addr + offset, 4); | |
2588 | } | |
2589 | } | |
2590 | else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) | |
2591 | { | |
2592 | /* MOV PC or MOVS PC. */ | |
2593 | nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); | |
50e98be4 | 2594 | nextpc = MAKE_THUMB_ADDR (nextpc); |
9dca5578 DJ |
2595 | } |
2596 | else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) | |
2597 | { | |
2598 | /* LDR PC. */ | |
2599 | CORE_ADDR base; | |
2600 | int rn, load_pc = 1; | |
2601 | ||
2602 | rn = bits (inst1, 0, 3); | |
2603 | base = get_frame_register_unsigned (frame, rn); | |
2604 | if (rn == 15) | |
2605 | { | |
2606 | base = (base + 4) & ~(CORE_ADDR) 0x3; | |
2607 | if (bit (inst1, 7)) | |
2608 | base += bits (inst2, 0, 11); | |
2609 | else | |
2610 | base -= bits (inst2, 0, 11); | |
2611 | } | |
2612 | else if (bit (inst1, 7)) | |
2613 | base += bits (inst2, 0, 11); | |
2614 | else if (bit (inst2, 11)) | |
2615 | { | |
2616 | if (bit (inst2, 10)) | |
2617 | { | |
2618 | if (bit (inst2, 9)) | |
2619 | base += bits (inst2, 0, 7); | |
2620 | else | |
2621 | base -= bits (inst2, 0, 7); | |
2622 | } | |
2623 | } | |
2624 | else if ((inst2 & 0x0fc0) == 0x0000) | |
2625 | { | |
2626 | int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3); | |
2627 | base += get_frame_register_unsigned (frame, rm) << shift; | |
2628 | } | |
2629 | else | |
2630 | /* Reserved. */ | |
2631 | load_pc = 0; | |
2632 | ||
2633 | if (load_pc) | |
2634 | nextpc = get_frame_memory_unsigned (frame, base, 4); | |
2635 | } | |
2636 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) | |
2637 | { | |
2638 | /* TBB. */ | |
2639 | CORE_ADDR table, offset, length; | |
2640 | ||
2641 | table = get_frame_register_unsigned (frame, bits (inst1, 0, 3)); | |
2642 | offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); | |
2643 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 1); | |
2644 | nextpc = pc_val + length; | |
2645 | } | |
2646 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) | |
2647 | { | |
2648 | /* TBH. */ | |
2649 | CORE_ADDR table, offset, length; | |
2650 | ||
2651 | table = get_frame_register_unsigned (frame, bits (inst1, 0, 3)); | |
2652 | offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3)); | |
2653 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 2); | |
2654 | nextpc = pc_val + length; | |
2655 | } | |
c906108c | 2656 | } |
aa17d93e | 2657 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
2658 | { |
2659 | if (bits (inst1, 3, 6) == 0x0f) | |
2660 | nextpc = pc_val; | |
2661 | else | |
0b1b3e42 | 2662 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 2663 | } |
9dca5578 DJ |
2664 | else if ((inst1 & 0xf500) == 0xb100) |
2665 | { | |
2666 | /* CBNZ or CBZ. */ | |
2667 | int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1); | |
2668 | ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2)); | |
2669 | ||
2670 | if (bit (inst1, 11) && reg != 0) | |
2671 | nextpc = pc_val + imm; | |
2672 | else if (!bit (inst1, 11) && reg == 0) | |
2673 | nextpc = pc_val + imm; | |
2674 | } | |
c906108c SS |
2675 | return nextpc; |
2676 | } | |
2677 | ||
50e98be4 DJ |
2678 | /* Get the raw next address. PC is the current program counter, in |
2679 | FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on | |
2680 | the alternative next instruction if there are two options. | |
2681 | ||
2682 | The value returned has the execution state of the next instruction | |
2683 | encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is | |
2684 | in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory | |
2685 | address. | |
2686 | */ | |
2687 | static CORE_ADDR | |
2688 | arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt) | |
c906108c | 2689 | { |
2af46ca0 | 2690 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
2691 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2692 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c906108c SS |
2693 | unsigned long pc_val; |
2694 | unsigned long this_instr; | |
2695 | unsigned long status; | |
2696 | CORE_ADDR nextpc; | |
2697 | ||
b39cc962 | 2698 | if (arm_frame_is_thumb (frame)) |
50e98be4 | 2699 | return thumb_get_next_pc_raw (frame, pc, insert_bkpt); |
c906108c SS |
2700 | |
2701 | pc_val = (unsigned long) pc; | |
e17a4113 | 2702 | this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); |
9d4fde75 | 2703 | |
0b1b3e42 | 2704 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 2705 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 2706 | |
daddc3c1 DJ |
2707 | if (bits (this_instr, 28, 31) == INST_NV) |
2708 | switch (bits (this_instr, 24, 27)) | |
2709 | { | |
2710 | case 0xa: | |
2711 | case 0xb: | |
2712 | { | |
2713 | /* Branch with Link and change to Thumb. */ | |
2714 | nextpc = BranchDest (pc, this_instr); | |
2715 | nextpc |= bit (this_instr, 24) << 1; | |
50e98be4 | 2716 | nextpc = MAKE_THUMB_ADDR (nextpc); |
daddc3c1 DJ |
2717 | break; |
2718 | } | |
2719 | case 0xc: | |
2720 | case 0xd: | |
2721 | case 0xe: | |
2722 | /* Coprocessor register transfer. */ | |
2723 | if (bits (this_instr, 12, 15) == 15) | |
2724 | error (_("Invalid update to pc in instruction")); | |
2725 | break; | |
2726 | } | |
2727 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
2728 | { |
2729 | switch (bits (this_instr, 24, 27)) | |
2730 | { | |
c5aa993b | 2731 | case 0x0: |
94c30b78 | 2732 | case 0x1: /* data processing */ |
c5aa993b JM |
2733 | case 0x2: |
2734 | case 0x3: | |
c906108c SS |
2735 | { |
2736 | unsigned long operand1, operand2, result = 0; | |
2737 | unsigned long rn; | |
2738 | int c; | |
c5aa993b | 2739 | |
c906108c SS |
2740 | if (bits (this_instr, 12, 15) != 15) |
2741 | break; | |
2742 | ||
2743 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 2744 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 2745 | error (_("Invalid update to pc in instruction")); |
c906108c | 2746 | |
9498281f | 2747 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
2748 | if (bits (this_instr, 4, 27) == 0x12fff1 |
2749 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
2750 | { |
2751 | rn = bits (this_instr, 0, 3); | |
50e98be4 | 2752 | nextpc = (rn == 15) ? pc_val + 8 |
0b1b3e42 | 2753 | : get_frame_register_unsigned (frame, rn); |
9498281f DJ |
2754 | return nextpc; |
2755 | } | |
2756 | ||
c906108c SS |
2757 | /* Multiply into PC */ |
2758 | c = (status & FLAG_C) ? 1 : 0; | |
2759 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
2760 | operand1 = (rn == 15) ? pc_val + 8 |
2761 | : get_frame_register_unsigned (frame, rn); | |
c5aa993b | 2762 | |
c906108c SS |
2763 | if (bit (this_instr, 25)) |
2764 | { | |
2765 | unsigned long immval = bits (this_instr, 0, 7); | |
2766 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
2767 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
2768 | & 0xffffffff; | |
c906108c | 2769 | } |
c5aa993b | 2770 | else /* operand 2 is a shifted register */ |
0b1b3e42 | 2771 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
c5aa993b | 2772 | |
c906108c SS |
2773 | switch (bits (this_instr, 21, 24)) |
2774 | { | |
c5aa993b | 2775 | case 0x0: /*and */ |
c906108c SS |
2776 | result = operand1 & operand2; |
2777 | break; | |
2778 | ||
c5aa993b | 2779 | case 0x1: /*eor */ |
c906108c SS |
2780 | result = operand1 ^ operand2; |
2781 | break; | |
2782 | ||
c5aa993b | 2783 | case 0x2: /*sub */ |
c906108c SS |
2784 | result = operand1 - operand2; |
2785 | break; | |
2786 | ||
c5aa993b | 2787 | case 0x3: /*rsb */ |
c906108c SS |
2788 | result = operand2 - operand1; |
2789 | break; | |
2790 | ||
c5aa993b | 2791 | case 0x4: /*add */ |
c906108c SS |
2792 | result = operand1 + operand2; |
2793 | break; | |
2794 | ||
c5aa993b | 2795 | case 0x5: /*adc */ |
c906108c SS |
2796 | result = operand1 + operand2 + c; |
2797 | break; | |
2798 | ||
c5aa993b | 2799 | case 0x6: /*sbc */ |
c906108c SS |
2800 | result = operand1 - operand2 + c; |
2801 | break; | |
2802 | ||
c5aa993b | 2803 | case 0x7: /*rsc */ |
c906108c SS |
2804 | result = operand2 - operand1 + c; |
2805 | break; | |
2806 | ||
c5aa993b JM |
2807 | case 0x8: |
2808 | case 0x9: | |
2809 | case 0xa: | |
2810 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
2811 | result = (unsigned long) nextpc; |
2812 | break; | |
2813 | ||
c5aa993b | 2814 | case 0xc: /*orr */ |
c906108c SS |
2815 | result = operand1 | operand2; |
2816 | break; | |
2817 | ||
c5aa993b | 2818 | case 0xd: /*mov */ |
c906108c SS |
2819 | /* Always step into a function. */ |
2820 | result = operand2; | |
c5aa993b | 2821 | break; |
c906108c | 2822 | |
c5aa993b | 2823 | case 0xe: /*bic */ |
c906108c SS |
2824 | result = operand1 & ~operand2; |
2825 | break; | |
2826 | ||
c5aa993b | 2827 | case 0xf: /*mvn */ |
c906108c SS |
2828 | result = ~operand2; |
2829 | break; | |
2830 | } | |
c906108c | 2831 | |
50e98be4 DJ |
2832 | /* In 26-bit APCS the bottom two bits of the result are |
2833 | ignored, and we always end up in ARM state. */ | |
2834 | if (!arm_apcs_32) | |
2835 | nextpc = arm_addr_bits_remove (gdbarch, result); | |
2836 | else | |
2837 | nextpc = result; | |
2838 | ||
c906108c SS |
2839 | break; |
2840 | } | |
c5aa993b JM |
2841 | |
2842 | case 0x4: | |
2843 | case 0x5: /* data transfer */ | |
2844 | case 0x6: | |
2845 | case 0x7: | |
c906108c SS |
2846 | if (bit (this_instr, 20)) |
2847 | { | |
2848 | /* load */ | |
2849 | if (bits (this_instr, 12, 15) == 15) | |
2850 | { | |
2851 | /* rd == pc */ | |
c5aa993b | 2852 | unsigned long rn; |
c906108c | 2853 | unsigned long base; |
c5aa993b | 2854 | |
c906108c | 2855 | if (bit (this_instr, 22)) |
edefbb7c | 2856 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
2857 | |
2858 | /* byte write to PC */ | |
2859 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
2860 | base = (rn == 15) ? pc_val + 8 |
2861 | : get_frame_register_unsigned (frame, rn); | |
c906108c SS |
2862 | if (bit (this_instr, 24)) |
2863 | { | |
2864 | /* pre-indexed */ | |
2865 | int c = (status & FLAG_C) ? 1 : 0; | |
2866 | unsigned long offset = | |
c5aa993b | 2867 | (bit (this_instr, 25) |
0b1b3e42 | 2868 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 2869 | : bits (this_instr, 0, 11)); |
c906108c SS |
2870 | |
2871 | if (bit (this_instr, 23)) | |
2872 | base += offset; | |
2873 | else | |
2874 | base -= offset; | |
2875 | } | |
c5aa993b | 2876 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
e17a4113 | 2877 | 4, byte_order); |
c906108c SS |
2878 | } |
2879 | } | |
2880 | break; | |
c5aa993b JM |
2881 | |
2882 | case 0x8: | |
2883 | case 0x9: /* block transfer */ | |
c906108c SS |
2884 | if (bit (this_instr, 20)) |
2885 | { | |
2886 | /* LDM */ | |
2887 | if (bit (this_instr, 15)) | |
2888 | { | |
2889 | /* loading pc */ | |
2890 | int offset = 0; | |
2891 | ||
2892 | if (bit (this_instr, 23)) | |
2893 | { | |
2894 | /* up */ | |
2895 | unsigned long reglist = bits (this_instr, 0, 14); | |
2896 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2897 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2898 | offset += 4; |
2899 | } | |
2900 | else if (bit (this_instr, 24)) | |
2901 | offset = -4; | |
c5aa993b | 2902 | |
c906108c | 2903 | { |
c5aa993b | 2904 | unsigned long rn_val = |
0b1b3e42 UW |
2905 | get_frame_register_unsigned (frame, |
2906 | bits (this_instr, 16, 19)); | |
c906108c SS |
2907 | nextpc = |
2908 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2909 | + offset), |
e17a4113 | 2910 | 4, byte_order); |
c906108c | 2911 | } |
c906108c SS |
2912 | } |
2913 | } | |
2914 | break; | |
c5aa993b JM |
2915 | |
2916 | case 0xb: /* branch & link */ | |
2917 | case 0xa: /* branch */ | |
c906108c SS |
2918 | { |
2919 | nextpc = BranchDest (pc, this_instr); | |
c906108c SS |
2920 | break; |
2921 | } | |
c5aa993b JM |
2922 | |
2923 | case 0xc: | |
2924 | case 0xd: | |
2925 | case 0xe: /* coproc ops */ | |
2926 | case 0xf: /* SWI */ | |
c906108c SS |
2927 | break; |
2928 | ||
2929 | default: | |
edefbb7c | 2930 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
2931 | return (pc); |
2932 | } | |
2933 | } | |
2934 | ||
2935 | return nextpc; | |
2936 | } | |
2937 | ||
50e98be4 DJ |
2938 | CORE_ADDR |
2939 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
2940 | { | |
2941 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2942 | CORE_ADDR nextpc = | |
2943 | gdbarch_addr_bits_remove (gdbarch, | |
2944 | arm_get_next_pc_raw (frame, pc, TRUE)); | |
2945 | if (nextpc == pc) | |
2946 | error (_("Infinite loop detected")); | |
2947 | return nextpc; | |
2948 | } | |
2949 | ||
9512d7fd FN |
2950 | /* single_step() is called just before we want to resume the inferior, |
2951 | if we want to single-step it but there is no hardware or kernel | |
2952 | single-step support. We find the target of the coming instruction | |
e0cd558a | 2953 | and breakpoint it. */ |
9512d7fd | 2954 | |
190dce09 | 2955 | int |
0b1b3e42 | 2956 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 2957 | { |
a6d9a66e | 2958 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2959 | struct address_space *aspace = get_frame_address_space (frame); |
a6d9a66e | 2960 | |
8181d85f DJ |
2961 | /* NOTE: This may insert the wrong breakpoint instruction when |
2962 | single-stepping over a mode-changing instruction, if the | |
2963 | CPSR heuristics are used. */ | |
9512d7fd | 2964 | |
0b1b3e42 | 2965 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
6c95b8df | 2966 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b UW |
2967 | |
2968 | return 1; | |
9512d7fd | 2969 | } |
9512d7fd | 2970 | |
f9d67f43 DJ |
2971 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
2972 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
2973 | NULL if an error occurs. BUF is freed. */ | |
2974 | ||
2975 | static gdb_byte * | |
2976 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
2977 | int old_len, int new_len) | |
2978 | { | |
2979 | gdb_byte *new_buf, *middle; | |
2980 | int bytes_to_read = new_len - old_len; | |
2981 | ||
2982 | new_buf = xmalloc (new_len); | |
2983 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
2984 | xfree (buf); | |
2985 | if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0) | |
2986 | { | |
2987 | xfree (new_buf); | |
2988 | return NULL; | |
2989 | } | |
2990 | return new_buf; | |
2991 | } | |
2992 | ||
2993 | /* An IT block is at most the 2-byte IT instruction followed by | |
2994 | four 4-byte instructions. The furthest back we must search to | |
2995 | find an IT block that affects the current instruction is thus | |
2996 | 2 + 3 * 4 == 14 bytes. */ | |
2997 | #define MAX_IT_BLOCK_PREFIX 14 | |
2998 | ||
2999 | /* Use a quick scan if there are more than this many bytes of | |
3000 | code. */ | |
3001 | #define IT_SCAN_THRESHOLD 32 | |
3002 | ||
3003 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. | |
3004 | A breakpoint in an IT block may not be hit, depending on the | |
3005 | condition flags. */ | |
3006 | static CORE_ADDR | |
3007 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
3008 | { | |
3009 | gdb_byte *buf; | |
3010 | char map_type; | |
3011 | CORE_ADDR boundary, func_start; | |
3012 | int buf_len, buf2_len; | |
3013 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
3014 | int i, any, last_it, last_it_count; | |
3015 | ||
3016 | /* If we are using BKPT breakpoints, none of this is necessary. */ | |
3017 | if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) | |
3018 | return bpaddr; | |
3019 | ||
3020 | /* ARM mode does not have this problem. */ | |
3021 | if (!arm_pc_is_thumb (bpaddr)) | |
3022 | return bpaddr; | |
3023 | ||
3024 | /* We are setting a breakpoint in Thumb code that could potentially | |
3025 | contain an IT block. The first step is to find how much Thumb | |
3026 | code there is; we do not need to read outside of known Thumb | |
3027 | sequences. */ | |
3028 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
3029 | if (map_type == 0) | |
3030 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
3031 | return bpaddr; | |
3032 | ||
3033 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); | |
3034 | ||
3035 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) | |
3036 | && func_start > boundary) | |
3037 | boundary = func_start; | |
3038 | ||
3039 | /* Search for a candidate IT instruction. We have to do some fancy | |
3040 | footwork to distinguish a real IT instruction from the second | |
3041 | half of a 32-bit instruction, but there is no need for that if | |
3042 | there's no candidate. */ | |
3043 | buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX); | |
3044 | if (buf_len == 0) | |
3045 | /* No room for an IT instruction. */ | |
3046 | return bpaddr; | |
3047 | ||
3048 | buf = xmalloc (buf_len); | |
3049 | if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0) | |
3050 | return bpaddr; | |
3051 | any = 0; | |
3052 | for (i = 0; i < buf_len; i += 2) | |
3053 | { | |
3054 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
3055 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
3056 | { | |
3057 | any = 1; | |
3058 | break; | |
3059 | } | |
3060 | } | |
3061 | if (any == 0) | |
3062 | { | |
3063 | xfree (buf); | |
3064 | return bpaddr; | |
3065 | } | |
3066 | ||
3067 | /* OK, the code bytes before this instruction contain at least one | |
3068 | halfword which resembles an IT instruction. We know that it's | |
3069 | Thumb code, but there are still two possibilities. Either the | |
3070 | halfword really is an IT instruction, or it is the second half of | |
3071 | a 32-bit Thumb instruction. The only way we can tell is to | |
3072 | scan forwards from a known instruction boundary. */ | |
3073 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
3074 | { | |
3075 | int definite; | |
3076 | ||
3077 | /* There's a lot of code before this instruction. Start with an | |
3078 | optimistic search; it's easy to recognize halfwords that can | |
3079 | not be the start of a 32-bit instruction, and use that to | |
3080 | lock on to the instruction boundaries. */ | |
3081 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
3082 | if (buf == NULL) | |
3083 | return bpaddr; | |
3084 | buf_len = IT_SCAN_THRESHOLD; | |
3085 | ||
3086 | definite = 0; | |
3087 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
3088 | { | |
3089 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
3090 | if (thumb_insn_size (inst1) == 2) | |
3091 | { | |
3092 | definite = 1; | |
3093 | break; | |
3094 | } | |
3095 | } | |
3096 | ||
3097 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
3098 | are sure that we know the instruction boundaries, and it is far | |
3099 | enough from BPADDR that we could not miss an IT instruction | |
3100 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
3101 | known boundary. */ | |
3102 | if (! definite) | |
3103 | { | |
3104 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
3105 | if (buf == NULL) | |
3106 | return bpaddr; | |
3107 | buf_len = bpaddr - boundary; | |
3108 | i = 0; | |
3109 | } | |
3110 | } | |
3111 | else | |
3112 | { | |
3113 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
3114 | if (buf == NULL) | |
3115 | return bpaddr; | |
3116 | buf_len = bpaddr - boundary; | |
3117 | i = 0; | |
3118 | } | |
3119 | ||
3120 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
3121 | last_it = -1; | |
3122 | last_it_count = 0; | |
3123 | while (i < buf_len) | |
3124 | { | |
3125 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
3126 | last_it_count--; | |
3127 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
3128 | { | |
3129 | last_it = i; | |
3130 | if (inst1 & 0x0001) | |
3131 | last_it_count = 4; | |
3132 | else if (inst1 & 0x0002) | |
3133 | last_it_count = 3; | |
3134 | else if (inst1 & 0x0004) | |
3135 | last_it_count = 2; | |
3136 | else | |
3137 | last_it_count = 1; | |
3138 | } | |
3139 | i += thumb_insn_size (inst1); | |
3140 | } | |
3141 | ||
3142 | xfree (buf); | |
3143 | ||
3144 | if (last_it == -1) | |
3145 | /* There wasn't really an IT instruction after all. */ | |
3146 | return bpaddr; | |
3147 | ||
3148 | if (last_it_count < 1) | |
3149 | /* It was too far away. */ | |
3150 | return bpaddr; | |
3151 | ||
3152 | /* This really is a trouble spot. Move the breakpoint to the IT | |
3153 | instruction. */ | |
3154 | return bpaddr - buf_len + last_it; | |
3155 | } | |
3156 | ||
cca44b1b | 3157 | /* ARM displaced stepping support. |
c906108c | 3158 | |
cca44b1b | 3159 | Generally ARM displaced stepping works as follows: |
c906108c | 3160 | |
cca44b1b JB |
3161 | 1. When an instruction is to be single-stepped, it is first decoded by |
3162 | arm_process_displaced_insn (called from arm_displaced_step_copy_insn). | |
3163 | Depending on the type of instruction, it is then copied to a scratch | |
3164 | location, possibly in a modified form. The copy_* set of functions | |
3165 | performs such modification, as necessary. A breakpoint is placed after | |
3166 | the modified instruction in the scratch space to return control to GDB. | |
3167 | Note in particular that instructions which modify the PC will no longer | |
3168 | do so after modification. | |
c5aa993b | 3169 | |
cca44b1b JB |
3170 | 2. The instruction is single-stepped, by setting the PC to the scratch |
3171 | location address, and resuming. Control returns to GDB when the | |
3172 | breakpoint is hit. | |
c5aa993b | 3173 | |
cca44b1b JB |
3174 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
3175 | function used for the current instruction. This function's job is to | |
3176 | put the CPU/memory state back to what it would have been if the | |
3177 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 3178 | |
cca44b1b JB |
3179 | /* NOP instruction (mov r0, r0). */ |
3180 | #define ARM_NOP 0xe1a00000 | |
3181 | ||
3182 | /* Helper for register reads for displaced stepping. In particular, this | |
3183 | returns the PC as it would be seen by the instruction at its original | |
3184 | location. */ | |
3185 | ||
3186 | ULONGEST | |
3187 | displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno) | |
3188 | { | |
3189 | ULONGEST ret; | |
3190 | ||
3191 | if (regno == 15) | |
3192 | { | |
3193 | if (debug_displaced) | |
3194 | fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", | |
3195 | (unsigned long) from + 8); | |
3196 | return (ULONGEST) from + 8; /* Pipeline offset. */ | |
3197 | } | |
c906108c | 3198 | else |
cca44b1b JB |
3199 | { |
3200 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
3201 | if (debug_displaced) | |
3202 | fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", | |
3203 | regno, (unsigned long) ret); | |
3204 | return ret; | |
3205 | } | |
c906108c SS |
3206 | } |
3207 | ||
cca44b1b JB |
3208 | static int |
3209 | displaced_in_arm_mode (struct regcache *regs) | |
3210 | { | |
3211 | ULONGEST ps; | |
66e810cd | 3212 | |
cca44b1b | 3213 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 3214 | |
cca44b1b JB |
3215 | return (ps & CPSR_T) == 0; |
3216 | } | |
66e810cd | 3217 | |
cca44b1b | 3218 | /* Write to the PC as from a branch instruction. */ |
c906108c | 3219 | |
cca44b1b JB |
3220 | static void |
3221 | branch_write_pc (struct regcache *regs, ULONGEST val) | |
c906108c | 3222 | { |
cca44b1b JB |
3223 | if (displaced_in_arm_mode (regs)) |
3224 | /* Note: If bits 0/1 are set, this branch would be unpredictable for | |
3225 | architecture versions < 6. */ | |
3226 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3); | |
3227 | else | |
3228 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1); | |
3229 | } | |
66e810cd | 3230 | |
cca44b1b JB |
3231 | /* Write to the PC as from a branch-exchange instruction. */ |
3232 | ||
3233 | static void | |
3234 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
3235 | { | |
3236 | ULONGEST ps; | |
3237 | ||
3238 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
3239 | ||
3240 | if ((val & 1) == 1) | |
c906108c | 3241 | { |
cca44b1b JB |
3242 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | CPSR_T); |
3243 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); | |
3244 | } | |
3245 | else if ((val & 2) == 0) | |
3246 | { | |
3247 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, | |
3248 | ps & ~(ULONGEST) CPSR_T); | |
3249 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); | |
c906108c SS |
3250 | } |
3251 | else | |
3252 | { | |
cca44b1b JB |
3253 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
3254 | mode, align dest to 4 bytes). */ | |
3255 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
3256 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, | |
3257 | ps & ~(ULONGEST) CPSR_T); | |
3258 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); | |
c906108c SS |
3259 | } |
3260 | } | |
ed9a39eb | 3261 | |
cca44b1b | 3262 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 3263 | |
34e8f22d | 3264 | static void |
cca44b1b | 3265 | load_write_pc (struct regcache *regs, ULONGEST val) |
ed9a39eb | 3266 | { |
cca44b1b JB |
3267 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
3268 | bx_write_pc (regs, val); | |
3269 | else | |
3270 | branch_write_pc (regs, val); | |
3271 | } | |
be8626e0 | 3272 | |
cca44b1b JB |
3273 | /* Write to the PC as if from an ALU instruction. */ |
3274 | ||
3275 | static void | |
3276 | alu_write_pc (struct regcache *regs, ULONGEST val) | |
3277 | { | |
3278 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && displaced_in_arm_mode (regs)) | |
3279 | bx_write_pc (regs, val); | |
3280 | else | |
3281 | branch_write_pc (regs, val); | |
3282 | } | |
3283 | ||
3284 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
3285 | has a varying effects depending on the instruction which does the write: | |
3286 | this is controlled by the WRITE_PC argument. */ | |
3287 | ||
3288 | void | |
3289 | displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, | |
3290 | int regno, ULONGEST val, enum pc_write_style write_pc) | |
3291 | { | |
3292 | if (regno == 15) | |
08216dd7 | 3293 | { |
cca44b1b JB |
3294 | if (debug_displaced) |
3295 | fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", | |
3296 | (unsigned long) val); | |
3297 | switch (write_pc) | |
08216dd7 | 3298 | { |
cca44b1b JB |
3299 | case BRANCH_WRITE_PC: |
3300 | branch_write_pc (regs, val); | |
08216dd7 RE |
3301 | break; |
3302 | ||
cca44b1b JB |
3303 | case BX_WRITE_PC: |
3304 | bx_write_pc (regs, val); | |
3305 | break; | |
3306 | ||
3307 | case LOAD_WRITE_PC: | |
3308 | load_write_pc (regs, val); | |
3309 | break; | |
3310 | ||
3311 | case ALU_WRITE_PC: | |
3312 | alu_write_pc (regs, val); | |
3313 | break; | |
3314 | ||
3315 | case CANNOT_WRITE_PC: | |
3316 | warning (_("Instruction wrote to PC in an unexpected way when " | |
3317 | "single-stepping")); | |
08216dd7 RE |
3318 | break; |
3319 | ||
3320 | default: | |
97b9747c JB |
3321 | internal_error (__FILE__, __LINE__, |
3322 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 3323 | } |
b508a996 | 3324 | |
cca44b1b | 3325 | dsc->wrote_to_pc = 1; |
b508a996 | 3326 | } |
ed9a39eb | 3327 | else |
b508a996 | 3328 | { |
cca44b1b JB |
3329 | if (debug_displaced) |
3330 | fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", | |
3331 | regno, (unsigned long) val); | |
3332 | regcache_cooked_write_unsigned (regs, regno, val); | |
b508a996 | 3333 | } |
34e8f22d RE |
3334 | } |
3335 | ||
cca44b1b JB |
3336 | /* This function is used to concisely determine if an instruction INSN |
3337 | references PC. Register fields of interest in INSN should have the | |
3338 | corresponding fields of BITMASK set to 0b1111. The function returns return 1 | |
3339 | if any of these fields in INSN reference the PC (also 0b1111, r15), else it | |
3340 | returns 0. */ | |
67255d04 RE |
3341 | |
3342 | static int | |
cca44b1b | 3343 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 3344 | { |
cca44b1b | 3345 | uint32_t lowbit = 1; |
67255d04 | 3346 | |
cca44b1b JB |
3347 | while (bitmask != 0) |
3348 | { | |
3349 | uint32_t mask; | |
44e1a9eb | 3350 | |
cca44b1b JB |
3351 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
3352 | ; | |
67255d04 | 3353 | |
cca44b1b JB |
3354 | if (!lowbit) |
3355 | break; | |
67255d04 | 3356 | |
cca44b1b | 3357 | mask = lowbit * 0xf; |
67255d04 | 3358 | |
cca44b1b JB |
3359 | if ((insn & mask) == mask) |
3360 | return 1; | |
3361 | ||
3362 | bitmask &= ~mask; | |
67255d04 RE |
3363 | } |
3364 | ||
cca44b1b JB |
3365 | return 0; |
3366 | } | |
2af48f68 | 3367 | |
cca44b1b JB |
3368 | /* The simplest copy function. Many instructions have the same effect no |
3369 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 3370 | |
cca44b1b JB |
3371 | static int |
3372 | copy_unmodified (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, | |
3373 | const char *iname, struct displaced_step_closure *dsc) | |
3374 | { | |
3375 | if (debug_displaced) | |
3376 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " | |
3377 | "opcode/class '%s' unmodified\n", (unsigned long) insn, | |
3378 | iname); | |
67255d04 | 3379 | |
cca44b1b | 3380 | dsc->modinsn[0] = insn; |
67255d04 | 3381 | |
cca44b1b JB |
3382 | return 0; |
3383 | } | |
3384 | ||
3385 | /* Preload instructions with immediate offset. */ | |
3386 | ||
3387 | static void | |
3388 | cleanup_preload (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
3389 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3390 | { | |
3391 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
3392 | if (!dsc->u.preload.immed) | |
3393 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
3394 | } | |
3395 | ||
3396 | static int | |
3397 | copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
3398 | struct displaced_step_closure *dsc) | |
3399 | { | |
3400 | unsigned int rn = bits (insn, 16, 19); | |
3401 | ULONGEST rn_val; | |
3402 | CORE_ADDR from = dsc->insn_addr; | |
3403 | ||
3404 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
3405 | return copy_unmodified (gdbarch, insn, "preload", dsc); | |
3406 | ||
3407 | if (debug_displaced) | |
3408 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
3409 | (unsigned long) insn); | |
3410 | ||
3411 | /* Preload instructions: | |
3412 | ||
3413 | {pli/pld} [rn, #+/-imm] | |
3414 | -> | |
3415 | {pli/pld} [r0, #+/-imm]. */ | |
3416 | ||
3417 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3418 | rn_val = displaced_read_reg (regs, from, rn); | |
3419 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); | |
3420 | ||
3421 | dsc->u.preload.immed = 1; | |
3422 | ||
3423 | dsc->modinsn[0] = insn & 0xfff0ffff; | |
3424 | ||
3425 | dsc->cleanup = &cleanup_preload; | |
3426 | ||
3427 | return 0; | |
3428 | } | |
3429 | ||
3430 | /* Preload instructions with register offset. */ | |
3431 | ||
3432 | static int | |
3433 | copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
3434 | struct displaced_step_closure *dsc) | |
3435 | { | |
3436 | unsigned int rn = bits (insn, 16, 19); | |
3437 | unsigned int rm = bits (insn, 0, 3); | |
3438 | ULONGEST rn_val, rm_val; | |
3439 | CORE_ADDR from = dsc->insn_addr; | |
3440 | ||
3441 | if (!insn_references_pc (insn, 0x000f000ful)) | |
3442 | return copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
3443 | ||
3444 | if (debug_displaced) | |
3445 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", | |
3446 | (unsigned long) insn); | |
3447 | ||
3448 | /* Preload register-offset instructions: | |
3449 | ||
3450 | {pli/pld} [rn, rm {, shift}] | |
3451 | -> | |
3452 | {pli/pld} [r0, r1 {, shift}]. */ | |
3453 | ||
3454 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3455 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); | |
3456 | rn_val = displaced_read_reg (regs, from, rn); | |
3457 | rm_val = displaced_read_reg (regs, from, rm); | |
3458 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); | |
3459 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
3460 | ||
3461 | dsc->u.preload.immed = 0; | |
3462 | ||
3463 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
3464 | ||
3465 | dsc->cleanup = &cleanup_preload; | |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
3470 | /* Copy/cleanup coprocessor load and store instructions. */ | |
3471 | ||
3472 | static void | |
3473 | cleanup_copro_load_store (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
3474 | struct regcache *regs, | |
3475 | struct displaced_step_closure *dsc) | |
3476 | { | |
3477 | ULONGEST rn_val = displaced_read_reg (regs, dsc->insn_addr, 0); | |
3478 | ||
3479 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
3480 | ||
3481 | if (dsc->u.ldst.writeback) | |
3482 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
3483 | } | |
3484 | ||
3485 | static int | |
3486 | copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
3487 | struct regcache *regs, | |
3488 | struct displaced_step_closure *dsc) | |
3489 | { | |
3490 | unsigned int rn = bits (insn, 16, 19); | |
3491 | ULONGEST rn_val; | |
3492 | CORE_ADDR from = dsc->insn_addr; | |
3493 | ||
3494 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
3495 | return copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
3496 | ||
3497 | if (debug_displaced) | |
3498 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " | |
3499 | "load/store insn %.8lx\n", (unsigned long) insn); | |
3500 | ||
3501 | /* Coprocessor load/store instructions: | |
3502 | ||
3503 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
3504 | -> | |
3505 | {stc/stc2} [r0, #+/-imm]. | |
3506 | ||
3507 | ldc/ldc2 are handled identically. */ | |
3508 | ||
3509 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3510 | rn_val = displaced_read_reg (regs, from, rn); | |
3511 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); | |
3512 | ||
3513 | dsc->u.ldst.writeback = bit (insn, 25); | |
3514 | dsc->u.ldst.rn = rn; | |
3515 | ||
3516 | dsc->modinsn[0] = insn & 0xfff0ffff; | |
3517 | ||
3518 | dsc->cleanup = &cleanup_copro_load_store; | |
3519 | ||
3520 | return 0; | |
3521 | } | |
3522 | ||
3523 | /* Clean up branch instructions (actually perform the branch, by setting | |
3524 | PC). */ | |
3525 | ||
3526 | static void | |
3527 | cleanup_branch (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, | |
3528 | struct displaced_step_closure *dsc) | |
3529 | { | |
3530 | ULONGEST from = dsc->insn_addr; | |
3531 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); | |
3532 | int branch_taken = condition_true (dsc->u.branch.cond, status); | |
3533 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
3534 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
3535 | ||
3536 | if (!branch_taken) | |
3537 | return; | |
3538 | ||
3539 | if (dsc->u.branch.link) | |
3540 | { | |
3541 | ULONGEST pc = displaced_read_reg (regs, from, 15); | |
3542 | displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC); | |
3543 | } | |
3544 | ||
3545 | displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc); | |
3546 | } | |
3547 | ||
3548 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
3549 | ||
3550 | static int | |
3551 | copy_b_bl_blx (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, | |
3552 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3553 | { | |
3554 | unsigned int cond = bits (insn, 28, 31); | |
3555 | int exchange = (cond == 0xf); | |
3556 | int link = exchange || bit (insn, 24); | |
3557 | CORE_ADDR from = dsc->insn_addr; | |
3558 | long offset; | |
3559 | ||
3560 | if (debug_displaced) | |
3561 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " | |
3562 | "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", | |
3563 | (unsigned long) insn); | |
3564 | ||
3565 | /* Implement "BL<cond> <label>" as: | |
3566 | ||
3567 | Preparation: cond <- instruction condition | |
3568 | Insn: mov r0, r0 (nop) | |
3569 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
3570 | ||
3571 | B<cond> similar, but don't set r14 in cleanup. */ | |
3572 | ||
3573 | if (exchange) | |
3574 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
3575 | then arrange the switch into Thumb mode. */ | |
3576 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
3577 | else | |
3578 | offset = bits (insn, 0, 23) << 2; | |
3579 | ||
3580 | if (bit (offset, 25)) | |
3581 | offset = offset | ~0x3ffffff; | |
3582 | ||
3583 | dsc->u.branch.cond = cond; | |
3584 | dsc->u.branch.link = link; | |
3585 | dsc->u.branch.exchange = exchange; | |
3586 | dsc->u.branch.dest = from + 8 + offset; | |
3587 | ||
3588 | dsc->modinsn[0] = ARM_NOP; | |
3589 | ||
3590 | dsc->cleanup = &cleanup_branch; | |
3591 | ||
3592 | return 0; | |
3593 | } | |
3594 | ||
3595 | /* Copy BX/BLX with register-specified destinations. */ | |
3596 | ||
3597 | static int | |
3598 | copy_bx_blx_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, | |
3599 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3600 | { | |
3601 | unsigned int cond = bits (insn, 28, 31); | |
3602 | /* BX: x12xxx1x | |
3603 | BLX: x12xxx3x. */ | |
3604 | int link = bit (insn, 5); | |
3605 | unsigned int rm = bits (insn, 0, 3); | |
3606 | CORE_ADDR from = dsc->insn_addr; | |
3607 | ||
3608 | if (debug_displaced) | |
3609 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s register insn " | |
3610 | "%.8lx\n", (link) ? "blx" : "bx", (unsigned long) insn); | |
3611 | ||
3612 | /* Implement {BX,BLX}<cond> <reg>" as: | |
3613 | ||
3614 | Preparation: cond <- instruction condition | |
3615 | Insn: mov r0, r0 (nop) | |
3616 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
3617 | ||
3618 | Don't set r14 in cleanup for BX. */ | |
3619 | ||
3620 | dsc->u.branch.dest = displaced_read_reg (regs, from, rm); | |
3621 | ||
3622 | dsc->u.branch.cond = cond; | |
3623 | dsc->u.branch.link = link; | |
3624 | dsc->u.branch.exchange = 1; | |
3625 | ||
3626 | dsc->modinsn[0] = ARM_NOP; | |
3627 | ||
3628 | dsc->cleanup = &cleanup_branch; | |
3629 | ||
3630 | return 0; | |
3631 | } | |
3632 | ||
3633 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ | |
3634 | ||
3635 | static void | |
3636 | cleanup_alu_imm (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
3637 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3638 | { | |
3639 | ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); | |
3640 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
3641 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
3642 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
3643 | } | |
3644 | ||
3645 | static int | |
3646 | copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
3647 | struct displaced_step_closure *dsc) | |
3648 | { | |
3649 | unsigned int rn = bits (insn, 16, 19); | |
3650 | unsigned int rd = bits (insn, 12, 15); | |
3651 | unsigned int op = bits (insn, 21, 24); | |
3652 | int is_mov = (op == 0xd); | |
3653 | ULONGEST rd_val, rn_val; | |
3654 | CORE_ADDR from = dsc->insn_addr; | |
3655 | ||
3656 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
3657 | return copy_unmodified (gdbarch, insn, "ALU immediate", dsc); | |
3658 | ||
3659 | if (debug_displaced) | |
3660 | fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn " | |
3661 | "%.8lx\n", is_mov ? "move" : "ALU", | |
3662 | (unsigned long) insn); | |
3663 | ||
3664 | /* Instruction is of form: | |
3665 | ||
3666 | <op><cond> rd, [rn,] #imm | |
3667 | ||
3668 | Rewrite as: | |
3669 | ||
3670 | Preparation: tmp1, tmp2 <- r0, r1; | |
3671 | r0, r1 <- rd, rn | |
3672 | Insn: <op><cond> r0, r1, #imm | |
3673 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
3674 | */ | |
3675 | ||
3676 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3677 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); | |
3678 | rn_val = displaced_read_reg (regs, from, rn); | |
3679 | rd_val = displaced_read_reg (regs, from, rd); | |
3680 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
3681 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
3682 | dsc->rd = rd; | |
3683 | ||
3684 | if (is_mov) | |
3685 | dsc->modinsn[0] = insn & 0xfff00fff; | |
3686 | else | |
3687 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
3688 | ||
3689 | dsc->cleanup = &cleanup_alu_imm; | |
3690 | ||
3691 | return 0; | |
3692 | } | |
3693 | ||
3694 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ | |
3695 | ||
3696 | static void | |
3697 | cleanup_alu_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
3698 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3699 | { | |
3700 | ULONGEST rd_val; | |
3701 | int i; | |
3702 | ||
3703 | rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); | |
3704 | ||
3705 | for (i = 0; i < 3; i++) | |
3706 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
3707 | ||
3708 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
3709 | } | |
3710 | ||
3711 | static int | |
3712 | copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
3713 | struct displaced_step_closure *dsc) | |
3714 | { | |
3715 | unsigned int rn = bits (insn, 16, 19); | |
3716 | unsigned int rm = bits (insn, 0, 3); | |
3717 | unsigned int rd = bits (insn, 12, 15); | |
3718 | unsigned int op = bits (insn, 21, 24); | |
3719 | int is_mov = (op == 0xd); | |
3720 | ULONGEST rd_val, rn_val, rm_val; | |
3721 | CORE_ADDR from = dsc->insn_addr; | |
3722 | ||
3723 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
3724 | return copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
3725 | ||
3726 | if (debug_displaced) | |
3727 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n", | |
3728 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
3729 | ||
3730 | /* Instruction is of form: | |
3731 | ||
3732 | <op><cond> rd, [rn,] rm [, <shift>] | |
3733 | ||
3734 | Rewrite as: | |
3735 | ||
3736 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
3737 | r0, r1, r2 <- rd, rn, rm | |
3738 | Insn: <op><cond> r0, r1, r2 [, <shift>] | |
3739 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 | |
3740 | */ | |
3741 | ||
3742 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3743 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); | |
3744 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); | |
3745 | rd_val = displaced_read_reg (regs, from, rd); | |
3746 | rn_val = displaced_read_reg (regs, from, rn); | |
3747 | rm_val = displaced_read_reg (regs, from, rm); | |
3748 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
3749 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
3750 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
3751 | dsc->rd = rd; | |
3752 | ||
3753 | if (is_mov) | |
3754 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
3755 | else | |
3756 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
3757 | ||
3758 | dsc->cleanup = &cleanup_alu_reg; | |
3759 | ||
3760 | return 0; | |
3761 | } | |
3762 | ||
3763 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ | |
3764 | ||
3765 | static void | |
3766 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
3767 | struct regcache *regs, | |
3768 | struct displaced_step_closure *dsc) | |
3769 | { | |
3770 | ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); | |
3771 | int i; | |
3772 | ||
3773 | for (i = 0; i < 4; i++) | |
3774 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
3775 | ||
3776 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
3777 | } | |
3778 | ||
3779 | static int | |
3780 | copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
3781 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3782 | { | |
3783 | unsigned int rn = bits (insn, 16, 19); | |
3784 | unsigned int rm = bits (insn, 0, 3); | |
3785 | unsigned int rd = bits (insn, 12, 15); | |
3786 | unsigned int rs = bits (insn, 8, 11); | |
3787 | unsigned int op = bits (insn, 21, 24); | |
3788 | int is_mov = (op == 0xd), i; | |
3789 | ULONGEST rd_val, rn_val, rm_val, rs_val; | |
3790 | CORE_ADDR from = dsc->insn_addr; | |
3791 | ||
3792 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
3793 | return copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
3794 | ||
3795 | if (debug_displaced) | |
3796 | fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn " | |
3797 | "%.8lx\n", is_mov ? "move" : "ALU", | |
3798 | (unsigned long) insn); | |
3799 | ||
3800 | /* Instruction is of form: | |
3801 | ||
3802 | <op><cond> rd, [rn,] rm, <shift> rs | |
3803 | ||
3804 | Rewrite as: | |
3805 | ||
3806 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
3807 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
3808 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
3809 | Cleanup: tmp5 <- r0 | |
3810 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
3811 | rd <- tmp5 | |
3812 | */ | |
3813 | ||
3814 | for (i = 0; i < 4; i++) | |
3815 | dsc->tmp[i] = displaced_read_reg (regs, from, i); | |
3816 | ||
3817 | rd_val = displaced_read_reg (regs, from, rd); | |
3818 | rn_val = displaced_read_reg (regs, from, rn); | |
3819 | rm_val = displaced_read_reg (regs, from, rm); | |
3820 | rs_val = displaced_read_reg (regs, from, rs); | |
3821 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
3822 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
3823 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
3824 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
3825 | dsc->rd = rd; | |
3826 | ||
3827 | if (is_mov) | |
3828 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
3829 | else | |
3830 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
3831 | ||
3832 | dsc->cleanup = &cleanup_alu_shifted_reg; | |
3833 | ||
3834 | return 0; | |
3835 | } | |
3836 | ||
3837 | /* Clean up load instructions. */ | |
3838 | ||
3839 | static void | |
3840 | cleanup_load (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, | |
3841 | struct displaced_step_closure *dsc) | |
3842 | { | |
3843 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
3844 | CORE_ADDR from = dsc->insn_addr; | |
3845 | ||
3846 | rt_val = displaced_read_reg (regs, from, 0); | |
3847 | if (dsc->u.ldst.xfersize == 8) | |
3848 | rt_val2 = displaced_read_reg (regs, from, 1); | |
3849 | rn_val = displaced_read_reg (regs, from, 2); | |
3850 | ||
3851 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
3852 | if (dsc->u.ldst.xfersize > 4) | |
3853 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
3854 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
3855 | if (!dsc->u.ldst.immed) | |
3856 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
3857 | ||
3858 | /* Handle register writeback. */ | |
3859 | if (dsc->u.ldst.writeback) | |
3860 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
3861 | /* Put result in right place. */ | |
3862 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
3863 | if (dsc->u.ldst.xfersize == 8) | |
3864 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
3865 | } | |
3866 | ||
3867 | /* Clean up store instructions. */ | |
3868 | ||
3869 | static void | |
3870 | cleanup_store (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, | |
3871 | struct displaced_step_closure *dsc) | |
3872 | { | |
3873 | CORE_ADDR from = dsc->insn_addr; | |
3874 | ULONGEST rn_val = displaced_read_reg (regs, from, 2); | |
3875 | ||
3876 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
3877 | if (dsc->u.ldst.xfersize > 4) | |
3878 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
3879 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
3880 | if (!dsc->u.ldst.immed) | |
3881 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
3882 | if (!dsc->u.ldst.restore_r4) | |
3883 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
3884 | ||
3885 | /* Writeback. */ | |
3886 | if (dsc->u.ldst.writeback) | |
3887 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
3888 | } | |
3889 | ||
3890 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
3891 | transfers, which have a different encoding to byte/word transfers. */ | |
3892 | ||
3893 | static int | |
3894 | copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, | |
3895 | struct regcache *regs, struct displaced_step_closure *dsc) | |
3896 | { | |
3897 | unsigned int op1 = bits (insn, 20, 24); | |
3898 | unsigned int op2 = bits (insn, 5, 6); | |
3899 | unsigned int rt = bits (insn, 12, 15); | |
3900 | unsigned int rn = bits (insn, 16, 19); | |
3901 | unsigned int rm = bits (insn, 0, 3); | |
3902 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
3903 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
3904 | int immed = (op1 & 0x4) != 0; | |
3905 | int opcode; | |
3906 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
3907 | CORE_ADDR from = dsc->insn_addr; | |
3908 | ||
3909 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
3910 | return copy_unmodified (gdbarch, insn, "extra load/store", dsc); | |
3911 | ||
3912 | if (debug_displaced) | |
3913 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " | |
3914 | "insn %.8lx\n", unpriveleged ? "unpriveleged " : "", | |
3915 | (unsigned long) insn); | |
3916 | ||
3917 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
3918 | ||
3919 | if (opcode < 0) | |
3920 | internal_error (__FILE__, __LINE__, | |
3921 | _("copy_extra_ld_st: instruction decode error")); | |
3922 | ||
3923 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3924 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); | |
3925 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); | |
3926 | if (!immed) | |
3927 | dsc->tmp[3] = displaced_read_reg (regs, from, 3); | |
3928 | ||
3929 | rt_val = displaced_read_reg (regs, from, rt); | |
3930 | if (bytesize[opcode] == 8) | |
3931 | rt_val2 = displaced_read_reg (regs, from, rt + 1); | |
3932 | rn_val = displaced_read_reg (regs, from, rn); | |
3933 | if (!immed) | |
3934 | rm_val = displaced_read_reg (regs, from, rm); | |
3935 | ||
3936 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
3937 | if (bytesize[opcode] == 8) | |
3938 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
3939 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
3940 | if (!immed) | |
3941 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
3942 | ||
3943 | dsc->rd = rt; | |
3944 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
3945 | dsc->u.ldst.rn = rn; | |
3946 | dsc->u.ldst.immed = immed; | |
3947 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
3948 | dsc->u.ldst.restore_r4 = 0; | |
3949 | ||
3950 | if (immed) | |
3951 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
3952 | -> | |
3953 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
3954 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
3955 | else | |
3956 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
3957 | -> | |
3958 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
3959 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
3960 | ||
3961 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
3962 | ||
3963 | return 0; | |
3964 | } | |
3965 | ||
3966 | /* Copy byte/word loads and stores. */ | |
3967 | ||
3968 | static int | |
3969 | copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
3970 | struct regcache *regs, | |
3971 | struct displaced_step_closure *dsc, int load, int byte, | |
3972 | int usermode) | |
3973 | { | |
3974 | int immed = !bit (insn, 25); | |
3975 | unsigned int rt = bits (insn, 12, 15); | |
3976 | unsigned int rn = bits (insn, 16, 19); | |
3977 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
3978 | ULONGEST rt_val, rn_val, rm_val = 0; | |
3979 | CORE_ADDR from = dsc->insn_addr; | |
3980 | ||
3981 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
3982 | return copy_unmodified (gdbarch, insn, "load/store", dsc); | |
3983 | ||
3984 | if (debug_displaced) | |
3985 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s%s insn %.8lx\n", | |
3986 | load ? (byte ? "ldrb" : "ldr") | |
3987 | : (byte ? "strb" : "str"), usermode ? "t" : "", | |
3988 | (unsigned long) insn); | |
3989 | ||
3990 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); | |
3991 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); | |
3992 | if (!immed) | |
3993 | dsc->tmp[3] = displaced_read_reg (regs, from, 3); | |
3994 | if (!load) | |
3995 | dsc->tmp[4] = displaced_read_reg (regs, from, 4); | |
3996 | ||
3997 | rt_val = displaced_read_reg (regs, from, rt); | |
3998 | rn_val = displaced_read_reg (regs, from, rn); | |
3999 | if (!immed) | |
4000 | rm_val = displaced_read_reg (regs, from, rm); | |
4001 | ||
4002 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
4003 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
4004 | if (!immed) | |
4005 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
4006 | ||
4007 | dsc->rd = rt; | |
4008 | dsc->u.ldst.xfersize = byte ? 1 : 4; | |
4009 | dsc->u.ldst.rn = rn; | |
4010 | dsc->u.ldst.immed = immed; | |
4011 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
4012 | ||
4013 | /* To write PC we can do: | |
4014 | ||
4015 | scratch+0: str pc, temp (*temp = scratch + 8 + offset) | |
4016 | scratch+4: ldr r4, temp | |
4017 | scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8) | |
4018 | scratch+12: add r4, r4, #8 (r4 = offset) | |
4019 | scratch+16: add r0, r0, r4 | |
4020 | scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3]) | |
4021 | scratch+24: <temp> | |
4022 | ||
4023 | Otherwise we don't know what value to write for PC, since the offset is | |
4024 | architecture-dependent (sometimes PC+8, sometimes PC+12). */ | |
4025 | ||
4026 | if (load || rt != 15) | |
4027 | { | |
4028 | dsc->u.ldst.restore_r4 = 0; | |
4029 | ||
4030 | if (immed) | |
4031 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
4032 | -> | |
4033 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
4034 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
4035 | else | |
4036 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
4037 | -> | |
4038 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
4039 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
4040 | } | |
4041 | else | |
4042 | { | |
4043 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
4044 | dsc->u.ldst.restore_r4 = 1; | |
4045 | ||
4046 | dsc->modinsn[0] = 0xe58ff014; /* str pc, [pc, #20]. */ | |
4047 | dsc->modinsn[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */ | |
4048 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ | |
4049 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
4050 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
4051 | ||
4052 | /* As above. */ | |
4053 | if (immed) | |
4054 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
4055 | else | |
4056 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
4057 | ||
4058 | dsc->modinsn[6] = 0x0; /* breakpoint location. */ | |
4059 | dsc->modinsn[7] = 0x0; /* scratch space. */ | |
4060 | ||
4061 | dsc->numinsns = 6; | |
4062 | } | |
4063 | ||
4064 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
4065 | ||
4066 | return 0; | |
4067 | } | |
4068 | ||
4069 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
4070 | unfortunate corner case: it's impossible to implement correctly by modifying | |
4071 | the instruction. The issue is as follows: we have an instruction, | |
4072 | ||
4073 | ldm rN, {r0-r15} | |
4074 | ||
4075 | which we must rewrite to avoid loading PC. A possible solution would be to | |
4076 | do the load in two halves, something like (with suitable cleanup | |
4077 | afterwards): | |
4078 | ||
4079 | mov r8, rN | |
4080 | ldm[id][ab] r8!, {r0-r7} | |
4081 | str r7, <temp> | |
4082 | ldm[id][ab] r8, {r7-r14} | |
4083 | <bkpt> | |
4084 | ||
4085 | but at present there's no suitable place for <temp>, since the scratch space | |
4086 | is overwritten before the cleanup routine is called. For now, we simply | |
4087 | emulate the instruction. */ | |
4088 | ||
4089 | static void | |
4090 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
4091 | struct displaced_step_closure *dsc) | |
4092 | { | |
4093 | ULONGEST from = dsc->insn_addr; | |
4094 | int inc = dsc->u.block.increment; | |
4095 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
4096 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
4097 | uint32_t regmask = dsc->u.block.regmask; | |
4098 | int regno = inc ? 0 : 15; | |
4099 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
4100 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
4101 | && (regmask & 0x8000) != 0; | |
4102 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); | |
4103 | int do_transfer = condition_true (dsc->u.block.cond, status); | |
4104 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4105 | ||
4106 | if (!do_transfer) | |
4107 | return; | |
4108 | ||
4109 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
4110 | sensible we can do here. Complain loudly. */ | |
4111 | if (exception_return) | |
4112 | error (_("Cannot single-step exception return")); | |
4113 | ||
4114 | /* We don't handle any stores here for now. */ | |
4115 | gdb_assert (dsc->u.block.load != 0); | |
4116 | ||
4117 | if (debug_displaced) | |
4118 | fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: " | |
4119 | "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm", | |
4120 | dsc->u.block.increment ? "inc" : "dec", | |
4121 | dsc->u.block.before ? "before" : "after"); | |
4122 | ||
4123 | while (regmask) | |
4124 | { | |
4125 | uint32_t memword; | |
4126 | ||
4127 | if (inc) | |
4128 | while (regno <= 15 && (regmask & (1 << regno)) == 0) | |
4129 | regno++; | |
4130 | else | |
4131 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
4132 | regno--; | |
4133 | ||
4134 | xfer_addr += bump_before; | |
4135 | ||
4136 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
4137 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
4138 | ||
4139 | xfer_addr += bump_after; | |
4140 | ||
4141 | regmask &= ~(1 << regno); | |
4142 | } | |
4143 | ||
4144 | if (dsc->u.block.writeback) | |
4145 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
4146 | CANNOT_WRITE_PC); | |
4147 | } | |
4148 | ||
4149 | /* Clean up an STM which included the PC in the register list. */ | |
4150 | ||
4151 | static void | |
4152 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
4153 | struct displaced_step_closure *dsc) | |
4154 | { | |
4155 | ULONGEST from = dsc->insn_addr; | |
4156 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); | |
4157 | int store_executed = condition_true (dsc->u.block.cond, status); | |
4158 | CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask); | |
4159 | CORE_ADDR stm_insn_addr; | |
4160 | uint32_t pc_val; | |
4161 | long offset; | |
4162 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4163 | ||
4164 | /* If condition code fails, there's nothing else to do. */ | |
4165 | if (!store_executed) | |
4166 | return; | |
4167 | ||
4168 | if (dsc->u.block.increment) | |
4169 | { | |
4170 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
4171 | ||
4172 | if (dsc->u.block.before) | |
4173 | pc_stored_at += 4; | |
4174 | } | |
4175 | else | |
4176 | { | |
4177 | pc_stored_at = dsc->u.block.xfer_addr; | |
4178 | ||
4179 | if (dsc->u.block.before) | |
4180 | pc_stored_at -= 4; | |
4181 | } | |
4182 | ||
4183 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
4184 | stm_insn_addr = dsc->scratch_base; | |
4185 | offset = pc_val - stm_insn_addr; | |
4186 | ||
4187 | if (debug_displaced) | |
4188 | fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for " | |
4189 | "STM instruction\n", offset); | |
4190 | ||
4191 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
4192 | instruction. */ | |
4193 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
4194 | dsc->insn_addr + offset); | |
4195 | } | |
4196 | ||
4197 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
4198 | the registers in the transferred list into a contiguous range r0...rX (to | |
4199 | avoid loading PC directly and losing control of the debugged program), so we | |
4200 | must undo that here. */ | |
4201 | ||
4202 | static void | |
4203 | cleanup_block_load_pc (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, | |
4204 | struct regcache *regs, | |
4205 | struct displaced_step_closure *dsc) | |
4206 | { | |
4207 | ULONGEST from = dsc->insn_addr; | |
4208 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); | |
4209 | int load_executed = condition_true (dsc->u.block.cond, status), i; | |
4210 | unsigned int mask = dsc->u.block.regmask, write_reg = 15; | |
4211 | unsigned int regs_loaded = bitcount (mask); | |
4212 | unsigned int num_to_shuffle = regs_loaded, clobbered; | |
4213 | ||
4214 | /* The method employed here will fail if the register list is fully populated | |
4215 | (we need to avoid loading PC directly). */ | |
4216 | gdb_assert (num_to_shuffle < 16); | |
4217 | ||
4218 | if (!load_executed) | |
4219 | return; | |
4220 | ||
4221 | clobbered = (1 << num_to_shuffle) - 1; | |
4222 | ||
4223 | while (num_to_shuffle > 0) | |
4224 | { | |
4225 | if ((mask & (1 << write_reg)) != 0) | |
4226 | { | |
4227 | unsigned int read_reg = num_to_shuffle - 1; | |
4228 | ||
4229 | if (read_reg != write_reg) | |
4230 | { | |
4231 | ULONGEST rval = displaced_read_reg (regs, from, read_reg); | |
4232 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); | |
4233 | if (debug_displaced) | |
4234 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move " | |
4235 | "loaded register r%d to r%d\n"), read_reg, | |
4236 | write_reg); | |
4237 | } | |
4238 | else if (debug_displaced) | |
4239 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register " | |
4240 | "r%d already in the right place\n"), | |
4241 | write_reg); | |
4242 | ||
4243 | clobbered &= ~(1 << write_reg); | |
4244 | ||
4245 | num_to_shuffle--; | |
4246 | } | |
4247 | ||
4248 | write_reg--; | |
4249 | } | |
4250 | ||
4251 | /* Restore any registers we scribbled over. */ | |
4252 | for (write_reg = 0; clobbered != 0; write_reg++) | |
4253 | { | |
4254 | if ((clobbered & (1 << write_reg)) != 0) | |
4255 | { | |
4256 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
4257 | CANNOT_WRITE_PC); | |
4258 | if (debug_displaced) | |
4259 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored " | |
4260 | "clobbered register r%d\n"), write_reg); | |
4261 | clobbered &= ~(1 << write_reg); | |
4262 | } | |
4263 | } | |
4264 | ||
4265 | /* Perform register writeback manually. */ | |
4266 | if (dsc->u.block.writeback) | |
4267 | { | |
4268 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
4269 | ||
4270 | if (dsc->u.block.increment) | |
4271 | new_rn_val += regs_loaded * 4; | |
4272 | else | |
4273 | new_rn_val -= regs_loaded * 4; | |
4274 | ||
4275 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
4276 | CANNOT_WRITE_PC); | |
4277 | } | |
4278 | } | |
4279 | ||
4280 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
4281 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
4282 | ||
4283 | static int | |
4284 | copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
4285 | struct displaced_step_closure *dsc) | |
4286 | { | |
4287 | int load = bit (insn, 20); | |
4288 | int user = bit (insn, 22); | |
4289 | int increment = bit (insn, 23); | |
4290 | int before = bit (insn, 24); | |
4291 | int writeback = bit (insn, 21); | |
4292 | int rn = bits (insn, 16, 19); | |
4293 | CORE_ADDR from = dsc->insn_addr; | |
4294 | ||
4295 | /* Block transfers which don't mention PC can be run directly out-of-line. */ | |
4296 | if (rn != 15 && (insn & 0x8000) == 0) | |
4297 | return copy_unmodified (gdbarch, insn, "ldm/stm", dsc); | |
4298 | ||
4299 | if (rn == 15) | |
4300 | { | |
4301 | warning (_("displaced: Unpredictable LDM or STM with base register r15")); | |
4302 | return copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); | |
4303 | } | |
4304 | ||
4305 | if (debug_displaced) | |
4306 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " | |
4307 | "%.8lx\n", (unsigned long) insn); | |
4308 | ||
4309 | dsc->u.block.xfer_addr = displaced_read_reg (regs, from, rn); | |
4310 | dsc->u.block.rn = rn; | |
4311 | ||
4312 | dsc->u.block.load = load; | |
4313 | dsc->u.block.user = user; | |
4314 | dsc->u.block.increment = increment; | |
4315 | dsc->u.block.before = before; | |
4316 | dsc->u.block.writeback = writeback; | |
4317 | dsc->u.block.cond = bits (insn, 28, 31); | |
4318 | ||
4319 | dsc->u.block.regmask = insn & 0xffff; | |
4320 | ||
4321 | if (load) | |
4322 | { | |
4323 | if ((insn & 0xffff) == 0xffff) | |
4324 | { | |
4325 | /* LDM with a fully-populated register list. This case is | |
4326 | particularly tricky. Implement for now by fully emulating the | |
4327 | instruction (which might not behave perfectly in all cases, but | |
4328 | these instructions should be rare enough for that not to matter | |
4329 | too much). */ | |
4330 | dsc->modinsn[0] = ARM_NOP; | |
4331 | ||
4332 | dsc->cleanup = &cleanup_block_load_all; | |
4333 | } | |
4334 | else | |
4335 | { | |
4336 | /* LDM of a list of registers which includes PC. Implement by | |
4337 | rewriting the list of registers to be transferred into a | |
4338 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
4339 | registers into the correct places in the cleanup routine. */ | |
4340 | unsigned int regmask = insn & 0xffff; | |
4341 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; | |
4342 | unsigned int to = 0, from = 0, i, new_rn; | |
4343 | ||
4344 | for (i = 0; i < num_in_list; i++) | |
4345 | dsc->tmp[i] = displaced_read_reg (regs, from, i); | |
4346 | ||
4347 | /* Writeback makes things complicated. We need to avoid clobbering | |
4348 | the base register with one of the registers in our modified | |
4349 | register list, but just using a different register can't work in | |
4350 | all cases, e.g.: | |
4351 | ||
4352 | ldm r14!, {r0-r13,pc} | |
4353 | ||
4354 | which would need to be rewritten as: | |
4355 | ||
4356 | ldm rN!, {r0-r14} | |
4357 | ||
4358 | but that can't work, because there's no free register for N. | |
4359 | ||
4360 | Solve this by turning off the writeback bit, and emulating | |
4361 | writeback manually in the cleanup routine. */ | |
4362 | ||
4363 | if (writeback) | |
4364 | insn &= ~(1 << 21); | |
4365 | ||
4366 | new_regmask = (1 << num_in_list) - 1; | |
4367 | ||
4368 | if (debug_displaced) | |
4369 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " | |
4370 | "{..., pc}: original reg list %.4x, modified " | |
4371 | "list %.4x\n"), rn, writeback ? "!" : "", | |
4372 | (int) insn & 0xffff, new_regmask); | |
4373 | ||
4374 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
4375 | ||
4376 | dsc->cleanup = &cleanup_block_load_pc; | |
4377 | } | |
4378 | } | |
4379 | else | |
4380 | { | |
4381 | /* STM of a list of registers which includes PC. Run the instruction | |
4382 | as-is, but out of line: this will store the wrong value for the PC, | |
4383 | so we must manually fix up the memory in the cleanup routine. | |
4384 | Doing things this way has the advantage that we can auto-detect | |
4385 | the offset of the PC write (which is architecture-dependent) in | |
4386 | the cleanup routine. */ | |
4387 | dsc->modinsn[0] = insn; | |
4388 | ||
4389 | dsc->cleanup = &cleanup_block_store_pc; | |
4390 | } | |
4391 | ||
4392 | return 0; | |
4393 | } | |
4394 | ||
4395 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden | |
4396 | for Linux, where some SVC instructions must be treated specially. */ | |
4397 | ||
4398 | static void | |
4399 | cleanup_svc (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, | |
4400 | struct displaced_step_closure *dsc) | |
4401 | { | |
4402 | CORE_ADDR from = dsc->insn_addr; | |
4403 | CORE_ADDR resume_addr = from + 4; | |
4404 | ||
4405 | if (debug_displaced) | |
4406 | fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at " | |
4407 | "%.8lx\n", (unsigned long) resume_addr); | |
4408 | ||
4409 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
4410 | } | |
4411 | ||
4412 | static int | |
4413 | copy_svc (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, | |
4414 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4415 | { | |
4416 | CORE_ADDR from = dsc->insn_addr; | |
4417 | ||
4418 | /* Allow OS-specific code to override SVC handling. */ | |
4419 | if (dsc->u.svc.copy_svc_os) | |
4420 | return dsc->u.svc.copy_svc_os (gdbarch, insn, to, regs, dsc); | |
4421 | ||
4422 | if (debug_displaced) | |
4423 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n", | |
4424 | (unsigned long) insn); | |
4425 | ||
4426 | /* Preparation: none. | |
4427 | Insn: unmodified svc. | |
4428 | Cleanup: pc <- insn_addr + 4. */ | |
4429 | ||
4430 | dsc->modinsn[0] = insn; | |
4431 | ||
4432 | dsc->cleanup = &cleanup_svc; | |
4433 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
4434 | instruction. */ | |
4435 | dsc->wrote_to_pc = 1; | |
4436 | ||
4437 | return 0; | |
4438 | } | |
4439 | ||
4440 | /* Copy undefined instructions. */ | |
4441 | ||
4442 | static int | |
4443 | copy_undef (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, | |
4444 | struct displaced_step_closure *dsc) | |
4445 | { | |
4446 | if (debug_displaced) | |
4447 | fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn %.8lx\n", | |
4448 | (unsigned long) insn); | |
4449 | ||
4450 | dsc->modinsn[0] = insn; | |
4451 | ||
4452 | return 0; | |
4453 | } | |
4454 | ||
4455 | /* Copy unpredictable instructions. */ | |
4456 | ||
4457 | static int | |
4458 | copy_unpred (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, | |
4459 | struct displaced_step_closure *dsc) | |
4460 | { | |
4461 | if (debug_displaced) | |
4462 | fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn " | |
4463 | "%.8lx\n", (unsigned long) insn); | |
4464 | ||
4465 | dsc->modinsn[0] = insn; | |
4466 | ||
4467 | return 0; | |
4468 | } | |
4469 | ||
4470 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
4471 | the presentation in the ARM ARM. */ | |
4472 | ||
4473 | static int | |
4474 | decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, | |
4475 | struct regcache *regs, | |
4476 | struct displaced_step_closure *dsc) | |
4477 | { | |
4478 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
4479 | unsigned int rn = bits (insn, 16, 19); | |
4480 | ||
4481 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0) | |
4482 | return copy_unmodified (gdbarch, insn, "cps", dsc); | |
4483 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1) | |
4484 | return copy_unmodified (gdbarch, insn, "setend", dsc); | |
4485 | else if ((op1 & 0x60) == 0x20) | |
4486 | return copy_unmodified (gdbarch, insn, "neon dataproc", dsc); | |
4487 | else if ((op1 & 0x71) == 0x40) | |
4488 | return copy_unmodified (gdbarch, insn, "neon elt/struct load/store", dsc); | |
4489 | else if ((op1 & 0x77) == 0x41) | |
4490 | return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); | |
4491 | else if ((op1 & 0x77) == 0x45) | |
4492 | return copy_preload (gdbarch, insn, regs, dsc); /* pli. */ | |
4493 | else if ((op1 & 0x77) == 0x51) | |
4494 | { | |
4495 | if (rn != 0xf) | |
4496 | return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ | |
4497 | else | |
4498 | return copy_unpred (gdbarch, insn, dsc); | |
4499 | } | |
4500 | else if ((op1 & 0x77) == 0x55) | |
4501 | return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ | |
4502 | else if (op1 == 0x57) | |
4503 | switch (op2) | |
4504 | { | |
4505 | case 0x1: return copy_unmodified (gdbarch, insn, "clrex", dsc); | |
4506 | case 0x4: return copy_unmodified (gdbarch, insn, "dsb", dsc); | |
4507 | case 0x5: return copy_unmodified (gdbarch, insn, "dmb", dsc); | |
4508 | case 0x6: return copy_unmodified (gdbarch, insn, "isb", dsc); | |
4509 | default: return copy_unpred (gdbarch, insn, dsc); | |
4510 | } | |
4511 | else if ((op1 & 0x63) == 0x43) | |
4512 | return copy_unpred (gdbarch, insn, dsc); | |
4513 | else if ((op2 & 0x1) == 0x0) | |
4514 | switch (op1 & ~0x80) | |
4515 | { | |
4516 | case 0x61: | |
4517 | return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); | |
4518 | case 0x65: | |
4519 | return copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ | |
4520 | case 0x71: case 0x75: | |
4521 | /* pld/pldw reg. */ | |
4522 | return copy_preload_reg (gdbarch, insn, regs, dsc); | |
4523 | case 0x63: case 0x67: case 0x73: case 0x77: | |
4524 | return copy_unpred (gdbarch, insn, dsc); | |
4525 | default: | |
4526 | return copy_undef (gdbarch, insn, dsc); | |
4527 | } | |
4528 | else | |
4529 | return copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ | |
4530 | } | |
4531 | ||
4532 | static int | |
4533 | decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, | |
4534 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4535 | { | |
4536 | if (bit (insn, 27) == 0) | |
4537 | return decode_misc_memhint_neon (gdbarch, insn, regs, dsc); | |
4538 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ | |
4539 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
4540 | { | |
4541 | case 0x0: case 0x2: | |
4542 | return copy_unmodified (gdbarch, insn, "srs", dsc); | |
4543 | ||
4544 | case 0x1: case 0x3: | |
4545 | return copy_unmodified (gdbarch, insn, "rfe", dsc); | |
4546 | ||
4547 | case 0x4: case 0x5: case 0x6: case 0x7: | |
4548 | return copy_b_bl_blx (gdbarch, insn, regs, dsc); | |
4549 | ||
4550 | case 0x8: | |
4551 | switch ((insn & 0xe00000) >> 21) | |
4552 | { | |
4553 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
4554 | /* stc/stc2. */ | |
4555 | return copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4556 | ||
4557 | case 0x2: | |
4558 | return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); | |
4559 | ||
4560 | default: | |
4561 | return copy_undef (gdbarch, insn, dsc); | |
4562 | } | |
4563 | ||
4564 | case 0x9: | |
4565 | { | |
4566 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
4567 | switch ((insn & 0xe00000) >> 21) | |
4568 | { | |
4569 | case 0x1: case 0x3: | |
4570 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
4571 | return rn_f ? copy_undef (gdbarch, insn, dsc) | |
4572 | : copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4573 | ||
4574 | case 0x2: | |
4575 | return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); | |
4576 | ||
4577 | case 0x4: case 0x5: case 0x6: case 0x7: | |
4578 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
4579 | return rn_f ? copy_copro_load_store (gdbarch, insn, regs, dsc) | |
4580 | : copy_undef (gdbarch, insn, dsc); | |
4581 | ||
4582 | default: | |
4583 | return copy_undef (gdbarch, insn, dsc); | |
4584 | } | |
4585 | } | |
4586 | ||
4587 | case 0xa: | |
4588 | return copy_unmodified (gdbarch, insn, "stc/stc2", dsc); | |
4589 | ||
4590 | case 0xb: | |
4591 | if (bits (insn, 16, 19) == 0xf) | |
4592 | /* ldc/ldc2 lit. */ | |
4593 | return copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4594 | else | |
4595 | return copy_undef (gdbarch, insn, dsc); | |
4596 | ||
4597 | case 0xc: | |
4598 | if (bit (insn, 4)) | |
4599 | return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); | |
4600 | else | |
4601 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); | |
4602 | ||
4603 | case 0xd: | |
4604 | if (bit (insn, 4)) | |
4605 | return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); | |
4606 | else | |
4607 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); | |
4608 | ||
4609 | default: | |
4610 | return copy_undef (gdbarch, insn, dsc); | |
4611 | } | |
4612 | } | |
4613 | ||
4614 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
4615 | ||
4616 | static int | |
4617 | decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, | |
4618 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4619 | { | |
4620 | unsigned int op2 = bits (insn, 4, 6); | |
4621 | unsigned int op = bits (insn, 21, 22); | |
4622 | unsigned int op1 = bits (insn, 16, 19); | |
4623 | ||
4624 | switch (op2) | |
4625 | { | |
4626 | case 0x0: | |
4627 | return copy_unmodified (gdbarch, insn, "mrs/msr", dsc); | |
4628 | ||
4629 | case 0x1: | |
4630 | if (op == 0x1) /* bx. */ | |
4631 | return copy_bx_blx_reg (gdbarch, insn, regs, dsc); | |
4632 | else if (op == 0x3) | |
4633 | return copy_unmodified (gdbarch, insn, "clz", dsc); | |
4634 | else | |
4635 | return copy_undef (gdbarch, insn, dsc); | |
4636 | ||
4637 | case 0x2: | |
4638 | if (op == 0x1) | |
4639 | /* Not really supported. */ | |
4640 | return copy_unmodified (gdbarch, insn, "bxj", dsc); | |
4641 | else | |
4642 | return copy_undef (gdbarch, insn, dsc); | |
4643 | ||
4644 | case 0x3: | |
4645 | if (op == 0x1) | |
4646 | return copy_bx_blx_reg (gdbarch, insn, regs, dsc); /* blx register. */ | |
4647 | else | |
4648 | return copy_undef (gdbarch, insn, dsc); | |
4649 | ||
4650 | case 0x5: | |
4651 | return copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); | |
4652 | ||
4653 | case 0x7: | |
4654 | if (op == 0x1) | |
4655 | return copy_unmodified (gdbarch, insn, "bkpt", dsc); | |
4656 | else if (op == 0x3) | |
4657 | /* Not really supported. */ | |
4658 | return copy_unmodified (gdbarch, insn, "smc", dsc); | |
4659 | ||
4660 | default: | |
4661 | return copy_undef (gdbarch, insn, dsc); | |
4662 | } | |
4663 | } | |
4664 | ||
4665 | static int | |
4666 | decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
4667 | struct displaced_step_closure *dsc) | |
4668 | { | |
4669 | if (bit (insn, 25)) | |
4670 | switch (bits (insn, 20, 24)) | |
4671 | { | |
4672 | case 0x10: | |
4673 | return copy_unmodified (gdbarch, insn, "movw", dsc); | |
4674 | ||
4675 | case 0x14: | |
4676 | return copy_unmodified (gdbarch, insn, "movt", dsc); | |
4677 | ||
4678 | case 0x12: case 0x16: | |
4679 | return copy_unmodified (gdbarch, insn, "msr imm", dsc); | |
4680 | ||
4681 | default: | |
4682 | return copy_alu_imm (gdbarch, insn, regs, dsc); | |
4683 | } | |
4684 | else | |
4685 | { | |
4686 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
4687 | ||
4688 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
4689 | return copy_alu_reg (gdbarch, insn, regs, dsc); | |
4690 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) | |
4691 | return copy_alu_shifted_reg (gdbarch, insn, regs, dsc); | |
4692 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) | |
4693 | return decode_miscellaneous (gdbarch, insn, regs, dsc); | |
4694 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) | |
4695 | return copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); | |
4696 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) | |
4697 | return copy_unmodified (gdbarch, insn, "mul/mla", dsc); | |
4698 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) | |
4699 | return copy_unmodified (gdbarch, insn, "synch", dsc); | |
4700 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) | |
4701 | /* 2nd arg means "unpriveleged". */ | |
4702 | return copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, | |
4703 | dsc); | |
4704 | } | |
4705 | ||
4706 | /* Should be unreachable. */ | |
4707 | return 1; | |
4708 | } | |
4709 | ||
4710 | static int | |
4711 | decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, | |
4712 | struct regcache *regs, | |
4713 | struct displaced_step_closure *dsc) | |
4714 | { | |
4715 | int a = bit (insn, 25), b = bit (insn, 4); | |
4716 | uint32_t op1 = bits (insn, 20, 24); | |
4717 | int rn_f = bits (insn, 16, 19) == 0xf; | |
4718 | ||
4719 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
4720 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
4721 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 0); | |
4722 | else if ((!a && (op1 & 0x17) == 0x02) | |
4723 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
4724 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 1); | |
4725 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) | |
4726 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
4727 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 0); | |
4728 | else if ((!a && (op1 & 0x17) == 0x03) | |
4729 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
4730 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 1); | |
4731 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) | |
4732 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
4733 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); | |
4734 | else if ((!a && (op1 & 0x17) == 0x06) | |
4735 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
4736 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); | |
4737 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) | |
4738 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
4739 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); | |
4740 | else if ((!a && (op1 & 0x17) == 0x07) | |
4741 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
4742 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); | |
4743 | ||
4744 | /* Should be unreachable. */ | |
4745 | return 1; | |
4746 | } | |
4747 | ||
4748 | static int | |
4749 | decode_media (struct gdbarch *gdbarch, uint32_t insn, | |
4750 | struct displaced_step_closure *dsc) | |
4751 | { | |
4752 | switch (bits (insn, 20, 24)) | |
4753 | { | |
4754 | case 0x00: case 0x01: case 0x02: case 0x03: | |
4755 | return copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); | |
4756 | ||
4757 | case 0x04: case 0x05: case 0x06: case 0x07: | |
4758 | return copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); | |
4759 | ||
4760 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
4761 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
4762 | return copy_unmodified (gdbarch, insn, | |
4763 | "decode/pack/unpack/saturate/reverse", dsc); | |
4764 | ||
4765 | case 0x18: | |
4766 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
4767 | { | |
4768 | if (bits (insn, 12, 15) == 0xf) | |
4769 | return copy_unmodified (gdbarch, insn, "usad8", dsc); | |
4770 | else | |
4771 | return copy_unmodified (gdbarch, insn, "usada8", dsc); | |
4772 | } | |
4773 | else | |
4774 | return copy_undef (gdbarch, insn, dsc); | |
4775 | ||
4776 | case 0x1a: case 0x1b: | |
4777 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
4778 | return copy_unmodified (gdbarch, insn, "sbfx", dsc); | |
4779 | else | |
4780 | return copy_undef (gdbarch, insn, dsc); | |
4781 | ||
4782 | case 0x1c: case 0x1d: | |
4783 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
4784 | { | |
4785 | if (bits (insn, 0, 3) == 0xf) | |
4786 | return copy_unmodified (gdbarch, insn, "bfc", dsc); | |
4787 | else | |
4788 | return copy_unmodified (gdbarch, insn, "bfi", dsc); | |
4789 | } | |
4790 | else | |
4791 | return copy_undef (gdbarch, insn, dsc); | |
4792 | ||
4793 | case 0x1e: case 0x1f: | |
4794 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
4795 | return copy_unmodified (gdbarch, insn, "ubfx", dsc); | |
4796 | else | |
4797 | return copy_undef (gdbarch, insn, dsc); | |
4798 | } | |
4799 | ||
4800 | /* Should be unreachable. */ | |
4801 | return 1; | |
4802 | } | |
4803 | ||
4804 | static int | |
4805 | decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn, | |
4806 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4807 | { | |
4808 | if (bit (insn, 25)) | |
4809 | return copy_b_bl_blx (gdbarch, insn, regs, dsc); | |
4810 | else | |
4811 | return copy_block_xfer (gdbarch, insn, regs, dsc); | |
4812 | } | |
4813 | ||
4814 | static int | |
4815 | decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, | |
4816 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4817 | { | |
4818 | unsigned int opcode = bits (insn, 20, 24); | |
4819 | ||
4820 | switch (opcode) | |
4821 | { | |
4822 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
4823 | return copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); | |
4824 | ||
4825 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
4826 | case 0x12: case 0x16: | |
4827 | return copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); | |
4828 | ||
4829 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
4830 | case 0x13: case 0x17: | |
4831 | return copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); | |
4832 | ||
4833 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
4834 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
4835 | /* Note: no writeback for these instructions. Bit 25 will always be | |
4836 | zero though (via caller), so the following works OK. */ | |
4837 | return copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4838 | } | |
4839 | ||
4840 | /* Should be unreachable. */ | |
4841 | return 1; | |
4842 | } | |
4843 | ||
4844 | static int | |
4845 | decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, | |
4846 | struct regcache *regs, struct displaced_step_closure *dsc) | |
4847 | { | |
4848 | unsigned int op1 = bits (insn, 20, 25); | |
4849 | int op = bit (insn, 4); | |
4850 | unsigned int coproc = bits (insn, 8, 11); | |
4851 | unsigned int rn = bits (insn, 16, 19); | |
4852 | ||
4853 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
4854 | return decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); | |
4855 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 | |
4856 | && (coproc & 0xe) != 0xa) | |
4857 | /* stc/stc2. */ | |
4858 | return copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4859 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 | |
4860 | && (coproc & 0xe) != 0xa) | |
4861 | /* ldc/ldc2 imm/lit. */ | |
4862 | return copy_copro_load_store (gdbarch, insn, regs, dsc); | |
4863 | else if ((op1 & 0x3e) == 0x00) | |
4864 | return copy_undef (gdbarch, insn, dsc); | |
4865 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) | |
4866 | return copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); | |
4867 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) | |
4868 | return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); | |
4869 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) | |
4870 | return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); | |
4871 | else if ((op1 & 0x30) == 0x20 && !op) | |
4872 | { | |
4873 | if ((coproc & 0xe) == 0xa) | |
4874 | return copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); | |
4875 | else | |
4876 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); | |
4877 | } | |
4878 | else if ((op1 & 0x30) == 0x20 && op) | |
4879 | return copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); | |
4880 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) | |
4881 | return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); | |
4882 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) | |
4883 | return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); | |
4884 | else if ((op1 & 0x30) == 0x30) | |
4885 | return copy_svc (gdbarch, insn, to, regs, dsc); | |
4886 | else | |
4887 | return copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ | |
4888 | } | |
4889 | ||
4890 | void | |
4891 | arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn, | |
4892 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs, | |
4893 | struct displaced_step_closure *dsc) | |
4894 | { | |
4895 | int err = 0; | |
4896 | ||
4897 | if (!displaced_in_arm_mode (regs)) | |
4898 | error (_("Displaced stepping is only supported in ARM mode")); | |
4899 | ||
4900 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
4901 | here and override below if/when necessary. */ | |
4902 | dsc->numinsns = 1; | |
4903 | dsc->insn_addr = from; | |
4904 | dsc->scratch_base = to; | |
4905 | dsc->cleanup = NULL; | |
4906 | dsc->wrote_to_pc = 0; | |
4907 | ||
4908 | if ((insn & 0xf0000000) == 0xf0000000) | |
4909 | err = decode_unconditional (gdbarch, insn, regs, dsc); | |
4910 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) | |
4911 | { | |
4912 | case 0x0: case 0x1: case 0x2: case 0x3: | |
4913 | err = decode_dp_misc (gdbarch, insn, regs, dsc); | |
4914 | break; | |
4915 | ||
4916 | case 0x4: case 0x5: case 0x6: | |
4917 | err = decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); | |
4918 | break; | |
4919 | ||
4920 | case 0x7: | |
4921 | err = decode_media (gdbarch, insn, dsc); | |
4922 | break; | |
4923 | ||
4924 | case 0x8: case 0x9: case 0xa: case 0xb: | |
4925 | err = decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); | |
4926 | break; | |
4927 | ||
4928 | case 0xc: case 0xd: case 0xe: case 0xf: | |
4929 | err = decode_svc_copro (gdbarch, insn, to, regs, dsc); | |
4930 | break; | |
4931 | } | |
4932 | ||
4933 | if (err) | |
4934 | internal_error (__FILE__, __LINE__, | |
4935 | _("arm_process_displaced_insn: Instruction decode error")); | |
4936 | } | |
4937 | ||
4938 | /* Actually set up the scratch space for a displaced instruction. */ | |
4939 | ||
4940 | void | |
4941 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
4942 | CORE_ADDR to, struct displaced_step_closure *dsc) | |
4943 | { | |
4944 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4945 | unsigned int i; | |
4946 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4947 | ||
4948 | /* Poke modified instruction(s). */ | |
4949 | for (i = 0; i < dsc->numinsns; i++) | |
4950 | { | |
4951 | if (debug_displaced) | |
4952 | fprintf_unfiltered (gdb_stdlog, "displaced: writing insn %.8lx at " | |
4953 | "%.8lx\n", (unsigned long) dsc->modinsn[i], | |
4954 | (unsigned long) to + i * 4); | |
4955 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, | |
4956 | dsc->modinsn[i]); | |
4957 | } | |
4958 | ||
4959 | /* Put breakpoint afterwards. */ | |
4960 | write_memory (to + dsc->numinsns * 4, tdep->arm_breakpoint, | |
4961 | tdep->arm_breakpoint_size); | |
4962 | ||
4963 | if (debug_displaced) | |
4964 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
4965 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
4966 | } | |
4967 | ||
4968 | /* Entry point for copying an instruction into scratch space for displaced | |
4969 | stepping. */ | |
4970 | ||
4971 | struct displaced_step_closure * | |
4972 | arm_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
4973 | CORE_ADDR from, CORE_ADDR to, | |
4974 | struct regcache *regs) | |
4975 | { | |
4976 | struct displaced_step_closure *dsc | |
4977 | = xmalloc (sizeof (struct displaced_step_closure)); | |
4978 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4979 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); | |
4980 | ||
4981 | if (debug_displaced) | |
4982 | fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " | |
4983 | "at %.8lx\n", (unsigned long) insn, | |
4984 | (unsigned long) from); | |
4985 | ||
4986 | arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc); | |
4987 | arm_displaced_init_closure (gdbarch, from, to, dsc); | |
4988 | ||
4989 | return dsc; | |
4990 | } | |
4991 | ||
4992 | /* Entry point for cleaning things up after a displaced instruction has been | |
4993 | single-stepped. */ | |
4994 | ||
4995 | void | |
4996 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
4997 | struct displaced_step_closure *dsc, | |
4998 | CORE_ADDR from, CORE_ADDR to, | |
4999 | struct regcache *regs) | |
5000 | { | |
5001 | if (dsc->cleanup) | |
5002 | dsc->cleanup (gdbarch, regs, dsc); | |
5003 | ||
5004 | if (!dsc->wrote_to_pc) | |
5005 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, dsc->insn_addr + 4); | |
5006 | } | |
5007 | ||
5008 | #include "bfd-in2.h" | |
5009 | #include "libcoff.h" | |
5010 | ||
5011 | static int | |
5012 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
5013 | { | |
5014 | if (arm_pc_is_thumb (memaddr)) | |
5015 | { | |
5016 | static asymbol *asym; | |
5017 | static combined_entry_type ce; | |
5018 | static struct coff_symbol_struct csym; | |
5019 | static struct bfd fake_bfd; | |
5020 | static bfd_target fake_target; | |
5021 | ||
5022 | if (csym.native == NULL) | |
5023 | { | |
5024 | /* Create a fake symbol vector containing a Thumb symbol. | |
5025 | This is solely so that the code in print_insn_little_arm() | |
5026 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
5027 | the presence of a Thumb symbol and switch to decoding | |
5028 | Thumb instructions. */ | |
5029 | ||
5030 | fake_target.flavour = bfd_target_coff_flavour; | |
5031 | fake_bfd.xvec = &fake_target; | |
5032 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
5033 | csym.native = &ce; | |
5034 | csym.symbol.the_bfd = &fake_bfd; | |
5035 | csym.symbol.name = "fake"; | |
5036 | asym = (asymbol *) & csym; | |
5037 | } | |
5038 | ||
5039 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
5040 | info->symbols = &asym; | |
5041 | } | |
5042 | else | |
5043 | info->symbols = NULL; | |
5044 | ||
5045 | if (info->endian == BFD_ENDIAN_BIG) | |
5046 | return print_insn_big_arm (memaddr, info); | |
5047 | else | |
5048 | return print_insn_little_arm (memaddr, info); | |
5049 | } | |
5050 | ||
5051 | /* The following define instruction sequences that will cause ARM | |
5052 | cpu's to take an undefined instruction trap. These are used to | |
5053 | signal a breakpoint to GDB. | |
5054 | ||
5055 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
5056 | modes. A different instruction is required for each mode. The ARM | |
5057 | cpu's can also be big or little endian. Thus four different | |
5058 | instructions are needed to support all cases. | |
5059 | ||
5060 | Note: ARMv4 defines several new instructions that will take the | |
5061 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
5062 | not in fact add the new instructions. The new undefined | |
5063 | instructions in ARMv4 are all instructions that had no defined | |
5064 | behaviour in earlier chips. There is no guarantee that they will | |
5065 | raise an exception, but may be treated as NOP's. In practice, it | |
5066 | may only safe to rely on instructions matching: | |
5067 | ||
5068 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
5069 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
5070 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
5071 | ||
5072 | Even this may only true if the condition predicate is true. The | |
5073 | following use a condition predicate of ALWAYS so it is always TRUE. | |
5074 | ||
5075 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
5076 | and NetBSD all use a software interrupt rather than an undefined | |
5077 | instruction to force a trap. This can be handled by by the | |
5078 | abi-specific code during establishment of the gdbarch vector. */ | |
5079 | ||
5080 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
5081 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
5082 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
5083 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
5084 | ||
5085 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
5086 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
5087 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
5088 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
5089 | ||
5090 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses | |
5091 | the program counter value to determine whether a 16-bit or 32-bit | |
5092 | breakpoint should be used. It returns a pointer to a string of | |
5093 | bytes that encode a breakpoint instruction, stores the length of | |
5094 | the string to *lenptr, and adjusts the program counter (if | |
5095 | necessary) to point to the actual memory location where the | |
5096 | breakpoint should be inserted. */ | |
5097 | ||
5098 | static const unsigned char * | |
5099 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) | |
5100 | { | |
5101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
177321bd | 5102 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b JB |
5103 | |
5104 | if (arm_pc_is_thumb (*pcptr)) | |
5105 | { | |
5106 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
5107 | |
5108 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
5109 | check whether we are replacing a 32-bit instruction. */ | |
5110 | if (tdep->thumb2_breakpoint != NULL) | |
5111 | { | |
5112 | gdb_byte buf[2]; | |
5113 | if (target_read_memory (*pcptr, buf, 2) == 0) | |
5114 | { | |
5115 | unsigned short inst1; | |
5116 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
5117 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) | |
5118 | { | |
5119 | *lenptr = tdep->thumb2_breakpoint_size; | |
5120 | return tdep->thumb2_breakpoint; | |
5121 | } | |
5122 | } | |
5123 | } | |
5124 | ||
cca44b1b JB |
5125 | *lenptr = tdep->thumb_breakpoint_size; |
5126 | return tdep->thumb_breakpoint; | |
5127 | } | |
5128 | else | |
5129 | { | |
5130 | *lenptr = tdep->arm_breakpoint_size; | |
5131 | return tdep->arm_breakpoint; | |
5132 | } | |
5133 | } | |
5134 | ||
177321bd DJ |
5135 | static void |
5136 | arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
5137 | int *kindptr) | |
5138 | { | |
5139 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5140 | ||
5141 | arm_breakpoint_from_pc (gdbarch, pcptr, kindptr); | |
5142 | ||
5143 | if (arm_pc_is_thumb (*pcptr) && *kindptr == 4) | |
5144 | /* The documented magic value for a 32-bit Thumb-2 breakpoint, so | |
5145 | that this is not confused with a 32-bit ARM breakpoint. */ | |
5146 | *kindptr = 3; | |
5147 | } | |
5148 | ||
cca44b1b JB |
5149 | /* Extract from an array REGBUF containing the (raw) register state a |
5150 | function return value of type TYPE, and copy that, in virtual | |
5151 | format, into VALBUF. */ | |
5152 | ||
5153 | static void | |
5154 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
5155 | gdb_byte *valbuf) | |
5156 | { | |
5157 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
5158 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5159 | ||
5160 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
5161 | { | |
5162 | switch (gdbarch_tdep (gdbarch)->fp_model) | |
5163 | { | |
5164 | case ARM_FLOAT_FPA: | |
5165 | { | |
5166 | /* The value is in register F0 in internal format. We need to | |
5167 | extract the raw value and then convert it to the desired | |
5168 | internal type. */ | |
5169 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; | |
5170 | ||
5171 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
5172 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
5173 | valbuf, gdbarch_byte_order (gdbarch)); | |
5174 | } | |
5175 | break; | |
5176 | ||
5177 | case ARM_FLOAT_SOFT_FPA: | |
5178 | case ARM_FLOAT_SOFT_VFP: | |
5179 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
5180 | not using the VFP ABI code. */ | |
5181 | case ARM_FLOAT_VFP: | |
5182 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); | |
5183 | if (TYPE_LENGTH (type) > 4) | |
5184 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
5185 | valbuf + INT_REGISTER_SIZE); | |
5186 | break; | |
5187 | ||
5188 | default: | |
5189 | internal_error | |
5190 | (__FILE__, __LINE__, | |
5191 | _("arm_extract_return_value: Floating point model not supported")); | |
5192 | break; | |
5193 | } | |
5194 | } | |
5195 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
5196 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
5197 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
5198 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
5199 | || TYPE_CODE (type) == TYPE_CODE_REF | |
5200 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
5201 | { | |
5202 | /* If the the type is a plain integer, then the access is | |
5203 | straight-forward. Otherwise we have to play around a bit more. */ | |
5204 | int len = TYPE_LENGTH (type); | |
5205 | int regno = ARM_A1_REGNUM; | |
5206 | ULONGEST tmp; | |
5207 | ||
5208 | while (len > 0) | |
5209 | { | |
5210 | /* By using store_unsigned_integer we avoid having to do | |
5211 | anything special for small big-endian values. */ | |
5212 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
5213 | store_unsigned_integer (valbuf, | |
5214 | (len > INT_REGISTER_SIZE | |
5215 | ? INT_REGISTER_SIZE : len), | |
5216 | byte_order, tmp); | |
5217 | len -= INT_REGISTER_SIZE; | |
5218 | valbuf += INT_REGISTER_SIZE; | |
5219 | } | |
5220 | } | |
5221 | else | |
5222 | { | |
5223 | /* For a structure or union the behaviour is as if the value had | |
5224 | been stored to word-aligned memory and then loaded into | |
5225 | registers with 32-bit load instruction(s). */ | |
5226 | int len = TYPE_LENGTH (type); | |
5227 | int regno = ARM_A1_REGNUM; | |
5228 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; | |
5229 | ||
5230 | while (len > 0) | |
5231 | { | |
5232 | regcache_cooked_read (regs, regno++, tmpbuf); | |
5233 | memcpy (valbuf, tmpbuf, | |
5234 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); | |
5235 | len -= INT_REGISTER_SIZE; | |
5236 | valbuf += INT_REGISTER_SIZE; | |
5237 | } | |
5238 | } | |
5239 | } | |
5240 | ||
5241 | ||
5242 | /* Will a function return an aggregate type in memory or in a | |
5243 | register? Return 0 if an aggregate type can be returned in a | |
5244 | register, 1 if it must be returned in memory. */ | |
5245 | ||
5246 | static int | |
5247 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
5248 | { | |
5249 | int nRc; | |
5250 | enum type_code code; | |
5251 | ||
5252 | CHECK_TYPEDEF (type); | |
5253 | ||
5254 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
5255 | registers. For an aggregate type to be integer like, its size | |
5256 | must be less than or equal to INT_REGISTER_SIZE and the | |
5257 | offset of each addressable subfield must be zero. Note that bit | |
5258 | fields are not addressable, and all addressable subfields of | |
5259 | unions always start at offset zero. | |
5260 | ||
5261 | This function is based on the behaviour of GCC 2.95.1. | |
5262 | See: gcc/arm.c: arm_return_in_memory() for details. | |
5263 | ||
5264 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
5265 | parameters correctly for a function returning the following | |
5266 | structure: struct { float f;}; This should be returned in memory, | |
5267 | not a register. Richard Earnshaw sent me a patch, but I do not | |
5268 | know of any way to detect if a function like the above has been | |
5269 | compiled with the correct calling convention. */ | |
5270 | ||
5271 | /* All aggregate types that won't fit in a register must be returned | |
5272 | in memory. */ | |
5273 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) | |
5274 | { | |
5275 | return 1; | |
5276 | } | |
5277 | ||
5278 | /* The AAPCS says all aggregates not larger than a word are returned | |
5279 | in a register. */ | |
5280 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
5281 | return 0; | |
5282 | ||
5283 | /* The only aggregate types that can be returned in a register are | |
5284 | structs and unions. Arrays must be returned in memory. */ | |
5285 | code = TYPE_CODE (type); | |
5286 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
5287 | { | |
5288 | return 1; | |
5289 | } | |
5290 | ||
5291 | /* Assume all other aggregate types can be returned in a register. | |
5292 | Run a check for structures, unions and arrays. */ | |
5293 | nRc = 0; | |
5294 | ||
5295 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
5296 | { | |
5297 | int i; | |
5298 | /* Need to check if this struct/union is "integer" like. For | |
5299 | this to be true, its size must be less than or equal to | |
5300 | INT_REGISTER_SIZE and the offset of each addressable | |
5301 | subfield must be zero. Note that bit fields are not | |
5302 | addressable, and unions always start at offset zero. If any | |
5303 | of the subfields is a floating point type, the struct/union | |
5304 | cannot be an integer type. */ | |
5305 | ||
5306 | /* For each field in the object, check: | |
5307 | 1) Is it FP? --> yes, nRc = 1; | |
67255d04 RE |
5308 | 2) Is it addressable (bitpos != 0) and |
5309 | not packed (bitsize == 0)? | |
5310 | --> yes, nRc = 1 | |
5311 | */ | |
5312 | ||
5313 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
5314 | { | |
5315 | enum type_code field_type_code; | |
44e1a9eb | 5316 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
5317 | |
5318 | /* Is it a floating point type field? */ | |
5319 | if (field_type_code == TYPE_CODE_FLT) | |
5320 | { | |
5321 | nRc = 1; | |
5322 | break; | |
5323 | } | |
5324 | ||
5325 | /* If bitpos != 0, then we have to care about it. */ | |
5326 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
5327 | { | |
5328 | /* Bitfields are not addressable. If the field bitsize is | |
5329 | zero, then the field is not packed. Hence it cannot be | |
5330 | a bitfield or any other packed type. */ | |
5331 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
5332 | { | |
5333 | nRc = 1; | |
5334 | break; | |
5335 | } | |
5336 | } | |
5337 | } | |
5338 | } | |
5339 | ||
5340 | return nRc; | |
5341 | } | |
5342 | ||
34e8f22d RE |
5343 | /* Write into appropriate registers a function return value of type |
5344 | TYPE, given in virtual format. */ | |
5345 | ||
5346 | static void | |
b508a996 | 5347 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 5348 | const gdb_byte *valbuf) |
34e8f22d | 5349 | { |
be8626e0 | 5350 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 5351 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 5352 | |
34e8f22d RE |
5353 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
5354 | { | |
7a5ea0d4 | 5355 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 5356 | |
be8626e0 | 5357 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
5358 | { |
5359 | case ARM_FLOAT_FPA: | |
5360 | ||
be8626e0 MD |
5361 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
5362 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 5363 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
5364 | break; |
5365 | ||
fd50bc42 | 5366 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 5367 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
5368 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
5369 | not using the VFP ABI code. */ | |
5370 | case ARM_FLOAT_VFP: | |
b508a996 RE |
5371 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
5372 | if (TYPE_LENGTH (type) > 4) | |
5373 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 5374 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
5375 | break; |
5376 | ||
5377 | default: | |
5378 | internal_error | |
5379 | (__FILE__, __LINE__, | |
edefbb7c | 5380 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
5381 | break; |
5382 | } | |
34e8f22d | 5383 | } |
b508a996 RE |
5384 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
5385 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
5386 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
5387 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
5388 | || TYPE_CODE (type) == TYPE_CODE_REF | |
5389 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
5390 | { | |
5391 | if (TYPE_LENGTH (type) <= 4) | |
5392 | { | |
5393 | /* Values of one word or less are zero/sign-extended and | |
5394 | returned in r0. */ | |
7a5ea0d4 | 5395 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
5396 | LONGEST val = unpack_long (type, valbuf); |
5397 | ||
e17a4113 | 5398 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
b508a996 RE |
5399 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
5400 | } | |
5401 | else | |
5402 | { | |
5403 | /* Integral values greater than one word are stored in consecutive | |
5404 | registers starting with r0. This will always be a multiple of | |
5405 | the regiser size. */ | |
5406 | int len = TYPE_LENGTH (type); | |
5407 | int regno = ARM_A1_REGNUM; | |
5408 | ||
5409 | while (len > 0) | |
5410 | { | |
5411 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
5412 | len -= INT_REGISTER_SIZE; |
5413 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
5414 | } |
5415 | } | |
5416 | } | |
34e8f22d | 5417 | else |
b508a996 RE |
5418 | { |
5419 | /* For a structure or union the behaviour is as if the value had | |
5420 | been stored to word-aligned memory and then loaded into | |
5421 | registers with 32-bit load instruction(s). */ | |
5422 | int len = TYPE_LENGTH (type); | |
5423 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 5424 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
5425 | |
5426 | while (len > 0) | |
5427 | { | |
5428 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 5429 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 5430 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
5431 | len -= INT_REGISTER_SIZE; |
5432 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
5433 | } |
5434 | } | |
34e8f22d RE |
5435 | } |
5436 | ||
2af48f68 PB |
5437 | |
5438 | /* Handle function return values. */ | |
5439 | ||
5440 | static enum return_value_convention | |
c055b101 CV |
5441 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
5442 | struct type *valtype, struct regcache *regcache, | |
5443 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 5444 | { |
7c00367c | 5445 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
90445bd3 DJ |
5446 | enum arm_vfp_cprc_base_type vfp_base_type; |
5447 | int vfp_base_count; | |
5448 | ||
5449 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
5450 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
5451 | { | |
5452 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
5453 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
5454 | int i; | |
5455 | for (i = 0; i < vfp_base_count; i++) | |
5456 | { | |
58d6951d DJ |
5457 | if (reg_char == 'q') |
5458 | { | |
5459 | if (writebuf) | |
5460 | arm_neon_quad_write (gdbarch, regcache, i, | |
5461 | writebuf + i * unit_length); | |
5462 | ||
5463 | if (readbuf) | |
5464 | arm_neon_quad_read (gdbarch, regcache, i, | |
5465 | readbuf + i * unit_length); | |
5466 | } | |
5467 | else | |
5468 | { | |
5469 | char name_buf[4]; | |
5470 | int regnum; | |
5471 | ||
5472 | sprintf (name_buf, "%c%d", reg_char, i); | |
5473 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
5474 | strlen (name_buf)); | |
5475 | if (writebuf) | |
5476 | regcache_cooked_write (regcache, regnum, | |
5477 | writebuf + i * unit_length); | |
5478 | if (readbuf) | |
5479 | regcache_cooked_read (regcache, regnum, | |
5480 | readbuf + i * unit_length); | |
5481 | } | |
90445bd3 DJ |
5482 | } |
5483 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5484 | } | |
7c00367c | 5485 | |
2af48f68 PB |
5486 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
5487 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
5488 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
5489 | { | |
7c00367c MK |
5490 | if (tdep->struct_return == pcc_struct_return |
5491 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
5492 | return RETURN_VALUE_STRUCT_CONVENTION; |
5493 | } | |
5494 | ||
5495 | if (writebuf) | |
5496 | arm_store_return_value (valtype, regcache, writebuf); | |
5497 | ||
5498 | if (readbuf) | |
5499 | arm_extract_return_value (valtype, regcache, readbuf); | |
5500 | ||
5501 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5502 | } | |
5503 | ||
5504 | ||
9df628e0 | 5505 | static int |
60ade65d | 5506 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 5507 | { |
e17a4113 UW |
5508 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5509 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5510 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 5511 | CORE_ADDR jb_addr; |
7a5ea0d4 | 5512 | char buf[INT_REGISTER_SIZE]; |
9df628e0 | 5513 | |
60ade65d | 5514 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
5515 | |
5516 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 5517 | INT_REGISTER_SIZE)) |
9df628e0 RE |
5518 | return 0; |
5519 | ||
e17a4113 | 5520 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
5521 | return 1; |
5522 | } | |
5523 | ||
faa95490 DJ |
5524 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
5525 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
5526 | |
5527 | CORE_ADDR | |
52f729a7 | 5528 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5529 | { |
c5aa993b | 5530 | char *name; |
faa95490 | 5531 | int namelen; |
c906108c SS |
5532 | CORE_ADDR start_addr; |
5533 | ||
5534 | /* Find the starting address and name of the function containing the PC. */ | |
5535 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5536 | return 0; | |
5537 | ||
faa95490 DJ |
5538 | /* If PC is in a Thumb call or return stub, return the address of the |
5539 | target PC, which is in a register. The thunk functions are called | |
5540 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
5541 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
5542 | functions, named __ARM_call_via_r[0-7]. */ | |
5543 | if (strncmp (name, "_call_via_", 10) == 0 | |
5544 | || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0) | |
c906108c | 5545 | { |
ed9a39eb JM |
5546 | /* Use the name suffix to determine which register contains the |
5547 | target PC. */ | |
c5aa993b JM |
5548 | static char *table[15] = |
5549 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5550 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
5551 | }; | |
c906108c | 5552 | int regno; |
faa95490 | 5553 | int offset = strlen (name) - 2; |
c906108c SS |
5554 | |
5555 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 5556 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 5557 | return get_frame_register_unsigned (frame, regno); |
c906108c | 5558 | } |
ed9a39eb | 5559 | |
faa95490 DJ |
5560 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
5561 | non-interworking calls to foo. We could decode the stubs | |
5562 | to find the target but it's easier to use the symbol table. */ | |
5563 | namelen = strlen (name); | |
5564 | if (name[0] == '_' && name[1] == '_' | |
5565 | && ((namelen > 2 + strlen ("_from_thumb") | |
5566 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", | |
5567 | strlen ("_from_thumb")) == 0) | |
5568 | || (namelen > 2 + strlen ("_from_arm") | |
5569 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", | |
5570 | strlen ("_from_arm")) == 0))) | |
5571 | { | |
5572 | char *target_name; | |
5573 | int target_len = namelen - 2; | |
5574 | struct minimal_symbol *minsym; | |
5575 | struct objfile *objfile; | |
5576 | struct obj_section *sec; | |
5577 | ||
5578 | if (name[namelen - 1] == 'b') | |
5579 | target_len -= strlen ("_from_thumb"); | |
5580 | else | |
5581 | target_len -= strlen ("_from_arm"); | |
5582 | ||
5583 | target_name = alloca (target_len + 1); | |
5584 | memcpy (target_name, name + 2, target_len); | |
5585 | target_name[target_len] = '\0'; | |
5586 | ||
5587 | sec = find_pc_section (pc); | |
5588 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
5589 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
5590 | if (minsym != NULL) | |
5591 | return SYMBOL_VALUE_ADDRESS (minsym); | |
5592 | else | |
5593 | return 0; | |
5594 | } | |
5595 | ||
c5aa993b | 5596 | return 0; /* not a stub */ |
c906108c SS |
5597 | } |
5598 | ||
afd7eef0 RE |
5599 | static void |
5600 | set_arm_command (char *args, int from_tty) | |
5601 | { | |
edefbb7c AC |
5602 | printf_unfiltered (_("\ |
5603 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
5604 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
5605 | } | |
5606 | ||
5607 | static void | |
5608 | show_arm_command (char *args, int from_tty) | |
5609 | { | |
26304000 | 5610 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
5611 | } |
5612 | ||
28e97307 DJ |
5613 | static void |
5614 | arm_update_current_architecture (void) | |
fd50bc42 | 5615 | { |
28e97307 | 5616 | struct gdbarch_info info; |
fd50bc42 | 5617 | |
28e97307 | 5618 | /* If the current architecture is not ARM, we have nothing to do. */ |
1cf3db46 | 5619 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm) |
28e97307 | 5620 | return; |
fd50bc42 | 5621 | |
28e97307 DJ |
5622 | /* Update the architecture. */ |
5623 | gdbarch_info_init (&info); | |
fd50bc42 | 5624 | |
28e97307 DJ |
5625 | if (!gdbarch_update_p (info)) |
5626 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
5627 | } |
5628 | ||
5629 | static void | |
5630 | set_fp_model_sfunc (char *args, int from_tty, | |
5631 | struct cmd_list_element *c) | |
5632 | { | |
5633 | enum arm_float_model fp_model; | |
5634 | ||
5635 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
5636 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
5637 | { | |
5638 | arm_fp_model = fp_model; | |
5639 | break; | |
5640 | } | |
5641 | ||
5642 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 5643 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
5644 | current_fp_model); |
5645 | ||
28e97307 | 5646 | arm_update_current_architecture (); |
fd50bc42 RE |
5647 | } |
5648 | ||
5649 | static void | |
08546159 AC |
5650 | show_fp_model (struct ui_file *file, int from_tty, |
5651 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 5652 | { |
1cf3db46 | 5653 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
fd50bc42 | 5654 | |
28e97307 | 5655 | if (arm_fp_model == ARM_FLOAT_AUTO |
1cf3db46 | 5656 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
5657 | fprintf_filtered (file, _("\ |
5658 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
5659 | fp_model_strings[tdep->fp_model]); | |
5660 | else | |
5661 | fprintf_filtered (file, _("\ | |
5662 | The current ARM floating point model is \"%s\".\n"), | |
5663 | fp_model_strings[arm_fp_model]); | |
5664 | } | |
5665 | ||
5666 | static void | |
5667 | arm_set_abi (char *args, int from_tty, | |
5668 | struct cmd_list_element *c) | |
5669 | { | |
5670 | enum arm_abi_kind arm_abi; | |
5671 | ||
5672 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
5673 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
5674 | { | |
5675 | arm_abi_global = arm_abi; | |
5676 | break; | |
5677 | } | |
5678 | ||
5679 | if (arm_abi == ARM_ABI_LAST) | |
5680 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
5681 | arm_abi_string); | |
5682 | ||
5683 | arm_update_current_architecture (); | |
5684 | } | |
5685 | ||
5686 | static void | |
5687 | arm_show_abi (struct ui_file *file, int from_tty, | |
5688 | struct cmd_list_element *c, const char *value) | |
5689 | { | |
1cf3db46 | 5690 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
28e97307 DJ |
5691 | |
5692 | if (arm_abi_global == ARM_ABI_AUTO | |
1cf3db46 | 5693 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
5694 | fprintf_filtered (file, _("\ |
5695 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
5696 | arm_abi_strings[tdep->arm_abi]); | |
5697 | else | |
5698 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
5699 | arm_abi_string); | |
fd50bc42 RE |
5700 | } |
5701 | ||
0428b8f5 DJ |
5702 | static void |
5703 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
5704 | struct cmd_list_element *c, const char *value) | |
5705 | { | |
1cf3db46 | 5706 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
5707 | |
5708 | fprintf_filtered (file, _("\ | |
5709 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), | |
5710 | arm_fallback_mode_string); | |
5711 | } | |
5712 | ||
5713 | static void | |
5714 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
5715 | struct cmd_list_element *c, const char *value) | |
5716 | { | |
1cf3db46 | 5717 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
5718 | |
5719 | fprintf_filtered (file, _("\ | |
5720 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), | |
5721 | arm_force_mode_string); | |
5722 | } | |
5723 | ||
afd7eef0 RE |
5724 | /* If the user changes the register disassembly style used for info |
5725 | register and other commands, we have to also switch the style used | |
5726 | in opcodes for disassembly output. This function is run in the "set | |
5727 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
5728 | |
5729 | static void | |
afd7eef0 | 5730 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
5731 | struct cmd_list_element *c) |
5732 | { | |
afd7eef0 | 5733 | set_disassembly_style (); |
bc90b915 FN |
5734 | } |
5735 | \f | |
966fbf70 | 5736 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 5737 | static const char * |
d93859e2 | 5738 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 5739 | { |
58d6951d DJ |
5740 | const int num_regs = gdbarch_num_regs (gdbarch); |
5741 | ||
5742 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos | |
5743 | && i >= num_regs && i < num_regs + 32) | |
5744 | { | |
5745 | static const char *const vfp_pseudo_names[] = { | |
5746 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
5747 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
5748 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
5749 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
5750 | }; | |
5751 | ||
5752 | return vfp_pseudo_names[i - num_regs]; | |
5753 | } | |
5754 | ||
5755 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos | |
5756 | && i >= num_regs + 32 && i < num_regs + 32 + 16) | |
5757 | { | |
5758 | static const char *const neon_pseudo_names[] = { | |
5759 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", | |
5760 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
5761 | }; | |
5762 | ||
5763 | return neon_pseudo_names[i - num_regs - 32]; | |
5764 | } | |
5765 | ||
ff6f572f DJ |
5766 | if (i >= ARRAY_SIZE (arm_register_names)) |
5767 | /* These registers are only supported on targets which supply | |
5768 | an XML description. */ | |
5769 | return ""; | |
5770 | ||
966fbf70 RE |
5771 | return arm_register_names[i]; |
5772 | } | |
5773 | ||
bc90b915 | 5774 | static void |
afd7eef0 | 5775 | set_disassembly_style (void) |
bc90b915 | 5776 | { |
123dc839 | 5777 | int current; |
bc90b915 | 5778 | |
123dc839 DJ |
5779 | /* Find the style that the user wants. */ |
5780 | for (current = 0; current < num_disassembly_options; current++) | |
5781 | if (disassembly_style == valid_disassembly_styles[current]) | |
5782 | break; | |
5783 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 5784 | |
94c30b78 | 5785 | /* Synchronize the disassembler. */ |
bc90b915 FN |
5786 | set_arm_regname_option (current); |
5787 | } | |
5788 | ||
082fc60d RE |
5789 | /* Test whether the coff symbol specific value corresponds to a Thumb |
5790 | function. */ | |
5791 | ||
5792 | static int | |
5793 | coff_sym_is_thumb (int val) | |
5794 | { | |
f8bf5763 PM |
5795 | return (val == C_THUMBEXT |
5796 | || val == C_THUMBSTAT | |
5797 | || val == C_THUMBEXTFUNC | |
5798 | || val == C_THUMBSTATFUNC | |
5799 | || val == C_THUMBLABEL); | |
082fc60d RE |
5800 | } |
5801 | ||
5802 | /* arm_coff_make_msymbol_special() | |
5803 | arm_elf_make_msymbol_special() | |
5804 | ||
5805 | These functions test whether the COFF or ELF symbol corresponds to | |
5806 | an address in thumb code, and set a "special" bit in a minimal | |
5807 | symbol to indicate that it does. */ | |
5808 | ||
34e8f22d | 5809 | static void |
082fc60d RE |
5810 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
5811 | { | |
5812 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
5813 | STT_ARM_TFUNC). */ | |
5814 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
5815 | == STT_LOPROC) | |
5816 | MSYMBOL_SET_SPECIAL (msym); | |
5817 | } | |
5818 | ||
34e8f22d | 5819 | static void |
082fc60d RE |
5820 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
5821 | { | |
5822 | if (coff_sym_is_thumb (val)) | |
5823 | MSYMBOL_SET_SPECIAL (msym); | |
5824 | } | |
5825 | ||
60c5725c | 5826 | static void |
c1bd65d0 | 5827 | arm_objfile_data_free (struct objfile *objfile, void *arg) |
60c5725c DJ |
5828 | { |
5829 | struct arm_per_objfile *data = arg; | |
5830 | unsigned int i; | |
5831 | ||
5832 | for (i = 0; i < objfile->obfd->section_count; i++) | |
5833 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); | |
5834 | } | |
5835 | ||
5836 | static void | |
5837 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
5838 | asymbol *sym) | |
5839 | { | |
5840 | const char *name = bfd_asymbol_name (sym); | |
5841 | struct arm_per_objfile *data; | |
5842 | VEC(arm_mapping_symbol_s) **map_p; | |
5843 | struct arm_mapping_symbol new_map_sym; | |
5844 | ||
5845 | gdb_assert (name[0] == '$'); | |
5846 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
5847 | return; | |
5848 | ||
5849 | data = objfile_data (objfile, arm_objfile_data_key); | |
5850 | if (data == NULL) | |
5851 | { | |
5852 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, | |
5853 | struct arm_per_objfile); | |
5854 | set_objfile_data (objfile, arm_objfile_data_key, data); | |
5855 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
5856 | objfile->obfd->section_count, | |
5857 | VEC(arm_mapping_symbol_s) *); | |
5858 | } | |
5859 | map_p = &data->section_maps[bfd_get_section (sym)->index]; | |
5860 | ||
5861 | new_map_sym.value = sym->value; | |
5862 | new_map_sym.type = name[1]; | |
5863 | ||
5864 | /* Assume that most mapping symbols appear in order of increasing | |
5865 | value. If they were randomly distributed, it would be faster to | |
5866 | always push here and then sort at first use. */ | |
5867 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) | |
5868 | { | |
5869 | struct arm_mapping_symbol *prev_map_sym; | |
5870 | ||
5871 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); | |
5872 | if (prev_map_sym->value >= sym->value) | |
5873 | { | |
5874 | unsigned int idx; | |
5875 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, | |
5876 | arm_compare_mapping_symbols); | |
5877 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); | |
5878 | return; | |
5879 | } | |
5880 | } | |
5881 | ||
5882 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); | |
5883 | } | |
5884 | ||
756fe439 | 5885 | static void |
61a1198a | 5886 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 5887 | { |
61a1198a | 5888 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
5889 | |
5890 | /* If necessary, set the T bit. */ | |
5891 | if (arm_apcs_32) | |
5892 | { | |
61a1198a UW |
5893 | ULONGEST val; |
5894 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); | |
756fe439 | 5895 | if (arm_pc_is_thumb (pc)) |
b39cc962 | 5896 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
756fe439 | 5897 | else |
61a1198a | 5898 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
b39cc962 | 5899 | val & ~(ULONGEST) CPSR_T); |
756fe439 DJ |
5900 | } |
5901 | } | |
123dc839 | 5902 | |
58d6951d DJ |
5903 | /* Read the contents of a NEON quad register, by reading from two |
5904 | double registers. This is used to implement the quad pseudo | |
5905 | registers, and for argument passing in case the quad registers are | |
5906 | missing; vectors are passed in quad registers when using the VFP | |
5907 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
5908 | the quad register, in [0, 15]. */ | |
5909 | ||
5910 | static void | |
5911 | arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
5912 | int regnum, gdb_byte *buf) | |
5913 | { | |
5914 | char name_buf[4]; | |
5915 | gdb_byte reg_buf[8]; | |
5916 | int offset, double_regnum; | |
5917 | ||
5918 | sprintf (name_buf, "d%d", regnum << 1); | |
5919 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
5920 | strlen (name_buf)); | |
5921 | ||
5922 | /* d0 is always the least significant half of q0. */ | |
5923 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
5924 | offset = 8; | |
5925 | else | |
5926 | offset = 0; | |
5927 | ||
5928 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
5929 | memcpy (buf + offset, reg_buf, 8); | |
5930 | ||
5931 | offset = 8 - offset; | |
5932 | regcache_raw_read (regcache, double_regnum + 1, reg_buf); | |
5933 | memcpy (buf + offset, reg_buf, 8); | |
5934 | } | |
5935 | ||
5936 | static void | |
5937 | arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
5938 | int regnum, gdb_byte *buf) | |
5939 | { | |
5940 | const int num_regs = gdbarch_num_regs (gdbarch); | |
5941 | char name_buf[4]; | |
5942 | gdb_byte reg_buf[8]; | |
5943 | int offset, double_regnum; | |
5944 | ||
5945 | gdb_assert (regnum >= num_regs); | |
5946 | regnum -= num_regs; | |
5947 | ||
5948 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
5949 | /* Quad-precision register. */ | |
5950 | arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); | |
5951 | else | |
5952 | { | |
5953 | /* Single-precision register. */ | |
5954 | gdb_assert (regnum < 32); | |
5955 | ||
5956 | /* s0 is always the least significant half of d0. */ | |
5957 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
5958 | offset = (regnum & 1) ? 0 : 4; | |
5959 | else | |
5960 | offset = (regnum & 1) ? 4 : 0; | |
5961 | ||
5962 | sprintf (name_buf, "d%d", regnum >> 1); | |
5963 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
5964 | strlen (name_buf)); | |
5965 | ||
5966 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
5967 | memcpy (buf, reg_buf + offset, 4); | |
5968 | } | |
5969 | } | |
5970 | ||
5971 | /* Store the contents of BUF to a NEON quad register, by writing to | |
5972 | two double registers. This is used to implement the quad pseudo | |
5973 | registers, and for argument passing in case the quad registers are | |
5974 | missing; vectors are passed in quad registers when using the VFP | |
5975 | ABI, even if a NEON unit is not present. REGNUM is the index | |
5976 | of the quad register, in [0, 15]. */ | |
5977 | ||
5978 | static void | |
5979 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
5980 | int regnum, const gdb_byte *buf) | |
5981 | { | |
5982 | char name_buf[4]; | |
5983 | gdb_byte reg_buf[8]; | |
5984 | int offset, double_regnum; | |
5985 | ||
5986 | sprintf (name_buf, "d%d", regnum << 1); | |
5987 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
5988 | strlen (name_buf)); | |
5989 | ||
5990 | /* d0 is always the least significant half of q0. */ | |
5991 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
5992 | offset = 8; | |
5993 | else | |
5994 | offset = 0; | |
5995 | ||
5996 | regcache_raw_write (regcache, double_regnum, buf + offset); | |
5997 | offset = 8 - offset; | |
5998 | regcache_raw_write (regcache, double_regnum + 1, buf + offset); | |
5999 | } | |
6000 | ||
6001 | static void | |
6002 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
6003 | int regnum, const gdb_byte *buf) | |
6004 | { | |
6005 | const int num_regs = gdbarch_num_regs (gdbarch); | |
6006 | char name_buf[4]; | |
6007 | gdb_byte reg_buf[8]; | |
6008 | int offset, double_regnum; | |
6009 | ||
6010 | gdb_assert (regnum >= num_regs); | |
6011 | regnum -= num_regs; | |
6012 | ||
6013 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) | |
6014 | /* Quad-precision register. */ | |
6015 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); | |
6016 | else | |
6017 | { | |
6018 | /* Single-precision register. */ | |
6019 | gdb_assert (regnum < 32); | |
6020 | ||
6021 | /* s0 is always the least significant half of d0. */ | |
6022 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
6023 | offset = (regnum & 1) ? 0 : 4; | |
6024 | else | |
6025 | offset = (regnum & 1) ? 4 : 0; | |
6026 | ||
6027 | sprintf (name_buf, "d%d", regnum >> 1); | |
6028 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, | |
6029 | strlen (name_buf)); | |
6030 | ||
6031 | regcache_raw_read (regcache, double_regnum, reg_buf); | |
6032 | memcpy (reg_buf + offset, buf, 4); | |
6033 | regcache_raw_write (regcache, double_regnum, reg_buf); | |
6034 | } | |
6035 | } | |
6036 | ||
123dc839 DJ |
6037 | static struct value * |
6038 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
6039 | { | |
6040 | const int *reg_p = baton; | |
6041 | return value_of_register (*reg_p, frame); | |
6042 | } | |
97e03143 | 6043 | \f |
70f80edf JT |
6044 | static enum gdb_osabi |
6045 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 6046 | { |
2af48f68 | 6047 | unsigned int elfosabi; |
70f80edf | 6048 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 6049 | |
70f80edf | 6050 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 6051 | |
28e97307 DJ |
6052 | if (elfosabi == ELFOSABI_ARM) |
6053 | /* GNU tools use this value. Check note sections in this case, | |
6054 | as well. */ | |
6055 | bfd_map_over_sections (abfd, | |
6056 | generic_elf_osabi_sniff_abi_tag_sections, | |
6057 | &osabi); | |
97e03143 | 6058 | |
28e97307 | 6059 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 6060 | return osabi; |
97e03143 RE |
6061 | } |
6062 | ||
70f80edf | 6063 | \f |
da3c6d4a MS |
6064 | /* Initialize the current architecture based on INFO. If possible, |
6065 | re-use an architecture from ARCHES, which is a list of | |
6066 | architectures already created during this debugging session. | |
97e03143 | 6067 | |
da3c6d4a MS |
6068 | Called e.g. at program startup, when reading a core file, and when |
6069 | reading a binary file. */ | |
97e03143 | 6070 | |
39bbf761 RE |
6071 | static struct gdbarch * |
6072 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
6073 | { | |
97e03143 | 6074 | struct gdbarch_tdep *tdep; |
39bbf761 | 6075 | struct gdbarch *gdbarch; |
28e97307 DJ |
6076 | struct gdbarch_list *best_arch; |
6077 | enum arm_abi_kind arm_abi = arm_abi_global; | |
6078 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
6079 | struct tdesc_arch_data *tdesc_data = NULL; |
6080 | int i; | |
58d6951d DJ |
6081 | int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; |
6082 | int have_neon = 0; | |
ff6f572f | 6083 | int have_fpa_registers = 1; |
123dc839 DJ |
6084 | |
6085 | /* Check any target description for validity. */ | |
6086 | if (tdesc_has_registers (info.target_desc)) | |
6087 | { | |
6088 | /* For most registers we require GDB's default names; but also allow | |
6089 | the numeric names for sp / lr / pc, as a convenience. */ | |
6090 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
6091 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
6092 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
6093 | ||
6094 | const struct tdesc_feature *feature; | |
58d6951d | 6095 | int valid_p; |
123dc839 DJ |
6096 | |
6097 | feature = tdesc_find_feature (info.target_desc, | |
6098 | "org.gnu.gdb.arm.core"); | |
6099 | if (feature == NULL) | |
6100 | return NULL; | |
6101 | ||
6102 | tdesc_data = tdesc_data_alloc (); | |
6103 | ||
6104 | valid_p = 1; | |
6105 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
6106 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
6107 | arm_register_names[i]); | |
6108 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6109 | ARM_SP_REGNUM, | |
6110 | arm_sp_names); | |
6111 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6112 | ARM_LR_REGNUM, | |
6113 | arm_lr_names); | |
6114 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6115 | ARM_PC_REGNUM, | |
6116 | arm_pc_names); | |
6117 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6118 | ARM_PS_REGNUM, "cpsr"); | |
6119 | ||
6120 | if (!valid_p) | |
6121 | { | |
6122 | tdesc_data_cleanup (tdesc_data); | |
6123 | return NULL; | |
6124 | } | |
6125 | ||
6126 | feature = tdesc_find_feature (info.target_desc, | |
6127 | "org.gnu.gdb.arm.fpa"); | |
6128 | if (feature != NULL) | |
6129 | { | |
6130 | valid_p = 1; | |
6131 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
6132 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
6133 | arm_register_names[i]); | |
6134 | if (!valid_p) | |
6135 | { | |
6136 | tdesc_data_cleanup (tdesc_data); | |
6137 | return NULL; | |
6138 | } | |
6139 | } | |
ff6f572f DJ |
6140 | else |
6141 | have_fpa_registers = 0; | |
6142 | ||
6143 | feature = tdesc_find_feature (info.target_desc, | |
6144 | "org.gnu.gdb.xscale.iwmmxt"); | |
6145 | if (feature != NULL) | |
6146 | { | |
6147 | static const char *const iwmmxt_names[] = { | |
6148 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
6149 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
6150 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
6151 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
6152 | }; | |
6153 | ||
6154 | valid_p = 1; | |
6155 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
6156 | valid_p | |
6157 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
6158 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
6159 | ||
6160 | /* Check for the control registers, but do not fail if they | |
6161 | are missing. */ | |
6162 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
6163 | tdesc_numbered_register (feature, tdesc_data, i, | |
6164 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
6165 | ||
6166 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
6167 | valid_p | |
6168 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
6169 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
6170 | ||
6171 | if (!valid_p) | |
6172 | { | |
6173 | tdesc_data_cleanup (tdesc_data); | |
6174 | return NULL; | |
6175 | } | |
6176 | } | |
58d6951d DJ |
6177 | |
6178 | /* If we have a VFP unit, check whether the single precision registers | |
6179 | are present. If not, then we will synthesize them as pseudo | |
6180 | registers. */ | |
6181 | feature = tdesc_find_feature (info.target_desc, | |
6182 | "org.gnu.gdb.arm.vfp"); | |
6183 | if (feature != NULL) | |
6184 | { | |
6185 | static const char *const vfp_double_names[] = { | |
6186 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
6187 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
6188 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
6189 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
6190 | }; | |
6191 | ||
6192 | /* Require the double precision registers. There must be either | |
6193 | 16 or 32. */ | |
6194 | valid_p = 1; | |
6195 | for (i = 0; i < 32; i++) | |
6196 | { | |
6197 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6198 | ARM_D0_REGNUM + i, | |
6199 | vfp_double_names[i]); | |
6200 | if (!valid_p) | |
6201 | break; | |
6202 | } | |
6203 | ||
6204 | if (!valid_p && i != 16) | |
6205 | { | |
6206 | tdesc_data_cleanup (tdesc_data); | |
6207 | return NULL; | |
6208 | } | |
6209 | ||
6210 | if (tdesc_unnumbered_register (feature, "s0") == 0) | |
6211 | have_vfp_pseudos = 1; | |
6212 | ||
6213 | have_vfp_registers = 1; | |
6214 | ||
6215 | /* If we have VFP, also check for NEON. The architecture allows | |
6216 | NEON without VFP (integer vector operations only), but GDB | |
6217 | does not support that. */ | |
6218 | feature = tdesc_find_feature (info.target_desc, | |
6219 | "org.gnu.gdb.arm.neon"); | |
6220 | if (feature != NULL) | |
6221 | { | |
6222 | /* NEON requires 32 double-precision registers. */ | |
6223 | if (i != 32) | |
6224 | { | |
6225 | tdesc_data_cleanup (tdesc_data); | |
6226 | return NULL; | |
6227 | } | |
6228 | ||
6229 | /* If there are quad registers defined by the stub, use | |
6230 | their type; otherwise (normally) provide them with | |
6231 | the default type. */ | |
6232 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
6233 | have_neon_pseudos = 1; | |
6234 | ||
6235 | have_neon = 1; | |
6236 | } | |
6237 | } | |
123dc839 | 6238 | } |
39bbf761 | 6239 | |
28e97307 DJ |
6240 | /* If we have an object to base this architecture on, try to determine |
6241 | its ABI. */ | |
39bbf761 | 6242 | |
28e97307 | 6243 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 6244 | { |
6b26d61a | 6245 | int ei_osabi, e_flags; |
28e97307 | 6246 | |
4be87837 | 6247 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 6248 | { |
4be87837 DJ |
6249 | case bfd_target_aout_flavour: |
6250 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 6251 | arm_abi = ARM_ABI_APCS; |
4be87837 | 6252 | break; |
97e03143 | 6253 | |
4be87837 DJ |
6254 | case bfd_target_coff_flavour: |
6255 | /* Assume it's an old APCS-style ABI. */ | |
6256 | /* XXX WinCE? */ | |
28e97307 DJ |
6257 | arm_abi = ARM_ABI_APCS; |
6258 | break; | |
6259 | ||
6260 | case bfd_target_elf_flavour: | |
6261 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
6262 | e_flags = elf_elfheader (info.abfd)->e_flags; |
6263 | ||
28e97307 DJ |
6264 | if (ei_osabi == ELFOSABI_ARM) |
6265 | { | |
6266 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
6267 | objects. There's nowhere to tag an EABI version |
6268 | anyway, so assume APCS. */ | |
28e97307 DJ |
6269 | arm_abi = ARM_ABI_APCS; |
6270 | } | |
6271 | else if (ei_osabi == ELFOSABI_NONE) | |
6272 | { | |
6b26d61a | 6273 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
6274 | |
6275 | switch (eabi_ver) | |
6276 | { | |
6277 | case EF_ARM_EABI_UNKNOWN: | |
6278 | /* Assume GNU tools. */ | |
6279 | arm_abi = ARM_ABI_APCS; | |
6280 | break; | |
6281 | ||
6282 | case EF_ARM_EABI_VER4: | |
625b5003 | 6283 | case EF_ARM_EABI_VER5: |
28e97307 | 6284 | arm_abi = ARM_ABI_AAPCS; |
90445bd3 DJ |
6285 | /* EABI binaries default to VFP float ordering. |
6286 | They may also contain build attributes that can | |
6287 | be used to identify if the VFP argument-passing | |
6288 | ABI is in use. */ | |
2af48f68 | 6289 | if (fp_model == ARM_FLOAT_AUTO) |
90445bd3 DJ |
6290 | { |
6291 | #ifdef HAVE_ELF | |
6292 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
6293 | OBJ_ATTR_PROC, | |
6294 | Tag_ABI_VFP_args)) | |
6295 | { | |
6296 | case 0: | |
6297 | /* "The user intended FP parameter/result | |
6298 | passing to conform to AAPCS, base | |
6299 | variant". */ | |
6300 | fp_model = ARM_FLOAT_SOFT_VFP; | |
6301 | break; | |
6302 | case 1: | |
6303 | /* "The user intended FP parameter/result | |
6304 | passing to conform to AAPCS, VFP | |
6305 | variant". */ | |
6306 | fp_model = ARM_FLOAT_VFP; | |
6307 | break; | |
6308 | case 2: | |
6309 | /* "The user intended FP parameter/result | |
6310 | passing to conform to tool chain-specific | |
6311 | conventions" - we don't know any such | |
6312 | conventions, so leave it as "auto". */ | |
6313 | break; | |
6314 | default: | |
6315 | /* Attribute value not mentioned in the | |
6316 | October 2008 ABI, so leave it as | |
6317 | "auto". */ | |
6318 | break; | |
6319 | } | |
6320 | #else | |
6321 | fp_model = ARM_FLOAT_SOFT_VFP; | |
6322 | #endif | |
6323 | } | |
28e97307 DJ |
6324 | break; |
6325 | ||
6326 | default: | |
6b26d61a | 6327 | /* Leave it as "auto". */ |
28e97307 | 6328 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
6329 | break; |
6330 | } | |
6331 | } | |
6332 | ||
6333 | if (fp_model == ARM_FLOAT_AUTO) | |
6334 | { | |
6335 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
6336 | ||
6337 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
6338 | { | |
6339 | case 0: | |
6340 | /* Leave it as "auto". Strictly speaking this case | |
6341 | means FPA, but almost nobody uses that now, and | |
6342 | many toolchains fail to set the appropriate bits | |
6343 | for the floating-point model they use. */ | |
6344 | break; | |
6345 | case EF_ARM_SOFT_FLOAT: | |
6346 | fp_model = ARM_FLOAT_SOFT_FPA; | |
6347 | break; | |
6348 | case EF_ARM_VFP_FLOAT: | |
6349 | fp_model = ARM_FLOAT_VFP; | |
6350 | break; | |
6351 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
6352 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
6353 | break; |
6354 | } | |
6355 | } | |
9d4fde75 SS |
6356 | |
6357 | if (e_flags & EF_ARM_BE8) | |
6358 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
6359 | ||
4be87837 | 6360 | break; |
97e03143 | 6361 | |
4be87837 | 6362 | default: |
28e97307 | 6363 | /* Leave it as "auto". */ |
50ceaba5 | 6364 | break; |
97e03143 RE |
6365 | } |
6366 | } | |
6367 | ||
28e97307 DJ |
6368 | /* If there is already a candidate, use it. */ |
6369 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
6370 | best_arch != NULL; | |
6371 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
6372 | { | |
b8926edc DJ |
6373 | if (arm_abi != ARM_ABI_AUTO |
6374 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
6375 | continue; |
6376 | ||
b8926edc DJ |
6377 | if (fp_model != ARM_FLOAT_AUTO |
6378 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
6379 | continue; |
6380 | ||
58d6951d DJ |
6381 | /* There are various other properties in tdep that we do not |
6382 | need to check here: those derived from a target description, | |
6383 | since gdbarches with a different target description are | |
6384 | automatically disqualified. */ | |
6385 | ||
28e97307 DJ |
6386 | /* Found a match. */ |
6387 | break; | |
6388 | } | |
97e03143 | 6389 | |
28e97307 | 6390 | if (best_arch != NULL) |
123dc839 DJ |
6391 | { |
6392 | if (tdesc_data != NULL) | |
6393 | tdesc_data_cleanup (tdesc_data); | |
6394 | return best_arch->gdbarch; | |
6395 | } | |
28e97307 DJ |
6396 | |
6397 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
6398 | gdbarch = gdbarch_alloc (&info, tdep); |
6399 | ||
28e97307 DJ |
6400 | /* Record additional information about the architecture we are defining. |
6401 | These are gdbarch discriminators, like the OSABI. */ | |
6402 | tdep->arm_abi = arm_abi; | |
6403 | tdep->fp_model = fp_model; | |
ff6f572f | 6404 | tdep->have_fpa_registers = have_fpa_registers; |
58d6951d DJ |
6405 | tdep->have_vfp_registers = have_vfp_registers; |
6406 | tdep->have_vfp_pseudos = have_vfp_pseudos; | |
6407 | tdep->have_neon_pseudos = have_neon_pseudos; | |
6408 | tdep->have_neon = have_neon; | |
08216dd7 RE |
6409 | |
6410 | /* Breakpoints. */ | |
9d4fde75 | 6411 | switch (info.byte_order_for_code) |
67255d04 RE |
6412 | { |
6413 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
6414 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
6415 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
6416 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
6417 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
6418 | ||
67255d04 RE |
6419 | break; |
6420 | ||
6421 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
6422 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
6423 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
6424 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
6425 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
6426 | ||
67255d04 RE |
6427 | break; |
6428 | ||
6429 | default: | |
6430 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 6431 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
6432 | } |
6433 | ||
d7b486e7 RE |
6434 | /* On ARM targets char defaults to unsigned. */ |
6435 | set_gdbarch_char_signed (gdbarch, 0); | |
6436 | ||
cca44b1b JB |
6437 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
6438 | of additional scratch space. This setting isn't used for anything beside | |
6439 | displaced stepping at present. */ | |
6440 | set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS); | |
6441 | ||
9df628e0 | 6442 | /* This should be low enough for everything. */ |
97e03143 | 6443 | tdep->lowest_pc = 0x20; |
94c30b78 | 6444 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 6445 | |
7c00367c MK |
6446 | /* The default, for both APCS and AAPCS, is to return small |
6447 | structures in registers. */ | |
6448 | tdep->struct_return = reg_struct_return; | |
6449 | ||
2dd604e7 | 6450 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 6451 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 6452 | |
756fe439 DJ |
6453 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
6454 | ||
148754e5 | 6455 | /* Frame handling. */ |
a262aec2 | 6456 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
6457 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
6458 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
6459 | ||
eb5492fa | 6460 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 6461 | |
34e8f22d RE |
6462 | /* Address manipulation. */ |
6463 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
6464 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
6465 | ||
34e8f22d RE |
6466 | /* Advance PC across function entry code. */ |
6467 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
6468 | ||
190dce09 UW |
6469 | /* Skip trampolines. */ |
6470 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
6471 | ||
34e8f22d RE |
6472 | /* The stack grows downward. */ |
6473 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
6474 | ||
6475 | /* Breakpoint manipulation. */ | |
6476 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
177321bd DJ |
6477 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
6478 | arm_remote_breakpoint_from_pc); | |
34e8f22d RE |
6479 | |
6480 | /* Information about registers, etc. */ | |
0ba6dca9 | 6481 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
6482 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
6483 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 6484 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 6485 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 6486 | |
ff6f572f DJ |
6487 | /* This "info float" is FPA-specific. Use the generic version if we |
6488 | do not have FPA. */ | |
6489 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
6490 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
6491 | ||
26216b98 | 6492 | /* Internal <-> external register number maps. */ |
ff6f572f | 6493 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
6494 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
6495 | ||
34e8f22d RE |
6496 | set_gdbarch_register_name (gdbarch, arm_register_name); |
6497 | ||
6498 | /* Returning results. */ | |
2af48f68 | 6499 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 6500 | |
03d48a7d RE |
6501 | /* Disassembly. */ |
6502 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
6503 | ||
34e8f22d RE |
6504 | /* Minsymbol frobbing. */ |
6505 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
6506 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
6507 | arm_coff_make_msymbol_special); | |
60c5725c | 6508 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 6509 | |
f9d67f43 DJ |
6510 | /* Thumb-2 IT block support. */ |
6511 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
6512 | arm_adjust_breakpoint_address); | |
6513 | ||
0d5de010 DJ |
6514 | /* Virtual tables. */ |
6515 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6516 | ||
97e03143 | 6517 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 6518 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 6519 | |
b39cc962 DJ |
6520 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
6521 | ||
eb5492fa | 6522 | /* Add some default predicates. */ |
a262aec2 DJ |
6523 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
6524 | dwarf2_append_unwinders (gdbarch); | |
6525 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); | |
eb5492fa | 6526 | |
97e03143 RE |
6527 | /* Now we have tuned the configuration, set a few final things, |
6528 | based on what the OS ABI has told us. */ | |
6529 | ||
b8926edc DJ |
6530 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
6531 | binaries are always marked. */ | |
6532 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
6533 | tdep->arm_abi = ARM_ABI_APCS; | |
6534 | ||
6535 | /* We used to default to FPA for generic ARM, but almost nobody | |
6536 | uses that now, and we now provide a way for the user to force | |
6537 | the model. So default to the most useful variant. */ | |
6538 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
6539 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
6540 | ||
9df628e0 RE |
6541 | if (tdep->jb_pc >= 0) |
6542 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
6543 | ||
08216dd7 | 6544 | /* Floating point sizes and format. */ |
8da61cc4 | 6545 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 6546 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 6547 | { |
8da61cc4 DJ |
6548 | set_gdbarch_double_format |
6549 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
6550 | set_gdbarch_long_double_format | |
6551 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
6552 | } | |
6553 | else | |
6554 | { | |
6555 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
6556 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
6557 | } |
6558 | ||
58d6951d DJ |
6559 | if (have_vfp_pseudos) |
6560 | { | |
6561 | /* NOTE: These are the only pseudo registers used by | |
6562 | the ARM target at the moment. If more are added, a | |
6563 | little more care in numbering will be needed. */ | |
6564 | ||
6565 | int num_pseudos = 32; | |
6566 | if (have_neon_pseudos) | |
6567 | num_pseudos += 16; | |
6568 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); | |
6569 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
6570 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
6571 | } | |
6572 | ||
123dc839 | 6573 | if (tdesc_data) |
58d6951d DJ |
6574 | { |
6575 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
6576 | ||
6577 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); | |
6578 | ||
6579 | /* Override tdesc_register_type to adjust the types of VFP | |
6580 | registers for NEON. */ | |
6581 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
6582 | } | |
123dc839 DJ |
6583 | |
6584 | /* Add standard register aliases. We add aliases even for those | |
6585 | nanes which are used by the current architecture - it's simpler, | |
6586 | and does no harm, since nothing ever lists user registers. */ | |
6587 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
6588 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
6589 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
6590 | ||
39bbf761 RE |
6591 | return gdbarch; |
6592 | } | |
6593 | ||
97e03143 | 6594 | static void |
2af46ca0 | 6595 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 6596 | { |
2af46ca0 | 6597 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
6598 | |
6599 | if (tdep == NULL) | |
6600 | return; | |
6601 | ||
edefbb7c | 6602 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
6603 | (unsigned long) tdep->lowest_pc); |
6604 | } | |
6605 | ||
a78f21af AC |
6606 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
6607 | ||
c906108c | 6608 | void |
ed9a39eb | 6609 | _initialize_arm_tdep (void) |
c906108c | 6610 | { |
bc90b915 FN |
6611 | struct ui_file *stb; |
6612 | long length; | |
26304000 | 6613 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
6614 | const char *setname; |
6615 | const char *setdesc; | |
4bd7b427 | 6616 | const char *const *regnames; |
bc90b915 FN |
6617 | int numregs, i, j; |
6618 | static char *helptext; | |
edefbb7c AC |
6619 | char regdesc[1024], *rdptr = regdesc; |
6620 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 6621 | |
42cf1509 | 6622 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 6623 | |
60c5725c | 6624 | arm_objfile_data_key |
c1bd65d0 | 6625 | = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free); |
60c5725c | 6626 | |
70f80edf JT |
6627 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
6628 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
6629 | bfd_target_elf_flavour, | |
6630 | arm_elf_osabi_sniffer); | |
6631 | ||
94c30b78 | 6632 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
6633 | num_disassembly_options = get_arm_regname_num_options (); |
6634 | ||
6635 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
6636 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 6637 | _("Various ARM-specific commands."), |
afd7eef0 RE |
6638 | &setarmcmdlist, "set arm ", 0, &setlist); |
6639 | ||
6640 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 6641 | _("Various ARM-specific commands."), |
afd7eef0 | 6642 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 6643 | |
94c30b78 | 6644 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 6645 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 6646 | |
eefe576e AC |
6647 | /* Initialize the array that will be passed to |
6648 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
6649 | valid_disassembly_styles |
6650 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
6651 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
6652 | { |
6653 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 6654 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
6655 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
6656 | rdptr += length; | |
6657 | rest -= length; | |
123dc839 DJ |
6658 | /* When we find the default names, tell the disassembler to use |
6659 | them. */ | |
bc90b915 FN |
6660 | if (!strcmp (setname, "std")) |
6661 | { | |
afd7eef0 | 6662 | disassembly_style = setname; |
bc90b915 FN |
6663 | set_arm_regname_option (i); |
6664 | } | |
6665 | } | |
94c30b78 | 6666 | /* Mark the end of valid options. */ |
afd7eef0 | 6667 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 6668 | |
edefbb7c AC |
6669 | /* Create the help text. */ |
6670 | stb = mem_fileopen (); | |
6671 | fprintf_unfiltered (stb, "%s%s%s", | |
6672 | _("The valid values are:\n"), | |
6673 | regdesc, | |
6674 | _("The default is \"std\".")); | |
759ef836 | 6675 | helptext = ui_file_xstrdup (stb, NULL); |
bc90b915 | 6676 | ui_file_delete (stb); |
ed9a39eb | 6677 | |
edefbb7c AC |
6678 | add_setshow_enum_cmd("disassembler", no_class, |
6679 | valid_disassembly_styles, &disassembly_style, | |
6680 | _("Set the disassembly style."), | |
6681 | _("Show the disassembly style."), | |
6682 | helptext, | |
2c5b56ce | 6683 | set_disassembly_style_sfunc, |
7915a72c | 6684 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 6685 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
6686 | |
6687 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
6688 | _("Set usage of ARM 32-bit mode."), | |
6689 | _("Show usage of ARM 32-bit mode."), | |
6690 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 6691 | NULL, |
7915a72c | 6692 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 6693 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 6694 | |
fd50bc42 | 6695 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
6696 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
6697 | _("Set the floating point type."), | |
6698 | _("Show the floating point type."), | |
6699 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
6700 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
6701 | fpa - FPA co-processor (GCC compiled).\n\ | |
6702 | softvfp - Software FP with pure-endian doubles.\n\ | |
6703 | vfp - VFP co-processor."), | |
edefbb7c | 6704 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 6705 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 6706 | |
28e97307 DJ |
6707 | /* Add a command to allow the user to force the ABI. */ |
6708 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
6709 | _("Set the ABI."), | |
6710 | _("Show the ABI."), | |
6711 | NULL, arm_set_abi, arm_show_abi, | |
6712 | &setarmcmdlist, &showarmcmdlist); | |
6713 | ||
0428b8f5 DJ |
6714 | /* Add two commands to allow the user to force the assumed |
6715 | execution mode. */ | |
6716 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
6717 | arm_mode_strings, &arm_fallback_mode_string, | |
6718 | _("Set the mode assumed when symbols are unavailable."), | |
6719 | _("Show the mode assumed when symbols are unavailable."), | |
6720 | NULL, NULL, arm_show_fallback_mode, | |
6721 | &setarmcmdlist, &showarmcmdlist); | |
6722 | add_setshow_enum_cmd ("force-mode", class_support, | |
6723 | arm_mode_strings, &arm_force_mode_string, | |
6724 | _("Set the mode assumed even when symbols are available."), | |
6725 | _("Show the mode assumed even when symbols are available."), | |
6726 | NULL, NULL, arm_show_force_mode, | |
6727 | &setarmcmdlist, &showarmcmdlist); | |
6728 | ||
6529d2dd | 6729 | /* Debugging flag. */ |
edefbb7c AC |
6730 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
6731 | _("Set ARM debugging."), | |
6732 | _("Show ARM debugging."), | |
6733 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 6734 | NULL, |
7915a72c | 6735 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 6736 | &setdebuglist, &showdebuglist); |
c906108c | 6737 | } |