Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
0fb0cc75 | 4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
9b254dd1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
123dc839 DJ |
43 | #include "target-descriptions.h" |
44 | #include "user-regs.h" | |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 | 53 | #include "gdb_assert.h" |
60c5725c | 54 | #include "vec.h" |
26216b98 | 55 | |
6529d2dd AC |
56 | static int arm_debug; |
57 | ||
082fc60d RE |
58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
59 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 60 | is used for this purpose. |
082fc60d RE |
61 | |
62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
64 | |
65 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
b887350f | 66 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
082fc60d RE |
67 | |
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 69 | MSYMBOL_TARGET_FLAG_1 (msym) |
082fc60d | 70 | |
60c5725c DJ |
71 | /* Per-objfile data used for mapping symbols. */ |
72 | static const struct objfile_data *arm_objfile_data_key; | |
73 | ||
74 | struct arm_mapping_symbol | |
75 | { | |
76 | bfd_vma value; | |
77 | char type; | |
78 | }; | |
79 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; | |
80 | DEF_VEC_O(arm_mapping_symbol_s); | |
81 | ||
82 | struct arm_per_objfile | |
83 | { | |
84 | VEC(arm_mapping_symbol_s) **section_maps; | |
85 | }; | |
86 | ||
afd7eef0 RE |
87 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
88 | static struct cmd_list_element *setarmcmdlist = NULL; | |
89 | static struct cmd_list_element *showarmcmdlist = NULL; | |
90 | ||
fd50bc42 RE |
91 | /* The type of floating-point to use. Keep this in sync with enum |
92 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
93 | static const char *fp_model_strings[] = | |
94 | { | |
95 | "auto", | |
96 | "softfpa", | |
97 | "fpa", | |
98 | "softvfp", | |
28e97307 DJ |
99 | "vfp", |
100 | NULL | |
fd50bc42 RE |
101 | }; |
102 | ||
103 | /* A variable that can be configured by the user. */ | |
104 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
105 | static const char *current_fp_model = "auto"; | |
106 | ||
28e97307 DJ |
107 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
108 | static const char *arm_abi_strings[] = | |
109 | { | |
110 | "auto", | |
111 | "APCS", | |
112 | "AAPCS", | |
113 | NULL | |
114 | }; | |
115 | ||
116 | /* A variable that can be configured by the user. */ | |
117 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
118 | static const char *arm_abi_string = "auto"; | |
119 | ||
0428b8f5 DJ |
120 | /* The execution mode to assume. */ |
121 | static const char *arm_mode_strings[] = | |
122 | { | |
123 | "auto", | |
124 | "arm", | |
125 | "thumb" | |
126 | }; | |
127 | ||
128 | static const char *arm_fallback_mode_string = "auto"; | |
129 | static const char *arm_force_mode_string = "auto"; | |
130 | ||
94c30b78 | 131 | /* Number of different reg name sets (options). */ |
afd7eef0 | 132 | static int num_disassembly_options; |
bc90b915 | 133 | |
123dc839 DJ |
134 | /* The standard register names, and all the valid aliases for them. */ |
135 | static const struct | |
136 | { | |
137 | const char *name; | |
138 | int regnum; | |
139 | } arm_register_aliases[] = { | |
140 | /* Basic register numbers. */ | |
141 | { "r0", 0 }, | |
142 | { "r1", 1 }, | |
143 | { "r2", 2 }, | |
144 | { "r3", 3 }, | |
145 | { "r4", 4 }, | |
146 | { "r5", 5 }, | |
147 | { "r6", 6 }, | |
148 | { "r7", 7 }, | |
149 | { "r8", 8 }, | |
150 | { "r9", 9 }, | |
151 | { "r10", 10 }, | |
152 | { "r11", 11 }, | |
153 | { "r12", 12 }, | |
154 | { "r13", 13 }, | |
155 | { "r14", 14 }, | |
156 | { "r15", 15 }, | |
157 | /* Synonyms (argument and variable registers). */ | |
158 | { "a1", 0 }, | |
159 | { "a2", 1 }, | |
160 | { "a3", 2 }, | |
161 | { "a4", 3 }, | |
162 | { "v1", 4 }, | |
163 | { "v2", 5 }, | |
164 | { "v3", 6 }, | |
165 | { "v4", 7 }, | |
166 | { "v5", 8 }, | |
167 | { "v6", 9 }, | |
168 | { "v7", 10 }, | |
169 | { "v8", 11 }, | |
170 | /* Other platform-specific names for r9. */ | |
171 | { "sb", 9 }, | |
172 | { "tr", 9 }, | |
173 | /* Special names. */ | |
174 | { "ip", 12 }, | |
175 | { "sp", 13 }, | |
176 | { "lr", 14 }, | |
177 | { "pc", 15 }, | |
178 | /* Names used by GCC (not listed in the ARM EABI). */ | |
179 | { "sl", 10 }, | |
180 | { "fp", 11 }, | |
181 | /* A special name from the older ATPCS. */ | |
182 | { "wr", 7 }, | |
183 | }; | |
bc90b915 | 184 | |
123dc839 | 185 | static const char *const arm_register_names[] = |
da59e081 JM |
186 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
187 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
188 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
189 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
190 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
191 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 192 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 193 | |
afd7eef0 RE |
194 | /* Valid register name styles. */ |
195 | static const char **valid_disassembly_styles; | |
ed9a39eb | 196 | |
afd7eef0 RE |
197 | /* Disassembly style to use. Default to "std" register names. */ |
198 | static const char *disassembly_style; | |
96baa820 | 199 | |
ed9a39eb | 200 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
201 | style. */ |
202 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 203 | struct cmd_list_element *); |
afd7eef0 | 204 | static void set_disassembly_style (void); |
ed9a39eb | 205 | |
b508a996 | 206 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 207 | void *, int); |
b508a996 | 208 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 209 | const void *, int); |
ed9a39eb | 210 | |
9b8d791a | 211 | struct arm_prologue_cache |
c3b4394c | 212 | { |
eb5492fa DJ |
213 | /* The stack pointer at the time this frame was created; i.e. the |
214 | caller's stack pointer when this function was called. It is used | |
215 | to identify this frame. */ | |
216 | CORE_ADDR prev_sp; | |
217 | ||
4be43953 DJ |
218 | /* The frame base for this frame is just prev_sp - frame size. |
219 | FRAMESIZE is the distance from the frame pointer to the | |
220 | initial stack pointer. */ | |
eb5492fa | 221 | |
c3b4394c | 222 | int framesize; |
eb5492fa DJ |
223 | |
224 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 225 | int framereg; |
eb5492fa DJ |
226 | |
227 | /* Saved register offsets. */ | |
228 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 229 | }; |
ed9a39eb | 230 | |
bc90b915 FN |
231 | /* Addresses for calling Thumb functions have the bit 0 set. |
232 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
233 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
234 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
235 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
236 | ||
94c30b78 | 237 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
238 | |
239 | int arm_apcs_32 = 1; | |
240 | ||
b39cc962 DJ |
241 | /* Determine if FRAME is executing in Thumb mode. */ |
242 | ||
243 | static int | |
244 | arm_frame_is_thumb (struct frame_info *frame) | |
245 | { | |
246 | CORE_ADDR cpsr; | |
247 | ||
248 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
249 | directly (from a signal frame or dummy frame) or by interpreting | |
250 | the saved LR (from a prologue or DWARF frame). So consult it and | |
251 | trust the unwinders. */ | |
252 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
253 | ||
254 | return (cpsr & CPSR_T) != 0; | |
255 | } | |
256 | ||
60c5725c DJ |
257 | /* Callback for VEC_lower_bound. */ |
258 | ||
259 | static inline int | |
260 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, | |
261 | const struct arm_mapping_symbol *rhs) | |
262 | { | |
263 | return lhs->value < rhs->value; | |
264 | } | |
265 | ||
ed9a39eb | 266 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
b39cc962 DJ |
267 | function. This function should be called for addresses unrelated to |
268 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
c906108c | 269 | |
ad527d2e | 270 | static int |
2a451106 | 271 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 272 | { |
60c5725c | 273 | struct obj_section *sec; |
c5aa993b | 274 | struct minimal_symbol *sym; |
c906108c | 275 | |
ed9a39eb | 276 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
277 | if (IS_THUMB_ADDR (memaddr)) |
278 | return 1; | |
279 | ||
0428b8f5 DJ |
280 | /* If the user wants to override the symbol table, let him. */ |
281 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
282 | return 0; | |
283 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
284 | return 1; | |
285 | ||
60c5725c DJ |
286 | /* If there are mapping symbols, consult them. */ |
287 | sec = find_pc_section (memaddr); | |
288 | if (sec != NULL) | |
289 | { | |
290 | struct arm_per_objfile *data; | |
291 | VEC(arm_mapping_symbol_s) *map; | |
aded6f54 PA |
292 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
293 | 0 }; | |
60c5725c DJ |
294 | unsigned int idx; |
295 | ||
296 | data = objfile_data (sec->objfile, arm_objfile_data_key); | |
297 | if (data != NULL) | |
298 | { | |
299 | map = data->section_maps[sec->the_bfd_section->index]; | |
300 | if (!VEC_empty (arm_mapping_symbol_s, map)) | |
301 | { | |
302 | struct arm_mapping_symbol *map_sym; | |
303 | ||
304 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, | |
305 | arm_compare_mapping_symbols); | |
306 | ||
307 | /* VEC_lower_bound finds the earliest ordered insertion | |
308 | point. If the following symbol starts at this exact | |
309 | address, we use that; otherwise, the preceding | |
310 | mapping symbol covers this address. */ | |
311 | if (idx < VEC_length (arm_mapping_symbol_s, map)) | |
312 | { | |
313 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); | |
314 | if (map_sym->value == map_key.value) | |
315 | return map_sym->type == 't'; | |
316 | } | |
317 | ||
318 | if (idx > 0) | |
319 | { | |
320 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); | |
321 | return map_sym->type == 't'; | |
322 | } | |
323 | } | |
324 | } | |
325 | } | |
326 | ||
ed9a39eb | 327 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
328 | sym = lookup_minimal_symbol_by_pc (memaddr); |
329 | if (sym) | |
0428b8f5 DJ |
330 | return (MSYMBOL_IS_SPECIAL (sym)); |
331 | ||
332 | /* If the user wants to override the fallback mode, let them. */ | |
333 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
334 | return 0; | |
335 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
336 | return 1; | |
337 | ||
338 | /* If we couldn't find any symbol, but we're talking to a running | |
339 | target, then trust the current value of $cpsr. This lets | |
340 | "display/i $pc" always show the correct mode (though if there is | |
341 | a symbol table we will not reach here, so it still may not be | |
342 | displayed in the mode it will be executed). */ | |
343 | if (target_has_registers) | |
344 | return arm_frame_is_thumb (get_current_frame ()); | |
345 | ||
346 | /* Otherwise we're out of luck; we assume ARM. */ | |
347 | return 0; | |
c906108c SS |
348 | } |
349 | ||
181c1381 | 350 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 351 | static CORE_ADDR |
24568a2c | 352 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 353 | { |
a3a2ee65 | 354 | if (arm_apcs_32) |
dd6be234 | 355 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 356 | else |
a3a2ee65 | 357 | return (val & 0x03fffffc); |
c906108c SS |
358 | } |
359 | ||
181c1381 RE |
360 | /* When reading symbols, we need to zap the low bit of the address, |
361 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 362 | static CORE_ADDR |
24568a2c | 363 | arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) |
181c1381 RE |
364 | { |
365 | return val & ~1; | |
366 | } | |
367 | ||
29d73ae4 DJ |
368 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
369 | and frame pointer. Scan until we encounter a store that could | |
370 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
371 | |
372 | static CORE_ADDR | |
29d73ae4 DJ |
373 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
374 | CORE_ADDR start, CORE_ADDR limit, | |
375 | struct arm_prologue_cache *cache) | |
c906108c | 376 | { |
e17a4113 | 377 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
378 | int i; |
379 | pv_t regs[16]; | |
380 | struct pv_area *stack; | |
381 | struct cleanup *back_to; | |
382 | CORE_ADDR offset; | |
da3c6d4a | 383 | |
29d73ae4 DJ |
384 | for (i = 0; i < 16; i++) |
385 | regs[i] = pv_register (i, 0); | |
55f960e1 | 386 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 DJ |
387 | back_to = make_cleanup_free_pv_area (stack); |
388 | ||
29d73ae4 | 389 | while (start < limit) |
c906108c | 390 | { |
29d73ae4 DJ |
391 | unsigned short insn; |
392 | ||
e17a4113 | 393 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 394 | |
94c30b78 | 395 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 396 | { |
29d73ae4 DJ |
397 | int regno; |
398 | int mask; | |
4be43953 DJ |
399 | |
400 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
401 | break; | |
29d73ae4 DJ |
402 | |
403 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
404 | whether to save LR (R14). */ | |
405 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
406 | ||
407 | /* Calculate offsets of saved R0-R7 and LR. */ | |
408 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
409 | if (mask & (1 << regno)) | |
410 | { | |
29d73ae4 DJ |
411 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
412 | -4); | |
413 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
414 | } | |
da59e081 | 415 | } |
da3c6d4a MS |
416 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
417 | sub sp, #simm */ | |
da59e081 | 418 | { |
29d73ae4 DJ |
419 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
420 | if (insn & 0x80) /* Check for SUB. */ | |
421 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
422 | -offset); | |
da59e081 | 423 | else |
29d73ae4 DJ |
424 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
425 | offset); | |
da59e081 JM |
426 | } |
427 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
428 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
429 | (insn & 0xff) << 2); | |
430 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 431 | { |
29d73ae4 DJ |
432 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
433 | int src_reg = (insn & 0x78) >> 3; | |
434 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 435 | } |
29d73ae4 | 436 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 437 | { |
29d73ae4 DJ |
438 | /* Handle stores to the stack. Normally pushes are used, |
439 | but with GCC -mtpcs-frame, there may be other stores | |
440 | in the prologue to create the frame. */ | |
441 | int regno = (insn >> 8) & 0x7; | |
442 | pv_t addr; | |
443 | ||
444 | offset = (insn & 0xff) << 2; | |
445 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
446 | ||
447 | if (pv_area_store_would_trash (stack, addr)) | |
448 | break; | |
449 | ||
450 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 451 | } |
29d73ae4 | 452 | else |
3d74b771 | 453 | { |
29d73ae4 DJ |
454 | /* We don't know what this instruction is. We're finished |
455 | scanning. NOTE: Recognizing more safe-to-ignore | |
456 | instructions here will improve support for optimized | |
457 | code. */ | |
da3c6d4a | 458 | break; |
3d74b771 | 459 | } |
29d73ae4 DJ |
460 | |
461 | start += 2; | |
c906108c SS |
462 | } |
463 | ||
29d73ae4 DJ |
464 | if (cache == NULL) |
465 | { | |
466 | do_cleanups (back_to); | |
467 | return start; | |
468 | } | |
469 | ||
29d73ae4 DJ |
470 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
471 | { | |
472 | /* Frame pointer is fp. Frame size is constant. */ | |
473 | cache->framereg = ARM_FP_REGNUM; | |
474 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
475 | } | |
476 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
477 | { | |
478 | /* Frame pointer is r7. Frame size is constant. */ | |
479 | cache->framereg = THUMB_FP_REGNUM; | |
480 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
481 | } | |
482 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
483 | { | |
484 | /* Try the stack pointer... this is a bit desperate. */ | |
485 | cache->framereg = ARM_SP_REGNUM; | |
486 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
487 | } | |
488 | else | |
489 | { | |
490 | /* We're just out of luck. We don't know where the frame is. */ | |
491 | cache->framereg = -1; | |
492 | cache->framesize = 0; | |
493 | } | |
494 | ||
495 | for (i = 0; i < 16; i++) | |
496 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
497 | cache->saved_regs[i].addr = offset; | |
498 | ||
499 | do_cleanups (back_to); | |
500 | return start; | |
c906108c SS |
501 | } |
502 | ||
da3c6d4a MS |
503 | /* Advance the PC across any function entry prologue instructions to |
504 | reach some "real" code. | |
34e8f22d RE |
505 | |
506 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 507 | prologue: |
c906108c | 508 | |
c5aa993b JM |
509 | mov ip, sp |
510 | [stmfd sp!, {a1,a2,a3,a4}] | |
511 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
512 | [stfe f7, [sp, #-12]!] |
513 | [stfe f6, [sp, #-12]!] | |
514 | [stfe f5, [sp, #-12]!] | |
515 | [stfe f4, [sp, #-12]!] | |
516 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 517 | |
34e8f22d | 518 | static CORE_ADDR |
6093d2eb | 519 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 520 | { |
e17a4113 | 521 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
c906108c SS |
522 | unsigned long inst; |
523 | CORE_ADDR skip_pc; | |
a89fea3c | 524 | CORE_ADDR func_addr, limit_pc; |
c906108c SS |
525 | struct symtab_and_line sal; |
526 | ||
848cfffb | 527 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
d80b854b | 528 | if (deprecated_pc_in_call_dummy (gdbarch, pc)) |
848cfffb AC |
529 | return pc; |
530 | ||
a89fea3c JL |
531 | /* See if we can determine the end of the prologue via the symbol table. |
532 | If so, then return either PC, or the PC after the prologue, whichever | |
533 | is greater. */ | |
534 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 535 | { |
d80b854b UW |
536 | CORE_ADDR post_prologue_pc |
537 | = skip_prologue_using_sal (gdbarch, func_addr); | |
a89fea3c JL |
538 | if (post_prologue_pc != 0) |
539 | return max (pc, post_prologue_pc); | |
c906108c SS |
540 | } |
541 | ||
a89fea3c JL |
542 | /* Can't determine prologue from the symbol table, need to examine |
543 | instructions. */ | |
c906108c | 544 | |
a89fea3c JL |
545 | /* Find an upper limit on the function prologue using the debug |
546 | information. If the debug information could not be used to provide | |
547 | that bound, then use an arbitrary large number as the upper bound. */ | |
b8d5e71d | 548 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 549 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
550 | if (limit_pc == 0) |
551 | limit_pc = pc + 64; /* Magic. */ | |
552 | ||
c906108c | 553 | |
29d73ae4 DJ |
554 | /* Check if this is Thumb code. */ |
555 | if (arm_pc_is_thumb (pc)) | |
a89fea3c | 556 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
29d73ae4 | 557 | |
a89fea3c | 558 | for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) |
f43845b3 | 559 | { |
e17a4113 | 560 | inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); |
9d4fde75 | 561 | |
b8d5e71d MS |
562 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
563 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
564 | continue; | |
c906108c | 565 | |
28cd8767 JG |
566 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
567 | continue; | |
568 | ||
569 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
570 | continue; | |
571 | ||
b8d5e71d MS |
572 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
573 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
574 | continue; | |
c906108c | 575 | |
b8d5e71d MS |
576 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
577 | continue; | |
c906108c | 578 | |
b8d5e71d MS |
579 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
580 | continue; | |
11d3b27d | 581 | |
b8d5e71d MS |
582 | /* Any insns after this point may float into the code, if it makes |
583 | for better instruction scheduling, so we skip them only if we | |
584 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 585 | |
b8d5e71d MS |
586 | /* We may have either one sfmfd instruction here, or several stfe |
587 | insns, depending on the version of floating point code we | |
588 | support. */ | |
589 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
590 | continue; | |
591 | ||
592 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
593 | continue; | |
594 | ||
595 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
596 | continue; | |
597 | ||
598 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
599 | continue; | |
600 | ||
601 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
602 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
603 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
604 | continue; | |
605 | ||
606 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
607 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
608 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
609 | continue; | |
610 | ||
611 | /* Un-recognized instruction; stop scanning. */ | |
612 | break; | |
f43845b3 | 613 | } |
c906108c | 614 | |
b8d5e71d | 615 | return skip_pc; /* End of prologue */ |
c906108c | 616 | } |
94c30b78 | 617 | |
c5aa993b | 618 | /* *INDENT-OFF* */ |
c906108c SS |
619 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
620 | This function decodes a Thumb function prologue to determine: | |
621 | 1) the size of the stack frame | |
622 | 2) which registers are saved on it | |
623 | 3) the offsets of saved regs | |
624 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 625 | |
da59e081 JM |
626 | A typical Thumb function prologue would create this stack frame |
627 | (offsets relative to FP) | |
c906108c SS |
628 | old SP -> 24 stack parameters |
629 | 20 LR | |
630 | 16 R7 | |
631 | R7 -> 0 local variables (16 bytes) | |
632 | SP -> -12 additional stack space (12 bytes) | |
633 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
634 | 12 bytes. The frame register is R7. |
635 | ||
da3c6d4a MS |
636 | The comments for thumb_skip_prolog() describe the algorithm we use |
637 | to detect the end of the prolog. */ | |
c5aa993b JM |
638 | /* *INDENT-ON* */ |
639 | ||
c906108c | 640 | static void |
be8626e0 | 641 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 642 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
643 | { |
644 | CORE_ADDR prologue_start; | |
645 | CORE_ADDR prologue_end; | |
646 | CORE_ADDR current_pc; | |
c906108c | 647 | |
b39cc962 DJ |
648 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
649 | &prologue_end)) | |
c906108c SS |
650 | { |
651 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
652 | ||
94c30b78 | 653 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 654 | prologue_end = prev_pc; |
c906108c | 655 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 656 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
657 | } |
658 | else | |
f7060f85 DJ |
659 | /* We're in the boondocks: we have no idea where the start of the |
660 | function is. */ | |
661 | return; | |
c906108c | 662 | |
eb5492fa | 663 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 664 | |
be8626e0 | 665 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
666 | } |
667 | ||
ed9a39eb | 668 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
669 | 1) the size of the stack frame |
670 | 2) which registers are saved on it | |
671 | 3) the offsets of saved regs | |
672 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
673 | This information is stored in the "extra" fields of the frame_info. |
674 | ||
96baa820 JM |
675 | There are two basic forms for the ARM prologue. The fixed argument |
676 | function call will look like: | |
ed9a39eb JM |
677 | |
678 | mov ip, sp | |
679 | stmfd sp!, {fp, ip, lr, pc} | |
680 | sub fp, ip, #4 | |
681 | [sub sp, sp, #4] | |
96baa820 | 682 | |
c906108c | 683 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
684 | IP -> 4 (caller's stack) |
685 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
686 | -4 LR (return address in caller) | |
687 | -8 IP (copy of caller's SP) | |
688 | -12 FP (caller's FP) | |
689 | SP -> -28 Local variables | |
690 | ||
c906108c | 691 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
692 | 28 bytes. The stmfd call can also save any of the vN registers it |
693 | plans to use, which increases the frame size accordingly. | |
694 | ||
695 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
696 | because the ARM Store instructions always store PC + 8 when you read | |
697 | the PC register. | |
ed9a39eb | 698 | |
96baa820 JM |
699 | A variable argument function call will look like: |
700 | ||
ed9a39eb JM |
701 | mov ip, sp |
702 | stmfd sp!, {a1, a2, a3, a4} | |
703 | stmfd sp!, {fp, ip, lr, pc} | |
704 | sub fp, ip, #20 | |
705 | ||
96baa820 | 706 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
707 | IP -> 20 (caller's stack) |
708 | 16 A4 | |
709 | 12 A3 | |
710 | 8 A2 | |
711 | 4 A1 | |
712 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
713 | -4 LR (return address in caller) | |
714 | -8 IP (copy of caller's SP) | |
715 | -12 FP (caller's FP) | |
716 | SP -> -28 Local variables | |
96baa820 JM |
717 | |
718 | The frame size would thus be 48 bytes, and the frame offset would be | |
719 | 28 bytes. | |
720 | ||
721 | There is another potential complication, which is that the optimizer | |
722 | will try to separate the store of fp in the "stmfd" instruction from | |
723 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
724 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
725 | ||
726 | Also, note, the original version of the ARM toolchain claimed that there | |
727 | should be an | |
728 | ||
729 | instruction at the end of the prologue. I have never seen GCC produce | |
730 | this, and the ARM docs don't mention it. We still test for it below in | |
731 | case it happens... | |
ed9a39eb JM |
732 | |
733 | */ | |
c906108c SS |
734 | |
735 | static void | |
a262aec2 | 736 | arm_scan_prologue (struct frame_info *this_frame, |
2af46ca0 | 737 | struct arm_prologue_cache *cache) |
c906108c | 738 | { |
a262aec2 | 739 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
740 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
741 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4be43953 | 742 | int regno; |
c906108c | 743 | CORE_ADDR prologue_start, prologue_end, current_pc; |
a262aec2 | 744 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
b39cc962 | 745 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
4be43953 DJ |
746 | pv_t regs[ARM_FPS_REGNUM]; |
747 | struct pv_area *stack; | |
748 | struct cleanup *back_to; | |
749 | CORE_ADDR offset; | |
c906108c | 750 | |
c906108c | 751 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
752 | cache->framereg = ARM_SP_REGNUM; |
753 | cache->framesize = 0; | |
c906108c SS |
754 | |
755 | /* Check for Thumb prologue. */ | |
b39cc962 | 756 | if (arm_frame_is_thumb (this_frame)) |
c906108c | 757 | { |
b39cc962 | 758 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
c906108c SS |
759 | return; |
760 | } | |
761 | ||
762 | /* Find the function prologue. If we can't find the function in | |
763 | the symbol table, peek in the stack frame to find the PC. */ | |
b39cc962 DJ |
764 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
765 | &prologue_end)) | |
c906108c | 766 | { |
2a451106 KB |
767 | /* One way to find the end of the prologue (which works well |
768 | for unoptimized code) is to do the following: | |
769 | ||
770 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
771 | ||
772 | if (sal.line == 0) | |
eb5492fa | 773 | prologue_end = prev_pc; |
2a451106 KB |
774 | else if (sal.end < prologue_end) |
775 | prologue_end = sal.end; | |
776 | ||
777 | This mechanism is very accurate so long as the optimizer | |
778 | doesn't move any instructions from the function body into the | |
779 | prologue. If this happens, sal.end will be the last | |
780 | instruction in the first hunk of prologue code just before | |
781 | the first instruction that the scheduler has moved from | |
782 | the body to the prologue. | |
783 | ||
784 | In order to make sure that we scan all of the prologue | |
785 | instructions, we use a slightly less accurate mechanism which | |
786 | may scan more than necessary. To help compensate for this | |
787 | lack of accuracy, the prologue scanning loop below contains | |
788 | several clauses which'll cause the loop to terminate early if | |
789 | an implausible prologue instruction is encountered. | |
790 | ||
791 | The expression | |
792 | ||
793 | prologue_start + 64 | |
794 | ||
795 | is a suitable endpoint since it accounts for the largest | |
796 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 797 | the scheduler. */ |
2a451106 KB |
798 | |
799 | if (prologue_end > prologue_start + 64) | |
800 | { | |
94c30b78 | 801 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 802 | } |
c906108c SS |
803 | } |
804 | else | |
805 | { | |
eb5492fa DJ |
806 | /* We have no symbol information. Our only option is to assume this |
807 | function has a standard stack frame and the normal frame register. | |
808 | Then, we can find the value of our frame pointer on entrance to | |
809 | the callee (or at the present moment if this is the innermost frame). | |
810 | The value stored there should be the address of the stmfd + 8. */ | |
811 | CORE_ADDR frame_loc; | |
812 | LONGEST return_value; | |
813 | ||
a262aec2 | 814 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
e17a4113 | 815 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) |
16a0f3e7 EZ |
816 | return; |
817 | else | |
818 | { | |
bf6ae464 | 819 | prologue_start = gdbarch_addr_bits_remove |
2af46ca0 | 820 | (gdbarch, return_value) - 8; |
94c30b78 | 821 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 822 | } |
c906108c SS |
823 | } |
824 | ||
eb5492fa DJ |
825 | if (prev_pc < prologue_end) |
826 | prologue_end = prev_pc; | |
827 | ||
c906108c | 828 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 829 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 830 | |
96baa820 JM |
831 | Be careful, however, and if it doesn't look like a prologue, |
832 | don't try to scan it. If, for instance, a frameless function | |
833 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 834 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
835 | and other operations that rely on a knowledge of the stack |
836 | traceback. | |
837 | ||
838 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 839 | if we don't see this as the first insn, we will stop. |
c906108c | 840 | |
f43845b3 MS |
841 | [Note: This doesn't seem to be true any longer, so it's now an |
842 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 843 | |
f43845b3 MS |
844 | [Note further: The "mov ip,sp" only seems to be missing in |
845 | frameless functions at optimization level "-O2" or above, | |
846 | in which case it is often (but not always) replaced by | |
b8d5e71d | 847 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 848 | |
4be43953 DJ |
849 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
850 | regs[regno] = pv_register (regno, 0); | |
55f960e1 | 851 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 DJ |
852 | back_to = make_cleanup_free_pv_area (stack); |
853 | ||
94c30b78 MS |
854 | for (current_pc = prologue_start; |
855 | current_pc < prologue_end; | |
f43845b3 | 856 | current_pc += 4) |
96baa820 | 857 | { |
e17a4113 UW |
858 | unsigned int insn |
859 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); | |
9d4fde75 | 860 | |
94c30b78 | 861 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 862 | { |
4be43953 | 863 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
864 | continue; |
865 | } | |
866 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
867 | { | |
868 | unsigned imm = insn & 0xff; /* immediate value */ | |
869 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
870 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 871 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
28cd8767 JG |
872 | continue; |
873 | } | |
874 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
875 | { | |
876 | unsigned imm = insn & 0xff; /* immediate value */ | |
877 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
878 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 879 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
f43845b3 MS |
880 | continue; |
881 | } | |
94c30b78 | 882 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 883 | { |
4be43953 DJ |
884 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
885 | break; | |
886 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
887 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); | |
f43845b3 MS |
888 | continue; |
889 | } | |
890 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
891 | /* stmfd sp!, {..., fp, ip, lr, pc} |
892 | or | |
893 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 894 | { |
d4473757 | 895 | int mask = insn & 0xffff; |
ed9a39eb | 896 | |
4be43953 DJ |
897 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
898 | break; | |
899 | ||
94c30b78 | 900 | /* Calculate offsets of saved registers. */ |
34e8f22d | 901 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
902 | if (mask & (1 << regno)) |
903 | { | |
4be43953 DJ |
904 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
905 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
d4473757 KB |
906 | } |
907 | } | |
b8d5e71d MS |
908 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
909 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
910 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
911 | { | |
912 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
913 | continue; | |
914 | } | |
915 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
916 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
917 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
918 | { |
919 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
920 | continue; | |
921 | } | |
d4473757 KB |
922 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
923 | { | |
94c30b78 MS |
924 | unsigned imm = insn & 0xff; /* immediate value */ |
925 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 926 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 927 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
928 | } |
929 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
930 | { | |
94c30b78 MS |
931 | unsigned imm = insn & 0xff; /* immediate value */ |
932 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 933 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 934 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 935 | } |
ff6f572f | 936 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
2af46ca0 | 937 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 938 | { |
4be43953 DJ |
939 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
940 | break; | |
941 | ||
942 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 943 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 944 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 945 | } |
ff6f572f | 946 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
2af46ca0 | 947 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
948 | { |
949 | int n_saved_fp_regs; | |
950 | unsigned int fp_start_reg, fp_bound_reg; | |
951 | ||
4be43953 DJ |
952 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
953 | break; | |
954 | ||
94c30b78 | 955 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 956 | { |
d4473757 KB |
957 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
958 | n_saved_fp_regs = 3; | |
959 | else | |
960 | n_saved_fp_regs = 1; | |
96baa820 | 961 | } |
d4473757 | 962 | else |
96baa820 | 963 | { |
d4473757 KB |
964 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
965 | n_saved_fp_regs = 2; | |
966 | else | |
967 | n_saved_fp_regs = 4; | |
96baa820 | 968 | } |
d4473757 | 969 | |
34e8f22d | 970 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
971 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
972 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 973 | { |
4be43953 DJ |
974 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
975 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
976 | regs[fp_start_reg++]); | |
96baa820 | 977 | } |
c906108c | 978 | } |
d4473757 | 979 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 980 | break; /* Condition not true, exit early */ |
b8d5e71d | 981 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 982 | break; /* Don't scan past a block load */ |
d4473757 KB |
983 | else |
984 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 985 | so we just skip what we don't recognize. */ |
d4473757 | 986 | continue; |
c906108c SS |
987 | } |
988 | ||
4be43953 DJ |
989 | /* The frame size is just the distance from the frame register |
990 | to the original stack pointer. */ | |
991 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
992 | { | |
993 | /* Frame pointer is fp. */ | |
994 | cache->framereg = ARM_FP_REGNUM; | |
995 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
996 | } | |
997 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
998 | { | |
999 | /* Try the stack pointer... this is a bit desperate. */ | |
1000 | cache->framereg = ARM_SP_REGNUM; | |
1001 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1002 | } | |
d4473757 | 1003 | else |
4be43953 DJ |
1004 | { |
1005 | /* We're just out of luck. We don't know where the frame is. */ | |
1006 | cache->framereg = -1; | |
1007 | cache->framesize = 0; | |
1008 | } | |
1009 | ||
1010 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
1011 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
1012 | cache->saved_regs[regno].addr = offset; | |
1013 | ||
1014 | do_cleanups (back_to); | |
c906108c SS |
1015 | } |
1016 | ||
eb5492fa | 1017 | static struct arm_prologue_cache * |
a262aec2 | 1018 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1019 | { |
eb5492fa DJ |
1020 | int reg; |
1021 | struct arm_prologue_cache *cache; | |
1022 | CORE_ADDR unwound_fp; | |
c5aa993b | 1023 | |
35d5d4ee | 1024 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1025 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1026 | |
a262aec2 | 1027 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1028 | |
a262aec2 | 1029 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1030 | if (unwound_fp == 0) |
1031 | return cache; | |
c906108c | 1032 | |
4be43953 | 1033 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1034 | |
eb5492fa DJ |
1035 | /* Calculate actual addresses of saved registers using offsets |
1036 | determined by arm_scan_prologue. */ | |
a262aec2 | 1037 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 1038 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
1039 | cache->saved_regs[reg].addr += cache->prev_sp; |
1040 | ||
1041 | return cache; | |
c906108c SS |
1042 | } |
1043 | ||
eb5492fa DJ |
1044 | /* Our frame ID for a normal frame is the current function's starting PC |
1045 | and the caller's SP when we were called. */ | |
c906108c | 1046 | |
148754e5 | 1047 | static void |
a262aec2 | 1048 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
1049 | void **this_cache, |
1050 | struct frame_id *this_id) | |
c906108c | 1051 | { |
eb5492fa DJ |
1052 | struct arm_prologue_cache *cache; |
1053 | struct frame_id id; | |
2c404490 | 1054 | CORE_ADDR pc, func; |
f079148d | 1055 | |
eb5492fa | 1056 | if (*this_cache == NULL) |
a262aec2 | 1057 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1058 | cache = *this_cache; |
2a451106 | 1059 | |
2c404490 DJ |
1060 | /* This is meant to halt the backtrace at "_start". */ |
1061 | pc = get_frame_pc (this_frame); | |
1062 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
eb5492fa | 1063 | return; |
5a203e44 | 1064 | |
eb5492fa DJ |
1065 | /* If we've hit a wall, stop. */ |
1066 | if (cache->prev_sp == 0) | |
1067 | return; | |
24de872b | 1068 | |
2c404490 | 1069 | func = get_frame_func (this_frame); |
eb5492fa | 1070 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1071 | *this_id = id; |
c906108c SS |
1072 | } |
1073 | ||
a262aec2 DJ |
1074 | static struct value * |
1075 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1076 | void **this_cache, |
a262aec2 | 1077 | int prev_regnum) |
24de872b | 1078 | { |
24568a2c | 1079 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
1080 | struct arm_prologue_cache *cache; |
1081 | ||
eb5492fa | 1082 | if (*this_cache == NULL) |
a262aec2 | 1083 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1084 | cache = *this_cache; |
24de872b | 1085 | |
eb5492fa | 1086 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1087 | instead. The prologue may save PC, but it will point into this |
1088 | frame's prologue, not the next frame's resume location. Also | |
1089 | strip the saved T bit. A valid LR may have the low bit set, but | |
1090 | a valid PC never does. */ | |
eb5492fa | 1091 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1092 | { |
1093 | CORE_ADDR lr; | |
1094 | ||
1095 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1096 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 1097 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 1098 | } |
24de872b | 1099 | |
eb5492fa | 1100 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1101 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1102 | The value was already reconstructed into PREV_SP. */ |
1103 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1104 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1105 | |
b39cc962 DJ |
1106 | /* The CPSR may have been changed by the call instruction and by the |
1107 | called function. The only bit we can reconstruct is the T bit, | |
1108 | by checking the low bit of LR as of the call. This is a reliable | |
1109 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
1110 | Thumb code, which could get away with a clear low bit as long as | |
1111 | the called function did not use bx. Guess that all other | |
1112 | bits are unchanged; the condition flags are presumably lost, | |
1113 | but the processor status is likely valid. */ | |
1114 | if (prev_regnum == ARM_PS_REGNUM) | |
1115 | { | |
1116 | CORE_ADDR lr, cpsr; | |
1117 | ||
1118 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
1119 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1120 | if (IS_THUMB_ADDR (lr)) | |
1121 | cpsr |= CPSR_T; | |
1122 | else | |
1123 | cpsr &= ~CPSR_T; | |
1124 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); | |
1125 | } | |
1126 | ||
a262aec2 DJ |
1127 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
1128 | prev_regnum); | |
eb5492fa DJ |
1129 | } |
1130 | ||
1131 | struct frame_unwind arm_prologue_unwind = { | |
1132 | NORMAL_FRAME, | |
1133 | arm_prologue_this_id, | |
a262aec2 DJ |
1134 | arm_prologue_prev_register, |
1135 | NULL, | |
1136 | default_frame_sniffer | |
eb5492fa DJ |
1137 | }; |
1138 | ||
909cf6ea | 1139 | static struct arm_prologue_cache * |
a262aec2 | 1140 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea DJ |
1141 | { |
1142 | int reg; | |
1143 | struct arm_prologue_cache *cache; | |
1144 | CORE_ADDR unwound_fp; | |
1145 | ||
35d5d4ee | 1146 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1147 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 1148 | |
a262aec2 | 1149 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
1150 | |
1151 | return cache; | |
1152 | } | |
1153 | ||
1154 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1155 | ||
1156 | static void | |
a262aec2 | 1157 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
1158 | void **this_cache, |
1159 | struct frame_id *this_id) | |
1160 | { | |
1161 | struct arm_prologue_cache *cache; | |
1162 | ||
1163 | if (*this_cache == NULL) | |
a262aec2 | 1164 | *this_cache = arm_make_stub_cache (this_frame); |
909cf6ea DJ |
1165 | cache = *this_cache; |
1166 | ||
a262aec2 | 1167 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
1168 | } |
1169 | ||
a262aec2 DJ |
1170 | static int |
1171 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
1172 | struct frame_info *this_frame, | |
1173 | void **this_prologue_cache) | |
909cf6ea | 1174 | { |
93d42b30 | 1175 | CORE_ADDR addr_in_block; |
909cf6ea DJ |
1176 | char dummy[4]; |
1177 | ||
a262aec2 | 1178 | addr_in_block = get_frame_address_in_block (this_frame); |
93d42b30 | 1179 | if (in_plt_section (addr_in_block, NULL) |
a262aec2 DJ |
1180 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
1181 | return 1; | |
909cf6ea | 1182 | |
a262aec2 | 1183 | return 0; |
909cf6ea DJ |
1184 | } |
1185 | ||
a262aec2 DJ |
1186 | struct frame_unwind arm_stub_unwind = { |
1187 | NORMAL_FRAME, | |
1188 | arm_stub_this_id, | |
1189 | arm_prologue_prev_register, | |
1190 | NULL, | |
1191 | arm_stub_unwind_sniffer | |
1192 | }; | |
1193 | ||
24de872b | 1194 | static CORE_ADDR |
a262aec2 | 1195 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
1196 | { |
1197 | struct arm_prologue_cache *cache; | |
1198 | ||
eb5492fa | 1199 | if (*this_cache == NULL) |
a262aec2 | 1200 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa DJ |
1201 | cache = *this_cache; |
1202 | ||
4be43953 | 1203 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
1204 | } |
1205 | ||
eb5492fa DJ |
1206 | struct frame_base arm_normal_base = { |
1207 | &arm_prologue_unwind, | |
1208 | arm_normal_frame_base, | |
1209 | arm_normal_frame_base, | |
1210 | arm_normal_frame_base | |
1211 | }; | |
1212 | ||
a262aec2 | 1213 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
1214 | dummy frame. The frame ID's base needs to match the TOS value |
1215 | saved by save_dummy_frame_tos() and returned from | |
1216 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1217 | breakpoint. */ | |
c906108c | 1218 | |
eb5492fa | 1219 | static struct frame_id |
a262aec2 | 1220 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 1221 | { |
a262aec2 DJ |
1222 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
1223 | get_frame_pc (this_frame)); | |
eb5492fa | 1224 | } |
c3b4394c | 1225 | |
eb5492fa DJ |
1226 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1227 | be used to construct the previous frame's ID, after looking up the | |
1228 | containing function). */ | |
c3b4394c | 1229 | |
eb5492fa DJ |
1230 | static CORE_ADDR |
1231 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1232 | { | |
1233 | CORE_ADDR pc; | |
1234 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
24568a2c | 1235 | return arm_addr_bits_remove (gdbarch, pc); |
eb5492fa DJ |
1236 | } |
1237 | ||
1238 | static CORE_ADDR | |
1239 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1240 | { | |
1241 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1242 | } |
1243 | ||
b39cc962 DJ |
1244 | static struct value * |
1245 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
1246 | int regnum) | |
1247 | { | |
24568a2c | 1248 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
b39cc962 DJ |
1249 | CORE_ADDR lr, cpsr; |
1250 | ||
1251 | switch (regnum) | |
1252 | { | |
1253 | case ARM_PC_REGNUM: | |
1254 | /* The PC is normally copied from the return column, which | |
1255 | describes saves of LR. However, that version may have an | |
1256 | extra bit set to indicate Thumb state. The bit is not | |
1257 | part of the PC. */ | |
1258 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1259 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 1260 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
1261 | |
1262 | case ARM_PS_REGNUM: | |
1263 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 1264 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
1265 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
1266 | if (IS_THUMB_ADDR (lr)) | |
1267 | cpsr |= CPSR_T; | |
1268 | else | |
1269 | cpsr &= ~CPSR_T; | |
ca38c58e | 1270 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
1271 | |
1272 | default: | |
1273 | internal_error (__FILE__, __LINE__, | |
1274 | _("Unexpected register %d"), regnum); | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | static void | |
1279 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1280 | struct dwarf2_frame_state_reg *reg, | |
1281 | struct frame_info *this_frame) | |
1282 | { | |
1283 | switch (regnum) | |
1284 | { | |
1285 | case ARM_PC_REGNUM: | |
1286 | case ARM_PS_REGNUM: | |
1287 | reg->how = DWARF2_FRAME_REG_FN; | |
1288 | reg->loc.fn = arm_dwarf2_prev_register; | |
1289 | break; | |
1290 | case ARM_SP_REGNUM: | |
1291 | reg->how = DWARF2_FRAME_REG_CFA; | |
1292 | break; | |
1293 | } | |
1294 | } | |
1295 | ||
2dd604e7 RE |
1296 | /* When arguments must be pushed onto the stack, they go on in reverse |
1297 | order. The code below implements a FILO (stack) to do this. */ | |
1298 | ||
1299 | struct stack_item | |
1300 | { | |
1301 | int len; | |
1302 | struct stack_item *prev; | |
1303 | void *data; | |
1304 | }; | |
1305 | ||
1306 | static struct stack_item * | |
1307 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1308 | { | |
1309 | struct stack_item *si; | |
1310 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1311 | si->data = xmalloc (len); |
2dd604e7 RE |
1312 | si->len = len; |
1313 | si->prev = prev; | |
1314 | memcpy (si->data, contents, len); | |
1315 | return si; | |
1316 | } | |
1317 | ||
1318 | static struct stack_item * | |
1319 | pop_stack_item (struct stack_item *si) | |
1320 | { | |
1321 | struct stack_item *dead = si; | |
1322 | si = si->prev; | |
1323 | xfree (dead->data); | |
1324 | xfree (dead); | |
1325 | return si; | |
1326 | } | |
1327 | ||
2af48f68 PB |
1328 | |
1329 | /* Return the alignment (in bytes) of the given type. */ | |
1330 | ||
1331 | static int | |
1332 | arm_type_align (struct type *t) | |
1333 | { | |
1334 | int n; | |
1335 | int align; | |
1336 | int falign; | |
1337 | ||
1338 | t = check_typedef (t); | |
1339 | switch (TYPE_CODE (t)) | |
1340 | { | |
1341 | default: | |
1342 | /* Should never happen. */ | |
1343 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1344 | return 4; | |
1345 | ||
1346 | case TYPE_CODE_PTR: | |
1347 | case TYPE_CODE_ENUM: | |
1348 | case TYPE_CODE_INT: | |
1349 | case TYPE_CODE_FLT: | |
1350 | case TYPE_CODE_SET: | |
1351 | case TYPE_CODE_RANGE: | |
1352 | case TYPE_CODE_BITSTRING: | |
1353 | case TYPE_CODE_REF: | |
1354 | case TYPE_CODE_CHAR: | |
1355 | case TYPE_CODE_BOOL: | |
1356 | return TYPE_LENGTH (t); | |
1357 | ||
1358 | case TYPE_CODE_ARRAY: | |
1359 | case TYPE_CODE_COMPLEX: | |
1360 | /* TODO: What about vector types? */ | |
1361 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1362 | ||
1363 | case TYPE_CODE_STRUCT: | |
1364 | case TYPE_CODE_UNION: | |
1365 | align = 1; | |
1366 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1367 | { | |
1368 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1369 | if (falign > align) | |
1370 | align = falign; | |
1371 | } | |
1372 | return align; | |
1373 | } | |
1374 | } | |
1375 | ||
2dd604e7 RE |
1376 | /* We currently only support passing parameters in integer registers. This |
1377 | conforms with GCC's default model. Several other variants exist and | |
1378 | we should probably support some of them based on the selected ABI. */ | |
1379 | ||
1380 | static CORE_ADDR | |
7d9b040b | 1381 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1382 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1383 | struct value **args, CORE_ADDR sp, int struct_return, | |
1384 | CORE_ADDR struct_addr) | |
2dd604e7 | 1385 | { |
e17a4113 | 1386 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
1387 | int argnum; |
1388 | int argreg; | |
1389 | int nstack; | |
1390 | struct stack_item *si = NULL; | |
1391 | ||
6a65450a AC |
1392 | /* Set the return address. For the ARM, the return breakpoint is |
1393 | always at BP_ADDR. */ | |
2dd604e7 | 1394 | /* XXX Fix for Thumb. */ |
6a65450a | 1395 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1396 | |
1397 | /* Walk through the list of args and determine how large a temporary | |
1398 | stack is required. Need to take care here as structs may be | |
1399 | passed on the stack, and we have to to push them. */ | |
1400 | nstack = 0; | |
1401 | ||
1402 | argreg = ARM_A1_REGNUM; | |
1403 | nstack = 0; | |
1404 | ||
2dd604e7 RE |
1405 | /* The struct_return pointer occupies the first parameter |
1406 | passing register. */ | |
1407 | if (struct_return) | |
1408 | { | |
1409 | if (arm_debug) | |
5af949e3 | 1410 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
2af46ca0 | 1411 | gdbarch_register_name (gdbarch, argreg), |
5af949e3 | 1412 | paddress (gdbarch, struct_addr)); |
2dd604e7 RE |
1413 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
1414 | argreg++; | |
1415 | } | |
1416 | ||
1417 | for (argnum = 0; argnum < nargs; argnum++) | |
1418 | { | |
1419 | int len; | |
1420 | struct type *arg_type; | |
1421 | struct type *target_type; | |
1422 | enum type_code typecode; | |
0fd88904 | 1423 | bfd_byte *val; |
2af48f68 | 1424 | int align; |
2dd604e7 | 1425 | |
df407dfe | 1426 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1427 | len = TYPE_LENGTH (arg_type); |
1428 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1429 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1430 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1431 | |
2af48f68 PB |
1432 | align = arm_type_align (arg_type); |
1433 | /* Round alignment up to a whole number of words. */ | |
1434 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1435 | /* Different ABIs have different maximum alignments. */ | |
1436 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1437 | { | |
1438 | /* The APCS ABI only requires word alignment. */ | |
1439 | align = INT_REGISTER_SIZE; | |
1440 | } | |
1441 | else | |
1442 | { | |
1443 | /* The AAPCS requires at most doubleword alignment. */ | |
1444 | if (align > INT_REGISTER_SIZE * 2) | |
1445 | align = INT_REGISTER_SIZE * 2; | |
1446 | } | |
1447 | ||
1448 | /* Push stack padding for dowubleword alignment. */ | |
1449 | if (nstack & (align - 1)) | |
1450 | { | |
1451 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1452 | nstack += INT_REGISTER_SIZE; | |
1453 | } | |
1454 | ||
1455 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1456 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1457 | && align > INT_REGISTER_SIZE | |
1458 | && argreg & 1) | |
1459 | argreg++; | |
1460 | ||
2dd604e7 RE |
1461 | /* If the argument is a pointer to a function, and it is a |
1462 | Thumb function, create a LOCAL copy of the value and set | |
1463 | the THUMB bit in it. */ | |
1464 | if (TYPE_CODE_PTR == typecode | |
1465 | && target_type != NULL | |
1466 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1467 | { | |
e17a4113 | 1468 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
2dd604e7 RE |
1469 | if (arm_pc_is_thumb (regval)) |
1470 | { | |
1471 | val = alloca (len); | |
e17a4113 UW |
1472 | store_unsigned_integer (val, len, byte_order, |
1473 | MAKE_THUMB_ADDR (regval)); | |
2dd604e7 RE |
1474 | } |
1475 | } | |
1476 | ||
1477 | /* Copy the argument to general registers or the stack in | |
1478 | register-sized pieces. Large arguments are split between | |
1479 | registers and stack. */ | |
1480 | while (len > 0) | |
1481 | { | |
f0c9063c | 1482 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 RE |
1483 | |
1484 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1485 | { | |
1486 | /* The argument is being passed in a general purpose | |
1487 | register. */ | |
e17a4113 UW |
1488 | CORE_ADDR regval |
1489 | = extract_unsigned_integer (val, partial_len, byte_order); | |
1490 | if (byte_order == BFD_ENDIAN_BIG) | |
8bf8793c | 1491 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
1492 | if (arm_debug) |
1493 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
1494 | argnum, |
1495 | gdbarch_register_name | |
2af46ca0 | 1496 | (gdbarch, argreg), |
f0c9063c | 1497 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
1498 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1499 | argreg++; | |
1500 | } | |
1501 | else | |
1502 | { | |
1503 | /* Push the arguments onto the stack. */ | |
1504 | if (arm_debug) | |
1505 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1506 | argnum, nstack); | |
f0c9063c UW |
1507 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
1508 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
1509 | } |
1510 | ||
1511 | len -= partial_len; | |
1512 | val += partial_len; | |
1513 | } | |
1514 | } | |
1515 | /* If we have an odd number of words to push, then decrement the stack | |
1516 | by one word now, so first stack argument will be dword aligned. */ | |
1517 | if (nstack & 4) | |
1518 | sp -= 4; | |
1519 | ||
1520 | while (si) | |
1521 | { | |
1522 | sp -= si->len; | |
1523 | write_memory (sp, si->data, si->len); | |
1524 | si = pop_stack_item (si); | |
1525 | } | |
1526 | ||
1527 | /* Finally, update teh SP register. */ | |
1528 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1529 | ||
1530 | return sp; | |
1531 | } | |
1532 | ||
f53f0d0b PB |
1533 | |
1534 | /* Always align the frame to an 8-byte boundary. This is required on | |
1535 | some platforms and harmless on the rest. */ | |
1536 | ||
1537 | static CORE_ADDR | |
1538 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1539 | { | |
1540 | /* Align the stack to eight bytes. */ | |
1541 | return sp & ~ (CORE_ADDR) 7; | |
1542 | } | |
1543 | ||
c906108c | 1544 | static void |
ed9a39eb | 1545 | print_fpu_flags (int flags) |
c906108c | 1546 | { |
c5aa993b JM |
1547 | if (flags & (1 << 0)) |
1548 | fputs ("IVO ", stdout); | |
1549 | if (flags & (1 << 1)) | |
1550 | fputs ("DVZ ", stdout); | |
1551 | if (flags & (1 << 2)) | |
1552 | fputs ("OFL ", stdout); | |
1553 | if (flags & (1 << 3)) | |
1554 | fputs ("UFL ", stdout); | |
1555 | if (flags & (1 << 4)) | |
1556 | fputs ("INX ", stdout); | |
1557 | putchar ('\n'); | |
c906108c SS |
1558 | } |
1559 | ||
5e74b15c RE |
1560 | /* Print interesting information about the floating point processor |
1561 | (if present) or emulator. */ | |
34e8f22d | 1562 | static void |
d855c300 | 1563 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1564 | struct frame_info *frame, const char *args) |
c906108c | 1565 | { |
9c9acae0 | 1566 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
1567 | int type; |
1568 | ||
1569 | type = (status >> 24) & 127; | |
edefbb7c AC |
1570 | if (status & (1 << 31)) |
1571 | printf (_("Hardware FPU type %d\n"), type); | |
1572 | else | |
1573 | printf (_("Software FPU type %d\n"), type); | |
1574 | /* i18n: [floating point unit] mask */ | |
1575 | fputs (_("mask: "), stdout); | |
c5aa993b | 1576 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1577 | /* i18n: [floating point unit] flags */ |
1578 | fputs (_("flags: "), stdout); | |
c5aa993b | 1579 | print_fpu_flags (status); |
c906108c SS |
1580 | } |
1581 | ||
27067745 UW |
1582 | /* Construct the ARM extended floating point type. */ |
1583 | static struct type * | |
1584 | arm_ext_type (struct gdbarch *gdbarch) | |
1585 | { | |
1586 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1587 | ||
1588 | if (!tdep->arm_ext_type) | |
1589 | tdep->arm_ext_type | |
e9bb382b | 1590 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
1591 | floatformats_arm_ext); |
1592 | ||
1593 | return tdep->arm_ext_type; | |
1594 | } | |
1595 | ||
34e8f22d RE |
1596 | /* Return the GDB type object for the "standard" data type of data in |
1597 | register N. */ | |
1598 | ||
1599 | static struct type * | |
7a5ea0d4 | 1600 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1601 | { |
34e8f22d | 1602 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
27067745 | 1603 | return arm_ext_type (gdbarch); |
e4c16157 | 1604 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 1605 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 1606 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 1607 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
1608 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
1609 | /* These registers are only supported on targets which supply | |
1610 | an XML description. */ | |
df4df182 | 1611 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 1612 | else |
df4df182 | 1613 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
1614 | } |
1615 | ||
ff6f572f DJ |
1616 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
1617 | number. */ | |
1618 | ||
1619 | static int | |
d3f73121 | 1620 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
1621 | { |
1622 | /* Core integer regs. */ | |
1623 | if (reg >= 0 && reg <= 15) | |
1624 | return reg; | |
1625 | ||
1626 | /* Legacy FPA encoding. These were once used in a way which | |
1627 | overlapped with VFP register numbering, so their use is | |
1628 | discouraged, but GDB doesn't support the ARM toolchain | |
1629 | which used them for VFP. */ | |
1630 | if (reg >= 16 && reg <= 23) | |
1631 | return ARM_F0_REGNUM + reg - 16; | |
1632 | ||
1633 | /* New assignments for the FPA registers. */ | |
1634 | if (reg >= 96 && reg <= 103) | |
1635 | return ARM_F0_REGNUM + reg - 96; | |
1636 | ||
1637 | /* WMMX register assignments. */ | |
1638 | if (reg >= 104 && reg <= 111) | |
1639 | return ARM_WCGR0_REGNUM + reg - 104; | |
1640 | ||
1641 | if (reg >= 112 && reg <= 127) | |
1642 | return ARM_WR0_REGNUM + reg - 112; | |
1643 | ||
1644 | if (reg >= 192 && reg <= 199) | |
1645 | return ARM_WC0_REGNUM + reg - 192; | |
1646 | ||
1647 | return -1; | |
1648 | } | |
1649 | ||
26216b98 AC |
1650 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1651 | static int | |
e7faf938 | 1652 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
1653 | { |
1654 | int reg = regnum; | |
e7faf938 | 1655 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 1656 | |
ff6f572f DJ |
1657 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
1658 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
1659 | ||
1660 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
1661 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
1662 | ||
1663 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
1664 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
1665 | ||
26216b98 AC |
1666 | if (reg < NUM_GREGS) |
1667 | return SIM_ARM_R0_REGNUM + reg; | |
1668 | reg -= NUM_GREGS; | |
1669 | ||
1670 | if (reg < NUM_FREGS) | |
1671 | return SIM_ARM_FP0_REGNUM + reg; | |
1672 | reg -= NUM_FREGS; | |
1673 | ||
1674 | if (reg < NUM_SREGS) | |
1675 | return SIM_ARM_FPS_REGNUM + reg; | |
1676 | reg -= NUM_SREGS; | |
1677 | ||
edefbb7c | 1678 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1679 | } |
34e8f22d | 1680 | |
a37b3cc0 AC |
1681 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1682 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1683 | It is thought that this is is the floating-point register format on | |
1684 | little-endian systems. */ | |
c906108c | 1685 | |
ed9a39eb | 1686 | static void |
b508a996 | 1687 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 1688 | void *dbl, int endianess) |
c906108c | 1689 | { |
a37b3cc0 | 1690 | DOUBLEST d; |
be8626e0 MD |
1691 | |
1692 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
1693 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1694 | else | |
1695 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1696 | ptr, &d); | |
b508a996 | 1697 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1698 | } |
1699 | ||
34e8f22d | 1700 | static void |
be8626e0 MD |
1701 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
1702 | int endianess) | |
c906108c | 1703 | { |
a37b3cc0 | 1704 | DOUBLEST d; |
be8626e0 | 1705 | |
b508a996 | 1706 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 1707 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1708 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1709 | else | |
1710 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1711 | &d, dbl); | |
c906108c | 1712 | } |
ed9a39eb | 1713 | |
c906108c | 1714 | static int |
ed9a39eb | 1715 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1716 | { |
1717 | if (cond == INST_AL || cond == INST_NV) | |
1718 | return 1; | |
1719 | ||
1720 | switch (cond) | |
1721 | { | |
1722 | case INST_EQ: | |
1723 | return ((status_reg & FLAG_Z) != 0); | |
1724 | case INST_NE: | |
1725 | return ((status_reg & FLAG_Z) == 0); | |
1726 | case INST_CS: | |
1727 | return ((status_reg & FLAG_C) != 0); | |
1728 | case INST_CC: | |
1729 | return ((status_reg & FLAG_C) == 0); | |
1730 | case INST_MI: | |
1731 | return ((status_reg & FLAG_N) != 0); | |
1732 | case INST_PL: | |
1733 | return ((status_reg & FLAG_N) == 0); | |
1734 | case INST_VS: | |
1735 | return ((status_reg & FLAG_V) != 0); | |
1736 | case INST_VC: | |
1737 | return ((status_reg & FLAG_V) == 0); | |
1738 | case INST_HI: | |
1739 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1740 | case INST_LS: | |
1741 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1742 | case INST_GE: | |
1743 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1744 | case INST_LT: | |
1745 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1746 | case INST_GT: | |
1747 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1748 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1749 | case INST_LE: |
1750 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1751 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1752 | } |
1753 | return 1; | |
1754 | } | |
1755 | ||
9512d7fd | 1756 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1757 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1758 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1759 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1760 | #define sbits(obj,st,fn) \ | |
1761 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1762 | #define BranchDest(addr,instr) \ | |
1763 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1764 | #define ARM_PC_32 1 | |
1765 | ||
1766 | static unsigned long | |
0b1b3e42 UW |
1767 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
1768 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
1769 | { |
1770 | unsigned long res, shift; | |
1771 | int rm = bits (inst, 0, 3); | |
1772 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1773 | |
1774 | if (bit (inst, 4)) | |
c906108c SS |
1775 | { |
1776 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
1777 | shift = (rs == 15 ? pc_val + 8 |
1778 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
1779 | } |
1780 | else | |
1781 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1782 | |
1783 | res = (rm == 15 | |
c906108c | 1784 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1785 | + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 1786 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
1787 | |
1788 | switch (shifttype) | |
1789 | { | |
c5aa993b | 1790 | case 0: /* LSL */ |
c906108c SS |
1791 | res = shift >= 32 ? 0 : res << shift; |
1792 | break; | |
c5aa993b JM |
1793 | |
1794 | case 1: /* LSR */ | |
c906108c SS |
1795 | res = shift >= 32 ? 0 : res >> shift; |
1796 | break; | |
1797 | ||
c5aa993b JM |
1798 | case 2: /* ASR */ |
1799 | if (shift >= 32) | |
1800 | shift = 31; | |
c906108c SS |
1801 | res = ((res & 0x80000000L) |
1802 | ? ~((~res) >> shift) : res >> shift); | |
1803 | break; | |
1804 | ||
c5aa993b | 1805 | case 3: /* ROR/RRX */ |
c906108c SS |
1806 | shift &= 31; |
1807 | if (shift == 0) | |
1808 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1809 | else | |
c5aa993b | 1810 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1811 | break; |
1812 | } | |
1813 | ||
1814 | return res & 0xffffffff; | |
1815 | } | |
1816 | ||
c906108c SS |
1817 | /* Return number of 1-bits in VAL. */ |
1818 | ||
1819 | static int | |
ed9a39eb | 1820 | bitcount (unsigned long val) |
c906108c SS |
1821 | { |
1822 | int nbits; | |
1823 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1824 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1825 | return nbits; |
1826 | } | |
1827 | ||
ad527d2e | 1828 | static CORE_ADDR |
0b1b3e42 | 1829 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1830 | { |
2af46ca0 | 1831 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
1832 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1833 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c5aa993b | 1834 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
e17a4113 | 1835 | unsigned short inst1; |
94c30b78 | 1836 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1837 | unsigned long offset; |
1838 | ||
e17a4113 | 1839 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); |
9d4fde75 | 1840 | |
c906108c SS |
1841 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
1842 | { | |
1843 | CORE_ADDR sp; | |
1844 | ||
1845 | /* Fetch the saved PC from the stack. It's stored above | |
1846 | all of the other registers. */ | |
f0c9063c | 1847 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 1848 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
e17a4113 | 1849 | nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); |
2af46ca0 | 1850 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 1851 | if (nextpc == pc) |
edefbb7c | 1852 | error (_("Infinite loop detected")); |
c906108c SS |
1853 | } |
1854 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1855 | { | |
0b1b3e42 | 1856 | unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1857 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1858 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1859 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1860 | } | |
1861 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1862 | { | |
1863 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1864 | } | |
aa17d93e | 1865 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1866 | { |
e17a4113 UW |
1867 | unsigned short inst2; |
1868 | inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); | |
c5aa993b | 1869 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1870 | nextpc = pc_val + offset; |
aa17d93e DJ |
1871 | /* For BLX make sure to clear the low bits. */ |
1872 | if (bits (inst2, 11, 12) == 1) | |
1873 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1874 | } |
aa17d93e | 1875 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1876 | { |
1877 | if (bits (inst1, 3, 6) == 0x0f) | |
1878 | nextpc = pc_val; | |
1879 | else | |
0b1b3e42 | 1880 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 1881 | |
2af46ca0 | 1882 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
9498281f | 1883 | if (nextpc == pc) |
edefbb7c | 1884 | error (_("Infinite loop detected")); |
9498281f | 1885 | } |
c906108c SS |
1886 | |
1887 | return nextpc; | |
1888 | } | |
1889 | ||
daddc3c1 | 1890 | CORE_ADDR |
0b1b3e42 | 1891 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1892 | { |
2af46ca0 | 1893 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 UW |
1894 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1895 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
c906108c SS |
1896 | unsigned long pc_val; |
1897 | unsigned long this_instr; | |
1898 | unsigned long status; | |
1899 | CORE_ADDR nextpc; | |
1900 | ||
b39cc962 | 1901 | if (arm_frame_is_thumb (frame)) |
0b1b3e42 | 1902 | return thumb_get_next_pc (frame, pc); |
c906108c SS |
1903 | |
1904 | pc_val = (unsigned long) pc; | |
e17a4113 | 1905 | this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); |
9d4fde75 | 1906 | |
0b1b3e42 | 1907 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1908 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 1909 | |
daddc3c1 DJ |
1910 | if (bits (this_instr, 28, 31) == INST_NV) |
1911 | switch (bits (this_instr, 24, 27)) | |
1912 | { | |
1913 | case 0xa: | |
1914 | case 0xb: | |
1915 | { | |
1916 | /* Branch with Link and change to Thumb. */ | |
1917 | nextpc = BranchDest (pc, this_instr); | |
1918 | nextpc |= bit (this_instr, 24) << 1; | |
1919 | ||
e1e01acd | 1920 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
daddc3c1 DJ |
1921 | if (nextpc == pc) |
1922 | error (_("Infinite loop detected")); | |
1923 | break; | |
1924 | } | |
1925 | case 0xc: | |
1926 | case 0xd: | |
1927 | case 0xe: | |
1928 | /* Coprocessor register transfer. */ | |
1929 | if (bits (this_instr, 12, 15) == 15) | |
1930 | error (_("Invalid update to pc in instruction")); | |
1931 | break; | |
1932 | } | |
1933 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
1934 | { |
1935 | switch (bits (this_instr, 24, 27)) | |
1936 | { | |
c5aa993b | 1937 | case 0x0: |
94c30b78 | 1938 | case 0x1: /* data processing */ |
c5aa993b JM |
1939 | case 0x2: |
1940 | case 0x3: | |
c906108c SS |
1941 | { |
1942 | unsigned long operand1, operand2, result = 0; | |
1943 | unsigned long rn; | |
1944 | int c; | |
c5aa993b | 1945 | |
c906108c SS |
1946 | if (bits (this_instr, 12, 15) != 15) |
1947 | break; | |
1948 | ||
1949 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1950 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1951 | error (_("Invalid update to pc in instruction")); |
c906108c | 1952 | |
9498281f | 1953 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
1954 | if (bits (this_instr, 4, 27) == 0x12fff1 |
1955 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
1956 | { |
1957 | rn = bits (this_instr, 0, 3); | |
0b1b3e42 UW |
1958 | result = (rn == 15) ? pc_val + 8 |
1959 | : get_frame_register_unsigned (frame, rn); | |
bf6ae464 | 1960 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 1961 | (gdbarch, result); |
9498281f DJ |
1962 | |
1963 | if (nextpc == pc) | |
edefbb7c | 1964 | error (_("Infinite loop detected")); |
9498281f DJ |
1965 | |
1966 | return nextpc; | |
1967 | } | |
1968 | ||
c906108c SS |
1969 | /* Multiply into PC */ |
1970 | c = (status & FLAG_C) ? 1 : 0; | |
1971 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
1972 | operand1 = (rn == 15) ? pc_val + 8 |
1973 | : get_frame_register_unsigned (frame, rn); | |
c5aa993b | 1974 | |
c906108c SS |
1975 | if (bit (this_instr, 25)) |
1976 | { | |
1977 | unsigned long immval = bits (this_instr, 0, 7); | |
1978 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1979 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1980 | & 0xffffffff; | |
c906108c | 1981 | } |
c5aa993b | 1982 | else /* operand 2 is a shifted register */ |
0b1b3e42 | 1983 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
c5aa993b | 1984 | |
c906108c SS |
1985 | switch (bits (this_instr, 21, 24)) |
1986 | { | |
c5aa993b | 1987 | case 0x0: /*and */ |
c906108c SS |
1988 | result = operand1 & operand2; |
1989 | break; | |
1990 | ||
c5aa993b | 1991 | case 0x1: /*eor */ |
c906108c SS |
1992 | result = operand1 ^ operand2; |
1993 | break; | |
1994 | ||
c5aa993b | 1995 | case 0x2: /*sub */ |
c906108c SS |
1996 | result = operand1 - operand2; |
1997 | break; | |
1998 | ||
c5aa993b | 1999 | case 0x3: /*rsb */ |
c906108c SS |
2000 | result = operand2 - operand1; |
2001 | break; | |
2002 | ||
c5aa993b | 2003 | case 0x4: /*add */ |
c906108c SS |
2004 | result = operand1 + operand2; |
2005 | break; | |
2006 | ||
c5aa993b | 2007 | case 0x5: /*adc */ |
c906108c SS |
2008 | result = operand1 + operand2 + c; |
2009 | break; | |
2010 | ||
c5aa993b | 2011 | case 0x6: /*sbc */ |
c906108c SS |
2012 | result = operand1 - operand2 + c; |
2013 | break; | |
2014 | ||
c5aa993b | 2015 | case 0x7: /*rsc */ |
c906108c SS |
2016 | result = operand2 - operand1 + c; |
2017 | break; | |
2018 | ||
c5aa993b JM |
2019 | case 0x8: |
2020 | case 0x9: | |
2021 | case 0xa: | |
2022 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
2023 | result = (unsigned long) nextpc; |
2024 | break; | |
2025 | ||
c5aa993b | 2026 | case 0xc: /*orr */ |
c906108c SS |
2027 | result = operand1 | operand2; |
2028 | break; | |
2029 | ||
c5aa993b | 2030 | case 0xd: /*mov */ |
c906108c SS |
2031 | /* Always step into a function. */ |
2032 | result = operand2; | |
c5aa993b | 2033 | break; |
c906108c | 2034 | |
c5aa993b | 2035 | case 0xe: /*bic */ |
c906108c SS |
2036 | result = operand1 & ~operand2; |
2037 | break; | |
2038 | ||
c5aa993b | 2039 | case 0xf: /*mvn */ |
c906108c SS |
2040 | result = ~operand2; |
2041 | break; | |
2042 | } | |
bf6ae464 | 2043 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 2044 | (gdbarch, result); |
c906108c SS |
2045 | |
2046 | if (nextpc == pc) | |
edefbb7c | 2047 | error (_("Infinite loop detected")); |
c906108c SS |
2048 | break; |
2049 | } | |
c5aa993b JM |
2050 | |
2051 | case 0x4: | |
2052 | case 0x5: /* data transfer */ | |
2053 | case 0x6: | |
2054 | case 0x7: | |
c906108c SS |
2055 | if (bit (this_instr, 20)) |
2056 | { | |
2057 | /* load */ | |
2058 | if (bits (this_instr, 12, 15) == 15) | |
2059 | { | |
2060 | /* rd == pc */ | |
c5aa993b | 2061 | unsigned long rn; |
c906108c | 2062 | unsigned long base; |
c5aa993b | 2063 | |
c906108c | 2064 | if (bit (this_instr, 22)) |
edefbb7c | 2065 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
2066 | |
2067 | /* byte write to PC */ | |
2068 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
2069 | base = (rn == 15) ? pc_val + 8 |
2070 | : get_frame_register_unsigned (frame, rn); | |
c906108c SS |
2071 | if (bit (this_instr, 24)) |
2072 | { | |
2073 | /* pre-indexed */ | |
2074 | int c = (status & FLAG_C) ? 1 : 0; | |
2075 | unsigned long offset = | |
c5aa993b | 2076 | (bit (this_instr, 25) |
0b1b3e42 | 2077 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 2078 | : bits (this_instr, 0, 11)); |
c906108c SS |
2079 | |
2080 | if (bit (this_instr, 23)) | |
2081 | base += offset; | |
2082 | else | |
2083 | base -= offset; | |
2084 | } | |
c5aa993b | 2085 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
e17a4113 | 2086 | 4, byte_order); |
c5aa993b | 2087 | |
2af46ca0 | 2088 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c SS |
2089 | |
2090 | if (nextpc == pc) | |
edefbb7c | 2091 | error (_("Infinite loop detected")); |
c906108c SS |
2092 | } |
2093 | } | |
2094 | break; | |
c5aa993b JM |
2095 | |
2096 | case 0x8: | |
2097 | case 0x9: /* block transfer */ | |
c906108c SS |
2098 | if (bit (this_instr, 20)) |
2099 | { | |
2100 | /* LDM */ | |
2101 | if (bit (this_instr, 15)) | |
2102 | { | |
2103 | /* loading pc */ | |
2104 | int offset = 0; | |
2105 | ||
2106 | if (bit (this_instr, 23)) | |
2107 | { | |
2108 | /* up */ | |
2109 | unsigned long reglist = bits (this_instr, 0, 14); | |
2110 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2111 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2112 | offset += 4; |
2113 | } | |
2114 | else if (bit (this_instr, 24)) | |
2115 | offset = -4; | |
c5aa993b | 2116 | |
c906108c | 2117 | { |
c5aa993b | 2118 | unsigned long rn_val = |
0b1b3e42 UW |
2119 | get_frame_register_unsigned (frame, |
2120 | bits (this_instr, 16, 19)); | |
c906108c SS |
2121 | nextpc = |
2122 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2123 | + offset), |
e17a4113 | 2124 | 4, byte_order); |
c906108c | 2125 | } |
bf6ae464 | 2126 | nextpc = gdbarch_addr_bits_remove |
2af46ca0 | 2127 | (gdbarch, nextpc); |
c906108c | 2128 | if (nextpc == pc) |
edefbb7c | 2129 | error (_("Infinite loop detected")); |
c906108c SS |
2130 | } |
2131 | } | |
2132 | break; | |
c5aa993b JM |
2133 | |
2134 | case 0xb: /* branch & link */ | |
2135 | case 0xa: /* branch */ | |
c906108c SS |
2136 | { |
2137 | nextpc = BranchDest (pc, this_instr); | |
2138 | ||
2af46ca0 | 2139 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 2140 | if (nextpc == pc) |
edefbb7c | 2141 | error (_("Infinite loop detected")); |
c906108c SS |
2142 | break; |
2143 | } | |
c5aa993b JM |
2144 | |
2145 | case 0xc: | |
2146 | case 0xd: | |
2147 | case 0xe: /* coproc ops */ | |
2148 | case 0xf: /* SWI */ | |
c906108c SS |
2149 | break; |
2150 | ||
2151 | default: | |
edefbb7c | 2152 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
2153 | return (pc); |
2154 | } | |
2155 | } | |
2156 | ||
2157 | return nextpc; | |
2158 | } | |
2159 | ||
9512d7fd FN |
2160 | /* single_step() is called just before we want to resume the inferior, |
2161 | if we want to single-step it but there is no hardware or kernel | |
2162 | single-step support. We find the target of the coming instruction | |
e0cd558a | 2163 | and breakpoint it. */ |
9512d7fd | 2164 | |
190dce09 | 2165 | int |
0b1b3e42 | 2166 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 2167 | { |
a6d9a66e UW |
2168 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2169 | ||
8181d85f DJ |
2170 | /* NOTE: This may insert the wrong breakpoint instruction when |
2171 | single-stepping over a mode-changing instruction, if the | |
2172 | CPSR heuristics are used. */ | |
9512d7fd | 2173 | |
0b1b3e42 | 2174 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
a6d9a66e | 2175 | insert_single_step_breakpoint (gdbarch, next_pc); |
e6590a1b UW |
2176 | |
2177 | return 1; | |
9512d7fd | 2178 | } |
9512d7fd | 2179 | |
c906108c SS |
2180 | #include "bfd-in2.h" |
2181 | #include "libcoff.h" | |
2182 | ||
2183 | static int | |
ed9a39eb | 2184 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2185 | { |
2186 | if (arm_pc_is_thumb (memaddr)) | |
2187 | { | |
c5aa993b JM |
2188 | static asymbol *asym; |
2189 | static combined_entry_type ce; | |
2190 | static struct coff_symbol_struct csym; | |
27cddce2 | 2191 | static struct bfd fake_bfd; |
c5aa993b | 2192 | static bfd_target fake_target; |
c906108c SS |
2193 | |
2194 | if (csym.native == NULL) | |
2195 | { | |
da3c6d4a MS |
2196 | /* Create a fake symbol vector containing a Thumb symbol. |
2197 | This is solely so that the code in print_insn_little_arm() | |
2198 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2199 | the presence of a Thumb symbol and switch to decoding | |
2200 | Thumb instructions. */ | |
c5aa993b JM |
2201 | |
2202 | fake_target.flavour = bfd_target_coff_flavour; | |
2203 | fake_bfd.xvec = &fake_target; | |
c906108c | 2204 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2205 | csym.native = &ce; |
2206 | csym.symbol.the_bfd = &fake_bfd; | |
2207 | csym.symbol.name = "fake"; | |
2208 | asym = (asymbol *) & csym; | |
c906108c | 2209 | } |
c5aa993b | 2210 | |
c906108c | 2211 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2212 | info->symbols = &asym; |
c906108c SS |
2213 | } |
2214 | else | |
2215 | info->symbols = NULL; | |
c5aa993b | 2216 | |
40887e1a | 2217 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
2218 | return print_insn_big_arm (memaddr, info); |
2219 | else | |
2220 | return print_insn_little_arm (memaddr, info); | |
2221 | } | |
2222 | ||
66e810cd RE |
2223 | /* The following define instruction sequences that will cause ARM |
2224 | cpu's to take an undefined instruction trap. These are used to | |
2225 | signal a breakpoint to GDB. | |
2226 | ||
2227 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2228 | modes. A different instruction is required for each mode. The ARM | |
2229 | cpu's can also be big or little endian. Thus four different | |
2230 | instructions are needed to support all cases. | |
2231 | ||
2232 | Note: ARMv4 defines several new instructions that will take the | |
2233 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2234 | not in fact add the new instructions. The new undefined | |
2235 | instructions in ARMv4 are all instructions that had no defined | |
2236 | behaviour in earlier chips. There is no guarantee that they will | |
2237 | raise an exception, but may be treated as NOP's. In practice, it | |
2238 | may only safe to rely on instructions matching: | |
2239 | ||
2240 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2241 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2242 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2243 | ||
2244 | Even this may only true if the condition predicate is true. The | |
2245 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2246 | ||
2247 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2248 | and NetBSD all use a software interrupt rather than an undefined | |
2249 | instruction to force a trap. This can be handled by by the | |
2250 | abi-specific code during establishment of the gdbarch vector. */ | |
2251 | ||
66e810cd | 2252 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
66e810cd | 2253 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
190dce09 UW |
2254 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
2255 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
66e810cd RE |
2256 | |
2257 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2258 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2259 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2260 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2261 | ||
34e8f22d RE |
2262 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2263 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2264 | breakpoint should be used. It returns a pointer to a string of |
2265 | bytes that encode a breakpoint instruction, stores the length of | |
2266 | the string to *lenptr, and adjusts the program counter (if | |
2267 | necessary) to point to the actual memory location where the | |
c906108c SS |
2268 | breakpoint should be inserted. */ |
2269 | ||
ab89facf | 2270 | static const unsigned char * |
67d57894 | 2271 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2272 | { |
67d57894 | 2273 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
66e810cd | 2274 | |
4bf7064c | 2275 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 2276 | { |
66e810cd RE |
2277 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2278 | *lenptr = tdep->thumb_breakpoint_size; | |
2279 | return tdep->thumb_breakpoint; | |
c906108c SS |
2280 | } |
2281 | else | |
2282 | { | |
66e810cd RE |
2283 | *lenptr = tdep->arm_breakpoint_size; |
2284 | return tdep->arm_breakpoint; | |
c906108c SS |
2285 | } |
2286 | } | |
ed9a39eb JM |
2287 | |
2288 | /* Extract from an array REGBUF containing the (raw) register state a | |
2289 | function return value of type TYPE, and copy that, in virtual | |
2290 | format, into VALBUF. */ | |
2291 | ||
34e8f22d | 2292 | static void |
5238cf52 MK |
2293 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2294 | gdb_byte *valbuf) | |
ed9a39eb | 2295 | { |
be8626e0 | 2296 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 2297 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 2298 | |
ed9a39eb | 2299 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2300 | { |
be8626e0 | 2301 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2302 | { |
2303 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2304 | { |
2305 | /* The value is in register F0 in internal format. We need to | |
2306 | extract the raw value and then convert it to the desired | |
2307 | internal type. */ | |
7a5ea0d4 | 2308 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2309 | |
2310 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2311 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
be8626e0 | 2312 | valbuf, gdbarch_byte_order (gdbarch)); |
b508a996 | 2313 | } |
08216dd7 RE |
2314 | break; |
2315 | ||
fd50bc42 | 2316 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2317 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2318 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2319 | if (TYPE_LENGTH (type) > 4) | |
2320 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2321 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2322 | break; |
2323 | ||
2324 | default: | |
2325 | internal_error | |
2326 | (__FILE__, __LINE__, | |
edefbb7c | 2327 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2328 | break; |
2329 | } | |
2330 | } | |
b508a996 RE |
2331 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2332 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2333 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2334 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2335 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2336 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2337 | { | |
2338 | /* If the the type is a plain integer, then the access is | |
2339 | straight-forward. Otherwise we have to play around a bit more. */ | |
2340 | int len = TYPE_LENGTH (type); | |
2341 | int regno = ARM_A1_REGNUM; | |
2342 | ULONGEST tmp; | |
2343 | ||
2344 | while (len > 0) | |
2345 | { | |
2346 | /* By using store_unsigned_integer we avoid having to do | |
2347 | anything special for small big-endian values. */ | |
2348 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2349 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2350 | (len > INT_REGISTER_SIZE |
2351 | ? INT_REGISTER_SIZE : len), | |
e17a4113 | 2352 | byte_order, tmp); |
7a5ea0d4 DJ |
2353 | len -= INT_REGISTER_SIZE; |
2354 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2355 | } |
2356 | } | |
ed9a39eb | 2357 | else |
b508a996 RE |
2358 | { |
2359 | /* For a structure or union the behaviour is as if the value had | |
2360 | been stored to word-aligned memory and then loaded into | |
2361 | registers with 32-bit load instruction(s). */ | |
2362 | int len = TYPE_LENGTH (type); | |
2363 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2364 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2365 | |
2366 | while (len > 0) | |
2367 | { | |
2368 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2369 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2370 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2371 | len -= INT_REGISTER_SIZE; | |
2372 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2373 | } |
2374 | } | |
34e8f22d RE |
2375 | } |
2376 | ||
67255d04 RE |
2377 | |
2378 | /* Will a function return an aggregate type in memory or in a | |
2379 | register? Return 0 if an aggregate type can be returned in a | |
2380 | register, 1 if it must be returned in memory. */ | |
2381 | ||
2382 | static int | |
2af48f68 | 2383 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2384 | { |
2385 | int nRc; | |
52f0bd74 | 2386 | enum type_code code; |
67255d04 | 2387 | |
44e1a9eb DJ |
2388 | CHECK_TYPEDEF (type); |
2389 | ||
67255d04 RE |
2390 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2391 | registers. For an aggregate type to be integer like, its size | |
f0c9063c | 2392 | must be less than or equal to INT_REGISTER_SIZE and the |
b1e29e33 AC |
2393 | offset of each addressable subfield must be zero. Note that bit |
2394 | fields are not addressable, and all addressable subfields of | |
2395 | unions always start at offset zero. | |
67255d04 RE |
2396 | |
2397 | This function is based on the behaviour of GCC 2.95.1. | |
2398 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2399 | ||
2400 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2401 | parameters correctly for a function returning the following | |
2402 | structure: struct { float f;}; This should be returned in memory, | |
2403 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2404 | know of any way to detect if a function like the above has been | |
2405 | compiled with the correct calling convention. */ | |
2406 | ||
2407 | /* All aggregate types that won't fit in a register must be returned | |
2408 | in memory. */ | |
f0c9063c | 2409 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
67255d04 RE |
2410 | { |
2411 | return 1; | |
2412 | } | |
2413 | ||
2af48f68 PB |
2414 | /* The AAPCS says all aggregates not larger than a word are returned |
2415 | in a register. */ | |
2416 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2417 | return 0; | |
2418 | ||
67255d04 RE |
2419 | /* The only aggregate types that can be returned in a register are |
2420 | structs and unions. Arrays must be returned in memory. */ | |
2421 | code = TYPE_CODE (type); | |
2422 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2423 | { | |
2424 | return 1; | |
2425 | } | |
2426 | ||
2427 | /* Assume all other aggregate types can be returned in a register. | |
2428 | Run a check for structures, unions and arrays. */ | |
2429 | nRc = 0; | |
2430 | ||
2431 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2432 | { | |
2433 | int i; | |
2434 | /* Need to check if this struct/union is "integer" like. For | |
2435 | this to be true, its size must be less than or equal to | |
f0c9063c | 2436 | INT_REGISTER_SIZE and the offset of each addressable |
b1e29e33 AC |
2437 | subfield must be zero. Note that bit fields are not |
2438 | addressable, and unions always start at offset zero. If any | |
2439 | of the subfields is a floating point type, the struct/union | |
2440 | cannot be an integer type. */ | |
67255d04 RE |
2441 | |
2442 | /* For each field in the object, check: | |
2443 | 1) Is it FP? --> yes, nRc = 1; | |
2444 | 2) Is it addressable (bitpos != 0) and | |
2445 | not packed (bitsize == 0)? | |
2446 | --> yes, nRc = 1 | |
2447 | */ | |
2448 | ||
2449 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2450 | { | |
2451 | enum type_code field_type_code; | |
44e1a9eb | 2452 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2453 | |
2454 | /* Is it a floating point type field? */ | |
2455 | if (field_type_code == TYPE_CODE_FLT) | |
2456 | { | |
2457 | nRc = 1; | |
2458 | break; | |
2459 | } | |
2460 | ||
2461 | /* If bitpos != 0, then we have to care about it. */ | |
2462 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2463 | { | |
2464 | /* Bitfields are not addressable. If the field bitsize is | |
2465 | zero, then the field is not packed. Hence it cannot be | |
2466 | a bitfield or any other packed type. */ | |
2467 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2468 | { | |
2469 | nRc = 1; | |
2470 | break; | |
2471 | } | |
2472 | } | |
2473 | } | |
2474 | } | |
2475 | ||
2476 | return nRc; | |
2477 | } | |
2478 | ||
34e8f22d RE |
2479 | /* Write into appropriate registers a function return value of type |
2480 | TYPE, given in virtual format. */ | |
2481 | ||
2482 | static void | |
b508a996 | 2483 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2484 | const gdb_byte *valbuf) |
34e8f22d | 2485 | { |
be8626e0 | 2486 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
e17a4113 | 2487 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 2488 | |
34e8f22d RE |
2489 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2490 | { | |
7a5ea0d4 | 2491 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2492 | |
be8626e0 | 2493 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2494 | { |
2495 | case ARM_FLOAT_FPA: | |
2496 | ||
be8626e0 MD |
2497 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
2498 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 2499 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
2500 | break; |
2501 | ||
fd50bc42 | 2502 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2503 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2504 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2505 | if (TYPE_LENGTH (type) > 4) | |
2506 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2507 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2508 | break; |
2509 | ||
2510 | default: | |
2511 | internal_error | |
2512 | (__FILE__, __LINE__, | |
edefbb7c | 2513 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2514 | break; |
2515 | } | |
34e8f22d | 2516 | } |
b508a996 RE |
2517 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2518 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2519 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2520 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2521 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2522 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2523 | { | |
2524 | if (TYPE_LENGTH (type) <= 4) | |
2525 | { | |
2526 | /* Values of one word or less are zero/sign-extended and | |
2527 | returned in r0. */ | |
7a5ea0d4 | 2528 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2529 | LONGEST val = unpack_long (type, valbuf); |
2530 | ||
e17a4113 | 2531 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
b508a996 RE |
2532 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2533 | } | |
2534 | else | |
2535 | { | |
2536 | /* Integral values greater than one word are stored in consecutive | |
2537 | registers starting with r0. This will always be a multiple of | |
2538 | the regiser size. */ | |
2539 | int len = TYPE_LENGTH (type); | |
2540 | int regno = ARM_A1_REGNUM; | |
2541 | ||
2542 | while (len > 0) | |
2543 | { | |
2544 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2545 | len -= INT_REGISTER_SIZE; |
2546 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2547 | } |
2548 | } | |
2549 | } | |
34e8f22d | 2550 | else |
b508a996 RE |
2551 | { |
2552 | /* For a structure or union the behaviour is as if the value had | |
2553 | been stored to word-aligned memory and then loaded into | |
2554 | registers with 32-bit load instruction(s). */ | |
2555 | int len = TYPE_LENGTH (type); | |
2556 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2557 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2558 | |
2559 | while (len > 0) | |
2560 | { | |
2561 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2562 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2563 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2564 | len -= INT_REGISTER_SIZE; |
2565 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2566 | } |
2567 | } | |
34e8f22d RE |
2568 | } |
2569 | ||
2af48f68 PB |
2570 | |
2571 | /* Handle function return values. */ | |
2572 | ||
2573 | static enum return_value_convention | |
c055b101 CV |
2574 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2575 | struct type *valtype, struct regcache *regcache, | |
2576 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 2577 | { |
7c00367c MK |
2578 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2579 | ||
2af48f68 PB |
2580 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
2581 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2582 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2583 | { | |
7c00367c MK |
2584 | if (tdep->struct_return == pcc_struct_return |
2585 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
2586 | return RETURN_VALUE_STRUCT_CONVENTION; |
2587 | } | |
2588 | ||
2589 | if (writebuf) | |
2590 | arm_store_return_value (valtype, regcache, writebuf); | |
2591 | ||
2592 | if (readbuf) | |
2593 | arm_extract_return_value (valtype, regcache, readbuf); | |
2594 | ||
2595 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2596 | } | |
2597 | ||
2598 | ||
9df628e0 | 2599 | static int |
60ade65d | 2600 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 2601 | { |
e17a4113 UW |
2602 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2603 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2604 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9df628e0 | 2605 | CORE_ADDR jb_addr; |
7a5ea0d4 | 2606 | char buf[INT_REGISTER_SIZE]; |
9df628e0 | 2607 | |
60ade65d | 2608 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
2609 | |
2610 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2611 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2612 | return 0; |
2613 | ||
e17a4113 | 2614 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
2615 | return 1; |
2616 | } | |
2617 | ||
faa95490 DJ |
2618 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
2619 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
2620 | |
2621 | CORE_ADDR | |
52f729a7 | 2622 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2623 | { |
c5aa993b | 2624 | char *name; |
faa95490 | 2625 | int namelen; |
c906108c SS |
2626 | CORE_ADDR start_addr; |
2627 | ||
2628 | /* Find the starting address and name of the function containing the PC. */ | |
2629 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2630 | return 0; | |
2631 | ||
faa95490 DJ |
2632 | /* If PC is in a Thumb call or return stub, return the address of the |
2633 | target PC, which is in a register. The thunk functions are called | |
2634 | _call_via_xx, where x is the register name. The possible names | |
2635 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2636 | if (strncmp (name, "_call_via_", 10) == 0) |
2637 | { | |
ed9a39eb JM |
2638 | /* Use the name suffix to determine which register contains the |
2639 | target PC. */ | |
c5aa993b JM |
2640 | static char *table[15] = |
2641 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2642 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2643 | }; | |
c906108c | 2644 | int regno; |
faa95490 | 2645 | int offset = strlen (name) - 2; |
c906108c SS |
2646 | |
2647 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 2648 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 2649 | return get_frame_register_unsigned (frame, regno); |
c906108c | 2650 | } |
ed9a39eb | 2651 | |
faa95490 DJ |
2652 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
2653 | non-interworking calls to foo. We could decode the stubs | |
2654 | to find the target but it's easier to use the symbol table. */ | |
2655 | namelen = strlen (name); | |
2656 | if (name[0] == '_' && name[1] == '_' | |
2657 | && ((namelen > 2 + strlen ("_from_thumb") | |
2658 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", | |
2659 | strlen ("_from_thumb")) == 0) | |
2660 | || (namelen > 2 + strlen ("_from_arm") | |
2661 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", | |
2662 | strlen ("_from_arm")) == 0))) | |
2663 | { | |
2664 | char *target_name; | |
2665 | int target_len = namelen - 2; | |
2666 | struct minimal_symbol *minsym; | |
2667 | struct objfile *objfile; | |
2668 | struct obj_section *sec; | |
2669 | ||
2670 | if (name[namelen - 1] == 'b') | |
2671 | target_len -= strlen ("_from_thumb"); | |
2672 | else | |
2673 | target_len -= strlen ("_from_arm"); | |
2674 | ||
2675 | target_name = alloca (target_len + 1); | |
2676 | memcpy (target_name, name + 2, target_len); | |
2677 | target_name[target_len] = '\0'; | |
2678 | ||
2679 | sec = find_pc_section (pc); | |
2680 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
2681 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
2682 | if (minsym != NULL) | |
2683 | return SYMBOL_VALUE_ADDRESS (minsym); | |
2684 | else | |
2685 | return 0; | |
2686 | } | |
2687 | ||
c5aa993b | 2688 | return 0; /* not a stub */ |
c906108c SS |
2689 | } |
2690 | ||
afd7eef0 RE |
2691 | static void |
2692 | set_arm_command (char *args, int from_tty) | |
2693 | { | |
edefbb7c AC |
2694 | printf_unfiltered (_("\ |
2695 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2696 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2697 | } | |
2698 | ||
2699 | static void | |
2700 | show_arm_command (char *args, int from_tty) | |
2701 | { | |
26304000 | 2702 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2703 | } |
2704 | ||
28e97307 DJ |
2705 | static void |
2706 | arm_update_current_architecture (void) | |
fd50bc42 | 2707 | { |
28e97307 | 2708 | struct gdbarch_info info; |
fd50bc42 | 2709 | |
28e97307 | 2710 | /* If the current architecture is not ARM, we have nothing to do. */ |
1cf3db46 | 2711 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm) |
28e97307 | 2712 | return; |
fd50bc42 | 2713 | |
28e97307 DJ |
2714 | /* Update the architecture. */ |
2715 | gdbarch_info_init (&info); | |
fd50bc42 | 2716 | |
28e97307 DJ |
2717 | if (!gdbarch_update_p (info)) |
2718 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2719 | } |
2720 | ||
2721 | static void | |
2722 | set_fp_model_sfunc (char *args, int from_tty, | |
2723 | struct cmd_list_element *c) | |
2724 | { | |
2725 | enum arm_float_model fp_model; | |
2726 | ||
2727 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2728 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2729 | { | |
2730 | arm_fp_model = fp_model; | |
2731 | break; | |
2732 | } | |
2733 | ||
2734 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2735 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2736 | current_fp_model); |
2737 | ||
28e97307 | 2738 | arm_update_current_architecture (); |
fd50bc42 RE |
2739 | } |
2740 | ||
2741 | static void | |
08546159 AC |
2742 | show_fp_model (struct ui_file *file, int from_tty, |
2743 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 2744 | { |
1cf3db46 | 2745 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
fd50bc42 | 2746 | |
28e97307 | 2747 | if (arm_fp_model == ARM_FLOAT_AUTO |
1cf3db46 | 2748 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2749 | fprintf_filtered (file, _("\ |
2750 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2751 | fp_model_strings[tdep->fp_model]); | |
2752 | else | |
2753 | fprintf_filtered (file, _("\ | |
2754 | The current ARM floating point model is \"%s\".\n"), | |
2755 | fp_model_strings[arm_fp_model]); | |
2756 | } | |
2757 | ||
2758 | static void | |
2759 | arm_set_abi (char *args, int from_tty, | |
2760 | struct cmd_list_element *c) | |
2761 | { | |
2762 | enum arm_abi_kind arm_abi; | |
2763 | ||
2764 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2765 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2766 | { | |
2767 | arm_abi_global = arm_abi; | |
2768 | break; | |
2769 | } | |
2770 | ||
2771 | if (arm_abi == ARM_ABI_LAST) | |
2772 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2773 | arm_abi_string); | |
2774 | ||
2775 | arm_update_current_architecture (); | |
2776 | } | |
2777 | ||
2778 | static void | |
2779 | arm_show_abi (struct ui_file *file, int from_tty, | |
2780 | struct cmd_list_element *c, const char *value) | |
2781 | { | |
1cf3db46 | 2782 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
28e97307 DJ |
2783 | |
2784 | if (arm_abi_global == ARM_ABI_AUTO | |
1cf3db46 | 2785 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2786 | fprintf_filtered (file, _("\ |
2787 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2788 | arm_abi_strings[tdep->arm_abi]); | |
2789 | else | |
2790 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2791 | arm_abi_string); | |
fd50bc42 RE |
2792 | } |
2793 | ||
0428b8f5 DJ |
2794 | static void |
2795 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
2796 | struct cmd_list_element *c, const char *value) | |
2797 | { | |
1cf3db46 | 2798 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
2799 | |
2800 | fprintf_filtered (file, _("\ | |
2801 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), | |
2802 | arm_fallback_mode_string); | |
2803 | } | |
2804 | ||
2805 | static void | |
2806 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
2807 | struct cmd_list_element *c, const char *value) | |
2808 | { | |
1cf3db46 | 2809 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
0428b8f5 DJ |
2810 | |
2811 | fprintf_filtered (file, _("\ | |
2812 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), | |
2813 | arm_force_mode_string); | |
2814 | } | |
2815 | ||
afd7eef0 RE |
2816 | /* If the user changes the register disassembly style used for info |
2817 | register and other commands, we have to also switch the style used | |
2818 | in opcodes for disassembly output. This function is run in the "set | |
2819 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2820 | |
2821 | static void | |
afd7eef0 | 2822 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2823 | struct cmd_list_element *c) |
2824 | { | |
afd7eef0 | 2825 | set_disassembly_style (); |
bc90b915 FN |
2826 | } |
2827 | \f | |
966fbf70 | 2828 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2829 | static const char * |
d93859e2 | 2830 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 2831 | { |
ff6f572f DJ |
2832 | if (i >= ARRAY_SIZE (arm_register_names)) |
2833 | /* These registers are only supported on targets which supply | |
2834 | an XML description. */ | |
2835 | return ""; | |
2836 | ||
966fbf70 RE |
2837 | return arm_register_names[i]; |
2838 | } | |
2839 | ||
bc90b915 | 2840 | static void |
afd7eef0 | 2841 | set_disassembly_style (void) |
bc90b915 | 2842 | { |
123dc839 | 2843 | int current; |
bc90b915 | 2844 | |
123dc839 DJ |
2845 | /* Find the style that the user wants. */ |
2846 | for (current = 0; current < num_disassembly_options; current++) | |
2847 | if (disassembly_style == valid_disassembly_styles[current]) | |
2848 | break; | |
2849 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 2850 | |
94c30b78 | 2851 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2852 | set_arm_regname_option (current); |
2853 | } | |
2854 | ||
082fc60d RE |
2855 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2856 | function. */ | |
2857 | ||
2858 | static int | |
2859 | coff_sym_is_thumb (int val) | |
2860 | { | |
2861 | return (val == C_THUMBEXT || | |
2862 | val == C_THUMBSTAT || | |
2863 | val == C_THUMBEXTFUNC || | |
2864 | val == C_THUMBSTATFUNC || | |
2865 | val == C_THUMBLABEL); | |
2866 | } | |
2867 | ||
2868 | /* arm_coff_make_msymbol_special() | |
2869 | arm_elf_make_msymbol_special() | |
2870 | ||
2871 | These functions test whether the COFF or ELF symbol corresponds to | |
2872 | an address in thumb code, and set a "special" bit in a minimal | |
2873 | symbol to indicate that it does. */ | |
2874 | ||
34e8f22d | 2875 | static void |
082fc60d RE |
2876 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2877 | { | |
2878 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2879 | STT_ARM_TFUNC). */ | |
2880 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2881 | == STT_LOPROC) | |
2882 | MSYMBOL_SET_SPECIAL (msym); | |
2883 | } | |
2884 | ||
34e8f22d | 2885 | static void |
082fc60d RE |
2886 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2887 | { | |
2888 | if (coff_sym_is_thumb (val)) | |
2889 | MSYMBOL_SET_SPECIAL (msym); | |
2890 | } | |
2891 | ||
60c5725c DJ |
2892 | static void |
2893 | arm_objfile_data_cleanup (struct objfile *objfile, void *arg) | |
2894 | { | |
2895 | struct arm_per_objfile *data = arg; | |
2896 | unsigned int i; | |
2897 | ||
2898 | for (i = 0; i < objfile->obfd->section_count; i++) | |
2899 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); | |
2900 | } | |
2901 | ||
2902 | static void | |
2903 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
2904 | asymbol *sym) | |
2905 | { | |
2906 | const char *name = bfd_asymbol_name (sym); | |
2907 | struct arm_per_objfile *data; | |
2908 | VEC(arm_mapping_symbol_s) **map_p; | |
2909 | struct arm_mapping_symbol new_map_sym; | |
2910 | ||
2911 | gdb_assert (name[0] == '$'); | |
2912 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
2913 | return; | |
2914 | ||
2915 | data = objfile_data (objfile, arm_objfile_data_key); | |
2916 | if (data == NULL) | |
2917 | { | |
2918 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, | |
2919 | struct arm_per_objfile); | |
2920 | set_objfile_data (objfile, arm_objfile_data_key, data); | |
2921 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
2922 | objfile->obfd->section_count, | |
2923 | VEC(arm_mapping_symbol_s) *); | |
2924 | } | |
2925 | map_p = &data->section_maps[bfd_get_section (sym)->index]; | |
2926 | ||
2927 | new_map_sym.value = sym->value; | |
2928 | new_map_sym.type = name[1]; | |
2929 | ||
2930 | /* Assume that most mapping symbols appear in order of increasing | |
2931 | value. If they were randomly distributed, it would be faster to | |
2932 | always push here and then sort at first use. */ | |
2933 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) | |
2934 | { | |
2935 | struct arm_mapping_symbol *prev_map_sym; | |
2936 | ||
2937 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); | |
2938 | if (prev_map_sym->value >= sym->value) | |
2939 | { | |
2940 | unsigned int idx; | |
2941 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, | |
2942 | arm_compare_mapping_symbols); | |
2943 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); | |
2944 | return; | |
2945 | } | |
2946 | } | |
2947 | ||
2948 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); | |
2949 | } | |
2950 | ||
756fe439 | 2951 | static void |
61a1198a | 2952 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 2953 | { |
61a1198a | 2954 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
2955 | |
2956 | /* If necessary, set the T bit. */ | |
2957 | if (arm_apcs_32) | |
2958 | { | |
61a1198a UW |
2959 | ULONGEST val; |
2960 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); | |
756fe439 | 2961 | if (arm_pc_is_thumb (pc)) |
b39cc962 | 2962 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
756fe439 | 2963 | else |
61a1198a | 2964 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
b39cc962 | 2965 | val & ~(ULONGEST) CPSR_T); |
756fe439 DJ |
2966 | } |
2967 | } | |
123dc839 DJ |
2968 | |
2969 | static struct value * | |
2970 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
2971 | { | |
2972 | const int *reg_p = baton; | |
2973 | return value_of_register (*reg_p, frame); | |
2974 | } | |
97e03143 | 2975 | \f |
70f80edf JT |
2976 | static enum gdb_osabi |
2977 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2978 | { |
2af48f68 | 2979 | unsigned int elfosabi; |
70f80edf | 2980 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2981 | |
70f80edf | 2982 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2983 | |
28e97307 DJ |
2984 | if (elfosabi == ELFOSABI_ARM) |
2985 | /* GNU tools use this value. Check note sections in this case, | |
2986 | as well. */ | |
2987 | bfd_map_over_sections (abfd, | |
2988 | generic_elf_osabi_sniff_abi_tag_sections, | |
2989 | &osabi); | |
97e03143 | 2990 | |
28e97307 | 2991 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2992 | return osabi; |
97e03143 RE |
2993 | } |
2994 | ||
70f80edf | 2995 | \f |
da3c6d4a MS |
2996 | /* Initialize the current architecture based on INFO. If possible, |
2997 | re-use an architecture from ARCHES, which is a list of | |
2998 | architectures already created during this debugging session. | |
97e03143 | 2999 | |
da3c6d4a MS |
3000 | Called e.g. at program startup, when reading a core file, and when |
3001 | reading a binary file. */ | |
97e03143 | 3002 | |
39bbf761 RE |
3003 | static struct gdbarch * |
3004 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3005 | { | |
97e03143 | 3006 | struct gdbarch_tdep *tdep; |
39bbf761 | 3007 | struct gdbarch *gdbarch; |
28e97307 DJ |
3008 | struct gdbarch_list *best_arch; |
3009 | enum arm_abi_kind arm_abi = arm_abi_global; | |
3010 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
3011 | struct tdesc_arch_data *tdesc_data = NULL; |
3012 | int i; | |
ff6f572f | 3013 | int have_fpa_registers = 1; |
123dc839 DJ |
3014 | |
3015 | /* Check any target description for validity. */ | |
3016 | if (tdesc_has_registers (info.target_desc)) | |
3017 | { | |
3018 | /* For most registers we require GDB's default names; but also allow | |
3019 | the numeric names for sp / lr / pc, as a convenience. */ | |
3020 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
3021 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
3022 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
3023 | ||
3024 | const struct tdesc_feature *feature; | |
3025 | int i, valid_p; | |
3026 | ||
3027 | feature = tdesc_find_feature (info.target_desc, | |
3028 | "org.gnu.gdb.arm.core"); | |
3029 | if (feature == NULL) | |
3030 | return NULL; | |
3031 | ||
3032 | tdesc_data = tdesc_data_alloc (); | |
3033 | ||
3034 | valid_p = 1; | |
3035 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
3036 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
3037 | arm_register_names[i]); | |
3038 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3039 | ARM_SP_REGNUM, | |
3040 | arm_sp_names); | |
3041 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3042 | ARM_LR_REGNUM, | |
3043 | arm_lr_names); | |
3044 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3045 | ARM_PC_REGNUM, | |
3046 | arm_pc_names); | |
3047 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3048 | ARM_PS_REGNUM, "cpsr"); | |
3049 | ||
3050 | if (!valid_p) | |
3051 | { | |
3052 | tdesc_data_cleanup (tdesc_data); | |
3053 | return NULL; | |
3054 | } | |
3055 | ||
3056 | feature = tdesc_find_feature (info.target_desc, | |
3057 | "org.gnu.gdb.arm.fpa"); | |
3058 | if (feature != NULL) | |
3059 | { | |
3060 | valid_p = 1; | |
3061 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
3062 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
3063 | arm_register_names[i]); | |
3064 | if (!valid_p) | |
3065 | { | |
3066 | tdesc_data_cleanup (tdesc_data); | |
3067 | return NULL; | |
3068 | } | |
3069 | } | |
ff6f572f DJ |
3070 | else |
3071 | have_fpa_registers = 0; | |
3072 | ||
3073 | feature = tdesc_find_feature (info.target_desc, | |
3074 | "org.gnu.gdb.xscale.iwmmxt"); | |
3075 | if (feature != NULL) | |
3076 | { | |
3077 | static const char *const iwmmxt_names[] = { | |
3078 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
3079 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
3080 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
3081 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
3082 | }; | |
3083 | ||
3084 | valid_p = 1; | |
3085 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
3086 | valid_p | |
3087 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
3088 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3089 | ||
3090 | /* Check for the control registers, but do not fail if they | |
3091 | are missing. */ | |
3092 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
3093 | tdesc_numbered_register (feature, tdesc_data, i, | |
3094 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3095 | ||
3096 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
3097 | valid_p | |
3098 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
3099 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
3100 | ||
3101 | if (!valid_p) | |
3102 | { | |
3103 | tdesc_data_cleanup (tdesc_data); | |
3104 | return NULL; | |
3105 | } | |
3106 | } | |
123dc839 | 3107 | } |
39bbf761 | 3108 | |
28e97307 DJ |
3109 | /* If we have an object to base this architecture on, try to determine |
3110 | its ABI. */ | |
39bbf761 | 3111 | |
28e97307 | 3112 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 3113 | { |
6b26d61a | 3114 | int ei_osabi, e_flags; |
28e97307 | 3115 | |
4be87837 | 3116 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 3117 | { |
4be87837 DJ |
3118 | case bfd_target_aout_flavour: |
3119 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 3120 | arm_abi = ARM_ABI_APCS; |
4be87837 | 3121 | break; |
97e03143 | 3122 | |
4be87837 DJ |
3123 | case bfd_target_coff_flavour: |
3124 | /* Assume it's an old APCS-style ABI. */ | |
3125 | /* XXX WinCE? */ | |
28e97307 DJ |
3126 | arm_abi = ARM_ABI_APCS; |
3127 | break; | |
3128 | ||
3129 | case bfd_target_elf_flavour: | |
3130 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
3131 | e_flags = elf_elfheader (info.abfd)->e_flags; |
3132 | ||
28e97307 DJ |
3133 | if (ei_osabi == ELFOSABI_ARM) |
3134 | { | |
3135 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
3136 | objects. There's nowhere to tag an EABI version |
3137 | anyway, so assume APCS. */ | |
28e97307 DJ |
3138 | arm_abi = ARM_ABI_APCS; |
3139 | } | |
3140 | else if (ei_osabi == ELFOSABI_NONE) | |
3141 | { | |
6b26d61a | 3142 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
3143 | |
3144 | switch (eabi_ver) | |
3145 | { | |
3146 | case EF_ARM_EABI_UNKNOWN: | |
3147 | /* Assume GNU tools. */ | |
3148 | arm_abi = ARM_ABI_APCS; | |
3149 | break; | |
3150 | ||
3151 | case EF_ARM_EABI_VER4: | |
625b5003 | 3152 | case EF_ARM_EABI_VER5: |
28e97307 | 3153 | arm_abi = ARM_ABI_AAPCS; |
2af48f68 PB |
3154 | /* EABI binaries default to VFP float ordering. */ |
3155 | if (fp_model == ARM_FLOAT_AUTO) | |
3156 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
3157 | break; |
3158 | ||
3159 | default: | |
6b26d61a | 3160 | /* Leave it as "auto". */ |
28e97307 | 3161 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
3162 | break; |
3163 | } | |
3164 | } | |
3165 | ||
3166 | if (fp_model == ARM_FLOAT_AUTO) | |
3167 | { | |
3168 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
3169 | ||
3170 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
3171 | { | |
3172 | case 0: | |
3173 | /* Leave it as "auto". Strictly speaking this case | |
3174 | means FPA, but almost nobody uses that now, and | |
3175 | many toolchains fail to set the appropriate bits | |
3176 | for the floating-point model they use. */ | |
3177 | break; | |
3178 | case EF_ARM_SOFT_FLOAT: | |
3179 | fp_model = ARM_FLOAT_SOFT_FPA; | |
3180 | break; | |
3181 | case EF_ARM_VFP_FLOAT: | |
3182 | fp_model = ARM_FLOAT_VFP; | |
3183 | break; | |
3184 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
3185 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
3186 | break; |
3187 | } | |
3188 | } | |
9d4fde75 SS |
3189 | |
3190 | if (e_flags & EF_ARM_BE8) | |
3191 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
3192 | ||
4be87837 | 3193 | break; |
97e03143 | 3194 | |
4be87837 | 3195 | default: |
28e97307 | 3196 | /* Leave it as "auto". */ |
50ceaba5 | 3197 | break; |
97e03143 RE |
3198 | } |
3199 | } | |
3200 | ||
28e97307 DJ |
3201 | /* If there is already a candidate, use it. */ |
3202 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3203 | best_arch != NULL; | |
3204 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3205 | { | |
b8926edc DJ |
3206 | if (arm_abi != ARM_ABI_AUTO |
3207 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
3208 | continue; |
3209 | ||
b8926edc DJ |
3210 | if (fp_model != ARM_FLOAT_AUTO |
3211 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
3212 | continue; |
3213 | ||
3214 | /* Found a match. */ | |
3215 | break; | |
3216 | } | |
97e03143 | 3217 | |
28e97307 | 3218 | if (best_arch != NULL) |
123dc839 DJ |
3219 | { |
3220 | if (tdesc_data != NULL) | |
3221 | tdesc_data_cleanup (tdesc_data); | |
3222 | return best_arch->gdbarch; | |
3223 | } | |
28e97307 DJ |
3224 | |
3225 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
3226 | gdbarch = gdbarch_alloc (&info, tdep); |
3227 | ||
28e97307 DJ |
3228 | /* Record additional information about the architecture we are defining. |
3229 | These are gdbarch discriminators, like the OSABI. */ | |
3230 | tdep->arm_abi = arm_abi; | |
3231 | tdep->fp_model = fp_model; | |
ff6f572f | 3232 | tdep->have_fpa_registers = have_fpa_registers; |
08216dd7 RE |
3233 | |
3234 | /* Breakpoints. */ | |
9d4fde75 | 3235 | switch (info.byte_order_for_code) |
67255d04 RE |
3236 | { |
3237 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
3238 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
3239 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
3240 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
3241 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
3242 | ||
67255d04 RE |
3243 | break; |
3244 | ||
3245 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
3246 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
3247 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
3248 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
3249 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
3250 | ||
67255d04 RE |
3251 | break; |
3252 | ||
3253 | default: | |
3254 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 3255 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
3256 | } |
3257 | ||
d7b486e7 RE |
3258 | /* On ARM targets char defaults to unsigned. */ |
3259 | set_gdbarch_char_signed (gdbarch, 0); | |
3260 | ||
9df628e0 | 3261 | /* This should be low enough for everything. */ |
97e03143 | 3262 | tdep->lowest_pc = 0x20; |
94c30b78 | 3263 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 3264 | |
7c00367c MK |
3265 | /* The default, for both APCS and AAPCS, is to return small |
3266 | structures in registers. */ | |
3267 | tdep->struct_return = reg_struct_return; | |
3268 | ||
2dd604e7 | 3269 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 3270 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 3271 | |
756fe439 DJ |
3272 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
3273 | ||
148754e5 | 3274 | /* Frame handling. */ |
a262aec2 | 3275 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
3276 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
3277 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
3278 | ||
eb5492fa | 3279 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 3280 | |
34e8f22d RE |
3281 | /* Address manipulation. */ |
3282 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
3283 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
3284 | ||
34e8f22d RE |
3285 | /* Advance PC across function entry code. */ |
3286 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
3287 | ||
190dce09 UW |
3288 | /* Skip trampolines. */ |
3289 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
3290 | ||
34e8f22d RE |
3291 | /* The stack grows downward. */ |
3292 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3293 | ||
3294 | /* Breakpoint manipulation. */ | |
3295 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
3296 | |
3297 | /* Information about registers, etc. */ | |
0ba6dca9 | 3298 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
3299 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
3300 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 3301 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 3302 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 3303 | |
ff6f572f DJ |
3304 | /* This "info float" is FPA-specific. Use the generic version if we |
3305 | do not have FPA. */ | |
3306 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
3307 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
3308 | ||
26216b98 | 3309 | /* Internal <-> external register number maps. */ |
ff6f572f | 3310 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
3311 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
3312 | ||
34e8f22d RE |
3313 | set_gdbarch_register_name (gdbarch, arm_register_name); |
3314 | ||
3315 | /* Returning results. */ | |
2af48f68 | 3316 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 3317 | |
03d48a7d RE |
3318 | /* Disassembly. */ |
3319 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
3320 | ||
34e8f22d RE |
3321 | /* Minsymbol frobbing. */ |
3322 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
3323 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
3324 | arm_coff_make_msymbol_special); | |
60c5725c | 3325 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 3326 | |
0d5de010 DJ |
3327 | /* Virtual tables. */ |
3328 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3329 | ||
97e03143 | 3330 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 3331 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 3332 | |
b39cc962 DJ |
3333 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
3334 | ||
eb5492fa | 3335 | /* Add some default predicates. */ |
a262aec2 DJ |
3336 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
3337 | dwarf2_append_unwinders (gdbarch); | |
3338 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); | |
eb5492fa | 3339 | |
97e03143 RE |
3340 | /* Now we have tuned the configuration, set a few final things, |
3341 | based on what the OS ABI has told us. */ | |
3342 | ||
b8926edc DJ |
3343 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
3344 | binaries are always marked. */ | |
3345 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
3346 | tdep->arm_abi = ARM_ABI_APCS; | |
3347 | ||
3348 | /* We used to default to FPA for generic ARM, but almost nobody | |
3349 | uses that now, and we now provide a way for the user to force | |
3350 | the model. So default to the most useful variant. */ | |
3351 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
3352 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
3353 | ||
9df628e0 RE |
3354 | if (tdep->jb_pc >= 0) |
3355 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3356 | ||
08216dd7 | 3357 | /* Floating point sizes and format. */ |
8da61cc4 | 3358 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 3359 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 3360 | { |
8da61cc4 DJ |
3361 | set_gdbarch_double_format |
3362 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3363 | set_gdbarch_long_double_format | |
3364 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3365 | } | |
3366 | else | |
3367 | { | |
3368 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
3369 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
3370 | } |
3371 | ||
123dc839 | 3372 | if (tdesc_data) |
7cc46491 | 3373 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
123dc839 DJ |
3374 | |
3375 | /* Add standard register aliases. We add aliases even for those | |
3376 | nanes which are used by the current architecture - it's simpler, | |
3377 | and does no harm, since nothing ever lists user registers. */ | |
3378 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
3379 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
3380 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
3381 | ||
39bbf761 RE |
3382 | return gdbarch; |
3383 | } | |
3384 | ||
97e03143 | 3385 | static void |
2af46ca0 | 3386 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 3387 | { |
2af46ca0 | 3388 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
3389 | |
3390 | if (tdep == NULL) | |
3391 | return; | |
3392 | ||
edefbb7c | 3393 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
3394 | (unsigned long) tdep->lowest_pc); |
3395 | } | |
3396 | ||
a78f21af AC |
3397 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
3398 | ||
c906108c | 3399 | void |
ed9a39eb | 3400 | _initialize_arm_tdep (void) |
c906108c | 3401 | { |
bc90b915 FN |
3402 | struct ui_file *stb; |
3403 | long length; | |
26304000 | 3404 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
3405 | const char *setname; |
3406 | const char *setdesc; | |
4bd7b427 | 3407 | const char *const *regnames; |
bc90b915 FN |
3408 | int numregs, i, j; |
3409 | static char *helptext; | |
edefbb7c AC |
3410 | char regdesc[1024], *rdptr = regdesc; |
3411 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 3412 | |
42cf1509 | 3413 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 3414 | |
60c5725c DJ |
3415 | arm_objfile_data_key |
3416 | = register_objfile_data_with_cleanup (arm_objfile_data_cleanup); | |
3417 | ||
70f80edf JT |
3418 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3419 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3420 | bfd_target_elf_flavour, | |
3421 | arm_elf_osabi_sniffer); | |
3422 | ||
94c30b78 | 3423 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3424 | num_disassembly_options = get_arm_regname_num_options (); |
3425 | ||
3426 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3427 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 3428 | _("Various ARM-specific commands."), |
afd7eef0 RE |
3429 | &setarmcmdlist, "set arm ", 0, &setlist); |
3430 | ||
3431 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 3432 | _("Various ARM-specific commands."), |
afd7eef0 | 3433 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 3434 | |
94c30b78 | 3435 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3436 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3437 | |
eefe576e AC |
3438 | /* Initialize the array that will be passed to |
3439 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
3440 | valid_disassembly_styles |
3441 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3442 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3443 | { |
3444 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3445 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
3446 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
3447 | rdptr += length; | |
3448 | rest -= length; | |
123dc839 DJ |
3449 | /* When we find the default names, tell the disassembler to use |
3450 | them. */ | |
bc90b915 FN |
3451 | if (!strcmp (setname, "std")) |
3452 | { | |
afd7eef0 | 3453 | disassembly_style = setname; |
bc90b915 FN |
3454 | set_arm_regname_option (i); |
3455 | } | |
3456 | } | |
94c30b78 | 3457 | /* Mark the end of valid options. */ |
afd7eef0 | 3458 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3459 | |
edefbb7c AC |
3460 | /* Create the help text. */ |
3461 | stb = mem_fileopen (); | |
3462 | fprintf_unfiltered (stb, "%s%s%s", | |
3463 | _("The valid values are:\n"), | |
3464 | regdesc, | |
3465 | _("The default is \"std\".")); | |
bc90b915 FN |
3466 | helptext = ui_file_xstrdup (stb, &length); |
3467 | ui_file_delete (stb); | |
ed9a39eb | 3468 | |
edefbb7c AC |
3469 | add_setshow_enum_cmd("disassembler", no_class, |
3470 | valid_disassembly_styles, &disassembly_style, | |
3471 | _("Set the disassembly style."), | |
3472 | _("Show the disassembly style."), | |
3473 | helptext, | |
2c5b56ce | 3474 | set_disassembly_style_sfunc, |
7915a72c | 3475 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 3476 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
3477 | |
3478 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3479 | _("Set usage of ARM 32-bit mode."), | |
3480 | _("Show usage of ARM 32-bit mode."), | |
3481 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 3482 | NULL, |
7915a72c | 3483 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 3484 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 3485 | |
fd50bc42 | 3486 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
3487 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
3488 | _("Set the floating point type."), | |
3489 | _("Show the floating point type."), | |
3490 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
3491 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
3492 | fpa - FPA co-processor (GCC compiled).\n\ | |
3493 | softvfp - Software FP with pure-endian doubles.\n\ | |
3494 | vfp - VFP co-processor."), | |
edefbb7c | 3495 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 3496 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 3497 | |
28e97307 DJ |
3498 | /* Add a command to allow the user to force the ABI. */ |
3499 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
3500 | _("Set the ABI."), | |
3501 | _("Show the ABI."), | |
3502 | NULL, arm_set_abi, arm_show_abi, | |
3503 | &setarmcmdlist, &showarmcmdlist); | |
3504 | ||
0428b8f5 DJ |
3505 | /* Add two commands to allow the user to force the assumed |
3506 | execution mode. */ | |
3507 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
3508 | arm_mode_strings, &arm_fallback_mode_string, | |
3509 | _("Set the mode assumed when symbols are unavailable."), | |
3510 | _("Show the mode assumed when symbols are unavailable."), | |
3511 | NULL, NULL, arm_show_fallback_mode, | |
3512 | &setarmcmdlist, &showarmcmdlist); | |
3513 | add_setshow_enum_cmd ("force-mode", class_support, | |
3514 | arm_mode_strings, &arm_force_mode_string, | |
3515 | _("Set the mode assumed even when symbols are available."), | |
3516 | _("Show the mode assumed even when symbols are available."), | |
3517 | NULL, NULL, arm_show_force_mode, | |
3518 | &setarmcmdlist, &showarmcmdlist); | |
3519 | ||
6529d2dd | 3520 | /* Debugging flag. */ |
edefbb7c AC |
3521 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3522 | _("Set ARM debugging."), | |
3523 | _("Show ARM debugging."), | |
3524 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 3525 | NULL, |
7915a72c | 3526 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 3527 | &setdebuglist, &showdebuglist); |
c906108c | 3528 | } |