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34e8f22d | 1 | /* Common target dependent code for GDB on ARM systems. |
32d0add0 | 2 | Copyright (C) 2002-2015 Free Software Foundation, Inc. |
34e8f22d RE |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
34e8f22d RE |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
34e8f22d | 18 | |
47ccd048 MK |
19 | #ifndef ARM_TDEP_H |
20 | #define ARM_TDEP_H | |
21 | ||
cb587d83 | 22 | /* Forward declarations. */ |
47ccd048 | 23 | struct gdbarch; |
cb587d83 | 24 | struct regset; |
3352110b | 25 | struct address_space; |
cb587d83 | 26 | |
ec741292 | 27 | #include "arch/arm.h" |
34e8f22d | 28 | |
34e8f22d | 29 | /* Size of integer registers. */ |
7a5ea0d4 | 30 | #define INT_REGISTER_SIZE 4 |
34e8f22d RE |
31 | |
32 | /* Say how long FP registers are. Used for documentation purposes and | |
33 | code readability in this header. IEEE extended doubles are 80 | |
34 | bits. DWORD aligned they use 96 bits. */ | |
7a5ea0d4 | 35 | #define FP_REGISTER_SIZE 12 |
34e8f22d | 36 | |
3184d3f9 JL |
37 | /* Say how long VFP double precision registers are. Used for documentation |
38 | purposes and code readability. These are fixed at 64 bits. */ | |
39 | #define VFP_REGISTER_SIZE 8 | |
40 | ||
34e8f22d | 41 | /* Number of machine registers. The only define actually required |
f57d151a | 42 | is gdbarch_num_regs. The other definitions are used for documentation |
34e8f22d RE |
43 | purposes and code readability. */ |
44 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) | |
45 | (and called PS for processor status) so the status bits can be cleared | |
46 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed | |
47 | in PS. */ | |
48 | #define NUM_FREGS 8 /* Number of floating point registers. */ | |
49 | #define NUM_SREGS 2 /* Number of status registers. */ | |
50 | #define NUM_GREGS 16 /* Number of general purpose registers. */ | |
51 | ||
52 | ||
53 | /* Instruction condition field values. */ | |
54 | #define INST_EQ 0x0 | |
55 | #define INST_NE 0x1 | |
56 | #define INST_CS 0x2 | |
57 | #define INST_CC 0x3 | |
58 | #define INST_MI 0x4 | |
59 | #define INST_PL 0x5 | |
60 | #define INST_VS 0x6 | |
61 | #define INST_VC 0x7 | |
62 | #define INST_HI 0x8 | |
63 | #define INST_LS 0x9 | |
64 | #define INST_GE 0xa | |
65 | #define INST_LT 0xb | |
66 | #define INST_GT 0xc | |
67 | #define INST_LE 0xd | |
68 | #define INST_AL 0xe | |
69 | #define INST_NV 0xf | |
70 | ||
71 | #define FLAG_N 0x80000000 | |
72 | #define FLAG_Z 0x40000000 | |
73 | #define FLAG_C 0x20000000 | |
74 | #define FLAG_V 0x10000000 | |
75 | ||
b39cc962 DJ |
76 | #define CPSR_T 0x20 |
77 | ||
9779414d DJ |
78 | #define XPSR_T 0x01000000 |
79 | ||
08216dd7 RE |
80 | /* Type of floating-point code in use by inferior. There are really 3 models |
81 | that are traditionally supported (plus the endianness issue), but gcc can | |
82 | only generate 2 of those. The third is APCS_FLOAT, where arguments to | |
83 | functions are passed in floating-point registers. | |
84 | ||
fd50bc42 RE |
85 | In addition to the traditional models, VFP adds two more. |
86 | ||
87 | If you update this enum, don't forget to update fp_model_strings in | |
88 | arm-tdep.c. */ | |
08216dd7 RE |
89 | |
90 | enum arm_float_model | |
91 | { | |
fd50bc42 RE |
92 | ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */ |
93 | ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */ | |
94 | ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */ | |
95 | ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */ | |
96 | ARM_FLOAT_VFP, /* Full VFP calling convention. */ | |
97 | ARM_FLOAT_LAST /* Keep at end. */ | |
08216dd7 RE |
98 | }; |
99 | ||
28e97307 DJ |
100 | /* ABI used by the inferior. */ |
101 | enum arm_abi_kind | |
102 | { | |
103 | ARM_ABI_AUTO, | |
104 | ARM_ABI_APCS, | |
105 | ARM_ABI_AAPCS, | |
106 | ARM_ABI_LAST | |
107 | }; | |
fd50bc42 | 108 | |
7c00367c MK |
109 | /* Convention for returning structures. */ |
110 | ||
111 | enum struct_return | |
112 | { | |
113 | pcc_struct_return, /* Return "short" structures in memory. */ | |
114 | reg_struct_return /* Return "short" structures in registers. */ | |
115 | }; | |
116 | ||
97e03143 RE |
117 | /* Target-dependent structure in gdbarch. */ |
118 | struct gdbarch_tdep | |
119 | { | |
28e97307 DJ |
120 | /* The ABI for this architecture. It should never be set to |
121 | ARM_ABI_AUTO. */ | |
122 | enum arm_abi_kind arm_abi; | |
123 | ||
08216dd7 RE |
124 | enum arm_float_model fp_model; /* Floating point calling conventions. */ |
125 | ||
ff6f572f | 126 | int have_fpa_registers; /* Does the target report the FPA registers? */ |
a56cc1ce | 127 | int have_wmmx_registers; /* Does the target report the WMMX registers? */ |
330c6ca9 YQ |
128 | /* The number of VFP registers reported by the target. It is zero |
129 | if VFP registers are not supported. */ | |
130 | int vfp_register_count; | |
58d6951d DJ |
131 | int have_vfp_pseudos; /* Are we synthesizing the single precision |
132 | VFP registers? */ | |
133 | int have_neon_pseudos; /* Are we synthesizing the quad precision | |
134 | NEON registers? Requires | |
135 | have_vfp_pseudos. */ | |
136 | int have_neon; /* Do we have a NEON unit? */ | |
ff6f572f | 137 | |
9779414d | 138 | int is_m; /* Does the target follow the "M" profile. */ |
97e03143 RE |
139 | CORE_ADDR lowest_pc; /* Lowest address at which instructions |
140 | will appear. */ | |
9df628e0 | 141 | |
948f8e3d | 142 | const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ |
9df628e0 | 143 | int arm_breakpoint_size; /* And its size. */ |
948f8e3d | 144 | const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ |
9df628e0 RE |
145 | int thumb_breakpoint_size; /* And its size. */ |
146 | ||
177321bd DJ |
147 | /* If the Thumb breakpoint is an undefined instruction (which is |
148 | affected by IT blocks) rather than a BKPT instruction (which is | |
149 | not), then we need a 32-bit Thumb breakpoint to preserve the | |
150 | instruction count in IT blocks. */ | |
948f8e3d | 151 | const gdb_byte *thumb2_breakpoint; |
177321bd DJ |
152 | int thumb2_breakpoint_size; |
153 | ||
0963b4bd | 154 | int jb_pc; /* Offset to PC value in jump buffer. |
9df628e0 RE |
155 | If this is negative, longjmp support |
156 | will be disabled. */ | |
157 | size_t jb_elt_size; /* And the size of each entry in the buf. */ | |
cb587d83 | 158 | |
7c00367c MK |
159 | /* Convention for returning structures. */ |
160 | enum struct_return struct_return; | |
161 | ||
27067745 UW |
162 | /* ISA-specific data types. */ |
163 | struct type *arm_ext_type; | |
58d6951d DJ |
164 | struct type *neon_double_type; |
165 | struct type *neon_quad_type; | |
25b41d01 YQ |
166 | |
167 | /* Return the expected next PC if FRAME is stopped at a syscall | |
168 | instruction. */ | |
169 | CORE_ADDR (*syscall_next_pc) (struct frame_info *frame); | |
72508ac0 | 170 | |
97dfe206 OJ |
171 | /* syscall record. */ |
172 | int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); | |
97e03143 RE |
173 | }; |
174 | ||
cca44b1b JB |
175 | /* Structures used for displaced stepping. */ |
176 | ||
177 | /* The maximum number of temporaries available for displaced instructions. */ | |
178 | #define DISPLACED_TEMPS 16 | |
179 | /* The maximum number of modified instructions generated for one single-stepped | |
180 | instruction, including the breakpoint (usually at the end of the instruction | |
181 | sequence) and any scratch words, etc. */ | |
182 | #define DISPLACED_MODIFIED_INSNS 8 | |
183 | ||
184 | struct displaced_step_closure | |
185 | { | |
186 | ULONGEST tmp[DISPLACED_TEMPS]; | |
187 | int rd; | |
188 | int wrote_to_pc; | |
189 | union | |
190 | { | |
191 | struct | |
192 | { | |
193 | int xfersize; | |
194 | int rn; /* Writeback register. */ | |
195 | unsigned int immed : 1; /* Offset is immediate. */ | |
196 | unsigned int writeback : 1; /* Perform base-register writeback. */ | |
197 | unsigned int restore_r4 : 1; /* Used r4 as scratch. */ | |
198 | } ldst; | |
199 | ||
200 | struct | |
201 | { | |
202 | unsigned long dest; | |
203 | unsigned int link : 1; | |
204 | unsigned int exchange : 1; | |
205 | unsigned int cond : 4; | |
206 | } branch; | |
207 | ||
208 | struct | |
209 | { | |
210 | unsigned int regmask; | |
211 | int rn; | |
212 | CORE_ADDR xfer_addr; | |
213 | unsigned int load : 1; | |
214 | unsigned int user : 1; | |
215 | unsigned int increment : 1; | |
216 | unsigned int before : 1; | |
217 | unsigned int writeback : 1; | |
218 | unsigned int cond : 4; | |
219 | } block; | |
220 | ||
221 | struct | |
222 | { | |
223 | unsigned int immed : 1; | |
224 | } preload; | |
225 | ||
226 | struct | |
227 | { | |
228 | /* If non-NULL, override generic SVC handling (e.g. for a particular | |
229 | OS). */ | |
bd18283a | 230 | int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, |
cca44b1b JB |
231 | struct displaced_step_closure *dsc); |
232 | } svc; | |
233 | } u; | |
4db71c0b YQ |
234 | |
235 | /* The size of original instruction, 2 or 4. */ | |
236 | unsigned int insn_size; | |
237 | /* True if the original insn (and thus all replacement insns) are Thumb | |
238 | instead of ARM. */ | |
239 | unsigned int is_thumb; | |
240 | ||
241 | /* The slots in the array is used in this way below, | |
242 | - ARM instruction occupies one slot, | |
243 | - Thumb 16 bit instruction occupies one slot, | |
244 | - Thumb 32-bit instruction occupies *two* slots, one part for each. */ | |
cca44b1b JB |
245 | unsigned long modinsn[DISPLACED_MODIFIED_INSNS]; |
246 | int numinsns; | |
247 | CORE_ADDR insn_addr; | |
248 | CORE_ADDR scratch_base; | |
249 | void (*cleanup) (struct gdbarch *, struct regcache *, | |
250 | struct displaced_step_closure *); | |
251 | }; | |
252 | ||
253 | /* Values for the WRITE_PC argument to displaced_write_reg. If the register | |
254 | write may write to the PC, specifies the way the CPSR T bit, etc. is | |
255 | modified by the instruction. */ | |
256 | ||
257 | enum pc_write_style | |
258 | { | |
259 | BRANCH_WRITE_PC, | |
260 | BX_WRITE_PC, | |
261 | LOAD_WRITE_PC, | |
262 | ALU_WRITE_PC, | |
263 | CANNOT_WRITE_PC | |
264 | }; | |
265 | ||
266 | extern void | |
b434a28f YQ |
267 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
268 | CORE_ADDR to, struct regcache *regs, | |
cca44b1b JB |
269 | struct displaced_step_closure *dsc); |
270 | extern void | |
271 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
272 | CORE_ADDR to, struct displaced_step_closure *dsc); | |
273 | extern ULONGEST | |
36073a92 YQ |
274 | displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, |
275 | int regno); | |
cca44b1b JB |
276 | extern void |
277 | displaced_write_reg (struct regcache *regs, | |
278 | struct displaced_step_closure *dsc, int regno, | |
279 | ULONGEST val, enum pc_write_style write_pc); | |
7c00367c | 280 | |
6dc13412 | 281 | CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); |
daddc3c1 | 282 | CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR); |
18819fa6 UW |
283 | void arm_insert_single_step_breakpoint (struct gdbarch *, |
284 | struct address_space *, CORE_ADDR); | |
35f73cfc | 285 | int arm_deal_with_atomic_sequence (struct frame_info *); |
0b1b3e42 | 286 | int arm_software_single_step (struct frame_info *); |
25b41d01 | 287 | int arm_frame_is_thumb (struct frame_info *frame); |
190dce09 | 288 | |
cca44b1b JB |
289 | extern struct displaced_step_closure * |
290 | arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR, | |
291 | struct regcache *); | |
292 | extern void arm_displaced_step_fixup (struct gdbarch *, | |
293 | struct displaced_step_closure *, | |
294 | CORE_ADDR, CORE_ADDR, struct regcache *); | |
295 | ||
478fd957 UW |
296 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
297 | extern int arm_psr_thumb_bit (struct gdbarch *); | |
298 | ||
e3039479 UW |
299 | /* Is the instruction at the given memory address a Thumb or ARM |
300 | instruction? */ | |
301 | extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); | |
302 | ||
72508ac0 PO |
303 | extern int arm_process_record (struct gdbarch *gdbarch, |
304 | struct regcache *regcache, CORE_ADDR addr); | |
47ccd048 MK |
305 | /* Functions exported from armbsd-tdep.h. */ |
306 | ||
307 | /* Return the appropriate register set for the core section identified | |
308 | by SECT_NAME and SECT_SIZE. */ | |
309 | ||
ed09174e AA |
310 | extern void |
311 | armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
312 | iterate_over_regset_sections_cb *cb, | |
313 | void *cb_data, | |
314 | const struct regcache *regcache); | |
47ccd048 | 315 | |
ef7e8358 UW |
316 | /* Target descriptions. */ |
317 | extern struct target_desc *tdesc_arm_with_m; | |
318 | extern struct target_desc *tdesc_arm_with_iwmmxt; | |
319 | extern struct target_desc *tdesc_arm_with_vfpv2; | |
320 | extern struct target_desc *tdesc_arm_with_vfpv3; | |
321 | extern struct target_desc *tdesc_arm_with_neon; | |
322 | ||
47ccd048 | 323 | #endif /* arm-tdep.h */ |