[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2019 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct regset;
struct address_space;
struct get_next_pcs;
struct arm_get_next_pcs;
struct gdb_get_next_pcs;

#include "gdbarch.h"
#include "arch/arm.h"
#include "infrun.h"

#include <vector>

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_wmmx_registers;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count;
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define ARM_DISPLACED_MODIFIED_INSNS	8

struct arm_displaced_step_closure : public displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  arm_displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   arm_displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      arm_displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, arm_displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       arm_displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);

ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
							int len,
							int byte_order);

CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
					     CORE_ADDR val);

int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);

std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);

extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from arm-bsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Get the correct Arm target description with given FP hardware type.  */
const target_desc *arm_read_description (arm_fp_type fp_type);

/* Get the correct Arm M-Profile target description with given hardware
   type.  */
const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
42a4f53d	2	Copyright (C) 2002-2019 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83 DJ	22	/* Forward declarations. */
cb587d83 DJ	23	struct regset;
3352110b	24	struct address_space;
d9311bfa AT	25	struct get_next_pcs;
	26	struct arm_get_next_pcs;
	27	struct gdb_get_next_pcs;
cb587d83	28
0d12e84c	29	#include "gdbarch.h"
ec741292	30	#include "arch/arm.h"
cfba9872	31	#include "infrun.h"
34e8f22d	32
a0ff9e1a SM	33	#include <vector>
a0ff9e1a SM	34
34e8f22d	35	/* Number of machine registers. The only define actually required
f57d151a	36	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	37	purposes and code readability. */
	38	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	39	(and called PS for processor status) so the status bits can be cleared
	40	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	41	in PS. */
	42	#define NUM_FREGS 8 /* Number of floating point registers. */
	43	#define NUM_SREGS 2 /* Number of status registers. */
	44	#define NUM_GREGS 16 /* Number of general purpose registers. */
	45
	46
9779414d	47
08216dd7 RE	48	/* Type of floating-point code in use by inferior. There are really 3 models
	49	that are traditionally supported (plus the endianness issue), but gcc can
	50	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	51	functions are passed in floating-point registers.
	52
fd50bc42 RE	53	In addition to the traditional models, VFP adds two more.
	54
	55	If you update this enum, don't forget to update fp_model_strings in
	56	arm-tdep.c. */
08216dd7 RE	57
	58	enum arm_float_model
	59	{
fd50bc42 RE	60	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	61	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	62	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	63	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	64	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	65	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	66	};
08216dd7 RE	67
28e97307 DJ	68	/* ABI used by the inferior. */
	69	enum arm_abi_kind
	70	{
	71	ARM_ABI_AUTO,
	72	ARM_ABI_APCS,
	73	ARM_ABI_AAPCS,
	74	ARM_ABI_LAST
	75	};
fd50bc42	76
7c00367c MK	77	/* Convention for returning structures. */
	78
	79	enum struct_return
	80	{
	81	pcc_struct_return, /* Return "short" structures in memory. */
	82	reg_struct_return /* Return "short" structures in registers. */
	83	};
	84
97e03143 RE	85	/* Target-dependent structure in gdbarch. */
	86	struct gdbarch_tdep
	87	{
28e97307 DJ	88	/* The ABI for this architecture. It should never be set to
	89	ARM_ABI_AUTO. */
	90	enum arm_abi_kind arm_abi;
	91
08216dd7 RE	92	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	93
ff6f572f	94	int have_fpa_registers; /* Does the target report the FPA registers? */
a56cc1ce	95	int have_wmmx_registers; /* Does the target report the WMMX registers? */
330c6ca9 YQ	96	/* The number of VFP registers reported by the target. It is zero
	97	if VFP registers are not supported. */
	98	int vfp_register_count;
58d6951d DJ	99	int have_vfp_pseudos; /* Are we synthesizing the single precision
	100	VFP registers? */
	101	int have_neon_pseudos; /* Are we synthesizing the quad precision
	102	NEON registers? Requires
	103	have_vfp_pseudos. */
	104	int have_neon; /* Do we have a NEON unit? */
ff6f572f	105
9779414d	106	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	107	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	108	will appear. */
9df628e0	109
948f8e3d	110	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	111	int arm_breakpoint_size; /* And its size. */
948f8e3d	112	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	113	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	114
177321bd DJ	115	/* If the Thumb breakpoint is an undefined instruction (which is
	116	affected by IT blocks) rather than a BKPT instruction (which is
	117	not), then we need a 32-bit Thumb breakpoint to preserve the
	118	instruction count in IT blocks. */
948f8e3d	119	const gdb_byte *thumb2_breakpoint;
177321bd DJ	120	int thumb2_breakpoint_size;
177321bd DJ	121
0963b4bd	122	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	123	If this is negative, longjmp support
	124	will be disabled. */
	125	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	126
7c00367c MK	127	/* Convention for returning structures. */
	128	enum struct_return struct_return;
	129
27067745 UW	130	/* ISA-specific data types. */
27067745 UW	131	struct type *arm_ext_type;
58d6951d DJ	132	struct type *neon_double_type;
58d6951d DJ	133	struct type *neon_quad_type;
25b41d01	134
97dfe206 OJ	135	/* syscall record. */
97dfe206 OJ	136	int (arm_syscall_record) (struct regcache regcache, unsigned long svc_number);
97e03143 RE	137	};
97e03143 RE	138
cca44b1b JB	139	/* Structures used for displaced stepping. */
	140
	141	/* The maximum number of temporaries available for displaced instructions. */
	142	#define DISPLACED_TEMPS 16
	143	/* The maximum number of modified instructions generated for one single-stepped
	144	instruction, including the breakpoint (usually at the end of the instruction
	145	sequence) and any scratch words, etc. */
e935475c	146	#define ARM_DISPLACED_MODIFIED_INSNS 8
cca44b1b	147
cfba9872	148	struct arm_displaced_step_closure : public displaced_step_closure
cca44b1b JB	149	{
	150	ULONGEST tmp[DISPLACED_TEMPS];
	151	int rd;
	152	int wrote_to_pc;
	153	union
	154	{
	155	struct
	156	{
	157	int xfersize;
	158	int rn; /* Writeback register. */
	159	unsigned int immed : 1; /* Offset is immediate. */
	160	unsigned int writeback : 1; /* Perform base-register writeback. */
	161	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	162	} ldst;
	163
	164	struct
	165	{
	166	unsigned long dest;
	167	unsigned int link : 1;
	168	unsigned int exchange : 1;
	169	unsigned int cond : 4;
	170	} branch;
	171
	172	struct
	173	{
	174	unsigned int regmask;
	175	int rn;
	176	CORE_ADDR xfer_addr;
	177	unsigned int load : 1;
	178	unsigned int user : 1;
	179	unsigned int increment : 1;
	180	unsigned int before : 1;
	181	unsigned int writeback : 1;
	182	unsigned int cond : 4;
	183	} block;
	184
	185	struct
	186	{
	187	unsigned int immed : 1;
	188	} preload;
	189
	190	struct
	191	{
	192	/* If non-NULL, override generic SVC handling (e.g. for a particular
	193	OS). */
bd18283a	194	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cfba9872	195	arm_displaced_step_closure *dsc);
cca44b1b JB	196	} svc;
cca44b1b JB	197	} u;
4db71c0b YQ	198
	199	/* The size of original instruction, 2 or 4. */
	200	unsigned int insn_size;
	201	/* True if the original insn (and thus all replacement insns) are Thumb
	202	instead of ARM. */
	203	unsigned int is_thumb;
	204
	205	/* The slots in the array is used in this way below,
	206	- ARM instruction occupies one slot,
	207	- Thumb 16 bit instruction occupies one slot,
	208	- Thumb 32-bit instruction occupies two slots, one part for each. */
e935475c	209	unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
cca44b1b JB	210	int numinsns;
	211	CORE_ADDR insn_addr;
	212	CORE_ADDR scratch_base;
	213	void (cleanup) (struct gdbarch , struct regcache *,
cfba9872	214	arm_displaced_step_closure *);
cca44b1b JB	215	};
	216
	217	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	218	write may write to the PC, specifies the way the CPSR T bit, etc. is
	219	modified by the instruction. */
	220
	221	enum pc_write_style
	222	{
	223	BRANCH_WRITE_PC,
	224	BX_WRITE_PC,
	225	LOAD_WRITE_PC,
	226	ALU_WRITE_PC,
	227	CANNOT_WRITE_PC
	228	};
	229
	230	extern void
b434a28f YQ	231	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	232	CORE_ADDR to, struct regcache *regs,
cfba9872	233	arm_displaced_step_closure *dsc);
cca44b1b JB	234	extern void
cca44b1b JB	235	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
cfba9872	236	CORE_ADDR to, arm_displaced_step_closure *dsc);
cca44b1b	237	extern ULONGEST
cfba9872	238	displaced_read_reg (struct regcache regs, arm_displaced_step_closure dsc,
36073a92	239	int regno);
cca44b1b JB	240	extern void
cca44b1b JB	241	displaced_write_reg (struct regcache *regs,
cfba9872	242	arm_displaced_step_closure *dsc, int regno,
cca44b1b	243	ULONGEST val, enum pc_write_style write_pc);
7c00367c	244
6dc13412	245	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
d9311bfa AT	246
	247	ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
	248	int len,
	249	int byte_order);
	250
	251	CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
	252	CORE_ADDR val);
	253
d9311bfa AT	254	int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
d9311bfa AT	255
a0ff9e1a	256	std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
d0e59a68	257	int arm_is_thumb (struct regcache *regcache);
25b41d01	258	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	259
cca44b1b JB	260	extern void arm_displaced_step_fixup (struct gdbarch *,
	261	struct displaced_step_closure *,
	262	CORE_ADDR, CORE_ADDR, struct regcache *);
	263
478fd957 UW	264	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	265	extern int arm_psr_thumb_bit (struct gdbarch *);
	266
e3039479 UW	267	/* Is the instruction at the given memory address a Thumb or ARM
	268	instruction? */
	269	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	270
72508ac0 PO	271	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	272	struct regcache *regcache, CORE_ADDR addr);
03b62bbb	273	/* Functions exported from arm-bsd-tdep.h. */
47ccd048 MK	274
	275	/* Return the appropriate register set for the core section identified
	276	by SECT_NAME and SECT_SIZE. */
	277
ed09174e AA	278	extern void
	279	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	280	iterate_over_regset_sections_cb *cb,
	281	void *cb_data,
	282	const struct regcache *regcache);
47ccd048	283
d105cce5 AH	284	/* Get the correct Arm target description with given FP hardware type. */
	285	const target_desc *arm_read_description (arm_fp_type fp_type);
	286
	287	/* Get the correct Arm M-Profile target description with given hardware
	288	type. */
	289	const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);
ef7e8358	290
47ccd048	291	#endif /* arm-tdep.h */