[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2013 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;
struct address_space;

/* Register numbers of various important registers.  */

enum gdb_regnum {
  ARM_A1_REGNUM = 0,		/* first integer-like argument */
  ARM_A4_REGNUM = 3,		/* last integer-like argument */
  ARM_AP_REGNUM = 11,
  ARM_IP_REGNUM = 12,
  ARM_SP_REGNUM = 13,		/* Contains address of top of stack */
  ARM_LR_REGNUM = 14,		/* address to return to from a function call */
  ARM_PC_REGNUM = 15,		/* Contains program counter */
  ARM_F0_REGNUM = 16,		/* first floating point register */
  ARM_F3_REGNUM = 19,		/* last floating point argument register */
  ARM_F7_REGNUM = 23, 		/* last floating point register */
  ARM_FPS_REGNUM = 24,		/* floating point status register */
  ARM_PS_REGNUM = 25,		/* Contains processor status */
  ARM_WR0_REGNUM,		/* WMMX data registers.  */
  ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  ARM_WC0_REGNUM,		/* WMMX control registers.  */
  ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  ARM_WCGR0_REGNUM,		/* WMMX general purpose registers.  */
  ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  ARM_D0_REGNUM,		/* VFP double-precision registers.  */
  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  ARM_FPSCR_REGNUM,

  ARM_NUM_REGS,

  /* Other useful registers.  */
  ARM_FP_REGNUM = 11,		/* Frame register in ARM code, if used.  */
  THUMB_FP_REGNUM = 7,		/* Frame register in Thumb code, if used.  */
  ARM_NUM_ARG_REGS = 4, 
  ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  ARM_NUM_FP_ARG_REGS = 4,
  ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
};

/* Size of integer registers.  */
#define INT_REGISTER_SIZE		4

/* Say how long FP registers are.  Used for documentation purposes and
   code readability in this header.  IEEE extended doubles are 80
   bits.  DWORD aligned they use 96 bits.  */
#define FP_REGISTER_SIZE	12

/* Say how long VFP double precision registers are.  Used for documentation
   purposes and code readability.  These are fixed at 64 bits.  */
#define VFP_REGISTER_SIZE	8

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Instruction condition field values.  */
#define INST_EQ		0x0
#define INST_NE		0x1
#define INST_CS		0x2
#define INST_CC		0x3
#define INST_MI		0x4
#define INST_PL		0x5
#define INST_VS		0x6
#define INST_VC		0x7
#define INST_HI		0x8
#define INST_LS		0x9
#define INST_GE		0xa
#define INST_LT		0xb
#define INST_GT		0xc
#define INST_LE		0xd
#define INST_AL		0xe
#define INST_NV		0xf

#define FLAG_N		0x80000000
#define FLAG_Z		0x40000000
#define FLAG_C		0x20000000
#define FLAG_V		0x10000000

#define CPSR_T		0x20

#define XPSR_T		0x01000000

/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_vfp_registers;	/* Does the target report the VFP registers?  */
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Cached core file helpers.  */
  struct regset *gregset, *fpregset, *vfpregset;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);

   /* Parse swi insn args, sycall record.  */
  int (*arm_swi_record) (struct regcache *regcache);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define DISPLACED_MODIFIED_INSNS	8

struct displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  struct displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   struct displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      struct displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       struct displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
void arm_insert_single_step_breakpoint (struct gdbarch *,
					struct address_space *, CORE_ADDR);
int arm_deal_with_atomic_sequence (struct frame_info *);
int arm_software_single_step (struct frame_info *);
int arm_frame_is_thumb (struct frame_info *frame);

extern struct displaced_step_closure *
  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
				struct regcache *);
extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from armbsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern const struct regset *
  armbsd_regset_from_core_section (struct gdbarch *gdbarch,
				   const char *sect_name, size_t sect_size);

/* Target descriptions.  */
extern struct target_desc *tdesc_arm_with_m;
extern struct target_desc *tdesc_arm_with_iwmmxt;
extern struct target_desc *tdesc_arm_with_vfpv2;
extern struct target_desc *tdesc_arm_with_vfpv3;
extern struct target_desc *tdesc_arm_with_neon;

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
28e7fd62	2	Copyright (C) 2002-2013 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83	22	/* Forward declarations. */
47ccd048	23	struct gdbarch;
cb587d83	24	struct regset;
3352110b	25	struct address_space;
cb587d83	26
7157eed4	27	/* Register numbers of various important registers. */
34e8f22d	28
47a73475 MS	29	enum gdb_regnum {
	30	ARM_A1_REGNUM = 0, /* first integer-like argument */
	31	ARM_A4_REGNUM = 3, /* last integer-like argument */
	32	ARM_AP_REGNUM = 11,
4be43953	33	ARM_IP_REGNUM = 12,
47a73475 MS	34	ARM_SP_REGNUM = 13, /* Contains address of top of stack */
	35	ARM_LR_REGNUM = 14, /* address to return to from a function call */
	36	ARM_PC_REGNUM = 15, /* Contains program counter */
	37	ARM_F0_REGNUM = 16, /* first floating point register */
	38	ARM_F3_REGNUM = 19, /* last floating point argument register */
	39	ARM_F7_REGNUM = 23, /* last floating point register */
	40	ARM_FPS_REGNUM = 24, /* floating point status register */
	41	ARM_PS_REGNUM = 25, /* Contains processor status */
ff6f572f DJ	42	ARM_WR0_REGNUM, /* WMMX data registers. */
	43	ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
	44	ARM_WC0_REGNUM, /* WMMX control registers. */
	45	ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
	46	ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
	47	ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
	48	ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
	49	ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
	50	ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
58d6951d DJ	51	ARM_D0_REGNUM, /* VFP double-precision registers. */
58d6951d DJ	52	ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
3b273a55	53	ARM_FPSCR_REGNUM,
ff6f572f DJ	54
	55	ARM_NUM_REGS,
	56
	57	/* Other useful registers. */
47a73475 MS	58	ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
	59	THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
	60	ARM_NUM_ARG_REGS = 4,
	61	ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
	62	ARM_NUM_FP_ARG_REGS = 4,
	63	ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
	64	};
34e8f22d	65
34e8f22d	66	/* Size of integer registers. */
7a5ea0d4	67	#define INT_REGISTER_SIZE 4
34e8f22d RE	68
	69	/* Say how long FP registers are. Used for documentation purposes and
	70	code readability in this header. IEEE extended doubles are 80
	71	bits. DWORD aligned they use 96 bits. */
7a5ea0d4	72	#define FP_REGISTER_SIZE 12
34e8f22d	73
3184d3f9 JL	74	/* Say how long VFP double precision registers are. Used for documentation
	75	purposes and code readability. These are fixed at 64 bits. */
	76	#define VFP_REGISTER_SIZE 8
	77
34e8f22d	78	/* Number of machine registers. The only define actually required
f57d151a	79	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	80	purposes and code readability. */
	81	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	82	(and called PS for processor status) so the status bits can be cleared
	83	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	84	in PS. */
	85	#define NUM_FREGS 8 /* Number of floating point registers. */
	86	#define NUM_SREGS 2 /* Number of status registers. */
	87	#define NUM_GREGS 16 /* Number of general purpose registers. */
	88
	89
	90	/* Instruction condition field values. */
	91	#define INST_EQ 0x0
	92	#define INST_NE 0x1
	93	#define INST_CS 0x2
	94	#define INST_CC 0x3
	95	#define INST_MI 0x4
	96	#define INST_PL 0x5
	97	#define INST_VS 0x6
	98	#define INST_VC 0x7
	99	#define INST_HI 0x8
	100	#define INST_LS 0x9
	101	#define INST_GE 0xa
	102	#define INST_LT 0xb
	103	#define INST_GT 0xc
	104	#define INST_LE 0xd
	105	#define INST_AL 0xe
	106	#define INST_NV 0xf
	107
	108	#define FLAG_N 0x80000000
	109	#define FLAG_Z 0x40000000
	110	#define FLAG_C 0x20000000
	111	#define FLAG_V 0x10000000
	112
b39cc962 DJ	113	#define CPSR_T 0x20
b39cc962 DJ	114
9779414d DJ	115	#define XPSR_T 0x01000000
9779414d DJ	116
08216dd7 RE	117	/* Type of floating-point code in use by inferior. There are really 3 models
	118	that are traditionally supported (plus the endianness issue), but gcc can
	119	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	120	functions are passed in floating-point registers.
	121
fd50bc42 RE	122	In addition to the traditional models, VFP adds two more.
	123
	124	If you update this enum, don't forget to update fp_model_strings in
	125	arm-tdep.c. */
08216dd7 RE	126
	127	enum arm_float_model
	128	{
fd50bc42 RE	129	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	130	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	131	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	132	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	133	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	134	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	135	};
08216dd7 RE	136
28e97307 DJ	137	/* ABI used by the inferior. */
	138	enum arm_abi_kind
	139	{
	140	ARM_ABI_AUTO,
	141	ARM_ABI_APCS,
	142	ARM_ABI_AAPCS,
	143	ARM_ABI_LAST
	144	};
fd50bc42	145
7c00367c MK	146	/* Convention for returning structures. */
	147
	148	enum struct_return
	149	{
	150	pcc_struct_return, /* Return "short" structures in memory. */
	151	reg_struct_return /* Return "short" structures in registers. */
	152	};
	153
97e03143 RE	154	/* Target-dependent structure in gdbarch. */
	155	struct gdbarch_tdep
	156	{
28e97307 DJ	157	/* The ABI for this architecture. It should never be set to
	158	ARM_ABI_AUTO. */
	159	enum arm_abi_kind arm_abi;
	160
08216dd7 RE	161	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	162
ff6f572f	163	int have_fpa_registers; /* Does the target report the FPA registers? */
58d6951d DJ	164	int have_vfp_registers; /* Does the target report the VFP registers? */
	165	int have_vfp_pseudos; /* Are we synthesizing the single precision
	166	VFP registers? */
	167	int have_neon_pseudos; /* Are we synthesizing the quad precision
	168	NEON registers? Requires
	169	have_vfp_pseudos. */
	170	int have_neon; /* Do we have a NEON unit? */
ff6f572f	171
9779414d	172	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	173	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	174	will appear. */
9df628e0	175
948f8e3d	176	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	177	int arm_breakpoint_size; /* And its size. */
948f8e3d	178	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	179	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	180
177321bd DJ	181	/* If the Thumb breakpoint is an undefined instruction (which is
	182	affected by IT blocks) rather than a BKPT instruction (which is
	183	not), then we need a 32-bit Thumb breakpoint to preserve the
	184	instruction count in IT blocks. */
948f8e3d	185	const gdb_byte *thumb2_breakpoint;
177321bd DJ	186	int thumb2_breakpoint_size;
177321bd DJ	187
0963b4bd	188	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	189	If this is negative, longjmp support
	190	will be disabled. */
	191	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	192
7c00367c MK	193	/* Convention for returning structures. */
	194	enum struct_return struct_return;
	195
cb587d83	196	/* Cached core file helpers. */
ef7e8358	197	struct regset gregset, fpregset, *vfpregset;
27067745 UW	198
	199	/* ISA-specific data types. */
	200	struct type *arm_ext_type;
58d6951d DJ	201	struct type *neon_double_type;
58d6951d DJ	202	struct type *neon_quad_type;
25b41d01 YQ	203
	204	/* Return the expected next PC if FRAME is stopped at a syscall
	205	instruction. */
	206	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
72508ac0 PO	207
	208	/* Parse swi insn args, sycall record. */
	209	int (arm_swi_record) (struct regcache regcache);
97e03143 RE	210	};
97e03143 RE	211
cca44b1b JB	212	/* Structures used for displaced stepping. */
	213
	214	/* The maximum number of temporaries available for displaced instructions. */
	215	#define DISPLACED_TEMPS 16
	216	/* The maximum number of modified instructions generated for one single-stepped
	217	instruction, including the breakpoint (usually at the end of the instruction
	218	sequence) and any scratch words, etc. */
	219	#define DISPLACED_MODIFIED_INSNS 8
	220
	221	struct displaced_step_closure
	222	{
	223	ULONGEST tmp[DISPLACED_TEMPS];
	224	int rd;
	225	int wrote_to_pc;
	226	union
	227	{
	228	struct
	229	{
	230	int xfersize;
	231	int rn; /* Writeback register. */
	232	unsigned int immed : 1; /* Offset is immediate. */
	233	unsigned int writeback : 1; /* Perform base-register writeback. */
	234	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	235	} ldst;
	236
	237	struct
	238	{
	239	unsigned long dest;
	240	unsigned int link : 1;
	241	unsigned int exchange : 1;
	242	unsigned int cond : 4;
	243	} branch;
	244
	245	struct
	246	{
	247	unsigned int regmask;
	248	int rn;
	249	CORE_ADDR xfer_addr;
	250	unsigned int load : 1;
	251	unsigned int user : 1;
	252	unsigned int increment : 1;
	253	unsigned int before : 1;
	254	unsigned int writeback : 1;
	255	unsigned int cond : 4;
	256	} block;
	257
	258	struct
	259	{
	260	unsigned int immed : 1;
	261	} preload;
	262
	263	struct
	264	{
	265	/* If non-NULL, override generic SVC handling (e.g. for a particular
	266	OS). */
bd18283a	267	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cca44b1b JB	268	struct displaced_step_closure *dsc);
	269	} svc;
	270	} u;
4db71c0b YQ	271
	272	/* The size of original instruction, 2 or 4. */
	273	unsigned int insn_size;
	274	/* True if the original insn (and thus all replacement insns) are Thumb
	275	instead of ARM. */
	276	unsigned int is_thumb;
	277
	278	/* The slots in the array is used in this way below,
	279	- ARM instruction occupies one slot,
	280	- Thumb 16 bit instruction occupies one slot,
	281	- Thumb 32-bit instruction occupies two slots, one part for each. */
cca44b1b JB	282	unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
	283	int numinsns;
	284	CORE_ADDR insn_addr;
	285	CORE_ADDR scratch_base;
	286	void (cleanup) (struct gdbarch , struct regcache *,
	287	struct displaced_step_closure *);
	288	};
	289
	290	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	291	write may write to the PC, specifies the way the CPSR T bit, etc. is
	292	modified by the instruction. */
	293
	294	enum pc_write_style
	295	{
	296	BRANCH_WRITE_PC,
	297	BX_WRITE_PC,
	298	LOAD_WRITE_PC,
	299	ALU_WRITE_PC,
	300	CANNOT_WRITE_PC
	301	};
	302
	303	extern void
b434a28f YQ	304	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	305	CORE_ADDR to, struct regcache *regs,
cca44b1b JB	306	struct displaced_step_closure *dsc);
	307	extern void
	308	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
	309	CORE_ADDR to, struct displaced_step_closure *dsc);
	310	extern ULONGEST
36073a92 YQ	311	displaced_read_reg (struct regcache regs, struct displaced_step_closure dsc,
36073a92 YQ	312	int regno);
cca44b1b JB	313	extern void
	314	displaced_write_reg (struct regcache *regs,
	315	struct displaced_step_closure *dsc, int regno,
	316	ULONGEST val, enum pc_write_style write_pc);
7c00367c	317
6dc13412	318	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
daddc3c1	319	CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
18819fa6 UW	320	void arm_insert_single_step_breakpoint (struct gdbarch *,
18819fa6 UW	321	struct address_space *, CORE_ADDR);
35f73cfc	322	int arm_deal_with_atomic_sequence (struct frame_info *);
0b1b3e42	323	int arm_software_single_step (struct frame_info *);
25b41d01	324	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	325
cca44b1b JB	326	extern struct displaced_step_closure *
	327	arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
	328	struct regcache *);
	329	extern void arm_displaced_step_fixup (struct gdbarch *,
	330	struct displaced_step_closure *,
	331	CORE_ADDR, CORE_ADDR, struct regcache *);
	332
478fd957 UW	333	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	334	extern int arm_psr_thumb_bit (struct gdbarch *);
	335
e3039479 UW	336	/* Is the instruction at the given memory address a Thumb or ARM
	337	instruction? */
	338	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	339
72508ac0 PO	340	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	341	struct regcache *regcache, CORE_ADDR addr);
47ccd048 MK	342	/* Functions exported from armbsd-tdep.h. */
	343
	344	/* Return the appropriate register set for the core section identified
	345	by SECT_NAME and SECT_SIZE. */
	346
	347	extern const struct regset *
	348	armbsd_regset_from_core_section (struct gdbarch *gdbarch,
	349	const char *sect_name, size_t sect_size);
	350
ef7e8358 UW	351	/* Target descriptions. */
	352	extern struct target_desc *tdesc_arm_with_m;
	353	extern struct target_desc *tdesc_arm_with_iwmmxt;
	354	extern struct target_desc *tdesc_arm_with_vfpv2;
	355	extern struct target_desc *tdesc_arm_with_vfpv3;
	356	extern struct target_desc *tdesc_arm_with_neon;
	357
47ccd048	358	#endif /* arm-tdep.h */