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34e8f22d | 1 | /* Common target dependent code for GDB on ARM systems. |
b811d2c2 | 2 | Copyright (C) 2002-2020 Free Software Foundation, Inc. |
34e8f22d RE |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
34e8f22d RE |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
34e8f22d | 18 | |
47ccd048 MK |
19 | #ifndef ARM_TDEP_H |
20 | #define ARM_TDEP_H | |
21 | ||
cb587d83 DJ |
22 | /* Forward declarations. */ |
23 | struct regset; | |
3352110b | 24 | struct address_space; |
d9311bfa AT |
25 | struct get_next_pcs; |
26 | struct arm_get_next_pcs; | |
27 | struct gdb_get_next_pcs; | |
cb587d83 | 28 | |
c7ae7675 CB |
29 | /* Set to true if the 32-bit mode is in use. */ |
30 | ||
31 | extern bool arm_apcs_32; | |
32 | ||
0d12e84c | 33 | #include "gdbarch.h" |
ec741292 | 34 | #include "arch/arm.h" |
cfba9872 | 35 | #include "infrun.h" |
34e8f22d | 36 | |
a0ff9e1a SM |
37 | #include <vector> |
38 | ||
34e8f22d | 39 | /* Number of machine registers. The only define actually required |
f57d151a | 40 | is gdbarch_num_regs. The other definitions are used for documentation |
34e8f22d RE |
41 | purposes and code readability. */ |
42 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) | |
43 | (and called PS for processor status) so the status bits can be cleared | |
44 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed | |
45 | in PS. */ | |
46 | #define NUM_FREGS 8 /* Number of floating point registers. */ | |
47 | #define NUM_SREGS 2 /* Number of status registers. */ | |
48 | #define NUM_GREGS 16 /* Number of general purpose registers. */ | |
49 | ||
50 | ||
9779414d | 51 | |
08216dd7 RE |
52 | /* Type of floating-point code in use by inferior. There are really 3 models |
53 | that are traditionally supported (plus the endianness issue), but gcc can | |
54 | only generate 2 of those. The third is APCS_FLOAT, where arguments to | |
55 | functions are passed in floating-point registers. | |
56 | ||
fd50bc42 RE |
57 | In addition to the traditional models, VFP adds two more. |
58 | ||
59 | If you update this enum, don't forget to update fp_model_strings in | |
60 | arm-tdep.c. */ | |
08216dd7 RE |
61 | |
62 | enum arm_float_model | |
63 | { | |
fd50bc42 RE |
64 | ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */ |
65 | ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */ | |
66 | ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */ | |
67 | ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */ | |
68 | ARM_FLOAT_VFP, /* Full VFP calling convention. */ | |
69 | ARM_FLOAT_LAST /* Keep at end. */ | |
08216dd7 RE |
70 | }; |
71 | ||
28e97307 DJ |
72 | /* ABI used by the inferior. */ |
73 | enum arm_abi_kind | |
74 | { | |
75 | ARM_ABI_AUTO, | |
76 | ARM_ABI_APCS, | |
77 | ARM_ABI_AAPCS, | |
78 | ARM_ABI_LAST | |
79 | }; | |
fd50bc42 | 80 | |
7c00367c MK |
81 | /* Convention for returning structures. */ |
82 | ||
83 | enum struct_return | |
84 | { | |
85 | pcc_struct_return, /* Return "short" structures in memory. */ | |
86 | reg_struct_return /* Return "short" structures in registers. */ | |
87 | }; | |
88 | ||
97e03143 RE |
89 | /* Target-dependent structure in gdbarch. */ |
90 | struct gdbarch_tdep | |
91 | { | |
28e97307 DJ |
92 | /* The ABI for this architecture. It should never be set to |
93 | ARM_ABI_AUTO. */ | |
94 | enum arm_abi_kind arm_abi; | |
95 | ||
08216dd7 RE |
96 | enum arm_float_model fp_model; /* Floating point calling conventions. */ |
97 | ||
7559c217 CB |
98 | bool have_fpa_registers; /* Does the target report the FPA registers? */ |
99 | bool have_wmmx_registers; /* Does the target report the WMMX registers? */ | |
330c6ca9 YQ |
100 | /* The number of VFP registers reported by the target. It is zero |
101 | if VFP registers are not supported. */ | |
102 | int vfp_register_count; | |
7559c217 | 103 | bool have_vfp_pseudos; /* Are we synthesizing the single precision |
58d6951d | 104 | VFP registers? */ |
7559c217 | 105 | bool have_neon_pseudos; /* Are we synthesizing the quad precision |
58d6951d DJ |
106 | NEON registers? Requires |
107 | have_vfp_pseudos. */ | |
7559c217 | 108 | bool have_neon; /* Do we have a NEON unit? */ |
ff6f572f | 109 | |
7559c217 | 110 | bool is_m; /* Does the target follow the "M" profile. */ |
97e03143 RE |
111 | CORE_ADDR lowest_pc; /* Lowest address at which instructions |
112 | will appear. */ | |
9df628e0 | 113 | |
948f8e3d | 114 | const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ |
9df628e0 | 115 | int arm_breakpoint_size; /* And its size. */ |
948f8e3d | 116 | const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ |
9df628e0 RE |
117 | int thumb_breakpoint_size; /* And its size. */ |
118 | ||
177321bd DJ |
119 | /* If the Thumb breakpoint is an undefined instruction (which is |
120 | affected by IT blocks) rather than a BKPT instruction (which is | |
121 | not), then we need a 32-bit Thumb breakpoint to preserve the | |
122 | instruction count in IT blocks. */ | |
948f8e3d | 123 | const gdb_byte *thumb2_breakpoint; |
177321bd DJ |
124 | int thumb2_breakpoint_size; |
125 | ||
0963b4bd | 126 | int jb_pc; /* Offset to PC value in jump buffer. |
9df628e0 RE |
127 | If this is negative, longjmp support |
128 | will be disabled. */ | |
129 | size_t jb_elt_size; /* And the size of each entry in the buf. */ | |
cb587d83 | 130 | |
7c00367c MK |
131 | /* Convention for returning structures. */ |
132 | enum struct_return struct_return; | |
133 | ||
27067745 UW |
134 | /* ISA-specific data types. */ |
135 | struct type *arm_ext_type; | |
58d6951d DJ |
136 | struct type *neon_double_type; |
137 | struct type *neon_quad_type; | |
25b41d01 | 138 | |
97dfe206 OJ |
139 | /* syscall record. */ |
140 | int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); | |
97e03143 RE |
141 | }; |
142 | ||
cca44b1b JB |
143 | /* Structures used for displaced stepping. */ |
144 | ||
145 | /* The maximum number of temporaries available for displaced instructions. */ | |
146 | #define DISPLACED_TEMPS 16 | |
147 | /* The maximum number of modified instructions generated for one single-stepped | |
148 | instruction, including the breakpoint (usually at the end of the instruction | |
149 | sequence) and any scratch words, etc. */ | |
e935475c | 150 | #define ARM_DISPLACED_MODIFIED_INSNS 8 |
cca44b1b | 151 | |
1152d984 SM |
152 | struct arm_displaced_step_copy_insn_closure |
153 | : public displaced_step_copy_insn_closure | |
cca44b1b JB |
154 | { |
155 | ULONGEST tmp[DISPLACED_TEMPS]; | |
156 | int rd; | |
157 | int wrote_to_pc; | |
158 | union | |
159 | { | |
160 | struct | |
161 | { | |
162 | int xfersize; | |
163 | int rn; /* Writeback register. */ | |
164 | unsigned int immed : 1; /* Offset is immediate. */ | |
165 | unsigned int writeback : 1; /* Perform base-register writeback. */ | |
166 | unsigned int restore_r4 : 1; /* Used r4 as scratch. */ | |
167 | } ldst; | |
168 | ||
169 | struct | |
170 | { | |
171 | unsigned long dest; | |
172 | unsigned int link : 1; | |
173 | unsigned int exchange : 1; | |
174 | unsigned int cond : 4; | |
175 | } branch; | |
176 | ||
177 | struct | |
178 | { | |
179 | unsigned int regmask; | |
180 | int rn; | |
181 | CORE_ADDR xfer_addr; | |
182 | unsigned int load : 1; | |
183 | unsigned int user : 1; | |
184 | unsigned int increment : 1; | |
185 | unsigned int before : 1; | |
186 | unsigned int writeback : 1; | |
187 | unsigned int cond : 4; | |
188 | } block; | |
189 | ||
190 | struct | |
191 | { | |
192 | unsigned int immed : 1; | |
193 | } preload; | |
194 | ||
195 | struct | |
196 | { | |
197 | /* If non-NULL, override generic SVC handling (e.g. for a particular | |
dda83cd7 | 198 | OS). */ |
bd18283a | 199 | int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 200 | arm_displaced_step_copy_insn_closure *dsc); |
cca44b1b JB |
201 | } svc; |
202 | } u; | |
4db71c0b YQ |
203 | |
204 | /* The size of original instruction, 2 or 4. */ | |
205 | unsigned int insn_size; | |
206 | /* True if the original insn (and thus all replacement insns) are Thumb | |
207 | instead of ARM. */ | |
208 | unsigned int is_thumb; | |
209 | ||
210 | /* The slots in the array is used in this way below, | |
211 | - ARM instruction occupies one slot, | |
212 | - Thumb 16 bit instruction occupies one slot, | |
213 | - Thumb 32-bit instruction occupies *two* slots, one part for each. */ | |
e935475c | 214 | unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS]; |
cca44b1b JB |
215 | int numinsns; |
216 | CORE_ADDR insn_addr; | |
217 | CORE_ADDR scratch_base; | |
218 | void (*cleanup) (struct gdbarch *, struct regcache *, | |
1152d984 | 219 | arm_displaced_step_copy_insn_closure *); |
cca44b1b JB |
220 | }; |
221 | ||
222 | /* Values for the WRITE_PC argument to displaced_write_reg. If the register | |
223 | write may write to the PC, specifies the way the CPSR T bit, etc. is | |
224 | modified by the instruction. */ | |
225 | ||
226 | enum pc_write_style | |
227 | { | |
228 | BRANCH_WRITE_PC, | |
229 | BX_WRITE_PC, | |
230 | LOAD_WRITE_PC, | |
231 | ALU_WRITE_PC, | |
232 | CANNOT_WRITE_PC | |
233 | }; | |
234 | ||
235 | extern void | |
b434a28f YQ |
236 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
237 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 238 | arm_displaced_step_copy_insn_closure *dsc); |
cca44b1b JB |
239 | extern void |
240 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
241 | CORE_ADDR to, |
242 | arm_displaced_step_copy_insn_closure *dsc); | |
cca44b1b | 243 | extern ULONGEST |
1152d984 | 244 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 245 | int regno); |
cca44b1b JB |
246 | extern void |
247 | displaced_write_reg (struct regcache *regs, | |
1152d984 | 248 | arm_displaced_step_copy_insn_closure *dsc, int regno, |
cca44b1b | 249 | ULONGEST val, enum pc_write_style write_pc); |
7c00367c | 250 | |
6dc13412 | 251 | CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); |
d9311bfa AT |
252 | |
253 | ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
254 | int len, | |
255 | int byte_order); | |
256 | ||
257 | CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
258 | CORE_ADDR val); | |
259 | ||
d9311bfa AT |
260 | int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); |
261 | ||
a0ff9e1a | 262 | std::vector<CORE_ADDR> arm_software_single_step (struct regcache *); |
d0e59a68 | 263 | int arm_is_thumb (struct regcache *regcache); |
25b41d01 | 264 | int arm_frame_is_thumb (struct frame_info *frame); |
190dce09 | 265 | |
cca44b1b | 266 | extern void arm_displaced_step_fixup (struct gdbarch *, |
1152d984 | 267 | displaced_step_copy_insn_closure *, |
cca44b1b JB |
268 | CORE_ADDR, CORE_ADDR, struct regcache *); |
269 | ||
478fd957 UW |
270 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
271 | extern int arm_psr_thumb_bit (struct gdbarch *); | |
272 | ||
e3039479 UW |
273 | /* Is the instruction at the given memory address a Thumb or ARM |
274 | instruction? */ | |
275 | extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); | |
276 | ||
72508ac0 | 277 | extern int arm_process_record (struct gdbarch *gdbarch, |
dda83cd7 | 278 | struct regcache *regcache, CORE_ADDR addr); |
03b62bbb | 279 | /* Functions exported from arm-bsd-tdep.h. */ |
47ccd048 MK |
280 | |
281 | /* Return the appropriate register set for the core section identified | |
282 | by SECT_NAME and SECT_SIZE. */ | |
283 | ||
ed09174e AA |
284 | extern void |
285 | armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
286 | iterate_over_regset_sections_cb *cb, | |
287 | void *cb_data, | |
288 | const struct regcache *regcache); | |
47ccd048 | 289 | |
d105cce5 AH |
290 | /* Get the correct Arm target description with given FP hardware type. */ |
291 | const target_desc *arm_read_description (arm_fp_type fp_type); | |
292 | ||
293 | /* Get the correct Arm M-Profile target description with given hardware | |
294 | type. */ | |
295 | const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type); | |
ef7e8358 | 296 | |
47ccd048 | 297 | #endif /* arm-tdep.h */ |