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34e8f22d RE |
1 | /* Common target dependent code for GDB on ARM systems. |
2 | Copyright 2002 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | /* Register numbers of various important registers. Note that some of | |
22 | these values are "real" register numbers, and correspond to the | |
23 | general registers of the machine, and some are "phony" register | |
24 | numbers which are too large to be actual register numbers as far as | |
25 | the user is concerned but do serve to get the desired values when | |
26 | passed to read_register. */ | |
27 | ||
47a73475 MS |
28 | enum gdb_regnum { |
29 | ARM_A1_REGNUM = 0, /* first integer-like argument */ | |
30 | ARM_A4_REGNUM = 3, /* last integer-like argument */ | |
31 | ARM_AP_REGNUM = 11, | |
32 | ARM_SP_REGNUM = 13, /* Contains address of top of stack */ | |
33 | ARM_LR_REGNUM = 14, /* address to return to from a function call */ | |
34 | ARM_PC_REGNUM = 15, /* Contains program counter */ | |
35 | ARM_F0_REGNUM = 16, /* first floating point register */ | |
36 | ARM_F3_REGNUM = 19, /* last floating point argument register */ | |
37 | ARM_F7_REGNUM = 23, /* last floating point register */ | |
38 | ARM_FPS_REGNUM = 24, /* floating point status register */ | |
39 | ARM_PS_REGNUM = 25, /* Contains processor status */ | |
40 | ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */ | |
41 | THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */ | |
42 | ARM_NUM_ARG_REGS = 4, | |
43 | ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM, | |
44 | ARM_NUM_FP_ARG_REGS = 4, | |
45 | ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM | |
46 | }; | |
34e8f22d | 47 | |
7bbcf283 RE |
48 | /* Used in target-specific code when we need to know the size of the |
49 | largest type of register we need to handle. */ | |
50 | #define ARM_MAX_REGISTER_RAW_SIZE 12 | |
51 | #define ARM_MAX_REGISTER_VIRTUAL_SIZE 8 | |
34e8f22d RE |
52 | |
53 | /* Size of integer registers. */ | |
54 | #define INT_REGISTER_RAW_SIZE 4 | |
55 | #define INT_REGISTER_VIRTUAL_SIZE 4 | |
56 | ||
57 | /* Say how long FP registers are. Used for documentation purposes and | |
58 | code readability in this header. IEEE extended doubles are 80 | |
59 | bits. DWORD aligned they use 96 bits. */ | |
60 | #define FP_REGISTER_RAW_SIZE 12 | |
61 | ||
62 | /* GCC doesn't support long doubles (extended IEEE values). The FP | |
63 | register virtual size is therefore 64 bits. Used for documentation | |
64 | purposes and code readability in this header. */ | |
65 | #define FP_REGISTER_VIRTUAL_SIZE 8 | |
66 | ||
67 | /* Status registers are the same size as general purpose registers. | |
68 | Used for documentation purposes and code readability in this | |
69 | header. */ | |
70 | #define STATUS_REGISTER_SIZE 4 | |
71 | ||
72 | /* Number of machine registers. The only define actually required | |
73 | is NUM_REGS. The other definitions are used for documentation | |
74 | purposes and code readability. */ | |
75 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) | |
76 | (and called PS for processor status) so the status bits can be cleared | |
77 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed | |
78 | in PS. */ | |
79 | #define NUM_FREGS 8 /* Number of floating point registers. */ | |
80 | #define NUM_SREGS 2 /* Number of status registers. */ | |
81 | #define NUM_GREGS 16 /* Number of general purpose registers. */ | |
82 | ||
83 | ||
84 | /* Instruction condition field values. */ | |
85 | #define INST_EQ 0x0 | |
86 | #define INST_NE 0x1 | |
87 | #define INST_CS 0x2 | |
88 | #define INST_CC 0x3 | |
89 | #define INST_MI 0x4 | |
90 | #define INST_PL 0x5 | |
91 | #define INST_VS 0x6 | |
92 | #define INST_VC 0x7 | |
93 | #define INST_HI 0x8 | |
94 | #define INST_LS 0x9 | |
95 | #define INST_GE 0xa | |
96 | #define INST_LT 0xb | |
97 | #define INST_GT 0xc | |
98 | #define INST_LE 0xd | |
99 | #define INST_AL 0xe | |
100 | #define INST_NV 0xf | |
101 | ||
102 | #define FLAG_N 0x80000000 | |
103 | #define FLAG_Z 0x40000000 | |
104 | #define FLAG_C 0x20000000 | |
105 | #define FLAG_V 0x10000000 | |
106 | ||
97e03143 RE |
107 | /* ABI variants that we know about. If you add to this enum, please |
108 | update the table of names in tm-arm.c. */ | |
109 | enum arm_abi | |
110 | { | |
111 | ARM_ABI_UNKNOWN = 0, | |
112 | ARM_ABI_EABI_V1, | |
113 | ARM_ABI_EABI_V2, | |
114 | ARM_ABI_LINUX, | |
115 | ARM_ABI_NETBSD_AOUT, | |
116 | ARM_ABI_NETBSD_ELF, | |
117 | ARM_ABI_APCS, | |
118 | ARM_ABI_FREEBSD, | |
119 | ARM_ABI_WINCE, | |
120 | ||
121 | ARM_ABI_INVALID /* Keep this last. */ | |
122 | }; | |
123 | ||
08216dd7 RE |
124 | /* Type of floating-point code in use by inferior. There are really 3 models |
125 | that are traditionally supported (plus the endianness issue), but gcc can | |
126 | only generate 2 of those. The third is APCS_FLOAT, where arguments to | |
127 | functions are passed in floating-point registers. | |
128 | ||
129 | In addition to the traditional models, VFP adds two more. */ | |
130 | ||
131 | enum arm_float_model | |
132 | { | |
133 | ARM_FLOAT_SOFT, | |
134 | ARM_FLOAT_FPA, | |
135 | ARM_FLOAT_SOFT_VFP, | |
136 | ARM_FLOAT_VFP | |
137 | }; | |
138 | ||
97e03143 RE |
139 | /* Target-dependent structure in gdbarch. */ |
140 | struct gdbarch_tdep | |
141 | { | |
142 | enum arm_abi arm_abi; /* OS/ABI of inferior. */ | |
143 | const char *abi_name; /* Name of the above. */ | |
08216dd7 RE |
144 | |
145 | enum arm_float_model fp_model; /* Floating point calling conventions. */ | |
146 | ||
97e03143 RE |
147 | CORE_ADDR lowest_pc; /* Lowest address at which instructions |
148 | will appear. */ | |
9df628e0 RE |
149 | |
150 | const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ | |
151 | int arm_breakpoint_size; /* And its size. */ | |
152 | const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */ | |
153 | int thumb_breakpoint_size; /* And its size. */ | |
154 | ||
155 | int jb_pc; /* Offset to PC value in jump buffer. | |
156 | If this is negative, longjmp support | |
157 | will be disabled. */ | |
158 | size_t jb_elt_size; /* And the size of each entry in the buf. */ | |
97e03143 RE |
159 | }; |
160 | ||
161 | #ifndef LOWEST_PC | |
162 | #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc) | |
163 | #endif | |
164 | ||
34e8f22d RE |
165 | /* Prototypes for internal interfaces needed by more than one MD file. */ |
166 | int arm_pc_is_thumb_dummy (CORE_ADDR); | |
167 | ||
168 | int arm_pc_is_thumb (CORE_ADDR); | |
169 | ||
170 | CORE_ADDR thumb_get_next_pc (CORE_ADDR); | |
171 | ||
3e0b0f48 | 172 | CORE_ADDR arm_get_next_pc (CORE_ADDR); |
97e03143 RE |
173 | |
174 | /* How a OS variant tells the ARM generic code that it can handle an ABI | |
175 | type. */ | |
176 | void | |
177 | arm_gdbarch_register_os_abi (enum arm_abi abi, | |
178 | void (*init_abi)(struct gdbarch_info, | |
179 | struct gdbarch *)); |