[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2020 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct regset;
struct address_space;
struct get_next_pcs;
struct arm_get_next_pcs;
struct gdb_get_next_pcs;

/* Set to true if the 32-bit mode is in use.  */

extern bool arm_apcs_32;

#include "gdbarch.h"
#include "arch/arm.h"
#include "infrun.h"

#include <vector>

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_wmmx_registers;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count;
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define ARM_DISPLACED_MODIFIED_INSNS	8

struct arm_displaced_step_closure : public displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  arm_displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   arm_displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      arm_displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, arm_displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       arm_displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);

ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
							int len,
							int byte_order);

CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
					     CORE_ADDR val);

int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);

std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);

extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from arm-bsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Get the correct Arm target description with given FP hardware type.  */
const target_desc *arm_read_description (arm_fp_type fp_type);

/* Get the correct Arm M-Profile target description with given hardware
   type.  */
const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
b811d2c2	2	Copyright (C) 2002-2020 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83 DJ	22	/* Forward declarations. */
cb587d83 DJ	23	struct regset;
3352110b	24	struct address_space;
d9311bfa AT	25	struct get_next_pcs;
	26	struct arm_get_next_pcs;
	27	struct gdb_get_next_pcs;
cb587d83	28
c7ae7675 CB	29	/* Set to true if the 32-bit mode is in use. */
	30
	31	extern bool arm_apcs_32;
	32
0d12e84c	33	#include "gdbarch.h"
ec741292	34	#include "arch/arm.h"
cfba9872	35	#include "infrun.h"
34e8f22d	36
a0ff9e1a SM	37	#include <vector>
a0ff9e1a SM	38
34e8f22d	39	/* Number of machine registers. The only define actually required
f57d151a	40	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	41	purposes and code readability. */
	42	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	43	(and called PS for processor status) so the status bits can be cleared
	44	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	45	in PS. */
	46	#define NUM_FREGS 8 /* Number of floating point registers. */
	47	#define NUM_SREGS 2 /* Number of status registers. */
	48	#define NUM_GREGS 16 /* Number of general purpose registers. */
	49
	50
9779414d	51
08216dd7 RE	52	/* Type of floating-point code in use by inferior. There are really 3 models
	53	that are traditionally supported (plus the endianness issue), but gcc can
	54	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	55	functions are passed in floating-point registers.
	56
fd50bc42 RE	57	In addition to the traditional models, VFP adds two more.
	58
	59	If you update this enum, don't forget to update fp_model_strings in
	60	arm-tdep.c. */
08216dd7 RE	61
	62	enum arm_float_model
	63	{
fd50bc42 RE	64	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	65	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	66	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	67	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	68	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	69	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	70	};
08216dd7 RE	71
28e97307 DJ	72	/* ABI used by the inferior. */
	73	enum arm_abi_kind
	74	{
	75	ARM_ABI_AUTO,
	76	ARM_ABI_APCS,
	77	ARM_ABI_AAPCS,
	78	ARM_ABI_LAST
	79	};
fd50bc42	80
7c00367c MK	81	/* Convention for returning structures. */
	82
	83	enum struct_return
	84	{
	85	pcc_struct_return, /* Return "short" structures in memory. */
	86	reg_struct_return /* Return "short" structures in registers. */
	87	};
	88
97e03143 RE	89	/* Target-dependent structure in gdbarch. */
	90	struct gdbarch_tdep
	91	{
28e97307 DJ	92	/* The ABI for this architecture. It should never be set to
	93	ARM_ABI_AUTO. */
	94	enum arm_abi_kind arm_abi;
	95
08216dd7 RE	96	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	97
ff6f572f	98	int have_fpa_registers; /* Does the target report the FPA registers? */
a56cc1ce	99	int have_wmmx_registers; /* Does the target report the WMMX registers? */
330c6ca9 YQ	100	/* The number of VFP registers reported by the target. It is zero
	101	if VFP registers are not supported. */
	102	int vfp_register_count;
58d6951d DJ	103	int have_vfp_pseudos; /* Are we synthesizing the single precision
	104	VFP registers? */
	105	int have_neon_pseudos; /* Are we synthesizing the quad precision
	106	NEON registers? Requires
	107	have_vfp_pseudos. */
	108	int have_neon; /* Do we have a NEON unit? */
ff6f572f	109
9779414d	110	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	111	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	112	will appear. */
9df628e0	113
948f8e3d	114	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	115	int arm_breakpoint_size; /* And its size. */
948f8e3d	116	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	117	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	118
177321bd DJ	119	/* If the Thumb breakpoint is an undefined instruction (which is
	120	affected by IT blocks) rather than a BKPT instruction (which is
	121	not), then we need a 32-bit Thumb breakpoint to preserve the
	122	instruction count in IT blocks. */
948f8e3d	123	const gdb_byte *thumb2_breakpoint;
177321bd DJ	124	int thumb2_breakpoint_size;
177321bd DJ	125
0963b4bd	126	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	127	If this is negative, longjmp support
	128	will be disabled. */
	129	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	130
7c00367c MK	131	/* Convention for returning structures. */
	132	enum struct_return struct_return;
	133
27067745 UW	134	/* ISA-specific data types. */
27067745 UW	135	struct type *arm_ext_type;
58d6951d DJ	136	struct type *neon_double_type;
58d6951d DJ	137	struct type *neon_quad_type;
25b41d01	138
97dfe206 OJ	139	/* syscall record. */
97dfe206 OJ	140	int (arm_syscall_record) (struct regcache regcache, unsigned long svc_number);
97e03143 RE	141	};
97e03143 RE	142
cca44b1b JB	143	/* Structures used for displaced stepping. */
	144
	145	/* The maximum number of temporaries available for displaced instructions. */
	146	#define DISPLACED_TEMPS 16
	147	/* The maximum number of modified instructions generated for one single-stepped
	148	instruction, including the breakpoint (usually at the end of the instruction
	149	sequence) and any scratch words, etc. */
e935475c	150	#define ARM_DISPLACED_MODIFIED_INSNS 8
cca44b1b	151
cfba9872	152	struct arm_displaced_step_closure : public displaced_step_closure
cca44b1b JB	153	{
	154	ULONGEST tmp[DISPLACED_TEMPS];
	155	int rd;
	156	int wrote_to_pc;
	157	union
	158	{
	159	struct
	160	{
	161	int xfersize;
	162	int rn; /* Writeback register. */
	163	unsigned int immed : 1; /* Offset is immediate. */
	164	unsigned int writeback : 1; /* Perform base-register writeback. */
	165	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	166	} ldst;
	167
	168	struct
	169	{
	170	unsigned long dest;
	171	unsigned int link : 1;
	172	unsigned int exchange : 1;
	173	unsigned int cond : 4;
	174	} branch;
	175
	176	struct
	177	{
	178	unsigned int regmask;
	179	int rn;
	180	CORE_ADDR xfer_addr;
	181	unsigned int load : 1;
	182	unsigned int user : 1;
	183	unsigned int increment : 1;
	184	unsigned int before : 1;
	185	unsigned int writeback : 1;
	186	unsigned int cond : 4;
	187	} block;
	188
	189	struct
	190	{
	191	unsigned int immed : 1;
	192	} preload;
	193
	194	struct
	195	{
	196	/* If non-NULL, override generic SVC handling (e.g. for a particular
	197	OS). */
bd18283a	198	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cfba9872	199	arm_displaced_step_closure *dsc);
cca44b1b JB	200	} svc;
cca44b1b JB	201	} u;
4db71c0b YQ	202
	203	/* The size of original instruction, 2 or 4. */
	204	unsigned int insn_size;
	205	/* True if the original insn (and thus all replacement insns) are Thumb
	206	instead of ARM. */
	207	unsigned int is_thumb;
	208
	209	/* The slots in the array is used in this way below,
	210	- ARM instruction occupies one slot,
	211	- Thumb 16 bit instruction occupies one slot,
	212	- Thumb 32-bit instruction occupies two slots, one part for each. */
e935475c	213	unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
cca44b1b JB	214	int numinsns;
	215	CORE_ADDR insn_addr;
	216	CORE_ADDR scratch_base;
	217	void (cleanup) (struct gdbarch , struct regcache *,
cfba9872	218	arm_displaced_step_closure *);
cca44b1b JB	219	};
	220
	221	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	222	write may write to the PC, specifies the way the CPSR T bit, etc. is
	223	modified by the instruction. */
	224
	225	enum pc_write_style
	226	{
	227	BRANCH_WRITE_PC,
	228	BX_WRITE_PC,
	229	LOAD_WRITE_PC,
	230	ALU_WRITE_PC,
	231	CANNOT_WRITE_PC
	232	};
	233
	234	extern void
b434a28f YQ	235	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	236	CORE_ADDR to, struct regcache *regs,
cfba9872	237	arm_displaced_step_closure *dsc);
cca44b1b JB	238	extern void
cca44b1b JB	239	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
cfba9872	240	CORE_ADDR to, arm_displaced_step_closure *dsc);
cca44b1b	241	extern ULONGEST
cfba9872	242	displaced_read_reg (struct regcache regs, arm_displaced_step_closure dsc,
36073a92	243	int regno);
cca44b1b JB	244	extern void
cca44b1b JB	245	displaced_write_reg (struct regcache *regs,
cfba9872	246	arm_displaced_step_closure *dsc, int regno,
cca44b1b	247	ULONGEST val, enum pc_write_style write_pc);
7c00367c	248
6dc13412	249	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
d9311bfa AT	250
	251	ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
	252	int len,
	253	int byte_order);
	254
	255	CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
	256	CORE_ADDR val);
	257
d9311bfa AT	258	int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
d9311bfa AT	259
a0ff9e1a	260	std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
d0e59a68	261	int arm_is_thumb (struct regcache *regcache);
25b41d01	262	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	263
cca44b1b JB	264	extern void arm_displaced_step_fixup (struct gdbarch *,
	265	struct displaced_step_closure *,
	266	CORE_ADDR, CORE_ADDR, struct regcache *);
	267
478fd957 UW	268	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	269	extern int arm_psr_thumb_bit (struct gdbarch *);
	270
e3039479 UW	271	/* Is the instruction at the given memory address a Thumb or ARM
	272	instruction? */
	273	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	274
72508ac0 PO	275	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	276	struct regcache *regcache, CORE_ADDR addr);
03b62bbb	277	/* Functions exported from arm-bsd-tdep.h. */
47ccd048 MK	278
	279	/* Return the appropriate register set for the core section identified
	280	by SECT_NAME and SECT_SIZE. */
	281
ed09174e AA	282	extern void
	283	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	284	iterate_over_regset_sections_cb *cb,
	285	void *cb_data,
	286	const struct regcache *regcache);
47ccd048	287
d105cce5 AH	288	/* Get the correct Arm target description with given FP hardware type. */
	289	const target_desc *arm_read_description (arm_fp_type fp_type);
	290
	291	/* Get the correct Arm M-Profile target description with given hardware
	292	type. */
	293	const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);
ef7e8358	294
47ccd048	295	#endif /* arm-tdep.h */