Commit | Line | Data |
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8818c391 | 1 | /* Target-dependent code for Atmel AVR, for GDB. |
0fd88904 | 2 | |
32d0add0 | 3 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
8818c391 TR |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
8818c391 TR |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
8818c391 | 19 | |
de18ac1f | 20 | /* Contributed by Theodore A. Roth, troth@openavr.org */ |
8818c391 TR |
21 | |
22 | /* Portions of this file were taken from the original gdb-4.18 patch developed | |
23 | by Denis Chertykov, denisc@overta.ru */ | |
24 | ||
25 | #include "defs.h" | |
4add8633 TR |
26 | #include "frame.h" |
27 | #include "frame-unwind.h" | |
28 | #include "frame-base.h" | |
29 | #include "trad-frame.h" | |
8818c391 TR |
30 | #include "gdbcmd.h" |
31 | #include "gdbcore.h" | |
e6bb342a | 32 | #include "gdbtypes.h" |
8818c391 TR |
33 | #include "inferior.h" |
34 | #include "symfile.h" | |
35 | #include "arch-utils.h" | |
36 | #include "regcache.h" | |
a89aa300 | 37 | #include "dis-asm.h" |
77e371c0 | 38 | #include "objfiles.h" |
8818c391 TR |
39 | |
40 | /* AVR Background: | |
41 | ||
42 | (AVR micros are pure Harvard Architecture processors.) | |
43 | ||
44 | The AVR family of microcontrollers have three distinctly different memory | |
0963b4bd MS |
45 | spaces: flash, sram and eeprom. The flash is 16 bits wide and is used for |
46 | the most part to store program instructions. The sram is 8 bits wide and is | |
47 | used for the stack and the heap. Some devices lack sram and some can have | |
8818c391 TR |
48 | an additional external sram added on as a peripheral. |
49 | ||
50 | The eeprom is 8 bits wide and is used to store data when the device is | |
0963b4bd MS |
51 | powered down. Eeprom is not directly accessible, it can only be accessed |
52 | via io-registers using a special algorithm. Accessing eeprom via gdb's | |
8818c391 TR |
53 | remote serial protocol ('m' or 'M' packets) looks difficult to do and is |
54 | not included at this time. | |
55 | ||
56 | [The eeprom could be read manually via ``x/b <eaddr + AVR_EMEM_START>'' or | |
57 | written using ``set {unsigned char}<eaddr + AVR_EMEM_START>''. For this to | |
58 | work, the remote target must be able to handle eeprom accesses and perform | |
59 | the address translation.] | |
60 | ||
0963b4bd | 61 | All three memory spaces have physical addresses beginning at 0x0. In |
8818c391 TR |
62 | addition, the flash is addressed by gcc/binutils/gdb with respect to 8 bit |
63 | bytes instead of the 16 bit wide words used by the real device for the | |
64 | Program Counter. | |
65 | ||
66 | In order for remote targets to work correctly, extra bits must be added to | |
67 | addresses before they are send to the target or received from the target | |
0963b4bd MS |
68 | via the remote serial protocol. The extra bits are the MSBs and are used to |
69 | decode which memory space the address is referring to. */ | |
8818c391 | 70 | |
8818c391 TR |
71 | /* Constants: prefixed with AVR_ to avoid name space clashes */ |
72 | ||
487d9753 PL |
73 | /* Address space flags */ |
74 | ||
75 | /* We are assigning the TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 to the flash address | |
76 | space. */ | |
77 | ||
78 | #define AVR_TYPE_ADDRESS_CLASS_FLASH TYPE_ADDRESS_CLASS_1 | |
79 | #define AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH \ | |
80 | TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 | |
81 | ||
82 | ||
8818c391 | 83 | enum |
2e5ff58c TR |
84 | { |
85 | AVR_REG_W = 24, | |
86 | AVR_REG_X = 26, | |
87 | AVR_REG_Y = 28, | |
88 | AVR_FP_REGNUM = 28, | |
89 | AVR_REG_Z = 30, | |
90 | ||
91 | AVR_SREG_REGNUM = 32, | |
92 | AVR_SP_REGNUM = 33, | |
93 | AVR_PC_REGNUM = 34, | |
94 | ||
95 | AVR_NUM_REGS = 32 + 1 /*SREG*/ + 1 /*SP*/ + 1 /*PC*/, | |
96 | AVR_NUM_REG_BYTES = 32 + 1 /*SREG*/ + 2 /*SP*/ + 4 /*PC*/, | |
97 | ||
7d2552b4 TG |
98 | /* Pseudo registers. */ |
99 | AVR_PSEUDO_PC_REGNUM = 35, | |
100 | AVR_NUM_PSEUDO_REGS = 1, | |
101 | ||
2e5ff58c TR |
102 | AVR_PC_REG_INDEX = 35, /* index into array of registers */ |
103 | ||
4add8633 | 104 | AVR_MAX_PROLOGUE_SIZE = 64, /* bytes */ |
2e5ff58c | 105 | |
0963b4bd | 106 | /* Count of pushed registers. From r2 to r17 (inclusively), r28, r29 */ |
2e5ff58c TR |
107 | AVR_MAX_PUSHES = 18, |
108 | ||
0963b4bd | 109 | /* Number of the last pushed register. r17 for current avr-gcc */ |
2e5ff58c TR |
110 | AVR_LAST_PUSHED_REGNUM = 17, |
111 | ||
4add8633 TR |
112 | AVR_ARG1_REGNUM = 24, /* Single byte argument */ |
113 | AVR_ARGN_REGNUM = 25, /* Multi byte argments */ | |
114 | ||
115 | AVR_RET1_REGNUM = 24, /* Single byte return value */ | |
116 | AVR_RETN_REGNUM = 25, /* Multi byte return value */ | |
117 | ||
2e5ff58c | 118 | /* FIXME: TRoth/2002-01-??: Can we shift all these memory masks left 8 |
0963b4bd | 119 | bits? Do these have to match the bfd vma values? It sure would make |
2e5ff58c TR |
120 | things easier in the future if they didn't need to match. |
121 | ||
122 | Note: I chose these values so as to be consistent with bfd vma | |
123 | addresses. | |
124 | ||
125 | TRoth/2002-04-08: There is already a conflict with very large programs | |
0963b4bd | 126 | in the mega128. The mega128 has 128K instruction bytes (64K words), |
2e5ff58c TR |
127 | thus the Most Significant Bit is 0x10000 which gets masked off my |
128 | AVR_MEM_MASK. | |
129 | ||
130 | The problem manifests itself when trying to set a breakpoint in a | |
131 | function which resides in the upper half of the instruction space and | |
132 | thus requires a 17-bit address. | |
133 | ||
134 | For now, I've just removed the EEPROM mask and changed AVR_MEM_MASK | |
0963b4bd | 135 | from 0x00ff0000 to 0x00f00000. Eeprom is not accessible from gdb yet, |
2e5ff58c TR |
136 | but could be for some remote targets by just adding the correct offset |
137 | to the address and letting the remote target handle the low-level | |
0963b4bd | 138 | details of actually accessing the eeprom. */ |
2e5ff58c TR |
139 | |
140 | AVR_IMEM_START = 0x00000000, /* INSN memory */ | |
141 | AVR_SMEM_START = 0x00800000, /* SRAM memory */ | |
8818c391 | 142 | #if 1 |
2e5ff58c TR |
143 | /* No eeprom mask defined */ |
144 | AVR_MEM_MASK = 0x00f00000, /* mask to determine memory space */ | |
8818c391 | 145 | #else |
2e5ff58c TR |
146 | AVR_EMEM_START = 0x00810000, /* EEPROM memory */ |
147 | AVR_MEM_MASK = 0x00ff0000, /* mask to determine memory space */ | |
8818c391 | 148 | #endif |
2e5ff58c | 149 | }; |
8818c391 | 150 | |
4add8633 TR |
151 | /* Prologue types: |
152 | ||
153 | NORMAL and CALL are the typical types (the -mcall-prologues gcc option | |
154 | causes the generation of the CALL type prologues). */ | |
155 | ||
156 | enum { | |
157 | AVR_PROLOGUE_NONE, /* No prologue */ | |
158 | AVR_PROLOGUE_NORMAL, | |
159 | AVR_PROLOGUE_CALL, /* -mcall-prologues */ | |
160 | AVR_PROLOGUE_MAIN, | |
161 | AVR_PROLOGUE_INTR, /* interrupt handler */ | |
162 | AVR_PROLOGUE_SIG, /* signal handler */ | |
163 | }; | |
164 | ||
8818c391 TR |
165 | /* Any function with a frame looks like this |
166 | ....... <-SP POINTS HERE | |
167 | LOCALS1 <-FP POINTS HERE | |
168 | LOCALS0 | |
169 | SAVED FP | |
170 | SAVED R3 | |
171 | SAVED R2 | |
172 | RET PC | |
173 | FIRST ARG | |
174 | SECOND ARG */ | |
175 | ||
4add8633 | 176 | struct avr_unwind_cache |
2e5ff58c | 177 | { |
4add8633 TR |
178 | /* The previous frame's inner most stack address. Used as this |
179 | frame ID's stack_addr. */ | |
180 | CORE_ADDR prev_sp; | |
181 | /* The frame's base, optionally used by the high-level debug info. */ | |
182 | CORE_ADDR base; | |
183 | int size; | |
184 | int prologue_type; | |
185 | /* Table indicating the location of each and every register. */ | |
186 | struct trad_frame_saved_reg *saved_regs; | |
2e5ff58c | 187 | }; |
8818c391 TR |
188 | |
189 | struct gdbarch_tdep | |
2e5ff58c | 190 | { |
4e99ad69 | 191 | /* Number of bytes stored to the stack by call instructions. |
9c97a070 | 192 | 2 bytes for avr1-5 and avrxmega1-5, 3 bytes for avr6 and avrxmega6-7. */ |
4e99ad69 | 193 | int call_length; |
7d2552b4 TG |
194 | |
195 | /* Type for void. */ | |
196 | struct type *void_type; | |
197 | /* Type for a function returning void. */ | |
198 | struct type *func_void_type; | |
199 | /* Type for a pointer to a function. Used for the type of PC. */ | |
200 | struct type *pc_type; | |
2e5ff58c | 201 | }; |
8818c391 | 202 | |
0963b4bd | 203 | /* Lookup the name of a register given it's number. */ |
8818c391 | 204 | |
fa88f677 | 205 | static const char * |
d93859e2 | 206 | avr_register_name (struct gdbarch *gdbarch, int regnum) |
8818c391 | 207 | { |
4e99ad69 | 208 | static const char * const register_names[] = { |
2e5ff58c TR |
209 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
210 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8818c391 TR |
211 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
212 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
7d2552b4 TG |
213 | "SREG", "SP", "PC2", |
214 | "pc" | |
8818c391 TR |
215 | }; |
216 | if (regnum < 0) | |
217 | return NULL; | |
218 | if (regnum >= (sizeof (register_names) / sizeof (*register_names))) | |
219 | return NULL; | |
220 | return register_names[regnum]; | |
221 | } | |
222 | ||
8818c391 TR |
223 | /* Return the GDB type object for the "standard" data type |
224 | of data in register N. */ | |
225 | ||
226 | static struct type * | |
866b76ea | 227 | avr_register_type (struct gdbarch *gdbarch, int reg_nr) |
8818c391 | 228 | { |
866b76ea | 229 | if (reg_nr == AVR_PC_REGNUM) |
df4df182 | 230 | return builtin_type (gdbarch)->builtin_uint32; |
7d2552b4 TG |
231 | if (reg_nr == AVR_PSEUDO_PC_REGNUM) |
232 | return gdbarch_tdep (gdbarch)->pc_type; | |
866b76ea | 233 | if (reg_nr == AVR_SP_REGNUM) |
0dfff4cb | 234 | return builtin_type (gdbarch)->builtin_data_ptr; |
7d2552b4 | 235 | return builtin_type (gdbarch)->builtin_uint8; |
8818c391 TR |
236 | } |
237 | ||
0963b4bd | 238 | /* Instruction address checks and convertions. */ |
8818c391 TR |
239 | |
240 | static CORE_ADDR | |
241 | avr_make_iaddr (CORE_ADDR x) | |
242 | { | |
243 | return ((x) | AVR_IMEM_START); | |
244 | } | |
245 | ||
0963b4bd | 246 | /* FIXME: TRoth: Really need to use a larger mask for instructions. Some |
8818c391 TR |
247 | devices are already up to 128KBytes of flash space. |
248 | ||
0963b4bd | 249 | TRoth/2002-04-8: See comment above where AVR_IMEM_START is defined. */ |
8818c391 TR |
250 | |
251 | static CORE_ADDR | |
252 | avr_convert_iaddr_to_raw (CORE_ADDR x) | |
253 | { | |
254 | return ((x) & 0xffffffff); | |
255 | } | |
256 | ||
0963b4bd | 257 | /* SRAM address checks and convertions. */ |
8818c391 TR |
258 | |
259 | static CORE_ADDR | |
260 | avr_make_saddr (CORE_ADDR x) | |
261 | { | |
ee143e81 TG |
262 | /* Return 0 for NULL. */ |
263 | if (x == 0) | |
264 | return 0; | |
265 | ||
8818c391 TR |
266 | return ((x) | AVR_SMEM_START); |
267 | } | |
268 | ||
8818c391 TR |
269 | static CORE_ADDR |
270 | avr_convert_saddr_to_raw (CORE_ADDR x) | |
271 | { | |
272 | return ((x) & 0xffffffff); | |
273 | } | |
274 | ||
0963b4bd MS |
275 | /* EEPROM address checks and convertions. I don't know if these will ever |
276 | actually be used, but I've added them just the same. TRoth */ | |
8818c391 TR |
277 | |
278 | /* TRoth/2002-04-08: Commented out for now to allow fix for problem with large | |
0963b4bd | 279 | programs in the mega128. */ |
8818c391 TR |
280 | |
281 | /* static CORE_ADDR */ | |
282 | /* avr_make_eaddr (CORE_ADDR x) */ | |
283 | /* { */ | |
284 | /* return ((x) | AVR_EMEM_START); */ | |
285 | /* } */ | |
286 | ||
287 | /* static int */ | |
288 | /* avr_eaddr_p (CORE_ADDR x) */ | |
289 | /* { */ | |
290 | /* return (((x) & AVR_MEM_MASK) == AVR_EMEM_START); */ | |
291 | /* } */ | |
292 | ||
293 | /* static CORE_ADDR */ | |
294 | /* avr_convert_eaddr_to_raw (CORE_ADDR x) */ | |
295 | /* { */ | |
296 | /* return ((x) & 0xffffffff); */ | |
297 | /* } */ | |
298 | ||
0963b4bd | 299 | /* Convert from address to pointer and vice-versa. */ |
8818c391 TR |
300 | |
301 | static void | |
9898f801 UW |
302 | avr_address_to_pointer (struct gdbarch *gdbarch, |
303 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
8818c391 | 304 | { |
e17a4113 UW |
305 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
306 | ||
487d9753 PL |
307 | /* Is it a data address in flash? */ |
308 | if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) | |
309 | { | |
7d0d9d2b | 310 | /* A data pointer in flash is byte addressed. */ |
487d9753 PL |
311 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
312 | avr_convert_iaddr_to_raw (addr)); | |
313 | } | |
8818c391 | 314 | /* Is it a code address? */ |
487d9753 PL |
315 | else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC |
316 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
8818c391 | 317 | { |
7d0d9d2b PL |
318 | /* A code pointer is word (16 bits) addressed. We shift the address down |
319 | by 1 bit to convert it to a pointer. */ | |
e17a4113 | 320 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
4ea2465e | 321 | avr_convert_iaddr_to_raw (addr >> 1)); |
8818c391 TR |
322 | } |
323 | else | |
324 | { | |
325 | /* Strip off any upper segment bits. */ | |
e17a4113 | 326 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
2e5ff58c | 327 | avr_convert_saddr_to_raw (addr)); |
8818c391 TR |
328 | } |
329 | } | |
330 | ||
331 | static CORE_ADDR | |
9898f801 UW |
332 | avr_pointer_to_address (struct gdbarch *gdbarch, |
333 | struct type *type, const gdb_byte *buf) | |
8818c391 | 334 | { |
e17a4113 UW |
335 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
336 | CORE_ADDR addr | |
337 | = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); | |
8818c391 | 338 | |
487d9753 PL |
339 | /* Is it a data address in flash? */ |
340 | if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) | |
7d0d9d2b PL |
341 | { |
342 | /* A data pointer in flash is already byte addressed. */ | |
343 | return avr_make_iaddr (addr); | |
344 | } | |
8818c391 | 345 | /* Is it a code address? */ |
487d9753 PL |
346 | else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC |
347 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD | |
348 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
7d0d9d2b PL |
349 | { |
350 | /* A code pointer is word (16 bits) addressed so we shift it up | |
351 | by 1 bit to convert it to an address. */ | |
352 | return avr_make_iaddr (addr << 1); | |
353 | } | |
8818c391 TR |
354 | else |
355 | return avr_make_saddr (addr); | |
356 | } | |
357 | ||
8a1d23b2 TG |
358 | static CORE_ADDR |
359 | avr_integer_to_address (struct gdbarch *gdbarch, | |
360 | struct type *type, const gdb_byte *buf) | |
361 | { | |
362 | ULONGEST addr = unpack_long (type, buf); | |
363 | ||
364 | return avr_make_saddr (addr); | |
365 | } | |
366 | ||
8818c391 | 367 | static CORE_ADDR |
61a1198a | 368 | avr_read_pc (struct regcache *regcache) |
8818c391 | 369 | { |
8619218d | 370 | ULONGEST pc; |
61a1198a UW |
371 | regcache_cooked_read_unsigned (regcache, AVR_PC_REGNUM, &pc); |
372 | return avr_make_iaddr (pc); | |
8818c391 TR |
373 | } |
374 | ||
375 | static void | |
61a1198a | 376 | avr_write_pc (struct regcache *regcache, CORE_ADDR val) |
8818c391 | 377 | { |
61a1198a | 378 | regcache_cooked_write_unsigned (regcache, AVR_PC_REGNUM, |
7d2552b4 TG |
379 | avr_convert_iaddr_to_raw (val)); |
380 | } | |
381 | ||
05d1431c | 382 | static enum register_status |
7d2552b4 TG |
383 | avr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
384 | int regnum, gdb_byte *buf) | |
385 | { | |
386 | ULONGEST val; | |
05d1431c | 387 | enum register_status status; |
7d2552b4 TG |
388 | |
389 | switch (regnum) | |
390 | { | |
391 | case AVR_PSEUDO_PC_REGNUM: | |
05d1431c PA |
392 | status = regcache_raw_read_unsigned (regcache, AVR_PC_REGNUM, &val); |
393 | if (status != REG_VALID) | |
394 | return status; | |
7d2552b4 TG |
395 | val >>= 1; |
396 | store_unsigned_integer (buf, 4, gdbarch_byte_order (gdbarch), val); | |
05d1431c | 397 | return status; |
7d2552b4 TG |
398 | default: |
399 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
400 | } | |
401 | } | |
402 | ||
403 | static void | |
404 | avr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
405 | int regnum, const gdb_byte *buf) | |
406 | { | |
407 | ULONGEST val; | |
408 | ||
409 | switch (regnum) | |
410 | { | |
411 | case AVR_PSEUDO_PC_REGNUM: | |
412 | val = extract_unsigned_integer (buf, 4, gdbarch_byte_order (gdbarch)); | |
413 | val <<= 1; | |
414 | regcache_raw_write_unsigned (regcache, AVR_PC_REGNUM, val); | |
415 | break; | |
416 | default: | |
417 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
418 | } | |
8818c391 TR |
419 | } |
420 | ||
4add8633 | 421 | /* Function: avr_scan_prologue |
8818c391 | 422 | |
4add8633 | 423 | This function decodes an AVR function prologue to determine: |
8818c391 TR |
424 | 1) the size of the stack frame |
425 | 2) which registers are saved on it | |
426 | 3) the offsets of saved regs | |
4add8633 | 427 | This information is stored in the avr_unwind_cache structure. |
8818c391 | 428 | |
e3d8b004 TR |
429 | Some devices lack the sbiw instruction, so on those replace this: |
430 | sbiw r28, XX | |
431 | with this: | |
432 | subi r28,lo8(XX) | |
433 | sbci r29,hi8(XX) | |
434 | ||
435 | A typical AVR function prologue with a frame pointer might look like this: | |
436 | push rXX ; saved regs | |
437 | ... | |
438 | push r28 | |
439 | push r29 | |
440 | in r28,__SP_L__ | |
441 | in r29,__SP_H__ | |
442 | sbiw r28,<LOCALS_SIZE> | |
443 | in __tmp_reg__,__SREG__ | |
8818c391 | 444 | cli |
e3d8b004 | 445 | out __SP_H__,r29 |
72fab697 TR |
446 | out __SREG__,__tmp_reg__ |
447 | out __SP_L__,r28 | |
e3d8b004 TR |
448 | |
449 | A typical AVR function prologue without a frame pointer might look like | |
450 | this: | |
451 | push rXX ; saved regs | |
452 | ... | |
453 | ||
454 | A main function prologue looks like this: | |
455 | ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) | |
456 | ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) | |
457 | out __SP_H__,r29 | |
458 | out __SP_L__,r28 | |
459 | ||
460 | A signal handler prologue looks like this: | |
461 | push __zero_reg__ | |
462 | push __tmp_reg__ | |
463 | in __tmp_reg__, __SREG__ | |
464 | push __tmp_reg__ | |
465 | clr __zero_reg__ | |
466 | push rXX ; save registers r18:r27, r30:r31 | |
467 | ... | |
468 | push r28 ; save frame pointer | |
469 | push r29 | |
470 | in r28, __SP_L__ | |
471 | in r29, __SP_H__ | |
472 | sbiw r28, <LOCALS_SIZE> | |
473 | out __SP_H__, r29 | |
474 | out __SP_L__, r28 | |
475 | ||
476 | A interrupt handler prologue looks like this: | |
477 | sei | |
478 | push __zero_reg__ | |
479 | push __tmp_reg__ | |
480 | in __tmp_reg__, __SREG__ | |
481 | push __tmp_reg__ | |
482 | clr __zero_reg__ | |
483 | push rXX ; save registers r18:r27, r30:r31 | |
484 | ... | |
485 | push r28 ; save frame pointer | |
486 | push r29 | |
487 | in r28, __SP_L__ | |
488 | in r29, __SP_H__ | |
489 | sbiw r28, <LOCALS_SIZE> | |
490 | cli | |
491 | out __SP_H__, r29 | |
492 | sei | |
493 | out __SP_L__, r28 | |
494 | ||
495 | A `-mcall-prologues' prologue looks like this (Note that the megas use a | |
496 | jmp instead of a rjmp, thus the prologue is one word larger since jmp is a | |
497 | 32 bit insn and rjmp is a 16 bit insn): | |
498 | ldi r26,lo8(<LOCALS_SIZE>) | |
499 | ldi r27,hi8(<LOCALS_SIZE>) | |
500 | ldi r30,pm_lo8(.L_foo_body) | |
501 | ldi r31,pm_hi8(.L_foo_body) | |
502 | rjmp __prologue_saves__+RRR | |
503 | .L_foo_body: */ | |
8818c391 | 504 | |
4add8633 TR |
505 | /* Not really part of a prologue, but still need to scan for it, is when a |
506 | function prologue moves values passed via registers as arguments to new | |
0963b4bd MS |
507 | registers. In this case, all local variables live in registers, so there |
508 | may be some register saves. This is what it looks like: | |
4add8633 TR |
509 | movw rMM, rNN |
510 | ... | |
511 | ||
0963b4bd MS |
512 | There could be multiple movw's. If the target doesn't have a movw insn, it |
513 | will use two mov insns. This could be done after any of the above prologue | |
4add8633 TR |
514 | types. */ |
515 | ||
516 | static CORE_ADDR | |
e17a4113 | 517 | avr_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, |
4e99ad69 | 518 | struct avr_unwind_cache *info) |
8818c391 | 519 | { |
e17a4113 | 520 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e5ff58c TR |
521 | int i; |
522 | unsigned short insn; | |
2e5ff58c | 523 | int scan_stage = 0; |
3b7344d5 | 524 | struct bound_minimal_symbol msymbol; |
8818c391 TR |
525 | unsigned char prologue[AVR_MAX_PROLOGUE_SIZE]; |
526 | int vpc = 0; | |
4e99ad69 TG |
527 | int len; |
528 | ||
529 | len = pc_end - pc_beg; | |
530 | if (len > AVR_MAX_PROLOGUE_SIZE) | |
531 | len = AVR_MAX_PROLOGUE_SIZE; | |
8818c391 | 532 | |
4add8633 | 533 | /* FIXME: TRoth/2003-06-11: This could be made more efficient by only |
0963b4bd MS |
534 | reading in the bytes of the prologue. The problem is that the figuring |
535 | out where the end of the prologue is is a bit difficult. The old code | |
4add8633 | 536 | tried to do that, but failed quite often. */ |
4e99ad69 | 537 | read_memory (pc_beg, prologue, len); |
8818c391 TR |
538 | |
539 | /* Scanning main()'s prologue | |
540 | ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) | |
541 | ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) | |
542 | out __SP_H__,r29 | |
543 | out __SP_L__,r28 */ | |
544 | ||
4e99ad69 | 545 | if (len >= 4) |
8818c391 TR |
546 | { |
547 | CORE_ADDR locals; | |
4e99ad69 | 548 | static const unsigned char img[] = { |
2e5ff58c TR |
549 | 0xde, 0xbf, /* out __SP_H__,r29 */ |
550 | 0xcd, 0xbf /* out __SP_L__,r28 */ | |
8818c391 TR |
551 | }; |
552 | ||
e17a4113 | 553 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
8818c391 | 554 | /* ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) */ |
2e5ff58c TR |
555 | if ((insn & 0xf0f0) == 0xe0c0) |
556 | { | |
557 | locals = (insn & 0xf) | ((insn & 0x0f00) >> 4); | |
e17a4113 | 558 | insn = extract_unsigned_integer (&prologue[vpc + 2], 2, byte_order); |
2e5ff58c TR |
559 | /* ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) */ |
560 | if ((insn & 0xf0f0) == 0xe0d0) | |
561 | { | |
562 | locals |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; | |
4e99ad69 TG |
563 | if (vpc + 4 + sizeof (img) < len |
564 | && memcmp (prologue + vpc + 4, img, sizeof (img)) == 0) | |
2e5ff58c | 565 | { |
4add8633 TR |
566 | info->prologue_type = AVR_PROLOGUE_MAIN; |
567 | info->base = locals; | |
4e99ad69 | 568 | return pc_beg + 4; |
2e5ff58c TR |
569 | } |
570 | } | |
571 | } | |
8818c391 | 572 | } |
2e5ff58c | 573 | |
4add8633 TR |
574 | /* Scanning `-mcall-prologues' prologue |
575 | Classic prologue is 10 bytes, mega prologue is a 12 bytes long */ | |
8818c391 | 576 | |
e3d8b004 | 577 | while (1) /* Using a while to avoid many goto's */ |
8818c391 TR |
578 | { |
579 | int loc_size; | |
580 | int body_addr; | |
581 | unsigned num_pushes; | |
4add8633 | 582 | int pc_offset = 0; |
2e5ff58c | 583 | |
4e99ad69 TG |
584 | /* At least the fifth instruction must have been executed to |
585 | modify frame shape. */ | |
586 | if (len < 10) | |
587 | break; | |
588 | ||
e17a4113 | 589 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
8818c391 | 590 | /* ldi r26,<LOCALS_SIZE> */ |
2e5ff58c TR |
591 | if ((insn & 0xf0f0) != 0xe0a0) |
592 | break; | |
8818c391 | 593 | loc_size = (insn & 0xf) | ((insn & 0x0f00) >> 4); |
4add8633 | 594 | pc_offset += 2; |
2e5ff58c | 595 | |
e17a4113 | 596 | insn = extract_unsigned_integer (&prologue[vpc + 2], 2, byte_order); |
8818c391 TR |
597 | /* ldi r27,<LOCALS_SIZE> / 256 */ |
598 | if ((insn & 0xf0f0) != 0xe0b0) | |
2e5ff58c | 599 | break; |
8818c391 | 600 | loc_size |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; |
4add8633 | 601 | pc_offset += 2; |
2e5ff58c | 602 | |
e17a4113 | 603 | insn = extract_unsigned_integer (&prologue[vpc + 4], 2, byte_order); |
8818c391 TR |
604 | /* ldi r30,pm_lo8(.L_foo_body) */ |
605 | if ((insn & 0xf0f0) != 0xe0e0) | |
2e5ff58c | 606 | break; |
8818c391 | 607 | body_addr = (insn & 0xf) | ((insn & 0x0f00) >> 4); |
4add8633 | 608 | pc_offset += 2; |
8818c391 | 609 | |
e17a4113 | 610 | insn = extract_unsigned_integer (&prologue[vpc + 6], 2, byte_order); |
8818c391 TR |
611 | /* ldi r31,pm_hi8(.L_foo_body) */ |
612 | if ((insn & 0xf0f0) != 0xe0f0) | |
2e5ff58c | 613 | break; |
8818c391 | 614 | body_addr |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; |
4add8633 | 615 | pc_offset += 2; |
8818c391 | 616 | |
8818c391 | 617 | msymbol = lookup_minimal_symbol ("__prologue_saves__", NULL, NULL); |
3b7344d5 | 618 | if (!msymbol.minsym) |
2e5ff58c | 619 | break; |
8818c391 | 620 | |
e17a4113 | 621 | insn = extract_unsigned_integer (&prologue[vpc + 8], 2, byte_order); |
8818c391 | 622 | /* rjmp __prologue_saves__+RRR */ |
e3d8b004 TR |
623 | if ((insn & 0xf000) == 0xc000) |
624 | { | |
625 | /* Extract PC relative offset from RJMP */ | |
626 | i = (insn & 0xfff) | (insn & 0x800 ? (-1 ^ 0xfff) : 0); | |
627 | /* Convert offset to byte addressable mode */ | |
628 | i *= 2; | |
629 | /* Destination address */ | |
4e99ad69 | 630 | i += pc_beg + 10; |
e3d8b004 | 631 | |
4e99ad69 | 632 | if (body_addr != (pc_beg + 10)/2) |
e3d8b004 | 633 | break; |
4add8633 TR |
634 | |
635 | pc_offset += 2; | |
e3d8b004 | 636 | } |
e3d8b004 TR |
637 | else if ((insn & 0xfe0e) == 0x940c) |
638 | { | |
639 | /* Extract absolute PC address from JMP */ | |
640 | i = (((insn & 0x1) | ((insn & 0x1f0) >> 3) << 16) | |
e17a4113 UW |
641 | | (extract_unsigned_integer (&prologue[vpc + 10], 2, byte_order) |
642 | & 0xffff)); | |
e3d8b004 TR |
643 | /* Convert address to byte addressable mode */ |
644 | i *= 2; | |
645 | ||
4e99ad69 | 646 | if (body_addr != (pc_beg + 12)/2) |
e3d8b004 | 647 | break; |
4add8633 TR |
648 | |
649 | pc_offset += 4; | |
e3d8b004 TR |
650 | } |
651 | else | |
652 | break; | |
2e5ff58c | 653 | |
4add8633 | 654 | /* Resolve offset (in words) from __prologue_saves__ symbol. |
8818c391 | 655 | Which is a pushes count in `-mcall-prologues' mode */ |
77e371c0 | 656 | num_pushes = AVR_MAX_PUSHES - (i - BMSYMBOL_VALUE_ADDRESS (msymbol)) / 2; |
8818c391 TR |
657 | |
658 | if (num_pushes > AVR_MAX_PUSHES) | |
4add8633 | 659 | { |
edefbb7c | 660 | fprintf_unfiltered (gdb_stderr, _("Num pushes too large: %d\n"), |
4add8633 TR |
661 | num_pushes); |
662 | num_pushes = 0; | |
663 | } | |
2e5ff58c | 664 | |
8818c391 | 665 | if (num_pushes) |
2e5ff58c TR |
666 | { |
667 | int from; | |
4add8633 TR |
668 | |
669 | info->saved_regs[AVR_FP_REGNUM + 1].addr = num_pushes; | |
2e5ff58c | 670 | if (num_pushes >= 2) |
4add8633 TR |
671 | info->saved_regs[AVR_FP_REGNUM].addr = num_pushes - 1; |
672 | ||
2e5ff58c TR |
673 | i = 0; |
674 | for (from = AVR_LAST_PUSHED_REGNUM + 1 - (num_pushes - 2); | |
675 | from <= AVR_LAST_PUSHED_REGNUM; ++from) | |
4add8633 | 676 | info->saved_regs [from].addr = ++i; |
2e5ff58c | 677 | } |
4add8633 TR |
678 | info->size = loc_size + num_pushes; |
679 | info->prologue_type = AVR_PROLOGUE_CALL; | |
680 | ||
4e99ad69 | 681 | return pc_beg + pc_offset; |
8818c391 TR |
682 | } |
683 | ||
4add8633 TR |
684 | /* Scan for the beginning of the prologue for an interrupt or signal |
685 | function. Note that we have to set the prologue type here since the | |
686 | third stage of the prologue may not be present (e.g. no saved registered | |
687 | or changing of the SP register). */ | |
8818c391 | 688 | |
4add8633 | 689 | if (1) |
8818c391 | 690 | { |
4e99ad69 | 691 | static const unsigned char img[] = { |
2e5ff58c TR |
692 | 0x78, 0x94, /* sei */ |
693 | 0x1f, 0x92, /* push r1 */ | |
694 | 0x0f, 0x92, /* push r0 */ | |
695 | 0x0f, 0xb6, /* in r0,0x3f SREG */ | |
696 | 0x0f, 0x92, /* push r0 */ | |
697 | 0x11, 0x24 /* clr r1 */ | |
8818c391 | 698 | }; |
4e99ad69 TG |
699 | if (len >= sizeof (img) |
700 | && memcmp (prologue, img, sizeof (img)) == 0) | |
2e5ff58c | 701 | { |
4add8633 | 702 | info->prologue_type = AVR_PROLOGUE_INTR; |
2e5ff58c | 703 | vpc += sizeof (img); |
4add8633 TR |
704 | info->saved_regs[AVR_SREG_REGNUM].addr = 3; |
705 | info->saved_regs[0].addr = 2; | |
706 | info->saved_regs[1].addr = 1; | |
707 | info->size += 3; | |
2e5ff58c | 708 | } |
4e99ad69 TG |
709 | else if (len >= sizeof (img) - 2 |
710 | && memcmp (img + 2, prologue, sizeof (img) - 2) == 0) | |
2e5ff58c | 711 | { |
4add8633 TR |
712 | info->prologue_type = AVR_PROLOGUE_SIG; |
713 | vpc += sizeof (img) - 2; | |
714 | info->saved_regs[AVR_SREG_REGNUM].addr = 3; | |
715 | info->saved_regs[0].addr = 2; | |
716 | info->saved_regs[1].addr = 1; | |
243e2c5d | 717 | info->size += 2; |
2e5ff58c | 718 | } |
8818c391 TR |
719 | } |
720 | ||
721 | /* First stage of the prologue scanning. | |
4add8633 | 722 | Scan pushes (saved registers) */ |
8818c391 | 723 | |
4e99ad69 | 724 | for (; vpc < len; vpc += 2) |
8818c391 | 725 | { |
e17a4113 | 726 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c TR |
727 | if ((insn & 0xfe0f) == 0x920f) /* push rXX */ |
728 | { | |
0963b4bd | 729 | /* Bits 4-9 contain a mask for registers R0-R32. */ |
4add8633 TR |
730 | int regno = (insn & 0x1f0) >> 4; |
731 | info->size++; | |
732 | info->saved_regs[regno].addr = info->size; | |
2e5ff58c TR |
733 | scan_stage = 1; |
734 | } | |
8818c391 | 735 | else |
2e5ff58c | 736 | break; |
8818c391 TR |
737 | } |
738 | ||
243e2c5d | 739 | gdb_assert (vpc < AVR_MAX_PROLOGUE_SIZE); |
4add8633 | 740 | |
1bd0bb72 TG |
741 | /* Handle static small stack allocation using rcall or push. */ |
742 | ||
743 | while (scan_stage == 1 && vpc < len) | |
744 | { | |
745 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); | |
746 | if (insn == 0xd000) /* rcall .+0 */ | |
747 | { | |
748 | info->size += gdbarch_tdep (gdbarch)->call_length; | |
749 | vpc += 2; | |
750 | } | |
7588d2ec | 751 | else if (insn == 0x920f || insn == 0x921f) /* push r0 or push r1 */ |
1bd0bb72 TG |
752 | { |
753 | info->size += 1; | |
754 | vpc += 2; | |
755 | } | |
756 | else | |
757 | break; | |
758 | } | |
759 | ||
8818c391 TR |
760 | /* Second stage of the prologue scanning. |
761 | Scan: | |
762 | in r28,__SP_L__ | |
763 | in r29,__SP_H__ */ | |
764 | ||
4e99ad69 | 765 | if (scan_stage == 1 && vpc < len) |
8818c391 | 766 | { |
4e99ad69 | 767 | static const unsigned char img[] = { |
2e5ff58c TR |
768 | 0xcd, 0xb7, /* in r28,__SP_L__ */ |
769 | 0xde, 0xb7 /* in r29,__SP_H__ */ | |
8818c391 | 770 | }; |
2e5ff58c | 771 | |
4e99ad69 TG |
772 | if (vpc + sizeof (img) < len |
773 | && memcmp (prologue + vpc, img, sizeof (img)) == 0) | |
2e5ff58c TR |
774 | { |
775 | vpc += 4; | |
2e5ff58c TR |
776 | scan_stage = 2; |
777 | } | |
8818c391 TR |
778 | } |
779 | ||
0963b4bd | 780 | /* Third stage of the prologue scanning. (Really two stages). |
8818c391 TR |
781 | Scan for: |
782 | sbiw r28,XX or subi r28,lo8(XX) | |
72fab697 | 783 | sbci r29,hi8(XX) |
8818c391 TR |
784 | in __tmp_reg__,__SREG__ |
785 | cli | |
e3d8b004 | 786 | out __SP_H__,r29 |
8818c391 | 787 | out __SREG__,__tmp_reg__ |
e3d8b004 | 788 | out __SP_L__,r28 */ |
8818c391 | 789 | |
4e99ad69 | 790 | if (scan_stage == 2 && vpc < len) |
8818c391 TR |
791 | { |
792 | int locals_size = 0; | |
4e99ad69 | 793 | static const unsigned char img[] = { |
2e5ff58c TR |
794 | 0x0f, 0xb6, /* in r0,0x3f */ |
795 | 0xf8, 0x94, /* cli */ | |
e3d8b004 | 796 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
2e5ff58c | 797 | 0x0f, 0xbe, /* out 0x3f,r0 ; SREG */ |
e3d8b004 | 798 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ |
8818c391 | 799 | }; |
4e99ad69 | 800 | static const unsigned char img_sig[] = { |
e3d8b004 TR |
801 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
802 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ | |
8818c391 | 803 | }; |
4e99ad69 | 804 | static const unsigned char img_int[] = { |
2e5ff58c | 805 | 0xf8, 0x94, /* cli */ |
e3d8b004 | 806 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
2e5ff58c | 807 | 0x78, 0x94, /* sei */ |
e3d8b004 | 808 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ |
8818c391 | 809 | }; |
2e5ff58c | 810 | |
e17a4113 | 811 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c | 812 | if ((insn & 0xff30) == 0x9720) /* sbiw r28,XXX */ |
1bd0bb72 TG |
813 | { |
814 | locals_size = (insn & 0xf) | ((insn & 0xc0) >> 2); | |
815 | vpc += 2; | |
816 | } | |
2e5ff58c TR |
817 | else if ((insn & 0xf0f0) == 0x50c0) /* subi r28,lo8(XX) */ |
818 | { | |
819 | locals_size = (insn & 0xf) | ((insn & 0xf00) >> 4); | |
1bd0bb72 | 820 | vpc += 2; |
e17a4113 | 821 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c | 822 | vpc += 2; |
1bd0bb72 | 823 | locals_size += ((insn & 0xf) | ((insn & 0xf00) >> 4)) << 8; |
2e5ff58c | 824 | } |
8818c391 | 825 | else |
1bd0bb72 | 826 | return pc_beg + vpc; |
4add8633 | 827 | |
0963b4bd | 828 | /* Scan the last part of the prologue. May not be present for interrupt |
4add8633 TR |
829 | or signal handler functions, which is why we set the prologue type |
830 | when we saw the beginning of the prologue previously. */ | |
831 | ||
4e99ad69 TG |
832 | if (vpc + sizeof (img_sig) < len |
833 | && memcmp (prologue + vpc, img_sig, sizeof (img_sig)) == 0) | |
4add8633 TR |
834 | { |
835 | vpc += sizeof (img_sig); | |
836 | } | |
4e99ad69 TG |
837 | else if (vpc + sizeof (img_int) < len |
838 | && memcmp (prologue + vpc, img_int, sizeof (img_int)) == 0) | |
4add8633 TR |
839 | { |
840 | vpc += sizeof (img_int); | |
841 | } | |
4e99ad69 TG |
842 | if (vpc + sizeof (img) < len |
843 | && memcmp (prologue + vpc, img, sizeof (img)) == 0) | |
4add8633 TR |
844 | { |
845 | info->prologue_type = AVR_PROLOGUE_NORMAL; | |
846 | vpc += sizeof (img); | |
847 | } | |
848 | ||
849 | info->size += locals_size; | |
850 | ||
4e99ad69 | 851 | /* Fall through. */ |
8818c391 | 852 | } |
4add8633 TR |
853 | |
854 | /* If we got this far, we could not scan the prologue, so just return the pc | |
855 | of the frame plus an adjustment for argument move insns. */ | |
856 | ||
4e99ad69 TG |
857 | for (; vpc < len; vpc += 2) |
858 | { | |
e17a4113 | 859 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
4e99ad69 TG |
860 | if ((insn & 0xff00) == 0x0100) /* movw rXX, rYY */ |
861 | continue; | |
862 | else if ((insn & 0xfc00) == 0x2c00) /* mov rXX, rYY */ | |
863 | continue; | |
864 | else | |
865 | break; | |
866 | } | |
867 | ||
868 | return pc_beg + vpc; | |
8818c391 TR |
869 | } |
870 | ||
4add8633 | 871 | static CORE_ADDR |
6093d2eb | 872 | avr_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
4add8633 TR |
873 | { |
874 | CORE_ADDR func_addr, func_end; | |
8c201e54 | 875 | CORE_ADDR post_prologue_pc; |
8818c391 | 876 | |
4add8633 | 877 | /* See what the symbol table says */ |
8818c391 | 878 | |
8c201e54 TG |
879 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
880 | return pc; | |
2e5ff58c | 881 | |
8c201e54 TG |
882 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); |
883 | if (post_prologue_pc != 0) | |
884 | return max (pc, post_prologue_pc); | |
8818c391 | 885 | |
8c201e54 TG |
886 | { |
887 | CORE_ADDR prologue_end = pc; | |
888 | struct avr_unwind_cache info = {0}; | |
889 | struct trad_frame_saved_reg saved_regs[AVR_NUM_REGS]; | |
8818c391 | 890 | |
8c201e54 TG |
891 | info.saved_regs = saved_regs; |
892 | ||
893 | /* Need to run the prologue scanner to figure out if the function has a | |
894 | prologue and possibly skip over moving arguments passed via registers | |
895 | to other registers. */ | |
896 | ||
897 | prologue_end = avr_scan_prologue (gdbarch, func_addr, func_end, &info); | |
898 | ||
899 | if (info.prologue_type != AVR_PROLOGUE_NONE) | |
900 | return prologue_end; | |
901 | } | |
2e5ff58c | 902 | |
4e99ad69 TG |
903 | /* Either we didn't find the start of this function (nothing we can do), |
904 | or there's no line info, or the line after the prologue is after | |
0963b4bd | 905 | the end of the function (there probably isn't a prologue). */ |
2e5ff58c | 906 | |
8c201e54 | 907 | return pc; |
4add8633 | 908 | } |
8818c391 | 909 | |
0963b4bd MS |
910 | /* Not all avr devices support the BREAK insn. Those that don't should treat |
911 | it as a NOP. Thus, it should be ok. Since the avr is currently a remote | |
912 | only target, this shouldn't be a problem (I hope). TRoth/2003-05-14 */ | |
8818c391 | 913 | |
4add8633 | 914 | static const unsigned char * |
0963b4bd MS |
915 | avr_breakpoint_from_pc (struct gdbarch *gdbarch, |
916 | CORE_ADDR *pcptr, int *lenptr) | |
4add8633 | 917 | { |
4e99ad69 | 918 | static const unsigned char avr_break_insn [] = { 0x98, 0x95 }; |
4add8633 TR |
919 | *lenptr = sizeof (avr_break_insn); |
920 | return avr_break_insn; | |
8818c391 TR |
921 | } |
922 | ||
4c8b6ae0 UW |
923 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
924 | should be returned. If it is supposed to be returned in registers, | |
925 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
926 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
927 | from WRITEBUF into REGCACHE. */ | |
928 | ||
63807e1d | 929 | static enum return_value_convention |
6a3a010b | 930 | avr_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
931 | struct type *valtype, struct regcache *regcache, |
932 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
4c8b6ae0 | 933 | { |
1bd0bb72 TG |
934 | int i; |
935 | /* Single byte are returned in r24. | |
936 | Otherwise, the MSB of the return value is always in r25, calculate which | |
937 | register holds the LSB. */ | |
938 | int lsb_reg; | |
939 | ||
940 | if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
941 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
942 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
943 | && TYPE_LENGTH (valtype) > 8) | |
944 | return RETURN_VALUE_STRUCT_CONVENTION; | |
945 | ||
946 | if (TYPE_LENGTH (valtype) <= 2) | |
947 | lsb_reg = 24; | |
948 | else if (TYPE_LENGTH (valtype) <= 4) | |
949 | lsb_reg = 22; | |
950 | else if (TYPE_LENGTH (valtype) <= 8) | |
951 | lsb_reg = 18; | |
952 | else | |
f3574227 | 953 | gdb_assert_not_reached ("unexpected type length"); |
4c8b6ae0 UW |
954 | |
955 | if (writebuf != NULL) | |
956 | { | |
1bd0bb72 TG |
957 | for (i = 0; i < TYPE_LENGTH (valtype); i++) |
958 | regcache_cooked_write (regcache, lsb_reg + i, writebuf + i); | |
4c8b6ae0 UW |
959 | } |
960 | ||
961 | if (readbuf != NULL) | |
962 | { | |
1bd0bb72 TG |
963 | for (i = 0; i < TYPE_LENGTH (valtype); i++) |
964 | regcache_cooked_read (regcache, lsb_reg + i, readbuf + i); | |
4c8b6ae0 UW |
965 | } |
966 | ||
1bd0bb72 | 967 | return RETURN_VALUE_REGISTER_CONVENTION; |
4c8b6ae0 UW |
968 | } |
969 | ||
970 | ||
4add8633 TR |
971 | /* Put here the code to store, into fi->saved_regs, the addresses of |
972 | the saved registers of frame described by FRAME_INFO. This | |
973 | includes special registers such as pc and fp saved in special ways | |
974 | in the stack frame. sp is even more special: the address we return | |
0963b4bd | 975 | for it IS the sp for the next frame. */ |
8818c391 | 976 | |
63807e1d | 977 | static struct avr_unwind_cache * |
94afd7a6 | 978 | avr_frame_unwind_cache (struct frame_info *this_frame, |
4add8633 | 979 | void **this_prologue_cache) |
8818c391 | 980 | { |
4e99ad69 | 981 | CORE_ADDR start_pc, current_pc; |
4add8633 TR |
982 | ULONGEST prev_sp; |
983 | ULONGEST this_base; | |
984 | struct avr_unwind_cache *info; | |
4e99ad69 TG |
985 | struct gdbarch *gdbarch; |
986 | struct gdbarch_tdep *tdep; | |
4add8633 TR |
987 | int i; |
988 | ||
4e99ad69 TG |
989 | if (*this_prologue_cache) |
990 | return *this_prologue_cache; | |
4add8633 TR |
991 | |
992 | info = FRAME_OBSTACK_ZALLOC (struct avr_unwind_cache); | |
4e99ad69 | 993 | *this_prologue_cache = info; |
94afd7a6 | 994 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
4add8633 TR |
995 | |
996 | info->size = 0; | |
997 | info->prologue_type = AVR_PROLOGUE_NONE; | |
998 | ||
4e99ad69 TG |
999 | start_pc = get_frame_func (this_frame); |
1000 | current_pc = get_frame_pc (this_frame); | |
1001 | if ((start_pc > 0) && (start_pc <= current_pc)) | |
e17a4113 UW |
1002 | avr_scan_prologue (get_frame_arch (this_frame), |
1003 | start_pc, current_pc, info); | |
4add8633 | 1004 | |
3b85b0f1 TR |
1005 | if ((info->prologue_type != AVR_PROLOGUE_NONE) |
1006 | && (info->prologue_type != AVR_PROLOGUE_MAIN)) | |
4add8633 TR |
1007 | { |
1008 | ULONGEST high_base; /* High byte of FP */ | |
1009 | ||
1010 | /* The SP was moved to the FP. This indicates that a new frame | |
1011 | was created. Get THIS frame's FP value by unwinding it from | |
1012 | the next frame. */ | |
94afd7a6 | 1013 | this_base = get_frame_register_unsigned (this_frame, AVR_FP_REGNUM); |
4e99ad69 | 1014 | high_base = get_frame_register_unsigned (this_frame, AVR_FP_REGNUM + 1); |
4add8633 TR |
1015 | this_base += (high_base << 8); |
1016 | ||
1017 | /* The FP points at the last saved register. Adjust the FP back | |
1018 | to before the first saved register giving the SP. */ | |
1019 | prev_sp = this_base + info->size; | |
1020 | } | |
8818c391 | 1021 | else |
4add8633 TR |
1022 | { |
1023 | /* Assume that the FP is this frame's SP but with that pushed | |
1024 | stack space added back. */ | |
94afd7a6 | 1025 | this_base = get_frame_register_unsigned (this_frame, AVR_SP_REGNUM); |
4add8633 TR |
1026 | prev_sp = this_base + info->size; |
1027 | } | |
1028 | ||
1029 | /* Add 1 here to adjust for the post-decrement nature of the push | |
1030 | instruction.*/ | |
4e99ad69 | 1031 | info->prev_sp = avr_make_saddr (prev_sp + 1); |
4add8633 TR |
1032 | info->base = avr_make_saddr (this_base); |
1033 | ||
4e99ad69 TG |
1034 | gdbarch = get_frame_arch (this_frame); |
1035 | ||
4add8633 | 1036 | /* Adjust all the saved registers so that they contain addresses and not |
3b85b0f1 | 1037 | offsets. */ |
4e99ad69 TG |
1038 | for (i = 0; i < gdbarch_num_regs (gdbarch) - 1; i++) |
1039 | if (info->saved_regs[i].addr > 0) | |
1040 | info->saved_regs[i].addr = info->prev_sp - info->saved_regs[i].addr; | |
4add8633 TR |
1041 | |
1042 | /* Except for the main and startup code, the return PC is always saved on | |
0963b4bd | 1043 | the stack and is at the base of the frame. */ |
4add8633 TR |
1044 | |
1045 | if (info->prologue_type != AVR_PROLOGUE_MAIN) | |
4e99ad69 | 1046 | info->saved_regs[AVR_PC_REGNUM].addr = info->prev_sp; |
4add8633 | 1047 | |
3b85b0f1 TR |
1048 | /* The previous frame's SP needed to be computed. Save the computed |
1049 | value. */ | |
4e99ad69 TG |
1050 | tdep = gdbarch_tdep (gdbarch); |
1051 | trad_frame_set_value (info->saved_regs, AVR_SP_REGNUM, | |
1052 | info->prev_sp - 1 + tdep->call_length); | |
3b85b0f1 | 1053 | |
4add8633 | 1054 | return info; |
8818c391 TR |
1055 | } |
1056 | ||
1057 | static CORE_ADDR | |
4add8633 | 1058 | avr_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
8818c391 | 1059 | { |
4add8633 TR |
1060 | ULONGEST pc; |
1061 | ||
11411de3 | 1062 | pc = frame_unwind_register_unsigned (next_frame, AVR_PC_REGNUM); |
4add8633 TR |
1063 | |
1064 | return avr_make_iaddr (pc); | |
8818c391 TR |
1065 | } |
1066 | ||
30244cd8 UW |
1067 | static CORE_ADDR |
1068 | avr_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1069 | { | |
1070 | ULONGEST sp; | |
1071 | ||
11411de3 | 1072 | sp = frame_unwind_register_unsigned (next_frame, AVR_SP_REGNUM); |
30244cd8 UW |
1073 | |
1074 | return avr_make_saddr (sp); | |
1075 | } | |
1076 | ||
4add8633 TR |
1077 | /* Given a GDB frame, determine the address of the calling function's |
1078 | frame. This will be used to create a new GDB frame struct. */ | |
8818c391 | 1079 | |
4add8633 | 1080 | static void |
94afd7a6 | 1081 | avr_frame_this_id (struct frame_info *this_frame, |
4add8633 TR |
1082 | void **this_prologue_cache, |
1083 | struct frame_id *this_id) | |
8818c391 | 1084 | { |
4add8633 | 1085 | struct avr_unwind_cache *info |
94afd7a6 | 1086 | = avr_frame_unwind_cache (this_frame, this_prologue_cache); |
4add8633 TR |
1087 | CORE_ADDR base; |
1088 | CORE_ADDR func; | |
1089 | struct frame_id id; | |
1090 | ||
1091 | /* The FUNC is easy. */ | |
94afd7a6 | 1092 | func = get_frame_func (this_frame); |
4add8633 | 1093 | |
4add8633 TR |
1094 | /* Hopefully the prologue analysis either correctly determined the |
1095 | frame's base (which is the SP from the previous frame), or set | |
1096 | that base to "NULL". */ | |
1097 | base = info->prev_sp; | |
1098 | if (base == 0) | |
1099 | return; | |
1100 | ||
1101 | id = frame_id_build (base, func); | |
4add8633 | 1102 | (*this_id) = id; |
8818c391 TR |
1103 | } |
1104 | ||
94afd7a6 UW |
1105 | static struct value * |
1106 | avr_frame_prev_register (struct frame_info *this_frame, | |
4e99ad69 | 1107 | void **this_prologue_cache, int regnum) |
8818c391 | 1108 | { |
e17a4113 UW |
1109 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1110 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4add8633 | 1111 | struct avr_unwind_cache *info |
94afd7a6 | 1112 | = avr_frame_unwind_cache (this_frame, this_prologue_cache); |
8818c391 | 1113 | |
7d2552b4 | 1114 | if (regnum == AVR_PC_REGNUM || regnum == AVR_PSEUDO_PC_REGNUM) |
3b85b0f1 | 1115 | { |
7d2552b4 | 1116 | if (trad_frame_addr_p (info->saved_regs, AVR_PC_REGNUM)) |
3b85b0f1 | 1117 | { |
94afd7a6 UW |
1118 | /* Reading the return PC from the PC register is slightly |
1119 | abnormal. register_size(AVR_PC_REGNUM) says it is 4 bytes, | |
1120 | but in reality, only two bytes (3 in upcoming mega256) are | |
1121 | stored on the stack. | |
1122 | ||
1123 | Also, note that the value on the stack is an addr to a word | |
1124 | not a byte, so we will need to multiply it by two at some | |
1125 | point. | |
1126 | ||
1127 | And to confuse matters even more, the return address stored | |
1128 | on the stack is in big endian byte order, even though most | |
0963b4bd | 1129 | everything else about the avr is little endian. Ick! */ |
94afd7a6 | 1130 | ULONGEST pc; |
4e99ad69 | 1131 | int i; |
e362b510 | 1132 | gdb_byte buf[3]; |
4e99ad69 TG |
1133 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1134 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
94afd7a6 | 1135 | |
7d2552b4 TG |
1136 | read_memory (info->saved_regs[AVR_PC_REGNUM].addr, |
1137 | buf, tdep->call_length); | |
94afd7a6 | 1138 | |
4e99ad69 TG |
1139 | /* Extract the PC read from memory as a big-endian. */ |
1140 | pc = 0; | |
1141 | for (i = 0; i < tdep->call_length; i++) | |
1142 | pc = (pc << 8) | buf[i]; | |
94afd7a6 | 1143 | |
7d2552b4 TG |
1144 | if (regnum == AVR_PC_REGNUM) |
1145 | pc <<= 1; | |
1146 | ||
1147 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
3b85b0f1 | 1148 | } |
94afd7a6 UW |
1149 | |
1150 | return frame_unwind_got_optimized (this_frame, regnum); | |
3b85b0f1 | 1151 | } |
94afd7a6 UW |
1152 | |
1153 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
4add8633 | 1154 | } |
8818c391 | 1155 | |
4add8633 TR |
1156 | static const struct frame_unwind avr_frame_unwind = { |
1157 | NORMAL_FRAME, | |
8fbca658 | 1158 | default_frame_unwind_stop_reason, |
4add8633 | 1159 | avr_frame_this_id, |
94afd7a6 UW |
1160 | avr_frame_prev_register, |
1161 | NULL, | |
1162 | default_frame_sniffer | |
4add8633 TR |
1163 | }; |
1164 | ||
8818c391 | 1165 | static CORE_ADDR |
94afd7a6 | 1166 | avr_frame_base_address (struct frame_info *this_frame, void **this_cache) |
8818c391 | 1167 | { |
4add8633 | 1168 | struct avr_unwind_cache *info |
94afd7a6 | 1169 | = avr_frame_unwind_cache (this_frame, this_cache); |
8818c391 | 1170 | |
4add8633 TR |
1171 | return info->base; |
1172 | } | |
8818c391 | 1173 | |
4add8633 TR |
1174 | static const struct frame_base avr_frame_base = { |
1175 | &avr_frame_unwind, | |
1176 | avr_frame_base_address, | |
1177 | avr_frame_base_address, | |
1178 | avr_frame_base_address | |
1179 | }; | |
ced15480 | 1180 | |
94afd7a6 UW |
1181 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
1182 | frame. The frame ID's base needs to match the TOS value saved by | |
1183 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
8818c391 | 1184 | |
4add8633 | 1185 | static struct frame_id |
94afd7a6 | 1186 | avr_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
4add8633 TR |
1187 | { |
1188 | ULONGEST base; | |
8818c391 | 1189 | |
94afd7a6 UW |
1190 | base = get_frame_register_unsigned (this_frame, AVR_SP_REGNUM); |
1191 | return frame_id_build (avr_make_saddr (base), get_frame_pc (this_frame)); | |
8818c391 TR |
1192 | } |
1193 | ||
4add8633 | 1194 | /* When arguments must be pushed onto the stack, they go on in reverse |
0963b4bd | 1195 | order. The below implements a FILO (stack) to do this. */ |
8818c391 | 1196 | |
4add8633 TR |
1197 | struct stack_item |
1198 | { | |
1199 | int len; | |
1200 | struct stack_item *prev; | |
1201 | void *data; | |
1202 | }; | |
8818c391 | 1203 | |
4add8633 | 1204 | static struct stack_item * |
0fd88904 | 1205 | push_stack_item (struct stack_item *prev, const bfd_byte *contents, int len) |
8818c391 | 1206 | { |
4add8633 TR |
1207 | struct stack_item *si; |
1208 | si = xmalloc (sizeof (struct stack_item)); | |
1209 | si->data = xmalloc (len); | |
1210 | si->len = len; | |
1211 | si->prev = prev; | |
1212 | memcpy (si->data, contents, len); | |
1213 | return si; | |
8818c391 TR |
1214 | } |
1215 | ||
4add8633 TR |
1216 | static struct stack_item *pop_stack_item (struct stack_item *si); |
1217 | static struct stack_item * | |
1218 | pop_stack_item (struct stack_item *si) | |
8818c391 | 1219 | { |
4add8633 TR |
1220 | struct stack_item *dead = si; |
1221 | si = si->prev; | |
1222 | xfree (dead->data); | |
1223 | xfree (dead); | |
1224 | return si; | |
8818c391 TR |
1225 | } |
1226 | ||
8818c391 TR |
1227 | /* Setup the function arguments for calling a function in the inferior. |
1228 | ||
1229 | On the AVR architecture, there are 18 registers (R25 to R8) which are | |
1230 | dedicated for passing function arguments. Up to the first 18 arguments | |
1231 | (depending on size) may go into these registers. The rest go on the stack. | |
1232 | ||
4add8633 | 1233 | All arguments are aligned to start in even-numbered registers (odd-sized |
0963b4bd | 1234 | arguments, including char, have one free register above them). For example, |
4add8633 TR |
1235 | an int in arg1 and a char in arg2 would be passed as such: |
1236 | ||
1237 | arg1 -> r25:r24 | |
1238 | arg2 -> r22 | |
1239 | ||
1240 | Arguments that are larger than 2 bytes will be split between two or more | |
1241 | registers as available, but will NOT be split between a register and the | |
0963b4bd | 1242 | stack. Arguments that go onto the stack are pushed last arg first (this is |
4add8633 TR |
1243 | similar to the d10v). */ |
1244 | ||
1245 | /* NOTE: TRoth/2003-06-17: The rest of this comment is old looks to be | |
1246 | inaccurate. | |
8818c391 TR |
1247 | |
1248 | An exceptional case exists for struct arguments (and possibly other | |
1249 | aggregates such as arrays) -- if the size is larger than WORDSIZE bytes but | |
1250 | not a multiple of WORDSIZE bytes. In this case the argument is never split | |
1251 | between the registers and the stack, but instead is copied in its entirety | |
1252 | onto the stack, AND also copied into as many registers as there is room | |
1253 | for. In other words, space in registers permitting, two copies of the same | |
1254 | argument are passed in. As far as I can tell, only the one on the stack is | |
1255 | used, although that may be a function of the level of compiler | |
1256 | optimization. I suspect this is a compiler bug. Arguments of these odd | |
1257 | sizes are left-justified within the word (as opposed to arguments smaller | |
1258 | than WORDSIZE bytes, which are right-justified). | |
1259 | ||
1260 | If the function is to return an aggregate type such as a struct, the caller | |
1261 | must allocate space into which the callee will copy the return value. In | |
1262 | this case, a pointer to the return value location is passed into the callee | |
1263 | in register R0, which displaces one of the other arguments passed in via | |
0963b4bd | 1264 | registers R0 to R2. */ |
8818c391 TR |
1265 | |
1266 | static CORE_ADDR | |
7d9b040b | 1267 | avr_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
4add8633 TR |
1268 | struct regcache *regcache, CORE_ADDR bp_addr, |
1269 | int nargs, struct value **args, CORE_ADDR sp, | |
1270 | int struct_return, CORE_ADDR struct_addr) | |
8818c391 | 1271 | { |
e17a4113 | 1272 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4add8633 | 1273 | int i; |
e362b510 | 1274 | gdb_byte buf[3]; |
6d1915d4 | 1275 | int call_length = gdbarch_tdep (gdbarch)->call_length; |
4add8633 TR |
1276 | CORE_ADDR return_pc = avr_convert_iaddr_to_raw (bp_addr); |
1277 | int regnum = AVR_ARGN_REGNUM; | |
1278 | struct stack_item *si = NULL; | |
8818c391 | 1279 | |
4add8633 | 1280 | if (struct_return) |
8818c391 | 1281 | { |
fd6d6815 TG |
1282 | regcache_cooked_write_unsigned |
1283 | (regcache, regnum--, (struct_addr >> 8) & 0xff); | |
1284 | regcache_cooked_write_unsigned | |
1285 | (regcache, regnum--, struct_addr & 0xff); | |
1286 | /* SP being post decremented, we need to reserve one byte so that the | |
1287 | return address won't overwrite the result (or vice-versa). */ | |
1288 | if (sp == struct_addr) | |
1289 | sp--; | |
8818c391 TR |
1290 | } |
1291 | ||
4add8633 | 1292 | for (i = 0; i < nargs; i++) |
8818c391 | 1293 | { |
4add8633 TR |
1294 | int last_regnum; |
1295 | int j; | |
1296 | struct value *arg = args[i]; | |
4991999e | 1297 | struct type *type = check_typedef (value_type (arg)); |
0fd88904 | 1298 | const bfd_byte *contents = value_contents (arg); |
4add8633 TR |
1299 | int len = TYPE_LENGTH (type); |
1300 | ||
0963b4bd | 1301 | /* Calculate the potential last register needed. */ |
4add8633 TR |
1302 | last_regnum = regnum - (len + (len & 1)); |
1303 | ||
0963b4bd MS |
1304 | /* If there are registers available, use them. Once we start putting |
1305 | stuff on the stack, all subsequent args go on stack. */ | |
4add8633 TR |
1306 | if ((si == NULL) && (last_regnum >= 8)) |
1307 | { | |
1308 | ULONGEST val; | |
1309 | ||
0963b4bd | 1310 | /* Skip a register for odd length args. */ |
4add8633 TR |
1311 | if (len & 1) |
1312 | regnum--; | |
1313 | ||
e17a4113 | 1314 | val = extract_unsigned_integer (contents, len, byte_order); |
6d1915d4 TG |
1315 | for (j = 0; j < len; j++) |
1316 | regcache_cooked_write_unsigned | |
1317 | (regcache, regnum--, val >> (8 * (len - j - 1))); | |
4add8633 | 1318 | } |
0963b4bd | 1319 | /* No registers available, push the args onto the stack. */ |
4add8633 TR |
1320 | else |
1321 | { | |
0963b4bd | 1322 | /* From here on, we don't care about regnum. */ |
4add8633 TR |
1323 | si = push_stack_item (si, contents, len); |
1324 | } | |
8818c391 | 1325 | } |
909cd28e | 1326 | |
0963b4bd | 1327 | /* Push args onto the stack. */ |
4add8633 TR |
1328 | while (si) |
1329 | { | |
1330 | sp -= si->len; | |
0963b4bd | 1331 | /* Add 1 to sp here to account for post decr nature of pushes. */ |
4e99ad69 | 1332 | write_memory (sp + 1, si->data, si->len); |
4add8633 TR |
1333 | si = pop_stack_item (si); |
1334 | } | |
3605c34a | 1335 | |
4add8633 TR |
1336 | /* Set the return address. For the avr, the return address is the BP_ADDR. |
1337 | Need to push the return address onto the stack noting that it needs to be | |
1338 | in big-endian order on the stack. */ | |
6d1915d4 TG |
1339 | for (i = 1; i <= call_length; i++) |
1340 | { | |
1341 | buf[call_length - i] = return_pc & 0xff; | |
1342 | return_pc >>= 8; | |
1343 | } | |
3605c34a | 1344 | |
6d1915d4 | 1345 | sp -= call_length; |
0963b4bd | 1346 | /* Use 'sp + 1' since pushes are post decr ops. */ |
6d1915d4 | 1347 | write_memory (sp + 1, buf, call_length); |
3605c34a | 1348 | |
0963b4bd | 1349 | /* Finally, update the SP register. */ |
4add8633 TR |
1350 | regcache_cooked_write_unsigned (regcache, AVR_SP_REGNUM, |
1351 | avr_convert_saddr_to_raw (sp)); | |
3605c34a | 1352 | |
6d1915d4 TG |
1353 | /* Return SP value for the dummy frame, where the return address hasn't been |
1354 | pushed. */ | |
1355 | return sp + call_length; | |
3605c34a TR |
1356 | } |
1357 | ||
53f6a2c9 TG |
1358 | /* Unfortunately dwarf2 register for SP is 32. */ |
1359 | ||
1360 | static int | |
1361 | avr_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1362 | { | |
1363 | if (reg >= 0 && reg < 32) | |
1364 | return reg; | |
1365 | if (reg == 32) | |
1366 | return AVR_SP_REGNUM; | |
1367 | ||
1368 | warning (_("Unmapped DWARF Register #%d encountered."), reg); | |
1369 | ||
1370 | return -1; | |
1371 | } | |
1372 | ||
487d9753 PL |
1373 | /* Implementation of `address_class_type_flags' gdbarch method. |
1374 | ||
1375 | This method maps DW_AT_address_class attributes to a | |
1376 | type_instance_flag_value. */ | |
1377 | ||
1378 | static int | |
1379 | avr_address_class_type_flags (int byte_size, int dwarf2_addr_class) | |
1380 | { | |
1381 | /* The value 1 of the DW_AT_address_class attribute corresponds to the | |
1382 | __flash qualifier. Note that this attribute is only valid with | |
1383 | pointer types and therefore the flag is set to the pointer type and | |
1384 | not its target type. */ | |
1385 | if (dwarf2_addr_class == 1 && byte_size == 2) | |
1386 | return AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | /* Implementation of `address_class_type_flags_to_name' gdbarch method. | |
1391 | ||
1392 | Convert a type_instance_flag_value to an address space qualifier. */ | |
1393 | ||
1394 | static const char* | |
1395 | avr_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags) | |
1396 | { | |
1397 | if (type_flags & AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH) | |
1398 | return "flash"; | |
1399 | else | |
1400 | return NULL; | |
1401 | } | |
1402 | ||
1403 | /* Implementation of `address_class_name_to_type_flags' gdbarch method. | |
1404 | ||
1405 | Convert an address space qualifier to a type_instance_flag_value. */ | |
1406 | ||
1407 | static int | |
1408 | avr_address_class_name_to_type_flags (struct gdbarch *gdbarch, | |
1409 | const char* name, | |
1410 | int *type_flags_ptr) | |
1411 | { | |
1412 | if (strcmp (name, "flash") == 0) | |
1413 | { | |
1414 | *type_flags_ptr = AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; | |
1415 | return 1; | |
1416 | } | |
1417 | else | |
1418 | return 0; | |
1419 | } | |
1420 | ||
0963b4bd | 1421 | /* Initialize the gdbarch structure for the AVR's. */ |
8818c391 TR |
1422 | |
1423 | static struct gdbarch * | |
2e5ff58c TR |
1424 | avr_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
1425 | { | |
2e5ff58c TR |
1426 | struct gdbarch *gdbarch; |
1427 | struct gdbarch_tdep *tdep; | |
4e99ad69 TG |
1428 | struct gdbarch_list *best_arch; |
1429 | int call_length; | |
8818c391 | 1430 | |
4e99ad69 | 1431 | /* Avr-6 call instructions save 3 bytes. */ |
8818c391 TR |
1432 | switch (info.bfd_arch_info->mach) |
1433 | { | |
1434 | case bfd_mach_avr1: | |
9c97a070 | 1435 | case bfd_mach_avrxmega1: |
8818c391 | 1436 | case bfd_mach_avr2: |
9c97a070 | 1437 | case bfd_mach_avrxmega2: |
8818c391 | 1438 | case bfd_mach_avr3: |
9c97a070 | 1439 | case bfd_mach_avrxmega3: |
8818c391 | 1440 | case bfd_mach_avr4: |
9c97a070 | 1441 | case bfd_mach_avrxmega4: |
8818c391 | 1442 | case bfd_mach_avr5: |
9c97a070 | 1443 | case bfd_mach_avrxmega5: |
4e99ad69 TG |
1444 | default: |
1445 | call_length = 2; | |
1446 | break; | |
1447 | case bfd_mach_avr6: | |
9c97a070 PL |
1448 | case bfd_mach_avrxmega6: |
1449 | case bfd_mach_avrxmega7: | |
4e99ad69 | 1450 | call_length = 3; |
8818c391 TR |
1451 | break; |
1452 | } | |
1453 | ||
4e99ad69 TG |
1454 | /* If there is already a candidate, use it. */ |
1455 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
1456 | best_arch != NULL; | |
1457 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
1458 | { | |
1459 | if (gdbarch_tdep (best_arch->gdbarch)->call_length == call_length) | |
1460 | return best_arch->gdbarch; | |
1461 | } | |
1462 | ||
0963b4bd | 1463 | /* None found, create a new architecture from the information provided. */ |
70ba0933 | 1464 | tdep = XNEW (struct gdbarch_tdep); |
4e99ad69 TG |
1465 | gdbarch = gdbarch_alloc (&info, tdep); |
1466 | ||
1467 | tdep->call_length = call_length; | |
1468 | ||
7d2552b4 TG |
1469 | /* Create a type for PC. We can't use builtin types here, as they may not |
1470 | be defined. */ | |
1471 | tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void"); | |
1472 | tdep->func_void_type = make_function_type (tdep->void_type, NULL); | |
1473 | tdep->pc_type = arch_type (gdbarch, TYPE_CODE_PTR, 4, NULL); | |
1474 | TYPE_TARGET_TYPE (tdep->pc_type) = tdep->func_void_type; | |
1475 | TYPE_UNSIGNED (tdep->pc_type) = 1; | |
1476 | ||
8818c391 TR |
1477 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1478 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1479 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1480 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
1481 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1482 | set_gdbarch_addr_bit (gdbarch, 32); | |
8818c391 TR |
1483 | |
1484 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1485 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1486 | set_gdbarch_long_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1487 | ||
8da61cc4 DJ |
1488 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
1489 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); | |
1490 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_single); | |
8818c391 TR |
1491 | |
1492 | set_gdbarch_read_pc (gdbarch, avr_read_pc); | |
1493 | set_gdbarch_write_pc (gdbarch, avr_write_pc); | |
8818c391 TR |
1494 | |
1495 | set_gdbarch_num_regs (gdbarch, AVR_NUM_REGS); | |
1496 | ||
1497 | set_gdbarch_sp_regnum (gdbarch, AVR_SP_REGNUM); | |
8818c391 TR |
1498 | set_gdbarch_pc_regnum (gdbarch, AVR_PC_REGNUM); |
1499 | ||
1500 | set_gdbarch_register_name (gdbarch, avr_register_name); | |
866b76ea | 1501 | set_gdbarch_register_type (gdbarch, avr_register_type); |
8818c391 | 1502 | |
7d2552b4 TG |
1503 | set_gdbarch_num_pseudo_regs (gdbarch, AVR_NUM_PSEUDO_REGS); |
1504 | set_gdbarch_pseudo_register_read (gdbarch, avr_pseudo_register_read); | |
1505 | set_gdbarch_pseudo_register_write (gdbarch, avr_pseudo_register_write); | |
1506 | ||
4c8b6ae0 | 1507 | set_gdbarch_return_value (gdbarch, avr_return_value); |
8818c391 TR |
1508 | set_gdbarch_print_insn (gdbarch, print_insn_avr); |
1509 | ||
4add8633 | 1510 | set_gdbarch_push_dummy_call (gdbarch, avr_push_dummy_call); |
8818c391 | 1511 | |
53f6a2c9 TG |
1512 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, avr_dwarf_reg_to_regnum); |
1513 | ||
8818c391 TR |
1514 | set_gdbarch_address_to_pointer (gdbarch, avr_address_to_pointer); |
1515 | set_gdbarch_pointer_to_address (gdbarch, avr_pointer_to_address); | |
8a1d23b2 | 1516 | set_gdbarch_integer_to_address (gdbarch, avr_integer_to_address); |
8818c391 | 1517 | |
8818c391 | 1518 | set_gdbarch_skip_prologue (gdbarch, avr_skip_prologue); |
8818c391 TR |
1519 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
1520 | ||
909cd28e | 1521 | set_gdbarch_breakpoint_from_pc (gdbarch, avr_breakpoint_from_pc); |
8818c391 | 1522 | |
94afd7a6 | 1523 | frame_unwind_append_unwinder (gdbarch, &avr_frame_unwind); |
4add8633 TR |
1524 | frame_base_set_default (gdbarch, &avr_frame_base); |
1525 | ||
94afd7a6 | 1526 | set_gdbarch_dummy_id (gdbarch, avr_dummy_id); |
4add8633 TR |
1527 | |
1528 | set_gdbarch_unwind_pc (gdbarch, avr_unwind_pc); | |
30244cd8 | 1529 | set_gdbarch_unwind_sp (gdbarch, avr_unwind_sp); |
8818c391 | 1530 | |
487d9753 PL |
1531 | set_gdbarch_address_class_type_flags (gdbarch, avr_address_class_type_flags); |
1532 | set_gdbarch_address_class_name_to_type_flags | |
1533 | (gdbarch, avr_address_class_name_to_type_flags); | |
1534 | set_gdbarch_address_class_type_flags_to_name | |
1535 | (gdbarch, avr_address_class_type_flags_to_name); | |
1536 | ||
8818c391 TR |
1537 | return gdbarch; |
1538 | } | |
1539 | ||
1540 | /* Send a query request to the avr remote target asking for values of the io | |
0963b4bd | 1541 | registers. If args parameter is not NULL, then the user has requested info |
8818c391 | 1542 | on a specific io register [This still needs implemented and is ignored for |
0963b4bd | 1543 | now]. The query string should be one of these forms: |
8818c391 TR |
1544 | |
1545 | "Ravr.io_reg" -> reply is "NN" number of io registers | |
1546 | ||
1547 | "Ravr.io_reg:addr,len" where addr is first register and len is number of | |
0963b4bd | 1548 | registers to be read. The reply should be "<NAME>,VV;" for each io register |
8818c391 TR |
1549 | where, <NAME> is a string, and VV is the hex value of the register. |
1550 | ||
0963b4bd | 1551 | All io registers are 8-bit. */ |
8818c391 TR |
1552 | |
1553 | static void | |
1554 | avr_io_reg_read_command (char *args, int from_tty) | |
1555 | { | |
1e3ff5ad | 1556 | LONGEST bufsiz = 0; |
13547ab6 | 1557 | gdb_byte *buf; |
001f13d8 | 1558 | const char *bufstr; |
2e5ff58c | 1559 | char query[400]; |
001f13d8 | 1560 | const char *p; |
2e5ff58c TR |
1561 | unsigned int nreg = 0; |
1562 | unsigned int val; | |
1563 | int i, j, k, step; | |
8818c391 | 1564 | |
0963b4bd | 1565 | /* Find out how many io registers the target has. */ |
13547ab6 DJ |
1566 | bufsiz = target_read_alloc (¤t_target, TARGET_OBJECT_AVR, |
1567 | "avr.io_reg", &buf); | |
001f13d8 | 1568 | bufstr = (const char *) buf; |
8818c391 | 1569 | |
13547ab6 | 1570 | if (bufsiz <= 0) |
8818c391 | 1571 | { |
2e5ff58c | 1572 | fprintf_unfiltered (gdb_stderr, |
13547ab6 DJ |
1573 | _("ERR: info io_registers NOT supported " |
1574 | "by current target\n")); | |
8818c391 TR |
1575 | return; |
1576 | } | |
1577 | ||
001f13d8 | 1578 | if (sscanf (bufstr, "%x", &nreg) != 1) |
8818c391 | 1579 | { |
2e5ff58c | 1580 | fprintf_unfiltered (gdb_stderr, |
edefbb7c | 1581 | _("Error fetching number of io registers\n")); |
13547ab6 | 1582 | xfree (buf); |
8818c391 TR |
1583 | return; |
1584 | } | |
1585 | ||
13547ab6 DJ |
1586 | xfree (buf); |
1587 | ||
2e5ff58c | 1588 | reinitialize_more_filter (); |
8818c391 | 1589 | |
edefbb7c | 1590 | printf_unfiltered (_("Target has %u io registers:\n\n"), nreg); |
8818c391 TR |
1591 | |
1592 | /* only fetch up to 8 registers at a time to keep the buffer small */ | |
1593 | step = 8; | |
1594 | ||
2e5ff58c | 1595 | for (i = 0; i < nreg; i += step) |
8818c391 | 1596 | { |
91ccbfc1 TR |
1597 | /* how many registers this round? */ |
1598 | j = step; | |
1599 | if ((i+j) >= nreg) | |
1600 | j = nreg - i; /* last block is less than 8 registers */ | |
8818c391 | 1601 | |
2e5ff58c | 1602 | snprintf (query, sizeof (query) - 1, "avr.io_reg:%x,%x", i, j); |
13547ab6 DJ |
1603 | bufsiz = target_read_alloc (¤t_target, TARGET_OBJECT_AVR, |
1604 | query, &buf); | |
8818c391 | 1605 | |
001f13d8 | 1606 | p = (const char *) buf; |
2e5ff58c TR |
1607 | for (k = i; k < (i + j); k++) |
1608 | { | |
1609 | if (sscanf (p, "%[^,],%x;", query, &val) == 2) | |
1610 | { | |
1611 | printf_filtered ("[%02x] %-15s : %02x\n", k, query, val); | |
1612 | while ((*p != ';') && (*p != '\0')) | |
1613 | p++; | |
1614 | p++; /* skip over ';' */ | |
1615 | if (*p == '\0') | |
1616 | break; | |
1617 | } | |
1618 | } | |
13547ab6 DJ |
1619 | |
1620 | xfree (buf); | |
8818c391 TR |
1621 | } |
1622 | } | |
1623 | ||
a78f21af AC |
1624 | extern initialize_file_ftype _initialize_avr_tdep; /* -Wmissing-prototypes */ |
1625 | ||
8818c391 TR |
1626 | void |
1627 | _initialize_avr_tdep (void) | |
1628 | { | |
1629 | register_gdbarch_init (bfd_arch_avr, avr_gdbarch_init); | |
1630 | ||
1631 | /* Add a new command to allow the user to query the avr remote target for | |
1632 | the values of the io space registers in a saner way than just using | |
0963b4bd | 1633 | `x/NNNb ADDR`. */ |
8818c391 TR |
1634 | |
1635 | /* FIXME: TRoth/2002-02-18: This should probably be changed to 'info avr | |
0963b4bd | 1636 | io_registers' to signify it is not available on other platforms. */ |
8818c391 TR |
1637 | |
1638 | add_cmd ("io_registers", class_info, avr_io_reg_read_command, | |
1a966eab AC |
1639 | _("query remote avr target for io space register values"), |
1640 | &infolist); | |
8818c391 | 1641 | } |