[deliverable/binutils-gdb.git] / gdb / common / i386-gcc-cpuid.h

/*
 * Helper cpuid.h file copied from gcc-4.8.0.  Code in gdb should not
 * include this directly, but pull in i386-cpuid.h and use that func.
 */
/*
 * Copyright (C) 2007-2013 Free Software Foundation, Inc.
 *
 * This file is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 3, or (at your option) any
 * later version.
 * 
 * This file is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * 
 * Under Section 7 of GPL version 3, you are granted additional
 * permissions described in the GCC Runtime Library Exception, version
 * 3.1, as published by the Free Software Foundation.
 * 
 * You should have received a copy of the GNU General Public License and
 * a copy of the GCC Runtime Library Exception along with this program;
 * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 * <http://www.gnu.org/licenses/>.
 */

/* %ecx */
#define bit_SSE3	(1 << 0)
#define bit_PCLMUL	(1 << 1)
#define bit_LZCNT	(1 << 5)
#define bit_SSSE3	(1 << 9)
#define bit_FMA		(1 << 12)
#define bit_CMPXCHG16B	(1 << 13)
#define bit_SSE4_1	(1 << 19)
#define bit_SSE4_2	(1 << 20)
#define bit_MOVBE	(1 << 22)
#define bit_POPCNT	(1 << 23)
#define bit_AES		(1 << 25)
#define bit_XSAVE	(1 << 26)
#define bit_OSXSAVE	(1 << 27)
#define bit_AVX		(1 << 28)
#define bit_F16C	(1 << 29)
#define bit_RDRND	(1 << 30)

/* %edx */
#define bit_CMPXCHG8B	(1 << 8)
#define bit_CMOV	(1 << 15)
#define bit_MMX		(1 << 23)
#define bit_FXSAVE	(1 << 24)
#define bit_SSE		(1 << 25)
#define bit_SSE2	(1 << 26)

/* Extended Features */
/* %ecx */
#define bit_LAHF_LM	(1 << 0)
#define bit_ABM		(1 << 5)
#define bit_SSE4a	(1 << 6)
#define bit_PRFCHW	(1 << 8)
#define bit_XOP         (1 << 11)
#define bit_LWP 	(1 << 15)
#define bit_FMA4        (1 << 16)
#define bit_TBM         (1 << 21)

/* %edx */
#define bit_MMXEXT	(1 << 22)
#define bit_LM		(1 << 29)
#define bit_3DNOWP	(1 << 30)
#define bit_3DNOW	(1 << 31)

/* Extended Features (%eax == 7) */
#define bit_FSGSBASE	(1 << 0)
#define bit_BMI	(1 << 3)
#define bit_HLE	(1 << 4)
#define bit_AVX2	(1 << 5)
#define bit_BMI2	(1 << 8)
#define bit_RTM	(1 << 11)
#define bit_RDSEED	(1 << 18)
#define bit_ADX	(1 << 19)

/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
#define bit_XSAVEOPT	(1 << 0)

/* Signatures for different CPU implementations as returned in uses
   of cpuid with level 0.  */
#define signature_AMD_ebx	0x68747541
#define signature_AMD_ecx	0x444d4163
#define signature_AMD_edx	0x69746e65

#define signature_CENTAUR_ebx	0x746e6543
#define signature_CENTAUR_ecx	0x736c7561
#define signature_CENTAUR_edx	0x48727561

#define signature_CYRIX_ebx	0x69727943
#define signature_CYRIX_ecx	0x64616574
#define signature_CYRIX_edx	0x736e4978

#define signature_INTEL_ebx	0x756e6547
#define signature_INTEL_ecx	0x6c65746e
#define signature_INTEL_edx	0x49656e69

#define signature_TM1_ebx	0x6e617254
#define signature_TM1_ecx	0x55504361
#define signature_TM1_edx	0x74656d73

#define signature_TM2_ebx	0x756e6547
#define signature_TM2_ecx	0x3638784d
#define signature_TM2_edx	0x54656e69

#define signature_NSC_ebx	0x646f6547
#define signature_NSC_ecx	0x43534e20
#define signature_NSC_edx	0x79622065

#define signature_NEXGEN_ebx	0x4778654e
#define signature_NEXGEN_ecx	0x6e657669
#define signature_NEXGEN_edx	0x72446e65

#define signature_RISE_ebx	0x65736952
#define signature_RISE_ecx	0x65736952
#define signature_RISE_edx	0x65736952

#define signature_SIS_ebx	0x20536953
#define signature_SIS_ecx	0x20536953
#define signature_SIS_edx	0x20536953

#define signature_UMC_ebx	0x20434d55
#define signature_UMC_ecx	0x20434d55
#define signature_UMC_edx	0x20434d55

#define signature_VIA_ebx	0x20414956
#define signature_VIA_ecx	0x20414956
#define signature_VIA_edx	0x20414956

#define signature_VORTEX_ebx	0x74726f56
#define signature_VORTEX_ecx	0x436f5320
#define signature_VORTEX_edx	0x36387865

#if defined(__i386__) && defined(__PIC__)
/* %ebx may be the PIC register.  */
#if __GNUC__ >= 3
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"			\
	   "cpuid\n\t"					\
	   "xchg{l}\t{%%}ebx, %k1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"			\
	   "cpuid\n\t"					\
	   "xchg{l}\t{%%}ebx, %k1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))
#else
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
   nor alternatives in i386 code.  */
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("xchgl\t%%ebx, %k1\n\t"			\
	   "cpuid\n\t"					\
	   "xchgl\t%%ebx, %k1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("xchgl\t%%ebx, %k1\n\t"			\
	   "cpuid\n\t"					\
	   "xchgl\t%%ebx, %k1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))
#endif
#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
/* %rbx may be the PIC register.  */
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"			\
	   "cpuid\n\t"					\
	   "xchg{q}\t{%%}rbx, %q1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"			\
	   "cpuid\n\t"					\
	   "xchg{q}\t{%%}rbx, %q1\n\t"			\
	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))
#else
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))
#endif

/* Return highest supported input value for cpuid instruction.  ext can
   be either 0x0 or 0x8000000 to return highest supported value for
   basic or extended cpuid information.  Function returns 0 if cpuid
   is not supported or whatever cpuid returns in eax register.  If sig
   pointer is non-null, then first four bytes of the signature
   (as found in ebx register) are returned in location pointed by sig.  */

static __inline unsigned int
__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
{
  unsigned int __eax, __ebx, __ecx, __edx;

#ifdef __i386__
  /* See if we can use cpuid.  On AMD64 we always can.  */
#if __GNUC__ >= 3
  __asm__ ("pushf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "mov{l}\t{%0, %1|%1, %0}\n\t"
	   "xor{l}\t{%2, %0|%0, %2}\n\t"
	   "push{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#else
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
   nor alternatives in i386 code.  */
  __asm__ ("pushfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "movl\t%0, %1\n\t"
	   "xorl\t%2, %0\n\t"
	   "pushl\t%0\n\t"
	   "popfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "popfl\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#endif

  if (!((__eax ^ __ebx) & 0x00200000))
    return 0;
#endif

  /* Host supports cpuid.  Return highest supported cpuid input value.  */
  __cpuid (__ext, __eax, __ebx, __ecx, __edx);

  if (__sig)
    *__sig = __ebx;

  return __eax;
}

/* Return cpuid data for requested cpuid level, as found in returned
   eax, ebx, ecx and edx registers.  The function checks if cpuid is
   supported and returns 1 for valid cpuid information or 0 for
   unsupported cpuid level.  All pointers are required to be non-null.  */

static __inline int
__get_cpuid (unsigned int __level,
	     unsigned int *__eax, unsigned int *__ebx,
	     unsigned int *__ecx, unsigned int *__edx)
{
  unsigned int __ext = __level & 0x80000000;

  if (__get_cpuid_max (__ext, 0) < __level)
    return 0;

  __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
  return 1;
}
Commit	Line	Data
4d157a3d MF	1	/*
	2	* Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not
	3	* include this directly, but pull in i386-cpuid.h and use that func.
	4	*/
	5	/*
28e7fd62	6	* Copyright (C) 2007-2013 Free Software Foundation, Inc.
a055a187 L	7	*
	8	* This file is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 3, or (at your option) any
	11	* later version.
	12	*
	13	* This file is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* Under Section 7 of GPL version 3, you are granted additional
	19	* permissions described in the GCC Runtime Library Exception, version
	20	* 3.1, as published by the Free Software Foundation.
	21	*
	22	* You should have received a copy of the GNU General Public License and
	23	* a copy of the GCC Runtime Library Exception along with this program;
	24	* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
	25	* <http://www.gnu.org/licenses/>.
	26	*/
83ecb59f	27
a055a187 L	28	/* %ecx */
	29	#define bit_SSE3 (1 << 0)
	30	#define bit_PCLMUL (1 << 1)
4d157a3d	31	#define bit_LZCNT (1 << 5)
a055a187 L	32	#define bit_SSSE3 (1 << 9)
	33	#define bit_FMA (1 << 12)
	34	#define bit_CMPXCHG16B (1 << 13)
	35	#define bit_SSE4_1 (1 << 19)
	36	#define bit_SSE4_2 (1 << 20)
	37	#define bit_MOVBE (1 << 22)
	38	#define bit_POPCNT (1 << 23)
	39	#define bit_AES (1 << 25)
	40	#define bit_XSAVE (1 << 26)
	41	#define bit_OSXSAVE (1 << 27)
	42	#define bit_AVX (1 << 28)
4d157a3d MF	43	#define bit_F16C (1 << 29)
4d157a3d MF	44	#define bit_RDRND (1 << 30)
83ecb59f	45
a055a187 L	46	/* %edx */
	47	#define bit_CMPXCHG8B (1 << 8)
	48	#define bit_CMOV (1 << 15)
	49	#define bit_MMX (1 << 23)
	50	#define bit_FXSAVE (1 << 24)
	51	#define bit_SSE (1 << 25)
	52	#define bit_SSE2 (1 << 26)
83ecb59f	53
a055a187 L	54	/* Extended Features */
	55	/* %ecx */
	56	#define bit_LAHF_LM (1 << 0)
	57	#define bit_ABM (1 << 5)
	58	#define bit_SSE4a (1 << 6)
4d157a3d	59	#define bit_PRFCHW (1 << 8)
a055a187 L	60	#define bit_XOP (1 << 11)
	61	#define bit_LWP (1 << 15)
	62	#define bit_FMA4 (1 << 16)
4d157a3d	63	#define bit_TBM (1 << 21)
a9762ec7	64
a055a187	65	/* %edx */
4d157a3d	66	#define bit_MMXEXT (1 << 22)
a055a187 L	67	#define bit_LM (1 << 29)
	68	#define bit_3DNOWP (1 << 30)
	69	#define bit_3DNOW (1 << 31)
a9762ec7	70
4d157a3d MF	71	/* Extended Features (%eax == 7) */
	72	#define bit_FSGSBASE (1 << 0)
	73	#define bit_BMI (1 << 3)
	74	#define bit_HLE (1 << 4)
	75	#define bit_AVX2 (1 << 5)
	76	#define bit_BMI2 (1 << 8)
	77	#define bit_RTM (1 << 11)
	78	#define bit_RDSEED (1 << 18)
	79	#define bit_ADX (1 << 19)
	80
	81	/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
	82	#define bit_XSAVEOPT (1 << 0)
	83
	84	/* Signatures for different CPU implementations as returned in uses
	85	of cpuid with level 0. */
	86	#define signature_AMD_ebx 0x68747541
	87	#define signature_AMD_ecx 0x444d4163
	88	#define signature_AMD_edx 0x69746e65
	89
	90	#define signature_CENTAUR_ebx 0x746e6543
	91	#define signature_CENTAUR_ecx 0x736c7561
	92	#define signature_CENTAUR_edx 0x48727561
	93
	94	#define signature_CYRIX_ebx 0x69727943
	95	#define signature_CYRIX_ecx 0x64616574
	96	#define signature_CYRIX_edx 0x736e4978
	97
	98	#define signature_INTEL_ebx 0x756e6547
	99	#define signature_INTEL_ecx 0x6c65746e
	100	#define signature_INTEL_edx 0x49656e69
	101
	102	#define signature_TM1_ebx 0x6e617254
	103	#define signature_TM1_ecx 0x55504361
	104	#define signature_TM1_edx 0x74656d73
	105
	106	#define signature_TM2_ebx 0x756e6547
	107	#define signature_TM2_ecx 0x3638784d
	108	#define signature_TM2_edx 0x54656e69
	109
	110	#define signature_NSC_ebx 0x646f6547
	111	#define signature_NSC_ecx 0x43534e20
	112	#define signature_NSC_edx 0x79622065
	113
	114	#define signature_NEXGEN_ebx 0x4778654e
	115	#define signature_NEXGEN_ecx 0x6e657669
	116	#define signature_NEXGEN_edx 0x72446e65
	117
	118	#define signature_RISE_ebx 0x65736952
	119	#define signature_RISE_ecx 0x65736952
	120	#define signature_RISE_edx 0x65736952
	121
	122	#define signature_SIS_ebx 0x20536953
	123	#define signature_SIS_ecx 0x20536953
	124	#define signature_SIS_edx 0x20536953
	125
	126	#define signature_UMC_ebx 0x20434d55
	127	#define signature_UMC_ecx 0x20434d55
	128	#define signature_UMC_edx 0x20434d55
	129
	130	#define signature_VIA_ebx 0x20414956
	131	#define signature_VIA_ecx 0x20414956
	132	#define signature_VIA_edx 0x20414956
	133
	134	#define signature_VORTEX_ebx 0x74726f56
135	#define signature_VORTEX_ecx 0x436f5320
136	#define signature_VORTEX_edx 0x36387865
83ecb59f	137
a055a187 L	138	#if defined(__i386__) && defined(__PIC__)
	139	/* %ebx may be the PIC register. */
	140	#if __GNUC__ >= 3
	141	#define __cpuid(level, a, b, c, d) \
4d157a3d	142	__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
a055a187	143	"cpuid\n\t" \
4d157a3d MF	144	"xchg{l}\t{%%}ebx, %k1\n\t" \
4d157a3d MF	145	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
a055a187	146	: "0" (level))
83ecb59f	147
a055a187	148	#define __cpuid_count(level, count, a, b, c, d) \
4d157a3d	149	__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
a055a187	150	"cpuid\n\t" \
4d157a3d MF	151	"xchg{l}\t{%%}ebx, %k1\n\t" \
4d157a3d MF	152	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
a055a187 L	153	: "0" (level), "2" (count))
	154	#else
	155	/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
	156	nor alternatives in i386 code. */
	157	#define __cpuid(level, a, b, c, d) \
4d157a3d	158	__asm__ ("xchgl\t%%ebx, %k1\n\t" \
a055a187	159	"cpuid\n\t" \
4d157a3d MF	160	"xchgl\t%%ebx, %k1\n\t" \
4d157a3d MF	161	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
a055a187	162	: "0" (level))
83ecb59f	163
a055a187	164	#define __cpuid_count(level, count, a, b, c, d) \
4d157a3d	165	__asm__ ("xchgl\t%%ebx, %k1\n\t" \
a055a187	166	"cpuid\n\t" \
4d157a3d MF	167	"xchgl\t%%ebx, %k1\n\t" \
4d157a3d MF	168	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
a055a187	169	: "0" (level), "2" (count))
83ecb59f	170	#endif
4d157a3d MF	171	#elif defined(__x86_64__) && (defined(__code_model_medium__) \|\| defined(__code_model_large__)) && defined(__PIC__)
	172	/* %rbx may be the PIC register. */
	173	#define __cpuid(level, a, b, c, d) \
	174	__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
	175	"cpuid\n\t" \
	176	"xchg{q}\t{%%}rbx, %q1\n\t" \
	177	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
	178	: "0" (level))
	179
	180	#define __cpuid_count(level, count, a, b, c, d) \
	181	__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
	182	"cpuid\n\t" \
	183	"xchg{q}\t{%%}rbx, %q1\n\t" \
	184	: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
	185	: "0" (level), "2" (count))
a055a187 L	186	#else
	187	#define __cpuid(level, a, b, c, d) \
	188	__asm__ ("cpuid\n\t" \
	189	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	190	: "0" (level))
83ecb59f	191
a055a187 L	192	#define __cpuid_count(level, count, a, b, c, d) \
	193	__asm__ ("cpuid\n\t" \
	194	: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
	195	: "0" (level), "2" (count))
	196	#endif
83ecb59f	197
a055a187 L	198	/* Return highest supported input value for cpuid instruction. ext can
	199	be either 0x0 or 0x8000000 to return highest supported value for
	200	basic or extended cpuid information. Function returns 0 if cpuid
	201	is not supported or whatever cpuid returns in eax register. If sig
	202	pointer is non-null, then first four bytes of the signature
	203	(as found in ebx register) are returned in location pointed by sig. */
	204
	205	static __inline unsigned int
	206	__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
83ecb59f	207	{
a055a187	208	unsigned int __eax, __ebx, __ecx, __edx;
83ecb59f	209
4d157a3d	210	#ifdef __i386__
83ecb59f	211	/* See if we can use cpuid. On AMD64 we always can. */
4d157a3d	212	#if __GNUC__ >= 3
a055a187 L	213	__asm__ ("pushf{l\|d}\n\t"
	214	"pushf{l\|d}\n\t"
	215	"pop{l}\t%0\n\t"
	216	"mov{l}\t{%0, %1\|%1, %0}\n\t"
	217	"xor{l}\t{%2, %0\|%0, %2}\n\t"
	218	"push{l}\t%0\n\t"
	219	"popf{l\|d}\n\t"
	220	"pushf{l\|d}\n\t"
	221	"pop{l}\t%0\n\t"
	222	"popf{l\|d}\n\t"
	223	: "=&r" (__eax), "=&r" (__ebx)
	224	: "i" (0x00200000));
	225	#else
	226	/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
	227	nor alternatives in i386 code. */
	228	__asm__ ("pushfl\n\t"
	229	"pushfl\n\t"
	230	"popl\t%0\n\t"
	231	"movl\t%0, %1\n\t"
	232	"xorl\t%2, %0\n\t"
	233	"pushl\t%0\n\t"
	234	"popfl\n\t"
	235	"pushfl\n\t"
	236	"popl\t%0\n\t"
	237	"popfl\n\t"
	238	: "=&r" (__eax), "=&r" (__ebx)
83ecb59f	239	: "i" (0x00200000));
83ecb59f JB	240	#endif
83ecb59f JB	241
a055a187 L	242	if (!((__eax ^ __ebx) & 0x00200000))
a055a187 L	243	return 0;
83ecb59f	244	#endif
a055a187 L	245
	246	/* Host supports cpuid. Return highest supported cpuid input value. */
	247	__cpuid (__ext, __eax, __ebx, __ecx, __edx);
	248
	249	if (__sig)
	250	*__sig = __ebx;
	251
	252	return __eax;
	253	}
	254
	255	/* Return cpuid data for requested cpuid level, as found in returned
	256	eax, ebx, ecx and edx registers. The function checks if cpuid is
	257	supported and returns 1 for valid cpuid information or 0 for
	258	unsupported cpuid level. All pointers are required to be non-null. */
	259
	260	static __inline int
	261	__get_cpuid (unsigned int __level,
	262	unsigned int __eax, unsigned int __ebx,
	263	unsigned int __ecx, unsigned int __edx)
	264	{
	265	unsigned int __ext = __level & 0x80000000;
	266
	267	if (__get_cpuid_max (__ext, 0) < __level)
	268	return 0;
	269
	270	__cpuid (__level, __eax, __ebx, __ecx, __edx);
	271	return 1;
	272	}