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c906108c SS |
1 | /* Definitions to make GDB run on a mips box under 4.3bsd. |
2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995 | |
3 | Free Software Foundation, Inc. | |
4 | Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin | |
5 | and by Alessandro Forin (af@cs.cmu.edu) at CMU.. | |
6 | ||
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #ifndef TM_MIPS_H | |
25 | #define TM_MIPS_H 1 | |
26 | ||
c906108c SS |
27 | struct frame_info; |
28 | struct symbol; | |
29 | struct type; | |
30 | struct value; | |
c906108c SS |
31 | |
32 | #include <bfd.h> | |
33 | #include "coff/sym.h" /* Needed for PDR below. */ | |
34 | #include "coff/symconst.h" | |
35 | ||
36 | #if !defined (TARGET_BYTE_ORDER_DEFAULT) | |
37 | #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN | |
38 | #endif | |
39 | ||
40 | #if !defined (GDB_TARGET_IS_MIPS64) | |
41 | #define GDB_TARGET_IS_MIPS64 0 | |
42 | #endif | |
43 | ||
44 | #if !defined (MIPS_EABI) | |
45 | #define MIPS_EABI 0 | |
46 | #endif | |
47 | ||
48 | #if !defined (TARGET_MONITOR_PROMPT) | |
49 | #define TARGET_MONITOR_PROMPT "<IDT>" | |
50 | #endif | |
51 | ||
52 | /* PC should be masked to remove possible MIPS16 flag */ | |
53 | #if !defined (GDB_TARGET_MASK_DISAS_PC) | |
54 | #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr) | |
55 | #endif | |
56 | #if !defined (GDB_TARGET_UNMASK_DISAS_PC) | |
57 | #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr) | |
58 | #endif | |
59 | ||
60 | /* Floating point is IEEE compliant */ | |
7355ddba | 61 | #define IEEE_FLOAT (1) |
c906108c SS |
62 | |
63 | /* The name of the usual type of MIPS processor that is in the target | |
64 | system. */ | |
65 | ||
66 | #define DEFAULT_MIPS_TYPE "generic" | |
67 | ||
68 | /* Remove useless bits from an instruction address. */ | |
69 | ||
70 | #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr) | |
a14ed312 | 71 | CORE_ADDR mips_addr_bits_remove (CORE_ADDR addr); |
c906108c SS |
72 | |
73 | /* Remove useless bits from the stack pointer. */ | |
74 | ||
75 | #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM)) | |
76 | ||
77 | /* Offset from address of function to start of its code. | |
78 | Zero on most machines. */ | |
79 | ||
80 | #define FUNCTION_START_OFFSET 0 | |
81 | ||
82 | /* Advance PC across any function entry prologue instructions | |
83 | to reach some "real" code. */ | |
84 | ||
b83266a0 | 85 | #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0)) |
a14ed312 | 86 | extern CORE_ADDR mips_skip_prologue (CORE_ADDR addr, int lenient); |
c906108c SS |
87 | |
88 | /* Return non-zero if PC points to an instruction which will cause a step | |
89 | to execute both the instruction at PC and an instruction at PC+4. */ | |
a14ed312 | 90 | extern int mips_step_skips_delay (CORE_ADDR); |
c906108c SS |
91 | #define STEP_SKIPS_DELAY_P (1) |
92 | #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc)) | |
93 | ||
94 | /* Immediately after a function call, return the saved pc. | |
95 | Can't always go through the frames for this because on some machines | |
96 | the new frame is not set up until the new function executes | |
97 | some instructions. */ | |
98 | ||
99 | #define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM) | |
100 | ||
101 | /* Are we currently handling a signal */ | |
102 | ||
a14ed312 | 103 | extern int in_sigtramp (CORE_ADDR, char *); |
c906108c SS |
104 | #define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name) |
105 | ||
106 | /* Stack grows downward. */ | |
107 | ||
108 | #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) | |
109 | ||
c906108c SS |
110 | /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a |
111 | 16- or 32-bit breakpoint should be used. It returns a pointer | |
112 | to a string of bytes that encode a breakpoint instruction, stores | |
113 | the length of the string to *lenptr, and adjusts the pc (if necessary) to | |
114 | point to the actual memory location where the breakpoint should be | |
115 | inserted. */ | |
116 | ||
117 | extern breakpoint_from_pc_fn mips_breakpoint_from_pc; | |
118 | #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr) | |
119 | ||
120 | /* Amount PC must be decremented by after a breakpoint. | |
121 | This is often the number of bytes in BREAKPOINT | |
122 | but not always. */ | |
123 | ||
124 | #define DECR_PC_AFTER_BREAK 0 | |
125 | ||
126 | /* Say how long (ordinary) registers are. This is a piece of bogosity | |
127 | used in push_word and a few other places; REGISTER_RAW_SIZE is the | |
128 | real way to know how big a register is. */ | |
129 | ||
130 | #define REGISTER_SIZE 4 | |
131 | ||
132 | /* The size of a register. This is predefined in tm-mips64.h. We | |
133 | can't use REGISTER_SIZE because that is used for various other | |
134 | things. */ | |
135 | ||
136 | #ifndef MIPS_REGSIZE | |
137 | #define MIPS_REGSIZE 4 | |
138 | #endif | |
139 | ||
140 | /* The sizes of floating point registers. */ | |
141 | ||
142 | #define MIPS_FPU_SINGLE_REGSIZE 4 | |
143 | #define MIPS_FPU_DOUBLE_REGSIZE 8 | |
144 | ||
145 | /* Number of machine registers */ | |
146 | ||
147 | #ifndef NUM_REGS | |
148 | #define NUM_REGS 90 | |
149 | #endif | |
150 | ||
cce74817 JM |
151 | /* Given the register index, return the name of the corresponding |
152 | register. */ | |
a14ed312 | 153 | extern char *mips_register_name (int regnr); |
cce74817 JM |
154 | #define REGISTER_NAME(i) mips_register_name (i) |
155 | ||
c906108c SS |
156 | /* Initializer for an array of names of registers. |
157 | There should be NUM_REGS strings in this initializer. */ | |
158 | ||
cce74817 JM |
159 | #ifndef MIPS_REGISTER_NAMES |
160 | #define MIPS_REGISTER_NAMES \ | |
c906108c SS |
161 | { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ |
162 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ | |
163 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ | |
164 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \ | |
165 | "sr", "lo", "hi", "bad", "cause","pc", \ | |
166 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
167 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
168 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\ | |
169 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\ | |
170 | "fsr", "fir", "fp", "", \ | |
171 | "", "", "", "", "", "", "", "", \ | |
172 | "", "", "", "", "", "", "", "", \ | |
173 | } | |
174 | #endif | |
175 | ||
176 | /* Register numbers of various important registers. | |
177 | Note that some of these values are "real" register numbers, | |
178 | and correspond to the general registers of the machine, | |
179 | and some are "phony" register numbers which are too large | |
180 | to be actual register numbers as far as the user is concerned | |
181 | but do serve to get the desired values when passed to read_register. */ | |
182 | ||
183 | #define ZERO_REGNUM 0 /* read-only register, always 0 */ | |
184 | #define V0_REGNUM 2 /* Function integer return value */ | |
185 | #define A0_REGNUM 4 /* Loc of first arg during a subr call */ | |
186 | #if MIPS_EABI | |
c5aa993b | 187 | #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */ |
c906108c | 188 | #else |
c5aa993b | 189 | #define MIPS_LAST_ARG_REGNUM 7 /* old ABI uses R4 through R7 for args */ |
c906108c SS |
190 | #endif |
191 | #define T9_REGNUM 25 /* Contains address of callee in PIC */ | |
192 | #define SP_REGNUM 29 /* Contains address of top of stack */ | |
193 | #define RA_REGNUM 31 /* Contains return address value */ | |
194 | #define PS_REGNUM 32 /* Contains processor status */ | |
c5aa993b JM |
195 | #define HI_REGNUM 34 /* Multiple/divide temp */ |
196 | #define LO_REGNUM 33 /* ... */ | |
c906108c SS |
197 | #define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */ |
198 | #define CAUSE_REGNUM 36 /* describes last exception */ | |
199 | #define PC_REGNUM 37 /* Contains program counter */ | |
c5aa993b JM |
200 | #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ |
201 | #define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */ | |
c906108c | 202 | #if MIPS_EABI /* EABI uses F12 through F19 for args */ |
c5aa993b | 203 | #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19) |
c5aa993b JM |
204 | #else /* old ABI uses F12 through F15 for args */ |
205 | #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15) | |
c906108c | 206 | #endif |
c5aa993b JM |
207 | #define FCRCS_REGNUM 70 /* FP control/status */ |
208 | #define FCRIR_REGNUM 71 /* FP implementation/revision */ | |
c906108c SS |
209 | #define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */ |
210 | #define UNUSED_REGNUM 73 /* Never used, FIXME */ | |
211 | #define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */ | |
212 | #define PRID_REGNUM 89 /* Processor ID */ | |
213 | #define LAST_EMBED_REGNUM 89 /* Last one */ | |
214 | ||
215 | /* Define DO_REGISTERS_INFO() to do machine-specific formatting | |
216 | of register dumps. */ | |
217 | ||
218 | #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp) | |
a14ed312 | 219 | extern void mips_do_registers_info (int, int); |
c906108c SS |
220 | |
221 | /* Total amount of space needed to store our copies of the machine's | |
222 | register state, the array `registers'. */ | |
223 | ||
224 | #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE) | |
225 | ||
226 | /* Index within `registers' of the first byte of the space for | |
227 | register N. */ | |
228 | ||
229 | #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE) | |
230 | ||
43e526b9 JM |
231 | /* Number of bytes of storage in the actual machine representation for |
232 | register N. NOTE: This indirectly defines the register size | |
233 | transfered by the GDB protocol. */ | |
234 | ||
a14ed312 | 235 | extern int mips_register_raw_size (int reg_nr); |
43e526b9 JM |
236 | #define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N))) |
237 | ||
238 | ||
239 | /* Covert between the RAW and VIRTUAL registers. | |
240 | ||
241 | Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are | |
242 | really 32 bit registers. This is a legacy of the 64 bit MIPS GDB | |
243 | protocol which transfers 64 bits for 32 bit registers. */ | |
244 | ||
a14ed312 | 245 | extern int mips_register_convertible (int reg_nr); |
43e526b9 JM |
246 | #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N))) |
247 | ||
248 | ||
a14ed312 KB |
249 | void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type, |
250 | char *raw_buf, char *virt_buf); | |
43e526b9 JM |
251 | #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \ |
252 | mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) | |
c906108c | 253 | |
a14ed312 KB |
254 | void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr, |
255 | char *virt_buf, char *raw_buf); | |
43e526b9 JM |
256 | #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \ |
257 | mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) | |
c906108c SS |
258 | |
259 | /* Number of bytes of storage in the program's representation | |
260 | for register N. */ | |
261 | ||
262 | #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N)) | |
263 | ||
264 | /* Largest value REGISTER_RAW_SIZE can have. */ | |
265 | ||
266 | #define MAX_REGISTER_RAW_SIZE 8 | |
267 | ||
268 | /* Largest value REGISTER_VIRTUAL_SIZE can have. */ | |
269 | ||
270 | #define MAX_REGISTER_VIRTUAL_SIZE 8 | |
271 | ||
272 | /* Return the GDB type object for the "standard" data type of data in | |
273 | register N. */ | |
274 | ||
275 | #ifndef REGISTER_VIRTUAL_TYPE | |
276 | #define REGISTER_VIRTUAL_TYPE(N) \ | |
277 | (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \ | |
278 | : ((N) == 32 /*SR*/) ? builtin_type_uint32 \ | |
279 | : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \ | |
280 | : builtin_type_int) | |
281 | #endif | |
282 | ||
283 | /* All mips targets store doubles in a register pair with the least | |
284 | significant register in the lower numbered register. | |
285 | If the target is big endian, double register values need conversion | |
286 | between memory and register formats. */ | |
287 | ||
288 | #define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \ | |
289 | do {if (TARGET_BYTE_ORDER == BIG_ENDIAN \ | |
290 | && REGISTER_RAW_SIZE (n) == 4 \ | |
291 | && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 \ | |
292 | && TYPE_CODE(type) == TYPE_CODE_FLT \ | |
293 | && TYPE_LENGTH(type) == 8) { \ | |
294 | char __temp[4]; \ | |
295 | memcpy (__temp, ((char *)(buffer))+4, 4); \ | |
296 | memcpy (((char *)(buffer))+4, (buffer), 4); \ | |
297 | memcpy (((char *)(buffer)), __temp, 4); }} while (0) | |
298 | ||
299 | #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \ | |
300 | do {if (TARGET_BYTE_ORDER == BIG_ENDIAN \ | |
301 | && REGISTER_RAW_SIZE (n) == 4 \ | |
302 | && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 \ | |
303 | && TYPE_CODE(type) == TYPE_CODE_FLT \ | |
304 | && TYPE_LENGTH(type) == 8) { \ | |
305 | char __temp[4]; \ | |
306 | memcpy (__temp, ((char *)(buffer))+4, 4); \ | |
307 | memcpy (((char *)(buffer))+4, (buffer), 4); \ | |
308 | memcpy (((char *)(buffer)), __temp, 4); }} while (0) | |
309 | ||
310 | /* Store the address of the place in which to copy the structure the | |
311 | subroutine will return. Handled by mips_push_arguments. */ | |
312 | ||
c5aa993b JM |
313 | #define STORE_STRUCT_RETURN(addr, sp) |
314 | /**/ | |
c906108c SS |
315 | |
316 | /* Extract from an array REGBUF containing the (raw) register state | |
317 | a function return value of type TYPE, and copy that, in virtual format, | |
318 | into VALBUF. XXX floats */ | |
319 | ||
320 | #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ | |
321 | mips_extract_return_value(TYPE, REGBUF, VALBUF) | |
a14ed312 | 322 | extern void mips_extract_return_value (struct type *, char[], char *); |
c906108c SS |
323 | |
324 | /* Write into appropriate registers a function return value | |
325 | of type TYPE, given in virtual format. */ | |
326 | ||
327 | #define STORE_RETURN_VALUE(TYPE,VALBUF) \ | |
328 | mips_store_return_value(TYPE, VALBUF) | |
a14ed312 | 329 | extern void mips_store_return_value (struct type *, char *); |
c906108c SS |
330 | |
331 | /* Extract from an array REGBUF containing the (raw) register state | |
332 | the address in which a function should return its structure value, | |
333 | as a CORE_ADDR (or an expression that can be used as one). */ | |
334 | /* The address is passed in a0 upon entry to the function, but when | |
335 | the function exits, the compiler has copied the value to v0. This | |
336 | convention is specified by the System V ABI, so I think we can rely | |
337 | on it. */ | |
338 | ||
339 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ | |
340 | (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \ | |
341 | REGISTER_RAW_SIZE (V0_REGNUM))) | |
342 | ||
343 | extern use_struct_convention_fn mips_use_struct_convention; | |
344 | #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type) | |
345 | \f | |
346 | /* Describe the pointer in each stack frame to the previous stack frame | |
347 | (its caller). */ | |
348 | ||
349 | /* FRAME_CHAIN takes a frame's nominal address | |
350 | and produces the frame's chain-pointer. */ | |
351 | ||
352 | #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe) | |
a14ed312 | 353 | extern CORE_ADDR mips_frame_chain (struct frame_info *); |
c906108c SS |
354 | |
355 | /* Define other aspects of the stack frame. */ | |
356 | ||
357 | ||
358 | /* A macro that tells us whether the function invocation represented | |
359 | by FI does not have a frame on the stack associated with it. If it | |
360 | does not, FRAMELESS is set to 1, else 0. */ | |
361 | /* We handle this differently for mips, and maybe we should not */ | |
362 | ||
392a587b | 363 | #define FRAMELESS_FUNCTION_INVOCATION(FI) (0) |
c906108c SS |
364 | |
365 | /* Saved Pc. */ | |
366 | ||
367 | #define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME)) | |
a14ed312 | 368 | extern CORE_ADDR mips_frame_saved_pc (struct frame_info *); |
c906108c SS |
369 | |
370 | #define FRAME_ARGS_ADDRESS(fi) (fi)->frame | |
371 | ||
372 | #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame | |
373 | ||
374 | /* Return number of args passed to a frame. | |
375 | Can return -1, meaning no way to tell. */ | |
376 | ||
392a587b | 377 | #define FRAME_NUM_ARGS(fi) (mips_frame_num_args(fi)) |
a14ed312 | 378 | extern int mips_frame_num_args (struct frame_info *); |
c906108c SS |
379 | |
380 | /* Return number of bytes at start of arglist that are not really args. */ | |
381 | ||
382 | #define FRAME_ARGS_SKIP 0 | |
383 | ||
384 | /* Put here the code to store, into a struct frame_saved_regs, | |
385 | the addresses of the saved registers of frame described by FRAME_INFO. | |
386 | This includes special registers such as pc and fp saved in special | |
387 | ways in the stack frame. sp is even more special: | |
388 | the address we return for it IS the sp for the next frame. */ | |
389 | ||
390 | #define FRAME_INIT_SAVED_REGS(frame_info) \ | |
391 | do { \ | |
392 | if ((frame_info)->saved_regs == NULL) \ | |
393 | mips_find_saved_regs (frame_info); \ | |
394 | (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \ | |
395 | } while (0) | |
a14ed312 | 396 | extern void mips_find_saved_regs (struct frame_info *); |
c906108c | 397 | \f |
c5aa993b | 398 | |
c906108c SS |
399 | /* Things needed for making the inferior call functions. */ |
400 | ||
401 | /* Stack must be aligned on 32-bit boundaries when synthesizing | |
402 | function calls. We don't need STACK_ALIGN, PUSH_ARGUMENTS will | |
403 | handle it. */ | |
404 | ||
a14ed312 KB |
405 | extern CORE_ADDR mips_push_arguments (int, struct value **, CORE_ADDR, int, |
406 | CORE_ADDR); | |
c906108c | 407 | #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ |
392a587b | 408 | (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))) |
0f71a2f6 | 409 | |
a14ed312 | 410 | extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp); |
0f71a2f6 | 411 | #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP))) |
c906108c SS |
412 | |
413 | /* Push an empty stack frame, to record the current PC, etc. */ | |
414 | ||
415 | #define PUSH_DUMMY_FRAME mips_push_dummy_frame() | |
a14ed312 | 416 | extern void mips_push_dummy_frame (void); |
c906108c SS |
417 | |
418 | /* Discard from the stack the innermost frame, restoring all registers. */ | |
419 | ||
420 | #define POP_FRAME mips_pop_frame() | |
a14ed312 | 421 | extern void mips_pop_frame (void); |
c906108c | 422 | |
ed9a39eb | 423 | #if !GDB_MULTI_ARCH |
c906108c | 424 | #define CALL_DUMMY { 0 } |
ed9a39eb | 425 | #endif |
c906108c SS |
426 | |
427 | #define CALL_DUMMY_START_OFFSET (0) | |
428 | ||
429 | #define CALL_DUMMY_BREAKPOINT_OFFSET (0) | |
430 | ||
6878c383 AC |
431 | /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant |
432 | platform), $t9 ($25) (Dest_Reg) contains the address of the callee | |
433 | (used for PIC). It doesn't hurt to do this on other systems; $t9 | |
434 | will be ignored. */ | |
c906108c SS |
435 | #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \ |
436 | write_register(T9_REGNUM, fun) | |
437 | ||
438 | #define CALL_DUMMY_LOCATION AT_ENTRY_POINT | |
439 | ||
440 | #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ()) | |
a14ed312 | 441 | extern CORE_ADDR mips_call_dummy_address (void); |
c906108c SS |
442 | |
443 | /* There's a mess in stack frame creation. See comments in blockframe.c | |
444 | near reference to INIT_FRAME_PC_FIRST. */ | |
445 | ||
c5aa993b | 446 | #define INIT_FRAME_PC(fromleaf, prev) /* nada */ |
c906108c SS |
447 | |
448 | #define INIT_FRAME_PC_FIRST(fromleaf, prev) \ | |
449 | mips_init_frame_pc_first(fromleaf, prev) | |
a14ed312 | 450 | extern void mips_init_frame_pc_first (int, struct frame_info *); |
c906108c SS |
451 | |
452 | /* Special symbol found in blocks associated with routines. We can hang | |
453 | mips_extra_func_info_t's off of this. */ | |
454 | ||
455 | #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__" | |
a14ed312 | 456 | extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR); |
c906108c SS |
457 | |
458 | /* Specific information about a procedure. | |
459 | This overlays the MIPS's PDR records, | |
460 | mipsread.c (ab)uses this to save memory */ | |
461 | ||
c5aa993b JM |
462 | typedef struct mips_extra_func_info |
463 | { | |
464 | long numargs; /* number of args to procedure (was iopt) */ | |
465 | bfd_vma high_addr; /* upper address bound */ | |
466 | long frame_adjust; /* offset of FP from SP (used on MIPS16) */ | |
467 | PDR pdr; /* Procedure descriptor record */ | |
468 | } | |
469 | *mips_extra_func_info_t; | |
c906108c | 470 | |
a14ed312 | 471 | extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *); |
cce74817 JM |
472 | #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \ |
473 | mips_init_extra_frame_info(fromleaf, fci) | |
c906108c | 474 | |
a14ed312 | 475 | extern void mips_print_extra_frame_info (struct frame_info *frame); |
c906108c | 476 | #define PRINT_EXTRA_FRAME_INFO(fi) \ |
cce74817 | 477 | mips_print_extra_frame_info (fi) |
c906108c SS |
478 | |
479 | /* It takes two values to specify a frame on the MIPS. | |
480 | ||
481 | In fact, the *PC* is the primary value that sets up a frame. The | |
482 | PC is looked up to see what function it's in; symbol information | |
483 | from that function tells us which register is the frame pointer | |
484 | base, and what offset from there is the "virtual frame pointer". | |
485 | (This is usually an offset from SP.) On most non-MIPS machines, | |
486 | the primary value is the SP, and the PC, if needed, disambiguates | |
487 | multiple functions with the same SP. But on the MIPS we can't do | |
488 | that since the PC is not stored in the same part of the frame every | |
489 | time. This does not seem to be a very clever way to set up frames, | |
490 | but there is nothing we can do about that). */ | |
491 | ||
492 | #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv) | |
a14ed312 | 493 | extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *); |
c906108c SS |
494 | |
495 | /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */ | |
496 | ||
497 | #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38) | |
498 | ||
499 | /* Convert a ecoff register number to a gdb REGNUM */ | |
500 | ||
501 | #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32) | |
502 | ||
b9a8e3bf | 503 | #if !GDB_MULTI_ARCH |
c906108c SS |
504 | /* If the current gcc for for this target does not produce correct debugging |
505 | information for float parameters, both prototyped and unprototyped, then | |
506 | define this macro. This forces gdb to always assume that floats are | |
507 | passed as doubles and then converted in the callee. | |
508 | ||
509 | For the mips chip, it appears that the debug info marks the parameters as | |
510 | floats regardless of whether the function is prototyped, but the actual | |
511 | values are passed as doubles for the non-prototyped case and floats for | |
512 | the prototyped case. Thus we choose to make the non-prototyped case work | |
513 | for C and break the prototyped case, since the non-prototyped case is | |
514 | probably much more common. (FIXME). */ | |
515 | ||
b9a8e3bf JB |
516 | #define COERCE_FLOAT_TO_DOUBLE(formal, actual) (current_language -> la_language == language_c) |
517 | #endif | |
c906108c SS |
518 | |
519 | /* Select the default mips disassembler */ | |
520 | ||
521 | #define TM_PRINT_INSN_MACH 0 | |
522 | ||
523 | ||
524 | /* These are defined in mdebugread.c and are used in mips-tdep.c */ | |
525 | extern CORE_ADDR sigtramp_address, sigtramp_end; | |
a14ed312 | 526 | extern void fixup_sigtramp (void); |
c906108c SS |
527 | |
528 | /* Defined in mips-tdep.c and used in remote-mips.c */ | |
a14ed312 | 529 | extern char *mips_read_processor_type (void); |
c906108c SS |
530 | |
531 | /* Functions for dealing with MIPS16 call and return stubs. */ | |
532 | #define IN_SOLIB_CALL_TRAMPOLINE(pc, name) mips_in_call_stub (pc, name) | |
533 | #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name) mips_in_return_stub (pc, name) | |
534 | #define SKIP_TRAMPOLINE_CODE(pc) mips_skip_stub (pc) | |
535 | #define IGNORE_HELPER_CALL(pc) mips_ignore_helper (pc) | |
a14ed312 KB |
536 | extern int mips_in_call_stub (CORE_ADDR pc, char *name); |
537 | extern int mips_in_return_stub (CORE_ADDR pc, char *name); | |
538 | extern CORE_ADDR mips_skip_stub (CORE_ADDR pc); | |
539 | extern int mips_ignore_helper (CORE_ADDR pc); | |
c906108c SS |
540 | |
541 | #ifndef TARGET_MIPS | |
542 | #define TARGET_MIPS | |
543 | #endif | |
544 | ||
545 | /* Definitions and declarations used by mips-tdep.c and remote-mips.c */ | |
546 | #define MIPS_INSTLEN 4 /* Length of an instruction */ | |
c5aa993b | 547 | #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16 */ |
c906108c SS |
548 | #define MIPS_NUMREGS 32 /* Number of integer or float registers */ |
549 | typedef unsigned long t_inst; /* Integer big enough to hold an instruction */ | |
550 | ||
551 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some | |
552 | macros to test, set, or clear bit 0 of addresses. */ | |
553 | #define IS_MIPS16_ADDR(addr) ((addr) & 1) | |
554 | #define MAKE_MIPS16_ADDR(addr) ((addr) | 1) | |
555 | #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1) | |
556 | ||
c5aa993b | 557 | #endif /* TM_MIPS_H */ |
c906108c SS |
558 | |
559 | /* Macros for setting and testing a bit in a minimal symbol that | |
560 | marks it as 16-bit function. The MSB of the minimal symbol's | |
561 | "info" field is used for this purpose. This field is already | |
562 | being used to store the symbol size, so the assumption is | |
563 | that the symbol size cannot exceed 2^31. | |
564 | ||
565 | ELF_MAKE_MSYMBOL_SPECIAL | |
c5aa993b JM |
566 | tests whether an ELF symbol is "special", i.e. refers |
567 | to a 16-bit function, and sets a "special" bit in a | |
568 | minimal symbol to mark it as a 16-bit function | |
569 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
570 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
571 | the "info" field with the "special" bit masked out | |
572 | */ | |
c906108c SS |
573 | |
574 | #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \ | |
575 | { \ | |
576 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \ | |
577 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \ | |
578 | SYMBOL_VALUE_ADDRESS (msym) |= 1; \ | |
579 | } \ | |
580 | } | |
c5aa993b | 581 | |
c906108c SS |
582 | #define MSYMBOL_IS_SPECIAL(msym) \ |
583 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
584 | #define MSYMBOL_SIZE(msym) \ | |
585 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
d4f3574e SS |
586 | |
587 | ||
588 | /* Command to set the processor type. */ | |
589 | extern void mips_set_processor_type_command (char *, int); |