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c906108c SS |
1 | /* Parameters for execution on an HP PA-RISC machine running OSF1, for GDB. |
2 | Contributed by the Center for Software Science at the | |
3 | University of Utah (pa-gdb-bugs@cs.utah.edu). */ | |
4 | ||
f88e2c52 AC |
5 | #include "regcache.h" |
6 | ||
c906108c SS |
7 | /* Define offsets to access CPROC stack when it does not have |
8 | * a kernel thread. | |
9 | */ | |
10 | #define MACHINE_CPROC_SP_OFFSET 20 | |
11 | #define MACHINE_CPROC_PC_OFFSET 16 | |
12 | #define MACHINE_CPROC_FP_OFFSET 12 | |
13 | ||
14 | /* | |
15 | * Software defined PSW masks. | |
16 | */ | |
c5aa993b | 17 | #define PSW_SS 0x10000000 /* Kernel managed single step */ |
c906108c SS |
18 | |
19 | /* Thread flavors used in re-setting the T bit. | |
20 | * @@ this is also bad for cross debugging. | |
21 | */ | |
22 | #define TRACE_FLAVOR HP800_THREAD_STATE | |
23 | #define TRACE_FLAVOR_SIZE HP800_THREAD_STATE_COUNT | |
24 | #define TRACE_SET(x,state) \ | |
25 | ((struct hp800_thread_state *)state)->cr22 |= PSW_SS | |
26 | #define TRACE_CLEAR(x,state) \ | |
27 | ((((struct hp800_thread_state *)state)->cr22 &= ~PSW_SS), 1) | |
28 | ||
29 | /* For OSF1 (Should be close if not identical to BSD, but I haven't | |
30 | tested it yet): | |
31 | ||
32 | The signal context structure pointer is always saved at the base | |
33 | of the frame + 0x4. | |
34 | ||
35 | We get the PC & SP directly from the sigcontext structure itself. | |
36 | For other registers we have to dive in a little deeper: | |
37 | ||
38 | The hardware save state pointer is at offset 0x10 within the | |
39 | signal context structure. | |
40 | ||
41 | Within the hardware save state, registers are found in the same order | |
42 | as the register numbers in GDB. */ | |
43 | ||
44 | #define FRAME_SAVED_PC_IN_SIGTRAMP(FRAME, TMP) \ | |
45 | { \ | |
46 | *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \ | |
47 | *(TMP) = read_memory_integer (*(TMP) + 0x18, 4); \ | |
48 | } | |
49 | ||
50 | #define FRAME_BASE_BEFORE_SIGTRAMP(FRAME, TMP) \ | |
51 | { \ | |
52 | *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \ | |
53 | *(TMP) = read_memory_integer (*(TMP) + 0x8, 4); \ | |
54 | } | |
55 | ||
56 | #define FRAME_FIND_SAVED_REGS_IN_SIGTRAMP(FRAME, FSR) \ | |
57 | { \ | |
58 | int i; \ | |
59 | CORE_ADDR TMP; \ | |
60 | TMP = read_memory_integer ((FRAME)->frame + 0x4, 4); \ | |
61 | TMP = read_memory_integer (TMP + 0x10, 4); \ | |
62 | for (i = 0; i < NUM_REGS; i++) \ | |
63 | { \ | |
64 | if (i == SP_REGNUM) \ | |
65 | (FSR)->regs[SP_REGNUM] = read_memory_integer (TMP + SP_REGNUM * 4, 4); \ | |
66 | else \ | |
67 | (FSR)->regs[i] = TMP + i * 4; \ | |
68 | } \ | |
69 | } | |
70 | ||
71 | /* OSF1 does not need the pc space queue restored. */ | |
72 | #define NO_PC_SPACE_QUEUE_RESTORE | |
73 | ||
74 | /* The mach kernel uses the recovery counter to implement single | |
75 | stepping. While this greatly simplifies the kernel support | |
76 | necessary for single stepping, it unfortunately does the wrong | |
77 | thing in the presense of a nullified instruction (gives control | |
78 | back two insns after the nullifed insn). This is an artifact | |
79 | of the HP architecture (recovery counter doesn't tick for | |
80 | nullified insns). | |
81 | ||
82 | Do our best to avoid losing in such situations. */ | |
83 | #define INSTRUCTION_NULLIFIED \ | |
84 | (({ \ | |
85 | int ipsw = (int)read_register(IPSW_REGNUM); \ | |
86 | if (ipsw & PSW_N) \ | |
87 | { \ | |
88 | int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \ | |
89 | write_register(PCOQ_HEAD_REGNUM, pcoqt); \ | |
90 | write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \ | |
91 | write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \ | |
92 | stop_pc = pcoqt; \ | |
93 | } \ | |
c5aa993b | 94 | }), 0) |
c906108c SS |
95 | |
96 | /* It's mostly just the common stuff. */ | |
97 | ||
98 | #include "pa/tm-hppa.h" |