Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
76a9d10f MK |
3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006 |
4 | Free Software Foundation, Inc. | |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
23 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
24 | Boston, MA 02110-1301, USA. */ | |
29134980 OF |
25 | |
26 | #include "defs.h" | |
27 | #include "frame.h" | |
2e4b5889 OF |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
30 | #include "trad-frame.h" | |
31 | #include "dwarf2-frame.h" | |
29134980 OF |
32 | #include "symtab.h" |
33 | #include "inferior.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "gdbcore.h" | |
36 | #include "gdbcmd.h" | |
37 | #include "target.h" | |
38 | #include "value.h" | |
39 | #include "opcode/cris.h" | |
40 | #include "arch-utils.h" | |
41 | #include "regcache.h" | |
36482093 | 42 | #include "gdb_assert.h" |
29134980 OF |
43 | |
44 | /* To get entry_point_address. */ | |
9ab9195f | 45 | #include "objfiles.h" |
29134980 | 46 | |
a5f6c8f5 | 47 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 48 | #include "solib-svr4.h" |
9bbe19fb | 49 | #include "gdb_string.h" |
a89aa300 | 50 | #include "dis-asm.h" |
dbbff683 | 51 | |
29134980 OF |
52 | enum cris_num_regs |
53 | { | |
54 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
55 | NUM_FREGS = 0, | |
56 | ||
57 | /* There are 16 general registers. */ | |
58 | NUM_GENREGS = 16, | |
59 | ||
60 | /* There are 16 special registers. */ | |
c600d464 OF |
61 | NUM_SPECREGS = 16, |
62 | ||
63 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
64 | ||
65 | /* CRISv32 has 16 support registers. */ | |
66 | NUM_SUPPREGS = 16 | |
29134980 OF |
67 | }; |
68 | ||
69 | /* Register numbers of various important registers. | |
2e4b5889 | 70 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
71 | STR_REGNUM Contains the address of structure return values. |
72 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
73 | ARG1_REGNUM Contains the first parameter to a function. | |
74 | ARG2_REGNUM Contains the second parameter to a function. | |
75 | ARG3_REGNUM Contains the third parameter to a function. | |
76 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
77 | SP_REGNUM Contains address of top of stack. | |
78 | PC_REGNUM Contains address of next instruction. | |
79 | SRP_REGNUM Subroutine return pointer register. | |
80 | BRP_REGNUM Breakpoint return pointer register. */ | |
81 | ||
29134980 OF |
82 | enum cris_regnums |
83 | { | |
84 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 85 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 86 | CRIS_FP_REGNUM = 8, |
c600d464 | 87 | /* ABI related registers. */ |
29134980 OF |
88 | STR_REGNUM = 9, |
89 | RET_REGNUM = 10, | |
90 | ARG1_REGNUM = 10, | |
91 | ARG2_REGNUM = 11, | |
92 | ARG3_REGNUM = 12, | |
93 | ARG4_REGNUM = 13, | |
94 | ||
c600d464 | 95 | /* Registers which happen to be common. */ |
29134980 | 96 | VR_REGNUM = 17, |
c600d464 OF |
97 | MOF_REGNUM = 23, |
98 | SRP_REGNUM = 27, | |
99 | ||
100 | /* CRISv10 et. al. specific registers. */ | |
101 | P0_REGNUM = 16, | |
29134980 OF |
102 | P4_REGNUM = 20, |
103 | CCR_REGNUM = 21, | |
29134980 OF |
104 | P8_REGNUM = 24, |
105 | IBR_REGNUM = 25, | |
106 | IRP_REGNUM = 26, | |
29134980 | 107 | BAR_REGNUM = 28, |
2a9ecef2 | 108 | DCCR_REGNUM = 29, |
29134980 | 109 | BRP_REGNUM = 30, |
c600d464 OF |
110 | USP_REGNUM = 31, |
111 | ||
112 | /* CRISv32 specific registers. */ | |
113 | ACR_REGNUM = 15, | |
114 | BZ_REGNUM = 16, | |
115 | PID_REGNUM = 18, | |
116 | SRS_REGNUM = 19, | |
117 | WZ_REGNUM = 20, | |
118 | EXS_REGNUM = 21, | |
119 | EDA_REGNUM = 22, | |
120 | DZ_REGNUM = 24, | |
121 | EBP_REGNUM = 25, | |
122 | ERP_REGNUM = 26, | |
123 | NRP_REGNUM = 28, | |
124 | CCS_REGNUM = 29, | |
125 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
126 | SPC_REGNUM = 31, | |
127 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
128 | ||
129 | S0_REGNUM = 33, | |
130 | S1_REGNUM = 34, | |
131 | S2_REGNUM = 35, | |
132 | S3_REGNUM = 36, | |
133 | S4_REGNUM = 37, | |
134 | S5_REGNUM = 38, | |
135 | S6_REGNUM = 39, | |
136 | S7_REGNUM = 40, | |
137 | S8_REGNUM = 41, | |
138 | S9_REGNUM = 42, | |
139 | S10_REGNUM = 43, | |
140 | S11_REGNUM = 44, | |
141 | S12_REGNUM = 45, | |
142 | S13_REGNUM = 46, | |
143 | S14_REGNUM = 47, | |
144 | S15_REGNUM = 48, | |
29134980 OF |
145 | }; |
146 | ||
147 | extern const struct cris_spec_reg cris_spec_regs[]; | |
148 | ||
149 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
150 | register names and sizes. */ |
151 | static int usr_cmd_cris_version; | |
29134980 OF |
152 | |
153 | /* Indicates whether to trust the above variable. */ | |
154 | static int usr_cmd_cris_version_valid = 0; | |
155 | ||
41922353 OF |
156 | static const char cris_mode_normal[] = "normal"; |
157 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
158 | static const char *cris_modes[] = { |
159 | cris_mode_normal, | |
160 | cris_mode_guru, | |
161 | 0 | |
162 | }; | |
163 | ||
164 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
165 | type of break instruction among other things. */ | |
166 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
167 | ||
a5f6c8f5 OF |
168 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
169 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 170 | |
29134980 OF |
171 | /* CRIS architecture specific information. */ |
172 | struct gdbarch_tdep | |
173 | { | |
0e6bdb31 OF |
174 | int cris_version; |
175 | const char *cris_mode; | |
a5f6c8f5 | 176 | int cris_dwarf2_cfi; |
29134980 OF |
177 | }; |
178 | ||
179 | /* Functions for accessing target dependent data. */ | |
180 | ||
181 | static int | |
182 | cris_version (void) | |
183 | { | |
184 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
185 | } | |
186 | ||
0e6bdb31 OF |
187 | static const char * |
188 | cris_mode (void) | |
189 | { | |
190 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
191 | } | |
192 | ||
a5f6c8f5 OF |
193 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
194 | ||
195 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
196 | #define SIGTRAMP_OFFSET0 0 | |
197 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
198 | #define SIGTRAMP_OFFSET1 4 | |
199 | ||
200 | static const unsigned short sigtramp_code[] = | |
201 | { | |
202 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
203 | SIGTRAMP_INSN1 /* break 13 */ | |
204 | }; | |
205 | ||
206 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
207 | ||
208 | /* Note: same length as normal sigtramp code. */ | |
209 | ||
210 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 211 | { |
a5f6c8f5 OF |
212 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
213 | SIGTRAMP_INSN1 /* break 13 */ | |
214 | }; | |
215 | ||
216 | /* If PC is in a sigtramp routine, return the address of the start of | |
217 | the routine. Otherwise, return 0. */ | |
218 | ||
219 | static CORE_ADDR | |
220 | cris_sigtramp_start (struct frame_info *next_frame) | |
221 | { | |
222 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 223 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
224 | |
225 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
226 | return 0; | |
227 | ||
e2a2a3e8 | 228 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 229 | { |
e2a2a3e8 | 230 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
231 | return 0; |
232 | ||
233 | pc -= SIGTRAMP_OFFSET1; | |
234 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
235 | return 0; | |
236 | } | |
237 | ||
238 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
239 | return 0; | |
240 | ||
241 | return pc; | |
242 | } | |
243 | ||
244 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
245 | the routine. Otherwise, return 0. */ | |
246 | ||
247 | static CORE_ADDR | |
248 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
249 | { | |
250 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 251 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
252 | |
253 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
254 | return 0; | |
255 | ||
e2a2a3e8 | 256 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 257 | { |
e2a2a3e8 | 258 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
259 | return 0; |
260 | ||
261 | pc -= SIGTRAMP_OFFSET1; | |
262 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
263 | return 0; | |
264 | } | |
265 | ||
266 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
267 | return 0; | |
268 | ||
269 | return pc; | |
270 | } | |
271 | ||
272 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
273 | routine, return the address of the associated sigcontext structure. */ | |
274 | ||
275 | static CORE_ADDR | |
276 | cris_sigcontext_addr (struct frame_info *next_frame) | |
277 | { | |
278 | CORE_ADDR pc; | |
279 | CORE_ADDR sp; | |
280 | char buf[4]; | |
281 | ||
282 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
283 | sp = extract_unsigned_integer (buf, 4); | |
284 | ||
285 | /* Look for normal sigtramp frame first. */ | |
286 | pc = cris_sigtramp_start (next_frame); | |
287 | if (pc) | |
288 | { | |
289 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
290 | struct sigcontext as its first member, meaning the SP points to | |
291 | it already. */ | |
292 | return sp; | |
293 | } | |
294 | ||
295 | pc = cris_rt_sigtramp_start (next_frame); | |
296 | if (pc) | |
297 | { | |
298 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
299 | a struct ucontext, which in turn contains a struct sigcontext. | |
300 | Magic digging: | |
301 | 4 + 4 + 128 to struct ucontext, then | |
302 | 4 + 4 + 12 to struct sigcontext. */ | |
303 | return (sp + 156); | |
304 | } | |
305 | ||
8a3fe4f8 | 306 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 307 | return 0; |
29134980 OF |
308 | } |
309 | ||
2e4b5889 | 310 | struct cris_unwind_cache |
29134980 | 311 | { |
2e4b5889 OF |
312 | /* The previous frame's inner most stack address. Used as this |
313 | frame ID's stack_addr. */ | |
314 | CORE_ADDR prev_sp; | |
315 | /* The frame's base, optionally used by the high-level debug info. */ | |
316 | CORE_ADDR base; | |
317 | int size; | |
318 | /* How far the SP and r8 (FP) have been offset from the start of | |
319 | the stack frame (as defined by the previous frame's stack | |
320 | pointer). */ | |
321 | LONGEST sp_offset; | |
322 | LONGEST r8_offset; | |
323 | int uses_frame; | |
324 | ||
325 | /* From old frame_extra_info struct. */ | |
29134980 OF |
326 | CORE_ADDR return_pc; |
327 | int leaf_function; | |
2e4b5889 OF |
328 | |
329 | /* Table indicating the location of each and every register. */ | |
330 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
331 | }; |
332 | ||
a5f6c8f5 OF |
333 | static struct cris_unwind_cache * |
334 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
335 | void **this_cache) | |
336 | { | |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
338 | struct cris_unwind_cache *info; | |
339 | CORE_ADDR pc; | |
340 | CORE_ADDR sp; | |
341 | CORE_ADDR addr; | |
342 | char buf[4]; | |
343 | int i; | |
344 | ||
345 | if ((*this_cache)) | |
346 | return (*this_cache); | |
347 | ||
348 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
349 | (*this_cache) = info; | |
350 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
351 | ||
352 | /* Zero all fields. */ | |
353 | info->prev_sp = 0; | |
354 | info->base = 0; | |
355 | info->size = 0; | |
356 | info->sp_offset = 0; | |
357 | info->r8_offset = 0; | |
358 | info->uses_frame = 0; | |
359 | info->return_pc = 0; | |
360 | info->leaf_function = 0; | |
361 | ||
362 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
363 | info->base = extract_unsigned_integer (buf, 4); | |
364 | ||
365 | addr = cris_sigcontext_addr (next_frame); | |
366 | ||
367 | /* Layout of the sigcontext struct: | |
368 | struct sigcontext { | |
369 | struct pt_regs regs; | |
370 | unsigned long oldmask; | |
371 | unsigned long usp; | |
372 | }; */ | |
373 | ||
c600d464 OF |
374 | if (tdep->cris_version == 10) |
375 | { | |
376 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
377 | struct pt_regs. */ | |
378 | for (i = 0; i <= 13; i++) | |
379 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
380 | ||
381 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
382 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
383 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
384 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
385 | it though since that will mean that the backtrace will show a PC | |
386 | different from what is shown when stopped. */ | |
387 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
388 | info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; | |
389 | info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); | |
390 | } | |
391 | else | |
392 | { | |
393 | /* CRISv32. */ | |
394 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
395 | struct pt_regs. */ | |
396 | for (i = 0; i <= 13; i++) | |
397 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
398 | ||
399 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
400 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
401 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
402 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
403 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
404 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
405 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
406 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
407 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
408 | ||
409 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
410 | be wrong at this point. This problem manifests itself in the | |
411 | sigaltstack.exp test case, which occasionally generates FAILs when | |
412 | the signal is received while in a delay slot. | |
413 | ||
414 | This could be solved by a couple of read_memory_unsigned_integer and a | |
415 | trad_frame_set_value. */ | |
416 | info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM]; | |
417 | ||
418 | info->saved_regs[SP_REGNUM].addr = addr + (25 * 4); | |
419 | } | |
a5f6c8f5 OF |
420 | |
421 | return info; | |
422 | } | |
423 | ||
424 | static void | |
425 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
426 | struct frame_id *this_id) | |
427 | { | |
428 | struct cris_unwind_cache *cache = | |
429 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
430 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
431 | } | |
432 | ||
433 | /* Forward declaration. */ | |
434 | ||
435 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
436 | void **this_prologue_cache, | |
437 | int regnum, int *optimizedp, | |
438 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 439 | int *realnump, gdb_byte *bufferp); |
a5f6c8f5 OF |
440 | static void |
441 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
442 | void **this_cache, | |
443 | int regnum, int *optimizedp, | |
444 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 445 | int *realnump, gdb_byte *valuep) |
a5f6c8f5 OF |
446 | { |
447 | /* Make sure we've initialized the cache. */ | |
448 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
449 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
450 | optimizedp, lvalp, addrp, realnump, valuep); | |
451 | } | |
452 | ||
453 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
454 | { | |
455 | SIGTRAMP_FRAME, | |
456 | cris_sigtramp_frame_this_id, | |
457 | cris_sigtramp_frame_prev_register | |
458 | }; | |
459 | ||
460 | static const struct frame_unwind * | |
461 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
462 | { | |
463 | if (cris_sigtramp_start (next_frame) | |
464 | || cris_rt_sigtramp_start (next_frame)) | |
465 | return &cris_sigtramp_frame_unwind; | |
466 | ||
467 | return NULL; | |
468 | } | |
469 | ||
c600d464 OF |
470 | int |
471 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
472 | struct frame_info *this_frame) | |
473 | { | |
474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
475 | ULONGEST erp; | |
476 | int ret = 0; | |
477 | char buf[4]; | |
478 | ||
0e6bdb31 OF |
479 | if (cris_mode () == cris_mode_guru) |
480 | { | |
481 | frame_unwind_register (this_frame, NRP_REGNUM, buf); | |
482 | } | |
483 | else | |
484 | { | |
485 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
486 | } | |
487 | ||
c600d464 OF |
488 | erp = extract_unsigned_integer (buf, 4); |
489 | ||
490 | if (erp & 0x1) | |
491 | { | |
492 | /* In delay slot - check if there's a breakpoint at the preceding | |
493 | instruction. */ | |
494 | if (breakpoint_here_p (erp & ~0x1)) | |
495 | ret = 1; | |
496 | } | |
497 | return ret; | |
498 | } | |
499 | ||
500 | /* Hardware watchpoint support. */ | |
501 | ||
502 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
503 | (any combination of read/write is fine). */ | |
504 | ||
505 | int | |
506 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
507 | { | |
508 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
509 | ||
510 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
511 | ||
512 | if (tdep->cris_version != 32) | |
513 | return 0; | |
514 | else | |
515 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
516 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
517 | || type == bp_hardware_watchpoint) && count <= 6) | |
518 | || (type == bp_hardware_breakpoint && count <= 1)); | |
519 | } | |
520 | ||
521 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
522 | which have no alignment or length restrictions. */ | |
523 | ||
524 | int | |
525 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
526 | { | |
527 | return 1; | |
528 | } | |
529 | ||
530 | /* If the inferior has some watchpoint that triggered, return the | |
531 | address associated with that watchpoint. Otherwise, return | |
532 | zero. */ | |
533 | ||
534 | CORE_ADDR | |
535 | cris_stopped_data_address (void) | |
536 | { | |
537 | CORE_ADDR eda; | |
538 | eda = read_register (EDA_REGNUM); | |
539 | return eda; | |
540 | } | |
541 | ||
29134980 | 542 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 543 | |
29134980 OF |
544 | typedef |
545 | struct instruction_environment | |
546 | { | |
547 | unsigned long reg[NUM_GENREGS]; | |
548 | unsigned long preg[NUM_SPECREGS]; | |
549 | unsigned long branch_break_address; | |
550 | unsigned long delay_slot_pc; | |
551 | unsigned long prefix_value; | |
552 | int branch_found; | |
553 | int prefix_found; | |
554 | int invalid; | |
555 | int slot_needed; | |
556 | int delay_slot_pc_active; | |
557 | int xflag_found; | |
558 | int disable_interrupt; | |
559 | } inst_env_type; | |
560 | ||
561 | /* Save old breakpoints in order to restore the state before a single_step. | |
562 | At most, two breakpoints will have to be remembered. */ | |
563 | typedef | |
564 | char binsn_quantum[BREAKPOINT_MAX]; | |
565 | static binsn_quantum break_mem[2]; | |
566 | static CORE_ADDR next_pc = 0; | |
567 | static CORE_ADDR branch_target_address = 0; | |
568 | static unsigned char branch_break_inserted = 0; | |
569 | ||
570 | /* Machine-dependencies in CRIS for opcodes. */ | |
571 | ||
572 | /* Instruction sizes. */ | |
573 | enum cris_instruction_sizes | |
574 | { | |
575 | INST_BYTE_SIZE = 0, | |
576 | INST_WORD_SIZE = 1, | |
577 | INST_DWORD_SIZE = 2 | |
578 | }; | |
579 | ||
580 | /* Addressing modes. */ | |
581 | enum cris_addressing_modes | |
582 | { | |
583 | REGISTER_MODE = 1, | |
584 | INDIRECT_MODE = 2, | |
585 | AUTOINC_MODE = 3 | |
586 | }; | |
587 | ||
588 | /* Prefix addressing modes. */ | |
589 | enum cris_prefix_addressing_modes | |
590 | { | |
591 | PREFIX_INDEX_MODE = 2, | |
592 | PREFIX_ASSIGN_MODE = 3, | |
593 | ||
594 | /* Handle immediate byte offset addressing mode prefix format. */ | |
595 | PREFIX_OFFSET_MODE = 2 | |
596 | }; | |
597 | ||
598 | /* Masks for opcodes. */ | |
599 | enum cris_opcode_masks | |
600 | { | |
601 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
602 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
603 | SIGNED_BYTE_MASK = 0x80, | |
604 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
605 | SIGNED_WORD_MASK = 0x8000, | |
606 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
607 | SIGNED_DWORD_MASK = 0x80000000, | |
608 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
609 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
610 | }; | |
611 | ||
612 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
613 | Bit 15 - 12 Operand2 | |
614 | 11 - 10 Mode | |
615 | 9 - 6 Opcode | |
616 | 5 - 4 Size | |
617 | 3 - 0 Operand1 */ | |
618 | ||
619 | static int | |
620 | cris_get_operand2 (unsigned short insn) | |
621 | { | |
622 | return ((insn & 0xF000) >> 12); | |
623 | } | |
624 | ||
625 | static int | |
626 | cris_get_mode (unsigned short insn) | |
627 | { | |
628 | return ((insn & 0x0C00) >> 10); | |
629 | } | |
630 | ||
631 | static int | |
632 | cris_get_opcode (unsigned short insn) | |
633 | { | |
634 | return ((insn & 0x03C0) >> 6); | |
635 | } | |
636 | ||
637 | static int | |
638 | cris_get_size (unsigned short insn) | |
639 | { | |
640 | return ((insn & 0x0030) >> 4); | |
641 | } | |
642 | ||
643 | static int | |
644 | cris_get_operand1 (unsigned short insn) | |
645 | { | |
646 | return (insn & 0x000F); | |
647 | } | |
648 | ||
649 | /* Additional functions in order to handle opcodes. */ | |
650 | ||
29134980 OF |
651 | static int |
652 | cris_get_quick_value (unsigned short insn) | |
653 | { | |
654 | return (insn & 0x003F); | |
655 | } | |
656 | ||
657 | static int | |
658 | cris_get_bdap_quick_offset (unsigned short insn) | |
659 | { | |
660 | return (insn & 0x00FF); | |
661 | } | |
662 | ||
663 | static int | |
664 | cris_get_branch_short_offset (unsigned short insn) | |
665 | { | |
666 | return (insn & 0x00FF); | |
667 | } | |
668 | ||
669 | static int | |
670 | cris_get_asr_shift_steps (unsigned long value) | |
671 | { | |
672 | return (value & 0x3F); | |
673 | } | |
674 | ||
29134980 OF |
675 | static int |
676 | cris_get_clear_size (unsigned short insn) | |
677 | { | |
678 | return ((insn) & 0xC000); | |
679 | } | |
680 | ||
681 | static int | |
682 | cris_is_signed_extend_bit_on (unsigned short insn) | |
683 | { | |
684 | return (((insn) & 0x20) == 0x20); | |
685 | } | |
686 | ||
687 | static int | |
688 | cris_is_xflag_bit_on (unsigned short insn) | |
689 | { | |
690 | return (((insn) & 0x1000) == 0x1000); | |
691 | } | |
692 | ||
693 | static void | |
694 | cris_set_size_to_dword (unsigned short *insn) | |
695 | { | |
696 | *insn &= 0xFFCF; | |
697 | *insn |= 0x20; | |
698 | } | |
699 | ||
8535cb38 | 700 | static signed char |
29134980 OF |
701 | cris_get_signed_offset (unsigned short insn) |
702 | { | |
8535cb38 | 703 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
704 | } |
705 | ||
706 | /* Calls an op function given the op-type, working on the insn and the | |
707 | inst_env. */ | |
708 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
709 | ||
29134980 OF |
710 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
711 | struct gdbarch_list *); | |
712 | ||
29134980 OF |
713 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
714 | ||
a5f6c8f5 OF |
715 | static void set_cris_version (char *ignore_args, int from_tty, |
716 | struct cmd_list_element *c); | |
29134980 | 717 | |
0e6bdb31 OF |
718 | static void set_cris_mode (char *ignore_args, int from_tty, |
719 | struct cmd_list_element *c); | |
720 | ||
a5f6c8f5 OF |
721 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
722 | struct cmd_list_element *c); | |
29134980 | 723 | |
2e4b5889 OF |
724 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
725 | struct frame_info *next_frame, | |
726 | struct cris_unwind_cache *info); | |
727 | ||
5114e29d OF |
728 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
729 | struct frame_info *next_frame, | |
730 | struct cris_unwind_cache *info); | |
731 | ||
2e4b5889 OF |
732 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
733 | struct frame_info *next_frame); | |
734 | ||
735 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
736 | struct frame_info *next_frame); | |
737 | ||
738 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
739 | order. The below implements a FILO (stack) to do this. |
740 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
741 | |
742 | struct stack_item | |
743 | { | |
744 | int len; | |
745 | struct stack_item *prev; | |
746 | void *data; | |
747 | }; | |
748 | ||
749 | static struct stack_item * | |
750 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
751 | { | |
752 | struct stack_item *si; | |
753 | si = xmalloc (sizeof (struct stack_item)); | |
754 | si->data = xmalloc (len); | |
755 | si->len = len; | |
756 | si->prev = prev; | |
757 | memcpy (si->data, contents, len); | |
758 | return si; | |
759 | } | |
760 | ||
761 | static struct stack_item * | |
762 | pop_stack_item (struct stack_item *si) | |
763 | { | |
764 | struct stack_item *dead = si; | |
765 | si = si->prev; | |
766 | xfree (dead->data); | |
767 | xfree (dead); | |
768 | return si; | |
769 | } | |
770 | ||
771 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
772 | the saved registers of frame described by FRAME_INFO. This | |
773 | includes special registers such as pc and fp saved in special ways | |
774 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 775 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
776 | |
777 | struct cris_unwind_cache * | |
778 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
779 | void **this_prologue_cache) | |
780 | { | |
781 | CORE_ADDR pc; | |
782 | struct cris_unwind_cache *info; | |
783 | int i; | |
784 | ||
785 | if ((*this_prologue_cache)) | |
786 | return (*this_prologue_cache); | |
787 | ||
788 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
789 | (*this_prologue_cache) = info; | |
790 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
791 | ||
792 | /* Zero all fields. */ | |
793 | info->prev_sp = 0; | |
794 | info->base = 0; | |
795 | info->size = 0; | |
796 | info->sp_offset = 0; | |
797 | info->r8_offset = 0; | |
798 | info->uses_frame = 0; | |
799 | info->return_pc = 0; | |
800 | info->leaf_function = 0; | |
801 | ||
802 | /* Prologue analysis does the rest... */ | |
5114e29d OF |
803 | if (cris_version () == 32) |
804 | crisv32_scan_prologue (frame_func_unwind (next_frame), next_frame, info); | |
805 | else | |
806 | cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info); | |
2e4b5889 OF |
807 | |
808 | return info; | |
809 | } | |
810 | ||
811 | /* Given a GDB frame, determine the address of the calling function's | |
812 | frame. This will be used to create a new GDB frame struct. */ | |
813 | ||
814 | static void | |
815 | cris_frame_this_id (struct frame_info *next_frame, | |
816 | void **this_prologue_cache, | |
817 | struct frame_id *this_id) | |
818 | { | |
819 | struct cris_unwind_cache *info | |
820 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
821 | CORE_ADDR base; | |
822 | CORE_ADDR func; | |
823 | struct frame_id id; | |
824 | ||
825 | /* The FUNC is easy. */ | |
826 | func = frame_func_unwind (next_frame); | |
827 | ||
828 | /* Hopefully the prologue analysis either correctly determined the | |
829 | frame's base (which is the SP from the previous frame), or set | |
830 | that base to "NULL". */ | |
831 | base = info->prev_sp; | |
832 | if (base == 0) | |
833 | return; | |
834 | ||
835 | id = frame_id_build (base, func); | |
836 | ||
837 | (*this_id) = id; | |
838 | } | |
839 | ||
840 | static void | |
841 | cris_frame_prev_register (struct frame_info *next_frame, | |
842 | void **this_prologue_cache, | |
843 | int regnum, int *optimizedp, | |
844 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 845 | int *realnump, gdb_byte *bufferp) |
2e4b5889 OF |
846 | { |
847 | struct cris_unwind_cache *info | |
848 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
849 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
850 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
851 | } |
852 | ||
853 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
854 | dummy frame. The frame ID's base needs to match the TOS value | |
855 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
856 | breakpoint. */ | |
857 | ||
858 | static struct frame_id | |
859 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
860 | { | |
861 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
862 | frame_pc_unwind (next_frame)); | |
863 | } | |
864 | ||
865 | static CORE_ADDR | |
866 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
867 | { | |
868 | /* Align to the size of an instruction (so that they can safely be | |
869 | pushed onto the stack). */ | |
870 | return sp & ~3; | |
871 | } | |
872 | ||
873 | static CORE_ADDR | |
874 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
875 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
876 | struct value **args, int nargs, | |
877 | struct type *value_type, | |
878 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
879 | { | |
880 | /* Allocate space sufficient for a breakpoint. */ | |
881 | sp = (sp - 4) & ~3; | |
882 | /* Store the address of that breakpoint */ | |
883 | *bp_addr = sp; | |
884 | /* CRIS always starts the call at the callee's entry point. */ | |
885 | *real_pc = funaddr; | |
886 | return sp; | |
887 | } | |
888 | ||
889 | static CORE_ADDR | |
7d9b040b | 890 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
891 | struct regcache *regcache, CORE_ADDR bp_addr, |
892 | int nargs, struct value **args, CORE_ADDR sp, | |
893 | int struct_return, CORE_ADDR struct_addr) | |
894 | { | |
895 | int stack_alloc; | |
896 | int stack_offset; | |
897 | int argreg; | |
898 | int argnum; | |
899 | ||
900 | CORE_ADDR regval; | |
901 | ||
902 | /* The function's arguments and memory allocated by gdb for the arguments to | |
903 | point at reside in separate areas on the stack. | |
904 | Both frame pointers grow toward higher addresses. */ | |
905 | CORE_ADDR fp_arg; | |
906 | CORE_ADDR fp_mem; | |
907 | ||
908 | struct stack_item *si = NULL; | |
909 | ||
a5f6c8f5 | 910 | /* Push the return address. */ |
2e4b5889 OF |
911 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
912 | ||
913 | /* Are we returning a value using a structure return or a normal value | |
914 | return? struct_addr is the address of the reserved space for the return | |
915 | structure to be written on the stack. */ | |
916 | if (struct_return) | |
917 | { | |
918 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
919 | } | |
920 | ||
921 | /* Now load as many as possible of the first arguments into registers, | |
922 | and push the rest onto the stack. */ | |
923 | argreg = ARG1_REGNUM; | |
924 | stack_offset = 0; | |
925 | ||
926 | for (argnum = 0; argnum < nargs; argnum++) | |
927 | { | |
928 | int len; | |
929 | char *val; | |
930 | int reg_demand; | |
931 | int i; | |
932 | ||
4991999e | 933 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 934 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
935 | |
936 | /* How may registers worth of storage do we need for this argument? */ | |
937 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
938 | ||
939 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
940 | { | |
941 | /* Data passed by value. Fits in available register(s). */ | |
942 | for (i = 0; i < reg_demand; i++) | |
943 | { | |
944 | regcache_cooked_write_unsigned (regcache, argreg, | |
945 | *(unsigned long *) val); | |
946 | argreg++; | |
947 | val += 4; | |
948 | } | |
949 | } | |
950 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
951 | { | |
952 | /* Data passed by value. Does not fit in available register(s). | |
953 | Use the register(s) first, then the stack. */ | |
954 | for (i = 0; i < reg_demand; i++) | |
955 | { | |
956 | if (argreg <= ARG4_REGNUM) | |
957 | { | |
958 | regcache_cooked_write_unsigned (regcache, argreg, | |
959 | *(unsigned long *) val); | |
960 | argreg++; | |
961 | val += 4; | |
962 | } | |
963 | else | |
964 | { | |
965 | /* Push item for later so that pushed arguments | |
966 | come in the right order. */ | |
967 | si = push_stack_item (si, val, 4); | |
968 | val += 4; | |
969 | } | |
970 | } | |
971 | } | |
972 | else if (len > (2 * 4)) | |
973 | { | |
974 | /* FIXME */ | |
e2e0b3e5 | 975 | internal_error (__FILE__, __LINE__, _("We don't do this")); |
2e4b5889 OF |
976 | } |
977 | else | |
978 | { | |
979 | /* Data passed by value. No available registers. Put it on | |
980 | the stack. */ | |
981 | si = push_stack_item (si, val, len); | |
982 | } | |
983 | } | |
984 | ||
985 | while (si) | |
986 | { | |
987 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
988 | the function prologue. */ | |
989 | sp = (sp - si->len) & ~3; | |
990 | write_memory (sp, si->data, si->len); | |
991 | si = pop_stack_item (si); | |
992 | } | |
993 | ||
994 | /* Finally, update the SP register. */ | |
995 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
996 | ||
997 | return sp; | |
998 | } | |
999 | ||
e2a2a3e8 OF |
1000 | static const struct frame_unwind cris_frame_unwind = |
1001 | { | |
2e4b5889 OF |
1002 | NORMAL_FRAME, |
1003 | cris_frame_this_id, | |
1004 | cris_frame_prev_register | |
1005 | }; | |
1006 | ||
1007 | const struct frame_unwind * | |
1008 | cris_frame_sniffer (struct frame_info *next_frame) | |
1009 | { | |
1010 | return &cris_frame_unwind; | |
1011 | } | |
1012 | ||
1013 | static CORE_ADDR | |
1014 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1015 | { | |
1016 | struct cris_unwind_cache *info | |
1017 | = cris_frame_unwind_cache (next_frame, this_cache); | |
1018 | return info->base; | |
1019 | } | |
1020 | ||
e2a2a3e8 OF |
1021 | static const struct frame_base cris_frame_base = |
1022 | { | |
2e4b5889 OF |
1023 | &cris_frame_unwind, |
1024 | cris_frame_base_address, | |
1025 | cris_frame_base_address, | |
1026 | cris_frame_base_address | |
1027 | }; | |
1028 | ||
29134980 OF |
1029 | /* Frames information. The definition of the struct frame_info is |
1030 | ||
1031 | CORE_ADDR frame | |
1032 | CORE_ADDR pc | |
5a203e44 | 1033 | enum frame_type type; |
29134980 OF |
1034 | CORE_ADDR return_pc |
1035 | int leaf_function | |
1036 | ||
1037 | If the compilation option -fno-omit-frame-pointer is present the | |
1038 | variable frame will be set to the content of R8 which is the frame | |
1039 | pointer register. | |
1040 | ||
1041 | The variable pc contains the address where execution is performed | |
1042 | in the present frame. The innermost frame contains the current content | |
1043 | of the register PC. All other frames contain the content of the | |
1044 | register PC in the next frame. | |
1045 | ||
5a203e44 AC |
1046 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1047 | (associated with a signal handler), dummy (associated with a dummy | |
1048 | frame). | |
29134980 OF |
1049 | |
1050 | The variable return_pc contains the address where execution should be | |
1051 | resumed when the present frame has finished, the return address. | |
1052 | ||
1053 | The variable leaf_function is 1 if the return address is in the register | |
1054 | SRP, and 0 if it is on the stack. | |
1055 | ||
1056 | Prologue instructions C-code. | |
1057 | The prologue may consist of (-fno-omit-frame-pointer) | |
1058 | 1) 2) | |
1059 | push srp | |
1060 | push r8 push r8 | |
1061 | move.d sp,r8 move.d sp,r8 | |
1062 | subq X,sp subq X,sp | |
1063 | movem rY,[sp] movem rY,[sp] | |
1064 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1065 | ||
1066 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1067 | ||
1068 | Note that this assumption is extremely brittle, and will break at the | |
1069 | slightest change in GCC's prologue. | |
1070 | ||
1071 | If local variables are declared or register contents are saved on stack | |
1072 | the subq-instruction will be present with X as the number of bytes | |
1073 | needed for storage. The reshuffle with respect to r8 may be performed | |
1074 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1075 | The offset U should be representable by a signed 8-bit value in all cases. | |
1076 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1077 | by another word containing the instruction. | |
1078 | ||
1079 | Degenerate cases: | |
1080 | 3) | |
1081 | push r8 | |
1082 | move.d sp,r8 | |
1083 | move.d r8,sp | |
1084 | pop r8 | |
1085 | ||
1086 | Prologue instructions C++-code. | |
1087 | Case 1) and 2) in the C-code may be followed by | |
1088 | ||
1089 | move.d r10,rS ; this | |
1090 | move.d r11,rT ; P1 | |
1091 | move.d r12,rU ; P2 | |
1092 | move.d r13,rV ; P3 | |
1093 | move.S [r8+U],rZ ; P4 | |
1094 | ||
1095 | if any of the call parameters are stored. The host expects these | |
1096 | instructions to be executed in order to get the call parameters right. */ | |
1097 | ||
1098 | /* Examine the prologue of a function. The variable ip is the address of | |
1099 | the first instruction of the prologue. The variable limit is the address | |
1100 | of the first instruction after the prologue. The variable fi contains the | |
1101 | information in struct frame_info. The variable frameless_p controls whether | |
1102 | the entire prologue is examined (0) or just enough instructions to | |
1103 | determine that it is a prologue (1). */ | |
1104 | ||
a78f21af | 1105 | static CORE_ADDR |
2e4b5889 OF |
1106 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1107 | struct cris_unwind_cache *info) | |
29134980 OF |
1108 | { |
1109 | /* Present instruction. */ | |
1110 | unsigned short insn; | |
1111 | ||
1112 | /* Next instruction, lookahead. */ | |
1113 | unsigned short insn_next; | |
1114 | int regno; | |
1115 | ||
1116 | /* Is there a push fp? */ | |
1117 | int have_fp; | |
1118 | ||
1119 | /* Number of byte on stack used for local variables and movem. */ | |
1120 | int val; | |
1121 | ||
1122 | /* Highest register number in a movem. */ | |
1123 | int regsave; | |
1124 | ||
1125 | /* move.d r<source_register>,rS */ | |
1126 | short source_register; | |
1127 | ||
2e4b5889 OF |
1128 | /* Scan limit. */ |
1129 | int limit; | |
29134980 | 1130 | |
2e4b5889 OF |
1131 | /* This frame is with respect to a leaf until a push srp is found. */ |
1132 | if (info) | |
1133 | { | |
1134 | info->leaf_function = 1; | |
1135 | } | |
29134980 OF |
1136 | |
1137 | /* Assume nothing on stack. */ | |
1138 | val = 0; | |
1139 | regsave = -1; | |
1140 | ||
2e4b5889 OF |
1141 | /* If we were called without a next_frame, that means we were called |
1142 | from cris_skip_prologue which already tried to find the end of the | |
1143 | prologue through the symbol information. 64 instructions past current | |
1144 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1145 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1146 | |
29134980 | 1147 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1148 | while (pc > 0 && pc < limit) |
29134980 | 1149 | { |
2e4b5889 OF |
1150 | insn = read_memory_unsigned_integer (pc, 2); |
1151 | pc += 2; | |
29134980 OF |
1152 | if (insn == 0xE1FC) |
1153 | { | |
1154 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1155 | insn_next = read_memory_unsigned_integer (pc, 2); |
1156 | pc += 2; | |
29134980 | 1157 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1158 | if (info) |
1159 | { | |
1160 | info->sp_offset += 4; | |
1161 | } | |
dbbff683 OF |
1162 | /* This check, meant to recognize srp, used to be regno == |
1163 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1164 | if (insn_next == 0xBE7E) | |
29134980 | 1165 | { |
2e4b5889 OF |
1166 | if (info) |
1167 | { | |
1168 | info->leaf_function = 0; | |
1169 | } | |
29134980 | 1170 | } |
b4206d25 OF |
1171 | else if (insn_next == 0x8FEE) |
1172 | { | |
1173 | /* push $r8 */ | |
1174 | if (info) | |
1175 | { | |
1176 | info->r8_offset = info->sp_offset; | |
1177 | } | |
1178 | } | |
29134980 OF |
1179 | } |
1180 | else if (insn == 0x866E) | |
1181 | { | |
1182 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1183 | if (info) |
1184 | { | |
1185 | info->uses_frame = 1; | |
2e4b5889 | 1186 | } |
29134980 OF |
1187 | continue; |
1188 | } | |
1189 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1190 | && cris_get_mode (insn) == 0x0000 | |
1191 | && cris_get_opcode (insn) == 0x000A) | |
1192 | { | |
1193 | /* subq <val>,sp */ | |
2e4b5889 OF |
1194 | if (info) |
1195 | { | |
1196 | info->sp_offset += cris_get_quick_value (insn); | |
1197 | } | |
29134980 OF |
1198 | } |
1199 | else if (cris_get_mode (insn) == 0x0002 | |
1200 | && cris_get_opcode (insn) == 0x000F | |
1201 | && cris_get_size (insn) == 0x0003 | |
1202 | && cris_get_operand1 (insn) == SP_REGNUM) | |
1203 | { | |
1204 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1205 | regsave = cris_get_operand2 (insn); |
1206 | } | |
1207 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1208 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1209 | && (cris_get_signed_offset (insn) < 0)) | |
1210 | { | |
1211 | /* Immediate byte offset addressing prefix word with sp as base | |
1212 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1213 | is between 64 and 128. | |
1214 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1215 | if (info) |
1216 | { | |
1217 | info->sp_offset += -cris_get_signed_offset (insn); | |
1218 | } | |
1219 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1220 | pc += 2; | |
29134980 OF |
1221 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1222 | && cris_get_opcode (insn_next) == 0x000F | |
1223 | && cris_get_size (insn_next) == 0x0003 | |
1224 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
1225 | { | |
29134980 OF |
1226 | regsave = cris_get_operand2 (insn_next); |
1227 | } | |
1228 | else | |
1229 | { | |
1230 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1231 | pc -= 4; |
29134980 OF |
1232 | break; |
1233 | } | |
1234 | } | |
1235 | else if (cris_get_mode (insn) == 0x0001 | |
1236 | && cris_get_opcode (insn) == 0x0009 | |
1237 | && cris_get_size (insn) == 0x0002) | |
1238 | { | |
1239 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1240 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1241 | |
1242 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1243 | like (this example taken from relocate_doit): | |
1244 | move.d $pc,$r0 | |
1245 | sub.d 0xfffef426,$r0 | |
1246 | which isn't covered by the source_register check below. Question | |
1247 | is whether to add a check for this combo, or make better use of | |
1248 | the limit variable instead. */ | |
29134980 OF |
1249 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1250 | { | |
1251 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1252 | pc -= 2; |
29134980 OF |
1253 | break; |
1254 | } | |
1255 | } | |
2e4b5889 | 1256 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1257 | /* The size is a fixed-size. */ |
1258 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1259 | /* A negative offset. */ | |
1260 | && (cris_get_signed_offset (insn) < 0)) | |
1261 | { | |
1262 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1263 | insn_next = read_memory_unsigned_integer (pc, 2); |
1264 | pc += 2; | |
29134980 OF |
1265 | regno = cris_get_operand2 (insn_next); |
1266 | if ((regno >= 0 && regno < SP_REGNUM) | |
1267 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1268 | && cris_get_opcode (insn_next) == 0x000F) | |
1269 | { | |
1270 | /* move.S rZ,[r8-U] */ | |
1271 | continue; | |
1272 | } | |
1273 | else | |
1274 | { | |
1275 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1276 | pc -= 4; |
29134980 OF |
1277 | break; |
1278 | } | |
1279 | } | |
2e4b5889 | 1280 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1281 | /* The size is a fixed-size. */ |
1282 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1283 | /* A positive offset. */ | |
1284 | && (cris_get_signed_offset (insn) > 0)) | |
1285 | { | |
1286 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1287 | insn_next = read_memory_unsigned_integer (pc, 2); |
1288 | pc += 2; | |
29134980 OF |
1289 | regno = cris_get_operand2 (insn_next); |
1290 | if ((regno >= 0 && regno < SP_REGNUM) | |
1291 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1292 | && cris_get_opcode (insn_next) == 0x0009 | |
1293 | && cris_get_operand1 (insn_next) == regno) | |
1294 | { | |
1295 | /* move.S [r8+U],rZ */ | |
1296 | continue; | |
1297 | } | |
1298 | else | |
1299 | { | |
1300 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1301 | pc -= 4; |
29134980 OF |
1302 | break; |
1303 | } | |
1304 | } | |
1305 | else | |
1306 | { | |
1307 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1308 | pc -= 2; |
29134980 OF |
1309 | break; |
1310 | } | |
1311 | } | |
29134980 | 1312 | |
2e4b5889 OF |
1313 | /* We only want to know the end of the prologue when next_frame and info |
1314 | are NULL (called from cris_skip_prologue i.e.). */ | |
1315 | if (next_frame == NULL && info == NULL) | |
1316 | { | |
1317 | return pc; | |
1318 | } | |
29134980 | 1319 | |
2e4b5889 OF |
1320 | info->size = info->sp_offset; |
1321 | ||
1322 | /* Compute the previous frame's stack pointer (which is also the | |
1323 | frame's ID's stack address), and this frame's base pointer. */ | |
1324 | if (info->uses_frame) | |
29134980 | 1325 | { |
2e4b5889 OF |
1326 | ULONGEST this_base; |
1327 | /* The SP was moved to the FP. This indicates that a new frame | |
1328 | was created. Get THIS frame's FP value by unwinding it from | |
1329 | the next frame. */ | |
1330 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1331 | &this_base); | |
1332 | info->base = this_base; | |
b4206d25 OF |
1333 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1334 | ||
2e4b5889 OF |
1335 | /* The FP points at the last saved register. Adjust the FP back |
1336 | to before the first saved register giving the SP. */ | |
1337 | info->prev_sp = info->base + info->r8_offset; | |
1338 | } | |
1339 | else | |
1340 | { | |
1341 | ULONGEST this_base; | |
1342 | /* Assume that the FP is this frame's SP but with that pushed | |
1343 | stack space added back. */ | |
1344 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1345 | info->base = this_base; | |
1346 | info->prev_sp = info->base + info->size; | |
1347 | } | |
29134980 | 1348 | |
2e4b5889 OF |
1349 | /* Calculate the addresses for the saved registers on the stack. */ |
1350 | /* FIXME: The address calculation should really be done on the fly while | |
1351 | we're analyzing the prologue (we only hold one regsave value as it is | |
1352 | now). */ | |
1353 | val = info->sp_offset; | |
1354 | ||
1355 | for (regno = regsave; regno >= 0; regno--) | |
1356 | { | |
1357 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1358 | val -= 4; | |
1359 | } | |
1360 | ||
1361 | /* The previous frame's SP needed to be computed. Save the computed | |
1362 | value. */ | |
1363 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
1364 | ||
1365 | if (!info->leaf_function) | |
1366 | { | |
b4206d25 OF |
1367 | /* SRP saved on the stack. But where? */ |
1368 | if (info->r8_offset == 0) | |
1369 | { | |
1370 | /* R8 not pushed yet. */ | |
1371 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1372 | } | |
1373 | else | |
1374 | { | |
1375 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1376 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1377 | } | |
29134980 | 1378 | } |
2e4b5889 OF |
1379 | |
1380 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1381 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1382 | ||
1383 | return pc; | |
29134980 OF |
1384 | } |
1385 | ||
5114e29d OF |
1386 | static CORE_ADDR |
1387 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, | |
1388 | struct cris_unwind_cache *info) | |
1389 | { | |
1390 | ULONGEST this_base; | |
1391 | ||
1392 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1393 | meant to be a full-fledged prologue scanner. It is only needed for | |
1394 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1395 | ||
1396 | * PLT stubs (library calls) | |
1397 | * call dummys | |
1398 | * signal trampolines | |
1399 | ||
1400 | For those cases, it is assumed that there is no actual prologue; that | |
1401 | the stack pointer is not adjusted, and (as a consequence) the return | |
1402 | address is not pushed onto the stack. */ | |
1403 | ||
1404 | /* We only want to know the end of the prologue when next_frame and info | |
1405 | are NULL (called from cris_skip_prologue i.e.). */ | |
1406 | if (next_frame == NULL && info == NULL) | |
1407 | { | |
1408 | return pc; | |
1409 | } | |
1410 | ||
1411 | /* The SP is assumed to be unaltered. */ | |
1412 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1413 | info->base = this_base; | |
1414 | info->prev_sp = this_base; | |
1415 | ||
1416 | /* The PC is assumed to be found in SRP. */ | |
1417 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1418 | ||
1419 | return pc; | |
1420 | } | |
1421 | ||
29134980 OF |
1422 | /* Advance pc beyond any function entry prologue instructions at pc |
1423 | to reach some "real" code. */ | |
1424 | ||
29134980 OF |
1425 | /* Given a PC value corresponding to the start of a function, return the PC |
1426 | of the first instruction after the function prologue. */ | |
1427 | ||
a78f21af | 1428 | static CORE_ADDR |
2e4b5889 | 1429 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1430 | { |
2e4b5889 OF |
1431 | CORE_ADDR func_addr, func_end; |
1432 | struct symtab_and_line sal; | |
29134980 OF |
1433 | CORE_ADDR pc_after_prologue; |
1434 | ||
2e4b5889 OF |
1435 | /* If we have line debugging information, then the end of the prologue |
1436 | should the first assembly instruction of the first source line. */ | |
1437 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1438 | { | |
1439 | sal = find_pc_line (func_addr, 0); | |
1440 | if (sal.end > 0 && sal.end < func_end) | |
1441 | return sal.end; | |
1442 | } | |
29134980 | 1443 | |
5114e29d OF |
1444 | if (cris_version () == 32) |
1445 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); | |
1446 | else | |
1447 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1448 | ||
29134980 OF |
1449 | return pc_after_prologue; |
1450 | } | |
1451 | ||
2e4b5889 OF |
1452 | static CORE_ADDR |
1453 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1454 | { | |
1455 | ULONGEST pc; | |
1456 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1457 | return pc; | |
1458 | } | |
1459 | ||
1460 | static CORE_ADDR | |
1461 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1462 | { | |
1463 | ULONGEST sp; | |
1464 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1465 | return sp; | |
1466 | } | |
1467 | ||
29134980 OF |
1468 | /* Use the program counter to determine the contents and size of a breakpoint |
1469 | instruction. It returns a pointer to a string of bytes that encode a | |
1470 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1471 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1472 | the breakpoint should be inserted. */ | |
1473 | ||
a78f21af | 1474 | static const unsigned char * |
29134980 OF |
1475 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1476 | { | |
0e6bdb31 OF |
1477 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1478 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1479 | *lenptr = 2; |
1480 | ||
0e6bdb31 OF |
1481 | if (cris_mode () == cris_mode_guru) |
1482 | return break15_insn; | |
1483 | else | |
1484 | return break8_insn; | |
29134980 OF |
1485 | } |
1486 | ||
29134980 OF |
1487 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1488 | 0 otherwise. */ | |
1489 | ||
a78f21af | 1490 | static int |
29134980 OF |
1491 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1492 | { | |
1493 | int version = cris_version (); | |
1494 | ||
1495 | switch (spec_reg.applicable_version) | |
1496 | { | |
1497 | case cris_ver_version_all: | |
1498 | return 1; | |
1499 | case cris_ver_warning: | |
1500 | /* Indeterminate/obsolete. */ | |
1501 | return 0; | |
29134980 OF |
1502 | case cris_ver_v0_3: |
1503 | return (version >= 0 && version <= 3); | |
1504 | case cris_ver_v3p: | |
1505 | return (version >= 3); | |
1506 | case cris_ver_v8: | |
1507 | return (version == 8 || version == 9); | |
1508 | case cris_ver_v8p: | |
1509 | return (version >= 8); | |
c600d464 OF |
1510 | case cris_ver_v0_10: |
1511 | return (version >= 0 && version <= 10); | |
1512 | case cris_ver_v3_10: | |
1513 | return (version >= 3 && version <= 10); | |
1514 | case cris_ver_v8_10: | |
1515 | return (version >= 8 && version <= 10); | |
1516 | case cris_ver_v10: | |
1517 | return (version == 10); | |
29134980 OF |
1518 | case cris_ver_v10p: |
1519 | return (version >= 10); | |
c600d464 OF |
1520 | case cris_ver_v32p: |
1521 | return (version >= 32); | |
29134980 OF |
1522 | default: |
1523 | /* Invalid cris version. */ | |
1524 | return 0; | |
1525 | } | |
1526 | } | |
1527 | ||
1d94326f AC |
1528 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1529 | register, -1 for an invalid register. */ | |
1530 | ||
1531 | static int | |
1532 | cris_register_size (int regno) | |
1533 | { | |
c600d464 | 1534 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1535 | int i; |
1536 | int spec_regno; | |
1537 | ||
1538 | if (regno >= 0 && regno < NUM_GENREGS) | |
1539 | { | |
1540 | /* General registers (R0 - R15) are 32 bits. */ | |
1541 | return 4; | |
1542 | } | |
c600d464 | 1543 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1544 | { |
1545 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1546 | Adjust regno accordingly. */ | |
1547 | spec_regno = regno - NUM_GENREGS; | |
1548 | ||
c600d464 | 1549 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1550 | { |
1551 | if (cris_spec_regs[i].number == spec_regno | |
1552 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1553 | /* Go with the first applicable register. */ | |
1554 | return cris_spec_regs[i].reg_size; | |
1555 | } | |
1556 | /* Special register not applicable to this CRIS version. */ | |
1557 | return 0; | |
1558 | } | |
c600d464 | 1559 | else if (regno >= PC_REGNUM && regno < NUM_REGS) |
1d94326f | 1560 | { |
c600d464 OF |
1561 | /* This will apply to CRISv32 only where there are additional registers |
1562 | after the special registers (pseudo PC and support registers). */ | |
1563 | return 4; | |
1d94326f | 1564 | } |
c600d464 OF |
1565 | |
1566 | ||
1567 | return -1; | |
1d94326f AC |
1568 | } |
1569 | ||
29134980 OF |
1570 | /* Nonzero if regno should not be fetched from the target. This is the case |
1571 | for unimplemented (size 0) and non-existant registers. */ | |
1572 | ||
a78f21af | 1573 | static int |
29134980 OF |
1574 | cris_cannot_fetch_register (int regno) |
1575 | { | |
1576 | return ((regno < 0 || regno >= NUM_REGS) | |
1577 | || (cris_register_size (regno) == 0)); | |
1578 | } | |
1579 | ||
1580 | /* Nonzero if regno should not be written to the target, for various | |
1581 | reasons. */ | |
1582 | ||
a78f21af | 1583 | static int |
29134980 OF |
1584 | cris_cannot_store_register (int regno) |
1585 | { | |
1586 | /* There are three kinds of registers we refuse to write to. | |
1587 | 1. Those that not implemented. | |
1588 | 2. Those that are read-only (depends on the processor mode). | |
1589 | 3. Those registers to which a write has no effect. | |
1590 | */ | |
1591 | ||
1592 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1593 | /* Not implemented. */ | |
1594 | return 1; | |
1595 | ||
1596 | else if (regno == VR_REGNUM) | |
1597 | /* Read-only. */ | |
1598 | return 1; | |
1599 | ||
1600 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1601 | /* Writing has no effect. */ | |
1602 | return 1; | |
1603 | ||
a5f6c8f5 OF |
1604 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1605 | agent decide whether they are writable. */ | |
29134980 OF |
1606 | |
1607 | return 0; | |
1608 | } | |
1609 | ||
c600d464 OF |
1610 | /* Nonzero if regno should not be fetched from the target. This is the case |
1611 | for unimplemented (size 0) and non-existant registers. */ | |
1612 | ||
1613 | static int | |
1614 | crisv32_cannot_fetch_register (int regno) | |
1615 | { | |
1616 | return ((regno < 0 || regno >= NUM_REGS) | |
1617 | || (cris_register_size (regno) == 0)); | |
1618 | } | |
1619 | ||
1620 | /* Nonzero if regno should not be written to the target, for various | |
1621 | reasons. */ | |
1622 | ||
1623 | static int | |
1624 | crisv32_cannot_store_register (int regno) | |
1625 | { | |
1626 | /* There are three kinds of registers we refuse to write to. | |
1627 | 1. Those that not implemented. | |
1628 | 2. Those that are read-only (depends on the processor mode). | |
1629 | 3. Those registers to which a write has no effect. | |
1630 | */ | |
1631 | ||
1632 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1633 | /* Not implemented. */ | |
1634 | return 1; | |
1635 | ||
1636 | else if (regno == VR_REGNUM) | |
1637 | /* Read-only. */ | |
1638 | return 1; | |
1639 | ||
1640 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1641 | /* Writing has no effect. */ | |
1642 | return 1; | |
1643 | ||
1644 | /* Many special registers are read-only in user mode. Let the debug | |
1645 | agent decide whether they are writable. */ | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
29134980 OF |
1650 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1651 | of data in register regno. */ | |
1652 | ||
a78f21af | 1653 | static struct type * |
c1d546cd | 1654 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1655 | { |
a5f6c8f5 OF |
1656 | if (regno == PC_REGNUM) |
1657 | return builtin_type_void_func_ptr; | |
1658 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1659 | return builtin_type_void_data_ptr; | |
1660 | else if ((regno >= 0 && regno < SP_REGNUM) | |
1661 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) | |
1662 | /* Note: R8 taken care of previous clause. */ | |
1663 | return builtin_type_uint32; | |
1664 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1665 | return builtin_type_uint16; | |
1666 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1667 | return builtin_type_uint8; | |
29134980 | 1668 | else |
a5f6c8f5 OF |
1669 | /* Invalid (unimplemented) register. */ |
1670 | return builtin_type_int0; | |
29134980 OF |
1671 | } |
1672 | ||
c600d464 OF |
1673 | static struct type * |
1674 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1675 | { | |
1676 | if (regno == PC_REGNUM) | |
1677 | return builtin_type_void_func_ptr; | |
1678 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1679 | return builtin_type_void_data_ptr; | |
1680 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1681 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1682 | || (regno == PID_REGNUM) | |
1683 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1684 | /* Note: R8 and SP taken care of by previous clause. */ | |
1685 | return builtin_type_uint32; | |
1686 | else if (regno == WZ_REGNUM) | |
1687 | return builtin_type_uint16; | |
1688 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1689 | return builtin_type_uint8; | |
1690 | else | |
1691 | { | |
1692 | /* Invalid (unimplemented) register. Should not happen as there are | |
1693 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1694 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
c600d464 OF |
1695 | return builtin_type_int0; |
1696 | } | |
1697 | } | |
1698 | ||
2e4b5889 OF |
1699 | /* Stores a function return value of type type, where valbuf is the address |
1700 | of the value to be stored. */ | |
29134980 | 1701 | |
2e4b5889 | 1702 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1703 | |
2e4b5889 OF |
1704 | static void |
1705 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1706 | const void *valbuf) | |
29134980 | 1707 | { |
2e4b5889 OF |
1708 | ULONGEST val; |
1709 | int len = TYPE_LENGTH (type); | |
29134980 | 1710 | |
2e4b5889 | 1711 | if (len <= 4) |
29134980 | 1712 | { |
2e4b5889 OF |
1713 | /* Put the return value in R10. */ |
1714 | val = extract_unsigned_integer (valbuf, len); | |
1715 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1716 | } |
2e4b5889 | 1717 | else if (len <= 8) |
29134980 | 1718 | { |
2e4b5889 OF |
1719 | /* Put the return value in R10 and R11. */ |
1720 | val = extract_unsigned_integer (valbuf, 4); | |
1721 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1722 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1723 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1724 | } |
2e4b5889 | 1725 | else |
8a3fe4f8 | 1726 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1727 | } |
1728 | ||
2e4b5889 OF |
1729 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1730 | unimplemented register. */ | |
29134980 | 1731 | |
c600d464 OF |
1732 | static const char * |
1733 | cris_special_register_name (int regno) | |
1734 | { | |
1735 | int spec_regno; | |
1736 | int i; | |
1737 | ||
1738 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1739 | Adjust regno accordingly. */ | |
1740 | spec_regno = regno - NUM_GENREGS; | |
1741 | ||
1742 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1743 | when searching. */ | |
1744 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1745 | { | |
1746 | if (cris_spec_regs[i].number == spec_regno | |
1747 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1748 | /* Go with the first applicable register. */ | |
1749 | return cris_spec_regs[i].name; | |
1750 | } | |
1751 | /* Special register not applicable to this CRIS version. */ | |
1752 | return NULL; | |
1753 | } | |
1754 | ||
2e4b5889 OF |
1755 | static const char * |
1756 | cris_register_name (int regno) | |
1757 | { | |
1758 | static char *cris_genreg_names[] = | |
1759 | { "r0", "r1", "r2", "r3", \ | |
1760 | "r4", "r5", "r6", "r7", \ | |
1761 | "r8", "r9", "r10", "r11", \ | |
1762 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1763 | |
2e4b5889 | 1764 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1765 | { |
2e4b5889 OF |
1766 | /* General register. */ |
1767 | return cris_genreg_names[regno]; | |
29134980 | 1768 | } |
2e4b5889 | 1769 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
29134980 | 1770 | { |
c600d464 OF |
1771 | return cris_special_register_name (regno); |
1772 | } | |
1773 | else | |
1774 | { | |
1775 | /* Invalid register. */ | |
2e4b5889 OF |
1776 | return NULL; |
1777 | } | |
c600d464 OF |
1778 | } |
1779 | ||
1780 | static const char * | |
1781 | crisv32_register_name (int regno) | |
1782 | { | |
1783 | static char *crisv32_genreg_names[] = | |
1784 | { "r0", "r1", "r2", "r3", \ | |
1785 | "r4", "r5", "r6", "r7", \ | |
1786 | "r8", "r9", "r10", "r11", \ | |
1787 | "r12", "r13", "sp", "acr" | |
1788 | }; | |
1789 | ||
1790 | static char *crisv32_sreg_names[] = | |
1791 | { "s0", "s1", "s2", "s3", \ | |
1792 | "s4", "s5", "s6", "s7", \ | |
1793 | "s8", "s9", "s10", "s11", \ | |
1794 | "s12", "s13", "s14", "s15" | |
1795 | }; | |
1796 | ||
1797 | if (regno >= 0 && regno < NUM_GENREGS) | |
1798 | { | |
1799 | /* General register. */ | |
1800 | return crisv32_genreg_names[regno]; | |
1801 | } | |
1802 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1803 | { | |
1804 | return cris_special_register_name (regno); | |
1805 | } | |
1806 | else if (regno == PC_REGNUM) | |
1807 | { | |
1808 | return "pc"; | |
1809 | } | |
1810 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1811 | { | |
1812 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1813 | } | |
2e4b5889 OF |
1814 | else |
1815 | { | |
1816 | /* Invalid register. */ | |
1817 | return NULL; | |
29134980 | 1818 | } |
29134980 OF |
1819 | } |
1820 | ||
a5f6c8f5 OF |
1821 | /* Convert DWARF register number REG to the appropriate register |
1822 | number used by GDB. */ | |
1823 | ||
2e4b5889 | 1824 | static int |
a5f6c8f5 | 1825 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1826 | { |
a5f6c8f5 OF |
1827 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1828 | numbering, MOF is 18). | |
1829 | Adapted from gcc/config/cris/cris.h. */ | |
1830 | static int cris_dwarf_regmap[] = { | |
1831 | 0, 1, 2, 3, | |
1832 | 4, 5, 6, 7, | |
1833 | 8, 9, 10, 11, | |
1834 | 12, 13, 14, 15, | |
1835 | 27, -1, -1, -1, | |
1836 | -1, -1, -1, 23, | |
1837 | -1, -1, -1, 27, | |
1838 | -1, -1, -1, -1 | |
1839 | }; | |
1840 | int regnum = -1; | |
1841 | ||
1842 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1843 | regnum = cris_dwarf_regmap[reg]; | |
1844 | ||
1845 | if (regnum == -1) | |
8a3fe4f8 | 1846 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1847 | |
1848 | return regnum; | |
1849 | } | |
1850 | ||
1851 | /* DWARF-2 frame support. */ | |
1852 | ||
1853 | static void | |
1854 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1855 | struct dwarf2_frame_state_reg *reg) | |
1856 | { | |
1857 | /* The return address column. */ | |
1858 | if (regnum == PC_REGNUM) | |
1859 | reg->how = DWARF2_FRAME_REG_RA; | |
1860 | ||
1861 | /* The call frame address. */ | |
1862 | else if (regnum == SP_REGNUM) | |
1863 | reg->how = DWARF2_FRAME_REG_CFA; | |
29134980 OF |
1864 | } |
1865 | ||
2e4b5889 OF |
1866 | /* Extract from an array regbuf containing the raw register state a function |
1867 | return value of type type, and copy that, in virtual format, into | |
1868 | valbuf. */ | |
1869 | ||
1870 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1871 | |
2e4b5889 OF |
1872 | static void |
1873 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1874 | void *valbuf) | |
29134980 | 1875 | { |
2e4b5889 OF |
1876 | ULONGEST val; |
1877 | int len = TYPE_LENGTH (type); | |
29134980 | 1878 | |
2e4b5889 | 1879 | if (len <= 4) |
29134980 | 1880 | { |
2e4b5889 OF |
1881 | /* Get the return value from R10. */ |
1882 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1883 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1884 | } |
2e4b5889 | 1885 | else if (len <= 8) |
29134980 | 1886 | { |
2e4b5889 OF |
1887 | /* Get the return value from R10 and R11. */ |
1888 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1889 | store_unsigned_integer (valbuf, 4, val); | |
1890 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1891 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1892 | } |
2e4b5889 | 1893 | else |
8a3fe4f8 | 1894 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1895 | } |
1896 | ||
b4206d25 OF |
1897 | /* Handle the CRIS return value convention. */ |
1898 | ||
1899 | static enum return_value_convention | |
1900 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
e2a2a3e8 OF |
1901 | struct regcache *regcache, gdb_byte *readbuf, |
1902 | const gdb_byte *writebuf) | |
b4206d25 OF |
1903 | { |
1904 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1905 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1906 | || TYPE_LENGTH (type) > 8) | |
1907 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1908 | goes on the stack. */ | |
1909 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1910 | ||
1911 | if (readbuf) | |
1912 | cris_extract_return_value (type, regcache, readbuf); | |
1913 | if (writebuf) | |
1914 | cris_store_return_value (type, regcache, writebuf); | |
1915 | ||
1916 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1917 | } | |
1918 | ||
2e4b5889 OF |
1919 | /* Returns 1 if the given type will be passed by pointer rather than |
1920 | directly. */ | |
1921 | ||
1922 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1923 | by value. */ | |
1924 | ||
1925 | static int | |
1926 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1927 | { | |
1928 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1929 | } |
1930 | ||
1931 | /* Calculates a value that measures how good inst_args constraints an | |
1932 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1933 | ||
1934 | static int | |
1935 | constraint (unsigned int insn, const signed char *inst_args, | |
1936 | inst_env_type *inst_env) | |
1937 | { | |
1938 | int retval = 0; | |
1939 | int tmp, i; | |
1940 | ||
1941 | const char *s = inst_args; | |
1942 | ||
1943 | for (; *s; s++) | |
1944 | switch (*s) | |
1945 | { | |
1946 | case 'm': | |
1947 | if ((insn & 0x30) == 0x30) | |
1948 | return -1; | |
1949 | break; | |
1950 | ||
1951 | case 'S': | |
1952 | /* A prefix operand. */ | |
1953 | if (inst_env->prefix_found) | |
1954 | break; | |
1955 | else | |
1956 | return -1; | |
1957 | ||
1958 | case 'B': | |
1959 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1960 | valid "push" size. In case of special register, it may be != 4. */ | |
1961 | if (inst_env->prefix_found) | |
1962 | break; | |
1963 | else | |
1964 | return -1; | |
1965 | ||
1966 | case 'D': | |
1967 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1968 | if (!retval) | |
1969 | return -1; | |
1970 | else | |
1971 | retval += 4; | |
1972 | break; | |
1973 | ||
1974 | case 'P': | |
1975 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1976 | |
1977 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1978 | { | |
1979 | /* Since we match four bits, we will give a value of | |
1980 | 4 - 1 = 3 in a match. If there is a corresponding | |
1981 | exact match of a special register in another pattern, it | |
1982 | will get a value of 4, which will be higher. This should | |
1983 | be correct in that an exact pattern would match better that | |
1984 | a general pattern. | |
1985 | Note that there is a reason for not returning zero; the | |
1986 | pattern for "clear" is partly matched in the bit-pattern | |
1987 | (the two lower bits must be zero), while the bit-pattern | |
1988 | for a move from a special register is matched in the | |
1989 | register constraint. | |
1990 | This also means we will will have a race condition if | |
1991 | there is a partly match in three bits in the bit pattern. */ | |
1992 | if (tmp == cris_spec_regs[i].number) | |
1993 | { | |
1994 | retval += 3; | |
1995 | break; | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
2000 | return -1; |
2001 | break; | |
2002 | } | |
2003 | return retval; | |
2004 | } | |
2005 | ||
2006 | /* Returns the number of bits set in the variable value. */ | |
2007 | ||
2008 | static int | |
2009 | number_of_bits (unsigned int value) | |
2010 | { | |
2011 | int number_of_bits = 0; | |
2012 | ||
2013 | while (value != 0) | |
2014 | { | |
2015 | number_of_bits += 1; | |
2016 | value &= (value - 1); | |
2017 | } | |
2018 | return number_of_bits; | |
2019 | } | |
2020 | ||
2021 | /* Finds the address that should contain the single step breakpoint(s). | |
2022 | It stems from code in cris-dis.c. */ | |
2023 | ||
2024 | static int | |
2025 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
2026 | { | |
2027 | int i; | |
2028 | int max_level_of_match = -1; | |
2029 | int max_matched = -1; | |
2030 | int level_of_match; | |
2031 | ||
2032 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
2033 | { | |
2034 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
2035 | && ((cris_opcodes[i].lose & insn) == 0) |
2036 | /* Only CRISv10 instructions, please. */ | |
2037 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
2038 | { |
2039 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
2040 | if (level_of_match >= 0) | |
2041 | { | |
2042 | level_of_match += | |
2043 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
2044 | if (level_of_match > max_level_of_match) | |
2045 | { | |
2046 | max_matched = i; | |
2047 | max_level_of_match = level_of_match; | |
2048 | if (level_of_match == 16) | |
2049 | { | |
2050 | /* All bits matched, cannot find better. */ | |
2051 | break; | |
2052 | } | |
2053 | } | |
2054 | } | |
2055 | } | |
2056 | } | |
2057 | return max_matched; | |
2058 | } | |
2059 | ||
2060 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2061 | actually an internal error. */ | |
2062 | ||
2063 | static int | |
2064 | find_step_target (inst_env_type *inst_env) | |
2065 | { | |
2066 | int i; | |
2067 | int offset; | |
2068 | unsigned short insn; | |
2069 | ||
2070 | /* Create a local register image and set the initial state. */ | |
2071 | for (i = 0; i < NUM_GENREGS; i++) | |
2072 | { | |
2073 | inst_env->reg[i] = (unsigned long) read_register (i); | |
2074 | } | |
2075 | offset = NUM_GENREGS; | |
2076 | for (i = 0; i < NUM_SPECREGS; i++) | |
2077 | { | |
2078 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
2079 | } | |
2080 | inst_env->branch_found = 0; | |
2081 | inst_env->slot_needed = 0; | |
2082 | inst_env->delay_slot_pc_active = 0; | |
2083 | inst_env->prefix_found = 0; | |
2084 | inst_env->invalid = 0; | |
2085 | inst_env->xflag_found = 0; | |
2086 | inst_env->disable_interrupt = 0; | |
2087 | ||
2088 | /* Look for a step target. */ | |
2089 | do | |
2090 | { | |
2091 | /* Read an instruction from the client. */ | |
2092 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
2093 | ||
2094 | /* If the instruction is not in a delay slot the new content of the | |
2095 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2096 | that simple. Since a instruction in a delay slot cannot change | |
2097 | the content of the PC, it does not matter what value PC will have. | |
2098 | Just make sure it is a valid instruction. */ | |
2099 | if (!inst_env->delay_slot_pc_active) | |
2100 | { | |
2101 | inst_env->reg[PC_REGNUM] += 2; | |
2102 | } | |
2103 | else | |
2104 | { | |
2105 | inst_env->delay_slot_pc_active = 0; | |
2106 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
2107 | } | |
2108 | /* Analyse the present instruction. */ | |
2109 | i = find_cris_op (insn, inst_env); | |
2110 | if (i == -1) | |
2111 | { | |
2112 | inst_env->invalid = 1; | |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2117 | } | |
2118 | } while (!inst_env->invalid | |
2119 | && (inst_env->prefix_found || inst_env->xflag_found | |
2120 | || inst_env->slot_needed)); | |
2121 | return i; | |
2122 | } | |
2123 | ||
2124 | /* There is no hardware single-step support. The function find_step_target | |
2125 | digs through the opcodes in order to find all possible targets. | |
2126 | Either one ordinary target or two targets for branches may be found. */ | |
2127 | ||
a78f21af | 2128 | static void |
29134980 OF |
2129 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) |
2130 | { | |
2131 | inst_env_type inst_env; | |
2132 | ||
2133 | if (insert_breakpoints) | |
2134 | { | |
2135 | /* Analyse the present instruction environment and insert | |
2136 | breakpoints. */ | |
2137 | int status = find_step_target (&inst_env); | |
2138 | if (status == -1) | |
2139 | { | |
c600d464 OF |
2140 | /* Could not find a target. Things are likely to go downhill |
2141 | from here. */ | |
8a3fe4f8 | 2142 | warning (_("CRIS software single step could not find a step target.")); |
29134980 OF |
2143 | } |
2144 | else | |
2145 | { | |
2146 | /* Insert at most two breakpoints. One for the next PC content | |
2147 | and possibly another one for a branch, jump, etc. */ | |
2148 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
2149 | target_insert_breakpoint (next_pc, break_mem[0]); | |
2150 | if (inst_env.branch_found | |
2151 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2152 | { | |
2153 | branch_target_address = | |
2154 | (CORE_ADDR) inst_env.branch_break_address; | |
2155 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
2156 | branch_break_inserted = 1; | |
2157 | } | |
2158 | } | |
2159 | } | |
2160 | else | |
2161 | { | |
2162 | /* Remove breakpoints. */ | |
2163 | target_remove_breakpoint (next_pc, break_mem[0]); | |
2164 | if (branch_break_inserted) | |
2165 | { | |
2166 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
2167 | branch_break_inserted = 0; | |
2168 | } | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2173 | ||
a78f21af | 2174 | static void |
29134980 OF |
2175 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2176 | { | |
2177 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2178 | instruction (not 100% sure). */ | |
2179 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2180 | { | |
2181 | inst_env->invalid = 1; | |
2182 | return; | |
2183 | } | |
2184 | ||
2185 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2186 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2187 | ||
2188 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2189 | need updating. */ | |
2190 | inst_env->slot_needed = 0; | |
2191 | inst_env->prefix_found = 1; | |
2192 | } | |
2193 | ||
2194 | /* Updates the autoincrement register. The size of the increment is derived | |
2195 | from the size of the operation. The PC is always kept aligned on even | |
2196 | word addresses. */ | |
2197 | ||
a78f21af | 2198 | static void |
29134980 OF |
2199 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2200 | { | |
2201 | if (size == INST_BYTE_SIZE) | |
2202 | { | |
2203 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2204 | ||
2205 | /* The PC must be word aligned, so increase the PC with one | |
2206 | word even if the size is byte. */ | |
2207 | if (cris_get_operand1 (inst) == REG_PC) | |
2208 | { | |
2209 | inst_env->reg[REG_PC] += 1; | |
2210 | } | |
2211 | } | |
2212 | else if (size == INST_WORD_SIZE) | |
2213 | { | |
2214 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2215 | } | |
2216 | else if (size == INST_DWORD_SIZE) | |
2217 | { | |
2218 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2219 | } | |
2220 | else | |
2221 | { | |
2222 | /* Invalid size. */ | |
2223 | inst_env->invalid = 1; | |
2224 | } | |
2225 | } | |
2226 | ||
2a9ecef2 OF |
2227 | /* Just a forward declaration. */ |
2228 | ||
a78f21af AC |
2229 | static unsigned long get_data_from_address (unsigned short *inst, |
2230 | CORE_ADDR address); | |
2a9ecef2 | 2231 | |
29134980 OF |
2232 | /* Calculates the prefix value for the general case of offset addressing |
2233 | mode. */ | |
2234 | ||
a78f21af | 2235 | static void |
29134980 OF |
2236 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2237 | { | |
2238 | ||
2239 | long offset; | |
2240 | ||
2241 | /* It's invalid to be in a delay slot. */ | |
2242 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2243 | { | |
2244 | inst_env->invalid = 1; | |
2245 | return; | |
2246 | } | |
2247 | ||
fa4e4598 OF |
2248 | /* The calculation of prefix_value used to be after process_autoincrement, |
2249 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2250 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2251 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2252 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2253 | ||
2254 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2255 | inst_env->prefix_value += | |
2a9ecef2 OF |
2256 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2257 | ||
fa4e4598 OF |
2258 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2259 | { | |
2260 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2261 | } | |
2262 | ||
29134980 OF |
2263 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2264 | need updating. */ | |
2265 | inst_env->slot_needed = 0; | |
2266 | inst_env->prefix_found = 1; | |
2267 | } | |
2268 | ||
2269 | /* Calculates the prefix value for the index addressing mode. */ | |
2270 | ||
a78f21af | 2271 | static void |
29134980 OF |
2272 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2273 | { | |
2274 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2275 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2276 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2277 | { | |
2278 | inst_env->invalid = 1; | |
2279 | return; | |
2280 | } | |
2281 | ||
2282 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2283 | ||
2284 | /* The offset is the operand2 value shifted the size of the instruction | |
2285 | to the left. */ | |
2286 | inst_env->prefix_value += | |
2287 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2288 | ||
2289 | /* If the PC is operand1 (base) the address used is the address after | |
2290 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2291 | for the prefix operation). */ | |
2292 | if (cris_get_operand1 (inst) == REG_PC) | |
2293 | { | |
2294 | inst_env->prefix_value += 2; | |
2295 | } | |
2296 | ||
2297 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2298 | need updating. */ | |
2299 | inst_env->slot_needed = 0; | |
2300 | inst_env->xflag_found = 0; | |
2301 | inst_env->prefix_found = 1; | |
2302 | } | |
2303 | ||
2304 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2305 | ||
a78f21af | 2306 | static void |
29134980 OF |
2307 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2308 | { | |
2309 | ||
2310 | CORE_ADDR address; | |
2311 | ||
2312 | /* It's invalid to be in a delay slot. */ | |
2313 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2314 | { | |
2315 | inst_env->invalid = 1; | |
2316 | return; | |
2317 | } | |
2318 | ||
2319 | /* The prefix value is one dereference of the contents of the operand1 | |
2320 | register. */ | |
2321 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2322 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2323 | ||
2324 | /* Check if the mode is autoincrement. */ | |
2325 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2326 | { | |
2327 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2328 | } | |
2329 | ||
2330 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2331 | need updating. */ | |
2332 | inst_env->slot_needed = 0; | |
2333 | inst_env->xflag_found = 0; | |
2334 | inst_env->prefix_found = 1; | |
2335 | } | |
2336 | ||
2337 | /* Finds the destination for a branch with 8-bits offset. */ | |
2338 | ||
a78f21af | 2339 | static void |
29134980 OF |
2340 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2341 | { | |
2342 | ||
2343 | short offset; | |
2344 | ||
2345 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2346 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2347 | { | |
2348 | inst_env->invalid = 1; | |
2349 | return; | |
2350 | } | |
2351 | ||
2352 | /* We have a branch, find out where the branch will land. */ | |
2353 | offset = cris_get_branch_short_offset (inst); | |
2354 | ||
2355 | /* Check if the offset is signed. */ | |
2356 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2357 | { | |
2358 | offset |= 0xFF00; | |
2359 | } | |
2360 | ||
2361 | /* The offset ends with the sign bit, set it to zero. The address | |
2362 | should always be word aligned. */ | |
2363 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2364 | ||
2365 | inst_env->branch_found = 1; | |
2366 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2367 | ||
2368 | inst_env->slot_needed = 1; | |
2369 | inst_env->prefix_found = 0; | |
2370 | inst_env->xflag_found = 0; | |
2371 | inst_env->disable_interrupt = 1; | |
2372 | } | |
2373 | ||
2374 | /* Finds the destination for a branch with 16-bits offset. */ | |
2375 | ||
a78f21af | 2376 | static void |
29134980 OF |
2377 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2378 | { | |
2379 | short offset; | |
2380 | ||
2381 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2382 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2383 | { | |
2384 | inst_env->invalid = 1; | |
2385 | return; | |
2386 | } | |
2387 | ||
2388 | /* We have a branch, find out the offset for the branch. */ | |
2389 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2390 | ||
2391 | /* The instruction is one word longer than normal, so add one word | |
2392 | to the PC. */ | |
2393 | inst_env->reg[REG_PC] += 2; | |
2394 | ||
2395 | inst_env->branch_found = 1; | |
2396 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2397 | ||
2398 | ||
2399 | inst_env->slot_needed = 1; | |
2400 | inst_env->prefix_found = 0; | |
2401 | inst_env->xflag_found = 0; | |
2402 | inst_env->disable_interrupt = 1; | |
2403 | } | |
2404 | ||
2405 | /* Handles the ABS instruction. */ | |
2406 | ||
a78f21af | 2407 | static void |
29134980 OF |
2408 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2409 | { | |
2410 | ||
2411 | long value; | |
2412 | ||
2413 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2414 | if (inst_env->prefix_found) | |
2415 | { | |
2416 | inst_env->invalid = 1; | |
2417 | return; | |
2418 | } | |
2419 | ||
2420 | /* Check if the operation affects the PC. */ | |
2421 | if (cris_get_operand2 (inst) == REG_PC) | |
2422 | { | |
2423 | ||
2424 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2425 | if (inst_env->slot_needed) | |
2426 | { | |
2427 | inst_env->invalid = 1; | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | value = (long) inst_env->reg[REG_PC]; | |
2432 | ||
2433 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2434 | if (value != SIGNED_DWORD_MASK) | |
2435 | { | |
2436 | value = -value; | |
2437 | inst_env->reg[REG_PC] = (long) value; | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | inst_env->slot_needed = 0; | |
2442 | inst_env->prefix_found = 0; | |
2443 | inst_env->xflag_found = 0; | |
2444 | inst_env->disable_interrupt = 0; | |
2445 | } | |
2446 | ||
2447 | /* Handles the ADDI instruction. */ | |
2448 | ||
a78f21af | 2449 | static void |
29134980 OF |
2450 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2451 | { | |
2452 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2453 | a prefix. */ | |
2454 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2455 | { | |
2456 | inst_env->invalid = 1; | |
2457 | return; | |
2458 | } | |
2459 | ||
2460 | inst_env->slot_needed = 0; | |
2461 | inst_env->prefix_found = 0; | |
2462 | inst_env->xflag_found = 0; | |
2463 | inst_env->disable_interrupt = 0; | |
2464 | } | |
2465 | ||
2466 | /* Handles the ASR instruction. */ | |
2467 | ||
a78f21af | 2468 | static void |
29134980 OF |
2469 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2470 | { | |
2471 | int shift_steps; | |
2472 | unsigned long value; | |
2473 | unsigned long signed_extend_mask = 0; | |
2474 | ||
2475 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2476 | if (inst_env->prefix_found) | |
2477 | { | |
2478 | inst_env->invalid = 1; | |
2479 | return; | |
2480 | } | |
2481 | ||
2482 | /* Check if the PC is the target register. */ | |
2483 | if (cris_get_operand2 (inst) == REG_PC) | |
2484 | { | |
2485 | /* It's invalid to change the PC in a delay slot. */ | |
2486 | if (inst_env->slot_needed) | |
2487 | { | |
2488 | inst_env->invalid = 1; | |
2489 | return; | |
2490 | } | |
2491 | /* Get the number of bits to shift. */ | |
2492 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2493 | value = inst_env->reg[REG_PC]; | |
2494 | ||
2495 | /* Find out how many bits the operation should apply to. */ | |
2496 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2497 | { | |
2498 | if (value & SIGNED_BYTE_MASK) | |
2499 | { | |
2500 | signed_extend_mask = 0xFF; | |
2501 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2502 | signed_extend_mask = ~signed_extend_mask; | |
2503 | } | |
2504 | value = value >> shift_steps; | |
2505 | value |= signed_extend_mask; | |
2506 | value &= 0xFF; | |
2507 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2508 | inst_env->reg[REG_PC] |= value; | |
2509 | } | |
2510 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2511 | { | |
2512 | if (value & SIGNED_WORD_MASK) | |
2513 | { | |
2514 | signed_extend_mask = 0xFFFF; | |
2515 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2516 | signed_extend_mask = ~signed_extend_mask; | |
2517 | } | |
2518 | value = value >> shift_steps; | |
2519 | value |= signed_extend_mask; | |
2520 | value &= 0xFFFF; | |
2521 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2522 | inst_env->reg[REG_PC] |= value; | |
2523 | } | |
2524 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2525 | { | |
2526 | if (value & SIGNED_DWORD_MASK) | |
2527 | { | |
2528 | signed_extend_mask = 0xFFFFFFFF; | |
2529 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2530 | signed_extend_mask = ~signed_extend_mask; | |
2531 | } | |
2532 | value = value >> shift_steps; | |
2533 | value |= signed_extend_mask; | |
2534 | inst_env->reg[REG_PC] = value; | |
2535 | } | |
2536 | } | |
2537 | inst_env->slot_needed = 0; | |
2538 | inst_env->prefix_found = 0; | |
2539 | inst_env->xflag_found = 0; | |
2540 | inst_env->disable_interrupt = 0; | |
2541 | } | |
2542 | ||
2543 | /* Handles the ASRQ instruction. */ | |
2544 | ||
a78f21af | 2545 | static void |
29134980 OF |
2546 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2547 | { | |
2548 | ||
2549 | int shift_steps; | |
2550 | unsigned long value; | |
2551 | unsigned long signed_extend_mask = 0; | |
2552 | ||
2553 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2554 | if (inst_env->prefix_found) | |
2555 | { | |
2556 | inst_env->invalid = 1; | |
2557 | return; | |
2558 | } | |
2559 | ||
2560 | /* Check if the PC is the target register. */ | |
2561 | if (cris_get_operand2 (inst) == REG_PC) | |
2562 | { | |
2563 | ||
2564 | /* It's invalid to change the PC in a delay slot. */ | |
2565 | if (inst_env->slot_needed) | |
2566 | { | |
2567 | inst_env->invalid = 1; | |
2568 | return; | |
2569 | } | |
2570 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2571 | want the the sign bit of the quick value. */ | |
2572 | shift_steps = cris_get_asr_shift_steps (inst); | |
2573 | value = inst_env->reg[REG_PC]; | |
2574 | if (value & SIGNED_DWORD_MASK) | |
2575 | { | |
2576 | signed_extend_mask = 0xFFFFFFFF; | |
2577 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2578 | signed_extend_mask = ~signed_extend_mask; | |
2579 | } | |
2580 | value = value >> shift_steps; | |
2581 | value |= signed_extend_mask; | |
2582 | inst_env->reg[REG_PC] = value; | |
2583 | } | |
2584 | inst_env->slot_needed = 0; | |
2585 | inst_env->prefix_found = 0; | |
2586 | inst_env->xflag_found = 0; | |
2587 | inst_env->disable_interrupt = 0; | |
2588 | } | |
2589 | ||
2590 | /* Handles the AX, EI and SETF instruction. */ | |
2591 | ||
a78f21af | 2592 | static void |
29134980 OF |
2593 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2594 | { | |
2595 | if (inst_env->prefix_found) | |
2596 | { | |
2597 | inst_env->invalid = 1; | |
2598 | return; | |
2599 | } | |
2600 | /* Check if the instruction is setting the X flag. */ | |
2601 | if (cris_is_xflag_bit_on (inst)) | |
2602 | { | |
2603 | inst_env->xflag_found = 1; | |
2604 | } | |
2605 | else | |
2606 | { | |
2607 | inst_env->xflag_found = 0; | |
2608 | } | |
2609 | inst_env->slot_needed = 0; | |
2610 | inst_env->prefix_found = 0; | |
2611 | inst_env->disable_interrupt = 1; | |
2612 | } | |
2613 | ||
2614 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2615 | register. Note that check_assign assumes that the caller has checked that | |
2616 | there is a prefix to this instruction. The mode check depends on this. */ | |
2617 | ||
a78f21af | 2618 | static void |
29134980 OF |
2619 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2620 | { | |
2621 | /* Check if it's an assign addressing mode. */ | |
2622 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2623 | { | |
2624 | /* Assign the prefix value to operand 1. */ | |
2625 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2626 | } | |
2627 | } | |
2628 | ||
2629 | /* Handles the 2-operand BOUND instruction. */ | |
2630 | ||
a78f21af | 2631 | static void |
29134980 OF |
2632 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2633 | { | |
2634 | /* It's invalid to have the PC as the index operand. */ | |
2635 | if (cris_get_operand2 (inst) == REG_PC) | |
2636 | { | |
2637 | inst_env->invalid = 1; | |
2638 | return; | |
2639 | } | |
2640 | /* Check if we have a prefix. */ | |
2641 | if (inst_env->prefix_found) | |
2642 | { | |
2643 | check_assign (inst, inst_env); | |
2644 | } | |
2645 | /* Check if this is an autoincrement mode. */ | |
2646 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2647 | { | |
2648 | /* It's invalid to change the PC in a delay slot. */ | |
2649 | if (inst_env->slot_needed) | |
2650 | { | |
2651 | inst_env->invalid = 1; | |
2652 | return; | |
2653 | } | |
2654 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2655 | } | |
2656 | inst_env->slot_needed = 0; | |
2657 | inst_env->prefix_found = 0; | |
2658 | inst_env->xflag_found = 0; | |
2659 | inst_env->disable_interrupt = 0; | |
2660 | } | |
2661 | ||
2662 | /* Handles the 3-operand BOUND instruction. */ | |
2663 | ||
a78f21af | 2664 | static void |
29134980 OF |
2665 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2666 | { | |
2667 | /* It's an error if we haven't got a prefix. And it's also an error | |
2668 | if the PC is the destination register. */ | |
2669 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2670 | { | |
2671 | inst_env->invalid = 1; | |
2672 | return; | |
2673 | } | |
2674 | inst_env->slot_needed = 0; | |
2675 | inst_env->prefix_found = 0; | |
2676 | inst_env->xflag_found = 0; | |
2677 | inst_env->disable_interrupt = 0; | |
2678 | } | |
2679 | ||
2680 | /* Clears the status flags in inst_env. */ | |
2681 | ||
a78f21af | 2682 | static void |
29134980 OF |
2683 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2684 | { | |
2685 | /* It's an error if we have got a prefix. */ | |
2686 | if (inst_env->prefix_found) | |
2687 | { | |
2688 | inst_env->invalid = 1; | |
2689 | return; | |
2690 | } | |
2691 | ||
2692 | inst_env->slot_needed = 0; | |
2693 | inst_env->prefix_found = 0; | |
2694 | inst_env->xflag_found = 0; | |
2695 | inst_env->disable_interrupt = 0; | |
2696 | } | |
2697 | ||
2698 | /* Clears the status flags in inst_env. */ | |
2699 | ||
a78f21af | 2700 | static void |
29134980 OF |
2701 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2702 | { | |
2703 | /* It's an error if we have got a prefix. */ | |
2704 | if (inst_env->prefix_found) | |
2705 | { | |
2706 | inst_env->invalid = 1; | |
2707 | return; | |
2708 | } | |
2709 | ||
2710 | inst_env->slot_needed = 0; | |
2711 | inst_env->prefix_found = 0; | |
2712 | inst_env->xflag_found = 0; | |
2713 | inst_env->disable_interrupt = 1; | |
2714 | } | |
2715 | ||
2716 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2717 | ||
a78f21af | 2718 | static void |
29134980 OF |
2719 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2720 | { | |
2721 | /* Check if the target is the PC. */ | |
2722 | if (cris_get_operand2 (inst) == REG_PC) | |
2723 | { | |
2724 | /* The instruction will clear the instruction's size bits. */ | |
2725 | int clear_size = cris_get_clear_size (inst); | |
2726 | if (clear_size == INST_BYTE_SIZE) | |
2727 | { | |
2728 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2729 | } | |
2730 | if (clear_size == INST_WORD_SIZE) | |
2731 | { | |
2732 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2733 | } | |
2734 | if (clear_size == INST_DWORD_SIZE) | |
2735 | { | |
2736 | inst_env->delay_slot_pc = 0x0; | |
2737 | } | |
2738 | /* The jump will be delayed with one delay slot. So we need a delay | |
2739 | slot. */ | |
2740 | inst_env->slot_needed = 1; | |
2741 | inst_env->delay_slot_pc_active = 1; | |
2742 | } | |
2743 | else | |
2744 | { | |
2745 | /* The PC will not change => no delay slot. */ | |
2746 | inst_env->slot_needed = 0; | |
2747 | } | |
2748 | inst_env->prefix_found = 0; | |
2749 | inst_env->xflag_found = 0; | |
2750 | inst_env->disable_interrupt = 0; | |
2751 | } | |
2752 | ||
2753 | /* Handles the TEST instruction if it's in register mode. */ | |
2754 | ||
a78f21af | 2755 | static void |
29134980 OF |
2756 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2757 | { | |
2758 | /* It's an error if we have got a prefix. */ | |
2759 | if (inst_env->prefix_found) | |
2760 | { | |
2761 | inst_env->invalid = 1; | |
2762 | return; | |
2763 | } | |
2764 | inst_env->slot_needed = 0; | |
2765 | inst_env->prefix_found = 0; | |
2766 | inst_env->xflag_found = 0; | |
2767 | inst_env->disable_interrupt = 0; | |
2768 | ||
2769 | } | |
2770 | ||
2771 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2772 | in register mode. */ | |
2773 | ||
a78f21af | 2774 | static void |
29134980 OF |
2775 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2776 | { | |
2777 | /* Check if we are in a prefix mode. */ | |
2778 | if (inst_env->prefix_found) | |
2779 | { | |
2780 | /* The only way the PC can change is if this instruction is in | |
2781 | assign addressing mode. */ | |
2782 | check_assign (inst, inst_env); | |
2783 | } | |
2784 | /* Indirect mode can't change the PC so just check if the mode is | |
2785 | autoincrement. */ | |
2786 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2787 | { | |
2788 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2789 | } | |
2790 | inst_env->slot_needed = 0; | |
2791 | inst_env->prefix_found = 0; | |
2792 | inst_env->xflag_found = 0; | |
2793 | inst_env->disable_interrupt = 0; | |
2794 | } | |
2795 | ||
2796 | /* Checks that the PC isn't the destination register or the instructions has | |
2797 | a prefix. */ | |
2798 | ||
a78f21af | 2799 | static void |
29134980 OF |
2800 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2801 | { | |
2802 | /* It's invalid to have the PC as the destination. The instruction can't | |
2803 | have a prefix. */ | |
2804 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2805 | { | |
2806 | inst_env->invalid = 1; | |
2807 | return; | |
2808 | } | |
2809 | ||
2810 | inst_env->slot_needed = 0; | |
2811 | inst_env->prefix_found = 0; | |
2812 | inst_env->xflag_found = 0; | |
2813 | inst_env->disable_interrupt = 0; | |
2814 | } | |
2815 | ||
2816 | /* Checks that the instruction doesn't have a prefix. */ | |
2817 | ||
a78f21af | 2818 | static void |
29134980 OF |
2819 | break_op (unsigned short inst, inst_env_type *inst_env) |
2820 | { | |
2821 | /* The instruction can't have a prefix. */ | |
2822 | if (inst_env->prefix_found) | |
2823 | { | |
2824 | inst_env->invalid = 1; | |
2825 | return; | |
2826 | } | |
2827 | ||
2828 | inst_env->slot_needed = 0; | |
2829 | inst_env->prefix_found = 0; | |
2830 | inst_env->xflag_found = 0; | |
2831 | inst_env->disable_interrupt = 1; | |
2832 | } | |
2833 | ||
2834 | /* Checks that the PC isn't the destination register and that the instruction | |
2835 | doesn't have a prefix. */ | |
2836 | ||
a78f21af | 2837 | static void |
29134980 OF |
2838 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2839 | { | |
2840 | /* It's invalid to have the PC as the destination. The instruction can't | |
2841 | have a prefix. */ | |
2842 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2843 | { | |
2844 | inst_env->invalid = 1; | |
2845 | return; | |
2846 | } | |
2847 | ||
2848 | inst_env->slot_needed = 0; | |
2849 | inst_env->prefix_found = 0; | |
2850 | inst_env->xflag_found = 0; | |
2851 | inst_env->disable_interrupt = 1; | |
2852 | } | |
2853 | ||
2854 | /* Handles the register mode JUMP instruction. */ | |
2855 | ||
a78f21af | 2856 | static void |
29134980 OF |
2857 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2858 | { | |
2859 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2860 | you can't have a prefix. */ | |
2861 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2862 | { | |
2863 | inst_env->invalid = 1; | |
2864 | return; | |
2865 | } | |
2866 | ||
2867 | /* Just change the PC. */ | |
2868 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2869 | inst_env->slot_needed = 0; | |
2870 | inst_env->prefix_found = 0; | |
2871 | inst_env->xflag_found = 0; | |
2872 | inst_env->disable_interrupt = 1; | |
2873 | } | |
2874 | ||
2875 | /* Handles the JUMP instruction for all modes except register. */ | |
2876 | ||
a78f21af AC |
2877 | static void |
2878 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2879 | { |
2880 | unsigned long newpc; | |
2881 | CORE_ADDR address; | |
2882 | ||
2883 | /* It's invalid to do a JUMP in a delay slot. */ | |
2884 | if (inst_env->slot_needed) | |
2885 | { | |
2886 | inst_env->invalid = 1; | |
2887 | } | |
2888 | else | |
2889 | { | |
2890 | /* Check if we have a prefix. */ | |
2891 | if (inst_env->prefix_found) | |
2892 | { | |
2893 | check_assign (inst, inst_env); | |
2894 | ||
2895 | /* Get the new value for the the PC. */ | |
2896 | newpc = | |
2897 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2898 | 4); | |
2899 | } | |
2900 | else | |
2901 | { | |
2902 | /* Get the new value for the PC. */ | |
2903 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2904 | newpc = read_memory_unsigned_integer (address, 4); | |
2905 | ||
2906 | /* Check if we should increment a register. */ | |
2907 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2908 | { | |
2909 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2910 | } | |
2911 | } | |
2912 | inst_env->reg[REG_PC] = newpc; | |
2913 | } | |
2914 | inst_env->slot_needed = 0; | |
2915 | inst_env->prefix_found = 0; | |
2916 | inst_env->xflag_found = 0; | |
2917 | inst_env->disable_interrupt = 1; | |
2918 | } | |
2919 | ||
2920 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2921 | ||
a78f21af | 2922 | static void |
29134980 OF |
2923 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2924 | { | |
2925 | if (inst_env->prefix_found) | |
2926 | { | |
2927 | /* The instruction has a prefix that means we are only interested if | |
2928 | the instruction is in assign mode. */ | |
2929 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2930 | { | |
2931 | /* The prefix handles the problem if we are in a delay slot. */ | |
2932 | if (cris_get_operand1 (inst) == REG_PC) | |
2933 | { | |
2934 | /* Just take care of the assign. */ | |
2935 | check_assign (inst, inst_env); | |
2936 | } | |
2937 | } | |
2938 | } | |
2939 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2940 | { | |
2941 | /* The instruction doesn't have a prefix, the only case left that we | |
2942 | are interested in is the autoincrement mode. */ | |
2943 | if (cris_get_operand1 (inst) == REG_PC) | |
2944 | { | |
2945 | /* If the PC is to be incremented it's invalid to be in a | |
2946 | delay slot. */ | |
2947 | if (inst_env->slot_needed) | |
2948 | { | |
2949 | inst_env->invalid = 1; | |
2950 | return; | |
2951 | } | |
2a9ecef2 OF |
2952 | |
2953 | /* The increment depends on the size of the special register. */ | |
2954 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2955 | { |
2956 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2957 | } | |
2a9ecef2 | 2958 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2959 | { |
2960 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2961 | } | |
2962 | else | |
2963 | { | |
2964 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2965 | } | |
2966 | } | |
2967 | } | |
2968 | inst_env->slot_needed = 0; | |
2969 | inst_env->prefix_found = 0; | |
2970 | inst_env->xflag_found = 0; | |
2971 | inst_env->disable_interrupt = 1; | |
2972 | } | |
2973 | ||
2974 | /* Handles moves from special registers (aka P-register) for all modes | |
2975 | except register. */ | |
2976 | ||
a78f21af | 2977 | static void |
29134980 OF |
2978 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2979 | { | |
2980 | if (inst_env->prefix_found) | |
2981 | { | |
2982 | /* The instruction has a prefix that means we are only interested if | |
2983 | the instruction is in assign mode. */ | |
2984 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2985 | { | |
2986 | /* The prefix handles the problem if we are in a delay slot. */ | |
2987 | if (cris_get_operand1 (inst) == REG_PC) | |
2988 | { | |
2989 | /* Just take care of the assign. */ | |
2990 | check_assign (inst, inst_env); | |
2991 | } | |
2992 | } | |
2993 | } | |
2994 | /* The instruction doesn't have a prefix, the only case left that we | |
2995 | are interested in is the autoincrement mode. */ | |
2996 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2997 | { | |
2998 | if (cris_get_operand1 (inst) == REG_PC) | |
2999 | { | |
3000 | /* If the PC is to be incremented it's invalid to be in a | |
3001 | delay slot. */ | |
3002 | if (inst_env->slot_needed) | |
3003 | { | |
3004 | inst_env->invalid = 1; | |
3005 | return; | |
3006 | } | |
2a9ecef2 OF |
3007 | |
3008 | /* The increment depends on the size of the special register. */ | |
3009 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
3010 | { |
3011 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
3012 | } | |
2a9ecef2 | 3013 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
3014 | { |
3015 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
3016 | } | |
3017 | else | |
3018 | { | |
3019 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
3020 | } | |
3021 | } | |
3022 | } | |
3023 | inst_env->slot_needed = 0; | |
3024 | inst_env->prefix_found = 0; | |
3025 | inst_env->xflag_found = 0; | |
3026 | inst_env->disable_interrupt = 1; | |
3027 | } | |
3028 | ||
3029 | /* Handles moves from special registers (aka P-register) when the mode | |
3030 | is register. */ | |
3031 | ||
a78f21af | 3032 | static void |
29134980 OF |
3033 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
3034 | { | |
3035 | /* Register mode move from special register can't have a prefix. */ | |
3036 | if (inst_env->prefix_found) | |
3037 | { | |
3038 | inst_env->invalid = 1; | |
3039 | return; | |
3040 | } | |
3041 | ||
3042 | if (cris_get_operand1 (inst) == REG_PC) | |
3043 | { | |
3044 | /* It's invalid to change the PC in a delay slot. */ | |
3045 | if (inst_env->slot_needed) | |
3046 | { | |
3047 | inst_env->invalid = 1; | |
3048 | return; | |
3049 | } | |
3050 | /* The destination is the PC, the jump will have a delay slot. */ | |
3051 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3052 | inst_env->slot_needed = 1; | |
3053 | inst_env->delay_slot_pc_active = 1; | |
3054 | } | |
3055 | else | |
3056 | { | |
3057 | /* If the destination isn't PC, there will be no jump. */ | |
3058 | inst_env->slot_needed = 0; | |
3059 | } | |
3060 | inst_env->prefix_found = 0; | |
3061 | inst_env->xflag_found = 0; | |
3062 | inst_env->disable_interrupt = 1; | |
3063 | } | |
3064 | ||
3065 | /* Handles the MOVEM from memory to general register instruction. */ | |
3066 | ||
a78f21af | 3067 | static void |
29134980 OF |
3068 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3069 | { | |
3070 | if (inst_env->prefix_found) | |
3071 | { | |
3072 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3073 | MOVEM instruction going to change the PC? */ | |
3074 | if (cris_get_operand2 (inst) >= REG_PC) | |
3075 | { | |
3076 | inst_env->reg[REG_PC] = | |
3077 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
3078 | } | |
3079 | /* The assign value is the value after the increment. Normally, the | |
3080 | assign value is the value before the increment. */ | |
3081 | if ((cris_get_operand1 (inst) == REG_PC) | |
3082 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3083 | { | |
3084 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3085 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3086 | } | |
3087 | } | |
3088 | else | |
3089 | { | |
3090 | /* Is the MOVEM instruction going to change the PC? */ | |
3091 | if (cris_get_operand2 (inst) == REG_PC) | |
3092 | { | |
3093 | /* It's invalid to change the PC in a delay slot. */ | |
3094 | if (inst_env->slot_needed) | |
3095 | { | |
3096 | inst_env->invalid = 1; | |
3097 | return; | |
3098 | } | |
3099 | inst_env->reg[REG_PC] = | |
3100 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3101 | 4); | |
3102 | } | |
3103 | /* The increment is not depending on the size, instead it's depending | |
3104 | on the number of registers loaded from memory. */ | |
3105 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3106 | { | |
3107 | /* It's invalid to change the PC in a delay slot. */ | |
3108 | if (inst_env->slot_needed) | |
3109 | { | |
3110 | inst_env->invalid = 1; | |
3111 | return; | |
3112 | } | |
3113 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3114 | } | |
3115 | } | |
3116 | inst_env->slot_needed = 0; | |
3117 | inst_env->prefix_found = 0; | |
3118 | inst_env->xflag_found = 0; | |
3119 | inst_env->disable_interrupt = 0; | |
3120 | } | |
3121 | ||
3122 | /* Handles the MOVEM to memory from general register instruction. */ | |
3123 | ||
a78f21af | 3124 | static void |
29134980 OF |
3125 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3126 | { | |
3127 | if (inst_env->prefix_found) | |
3128 | { | |
3129 | /* The assign value is the value after the increment. Normally, the | |
3130 | assign value is the value before the increment. */ | |
3131 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3132 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3133 | { | |
3134 | /* The prefix handles the problem if we are in a delay slot. */ | |
3135 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3136 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3137 | } | |
3138 | } | |
3139 | else | |
3140 | { | |
3141 | /* The increment is not depending on the size, instead it's depending | |
3142 | on the number of registers loaded to memory. */ | |
3143 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3144 | { | |
3145 | /* It's invalid to change the PC in a delay slot. */ | |
3146 | if (inst_env->slot_needed) | |
3147 | { | |
3148 | inst_env->invalid = 1; | |
3149 | return; | |
3150 | } | |
3151 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3152 | } | |
3153 | } | |
3154 | inst_env->slot_needed = 0; | |
3155 | inst_env->prefix_found = 0; | |
3156 | inst_env->xflag_found = 0; | |
3157 | inst_env->disable_interrupt = 0; | |
3158 | } | |
3159 | ||
29134980 OF |
3160 | /* Handles the intructions that's not yet implemented, by setting |
3161 | inst_env->invalid to true. */ | |
3162 | ||
a78f21af | 3163 | static void |
29134980 OF |
3164 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3165 | { | |
3166 | inst_env->invalid = 1; | |
3167 | } | |
3168 | ||
3169 | /* Handles the XOR instruction. */ | |
3170 | ||
a78f21af | 3171 | static void |
29134980 OF |
3172 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3173 | { | |
3174 | /* XOR can't have a prefix. */ | |
3175 | if (inst_env->prefix_found) | |
3176 | { | |
3177 | inst_env->invalid = 1; | |
3178 | return; | |
3179 | } | |
3180 | ||
3181 | /* Check if the PC is the target. */ | |
3182 | if (cris_get_operand2 (inst) == REG_PC) | |
3183 | { | |
3184 | /* It's invalid to change the PC in a delay slot. */ | |
3185 | if (inst_env->slot_needed) | |
3186 | { | |
3187 | inst_env->invalid = 1; | |
3188 | return; | |
3189 | } | |
3190 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3191 | } | |
3192 | inst_env->slot_needed = 0; | |
3193 | inst_env->prefix_found = 0; | |
3194 | inst_env->xflag_found = 0; | |
3195 | inst_env->disable_interrupt = 0; | |
3196 | } | |
3197 | ||
3198 | /* Handles the MULS instruction. */ | |
3199 | ||
a78f21af | 3200 | static void |
29134980 OF |
3201 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3202 | { | |
3203 | /* MULS/U can't have a prefix. */ | |
3204 | if (inst_env->prefix_found) | |
3205 | { | |
3206 | inst_env->invalid = 1; | |
3207 | return; | |
3208 | } | |
3209 | ||
3210 | /* Consider it invalid if the PC is the target. */ | |
3211 | if (cris_get_operand2 (inst) == REG_PC) | |
3212 | { | |
3213 | inst_env->invalid = 1; | |
3214 | return; | |
3215 | } | |
3216 | inst_env->slot_needed = 0; | |
3217 | inst_env->prefix_found = 0; | |
3218 | inst_env->xflag_found = 0; | |
3219 | inst_env->disable_interrupt = 0; | |
3220 | } | |
3221 | ||
3222 | /* Handles the MULU instruction. */ | |
3223 | ||
a78f21af | 3224 | static void |
29134980 OF |
3225 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3226 | { | |
3227 | /* MULS/U can't have a prefix. */ | |
3228 | if (inst_env->prefix_found) | |
3229 | { | |
3230 | inst_env->invalid = 1; | |
3231 | return; | |
3232 | } | |
3233 | ||
3234 | /* Consider it invalid if the PC is the target. */ | |
3235 | if (cris_get_operand2 (inst) == REG_PC) | |
3236 | { | |
3237 | inst_env->invalid = 1; | |
3238 | return; | |
3239 | } | |
3240 | inst_env->slot_needed = 0; | |
3241 | inst_env->prefix_found = 0; | |
3242 | inst_env->xflag_found = 0; | |
3243 | inst_env->disable_interrupt = 0; | |
3244 | } | |
3245 | ||
3246 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3247 | The MOVE instruction is the move from source to register. */ | |
3248 | ||
a78f21af | 3249 | static void |
29134980 OF |
3250 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3251 | unsigned long source1, unsigned long source2) | |
3252 | { | |
3253 | unsigned long pc_mask; | |
3254 | unsigned long operation_mask; | |
3255 | ||
3256 | /* Find out how many bits the operation should apply to. */ | |
3257 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3258 | { | |
3259 | pc_mask = 0xFFFFFF00; | |
3260 | operation_mask = 0xFF; | |
3261 | } | |
3262 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3263 | { | |
3264 | pc_mask = 0xFFFF0000; | |
3265 | operation_mask = 0xFFFF; | |
3266 | } | |
3267 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3268 | { | |
3269 | pc_mask = 0x0; | |
3270 | operation_mask = 0xFFFFFFFF; | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | /* The size is out of range. */ | |
3275 | inst_env->invalid = 1; | |
3276 | return; | |
3277 | } | |
3278 | ||
3279 | /* The instruction just works on uw_operation_mask bits. */ | |
3280 | source2 &= operation_mask; | |
3281 | source1 &= operation_mask; | |
3282 | ||
3283 | /* Now calculate the result. The opcode's 3 first bits separates | |
3284 | the different actions. */ | |
3285 | switch (cris_get_opcode (inst) & 7) | |
3286 | { | |
3287 | case 0: /* add */ | |
3288 | source1 += source2; | |
3289 | break; | |
3290 | ||
3291 | case 1: /* move */ | |
3292 | source1 = source2; | |
3293 | break; | |
3294 | ||
3295 | case 2: /* subtract */ | |
3296 | source1 -= source2; | |
3297 | break; | |
3298 | ||
3299 | case 3: /* compare */ | |
3300 | break; | |
3301 | ||
3302 | case 4: /* and */ | |
3303 | source1 &= source2; | |
3304 | break; | |
3305 | ||
3306 | case 5: /* or */ | |
3307 | source1 |= source2; | |
3308 | break; | |
3309 | ||
3310 | default: | |
3311 | inst_env->invalid = 1; | |
3312 | return; | |
3313 | ||
3314 | break; | |
3315 | } | |
3316 | ||
3317 | /* Make sure that the result doesn't contain more than the instruction | |
3318 | size bits. */ | |
3319 | source2 &= operation_mask; | |
3320 | ||
3321 | /* Calculate the new breakpoint address. */ | |
3322 | inst_env->reg[REG_PC] &= pc_mask; | |
3323 | inst_env->reg[REG_PC] |= source1; | |
3324 | ||
3325 | } | |
3326 | ||
3327 | /* Extends the value from either byte or word size to a dword. If the mode | |
3328 | is zero extend then the value is extended with zero. If instead the mode | |
3329 | is signed extend the sign bit of the value is taken into consideration. */ | |
3330 | ||
a78f21af | 3331 | static unsigned long |
29134980 OF |
3332 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3333 | { | |
3334 | /* The size can be either byte or word, check which one it is. | |
3335 | Don't check the highest bit, it's indicating if it's a zero | |
3336 | or sign extend. */ | |
3337 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3338 | { | |
3339 | /* Word size. */ | |
3340 | value &= 0xFFFF; | |
3341 | ||
3342 | /* Check if the instruction is signed extend. If so, check if value has | |
3343 | the sign bit on. */ | |
3344 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3345 | { | |
3346 | value |= SIGNED_WORD_EXTEND_MASK; | |
3347 | } | |
3348 | } | |
3349 | else | |
3350 | { | |
3351 | /* Byte size. */ | |
3352 | value &= 0xFF; | |
3353 | ||
3354 | /* Check if the instruction is signed extend. If so, check if value has | |
3355 | the sign bit on. */ | |
3356 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3357 | { | |
3358 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3359 | } | |
3360 | } | |
3361 | /* The size should now be dword. */ | |
3362 | cris_set_size_to_dword (inst); | |
3363 | return value; | |
3364 | } | |
3365 | ||
3366 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3367 | instruction. The MOVE instruction is the move from source to register. */ | |
3368 | ||
a78f21af | 3369 | static void |
29134980 OF |
3370 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3371 | inst_env_type *inst_env) | |
3372 | { | |
3373 | unsigned long operand1; | |
3374 | unsigned long operand2; | |
3375 | ||
3376 | /* It's invalid to have a prefix to the instruction. This is a register | |
3377 | mode instruction and can't have a prefix. */ | |
3378 | if (inst_env->prefix_found) | |
3379 | { | |
3380 | inst_env->invalid = 1; | |
3381 | return; | |
3382 | } | |
3383 | /* Check if the instruction has PC as its target. */ | |
3384 | if (cris_get_operand2 (inst) == REG_PC) | |
3385 | { | |
3386 | if (inst_env->slot_needed) | |
3387 | { | |
3388 | inst_env->invalid = 1; | |
3389 | return; | |
3390 | } | |
3391 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3392 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3393 | operand2 = inst_env->reg[REG_PC]; |
3394 | ||
3395 | /* Check if it's a extend, signed or zero instruction. */ | |
3396 | if (cris_get_opcode (inst) < 4) | |
3397 | { | |
3398 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3399 | } | |
3400 | /* Calculate the PC value after the instruction, i.e. where the | |
3401 | breakpoint should be. The order of the udw_operands is vital. */ | |
3402 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3403 | } | |
3404 | inst_env->slot_needed = 0; | |
3405 | inst_env->prefix_found = 0; | |
3406 | inst_env->xflag_found = 0; | |
3407 | inst_env->disable_interrupt = 0; | |
3408 | } | |
3409 | ||
3410 | /* Returns the data contained at address. The size of the data is derived from | |
3411 | the size of the operation. If the instruction is a zero or signed | |
3412 | extend instruction, the size field is changed in instruction. */ | |
3413 | ||
a78f21af | 3414 | static unsigned long |
29134980 OF |
3415 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3416 | { | |
3417 | int size = cris_get_size (*inst); | |
3418 | unsigned long value; | |
3419 | ||
3420 | /* If it's an extend instruction we don't want the signed extend bit, | |
3421 | because it influences the size. */ | |
3422 | if (cris_get_opcode (*inst) < 4) | |
3423 | { | |
3424 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3425 | } | |
3426 | /* Is there a need for checking the size? Size should contain the number of | |
3427 | bytes to read. */ | |
3428 | size = 1 << size; | |
3429 | value = read_memory_unsigned_integer (address, size); | |
3430 | ||
3431 | /* Check if it's an extend, signed or zero instruction. */ | |
3432 | if (cris_get_opcode (*inst) < 4) | |
3433 | { | |
3434 | value = do_sign_or_zero_extend (value, inst); | |
3435 | } | |
3436 | return value; | |
3437 | } | |
3438 | ||
3439 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3440 | instructions. The MOVE instruction is the move from source to register. */ | |
3441 | ||
a78f21af | 3442 | static void |
29134980 OF |
3443 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3444 | inst_env_type *inst_env) | |
3445 | { | |
3446 | unsigned long operand2; | |
3447 | unsigned long operand3; | |
3448 | ||
3449 | check_assign (inst, inst_env); | |
3450 | if (cris_get_operand2 (inst) == REG_PC) | |
3451 | { | |
3452 | operand2 = inst_env->reg[REG_PC]; | |
3453 | ||
3454 | /* Get the value of the third operand. */ | |
3455 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3456 | ||
3457 | /* Calculate the PC value after the instruction, i.e. where the | |
3458 | breakpoint should be. The order of the udw_operands is vital. */ | |
3459 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3460 | } | |
3461 | inst_env->slot_needed = 0; | |
3462 | inst_env->prefix_found = 0; | |
3463 | inst_env->xflag_found = 0; | |
3464 | inst_env->disable_interrupt = 0; | |
3465 | } | |
3466 | ||
3467 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3468 | OR instructions. Note that for this to work as expected, the calling | |
3469 | function must have made sure that there is a prefix to this instruction. */ | |
3470 | ||
a78f21af | 3471 | static void |
29134980 OF |
3472 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3473 | inst_env_type *inst_env) | |
3474 | { | |
3475 | unsigned long operand2; | |
3476 | unsigned long operand3; | |
3477 | ||
3478 | if (cris_get_operand1 (inst) == REG_PC) | |
3479 | { | |
3480 | /* The PC will be changed by the instruction. */ | |
3481 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3482 | ||
3483 | /* Get the value of the third operand. */ | |
3484 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3485 | ||
3486 | /* Calculate the PC value after the instruction, i.e. where the | |
3487 | breakpoint should be. */ | |
3488 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3489 | } | |
3490 | inst_env->slot_needed = 0; | |
3491 | inst_env->prefix_found = 0; | |
3492 | inst_env->xflag_found = 0; | |
3493 | inst_env->disable_interrupt = 0; | |
3494 | } | |
3495 | ||
3496 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3497 | instructions. The MOVE instruction is the move from source to register. */ | |
3498 | ||
a78f21af | 3499 | static void |
29134980 OF |
3500 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3501 | inst_env_type *inst_env) | |
3502 | { | |
3503 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3504 | { | |
3505 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3506 | SUB, AND or OR something weird is going on (if everything works these | |
3507 | instructions should end up in the three operand version). */ | |
3508 | inst_env->invalid = 1; | |
3509 | return; | |
3510 | } | |
3511 | else | |
3512 | { | |
3513 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3514 | so use it. */ | |
3515 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3516 | } | |
3517 | inst_env->slot_needed = 0; | |
3518 | inst_env->prefix_found = 0; | |
3519 | inst_env->xflag_found = 0; | |
3520 | inst_env->disable_interrupt = 0; | |
3521 | } | |
3522 | ||
3523 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3524 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3525 | source to register. */ | |
3526 | ||
a78f21af | 3527 | static void |
29134980 OF |
3528 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3529 | inst_env_type *inst_env) | |
3530 | { | |
3531 | unsigned long operand1; | |
3532 | unsigned long operand2; | |
3533 | unsigned long operand3; | |
3534 | int size; | |
3535 | ||
3536 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3537 | Check if the destination register is the PC. */ | |
3538 | if (cris_get_operand2 (inst) == REG_PC) | |
3539 | { | |
3540 | /* Must be done here, get_data_from_address may change the size | |
3541 | field. */ | |
3542 | size = cris_get_size (inst); | |
3543 | operand2 = inst_env->reg[REG_PC]; | |
3544 | ||
3545 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3546 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3547 | operand3 = get_data_from_address (&inst, operand1); | |
3548 | ||
3549 | /* Calculate the PC value after the instruction, i.e. where the | |
3550 | breakpoint should be. The order of the udw_operands is vital. */ | |
3551 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3552 | } | |
3553 | /* If this is an autoincrement addressing mode, check if the increment | |
3554 | changes the PC. */ | |
3555 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3556 | { | |
3557 | /* Get the size field. */ | |
3558 | size = cris_get_size (inst); | |
3559 | ||
3560 | /* If it's an extend instruction we don't want the signed extend bit, | |
3561 | because it influences the size. */ | |
3562 | if (cris_get_opcode (inst) < 4) | |
3563 | { | |
3564 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3565 | } | |
3566 | process_autoincrement (size, inst, inst_env); | |
3567 | } | |
3568 | inst_env->slot_needed = 0; | |
3569 | inst_env->prefix_found = 0; | |
3570 | inst_env->xflag_found = 0; | |
3571 | inst_env->disable_interrupt = 0; | |
3572 | } | |
3573 | ||
3574 | /* Handles the two-operand addressing mode, all modes except register, for | |
3575 | the ADD, SUB CMP, AND and OR instruction. */ | |
3576 | ||
a78f21af | 3577 | static void |
29134980 OF |
3578 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3579 | inst_env_type *inst_env) | |
3580 | { | |
3581 | if (inst_env->prefix_found) | |
3582 | { | |
3583 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3584 | { | |
3585 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3586 | } | |
3587 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3588 | { | |
3589 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3590 | } | |
3591 | else | |
3592 | { | |
3593 | /* The mode is invalid for a prefixed base instruction. */ | |
3594 | inst_env->invalid = 1; | |
3595 | return; | |
3596 | } | |
3597 | } | |
3598 | else | |
3599 | { | |
3600 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3605 | ||
a78f21af | 3606 | static void |
29134980 OF |
3607 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3608 | { | |
3609 | unsigned long operand1; | |
3610 | unsigned long operand2; | |
3611 | ||
3612 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3613 | instruction and can't have a prefix. */ | |
3614 | if (inst_env->prefix_found) | |
3615 | { | |
3616 | inst_env->invalid = 1; | |
3617 | return; | |
3618 | } | |
3619 | ||
3620 | /* Check if the instruction has PC as its target. */ | |
3621 | if (cris_get_operand2 (inst) == REG_PC) | |
3622 | { | |
3623 | if (inst_env->slot_needed) | |
3624 | { | |
3625 | inst_env->invalid = 1; | |
3626 | return; | |
3627 | } | |
3628 | operand1 = cris_get_quick_value (inst); | |
3629 | operand2 = inst_env->reg[REG_PC]; | |
3630 | ||
3631 | /* The size should now be dword. */ | |
3632 | cris_set_size_to_dword (&inst); | |
3633 | ||
3634 | /* Calculate the PC value after the instruction, i.e. where the | |
3635 | breakpoint should be. */ | |
3636 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3637 | } | |
3638 | inst_env->slot_needed = 0; | |
3639 | inst_env->prefix_found = 0; | |
3640 | inst_env->xflag_found = 0; | |
3641 | inst_env->disable_interrupt = 0; | |
3642 | } | |
3643 | ||
3644 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3645 | ||
a78f21af | 3646 | static void |
29134980 OF |
3647 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3648 | { | |
3649 | unsigned long operand1; | |
3650 | unsigned long operand2; | |
3651 | ||
3652 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3653 | instruction and can't have a prefix. */ | |
3654 | if (inst_env->prefix_found) | |
3655 | { | |
3656 | inst_env->invalid = 1; | |
3657 | return; | |
3658 | } | |
3659 | /* Check if the instruction has PC as its target. */ | |
3660 | if (cris_get_operand2 (inst) == REG_PC) | |
3661 | { | |
3662 | if (inst_env->slot_needed) | |
3663 | { | |
3664 | inst_env->invalid = 1; | |
3665 | return; | |
3666 | } | |
3667 | /* The instruction has the PC as its target register. */ | |
3668 | operand1 = cris_get_quick_value (inst); | |
3669 | operand2 = inst_env->reg[REG_PC]; | |
3670 | ||
3671 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3672 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3673 | { | |
3674 | /* sign extend */ | |
3675 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3676 | } | |
3677 | /* The size should now be dword. */ | |
3678 | cris_set_size_to_dword (&inst); | |
3679 | ||
3680 | /* Calculate the PC value after the instruction, i.e. where the | |
3681 | breakpoint should be. */ | |
3682 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3683 | } | |
3684 | inst_env->slot_needed = 0; | |
3685 | inst_env->prefix_found = 0; | |
3686 | inst_env->xflag_found = 0; | |
3687 | inst_env->disable_interrupt = 0; | |
3688 | } | |
3689 | ||
3690 | /* Translate op_type to a function and call it. */ | |
3691 | ||
a78f21af AC |
3692 | static void |
3693 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3694 | inst_env_type *inst_env) | |
29134980 OF |
3695 | { |
3696 | switch (op_type) | |
3697 | { | |
3698 | case cris_not_implemented_op: | |
3699 | not_implemented_op (inst, inst_env); | |
3700 | break; | |
3701 | ||
3702 | case cris_abs_op: | |
3703 | abs_op (inst, inst_env); | |
3704 | break; | |
3705 | ||
3706 | case cris_addi_op: | |
3707 | addi_op (inst, inst_env); | |
3708 | break; | |
3709 | ||
3710 | case cris_asr_op: | |
3711 | asr_op (inst, inst_env); | |
3712 | break; | |
3713 | ||
3714 | case cris_asrq_op: | |
3715 | asrq_op (inst, inst_env); | |
3716 | break; | |
3717 | ||
3718 | case cris_ax_ei_setf_op: | |
3719 | ax_ei_setf_op (inst, inst_env); | |
3720 | break; | |
3721 | ||
3722 | case cris_bdap_prefix: | |
3723 | bdap_prefix (inst, inst_env); | |
3724 | break; | |
3725 | ||
3726 | case cris_biap_prefix: | |
3727 | biap_prefix (inst, inst_env); | |
3728 | break; | |
3729 | ||
3730 | case cris_break_op: | |
3731 | break_op (inst, inst_env); | |
3732 | break; | |
3733 | ||
3734 | case cris_btst_nop_op: | |
3735 | btst_nop_op (inst, inst_env); | |
3736 | break; | |
3737 | ||
3738 | case cris_clearf_di_op: | |
3739 | clearf_di_op (inst, inst_env); | |
3740 | break; | |
3741 | ||
3742 | case cris_dip_prefix: | |
3743 | dip_prefix (inst, inst_env); | |
3744 | break; | |
3745 | ||
3746 | case cris_dstep_logshift_mstep_neg_not_op: | |
3747 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3748 | break; | |
3749 | ||
3750 | case cris_eight_bit_offset_branch_op: | |
3751 | eight_bit_offset_branch_op (inst, inst_env); | |
3752 | break; | |
3753 | ||
3754 | case cris_move_mem_to_reg_movem_op: | |
3755 | move_mem_to_reg_movem_op (inst, inst_env); | |
3756 | break; | |
3757 | ||
3758 | case cris_move_reg_to_mem_movem_op: | |
3759 | move_reg_to_mem_movem_op (inst, inst_env); | |
3760 | break; | |
3761 | ||
3762 | case cris_move_to_preg_op: | |
3763 | move_to_preg_op (inst, inst_env); | |
3764 | break; | |
3765 | ||
3766 | case cris_muls_op: | |
3767 | muls_op (inst, inst_env); | |
3768 | break; | |
3769 | ||
3770 | case cris_mulu_op: | |
3771 | mulu_op (inst, inst_env); | |
3772 | break; | |
3773 | ||
3774 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3775 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3776 | break; | |
3777 | ||
3778 | case cris_none_reg_mode_clear_test_op: | |
3779 | none_reg_mode_clear_test_op (inst, inst_env); | |
3780 | break; | |
3781 | ||
3782 | case cris_none_reg_mode_jump_op: | |
3783 | none_reg_mode_jump_op (inst, inst_env); | |
3784 | break; | |
3785 | ||
3786 | case cris_none_reg_mode_move_from_preg_op: | |
3787 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3788 | break; | |
3789 | ||
3790 | case cris_quick_mode_add_sub_op: | |
3791 | quick_mode_add_sub_op (inst, inst_env); | |
3792 | break; | |
3793 | ||
3794 | case cris_quick_mode_and_cmp_move_or_op: | |
3795 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3796 | break; | |
3797 | ||
3798 | case cris_quick_mode_bdap_prefix: | |
3799 | quick_mode_bdap_prefix (inst, inst_env); | |
3800 | break; | |
3801 | ||
3802 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3803 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3804 | break; | |
3805 | ||
3806 | case cris_reg_mode_clear_op: | |
3807 | reg_mode_clear_op (inst, inst_env); | |
3808 | break; | |
3809 | ||
3810 | case cris_reg_mode_jump_op: | |
3811 | reg_mode_jump_op (inst, inst_env); | |
3812 | break; | |
3813 | ||
3814 | case cris_reg_mode_move_from_preg_op: | |
3815 | reg_mode_move_from_preg_op (inst, inst_env); | |
3816 | break; | |
3817 | ||
3818 | case cris_reg_mode_test_op: | |
3819 | reg_mode_test_op (inst, inst_env); | |
3820 | break; | |
3821 | ||
3822 | case cris_scc_op: | |
3823 | scc_op (inst, inst_env); | |
3824 | break; | |
3825 | ||
3826 | case cris_sixteen_bit_offset_branch_op: | |
3827 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3828 | break; | |
3829 | ||
3830 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3831 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3832 | break; | |
3833 | ||
3834 | case cris_three_operand_bound_op: | |
3835 | three_operand_bound_op (inst, inst_env); | |
3836 | break; | |
3837 | ||
3838 | case cris_two_operand_bound_op: | |
3839 | two_operand_bound_op (inst, inst_env); | |
3840 | break; | |
3841 | ||
3842 | case cris_xor_op: | |
3843 | xor_op (inst, inst_env); | |
3844 | break; | |
3845 | } | |
3846 | } | |
3847 | ||
3848 | /* This wrapper is to avoid cris_get_assembler being called before | |
3849 | exec_bfd has been set. */ | |
3850 | ||
3851 | static int | |
a89aa300 | 3852 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3853 | { |
a89aa300 | 3854 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3855 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3856 | disassembler, even when there is no BFD. Does something like | |
3857 | "gdb; target remote; disassmeble *0x123" work? */ | |
3858 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3859 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3860 | gdb_assert (print_insn != NULL); |
3861 | return print_insn (addr, info); | |
29134980 OF |
3862 | } |
3863 | ||
dbbff683 OF |
3864 | /* Copied from <asm/elf.h>. */ |
3865 | typedef unsigned long elf_greg_t; | |
3866 | ||
3867 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3868 | #define CRISV10_ELF_NGREG 35 |
3869 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3870 | ||
3871 | #define CRISV32_ELF_NGREG 32 | |
3872 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3873 | |
3874 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3875 | ||
a78f21af | 3876 | static void |
dbbff683 OF |
3877 | supply_gregset (elf_gregset_t *gregsetp) |
3878 | { | |
c600d464 | 3879 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3880 | int i; |
3881 | elf_greg_t *regp = *gregsetp; | |
3882 | static char zerobuf[4] = {0}; | |
3883 | ||
3884 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3885 | knows about the actual size of each register so that's no problem. */ | |
3886 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3887 | { | |
23a6d369 | 3888 | regcache_raw_supply (current_regcache, i, (char *)®p[i]); |
dbbff683 | 3889 | } |
c600d464 OF |
3890 | |
3891 | if (tdep->cris_version == 32) | |
3892 | { | |
3893 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3894 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3895 | be wrong. Issue a warning to alert the user. */ | |
3896 | regcache_raw_supply (current_regcache, PC_REGNUM, | |
3897 | (char *)®p[ERP_REGNUM]); | |
3898 | ||
3899 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3900 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3901 | } | |
dbbff683 OF |
3902 | } |
3903 | ||
3904 | /* Use a local version of this function to get the correct types for | |
3905 | regsets, until multi-arch core support is ready. */ | |
3906 | ||
3907 | static void | |
3908 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, | |
3909 | int which, CORE_ADDR reg_addr) | |
3910 | { | |
3911 | elf_gregset_t gregset; | |
3912 | ||
3913 | switch (which) | |
3914 | { | |
3915 | case 0: | |
c600d464 OF |
3916 | if (core_reg_size != sizeof (elf_gregset_t) |
3917 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3918 | { |
8a3fe4f8 | 3919 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3920 | } |
3921 | else | |
3922 | { | |
3923 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
3924 | supply_gregset (&gregset); | |
3925 | } | |
3926 | ||
3927 | default: | |
3928 | /* We've covered all the kinds of registers we know about here, | |
3929 | so this must be something we wouldn't know what to do with | |
3930 | anyway. Just ignore it. */ | |
3931 | break; | |
3932 | } | |
3933 | } | |
3934 | ||
3935 | static struct core_fns cris_elf_core_fns = | |
3936 | { | |
3937 | bfd_target_elf_flavour, /* core_flavour */ | |
3938 | default_check_format, /* check_format */ | |
3939 | default_core_sniffer, /* core_sniffer */ | |
3940 | fetch_core_registers, /* core_read_registers */ | |
3941 | NULL /* next */ | |
3942 | }; | |
3943 | ||
a78f21af AC |
3944 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3945 | ||
29134980 OF |
3946 | void |
3947 | _initialize_cris_tdep (void) | |
3948 | { | |
a5f6c8f5 OF |
3949 | static struct cmd_list_element *cris_set_cmdlist; |
3950 | static struct cmd_list_element *cris_show_cmdlist; | |
3951 | ||
29134980 OF |
3952 | struct cmd_list_element *c; |
3953 | ||
3954 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3955 | ||
29134980 | 3956 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3957 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3958 | &usr_cmd_cris_version, | |
7915a72c AC |
3959 | _("Set the current CRIS version."), |
3960 | _("Show the current CRIS version."), | |
bdd56253 OF |
3961 | _("\ |
3962 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3963 | Defaults to 10. "), | |
2c5b56ce | 3964 | set_cris_version, |
7915a72c | 3965 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3966 | &setlist, &showlist); |
0e6bdb31 OF |
3967 | |
3968 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3969 | cris_modes, &usr_cmd_cris_mode, | |
3970 | _("Set the current CRIS mode."), | |
3971 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3972 | _("\ |
3973 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3974 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3975 | set_cris_mode, |
3976 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3977 | &setlist, &showlist); | |
dbbff683 | 3978 | |
a5f6c8f5 OF |
3979 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3980 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3981 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3982 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3983 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3984 | set_cris_dwarf2_cfi, |
7915a72c | 3985 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3986 | &setlist, &showlist); |
3987 | ||
52bd1401 | 3988 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3989 | } |
3990 | ||
3991 | /* Prints out all target specific values. */ | |
3992 | ||
3993 | static void | |
3994 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3995 | { | |
3996 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3997 | if (tdep != NULL) | |
3998 | { | |
3999 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
4000 | tdep->cris_version); | |
0e6bdb31 OF |
4001 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
4002 | tdep->cris_mode); | |
a5f6c8f5 OF |
4003 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
4004 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
4005 | } |
4006 | } | |
4007 | ||
4008 | static void | |
a5f6c8f5 OF |
4009 | set_cris_version (char *ignore_args, int from_tty, |
4010 | struct cmd_list_element *c) | |
29134980 OF |
4011 | { |
4012 | struct gdbarch_info info; | |
4013 | ||
a5f6c8f5 | 4014 | usr_cmd_cris_version_valid = 1; |
29134980 | 4015 | |
a5f6c8f5 OF |
4016 | /* Update the current architecture, if needed. */ |
4017 | gdbarch_info_init (&info); | |
4018 | if (!gdbarch_update_p (info)) | |
4019 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4020 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4021 | } |
4022 | ||
0e6bdb31 OF |
4023 | static void |
4024 | set_cris_mode (char *ignore_args, int from_tty, | |
4025 | struct cmd_list_element *c) | |
4026 | { | |
4027 | struct gdbarch_info info; | |
4028 | ||
4029 | /* Update the current architecture, if needed. */ | |
4030 | gdbarch_info_init (&info); | |
4031 | if (!gdbarch_update_p (info)) | |
4032 | internal_error (__FILE__, __LINE__, | |
4033 | "cris_gdbarch_update: failed to update architecture."); | |
4034 | } | |
4035 | ||
29134980 | 4036 | static void |
a5f6c8f5 OF |
4037 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4038 | struct cmd_list_element *c) | |
29134980 OF |
4039 | { |
4040 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4041 | |
4042 | /* Update the current architecture, if needed. */ | |
4043 | gdbarch_info_init (&info); | |
4044 | if (!gdbarch_update_p (info)) | |
4045 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4046 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4047 | } |
4048 | ||
29134980 OF |
4049 | static struct gdbarch * |
4050 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4051 | { | |
4052 | struct gdbarch *gdbarch; | |
4053 | struct gdbarch_tdep *tdep; | |
4054 | int cris_version; | |
29134980 OF |
4055 | |
4056 | if (usr_cmd_cris_version_valid) | |
4057 | { | |
4058 | /* Trust the user's CRIS version setting. */ | |
4059 | cris_version = usr_cmd_cris_version; | |
4060 | } | |
c600d464 OF |
4061 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4062 | { | |
4063 | cris_version = 32; | |
4064 | } | |
29134980 OF |
4065 | else |
4066 | { | |
4067 | /* Assume it's CRIS version 10. */ | |
4068 | cris_version = 10; | |
4069 | } | |
4070 | ||
29134980 OF |
4071 | /* Make the current settings visible to the user. */ |
4072 | usr_cmd_cris_version = cris_version; | |
29134980 | 4073 | |
0e6bdb31 | 4074 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4075 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4076 | arches != NULL; | |
4077 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4078 | { | |
a5f6c8f5 OF |
4079 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4080 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4081 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4082 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4083 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4084 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4085 | return arches->gdbarch; |
4086 | } | |
4087 | ||
4088 | /* No matching architecture was found. Create a new one. */ | |
4089 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4090 | gdbarch = gdbarch_alloc (&info, tdep); | |
4091 | ||
a5f6c8f5 | 4092 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4093 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4094 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4095 | |
4096 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4097 | switch (info.byte_order) | |
4098 | { | |
778eb05e | 4099 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4100 | /* Ok. */ |
4101 | break; | |
4102 | ||
d7449b42 | 4103 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4104 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4105 | break; |
4106 | ||
4107 | default: | |
e2e0b3e5 | 4108 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4109 | } |
4110 | ||
b4206d25 | 4111 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4112 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4113 | cris_reg_struct_has_addr); | |
b5622e8d | 4114 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4115 | |
29134980 | 4116 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4117 | |
4118 | /* Length of ordinary registers used in push_word and a few other | |
4119 | places. register_size() is the real way to know how big a | |
4120 | register is. */ | |
a5f6c8f5 | 4121 | |
2e4b5889 OF |
4122 | set_gdbarch_double_bit (gdbarch, 64); |
4123 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
4124 | which means we have to set this explicitly. */ | |
c600d464 | 4125 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4126 | |
29134980 OF |
4127 | /* The total amount of space needed to store (in an array called registers) |
4128 | GDB's copy of the machine's register state. Note: We can not use | |
4129 | cris_register_size at this point, since it relies on current_gdbarch | |
4130 | being set. */ | |
4131 | switch (tdep->cris_version) | |
4132 | { | |
4133 | case 0: | |
4134 | case 1: | |
4135 | case 2: | |
4136 | case 3: | |
29134980 OF |
4137 | case 8: |
4138 | case 9: | |
a5f6c8f5 OF |
4139 | /* Old versions; not supported. */ |
4140 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4141 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4142 | break; |
4143 | ||
4144 | case 10: | |
4145 | case 11: | |
4146 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4147 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4148 | set_gdbarch_pc_regnum (gdbarch, 15); |
4149 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4150 | /* There are 32 registers (some of which may not be implemented). */ | |
4151 | set_gdbarch_num_regs (gdbarch, 32); | |
4152 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4153 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4154 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4155 | ||
4156 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4157 | break; | |
4158 | ||
4159 | case 32: | |
4160 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4161 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4162 | and pseudo-register PC (32 bits). */ | |
4163 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4164 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4165 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4166 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4167 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4168 | ||
4169 | set_gdbarch_cannot_store_register | |
4170 | (gdbarch, crisv32_cannot_store_register); | |
4171 | set_gdbarch_cannot_fetch_register | |
4172 | (gdbarch, crisv32_cannot_fetch_register); | |
4173 | ||
4174 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4175 | ||
4176 | set_gdbarch_single_step_through_delay | |
4177 | (gdbarch, crisv32_single_step_through_delay); | |
4178 | ||
29134980 OF |
4179 | break; |
4180 | ||
4181 | default: | |
c600d464 | 4182 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4183 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4184 | } |
4185 | ||
c600d464 OF |
4186 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4187 | have the same ABI). */ | |
2e4b5889 OF |
4188 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4189 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4190 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4191 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4192 | |
4193 | /* The stack grows downward. */ | |
4194 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4195 | ||
4196 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4197 | ||
2e4b5889 OF |
4198 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4199 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4200 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4201 | ||
a5f6c8f5 OF |
4202 | if (tdep->cris_dwarf2_cfi == 1) |
4203 | { | |
4204 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4205 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4206 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4207 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4208 | } | |
4209 | ||
0e6bdb31 OF |
4210 | if (tdep->cris_mode != cris_mode_guru) |
4211 | { | |
4212 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4213 | } | |
a5f6c8f5 | 4214 | |
2e4b5889 OF |
4215 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4216 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4217 | |
76a9d10f MK |
4218 | set_solib_svr4_fetch_link_map_offsets |
4219 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
dbbff683 | 4220 | |
36482093 AC |
4221 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4222 | disassembler, even when there is no BFD. Does something like | |
4223 | "gdb; target remote; disassmeble *0x123" work? */ | |
4224 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4225 | ||
29134980 OF |
4226 | return gdbarch; |
4227 | } |