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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
23 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
24 | Boston, MA 02110-1301, USA. */ | |
29134980 OF |
25 | |
26 | #include "defs.h" | |
27 | #include "frame.h" | |
2e4b5889 OF |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
30 | #include "trad-frame.h" | |
31 | #include "dwarf2-frame.h" | |
29134980 OF |
32 | #include "symtab.h" |
33 | #include "inferior.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "gdbcore.h" | |
36 | #include "gdbcmd.h" | |
37 | #include "target.h" | |
38 | #include "value.h" | |
39 | #include "opcode/cris.h" | |
40 | #include "arch-utils.h" | |
41 | #include "regcache.h" | |
36482093 | 42 | #include "gdb_assert.h" |
29134980 OF |
43 | |
44 | /* To get entry_point_address. */ | |
9ab9195f | 45 | #include "objfiles.h" |
29134980 | 46 | |
a5f6c8f5 | 47 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 48 | #include "solib-svr4.h" |
9bbe19fb | 49 | #include "gdb_string.h" |
a89aa300 | 50 | #include "dis-asm.h" |
dbbff683 | 51 | |
29134980 OF |
52 | enum cris_num_regs |
53 | { | |
54 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
55 | NUM_FREGS = 0, | |
56 | ||
57 | /* There are 16 general registers. */ | |
58 | NUM_GENREGS = 16, | |
59 | ||
60 | /* There are 16 special registers. */ | |
c600d464 OF |
61 | NUM_SPECREGS = 16, |
62 | ||
63 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
64 | ||
65 | /* CRISv32 has 16 support registers. */ | |
66 | NUM_SUPPREGS = 16 | |
29134980 OF |
67 | }; |
68 | ||
69 | /* Register numbers of various important registers. | |
2e4b5889 | 70 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
71 | STR_REGNUM Contains the address of structure return values. |
72 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
73 | ARG1_REGNUM Contains the first parameter to a function. | |
74 | ARG2_REGNUM Contains the second parameter to a function. | |
75 | ARG3_REGNUM Contains the third parameter to a function. | |
76 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
77 | SP_REGNUM Contains address of top of stack. | |
78 | PC_REGNUM Contains address of next instruction. | |
79 | SRP_REGNUM Subroutine return pointer register. | |
80 | BRP_REGNUM Breakpoint return pointer register. */ | |
81 | ||
29134980 OF |
82 | enum cris_regnums |
83 | { | |
84 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 85 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 86 | CRIS_FP_REGNUM = 8, |
c600d464 | 87 | /* ABI related registers. */ |
29134980 OF |
88 | STR_REGNUM = 9, |
89 | RET_REGNUM = 10, | |
90 | ARG1_REGNUM = 10, | |
91 | ARG2_REGNUM = 11, | |
92 | ARG3_REGNUM = 12, | |
93 | ARG4_REGNUM = 13, | |
94 | ||
c600d464 | 95 | /* Registers which happen to be common. */ |
29134980 | 96 | VR_REGNUM = 17, |
c600d464 OF |
97 | MOF_REGNUM = 23, |
98 | SRP_REGNUM = 27, | |
99 | ||
100 | /* CRISv10 et. al. specific registers. */ | |
101 | P0_REGNUM = 16, | |
29134980 OF |
102 | P4_REGNUM = 20, |
103 | CCR_REGNUM = 21, | |
29134980 OF |
104 | P8_REGNUM = 24, |
105 | IBR_REGNUM = 25, | |
106 | IRP_REGNUM = 26, | |
29134980 | 107 | BAR_REGNUM = 28, |
2a9ecef2 | 108 | DCCR_REGNUM = 29, |
29134980 | 109 | BRP_REGNUM = 30, |
c600d464 OF |
110 | USP_REGNUM = 31, |
111 | ||
112 | /* CRISv32 specific registers. */ | |
113 | ACR_REGNUM = 15, | |
114 | BZ_REGNUM = 16, | |
115 | PID_REGNUM = 18, | |
116 | SRS_REGNUM = 19, | |
117 | WZ_REGNUM = 20, | |
118 | EXS_REGNUM = 21, | |
119 | EDA_REGNUM = 22, | |
120 | DZ_REGNUM = 24, | |
121 | EBP_REGNUM = 25, | |
122 | ERP_REGNUM = 26, | |
123 | NRP_REGNUM = 28, | |
124 | CCS_REGNUM = 29, | |
125 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
126 | SPC_REGNUM = 31, | |
127 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
128 | ||
129 | S0_REGNUM = 33, | |
130 | S1_REGNUM = 34, | |
131 | S2_REGNUM = 35, | |
132 | S3_REGNUM = 36, | |
133 | S4_REGNUM = 37, | |
134 | S5_REGNUM = 38, | |
135 | S6_REGNUM = 39, | |
136 | S7_REGNUM = 40, | |
137 | S8_REGNUM = 41, | |
138 | S9_REGNUM = 42, | |
139 | S10_REGNUM = 43, | |
140 | S11_REGNUM = 44, | |
141 | S12_REGNUM = 45, | |
142 | S13_REGNUM = 46, | |
143 | S14_REGNUM = 47, | |
144 | S15_REGNUM = 48, | |
29134980 OF |
145 | }; |
146 | ||
147 | extern const struct cris_spec_reg cris_spec_regs[]; | |
148 | ||
149 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
150 | register names and sizes. */ |
151 | static int usr_cmd_cris_version; | |
29134980 OF |
152 | |
153 | /* Indicates whether to trust the above variable. */ | |
154 | static int usr_cmd_cris_version_valid = 0; | |
155 | ||
41922353 OF |
156 | static const char cris_mode_normal[] = "normal"; |
157 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
158 | static const char *cris_modes[] = { |
159 | cris_mode_normal, | |
160 | cris_mode_guru, | |
161 | 0 | |
162 | }; | |
163 | ||
164 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
165 | type of break instruction among other things. */ | |
166 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
167 | ||
a5f6c8f5 OF |
168 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
169 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 170 | |
29134980 OF |
171 | /* CRIS architecture specific information. */ |
172 | struct gdbarch_tdep | |
173 | { | |
0e6bdb31 OF |
174 | int cris_version; |
175 | const char *cris_mode; | |
a5f6c8f5 | 176 | int cris_dwarf2_cfi; |
29134980 OF |
177 | }; |
178 | ||
179 | /* Functions for accessing target dependent data. */ | |
180 | ||
181 | static int | |
182 | cris_version (void) | |
183 | { | |
184 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
185 | } | |
186 | ||
0e6bdb31 OF |
187 | static const char * |
188 | cris_mode (void) | |
189 | { | |
190 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
191 | } | |
192 | ||
a5f6c8f5 OF |
193 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
194 | ||
195 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
196 | #define SIGTRAMP_OFFSET0 0 | |
197 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
198 | #define SIGTRAMP_OFFSET1 4 | |
199 | ||
200 | static const unsigned short sigtramp_code[] = | |
201 | { | |
202 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
203 | SIGTRAMP_INSN1 /* break 13 */ | |
204 | }; | |
205 | ||
206 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
207 | ||
208 | /* Note: same length as normal sigtramp code. */ | |
209 | ||
210 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 211 | { |
a5f6c8f5 OF |
212 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
213 | SIGTRAMP_INSN1 /* break 13 */ | |
214 | }; | |
215 | ||
216 | /* If PC is in a sigtramp routine, return the address of the start of | |
217 | the routine. Otherwise, return 0. */ | |
218 | ||
219 | static CORE_ADDR | |
220 | cris_sigtramp_start (struct frame_info *next_frame) | |
221 | { | |
222 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 223 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
224 | |
225 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
226 | return 0; | |
227 | ||
e2a2a3e8 | 228 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 229 | { |
e2a2a3e8 | 230 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
231 | return 0; |
232 | ||
233 | pc -= SIGTRAMP_OFFSET1; | |
234 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
235 | return 0; | |
236 | } | |
237 | ||
238 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
239 | return 0; | |
240 | ||
241 | return pc; | |
242 | } | |
243 | ||
244 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
245 | the routine. Otherwise, return 0. */ | |
246 | ||
247 | static CORE_ADDR | |
248 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
249 | { | |
250 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 251 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
252 | |
253 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
254 | return 0; | |
255 | ||
e2a2a3e8 | 256 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 257 | { |
e2a2a3e8 | 258 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
259 | return 0; |
260 | ||
261 | pc -= SIGTRAMP_OFFSET1; | |
262 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
263 | return 0; | |
264 | } | |
265 | ||
266 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
267 | return 0; | |
268 | ||
269 | return pc; | |
270 | } | |
271 | ||
272 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
273 | routine, return the address of the associated sigcontext structure. */ | |
274 | ||
275 | static CORE_ADDR | |
276 | cris_sigcontext_addr (struct frame_info *next_frame) | |
277 | { | |
278 | CORE_ADDR pc; | |
279 | CORE_ADDR sp; | |
280 | char buf[4]; | |
281 | ||
282 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
283 | sp = extract_unsigned_integer (buf, 4); | |
284 | ||
285 | /* Look for normal sigtramp frame first. */ | |
286 | pc = cris_sigtramp_start (next_frame); | |
287 | if (pc) | |
288 | { | |
289 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
290 | struct sigcontext as its first member, meaning the SP points to | |
291 | it already. */ | |
292 | return sp; | |
293 | } | |
294 | ||
295 | pc = cris_rt_sigtramp_start (next_frame); | |
296 | if (pc) | |
297 | { | |
298 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
299 | a struct ucontext, which in turn contains a struct sigcontext. | |
300 | Magic digging: | |
301 | 4 + 4 + 128 to struct ucontext, then | |
302 | 4 + 4 + 12 to struct sigcontext. */ | |
303 | return (sp + 156); | |
304 | } | |
305 | ||
8a3fe4f8 | 306 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 307 | return 0; |
29134980 OF |
308 | } |
309 | ||
2e4b5889 | 310 | struct cris_unwind_cache |
29134980 | 311 | { |
2e4b5889 OF |
312 | /* The previous frame's inner most stack address. Used as this |
313 | frame ID's stack_addr. */ | |
314 | CORE_ADDR prev_sp; | |
315 | /* The frame's base, optionally used by the high-level debug info. */ | |
316 | CORE_ADDR base; | |
317 | int size; | |
318 | /* How far the SP and r8 (FP) have been offset from the start of | |
319 | the stack frame (as defined by the previous frame's stack | |
320 | pointer). */ | |
321 | LONGEST sp_offset; | |
322 | LONGEST r8_offset; | |
323 | int uses_frame; | |
324 | ||
325 | /* From old frame_extra_info struct. */ | |
29134980 OF |
326 | CORE_ADDR return_pc; |
327 | int leaf_function; | |
2e4b5889 OF |
328 | |
329 | /* Table indicating the location of each and every register. */ | |
330 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
331 | }; |
332 | ||
a5f6c8f5 OF |
333 | static struct cris_unwind_cache * |
334 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
335 | void **this_cache) | |
336 | { | |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
338 | struct cris_unwind_cache *info; | |
339 | CORE_ADDR pc; | |
340 | CORE_ADDR sp; | |
341 | CORE_ADDR addr; | |
342 | char buf[4]; | |
343 | int i; | |
344 | ||
345 | if ((*this_cache)) | |
346 | return (*this_cache); | |
347 | ||
348 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
349 | (*this_cache) = info; | |
350 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
351 | ||
352 | /* Zero all fields. */ | |
353 | info->prev_sp = 0; | |
354 | info->base = 0; | |
355 | info->size = 0; | |
356 | info->sp_offset = 0; | |
357 | info->r8_offset = 0; | |
358 | info->uses_frame = 0; | |
359 | info->return_pc = 0; | |
360 | info->leaf_function = 0; | |
361 | ||
362 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
363 | info->base = extract_unsigned_integer (buf, 4); | |
364 | ||
365 | addr = cris_sigcontext_addr (next_frame); | |
366 | ||
367 | /* Layout of the sigcontext struct: | |
368 | struct sigcontext { | |
369 | struct pt_regs regs; | |
370 | unsigned long oldmask; | |
371 | unsigned long usp; | |
372 | }; */ | |
373 | ||
c600d464 OF |
374 | if (tdep->cris_version == 10) |
375 | { | |
376 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
377 | struct pt_regs. */ | |
378 | for (i = 0; i <= 13; i++) | |
379 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
380 | ||
381 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
382 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
383 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
384 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
385 | it though since that will mean that the backtrace will show a PC | |
386 | different from what is shown when stopped. */ | |
387 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
388 | info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; | |
389 | info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); | |
390 | } | |
391 | else | |
392 | { | |
393 | /* CRISv32. */ | |
394 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
395 | struct pt_regs. */ | |
396 | for (i = 0; i <= 13; i++) | |
397 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
398 | ||
399 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
400 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
401 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
402 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
403 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
404 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
405 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
406 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
407 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
408 | ||
409 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
410 | be wrong at this point. This problem manifests itself in the | |
411 | sigaltstack.exp test case, which occasionally generates FAILs when | |
412 | the signal is received while in a delay slot. | |
413 | ||
414 | This could be solved by a couple of read_memory_unsigned_integer and a | |
415 | trad_frame_set_value. */ | |
416 | info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM]; | |
417 | ||
418 | info->saved_regs[SP_REGNUM].addr = addr + (25 * 4); | |
419 | } | |
a5f6c8f5 OF |
420 | |
421 | return info; | |
422 | } | |
423 | ||
424 | static void | |
425 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
426 | struct frame_id *this_id) | |
427 | { | |
428 | struct cris_unwind_cache *cache = | |
429 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
430 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
431 | } | |
432 | ||
433 | /* Forward declaration. */ | |
434 | ||
435 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
436 | void **this_prologue_cache, | |
437 | int regnum, int *optimizedp, | |
438 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 439 | int *realnump, gdb_byte *bufferp); |
a5f6c8f5 OF |
440 | static void |
441 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
442 | void **this_cache, | |
443 | int regnum, int *optimizedp, | |
444 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 445 | int *realnump, gdb_byte *valuep) |
a5f6c8f5 OF |
446 | { |
447 | /* Make sure we've initialized the cache. */ | |
448 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
449 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
450 | optimizedp, lvalp, addrp, realnump, valuep); | |
451 | } | |
452 | ||
453 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
454 | { | |
455 | SIGTRAMP_FRAME, | |
456 | cris_sigtramp_frame_this_id, | |
457 | cris_sigtramp_frame_prev_register | |
458 | }; | |
459 | ||
460 | static const struct frame_unwind * | |
461 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
462 | { | |
463 | if (cris_sigtramp_start (next_frame) | |
464 | || cris_rt_sigtramp_start (next_frame)) | |
465 | return &cris_sigtramp_frame_unwind; | |
466 | ||
467 | return NULL; | |
468 | } | |
469 | ||
c600d464 OF |
470 | int |
471 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
472 | struct frame_info *this_frame) | |
473 | { | |
474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
475 | ULONGEST erp; | |
476 | int ret = 0; | |
477 | char buf[4]; | |
478 | ||
0e6bdb31 OF |
479 | if (cris_mode () == cris_mode_guru) |
480 | { | |
481 | frame_unwind_register (this_frame, NRP_REGNUM, buf); | |
482 | } | |
483 | else | |
484 | { | |
485 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
486 | } | |
487 | ||
c600d464 OF |
488 | erp = extract_unsigned_integer (buf, 4); |
489 | ||
490 | if (erp & 0x1) | |
491 | { | |
492 | /* In delay slot - check if there's a breakpoint at the preceding | |
493 | instruction. */ | |
494 | if (breakpoint_here_p (erp & ~0x1)) | |
495 | ret = 1; | |
496 | } | |
497 | return ret; | |
498 | } | |
499 | ||
500 | /* Hardware watchpoint support. */ | |
501 | ||
502 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
503 | (any combination of read/write is fine). */ | |
504 | ||
505 | int | |
506 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
507 | { | |
508 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
509 | ||
510 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
511 | ||
512 | if (tdep->cris_version != 32) | |
513 | return 0; | |
514 | else | |
515 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
516 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
517 | || type == bp_hardware_watchpoint) && count <= 6) | |
518 | || (type == bp_hardware_breakpoint && count <= 1)); | |
519 | } | |
520 | ||
521 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
522 | which have no alignment or length restrictions. */ | |
523 | ||
524 | int | |
525 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
526 | { | |
527 | return 1; | |
528 | } | |
529 | ||
530 | /* If the inferior has some watchpoint that triggered, return the | |
531 | address associated with that watchpoint. Otherwise, return | |
532 | zero. */ | |
533 | ||
534 | CORE_ADDR | |
535 | cris_stopped_data_address (void) | |
536 | { | |
537 | CORE_ADDR eda; | |
538 | eda = read_register (EDA_REGNUM); | |
539 | return eda; | |
540 | } | |
541 | ||
29134980 | 542 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 543 | |
29134980 OF |
544 | typedef |
545 | struct instruction_environment | |
546 | { | |
547 | unsigned long reg[NUM_GENREGS]; | |
548 | unsigned long preg[NUM_SPECREGS]; | |
549 | unsigned long branch_break_address; | |
550 | unsigned long delay_slot_pc; | |
551 | unsigned long prefix_value; | |
552 | int branch_found; | |
553 | int prefix_found; | |
554 | int invalid; | |
555 | int slot_needed; | |
556 | int delay_slot_pc_active; | |
557 | int xflag_found; | |
558 | int disable_interrupt; | |
559 | } inst_env_type; | |
560 | ||
29134980 OF |
561 | /* Machine-dependencies in CRIS for opcodes. */ |
562 | ||
563 | /* Instruction sizes. */ | |
564 | enum cris_instruction_sizes | |
565 | { | |
566 | INST_BYTE_SIZE = 0, | |
567 | INST_WORD_SIZE = 1, | |
568 | INST_DWORD_SIZE = 2 | |
569 | }; | |
570 | ||
571 | /* Addressing modes. */ | |
572 | enum cris_addressing_modes | |
573 | { | |
574 | REGISTER_MODE = 1, | |
575 | INDIRECT_MODE = 2, | |
576 | AUTOINC_MODE = 3 | |
577 | }; | |
578 | ||
579 | /* Prefix addressing modes. */ | |
580 | enum cris_prefix_addressing_modes | |
581 | { | |
582 | PREFIX_INDEX_MODE = 2, | |
583 | PREFIX_ASSIGN_MODE = 3, | |
584 | ||
585 | /* Handle immediate byte offset addressing mode prefix format. */ | |
586 | PREFIX_OFFSET_MODE = 2 | |
587 | }; | |
588 | ||
589 | /* Masks for opcodes. */ | |
590 | enum cris_opcode_masks | |
591 | { | |
592 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
593 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
594 | SIGNED_BYTE_MASK = 0x80, | |
595 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
596 | SIGNED_WORD_MASK = 0x8000, | |
597 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
598 | SIGNED_DWORD_MASK = 0x80000000, | |
599 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
600 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
601 | }; | |
602 | ||
603 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
604 | Bit 15 - 12 Operand2 | |
605 | 11 - 10 Mode | |
606 | 9 - 6 Opcode | |
607 | 5 - 4 Size | |
608 | 3 - 0 Operand1 */ | |
609 | ||
610 | static int | |
611 | cris_get_operand2 (unsigned short insn) | |
612 | { | |
613 | return ((insn & 0xF000) >> 12); | |
614 | } | |
615 | ||
616 | static int | |
617 | cris_get_mode (unsigned short insn) | |
618 | { | |
619 | return ((insn & 0x0C00) >> 10); | |
620 | } | |
621 | ||
622 | static int | |
623 | cris_get_opcode (unsigned short insn) | |
624 | { | |
625 | return ((insn & 0x03C0) >> 6); | |
626 | } | |
627 | ||
628 | static int | |
629 | cris_get_size (unsigned short insn) | |
630 | { | |
631 | return ((insn & 0x0030) >> 4); | |
632 | } | |
633 | ||
634 | static int | |
635 | cris_get_operand1 (unsigned short insn) | |
636 | { | |
637 | return (insn & 0x000F); | |
638 | } | |
639 | ||
640 | /* Additional functions in order to handle opcodes. */ | |
641 | ||
29134980 OF |
642 | static int |
643 | cris_get_quick_value (unsigned short insn) | |
644 | { | |
645 | return (insn & 0x003F); | |
646 | } | |
647 | ||
648 | static int | |
649 | cris_get_bdap_quick_offset (unsigned short insn) | |
650 | { | |
651 | return (insn & 0x00FF); | |
652 | } | |
653 | ||
654 | static int | |
655 | cris_get_branch_short_offset (unsigned short insn) | |
656 | { | |
657 | return (insn & 0x00FF); | |
658 | } | |
659 | ||
660 | static int | |
661 | cris_get_asr_shift_steps (unsigned long value) | |
662 | { | |
663 | return (value & 0x3F); | |
664 | } | |
665 | ||
29134980 OF |
666 | static int |
667 | cris_get_clear_size (unsigned short insn) | |
668 | { | |
669 | return ((insn) & 0xC000); | |
670 | } | |
671 | ||
672 | static int | |
673 | cris_is_signed_extend_bit_on (unsigned short insn) | |
674 | { | |
675 | return (((insn) & 0x20) == 0x20); | |
676 | } | |
677 | ||
678 | static int | |
679 | cris_is_xflag_bit_on (unsigned short insn) | |
680 | { | |
681 | return (((insn) & 0x1000) == 0x1000); | |
682 | } | |
683 | ||
684 | static void | |
685 | cris_set_size_to_dword (unsigned short *insn) | |
686 | { | |
687 | *insn &= 0xFFCF; | |
688 | *insn |= 0x20; | |
689 | } | |
690 | ||
8535cb38 | 691 | static signed char |
29134980 OF |
692 | cris_get_signed_offset (unsigned short insn) |
693 | { | |
8535cb38 | 694 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
695 | } |
696 | ||
697 | /* Calls an op function given the op-type, working on the insn and the | |
698 | inst_env. */ | |
699 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
700 | ||
29134980 OF |
701 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
702 | struct gdbarch_list *); | |
703 | ||
29134980 OF |
704 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
705 | ||
a5f6c8f5 OF |
706 | static void set_cris_version (char *ignore_args, int from_tty, |
707 | struct cmd_list_element *c); | |
29134980 | 708 | |
0e6bdb31 OF |
709 | static void set_cris_mode (char *ignore_args, int from_tty, |
710 | struct cmd_list_element *c); | |
711 | ||
a5f6c8f5 OF |
712 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
713 | struct cmd_list_element *c); | |
29134980 | 714 | |
2e4b5889 OF |
715 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
716 | struct frame_info *next_frame, | |
717 | struct cris_unwind_cache *info); | |
718 | ||
5114e29d OF |
719 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
720 | struct frame_info *next_frame, | |
721 | struct cris_unwind_cache *info); | |
722 | ||
2e4b5889 OF |
723 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
724 | struct frame_info *next_frame); | |
725 | ||
726 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
727 | struct frame_info *next_frame); | |
728 | ||
729 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
730 | order. The below implements a FILO (stack) to do this. |
731 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
732 | |
733 | struct stack_item | |
734 | { | |
735 | int len; | |
736 | struct stack_item *prev; | |
737 | void *data; | |
738 | }; | |
739 | ||
740 | static struct stack_item * | |
741 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
742 | { | |
743 | struct stack_item *si; | |
744 | si = xmalloc (sizeof (struct stack_item)); | |
745 | si->data = xmalloc (len); | |
746 | si->len = len; | |
747 | si->prev = prev; | |
748 | memcpy (si->data, contents, len); | |
749 | return si; | |
750 | } | |
751 | ||
752 | static struct stack_item * | |
753 | pop_stack_item (struct stack_item *si) | |
754 | { | |
755 | struct stack_item *dead = si; | |
756 | si = si->prev; | |
757 | xfree (dead->data); | |
758 | xfree (dead); | |
759 | return si; | |
760 | } | |
761 | ||
762 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
763 | the saved registers of frame described by FRAME_INFO. This | |
764 | includes special registers such as pc and fp saved in special ways | |
765 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 766 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
767 | |
768 | struct cris_unwind_cache * | |
769 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
770 | void **this_prologue_cache) | |
771 | { | |
772 | CORE_ADDR pc; | |
773 | struct cris_unwind_cache *info; | |
774 | int i; | |
775 | ||
776 | if ((*this_prologue_cache)) | |
777 | return (*this_prologue_cache); | |
778 | ||
779 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
780 | (*this_prologue_cache) = info; | |
781 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
782 | ||
783 | /* Zero all fields. */ | |
784 | info->prev_sp = 0; | |
785 | info->base = 0; | |
786 | info->size = 0; | |
787 | info->sp_offset = 0; | |
788 | info->r8_offset = 0; | |
789 | info->uses_frame = 0; | |
790 | info->return_pc = 0; | |
791 | info->leaf_function = 0; | |
792 | ||
793 | /* Prologue analysis does the rest... */ | |
5114e29d | 794 | if (cris_version () == 32) |
93d42b30 DJ |
795 | crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
796 | next_frame, info); | |
5114e29d | 797 | else |
93d42b30 DJ |
798 | cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
799 | next_frame, info); | |
2e4b5889 OF |
800 | |
801 | return info; | |
802 | } | |
803 | ||
804 | /* Given a GDB frame, determine the address of the calling function's | |
805 | frame. This will be used to create a new GDB frame struct. */ | |
806 | ||
807 | static void | |
808 | cris_frame_this_id (struct frame_info *next_frame, | |
809 | void **this_prologue_cache, | |
810 | struct frame_id *this_id) | |
811 | { | |
812 | struct cris_unwind_cache *info | |
813 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
814 | CORE_ADDR base; | |
815 | CORE_ADDR func; | |
816 | struct frame_id id; | |
817 | ||
818 | /* The FUNC is easy. */ | |
93d42b30 | 819 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
2e4b5889 OF |
820 | |
821 | /* Hopefully the prologue analysis either correctly determined the | |
822 | frame's base (which is the SP from the previous frame), or set | |
823 | that base to "NULL". */ | |
824 | base = info->prev_sp; | |
825 | if (base == 0) | |
826 | return; | |
827 | ||
828 | id = frame_id_build (base, func); | |
829 | ||
830 | (*this_id) = id; | |
831 | } | |
832 | ||
833 | static void | |
834 | cris_frame_prev_register (struct frame_info *next_frame, | |
835 | void **this_prologue_cache, | |
836 | int regnum, int *optimizedp, | |
837 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 838 | int *realnump, gdb_byte *bufferp) |
2e4b5889 OF |
839 | { |
840 | struct cris_unwind_cache *info | |
841 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
842 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
843 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
844 | } |
845 | ||
846 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
847 | dummy frame. The frame ID's base needs to match the TOS value | |
848 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
849 | breakpoint. */ | |
850 | ||
851 | static struct frame_id | |
852 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
853 | { | |
854 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
855 | frame_pc_unwind (next_frame)); | |
856 | } | |
857 | ||
858 | static CORE_ADDR | |
859 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
860 | { | |
861 | /* Align to the size of an instruction (so that they can safely be | |
862 | pushed onto the stack). */ | |
863 | return sp & ~3; | |
864 | } | |
865 | ||
866 | static CORE_ADDR | |
867 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
868 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
869 | struct value **args, int nargs, | |
870 | struct type *value_type, | |
871 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
872 | { | |
873 | /* Allocate space sufficient for a breakpoint. */ | |
874 | sp = (sp - 4) & ~3; | |
875 | /* Store the address of that breakpoint */ | |
876 | *bp_addr = sp; | |
877 | /* CRIS always starts the call at the callee's entry point. */ | |
878 | *real_pc = funaddr; | |
879 | return sp; | |
880 | } | |
881 | ||
882 | static CORE_ADDR | |
7d9b040b | 883 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
884 | struct regcache *regcache, CORE_ADDR bp_addr, |
885 | int nargs, struct value **args, CORE_ADDR sp, | |
886 | int struct_return, CORE_ADDR struct_addr) | |
887 | { | |
888 | int stack_alloc; | |
889 | int stack_offset; | |
890 | int argreg; | |
891 | int argnum; | |
892 | ||
893 | CORE_ADDR regval; | |
894 | ||
895 | /* The function's arguments and memory allocated by gdb for the arguments to | |
896 | point at reside in separate areas on the stack. | |
897 | Both frame pointers grow toward higher addresses. */ | |
898 | CORE_ADDR fp_arg; | |
899 | CORE_ADDR fp_mem; | |
900 | ||
901 | struct stack_item *si = NULL; | |
902 | ||
a5f6c8f5 | 903 | /* Push the return address. */ |
2e4b5889 OF |
904 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
905 | ||
906 | /* Are we returning a value using a structure return or a normal value | |
907 | return? struct_addr is the address of the reserved space for the return | |
908 | structure to be written on the stack. */ | |
909 | if (struct_return) | |
910 | { | |
911 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
912 | } | |
913 | ||
914 | /* Now load as many as possible of the first arguments into registers, | |
915 | and push the rest onto the stack. */ | |
916 | argreg = ARG1_REGNUM; | |
917 | stack_offset = 0; | |
918 | ||
919 | for (argnum = 0; argnum < nargs; argnum++) | |
920 | { | |
921 | int len; | |
922 | char *val; | |
923 | int reg_demand; | |
924 | int i; | |
925 | ||
4991999e | 926 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 927 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
928 | |
929 | /* How may registers worth of storage do we need for this argument? */ | |
930 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
931 | ||
932 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
933 | { | |
934 | /* Data passed by value. Fits in available register(s). */ | |
935 | for (i = 0; i < reg_demand; i++) | |
936 | { | |
937 | regcache_cooked_write_unsigned (regcache, argreg, | |
938 | *(unsigned long *) val); | |
939 | argreg++; | |
940 | val += 4; | |
941 | } | |
942 | } | |
943 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
944 | { | |
945 | /* Data passed by value. Does not fit in available register(s). | |
946 | Use the register(s) first, then the stack. */ | |
947 | for (i = 0; i < reg_demand; i++) | |
948 | { | |
949 | if (argreg <= ARG4_REGNUM) | |
950 | { | |
951 | regcache_cooked_write_unsigned (regcache, argreg, | |
952 | *(unsigned long *) val); | |
953 | argreg++; | |
954 | val += 4; | |
955 | } | |
956 | else | |
957 | { | |
958 | /* Push item for later so that pushed arguments | |
959 | come in the right order. */ | |
960 | si = push_stack_item (si, val, 4); | |
961 | val += 4; | |
962 | } | |
963 | } | |
964 | } | |
965 | else if (len > (2 * 4)) | |
966 | { | |
967 | /* FIXME */ | |
e2e0b3e5 | 968 | internal_error (__FILE__, __LINE__, _("We don't do this")); |
2e4b5889 OF |
969 | } |
970 | else | |
971 | { | |
972 | /* Data passed by value. No available registers. Put it on | |
973 | the stack. */ | |
974 | si = push_stack_item (si, val, len); | |
975 | } | |
976 | } | |
977 | ||
978 | while (si) | |
979 | { | |
980 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
981 | the function prologue. */ | |
982 | sp = (sp - si->len) & ~3; | |
983 | write_memory (sp, si->data, si->len); | |
984 | si = pop_stack_item (si); | |
985 | } | |
986 | ||
987 | /* Finally, update the SP register. */ | |
988 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
989 | ||
990 | return sp; | |
991 | } | |
992 | ||
e2a2a3e8 OF |
993 | static const struct frame_unwind cris_frame_unwind = |
994 | { | |
2e4b5889 OF |
995 | NORMAL_FRAME, |
996 | cris_frame_this_id, | |
997 | cris_frame_prev_register | |
998 | }; | |
999 | ||
1000 | const struct frame_unwind * | |
1001 | cris_frame_sniffer (struct frame_info *next_frame) | |
1002 | { | |
1003 | return &cris_frame_unwind; | |
1004 | } | |
1005 | ||
1006 | static CORE_ADDR | |
1007 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1008 | { | |
1009 | struct cris_unwind_cache *info | |
1010 | = cris_frame_unwind_cache (next_frame, this_cache); | |
1011 | return info->base; | |
1012 | } | |
1013 | ||
e2a2a3e8 OF |
1014 | static const struct frame_base cris_frame_base = |
1015 | { | |
2e4b5889 OF |
1016 | &cris_frame_unwind, |
1017 | cris_frame_base_address, | |
1018 | cris_frame_base_address, | |
1019 | cris_frame_base_address | |
1020 | }; | |
1021 | ||
29134980 OF |
1022 | /* Frames information. The definition of the struct frame_info is |
1023 | ||
1024 | CORE_ADDR frame | |
1025 | CORE_ADDR pc | |
5a203e44 | 1026 | enum frame_type type; |
29134980 OF |
1027 | CORE_ADDR return_pc |
1028 | int leaf_function | |
1029 | ||
1030 | If the compilation option -fno-omit-frame-pointer is present the | |
1031 | variable frame will be set to the content of R8 which is the frame | |
1032 | pointer register. | |
1033 | ||
1034 | The variable pc contains the address where execution is performed | |
1035 | in the present frame. The innermost frame contains the current content | |
1036 | of the register PC. All other frames contain the content of the | |
1037 | register PC in the next frame. | |
1038 | ||
5a203e44 AC |
1039 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1040 | (associated with a signal handler), dummy (associated with a dummy | |
1041 | frame). | |
29134980 OF |
1042 | |
1043 | The variable return_pc contains the address where execution should be | |
1044 | resumed when the present frame has finished, the return address. | |
1045 | ||
1046 | The variable leaf_function is 1 if the return address is in the register | |
1047 | SRP, and 0 if it is on the stack. | |
1048 | ||
1049 | Prologue instructions C-code. | |
1050 | The prologue may consist of (-fno-omit-frame-pointer) | |
1051 | 1) 2) | |
1052 | push srp | |
1053 | push r8 push r8 | |
1054 | move.d sp,r8 move.d sp,r8 | |
1055 | subq X,sp subq X,sp | |
1056 | movem rY,[sp] movem rY,[sp] | |
1057 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1058 | ||
1059 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1060 | ||
1061 | Note that this assumption is extremely brittle, and will break at the | |
1062 | slightest change in GCC's prologue. | |
1063 | ||
1064 | If local variables are declared or register contents are saved on stack | |
1065 | the subq-instruction will be present with X as the number of bytes | |
1066 | needed for storage. The reshuffle with respect to r8 may be performed | |
1067 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1068 | The offset U should be representable by a signed 8-bit value in all cases. | |
1069 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1070 | by another word containing the instruction. | |
1071 | ||
1072 | Degenerate cases: | |
1073 | 3) | |
1074 | push r8 | |
1075 | move.d sp,r8 | |
1076 | move.d r8,sp | |
1077 | pop r8 | |
1078 | ||
1079 | Prologue instructions C++-code. | |
1080 | Case 1) and 2) in the C-code may be followed by | |
1081 | ||
1082 | move.d r10,rS ; this | |
1083 | move.d r11,rT ; P1 | |
1084 | move.d r12,rU ; P2 | |
1085 | move.d r13,rV ; P3 | |
1086 | move.S [r8+U],rZ ; P4 | |
1087 | ||
1088 | if any of the call parameters are stored. The host expects these | |
1089 | instructions to be executed in order to get the call parameters right. */ | |
1090 | ||
1091 | /* Examine the prologue of a function. The variable ip is the address of | |
1092 | the first instruction of the prologue. The variable limit is the address | |
1093 | of the first instruction after the prologue. The variable fi contains the | |
1094 | information in struct frame_info. The variable frameless_p controls whether | |
1095 | the entire prologue is examined (0) or just enough instructions to | |
1096 | determine that it is a prologue (1). */ | |
1097 | ||
a78f21af | 1098 | static CORE_ADDR |
2e4b5889 OF |
1099 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1100 | struct cris_unwind_cache *info) | |
29134980 OF |
1101 | { |
1102 | /* Present instruction. */ | |
1103 | unsigned short insn; | |
1104 | ||
1105 | /* Next instruction, lookahead. */ | |
1106 | unsigned short insn_next; | |
1107 | int regno; | |
1108 | ||
1109 | /* Is there a push fp? */ | |
1110 | int have_fp; | |
1111 | ||
1112 | /* Number of byte on stack used for local variables and movem. */ | |
1113 | int val; | |
1114 | ||
1115 | /* Highest register number in a movem. */ | |
1116 | int regsave; | |
1117 | ||
1118 | /* move.d r<source_register>,rS */ | |
1119 | short source_register; | |
1120 | ||
2e4b5889 OF |
1121 | /* Scan limit. */ |
1122 | int limit; | |
29134980 | 1123 | |
2e4b5889 OF |
1124 | /* This frame is with respect to a leaf until a push srp is found. */ |
1125 | if (info) | |
1126 | { | |
1127 | info->leaf_function = 1; | |
1128 | } | |
29134980 OF |
1129 | |
1130 | /* Assume nothing on stack. */ | |
1131 | val = 0; | |
1132 | regsave = -1; | |
1133 | ||
2e4b5889 OF |
1134 | /* If we were called without a next_frame, that means we were called |
1135 | from cris_skip_prologue which already tried to find the end of the | |
1136 | prologue through the symbol information. 64 instructions past current | |
1137 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1138 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1139 | |
29134980 | 1140 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1141 | while (pc > 0 && pc < limit) |
29134980 | 1142 | { |
2e4b5889 OF |
1143 | insn = read_memory_unsigned_integer (pc, 2); |
1144 | pc += 2; | |
29134980 OF |
1145 | if (insn == 0xE1FC) |
1146 | { | |
1147 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1148 | insn_next = read_memory_unsigned_integer (pc, 2); |
1149 | pc += 2; | |
29134980 | 1150 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1151 | if (info) |
1152 | { | |
1153 | info->sp_offset += 4; | |
1154 | } | |
dbbff683 OF |
1155 | /* This check, meant to recognize srp, used to be regno == |
1156 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1157 | if (insn_next == 0xBE7E) | |
29134980 | 1158 | { |
2e4b5889 OF |
1159 | if (info) |
1160 | { | |
1161 | info->leaf_function = 0; | |
1162 | } | |
29134980 | 1163 | } |
b4206d25 OF |
1164 | else if (insn_next == 0x8FEE) |
1165 | { | |
1166 | /* push $r8 */ | |
1167 | if (info) | |
1168 | { | |
1169 | info->r8_offset = info->sp_offset; | |
1170 | } | |
1171 | } | |
29134980 OF |
1172 | } |
1173 | else if (insn == 0x866E) | |
1174 | { | |
1175 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1176 | if (info) |
1177 | { | |
1178 | info->uses_frame = 1; | |
2e4b5889 | 1179 | } |
29134980 OF |
1180 | continue; |
1181 | } | |
1182 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1183 | && cris_get_mode (insn) == 0x0000 | |
1184 | && cris_get_opcode (insn) == 0x000A) | |
1185 | { | |
1186 | /* subq <val>,sp */ | |
2e4b5889 OF |
1187 | if (info) |
1188 | { | |
1189 | info->sp_offset += cris_get_quick_value (insn); | |
1190 | } | |
29134980 OF |
1191 | } |
1192 | else if (cris_get_mode (insn) == 0x0002 | |
1193 | && cris_get_opcode (insn) == 0x000F | |
1194 | && cris_get_size (insn) == 0x0003 | |
1195 | && cris_get_operand1 (insn) == SP_REGNUM) | |
1196 | { | |
1197 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1198 | regsave = cris_get_operand2 (insn); |
1199 | } | |
1200 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1201 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1202 | && (cris_get_signed_offset (insn) < 0)) | |
1203 | { | |
1204 | /* Immediate byte offset addressing prefix word with sp as base | |
1205 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1206 | is between 64 and 128. | |
1207 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1208 | if (info) |
1209 | { | |
1210 | info->sp_offset += -cris_get_signed_offset (insn); | |
1211 | } | |
1212 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1213 | pc += 2; | |
29134980 OF |
1214 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1215 | && cris_get_opcode (insn_next) == 0x000F | |
1216 | && cris_get_size (insn_next) == 0x0003 | |
1217 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
1218 | { | |
29134980 OF |
1219 | regsave = cris_get_operand2 (insn_next); |
1220 | } | |
1221 | else | |
1222 | { | |
1223 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1224 | pc -= 4; |
29134980 OF |
1225 | break; |
1226 | } | |
1227 | } | |
1228 | else if (cris_get_mode (insn) == 0x0001 | |
1229 | && cris_get_opcode (insn) == 0x0009 | |
1230 | && cris_get_size (insn) == 0x0002) | |
1231 | { | |
1232 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1233 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1234 | |
1235 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1236 | like (this example taken from relocate_doit): | |
1237 | move.d $pc,$r0 | |
1238 | sub.d 0xfffef426,$r0 | |
1239 | which isn't covered by the source_register check below. Question | |
1240 | is whether to add a check for this combo, or make better use of | |
1241 | the limit variable instead. */ | |
29134980 OF |
1242 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1243 | { | |
1244 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1245 | pc -= 2; |
29134980 OF |
1246 | break; |
1247 | } | |
1248 | } | |
2e4b5889 | 1249 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1250 | /* The size is a fixed-size. */ |
1251 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1252 | /* A negative offset. */ | |
1253 | && (cris_get_signed_offset (insn) < 0)) | |
1254 | { | |
1255 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1256 | insn_next = read_memory_unsigned_integer (pc, 2); |
1257 | pc += 2; | |
29134980 OF |
1258 | regno = cris_get_operand2 (insn_next); |
1259 | if ((regno >= 0 && regno < SP_REGNUM) | |
1260 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1261 | && cris_get_opcode (insn_next) == 0x000F) | |
1262 | { | |
1263 | /* move.S rZ,[r8-U] */ | |
1264 | continue; | |
1265 | } | |
1266 | else | |
1267 | { | |
1268 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1269 | pc -= 4; |
29134980 OF |
1270 | break; |
1271 | } | |
1272 | } | |
2e4b5889 | 1273 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1274 | /* The size is a fixed-size. */ |
1275 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1276 | /* A positive offset. */ | |
1277 | && (cris_get_signed_offset (insn) > 0)) | |
1278 | { | |
1279 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1280 | insn_next = read_memory_unsigned_integer (pc, 2); |
1281 | pc += 2; | |
29134980 OF |
1282 | regno = cris_get_operand2 (insn_next); |
1283 | if ((regno >= 0 && regno < SP_REGNUM) | |
1284 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1285 | && cris_get_opcode (insn_next) == 0x0009 | |
1286 | && cris_get_operand1 (insn_next) == regno) | |
1287 | { | |
1288 | /* move.S [r8+U],rZ */ | |
1289 | continue; | |
1290 | } | |
1291 | else | |
1292 | { | |
1293 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1294 | pc -= 4; |
29134980 OF |
1295 | break; |
1296 | } | |
1297 | } | |
1298 | else | |
1299 | { | |
1300 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1301 | pc -= 2; |
29134980 OF |
1302 | break; |
1303 | } | |
1304 | } | |
29134980 | 1305 | |
2e4b5889 OF |
1306 | /* We only want to know the end of the prologue when next_frame and info |
1307 | are NULL (called from cris_skip_prologue i.e.). */ | |
1308 | if (next_frame == NULL && info == NULL) | |
1309 | { | |
1310 | return pc; | |
1311 | } | |
29134980 | 1312 | |
2e4b5889 OF |
1313 | info->size = info->sp_offset; |
1314 | ||
1315 | /* Compute the previous frame's stack pointer (which is also the | |
1316 | frame's ID's stack address), and this frame's base pointer. */ | |
1317 | if (info->uses_frame) | |
29134980 | 1318 | { |
2e4b5889 OF |
1319 | ULONGEST this_base; |
1320 | /* The SP was moved to the FP. This indicates that a new frame | |
1321 | was created. Get THIS frame's FP value by unwinding it from | |
1322 | the next frame. */ | |
1323 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1324 | &this_base); | |
1325 | info->base = this_base; | |
b4206d25 OF |
1326 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1327 | ||
2e4b5889 OF |
1328 | /* The FP points at the last saved register. Adjust the FP back |
1329 | to before the first saved register giving the SP. */ | |
1330 | info->prev_sp = info->base + info->r8_offset; | |
1331 | } | |
1332 | else | |
1333 | { | |
1334 | ULONGEST this_base; | |
1335 | /* Assume that the FP is this frame's SP but with that pushed | |
1336 | stack space added back. */ | |
1337 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1338 | info->base = this_base; | |
1339 | info->prev_sp = info->base + info->size; | |
1340 | } | |
29134980 | 1341 | |
2e4b5889 OF |
1342 | /* Calculate the addresses for the saved registers on the stack. */ |
1343 | /* FIXME: The address calculation should really be done on the fly while | |
1344 | we're analyzing the prologue (we only hold one regsave value as it is | |
1345 | now). */ | |
1346 | val = info->sp_offset; | |
1347 | ||
1348 | for (regno = regsave; regno >= 0; regno--) | |
1349 | { | |
1350 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1351 | val -= 4; | |
1352 | } | |
1353 | ||
1354 | /* The previous frame's SP needed to be computed. Save the computed | |
1355 | value. */ | |
1356 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
1357 | ||
1358 | if (!info->leaf_function) | |
1359 | { | |
b4206d25 OF |
1360 | /* SRP saved on the stack. But where? */ |
1361 | if (info->r8_offset == 0) | |
1362 | { | |
1363 | /* R8 not pushed yet. */ | |
1364 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1365 | } | |
1366 | else | |
1367 | { | |
1368 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1369 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1370 | } | |
29134980 | 1371 | } |
2e4b5889 OF |
1372 | |
1373 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1374 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1375 | ||
1376 | return pc; | |
29134980 OF |
1377 | } |
1378 | ||
5114e29d OF |
1379 | static CORE_ADDR |
1380 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, | |
1381 | struct cris_unwind_cache *info) | |
1382 | { | |
1383 | ULONGEST this_base; | |
1384 | ||
1385 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1386 | meant to be a full-fledged prologue scanner. It is only needed for | |
1387 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1388 | ||
1389 | * PLT stubs (library calls) | |
1390 | * call dummys | |
1391 | * signal trampolines | |
1392 | ||
1393 | For those cases, it is assumed that there is no actual prologue; that | |
1394 | the stack pointer is not adjusted, and (as a consequence) the return | |
1395 | address is not pushed onto the stack. */ | |
1396 | ||
1397 | /* We only want to know the end of the prologue when next_frame and info | |
1398 | are NULL (called from cris_skip_prologue i.e.). */ | |
1399 | if (next_frame == NULL && info == NULL) | |
1400 | { | |
1401 | return pc; | |
1402 | } | |
1403 | ||
1404 | /* The SP is assumed to be unaltered. */ | |
1405 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1406 | info->base = this_base; | |
1407 | info->prev_sp = this_base; | |
1408 | ||
1409 | /* The PC is assumed to be found in SRP. */ | |
1410 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1411 | ||
1412 | return pc; | |
1413 | } | |
1414 | ||
29134980 OF |
1415 | /* Advance pc beyond any function entry prologue instructions at pc |
1416 | to reach some "real" code. */ | |
1417 | ||
29134980 OF |
1418 | /* Given a PC value corresponding to the start of a function, return the PC |
1419 | of the first instruction after the function prologue. */ | |
1420 | ||
a78f21af | 1421 | static CORE_ADDR |
2e4b5889 | 1422 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1423 | { |
2e4b5889 OF |
1424 | CORE_ADDR func_addr, func_end; |
1425 | struct symtab_and_line sal; | |
29134980 OF |
1426 | CORE_ADDR pc_after_prologue; |
1427 | ||
2e4b5889 OF |
1428 | /* If we have line debugging information, then the end of the prologue |
1429 | should the first assembly instruction of the first source line. */ | |
1430 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1431 | { | |
1432 | sal = find_pc_line (func_addr, 0); | |
1433 | if (sal.end > 0 && sal.end < func_end) | |
1434 | return sal.end; | |
1435 | } | |
29134980 | 1436 | |
5114e29d OF |
1437 | if (cris_version () == 32) |
1438 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); | |
1439 | else | |
1440 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1441 | ||
29134980 OF |
1442 | return pc_after_prologue; |
1443 | } | |
1444 | ||
2e4b5889 OF |
1445 | static CORE_ADDR |
1446 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1447 | { | |
1448 | ULONGEST pc; | |
1449 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1450 | return pc; | |
1451 | } | |
1452 | ||
1453 | static CORE_ADDR | |
1454 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1455 | { | |
1456 | ULONGEST sp; | |
1457 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1458 | return sp; | |
1459 | } | |
1460 | ||
29134980 OF |
1461 | /* Use the program counter to determine the contents and size of a breakpoint |
1462 | instruction. It returns a pointer to a string of bytes that encode a | |
1463 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1464 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1465 | the breakpoint should be inserted. */ | |
1466 | ||
a78f21af | 1467 | static const unsigned char * |
29134980 OF |
1468 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1469 | { | |
0e6bdb31 OF |
1470 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1471 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1472 | *lenptr = 2; |
1473 | ||
0e6bdb31 OF |
1474 | if (cris_mode () == cris_mode_guru) |
1475 | return break15_insn; | |
1476 | else | |
1477 | return break8_insn; | |
29134980 OF |
1478 | } |
1479 | ||
29134980 OF |
1480 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1481 | 0 otherwise. */ | |
1482 | ||
a78f21af | 1483 | static int |
29134980 OF |
1484 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1485 | { | |
1486 | int version = cris_version (); | |
1487 | ||
1488 | switch (spec_reg.applicable_version) | |
1489 | { | |
1490 | case cris_ver_version_all: | |
1491 | return 1; | |
1492 | case cris_ver_warning: | |
1493 | /* Indeterminate/obsolete. */ | |
1494 | return 0; | |
29134980 OF |
1495 | case cris_ver_v0_3: |
1496 | return (version >= 0 && version <= 3); | |
1497 | case cris_ver_v3p: | |
1498 | return (version >= 3); | |
1499 | case cris_ver_v8: | |
1500 | return (version == 8 || version == 9); | |
1501 | case cris_ver_v8p: | |
1502 | return (version >= 8); | |
c600d464 OF |
1503 | case cris_ver_v0_10: |
1504 | return (version >= 0 && version <= 10); | |
1505 | case cris_ver_v3_10: | |
1506 | return (version >= 3 && version <= 10); | |
1507 | case cris_ver_v8_10: | |
1508 | return (version >= 8 && version <= 10); | |
1509 | case cris_ver_v10: | |
1510 | return (version == 10); | |
29134980 OF |
1511 | case cris_ver_v10p: |
1512 | return (version >= 10); | |
c600d464 OF |
1513 | case cris_ver_v32p: |
1514 | return (version >= 32); | |
29134980 OF |
1515 | default: |
1516 | /* Invalid cris version. */ | |
1517 | return 0; | |
1518 | } | |
1519 | } | |
1520 | ||
1d94326f AC |
1521 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1522 | register, -1 for an invalid register. */ | |
1523 | ||
1524 | static int | |
1525 | cris_register_size (int regno) | |
1526 | { | |
c600d464 | 1527 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1528 | int i; |
1529 | int spec_regno; | |
1530 | ||
1531 | if (regno >= 0 && regno < NUM_GENREGS) | |
1532 | { | |
1533 | /* General registers (R0 - R15) are 32 bits. */ | |
1534 | return 4; | |
1535 | } | |
c600d464 | 1536 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1537 | { |
1538 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1539 | Adjust regno accordingly. */ | |
1540 | spec_regno = regno - NUM_GENREGS; | |
1541 | ||
c600d464 | 1542 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1543 | { |
1544 | if (cris_spec_regs[i].number == spec_regno | |
1545 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1546 | /* Go with the first applicable register. */ | |
1547 | return cris_spec_regs[i].reg_size; | |
1548 | } | |
1549 | /* Special register not applicable to this CRIS version. */ | |
1550 | return 0; | |
1551 | } | |
f57d151a | 1552 | else if (regno >= PC_REGNUM && regno < gdbarch_num_regs (current_gdbarch)) |
1d94326f | 1553 | { |
c600d464 OF |
1554 | /* This will apply to CRISv32 only where there are additional registers |
1555 | after the special registers (pseudo PC and support registers). */ | |
1556 | return 4; | |
1d94326f | 1557 | } |
c600d464 OF |
1558 | |
1559 | ||
1560 | return -1; | |
1d94326f AC |
1561 | } |
1562 | ||
29134980 OF |
1563 | /* Nonzero if regno should not be fetched from the target. This is the case |
1564 | for unimplemented (size 0) and non-existant registers. */ | |
1565 | ||
a78f21af | 1566 | static int |
29134980 OF |
1567 | cris_cannot_fetch_register (int regno) |
1568 | { | |
f57d151a | 1569 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
29134980 OF |
1570 | || (cris_register_size (regno) == 0)); |
1571 | } | |
1572 | ||
1573 | /* Nonzero if regno should not be written to the target, for various | |
1574 | reasons. */ | |
1575 | ||
a78f21af | 1576 | static int |
29134980 OF |
1577 | cris_cannot_store_register (int regno) |
1578 | { | |
1579 | /* There are three kinds of registers we refuse to write to. | |
1580 | 1. Those that not implemented. | |
1581 | 2. Those that are read-only (depends on the processor mode). | |
1582 | 3. Those registers to which a write has no effect. | |
1583 | */ | |
1584 | ||
f57d151a UW |
1585 | if (regno < 0 |
1586 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1587 | || cris_register_size (regno) == 0) | |
29134980 OF |
1588 | /* Not implemented. */ |
1589 | return 1; | |
1590 | ||
1591 | else if (regno == VR_REGNUM) | |
1592 | /* Read-only. */ | |
1593 | return 1; | |
1594 | ||
1595 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1596 | /* Writing has no effect. */ | |
1597 | return 1; | |
1598 | ||
a5f6c8f5 OF |
1599 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1600 | agent decide whether they are writable. */ | |
29134980 OF |
1601 | |
1602 | return 0; | |
1603 | } | |
1604 | ||
c600d464 OF |
1605 | /* Nonzero if regno should not be fetched from the target. This is the case |
1606 | for unimplemented (size 0) and non-existant registers. */ | |
1607 | ||
1608 | static int | |
1609 | crisv32_cannot_fetch_register (int regno) | |
1610 | { | |
f57d151a | 1611 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
c600d464 OF |
1612 | || (cris_register_size (regno) == 0)); |
1613 | } | |
1614 | ||
1615 | /* Nonzero if regno should not be written to the target, for various | |
1616 | reasons. */ | |
1617 | ||
1618 | static int | |
1619 | crisv32_cannot_store_register (int regno) | |
1620 | { | |
1621 | /* There are three kinds of registers we refuse to write to. | |
1622 | 1. Those that not implemented. | |
1623 | 2. Those that are read-only (depends on the processor mode). | |
1624 | 3. Those registers to which a write has no effect. | |
1625 | */ | |
1626 | ||
f57d151a UW |
1627 | if (regno < 0 |
1628 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1629 | || cris_register_size (regno) == 0) | |
c600d464 OF |
1630 | /* Not implemented. */ |
1631 | return 1; | |
1632 | ||
1633 | else if (regno == VR_REGNUM) | |
1634 | /* Read-only. */ | |
1635 | return 1; | |
1636 | ||
1637 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1638 | /* Writing has no effect. */ | |
1639 | return 1; | |
1640 | ||
1641 | /* Many special registers are read-only in user mode. Let the debug | |
1642 | agent decide whether they are writable. */ | |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | ||
29134980 OF |
1647 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1648 | of data in register regno. */ | |
1649 | ||
a78f21af | 1650 | static struct type * |
c1d546cd | 1651 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1652 | { |
a5f6c8f5 OF |
1653 | if (regno == PC_REGNUM) |
1654 | return builtin_type_void_func_ptr; | |
1655 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1656 | return builtin_type_void_data_ptr; | |
1657 | else if ((regno >= 0 && regno < SP_REGNUM) | |
1658 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) | |
1659 | /* Note: R8 taken care of previous clause. */ | |
1660 | return builtin_type_uint32; | |
1661 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1662 | return builtin_type_uint16; | |
1663 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1664 | return builtin_type_uint8; | |
29134980 | 1665 | else |
a5f6c8f5 OF |
1666 | /* Invalid (unimplemented) register. */ |
1667 | return builtin_type_int0; | |
29134980 OF |
1668 | } |
1669 | ||
c600d464 OF |
1670 | static struct type * |
1671 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1672 | { | |
1673 | if (regno == PC_REGNUM) | |
1674 | return builtin_type_void_func_ptr; | |
1675 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1676 | return builtin_type_void_data_ptr; | |
1677 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1678 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1679 | || (regno == PID_REGNUM) | |
1680 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1681 | /* Note: R8 and SP taken care of by previous clause. */ | |
1682 | return builtin_type_uint32; | |
1683 | else if (regno == WZ_REGNUM) | |
1684 | return builtin_type_uint16; | |
1685 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1686 | return builtin_type_uint8; | |
1687 | else | |
1688 | { | |
1689 | /* Invalid (unimplemented) register. Should not happen as there are | |
1690 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1691 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
c600d464 OF |
1692 | return builtin_type_int0; |
1693 | } | |
1694 | } | |
1695 | ||
2e4b5889 OF |
1696 | /* Stores a function return value of type type, where valbuf is the address |
1697 | of the value to be stored. */ | |
29134980 | 1698 | |
2e4b5889 | 1699 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1700 | |
2e4b5889 OF |
1701 | static void |
1702 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1703 | const void *valbuf) | |
29134980 | 1704 | { |
2e4b5889 OF |
1705 | ULONGEST val; |
1706 | int len = TYPE_LENGTH (type); | |
29134980 | 1707 | |
2e4b5889 | 1708 | if (len <= 4) |
29134980 | 1709 | { |
2e4b5889 OF |
1710 | /* Put the return value in R10. */ |
1711 | val = extract_unsigned_integer (valbuf, len); | |
1712 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1713 | } |
2e4b5889 | 1714 | else if (len <= 8) |
29134980 | 1715 | { |
2e4b5889 OF |
1716 | /* Put the return value in R10 and R11. */ |
1717 | val = extract_unsigned_integer (valbuf, 4); | |
1718 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1719 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1720 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1721 | } |
2e4b5889 | 1722 | else |
8a3fe4f8 | 1723 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1724 | } |
1725 | ||
2e4b5889 OF |
1726 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1727 | unimplemented register. */ | |
29134980 | 1728 | |
c600d464 OF |
1729 | static const char * |
1730 | cris_special_register_name (int regno) | |
1731 | { | |
1732 | int spec_regno; | |
1733 | int i; | |
1734 | ||
1735 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1736 | Adjust regno accordingly. */ | |
1737 | spec_regno = regno - NUM_GENREGS; | |
1738 | ||
1739 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1740 | when searching. */ | |
1741 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1742 | { | |
1743 | if (cris_spec_regs[i].number == spec_regno | |
1744 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1745 | /* Go with the first applicable register. */ | |
1746 | return cris_spec_regs[i].name; | |
1747 | } | |
1748 | /* Special register not applicable to this CRIS version. */ | |
1749 | return NULL; | |
1750 | } | |
1751 | ||
2e4b5889 OF |
1752 | static const char * |
1753 | cris_register_name (int regno) | |
1754 | { | |
1755 | static char *cris_genreg_names[] = | |
1756 | { "r0", "r1", "r2", "r3", \ | |
1757 | "r4", "r5", "r6", "r7", \ | |
1758 | "r8", "r9", "r10", "r11", \ | |
1759 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1760 | |
2e4b5889 | 1761 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1762 | { |
2e4b5889 OF |
1763 | /* General register. */ |
1764 | return cris_genreg_names[regno]; | |
29134980 | 1765 | } |
f57d151a | 1766 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (current_gdbarch)) |
29134980 | 1767 | { |
c600d464 OF |
1768 | return cris_special_register_name (regno); |
1769 | } | |
1770 | else | |
1771 | { | |
1772 | /* Invalid register. */ | |
2e4b5889 OF |
1773 | return NULL; |
1774 | } | |
c600d464 OF |
1775 | } |
1776 | ||
1777 | static const char * | |
1778 | crisv32_register_name (int regno) | |
1779 | { | |
1780 | static char *crisv32_genreg_names[] = | |
1781 | { "r0", "r1", "r2", "r3", \ | |
1782 | "r4", "r5", "r6", "r7", \ | |
1783 | "r8", "r9", "r10", "r11", \ | |
1784 | "r12", "r13", "sp", "acr" | |
1785 | }; | |
1786 | ||
1787 | static char *crisv32_sreg_names[] = | |
1788 | { "s0", "s1", "s2", "s3", \ | |
1789 | "s4", "s5", "s6", "s7", \ | |
1790 | "s8", "s9", "s10", "s11", \ | |
1791 | "s12", "s13", "s14", "s15" | |
1792 | }; | |
1793 | ||
1794 | if (regno >= 0 && regno < NUM_GENREGS) | |
1795 | { | |
1796 | /* General register. */ | |
1797 | return crisv32_genreg_names[regno]; | |
1798 | } | |
1799 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1800 | { | |
1801 | return cris_special_register_name (regno); | |
1802 | } | |
1803 | else if (regno == PC_REGNUM) | |
1804 | { | |
1805 | return "pc"; | |
1806 | } | |
1807 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1808 | { | |
1809 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1810 | } | |
2e4b5889 OF |
1811 | else |
1812 | { | |
1813 | /* Invalid register. */ | |
1814 | return NULL; | |
29134980 | 1815 | } |
29134980 OF |
1816 | } |
1817 | ||
a5f6c8f5 OF |
1818 | /* Convert DWARF register number REG to the appropriate register |
1819 | number used by GDB. */ | |
1820 | ||
2e4b5889 | 1821 | static int |
a5f6c8f5 | 1822 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1823 | { |
a5f6c8f5 OF |
1824 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1825 | numbering, MOF is 18). | |
1826 | Adapted from gcc/config/cris/cris.h. */ | |
1827 | static int cris_dwarf_regmap[] = { | |
1828 | 0, 1, 2, 3, | |
1829 | 4, 5, 6, 7, | |
1830 | 8, 9, 10, 11, | |
1831 | 12, 13, 14, 15, | |
1832 | 27, -1, -1, -1, | |
1833 | -1, -1, -1, 23, | |
1834 | -1, -1, -1, 27, | |
1835 | -1, -1, -1, -1 | |
1836 | }; | |
1837 | int regnum = -1; | |
1838 | ||
1839 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1840 | regnum = cris_dwarf_regmap[reg]; | |
1841 | ||
1842 | if (regnum == -1) | |
8a3fe4f8 | 1843 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1844 | |
1845 | return regnum; | |
1846 | } | |
1847 | ||
1848 | /* DWARF-2 frame support. */ | |
1849 | ||
1850 | static void | |
1851 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1852 | struct dwarf2_frame_state_reg *reg, |
1853 | struct frame_info *next_frame) | |
a5f6c8f5 OF |
1854 | { |
1855 | /* The return address column. */ | |
1856 | if (regnum == PC_REGNUM) | |
1857 | reg->how = DWARF2_FRAME_REG_RA; | |
1858 | ||
1859 | /* The call frame address. */ | |
1860 | else if (regnum == SP_REGNUM) | |
1861 | reg->how = DWARF2_FRAME_REG_CFA; | |
29134980 OF |
1862 | } |
1863 | ||
2e4b5889 OF |
1864 | /* Extract from an array regbuf containing the raw register state a function |
1865 | return value of type type, and copy that, in virtual format, into | |
1866 | valbuf. */ | |
1867 | ||
1868 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1869 | |
2e4b5889 OF |
1870 | static void |
1871 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1872 | void *valbuf) | |
29134980 | 1873 | { |
2e4b5889 OF |
1874 | ULONGEST val; |
1875 | int len = TYPE_LENGTH (type); | |
29134980 | 1876 | |
2e4b5889 | 1877 | if (len <= 4) |
29134980 | 1878 | { |
2e4b5889 OF |
1879 | /* Get the return value from R10. */ |
1880 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1881 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1882 | } |
2e4b5889 | 1883 | else if (len <= 8) |
29134980 | 1884 | { |
2e4b5889 OF |
1885 | /* Get the return value from R10 and R11. */ |
1886 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1887 | store_unsigned_integer (valbuf, 4, val); | |
1888 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1889 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1890 | } |
2e4b5889 | 1891 | else |
8a3fe4f8 | 1892 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1893 | } |
1894 | ||
b4206d25 OF |
1895 | /* Handle the CRIS return value convention. */ |
1896 | ||
1897 | static enum return_value_convention | |
1898 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
e2a2a3e8 OF |
1899 | struct regcache *regcache, gdb_byte *readbuf, |
1900 | const gdb_byte *writebuf) | |
b4206d25 OF |
1901 | { |
1902 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1903 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1904 | || TYPE_LENGTH (type) > 8) | |
1905 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1906 | goes on the stack. */ | |
1907 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1908 | ||
1909 | if (readbuf) | |
1910 | cris_extract_return_value (type, regcache, readbuf); | |
1911 | if (writebuf) | |
1912 | cris_store_return_value (type, regcache, writebuf); | |
1913 | ||
1914 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1915 | } | |
1916 | ||
2e4b5889 OF |
1917 | /* Returns 1 if the given type will be passed by pointer rather than |
1918 | directly. */ | |
1919 | ||
1920 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1921 | by value. */ | |
1922 | ||
1923 | static int | |
1924 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1925 | { | |
1926 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1927 | } |
1928 | ||
1929 | /* Calculates a value that measures how good inst_args constraints an | |
1930 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1931 | ||
1932 | static int | |
1933 | constraint (unsigned int insn, const signed char *inst_args, | |
1934 | inst_env_type *inst_env) | |
1935 | { | |
1936 | int retval = 0; | |
1937 | int tmp, i; | |
1938 | ||
1939 | const char *s = inst_args; | |
1940 | ||
1941 | for (; *s; s++) | |
1942 | switch (*s) | |
1943 | { | |
1944 | case 'm': | |
1945 | if ((insn & 0x30) == 0x30) | |
1946 | return -1; | |
1947 | break; | |
1948 | ||
1949 | case 'S': | |
1950 | /* A prefix operand. */ | |
1951 | if (inst_env->prefix_found) | |
1952 | break; | |
1953 | else | |
1954 | return -1; | |
1955 | ||
1956 | case 'B': | |
1957 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1958 | valid "push" size. In case of special register, it may be != 4. */ | |
1959 | if (inst_env->prefix_found) | |
1960 | break; | |
1961 | else | |
1962 | return -1; | |
1963 | ||
1964 | case 'D': | |
1965 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1966 | if (!retval) | |
1967 | return -1; | |
1968 | else | |
1969 | retval += 4; | |
1970 | break; | |
1971 | ||
1972 | case 'P': | |
1973 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1974 | |
1975 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1976 | { | |
1977 | /* Since we match four bits, we will give a value of | |
1978 | 4 - 1 = 3 in a match. If there is a corresponding | |
1979 | exact match of a special register in another pattern, it | |
1980 | will get a value of 4, which will be higher. This should | |
1981 | be correct in that an exact pattern would match better that | |
1982 | a general pattern. | |
1983 | Note that there is a reason for not returning zero; the | |
1984 | pattern for "clear" is partly matched in the bit-pattern | |
1985 | (the two lower bits must be zero), while the bit-pattern | |
1986 | for a move from a special register is matched in the | |
1987 | register constraint. | |
1988 | This also means we will will have a race condition if | |
1989 | there is a partly match in three bits in the bit pattern. */ | |
1990 | if (tmp == cris_spec_regs[i].number) | |
1991 | { | |
1992 | retval += 3; | |
1993 | break; | |
1994 | } | |
1995 | } | |
1996 | ||
1997 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1998 | return -1; |
1999 | break; | |
2000 | } | |
2001 | return retval; | |
2002 | } | |
2003 | ||
2004 | /* Returns the number of bits set in the variable value. */ | |
2005 | ||
2006 | static int | |
2007 | number_of_bits (unsigned int value) | |
2008 | { | |
2009 | int number_of_bits = 0; | |
2010 | ||
2011 | while (value != 0) | |
2012 | { | |
2013 | number_of_bits += 1; | |
2014 | value &= (value - 1); | |
2015 | } | |
2016 | return number_of_bits; | |
2017 | } | |
2018 | ||
2019 | /* Finds the address that should contain the single step breakpoint(s). | |
2020 | It stems from code in cris-dis.c. */ | |
2021 | ||
2022 | static int | |
2023 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
2024 | { | |
2025 | int i; | |
2026 | int max_level_of_match = -1; | |
2027 | int max_matched = -1; | |
2028 | int level_of_match; | |
2029 | ||
2030 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
2031 | { | |
2032 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
2033 | && ((cris_opcodes[i].lose & insn) == 0) |
2034 | /* Only CRISv10 instructions, please. */ | |
2035 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
2036 | { |
2037 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
2038 | if (level_of_match >= 0) | |
2039 | { | |
2040 | level_of_match += | |
2041 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
2042 | if (level_of_match > max_level_of_match) | |
2043 | { | |
2044 | max_matched = i; | |
2045 | max_level_of_match = level_of_match; | |
2046 | if (level_of_match == 16) | |
2047 | { | |
2048 | /* All bits matched, cannot find better. */ | |
2049 | break; | |
2050 | } | |
2051 | } | |
2052 | } | |
2053 | } | |
2054 | } | |
2055 | return max_matched; | |
2056 | } | |
2057 | ||
2058 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2059 | actually an internal error. */ | |
2060 | ||
2061 | static int | |
2062 | find_step_target (inst_env_type *inst_env) | |
2063 | { | |
2064 | int i; | |
2065 | int offset; | |
2066 | unsigned short insn; | |
2067 | ||
2068 | /* Create a local register image and set the initial state. */ | |
2069 | for (i = 0; i < NUM_GENREGS; i++) | |
2070 | { | |
2071 | inst_env->reg[i] = (unsigned long) read_register (i); | |
2072 | } | |
2073 | offset = NUM_GENREGS; | |
2074 | for (i = 0; i < NUM_SPECREGS; i++) | |
2075 | { | |
2076 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
2077 | } | |
2078 | inst_env->branch_found = 0; | |
2079 | inst_env->slot_needed = 0; | |
2080 | inst_env->delay_slot_pc_active = 0; | |
2081 | inst_env->prefix_found = 0; | |
2082 | inst_env->invalid = 0; | |
2083 | inst_env->xflag_found = 0; | |
2084 | inst_env->disable_interrupt = 0; | |
2085 | ||
2086 | /* Look for a step target. */ | |
2087 | do | |
2088 | { | |
2089 | /* Read an instruction from the client. */ | |
2090 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
2091 | ||
2092 | /* If the instruction is not in a delay slot the new content of the | |
2093 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2094 | that simple. Since a instruction in a delay slot cannot change | |
2095 | the content of the PC, it does not matter what value PC will have. | |
2096 | Just make sure it is a valid instruction. */ | |
2097 | if (!inst_env->delay_slot_pc_active) | |
2098 | { | |
2099 | inst_env->reg[PC_REGNUM] += 2; | |
2100 | } | |
2101 | else | |
2102 | { | |
2103 | inst_env->delay_slot_pc_active = 0; | |
2104 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
2105 | } | |
2106 | /* Analyse the present instruction. */ | |
2107 | i = find_cris_op (insn, inst_env); | |
2108 | if (i == -1) | |
2109 | { | |
2110 | inst_env->invalid = 1; | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2115 | } | |
2116 | } while (!inst_env->invalid | |
2117 | && (inst_env->prefix_found || inst_env->xflag_found | |
2118 | || inst_env->slot_needed)); | |
2119 | return i; | |
2120 | } | |
2121 | ||
2122 | /* There is no hardware single-step support. The function find_step_target | |
2123 | digs through the opcodes in order to find all possible targets. | |
2124 | Either one ordinary target or two targets for branches may be found. */ | |
2125 | ||
e6590a1b | 2126 | static int |
e0cd558a | 2127 | cris_software_single_step (struct regcache *regcache) |
29134980 OF |
2128 | { |
2129 | inst_env_type inst_env; | |
8181d85f | 2130 | |
e0cd558a UW |
2131 | /* Analyse the present instruction environment and insert |
2132 | breakpoints. */ | |
2133 | int status = find_step_target (&inst_env); | |
2134 | if (status == -1) | |
29134980 | 2135 | { |
e0cd558a UW |
2136 | /* Could not find a target. Things are likely to go downhill |
2137 | from here. */ | |
2138 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2139 | } |
2140 | else | |
e0cd558a UW |
2141 | { |
2142 | /* Insert at most two breakpoints. One for the next PC content | |
2143 | and possibly another one for a branch, jump, etc. */ | |
2144 | CORE_ADDR next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
2145 | insert_single_step_breakpoint (next_pc); | |
2146 | if (inst_env.branch_found | |
2147 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2148 | { | |
2149 | CORE_ADDR branch_target_address | |
2150 | = (CORE_ADDR) inst_env.branch_break_address; | |
2151 | insert_single_step_breakpoint (branch_target_address); | |
2152 | } | |
2153 | } | |
e6590a1b UW |
2154 | |
2155 | return 1; | |
29134980 OF |
2156 | } |
2157 | ||
2158 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2159 | ||
a78f21af | 2160 | static void |
29134980 OF |
2161 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2162 | { | |
2163 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2164 | instruction (not 100% sure). */ | |
2165 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2166 | { | |
2167 | inst_env->invalid = 1; | |
2168 | return; | |
2169 | } | |
2170 | ||
2171 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2172 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2173 | ||
2174 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2175 | need updating. */ | |
2176 | inst_env->slot_needed = 0; | |
2177 | inst_env->prefix_found = 1; | |
2178 | } | |
2179 | ||
2180 | /* Updates the autoincrement register. The size of the increment is derived | |
2181 | from the size of the operation. The PC is always kept aligned on even | |
2182 | word addresses. */ | |
2183 | ||
a78f21af | 2184 | static void |
29134980 OF |
2185 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2186 | { | |
2187 | if (size == INST_BYTE_SIZE) | |
2188 | { | |
2189 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2190 | ||
2191 | /* The PC must be word aligned, so increase the PC with one | |
2192 | word even if the size is byte. */ | |
2193 | if (cris_get_operand1 (inst) == REG_PC) | |
2194 | { | |
2195 | inst_env->reg[REG_PC] += 1; | |
2196 | } | |
2197 | } | |
2198 | else if (size == INST_WORD_SIZE) | |
2199 | { | |
2200 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2201 | } | |
2202 | else if (size == INST_DWORD_SIZE) | |
2203 | { | |
2204 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2205 | } | |
2206 | else | |
2207 | { | |
2208 | /* Invalid size. */ | |
2209 | inst_env->invalid = 1; | |
2210 | } | |
2211 | } | |
2212 | ||
2a9ecef2 OF |
2213 | /* Just a forward declaration. */ |
2214 | ||
a78f21af AC |
2215 | static unsigned long get_data_from_address (unsigned short *inst, |
2216 | CORE_ADDR address); | |
2a9ecef2 | 2217 | |
29134980 OF |
2218 | /* Calculates the prefix value for the general case of offset addressing |
2219 | mode. */ | |
2220 | ||
a78f21af | 2221 | static void |
29134980 OF |
2222 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2223 | { | |
2224 | ||
2225 | long offset; | |
2226 | ||
2227 | /* It's invalid to be in a delay slot. */ | |
2228 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2229 | { | |
2230 | inst_env->invalid = 1; | |
2231 | return; | |
2232 | } | |
2233 | ||
fa4e4598 OF |
2234 | /* The calculation of prefix_value used to be after process_autoincrement, |
2235 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2236 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2237 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2238 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2239 | ||
2240 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2241 | inst_env->prefix_value += | |
2a9ecef2 OF |
2242 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2243 | ||
fa4e4598 OF |
2244 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2245 | { | |
2246 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2247 | } | |
2248 | ||
29134980 OF |
2249 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2250 | need updating. */ | |
2251 | inst_env->slot_needed = 0; | |
2252 | inst_env->prefix_found = 1; | |
2253 | } | |
2254 | ||
2255 | /* Calculates the prefix value for the index addressing mode. */ | |
2256 | ||
a78f21af | 2257 | static void |
29134980 OF |
2258 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2259 | { | |
2260 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2261 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2262 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2263 | { | |
2264 | inst_env->invalid = 1; | |
2265 | return; | |
2266 | } | |
2267 | ||
2268 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2269 | ||
2270 | /* The offset is the operand2 value shifted the size of the instruction | |
2271 | to the left. */ | |
2272 | inst_env->prefix_value += | |
2273 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2274 | ||
2275 | /* If the PC is operand1 (base) the address used is the address after | |
2276 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2277 | for the prefix operation). */ | |
2278 | if (cris_get_operand1 (inst) == REG_PC) | |
2279 | { | |
2280 | inst_env->prefix_value += 2; | |
2281 | } | |
2282 | ||
2283 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2284 | need updating. */ | |
2285 | inst_env->slot_needed = 0; | |
2286 | inst_env->xflag_found = 0; | |
2287 | inst_env->prefix_found = 1; | |
2288 | } | |
2289 | ||
2290 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2291 | ||
a78f21af | 2292 | static void |
29134980 OF |
2293 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2294 | { | |
2295 | ||
2296 | CORE_ADDR address; | |
2297 | ||
2298 | /* It's invalid to be in a delay slot. */ | |
2299 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2300 | { | |
2301 | inst_env->invalid = 1; | |
2302 | return; | |
2303 | } | |
2304 | ||
2305 | /* The prefix value is one dereference of the contents of the operand1 | |
2306 | register. */ | |
2307 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2308 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2309 | ||
2310 | /* Check if the mode is autoincrement. */ | |
2311 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2312 | { | |
2313 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2314 | } | |
2315 | ||
2316 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2317 | need updating. */ | |
2318 | inst_env->slot_needed = 0; | |
2319 | inst_env->xflag_found = 0; | |
2320 | inst_env->prefix_found = 1; | |
2321 | } | |
2322 | ||
2323 | /* Finds the destination for a branch with 8-bits offset. */ | |
2324 | ||
a78f21af | 2325 | static void |
29134980 OF |
2326 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2327 | { | |
2328 | ||
2329 | short offset; | |
2330 | ||
2331 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2332 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2333 | { | |
2334 | inst_env->invalid = 1; | |
2335 | return; | |
2336 | } | |
2337 | ||
2338 | /* We have a branch, find out where the branch will land. */ | |
2339 | offset = cris_get_branch_short_offset (inst); | |
2340 | ||
2341 | /* Check if the offset is signed. */ | |
2342 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2343 | { | |
2344 | offset |= 0xFF00; | |
2345 | } | |
2346 | ||
2347 | /* The offset ends with the sign bit, set it to zero. The address | |
2348 | should always be word aligned. */ | |
2349 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2350 | ||
2351 | inst_env->branch_found = 1; | |
2352 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2353 | ||
2354 | inst_env->slot_needed = 1; | |
2355 | inst_env->prefix_found = 0; | |
2356 | inst_env->xflag_found = 0; | |
2357 | inst_env->disable_interrupt = 1; | |
2358 | } | |
2359 | ||
2360 | /* Finds the destination for a branch with 16-bits offset. */ | |
2361 | ||
a78f21af | 2362 | static void |
29134980 OF |
2363 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2364 | { | |
2365 | short offset; | |
2366 | ||
2367 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2368 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2369 | { | |
2370 | inst_env->invalid = 1; | |
2371 | return; | |
2372 | } | |
2373 | ||
2374 | /* We have a branch, find out the offset for the branch. */ | |
2375 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2376 | ||
2377 | /* The instruction is one word longer than normal, so add one word | |
2378 | to the PC. */ | |
2379 | inst_env->reg[REG_PC] += 2; | |
2380 | ||
2381 | inst_env->branch_found = 1; | |
2382 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2383 | ||
2384 | ||
2385 | inst_env->slot_needed = 1; | |
2386 | inst_env->prefix_found = 0; | |
2387 | inst_env->xflag_found = 0; | |
2388 | inst_env->disable_interrupt = 1; | |
2389 | } | |
2390 | ||
2391 | /* Handles the ABS instruction. */ | |
2392 | ||
a78f21af | 2393 | static void |
29134980 OF |
2394 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2395 | { | |
2396 | ||
2397 | long value; | |
2398 | ||
2399 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2400 | if (inst_env->prefix_found) | |
2401 | { | |
2402 | inst_env->invalid = 1; | |
2403 | return; | |
2404 | } | |
2405 | ||
2406 | /* Check if the operation affects the PC. */ | |
2407 | if (cris_get_operand2 (inst) == REG_PC) | |
2408 | { | |
2409 | ||
2410 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2411 | if (inst_env->slot_needed) | |
2412 | { | |
2413 | inst_env->invalid = 1; | |
2414 | return; | |
2415 | } | |
2416 | ||
2417 | value = (long) inst_env->reg[REG_PC]; | |
2418 | ||
2419 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2420 | if (value != SIGNED_DWORD_MASK) | |
2421 | { | |
2422 | value = -value; | |
2423 | inst_env->reg[REG_PC] = (long) value; | |
2424 | } | |
2425 | } | |
2426 | ||
2427 | inst_env->slot_needed = 0; | |
2428 | inst_env->prefix_found = 0; | |
2429 | inst_env->xflag_found = 0; | |
2430 | inst_env->disable_interrupt = 0; | |
2431 | } | |
2432 | ||
2433 | /* Handles the ADDI instruction. */ | |
2434 | ||
a78f21af | 2435 | static void |
29134980 OF |
2436 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2437 | { | |
2438 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2439 | a prefix. */ | |
2440 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2441 | { | |
2442 | inst_env->invalid = 1; | |
2443 | return; | |
2444 | } | |
2445 | ||
2446 | inst_env->slot_needed = 0; | |
2447 | inst_env->prefix_found = 0; | |
2448 | inst_env->xflag_found = 0; | |
2449 | inst_env->disable_interrupt = 0; | |
2450 | } | |
2451 | ||
2452 | /* Handles the ASR instruction. */ | |
2453 | ||
a78f21af | 2454 | static void |
29134980 OF |
2455 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2456 | { | |
2457 | int shift_steps; | |
2458 | unsigned long value; | |
2459 | unsigned long signed_extend_mask = 0; | |
2460 | ||
2461 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2462 | if (inst_env->prefix_found) | |
2463 | { | |
2464 | inst_env->invalid = 1; | |
2465 | return; | |
2466 | } | |
2467 | ||
2468 | /* Check if the PC is the target register. */ | |
2469 | if (cris_get_operand2 (inst) == REG_PC) | |
2470 | { | |
2471 | /* It's invalid to change the PC in a delay slot. */ | |
2472 | if (inst_env->slot_needed) | |
2473 | { | |
2474 | inst_env->invalid = 1; | |
2475 | return; | |
2476 | } | |
2477 | /* Get the number of bits to shift. */ | |
2478 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2479 | value = inst_env->reg[REG_PC]; | |
2480 | ||
2481 | /* Find out how many bits the operation should apply to. */ | |
2482 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2483 | { | |
2484 | if (value & SIGNED_BYTE_MASK) | |
2485 | { | |
2486 | signed_extend_mask = 0xFF; | |
2487 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2488 | signed_extend_mask = ~signed_extend_mask; | |
2489 | } | |
2490 | value = value >> shift_steps; | |
2491 | value |= signed_extend_mask; | |
2492 | value &= 0xFF; | |
2493 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2494 | inst_env->reg[REG_PC] |= value; | |
2495 | } | |
2496 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2497 | { | |
2498 | if (value & SIGNED_WORD_MASK) | |
2499 | { | |
2500 | signed_extend_mask = 0xFFFF; | |
2501 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2502 | signed_extend_mask = ~signed_extend_mask; | |
2503 | } | |
2504 | value = value >> shift_steps; | |
2505 | value |= signed_extend_mask; | |
2506 | value &= 0xFFFF; | |
2507 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2508 | inst_env->reg[REG_PC] |= value; | |
2509 | } | |
2510 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2511 | { | |
2512 | if (value & SIGNED_DWORD_MASK) | |
2513 | { | |
2514 | signed_extend_mask = 0xFFFFFFFF; | |
2515 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2516 | signed_extend_mask = ~signed_extend_mask; | |
2517 | } | |
2518 | value = value >> shift_steps; | |
2519 | value |= signed_extend_mask; | |
2520 | inst_env->reg[REG_PC] = value; | |
2521 | } | |
2522 | } | |
2523 | inst_env->slot_needed = 0; | |
2524 | inst_env->prefix_found = 0; | |
2525 | inst_env->xflag_found = 0; | |
2526 | inst_env->disable_interrupt = 0; | |
2527 | } | |
2528 | ||
2529 | /* Handles the ASRQ instruction. */ | |
2530 | ||
a78f21af | 2531 | static void |
29134980 OF |
2532 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2533 | { | |
2534 | ||
2535 | int shift_steps; | |
2536 | unsigned long value; | |
2537 | unsigned long signed_extend_mask = 0; | |
2538 | ||
2539 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2540 | if (inst_env->prefix_found) | |
2541 | { | |
2542 | inst_env->invalid = 1; | |
2543 | return; | |
2544 | } | |
2545 | ||
2546 | /* Check if the PC is the target register. */ | |
2547 | if (cris_get_operand2 (inst) == REG_PC) | |
2548 | { | |
2549 | ||
2550 | /* It's invalid to change the PC in a delay slot. */ | |
2551 | if (inst_env->slot_needed) | |
2552 | { | |
2553 | inst_env->invalid = 1; | |
2554 | return; | |
2555 | } | |
2556 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2557 | want the the sign bit of the quick value. */ | |
2558 | shift_steps = cris_get_asr_shift_steps (inst); | |
2559 | value = inst_env->reg[REG_PC]; | |
2560 | if (value & SIGNED_DWORD_MASK) | |
2561 | { | |
2562 | signed_extend_mask = 0xFFFFFFFF; | |
2563 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2564 | signed_extend_mask = ~signed_extend_mask; | |
2565 | } | |
2566 | value = value >> shift_steps; | |
2567 | value |= signed_extend_mask; | |
2568 | inst_env->reg[REG_PC] = value; | |
2569 | } | |
2570 | inst_env->slot_needed = 0; | |
2571 | inst_env->prefix_found = 0; | |
2572 | inst_env->xflag_found = 0; | |
2573 | inst_env->disable_interrupt = 0; | |
2574 | } | |
2575 | ||
2576 | /* Handles the AX, EI and SETF instruction. */ | |
2577 | ||
a78f21af | 2578 | static void |
29134980 OF |
2579 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2580 | { | |
2581 | if (inst_env->prefix_found) | |
2582 | { | |
2583 | inst_env->invalid = 1; | |
2584 | return; | |
2585 | } | |
2586 | /* Check if the instruction is setting the X flag. */ | |
2587 | if (cris_is_xflag_bit_on (inst)) | |
2588 | { | |
2589 | inst_env->xflag_found = 1; | |
2590 | } | |
2591 | else | |
2592 | { | |
2593 | inst_env->xflag_found = 0; | |
2594 | } | |
2595 | inst_env->slot_needed = 0; | |
2596 | inst_env->prefix_found = 0; | |
2597 | inst_env->disable_interrupt = 1; | |
2598 | } | |
2599 | ||
2600 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2601 | register. Note that check_assign assumes that the caller has checked that | |
2602 | there is a prefix to this instruction. The mode check depends on this. */ | |
2603 | ||
a78f21af | 2604 | static void |
29134980 OF |
2605 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2606 | { | |
2607 | /* Check if it's an assign addressing mode. */ | |
2608 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2609 | { | |
2610 | /* Assign the prefix value to operand 1. */ | |
2611 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2612 | } | |
2613 | } | |
2614 | ||
2615 | /* Handles the 2-operand BOUND instruction. */ | |
2616 | ||
a78f21af | 2617 | static void |
29134980 OF |
2618 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2619 | { | |
2620 | /* It's invalid to have the PC as the index operand. */ | |
2621 | if (cris_get_operand2 (inst) == REG_PC) | |
2622 | { | |
2623 | inst_env->invalid = 1; | |
2624 | return; | |
2625 | } | |
2626 | /* Check if we have a prefix. */ | |
2627 | if (inst_env->prefix_found) | |
2628 | { | |
2629 | check_assign (inst, inst_env); | |
2630 | } | |
2631 | /* Check if this is an autoincrement mode. */ | |
2632 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2633 | { | |
2634 | /* It's invalid to change the PC in a delay slot. */ | |
2635 | if (inst_env->slot_needed) | |
2636 | { | |
2637 | inst_env->invalid = 1; | |
2638 | return; | |
2639 | } | |
2640 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2641 | } | |
2642 | inst_env->slot_needed = 0; | |
2643 | inst_env->prefix_found = 0; | |
2644 | inst_env->xflag_found = 0; | |
2645 | inst_env->disable_interrupt = 0; | |
2646 | } | |
2647 | ||
2648 | /* Handles the 3-operand BOUND instruction. */ | |
2649 | ||
a78f21af | 2650 | static void |
29134980 OF |
2651 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2652 | { | |
2653 | /* It's an error if we haven't got a prefix. And it's also an error | |
2654 | if the PC is the destination register. */ | |
2655 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2656 | { | |
2657 | inst_env->invalid = 1; | |
2658 | return; | |
2659 | } | |
2660 | inst_env->slot_needed = 0; | |
2661 | inst_env->prefix_found = 0; | |
2662 | inst_env->xflag_found = 0; | |
2663 | inst_env->disable_interrupt = 0; | |
2664 | } | |
2665 | ||
2666 | /* Clears the status flags in inst_env. */ | |
2667 | ||
a78f21af | 2668 | static void |
29134980 OF |
2669 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2670 | { | |
2671 | /* It's an error if we have got a prefix. */ | |
2672 | if (inst_env->prefix_found) | |
2673 | { | |
2674 | inst_env->invalid = 1; | |
2675 | return; | |
2676 | } | |
2677 | ||
2678 | inst_env->slot_needed = 0; | |
2679 | inst_env->prefix_found = 0; | |
2680 | inst_env->xflag_found = 0; | |
2681 | inst_env->disable_interrupt = 0; | |
2682 | } | |
2683 | ||
2684 | /* Clears the status flags in inst_env. */ | |
2685 | ||
a78f21af | 2686 | static void |
29134980 OF |
2687 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2688 | { | |
2689 | /* It's an error if we have got a prefix. */ | |
2690 | if (inst_env->prefix_found) | |
2691 | { | |
2692 | inst_env->invalid = 1; | |
2693 | return; | |
2694 | } | |
2695 | ||
2696 | inst_env->slot_needed = 0; | |
2697 | inst_env->prefix_found = 0; | |
2698 | inst_env->xflag_found = 0; | |
2699 | inst_env->disable_interrupt = 1; | |
2700 | } | |
2701 | ||
2702 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2703 | ||
a78f21af | 2704 | static void |
29134980 OF |
2705 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2706 | { | |
2707 | /* Check if the target is the PC. */ | |
2708 | if (cris_get_operand2 (inst) == REG_PC) | |
2709 | { | |
2710 | /* The instruction will clear the instruction's size bits. */ | |
2711 | int clear_size = cris_get_clear_size (inst); | |
2712 | if (clear_size == INST_BYTE_SIZE) | |
2713 | { | |
2714 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2715 | } | |
2716 | if (clear_size == INST_WORD_SIZE) | |
2717 | { | |
2718 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2719 | } | |
2720 | if (clear_size == INST_DWORD_SIZE) | |
2721 | { | |
2722 | inst_env->delay_slot_pc = 0x0; | |
2723 | } | |
2724 | /* The jump will be delayed with one delay slot. So we need a delay | |
2725 | slot. */ | |
2726 | inst_env->slot_needed = 1; | |
2727 | inst_env->delay_slot_pc_active = 1; | |
2728 | } | |
2729 | else | |
2730 | { | |
2731 | /* The PC will not change => no delay slot. */ | |
2732 | inst_env->slot_needed = 0; | |
2733 | } | |
2734 | inst_env->prefix_found = 0; | |
2735 | inst_env->xflag_found = 0; | |
2736 | inst_env->disable_interrupt = 0; | |
2737 | } | |
2738 | ||
2739 | /* Handles the TEST instruction if it's in register mode. */ | |
2740 | ||
a78f21af | 2741 | static void |
29134980 OF |
2742 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2743 | { | |
2744 | /* It's an error if we have got a prefix. */ | |
2745 | if (inst_env->prefix_found) | |
2746 | { | |
2747 | inst_env->invalid = 1; | |
2748 | return; | |
2749 | } | |
2750 | inst_env->slot_needed = 0; | |
2751 | inst_env->prefix_found = 0; | |
2752 | inst_env->xflag_found = 0; | |
2753 | inst_env->disable_interrupt = 0; | |
2754 | ||
2755 | } | |
2756 | ||
2757 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2758 | in register mode. */ | |
2759 | ||
a78f21af | 2760 | static void |
29134980 OF |
2761 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2762 | { | |
2763 | /* Check if we are in a prefix mode. */ | |
2764 | if (inst_env->prefix_found) | |
2765 | { | |
2766 | /* The only way the PC can change is if this instruction is in | |
2767 | assign addressing mode. */ | |
2768 | check_assign (inst, inst_env); | |
2769 | } | |
2770 | /* Indirect mode can't change the PC so just check if the mode is | |
2771 | autoincrement. */ | |
2772 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2773 | { | |
2774 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2775 | } | |
2776 | inst_env->slot_needed = 0; | |
2777 | inst_env->prefix_found = 0; | |
2778 | inst_env->xflag_found = 0; | |
2779 | inst_env->disable_interrupt = 0; | |
2780 | } | |
2781 | ||
2782 | /* Checks that the PC isn't the destination register or the instructions has | |
2783 | a prefix. */ | |
2784 | ||
a78f21af | 2785 | static void |
29134980 OF |
2786 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2787 | { | |
2788 | /* It's invalid to have the PC as the destination. The instruction can't | |
2789 | have a prefix. */ | |
2790 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2791 | { | |
2792 | inst_env->invalid = 1; | |
2793 | return; | |
2794 | } | |
2795 | ||
2796 | inst_env->slot_needed = 0; | |
2797 | inst_env->prefix_found = 0; | |
2798 | inst_env->xflag_found = 0; | |
2799 | inst_env->disable_interrupt = 0; | |
2800 | } | |
2801 | ||
2802 | /* Checks that the instruction doesn't have a prefix. */ | |
2803 | ||
a78f21af | 2804 | static void |
29134980 OF |
2805 | break_op (unsigned short inst, inst_env_type *inst_env) |
2806 | { | |
2807 | /* The instruction can't have a prefix. */ | |
2808 | if (inst_env->prefix_found) | |
2809 | { | |
2810 | inst_env->invalid = 1; | |
2811 | return; | |
2812 | } | |
2813 | ||
2814 | inst_env->slot_needed = 0; | |
2815 | inst_env->prefix_found = 0; | |
2816 | inst_env->xflag_found = 0; | |
2817 | inst_env->disable_interrupt = 1; | |
2818 | } | |
2819 | ||
2820 | /* Checks that the PC isn't the destination register and that the instruction | |
2821 | doesn't have a prefix. */ | |
2822 | ||
a78f21af | 2823 | static void |
29134980 OF |
2824 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2825 | { | |
2826 | /* It's invalid to have the PC as the destination. The instruction can't | |
2827 | have a prefix. */ | |
2828 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2829 | { | |
2830 | inst_env->invalid = 1; | |
2831 | return; | |
2832 | } | |
2833 | ||
2834 | inst_env->slot_needed = 0; | |
2835 | inst_env->prefix_found = 0; | |
2836 | inst_env->xflag_found = 0; | |
2837 | inst_env->disable_interrupt = 1; | |
2838 | } | |
2839 | ||
2840 | /* Handles the register mode JUMP instruction. */ | |
2841 | ||
a78f21af | 2842 | static void |
29134980 OF |
2843 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2844 | { | |
2845 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2846 | you can't have a prefix. */ | |
2847 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2848 | { | |
2849 | inst_env->invalid = 1; | |
2850 | return; | |
2851 | } | |
2852 | ||
2853 | /* Just change the PC. */ | |
2854 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2855 | inst_env->slot_needed = 0; | |
2856 | inst_env->prefix_found = 0; | |
2857 | inst_env->xflag_found = 0; | |
2858 | inst_env->disable_interrupt = 1; | |
2859 | } | |
2860 | ||
2861 | /* Handles the JUMP instruction for all modes except register. */ | |
2862 | ||
a78f21af AC |
2863 | static void |
2864 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2865 | { |
2866 | unsigned long newpc; | |
2867 | CORE_ADDR address; | |
2868 | ||
2869 | /* It's invalid to do a JUMP in a delay slot. */ | |
2870 | if (inst_env->slot_needed) | |
2871 | { | |
2872 | inst_env->invalid = 1; | |
2873 | } | |
2874 | else | |
2875 | { | |
2876 | /* Check if we have a prefix. */ | |
2877 | if (inst_env->prefix_found) | |
2878 | { | |
2879 | check_assign (inst, inst_env); | |
2880 | ||
2881 | /* Get the new value for the the PC. */ | |
2882 | newpc = | |
2883 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2884 | 4); | |
2885 | } | |
2886 | else | |
2887 | { | |
2888 | /* Get the new value for the PC. */ | |
2889 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2890 | newpc = read_memory_unsigned_integer (address, 4); | |
2891 | ||
2892 | /* Check if we should increment a register. */ | |
2893 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2894 | { | |
2895 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2896 | } | |
2897 | } | |
2898 | inst_env->reg[REG_PC] = newpc; | |
2899 | } | |
2900 | inst_env->slot_needed = 0; | |
2901 | inst_env->prefix_found = 0; | |
2902 | inst_env->xflag_found = 0; | |
2903 | inst_env->disable_interrupt = 1; | |
2904 | } | |
2905 | ||
2906 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2907 | ||
a78f21af | 2908 | static void |
29134980 OF |
2909 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2910 | { | |
2911 | if (inst_env->prefix_found) | |
2912 | { | |
2913 | /* The instruction has a prefix that means we are only interested if | |
2914 | the instruction is in assign mode. */ | |
2915 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2916 | { | |
2917 | /* The prefix handles the problem if we are in a delay slot. */ | |
2918 | if (cris_get_operand1 (inst) == REG_PC) | |
2919 | { | |
2920 | /* Just take care of the assign. */ | |
2921 | check_assign (inst, inst_env); | |
2922 | } | |
2923 | } | |
2924 | } | |
2925 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2926 | { | |
2927 | /* The instruction doesn't have a prefix, the only case left that we | |
2928 | are interested in is the autoincrement mode. */ | |
2929 | if (cris_get_operand1 (inst) == REG_PC) | |
2930 | { | |
2931 | /* If the PC is to be incremented it's invalid to be in a | |
2932 | delay slot. */ | |
2933 | if (inst_env->slot_needed) | |
2934 | { | |
2935 | inst_env->invalid = 1; | |
2936 | return; | |
2937 | } | |
2a9ecef2 OF |
2938 | |
2939 | /* The increment depends on the size of the special register. */ | |
2940 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2941 | { |
2942 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2943 | } | |
2a9ecef2 | 2944 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2945 | { |
2946 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2947 | } | |
2948 | else | |
2949 | { | |
2950 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2951 | } | |
2952 | } | |
2953 | } | |
2954 | inst_env->slot_needed = 0; | |
2955 | inst_env->prefix_found = 0; | |
2956 | inst_env->xflag_found = 0; | |
2957 | inst_env->disable_interrupt = 1; | |
2958 | } | |
2959 | ||
2960 | /* Handles moves from special registers (aka P-register) for all modes | |
2961 | except register. */ | |
2962 | ||
a78f21af | 2963 | static void |
29134980 OF |
2964 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2965 | { | |
2966 | if (inst_env->prefix_found) | |
2967 | { | |
2968 | /* The instruction has a prefix that means we are only interested if | |
2969 | the instruction is in assign mode. */ | |
2970 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2971 | { | |
2972 | /* The prefix handles the problem if we are in a delay slot. */ | |
2973 | if (cris_get_operand1 (inst) == REG_PC) | |
2974 | { | |
2975 | /* Just take care of the assign. */ | |
2976 | check_assign (inst, inst_env); | |
2977 | } | |
2978 | } | |
2979 | } | |
2980 | /* The instruction doesn't have a prefix, the only case left that we | |
2981 | are interested in is the autoincrement mode. */ | |
2982 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2983 | { | |
2984 | if (cris_get_operand1 (inst) == REG_PC) | |
2985 | { | |
2986 | /* If the PC is to be incremented it's invalid to be in a | |
2987 | delay slot. */ | |
2988 | if (inst_env->slot_needed) | |
2989 | { | |
2990 | inst_env->invalid = 1; | |
2991 | return; | |
2992 | } | |
2a9ecef2 OF |
2993 | |
2994 | /* The increment depends on the size of the special register. */ | |
2995 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2996 | { |
2997 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2998 | } | |
2a9ecef2 | 2999 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
3000 | { |
3001 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
3002 | } | |
3003 | else | |
3004 | { | |
3005 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
3006 | } | |
3007 | } | |
3008 | } | |
3009 | inst_env->slot_needed = 0; | |
3010 | inst_env->prefix_found = 0; | |
3011 | inst_env->xflag_found = 0; | |
3012 | inst_env->disable_interrupt = 1; | |
3013 | } | |
3014 | ||
3015 | /* Handles moves from special registers (aka P-register) when the mode | |
3016 | is register. */ | |
3017 | ||
a78f21af | 3018 | static void |
29134980 OF |
3019 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
3020 | { | |
3021 | /* Register mode move from special register can't have a prefix. */ | |
3022 | if (inst_env->prefix_found) | |
3023 | { | |
3024 | inst_env->invalid = 1; | |
3025 | return; | |
3026 | } | |
3027 | ||
3028 | if (cris_get_operand1 (inst) == REG_PC) | |
3029 | { | |
3030 | /* It's invalid to change the PC in a delay slot. */ | |
3031 | if (inst_env->slot_needed) | |
3032 | { | |
3033 | inst_env->invalid = 1; | |
3034 | return; | |
3035 | } | |
3036 | /* The destination is the PC, the jump will have a delay slot. */ | |
3037 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3038 | inst_env->slot_needed = 1; | |
3039 | inst_env->delay_slot_pc_active = 1; | |
3040 | } | |
3041 | else | |
3042 | { | |
3043 | /* If the destination isn't PC, there will be no jump. */ | |
3044 | inst_env->slot_needed = 0; | |
3045 | } | |
3046 | inst_env->prefix_found = 0; | |
3047 | inst_env->xflag_found = 0; | |
3048 | inst_env->disable_interrupt = 1; | |
3049 | } | |
3050 | ||
3051 | /* Handles the MOVEM from memory to general register instruction. */ | |
3052 | ||
a78f21af | 3053 | static void |
29134980 OF |
3054 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3055 | { | |
3056 | if (inst_env->prefix_found) | |
3057 | { | |
3058 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3059 | MOVEM instruction going to change the PC? */ | |
3060 | if (cris_get_operand2 (inst) >= REG_PC) | |
3061 | { | |
3062 | inst_env->reg[REG_PC] = | |
3063 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
3064 | } | |
3065 | /* The assign value is the value after the increment. Normally, the | |
3066 | assign value is the value before the increment. */ | |
3067 | if ((cris_get_operand1 (inst) == REG_PC) | |
3068 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3069 | { | |
3070 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3071 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3072 | } | |
3073 | } | |
3074 | else | |
3075 | { | |
3076 | /* Is the MOVEM instruction going to change the PC? */ | |
3077 | if (cris_get_operand2 (inst) == REG_PC) | |
3078 | { | |
3079 | /* It's invalid to change the PC in a delay slot. */ | |
3080 | if (inst_env->slot_needed) | |
3081 | { | |
3082 | inst_env->invalid = 1; | |
3083 | return; | |
3084 | } | |
3085 | inst_env->reg[REG_PC] = | |
3086 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3087 | 4); | |
3088 | } | |
3089 | /* The increment is not depending on the size, instead it's depending | |
3090 | on the number of registers loaded from memory. */ | |
3091 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3092 | { | |
3093 | /* It's invalid to change the PC in a delay slot. */ | |
3094 | if (inst_env->slot_needed) | |
3095 | { | |
3096 | inst_env->invalid = 1; | |
3097 | return; | |
3098 | } | |
3099 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3100 | } | |
3101 | } | |
3102 | inst_env->slot_needed = 0; | |
3103 | inst_env->prefix_found = 0; | |
3104 | inst_env->xflag_found = 0; | |
3105 | inst_env->disable_interrupt = 0; | |
3106 | } | |
3107 | ||
3108 | /* Handles the MOVEM to memory from general register instruction. */ | |
3109 | ||
a78f21af | 3110 | static void |
29134980 OF |
3111 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3112 | { | |
3113 | if (inst_env->prefix_found) | |
3114 | { | |
3115 | /* The assign value is the value after the increment. Normally, the | |
3116 | assign value is the value before the increment. */ | |
3117 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3118 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3119 | { | |
3120 | /* The prefix handles the problem if we are in a delay slot. */ | |
3121 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3122 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3123 | } | |
3124 | } | |
3125 | else | |
3126 | { | |
3127 | /* The increment is not depending on the size, instead it's depending | |
3128 | on the number of registers loaded to memory. */ | |
3129 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3130 | { | |
3131 | /* It's invalid to change the PC in a delay slot. */ | |
3132 | if (inst_env->slot_needed) | |
3133 | { | |
3134 | inst_env->invalid = 1; | |
3135 | return; | |
3136 | } | |
3137 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3138 | } | |
3139 | } | |
3140 | inst_env->slot_needed = 0; | |
3141 | inst_env->prefix_found = 0; | |
3142 | inst_env->xflag_found = 0; | |
3143 | inst_env->disable_interrupt = 0; | |
3144 | } | |
3145 | ||
29134980 OF |
3146 | /* Handles the intructions that's not yet implemented, by setting |
3147 | inst_env->invalid to true. */ | |
3148 | ||
a78f21af | 3149 | static void |
29134980 OF |
3150 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3151 | { | |
3152 | inst_env->invalid = 1; | |
3153 | } | |
3154 | ||
3155 | /* Handles the XOR instruction. */ | |
3156 | ||
a78f21af | 3157 | static void |
29134980 OF |
3158 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3159 | { | |
3160 | /* XOR can't have a prefix. */ | |
3161 | if (inst_env->prefix_found) | |
3162 | { | |
3163 | inst_env->invalid = 1; | |
3164 | return; | |
3165 | } | |
3166 | ||
3167 | /* Check if the PC is the target. */ | |
3168 | if (cris_get_operand2 (inst) == REG_PC) | |
3169 | { | |
3170 | /* It's invalid to change the PC in a delay slot. */ | |
3171 | if (inst_env->slot_needed) | |
3172 | { | |
3173 | inst_env->invalid = 1; | |
3174 | return; | |
3175 | } | |
3176 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3177 | } | |
3178 | inst_env->slot_needed = 0; | |
3179 | inst_env->prefix_found = 0; | |
3180 | inst_env->xflag_found = 0; | |
3181 | inst_env->disable_interrupt = 0; | |
3182 | } | |
3183 | ||
3184 | /* Handles the MULS instruction. */ | |
3185 | ||
a78f21af | 3186 | static void |
29134980 OF |
3187 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3188 | { | |
3189 | /* MULS/U can't have a prefix. */ | |
3190 | if (inst_env->prefix_found) | |
3191 | { | |
3192 | inst_env->invalid = 1; | |
3193 | return; | |
3194 | } | |
3195 | ||
3196 | /* Consider it invalid if the PC is the target. */ | |
3197 | if (cris_get_operand2 (inst) == REG_PC) | |
3198 | { | |
3199 | inst_env->invalid = 1; | |
3200 | return; | |
3201 | } | |
3202 | inst_env->slot_needed = 0; | |
3203 | inst_env->prefix_found = 0; | |
3204 | inst_env->xflag_found = 0; | |
3205 | inst_env->disable_interrupt = 0; | |
3206 | } | |
3207 | ||
3208 | /* Handles the MULU instruction. */ | |
3209 | ||
a78f21af | 3210 | static void |
29134980 OF |
3211 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3212 | { | |
3213 | /* MULS/U can't have a prefix. */ | |
3214 | if (inst_env->prefix_found) | |
3215 | { | |
3216 | inst_env->invalid = 1; | |
3217 | return; | |
3218 | } | |
3219 | ||
3220 | /* Consider it invalid if the PC is the target. */ | |
3221 | if (cris_get_operand2 (inst) == REG_PC) | |
3222 | { | |
3223 | inst_env->invalid = 1; | |
3224 | return; | |
3225 | } | |
3226 | inst_env->slot_needed = 0; | |
3227 | inst_env->prefix_found = 0; | |
3228 | inst_env->xflag_found = 0; | |
3229 | inst_env->disable_interrupt = 0; | |
3230 | } | |
3231 | ||
3232 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3233 | The MOVE instruction is the move from source to register. */ | |
3234 | ||
a78f21af | 3235 | static void |
29134980 OF |
3236 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3237 | unsigned long source1, unsigned long source2) | |
3238 | { | |
3239 | unsigned long pc_mask; | |
3240 | unsigned long operation_mask; | |
3241 | ||
3242 | /* Find out how many bits the operation should apply to. */ | |
3243 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3244 | { | |
3245 | pc_mask = 0xFFFFFF00; | |
3246 | operation_mask = 0xFF; | |
3247 | } | |
3248 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3249 | { | |
3250 | pc_mask = 0xFFFF0000; | |
3251 | operation_mask = 0xFFFF; | |
3252 | } | |
3253 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3254 | { | |
3255 | pc_mask = 0x0; | |
3256 | operation_mask = 0xFFFFFFFF; | |
3257 | } | |
3258 | else | |
3259 | { | |
3260 | /* The size is out of range. */ | |
3261 | inst_env->invalid = 1; | |
3262 | return; | |
3263 | } | |
3264 | ||
3265 | /* The instruction just works on uw_operation_mask bits. */ | |
3266 | source2 &= operation_mask; | |
3267 | source1 &= operation_mask; | |
3268 | ||
3269 | /* Now calculate the result. The opcode's 3 first bits separates | |
3270 | the different actions. */ | |
3271 | switch (cris_get_opcode (inst) & 7) | |
3272 | { | |
3273 | case 0: /* add */ | |
3274 | source1 += source2; | |
3275 | break; | |
3276 | ||
3277 | case 1: /* move */ | |
3278 | source1 = source2; | |
3279 | break; | |
3280 | ||
3281 | case 2: /* subtract */ | |
3282 | source1 -= source2; | |
3283 | break; | |
3284 | ||
3285 | case 3: /* compare */ | |
3286 | break; | |
3287 | ||
3288 | case 4: /* and */ | |
3289 | source1 &= source2; | |
3290 | break; | |
3291 | ||
3292 | case 5: /* or */ | |
3293 | source1 |= source2; | |
3294 | break; | |
3295 | ||
3296 | default: | |
3297 | inst_env->invalid = 1; | |
3298 | return; | |
3299 | ||
3300 | break; | |
3301 | } | |
3302 | ||
3303 | /* Make sure that the result doesn't contain more than the instruction | |
3304 | size bits. */ | |
3305 | source2 &= operation_mask; | |
3306 | ||
3307 | /* Calculate the new breakpoint address. */ | |
3308 | inst_env->reg[REG_PC] &= pc_mask; | |
3309 | inst_env->reg[REG_PC] |= source1; | |
3310 | ||
3311 | } | |
3312 | ||
3313 | /* Extends the value from either byte or word size to a dword. If the mode | |
3314 | is zero extend then the value is extended with zero. If instead the mode | |
3315 | is signed extend the sign bit of the value is taken into consideration. */ | |
3316 | ||
a78f21af | 3317 | static unsigned long |
29134980 OF |
3318 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3319 | { | |
3320 | /* The size can be either byte or word, check which one it is. | |
3321 | Don't check the highest bit, it's indicating if it's a zero | |
3322 | or sign extend. */ | |
3323 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3324 | { | |
3325 | /* Word size. */ | |
3326 | value &= 0xFFFF; | |
3327 | ||
3328 | /* Check if the instruction is signed extend. If so, check if value has | |
3329 | the sign bit on. */ | |
3330 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3331 | { | |
3332 | value |= SIGNED_WORD_EXTEND_MASK; | |
3333 | } | |
3334 | } | |
3335 | else | |
3336 | { | |
3337 | /* Byte size. */ | |
3338 | value &= 0xFF; | |
3339 | ||
3340 | /* Check if the instruction is signed extend. If so, check if value has | |
3341 | the sign bit on. */ | |
3342 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3343 | { | |
3344 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3345 | } | |
3346 | } | |
3347 | /* The size should now be dword. */ | |
3348 | cris_set_size_to_dword (inst); | |
3349 | return value; | |
3350 | } | |
3351 | ||
3352 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3353 | instruction. The MOVE instruction is the move from source to register. */ | |
3354 | ||
a78f21af | 3355 | static void |
29134980 OF |
3356 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3357 | inst_env_type *inst_env) | |
3358 | { | |
3359 | unsigned long operand1; | |
3360 | unsigned long operand2; | |
3361 | ||
3362 | /* It's invalid to have a prefix to the instruction. This is a register | |
3363 | mode instruction and can't have a prefix. */ | |
3364 | if (inst_env->prefix_found) | |
3365 | { | |
3366 | inst_env->invalid = 1; | |
3367 | return; | |
3368 | } | |
3369 | /* Check if the instruction has PC as its target. */ | |
3370 | if (cris_get_operand2 (inst) == REG_PC) | |
3371 | { | |
3372 | if (inst_env->slot_needed) | |
3373 | { | |
3374 | inst_env->invalid = 1; | |
3375 | return; | |
3376 | } | |
3377 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3378 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3379 | operand2 = inst_env->reg[REG_PC]; |
3380 | ||
3381 | /* Check if it's a extend, signed or zero instruction. */ | |
3382 | if (cris_get_opcode (inst) < 4) | |
3383 | { | |
3384 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3385 | } | |
3386 | /* Calculate the PC value after the instruction, i.e. where the | |
3387 | breakpoint should be. The order of the udw_operands is vital. */ | |
3388 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3389 | } | |
3390 | inst_env->slot_needed = 0; | |
3391 | inst_env->prefix_found = 0; | |
3392 | inst_env->xflag_found = 0; | |
3393 | inst_env->disable_interrupt = 0; | |
3394 | } | |
3395 | ||
3396 | /* Returns the data contained at address. The size of the data is derived from | |
3397 | the size of the operation. If the instruction is a zero or signed | |
3398 | extend instruction, the size field is changed in instruction. */ | |
3399 | ||
a78f21af | 3400 | static unsigned long |
29134980 OF |
3401 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3402 | { | |
3403 | int size = cris_get_size (*inst); | |
3404 | unsigned long value; | |
3405 | ||
3406 | /* If it's an extend instruction we don't want the signed extend bit, | |
3407 | because it influences the size. */ | |
3408 | if (cris_get_opcode (*inst) < 4) | |
3409 | { | |
3410 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3411 | } | |
3412 | /* Is there a need for checking the size? Size should contain the number of | |
3413 | bytes to read. */ | |
3414 | size = 1 << size; | |
3415 | value = read_memory_unsigned_integer (address, size); | |
3416 | ||
3417 | /* Check if it's an extend, signed or zero instruction. */ | |
3418 | if (cris_get_opcode (*inst) < 4) | |
3419 | { | |
3420 | value = do_sign_or_zero_extend (value, inst); | |
3421 | } | |
3422 | return value; | |
3423 | } | |
3424 | ||
3425 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3426 | instructions. The MOVE instruction is the move from source to register. */ | |
3427 | ||
a78f21af | 3428 | static void |
29134980 OF |
3429 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3430 | inst_env_type *inst_env) | |
3431 | { | |
3432 | unsigned long operand2; | |
3433 | unsigned long operand3; | |
3434 | ||
3435 | check_assign (inst, inst_env); | |
3436 | if (cris_get_operand2 (inst) == REG_PC) | |
3437 | { | |
3438 | operand2 = inst_env->reg[REG_PC]; | |
3439 | ||
3440 | /* Get the value of the third operand. */ | |
3441 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3442 | ||
3443 | /* Calculate the PC value after the instruction, i.e. where the | |
3444 | breakpoint should be. The order of the udw_operands is vital. */ | |
3445 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3446 | } | |
3447 | inst_env->slot_needed = 0; | |
3448 | inst_env->prefix_found = 0; | |
3449 | inst_env->xflag_found = 0; | |
3450 | inst_env->disable_interrupt = 0; | |
3451 | } | |
3452 | ||
3453 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3454 | OR instructions. Note that for this to work as expected, the calling | |
3455 | function must have made sure that there is a prefix to this instruction. */ | |
3456 | ||
a78f21af | 3457 | static void |
29134980 OF |
3458 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3459 | inst_env_type *inst_env) | |
3460 | { | |
3461 | unsigned long operand2; | |
3462 | unsigned long operand3; | |
3463 | ||
3464 | if (cris_get_operand1 (inst) == REG_PC) | |
3465 | { | |
3466 | /* The PC will be changed by the instruction. */ | |
3467 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3468 | ||
3469 | /* Get the value of the third operand. */ | |
3470 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3471 | ||
3472 | /* Calculate the PC value after the instruction, i.e. where the | |
3473 | breakpoint should be. */ | |
3474 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3475 | } | |
3476 | inst_env->slot_needed = 0; | |
3477 | inst_env->prefix_found = 0; | |
3478 | inst_env->xflag_found = 0; | |
3479 | inst_env->disable_interrupt = 0; | |
3480 | } | |
3481 | ||
3482 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3483 | instructions. The MOVE instruction is the move from source to register. */ | |
3484 | ||
a78f21af | 3485 | static void |
29134980 OF |
3486 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3487 | inst_env_type *inst_env) | |
3488 | { | |
3489 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3490 | { | |
3491 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3492 | SUB, AND or OR something weird is going on (if everything works these | |
3493 | instructions should end up in the three operand version). */ | |
3494 | inst_env->invalid = 1; | |
3495 | return; | |
3496 | } | |
3497 | else | |
3498 | { | |
3499 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3500 | so use it. */ | |
3501 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3502 | } | |
3503 | inst_env->slot_needed = 0; | |
3504 | inst_env->prefix_found = 0; | |
3505 | inst_env->xflag_found = 0; | |
3506 | inst_env->disable_interrupt = 0; | |
3507 | } | |
3508 | ||
3509 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3510 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3511 | source to register. */ | |
3512 | ||
a78f21af | 3513 | static void |
29134980 OF |
3514 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3515 | inst_env_type *inst_env) | |
3516 | { | |
3517 | unsigned long operand1; | |
3518 | unsigned long operand2; | |
3519 | unsigned long operand3; | |
3520 | int size; | |
3521 | ||
3522 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3523 | Check if the destination register is the PC. */ | |
3524 | if (cris_get_operand2 (inst) == REG_PC) | |
3525 | { | |
3526 | /* Must be done here, get_data_from_address may change the size | |
3527 | field. */ | |
3528 | size = cris_get_size (inst); | |
3529 | operand2 = inst_env->reg[REG_PC]; | |
3530 | ||
3531 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3532 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3533 | operand3 = get_data_from_address (&inst, operand1); | |
3534 | ||
3535 | /* Calculate the PC value after the instruction, i.e. where the | |
3536 | breakpoint should be. The order of the udw_operands is vital. */ | |
3537 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3538 | } | |
3539 | /* If this is an autoincrement addressing mode, check if the increment | |
3540 | changes the PC. */ | |
3541 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3542 | { | |
3543 | /* Get the size field. */ | |
3544 | size = cris_get_size (inst); | |
3545 | ||
3546 | /* If it's an extend instruction we don't want the signed extend bit, | |
3547 | because it influences the size. */ | |
3548 | if (cris_get_opcode (inst) < 4) | |
3549 | { | |
3550 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3551 | } | |
3552 | process_autoincrement (size, inst, inst_env); | |
3553 | } | |
3554 | inst_env->slot_needed = 0; | |
3555 | inst_env->prefix_found = 0; | |
3556 | inst_env->xflag_found = 0; | |
3557 | inst_env->disable_interrupt = 0; | |
3558 | } | |
3559 | ||
3560 | /* Handles the two-operand addressing mode, all modes except register, for | |
3561 | the ADD, SUB CMP, AND and OR instruction. */ | |
3562 | ||
a78f21af | 3563 | static void |
29134980 OF |
3564 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3565 | inst_env_type *inst_env) | |
3566 | { | |
3567 | if (inst_env->prefix_found) | |
3568 | { | |
3569 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3570 | { | |
3571 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3572 | } | |
3573 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3574 | { | |
3575 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3576 | } | |
3577 | else | |
3578 | { | |
3579 | /* The mode is invalid for a prefixed base instruction. */ | |
3580 | inst_env->invalid = 1; | |
3581 | return; | |
3582 | } | |
3583 | } | |
3584 | else | |
3585 | { | |
3586 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3587 | } | |
3588 | } | |
3589 | ||
3590 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3591 | ||
a78f21af | 3592 | static void |
29134980 OF |
3593 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3594 | { | |
3595 | unsigned long operand1; | |
3596 | unsigned long operand2; | |
3597 | ||
3598 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3599 | instruction and can't have a prefix. */ | |
3600 | if (inst_env->prefix_found) | |
3601 | { | |
3602 | inst_env->invalid = 1; | |
3603 | return; | |
3604 | } | |
3605 | ||
3606 | /* Check if the instruction has PC as its target. */ | |
3607 | if (cris_get_operand2 (inst) == REG_PC) | |
3608 | { | |
3609 | if (inst_env->slot_needed) | |
3610 | { | |
3611 | inst_env->invalid = 1; | |
3612 | return; | |
3613 | } | |
3614 | operand1 = cris_get_quick_value (inst); | |
3615 | operand2 = inst_env->reg[REG_PC]; | |
3616 | ||
3617 | /* The size should now be dword. */ | |
3618 | cris_set_size_to_dword (&inst); | |
3619 | ||
3620 | /* Calculate the PC value after the instruction, i.e. where the | |
3621 | breakpoint should be. */ | |
3622 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3623 | } | |
3624 | inst_env->slot_needed = 0; | |
3625 | inst_env->prefix_found = 0; | |
3626 | inst_env->xflag_found = 0; | |
3627 | inst_env->disable_interrupt = 0; | |
3628 | } | |
3629 | ||
3630 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3631 | ||
a78f21af | 3632 | static void |
29134980 OF |
3633 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3634 | { | |
3635 | unsigned long operand1; | |
3636 | unsigned long operand2; | |
3637 | ||
3638 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3639 | instruction and can't have a prefix. */ | |
3640 | if (inst_env->prefix_found) | |
3641 | { | |
3642 | inst_env->invalid = 1; | |
3643 | return; | |
3644 | } | |
3645 | /* Check if the instruction has PC as its target. */ | |
3646 | if (cris_get_operand2 (inst) == REG_PC) | |
3647 | { | |
3648 | if (inst_env->slot_needed) | |
3649 | { | |
3650 | inst_env->invalid = 1; | |
3651 | return; | |
3652 | } | |
3653 | /* The instruction has the PC as its target register. */ | |
3654 | operand1 = cris_get_quick_value (inst); | |
3655 | operand2 = inst_env->reg[REG_PC]; | |
3656 | ||
3657 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3658 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3659 | { | |
3660 | /* sign extend */ | |
3661 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3662 | } | |
3663 | /* The size should now be dword. */ | |
3664 | cris_set_size_to_dword (&inst); | |
3665 | ||
3666 | /* Calculate the PC value after the instruction, i.e. where the | |
3667 | breakpoint should be. */ | |
3668 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3669 | } | |
3670 | inst_env->slot_needed = 0; | |
3671 | inst_env->prefix_found = 0; | |
3672 | inst_env->xflag_found = 0; | |
3673 | inst_env->disable_interrupt = 0; | |
3674 | } | |
3675 | ||
3676 | /* Translate op_type to a function and call it. */ | |
3677 | ||
a78f21af AC |
3678 | static void |
3679 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3680 | inst_env_type *inst_env) | |
29134980 OF |
3681 | { |
3682 | switch (op_type) | |
3683 | { | |
3684 | case cris_not_implemented_op: | |
3685 | not_implemented_op (inst, inst_env); | |
3686 | break; | |
3687 | ||
3688 | case cris_abs_op: | |
3689 | abs_op (inst, inst_env); | |
3690 | break; | |
3691 | ||
3692 | case cris_addi_op: | |
3693 | addi_op (inst, inst_env); | |
3694 | break; | |
3695 | ||
3696 | case cris_asr_op: | |
3697 | asr_op (inst, inst_env); | |
3698 | break; | |
3699 | ||
3700 | case cris_asrq_op: | |
3701 | asrq_op (inst, inst_env); | |
3702 | break; | |
3703 | ||
3704 | case cris_ax_ei_setf_op: | |
3705 | ax_ei_setf_op (inst, inst_env); | |
3706 | break; | |
3707 | ||
3708 | case cris_bdap_prefix: | |
3709 | bdap_prefix (inst, inst_env); | |
3710 | break; | |
3711 | ||
3712 | case cris_biap_prefix: | |
3713 | biap_prefix (inst, inst_env); | |
3714 | break; | |
3715 | ||
3716 | case cris_break_op: | |
3717 | break_op (inst, inst_env); | |
3718 | break; | |
3719 | ||
3720 | case cris_btst_nop_op: | |
3721 | btst_nop_op (inst, inst_env); | |
3722 | break; | |
3723 | ||
3724 | case cris_clearf_di_op: | |
3725 | clearf_di_op (inst, inst_env); | |
3726 | break; | |
3727 | ||
3728 | case cris_dip_prefix: | |
3729 | dip_prefix (inst, inst_env); | |
3730 | break; | |
3731 | ||
3732 | case cris_dstep_logshift_mstep_neg_not_op: | |
3733 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3734 | break; | |
3735 | ||
3736 | case cris_eight_bit_offset_branch_op: | |
3737 | eight_bit_offset_branch_op (inst, inst_env); | |
3738 | break; | |
3739 | ||
3740 | case cris_move_mem_to_reg_movem_op: | |
3741 | move_mem_to_reg_movem_op (inst, inst_env); | |
3742 | break; | |
3743 | ||
3744 | case cris_move_reg_to_mem_movem_op: | |
3745 | move_reg_to_mem_movem_op (inst, inst_env); | |
3746 | break; | |
3747 | ||
3748 | case cris_move_to_preg_op: | |
3749 | move_to_preg_op (inst, inst_env); | |
3750 | break; | |
3751 | ||
3752 | case cris_muls_op: | |
3753 | muls_op (inst, inst_env); | |
3754 | break; | |
3755 | ||
3756 | case cris_mulu_op: | |
3757 | mulu_op (inst, inst_env); | |
3758 | break; | |
3759 | ||
3760 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3761 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3762 | break; | |
3763 | ||
3764 | case cris_none_reg_mode_clear_test_op: | |
3765 | none_reg_mode_clear_test_op (inst, inst_env); | |
3766 | break; | |
3767 | ||
3768 | case cris_none_reg_mode_jump_op: | |
3769 | none_reg_mode_jump_op (inst, inst_env); | |
3770 | break; | |
3771 | ||
3772 | case cris_none_reg_mode_move_from_preg_op: | |
3773 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3774 | break; | |
3775 | ||
3776 | case cris_quick_mode_add_sub_op: | |
3777 | quick_mode_add_sub_op (inst, inst_env); | |
3778 | break; | |
3779 | ||
3780 | case cris_quick_mode_and_cmp_move_or_op: | |
3781 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3782 | break; | |
3783 | ||
3784 | case cris_quick_mode_bdap_prefix: | |
3785 | quick_mode_bdap_prefix (inst, inst_env); | |
3786 | break; | |
3787 | ||
3788 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3789 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3790 | break; | |
3791 | ||
3792 | case cris_reg_mode_clear_op: | |
3793 | reg_mode_clear_op (inst, inst_env); | |
3794 | break; | |
3795 | ||
3796 | case cris_reg_mode_jump_op: | |
3797 | reg_mode_jump_op (inst, inst_env); | |
3798 | break; | |
3799 | ||
3800 | case cris_reg_mode_move_from_preg_op: | |
3801 | reg_mode_move_from_preg_op (inst, inst_env); | |
3802 | break; | |
3803 | ||
3804 | case cris_reg_mode_test_op: | |
3805 | reg_mode_test_op (inst, inst_env); | |
3806 | break; | |
3807 | ||
3808 | case cris_scc_op: | |
3809 | scc_op (inst, inst_env); | |
3810 | break; | |
3811 | ||
3812 | case cris_sixteen_bit_offset_branch_op: | |
3813 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3814 | break; | |
3815 | ||
3816 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3817 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3818 | break; | |
3819 | ||
3820 | case cris_three_operand_bound_op: | |
3821 | three_operand_bound_op (inst, inst_env); | |
3822 | break; | |
3823 | ||
3824 | case cris_two_operand_bound_op: | |
3825 | two_operand_bound_op (inst, inst_env); | |
3826 | break; | |
3827 | ||
3828 | case cris_xor_op: | |
3829 | xor_op (inst, inst_env); | |
3830 | break; | |
3831 | } | |
3832 | } | |
3833 | ||
3834 | /* This wrapper is to avoid cris_get_assembler being called before | |
3835 | exec_bfd has been set. */ | |
3836 | ||
3837 | static int | |
a89aa300 | 3838 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3839 | { |
a89aa300 | 3840 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3841 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3842 | disassembler, even when there is no BFD. Does something like | |
3843 | "gdb; target remote; disassmeble *0x123" work? */ | |
3844 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3845 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3846 | gdb_assert (print_insn != NULL); |
3847 | return print_insn (addr, info); | |
29134980 OF |
3848 | } |
3849 | ||
dbbff683 OF |
3850 | /* Copied from <asm/elf.h>. */ |
3851 | typedef unsigned long elf_greg_t; | |
3852 | ||
3853 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3854 | #define CRISV10_ELF_NGREG 35 |
3855 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3856 | ||
3857 | #define CRISV32_ELF_NGREG 32 | |
3858 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3859 | |
3860 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3861 | ||
a78f21af | 3862 | static void |
c6b4e5a2 | 3863 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
dbbff683 | 3864 | { |
c600d464 | 3865 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3866 | int i; |
3867 | elf_greg_t *regp = *gregsetp; | |
3868 | static char zerobuf[4] = {0}; | |
3869 | ||
3870 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3871 | knows about the actual size of each register so that's no problem. */ | |
3872 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3873 | { | |
c6b4e5a2 | 3874 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
dbbff683 | 3875 | } |
c600d464 OF |
3876 | |
3877 | if (tdep->cris_version == 32) | |
3878 | { | |
3879 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3880 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3881 | be wrong. Issue a warning to alert the user. */ | |
c6b4e5a2 | 3882 | regcache_raw_supply (regcache, PC_REGNUM, |
c600d464 OF |
3883 | (char *)®p[ERP_REGNUM]); |
3884 | ||
3885 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3886 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3887 | } | |
dbbff683 OF |
3888 | } |
3889 | ||
3890 | /* Use a local version of this function to get the correct types for | |
3891 | regsets, until multi-arch core support is ready. */ | |
3892 | ||
3893 | static void | |
9eefc95f UW |
3894 | fetch_core_registers (struct regcache *regcache, |
3895 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3896 | int which, CORE_ADDR reg_addr) |
3897 | { | |
3898 | elf_gregset_t gregset; | |
3899 | ||
3900 | switch (which) | |
3901 | { | |
3902 | case 0: | |
c600d464 OF |
3903 | if (core_reg_size != sizeof (elf_gregset_t) |
3904 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3905 | { |
8a3fe4f8 | 3906 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3907 | } |
3908 | else | |
3909 | { | |
3910 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3911 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3912 | } |
3913 | ||
3914 | default: | |
3915 | /* We've covered all the kinds of registers we know about here, | |
3916 | so this must be something we wouldn't know what to do with | |
3917 | anyway. Just ignore it. */ | |
3918 | break; | |
3919 | } | |
3920 | } | |
3921 | ||
3922 | static struct core_fns cris_elf_core_fns = | |
3923 | { | |
3924 | bfd_target_elf_flavour, /* core_flavour */ | |
3925 | default_check_format, /* check_format */ | |
3926 | default_core_sniffer, /* core_sniffer */ | |
3927 | fetch_core_registers, /* core_read_registers */ | |
3928 | NULL /* next */ | |
3929 | }; | |
3930 | ||
a78f21af AC |
3931 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3932 | ||
29134980 OF |
3933 | void |
3934 | _initialize_cris_tdep (void) | |
3935 | { | |
a5f6c8f5 OF |
3936 | static struct cmd_list_element *cris_set_cmdlist; |
3937 | static struct cmd_list_element *cris_show_cmdlist; | |
3938 | ||
29134980 OF |
3939 | struct cmd_list_element *c; |
3940 | ||
3941 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3942 | ||
29134980 | 3943 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3944 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3945 | &usr_cmd_cris_version, | |
7915a72c AC |
3946 | _("Set the current CRIS version."), |
3947 | _("Show the current CRIS version."), | |
bdd56253 OF |
3948 | _("\ |
3949 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3950 | Defaults to 10. "), | |
2c5b56ce | 3951 | set_cris_version, |
7915a72c | 3952 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3953 | &setlist, &showlist); |
0e6bdb31 OF |
3954 | |
3955 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3956 | cris_modes, &usr_cmd_cris_mode, | |
3957 | _("Set the current CRIS mode."), | |
3958 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3959 | _("\ |
3960 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3961 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3962 | set_cris_mode, |
3963 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3964 | &setlist, &showlist); | |
dbbff683 | 3965 | |
a5f6c8f5 OF |
3966 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3967 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3968 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3969 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3970 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3971 | set_cris_dwarf2_cfi, |
7915a72c | 3972 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3973 | &setlist, &showlist); |
3974 | ||
52bd1401 | 3975 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3976 | } |
3977 | ||
3978 | /* Prints out all target specific values. */ | |
3979 | ||
3980 | static void | |
3981 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3982 | { | |
3983 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3984 | if (tdep != NULL) | |
3985 | { | |
3986 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3987 | tdep->cris_version); | |
0e6bdb31 OF |
3988 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
3989 | tdep->cris_mode); | |
a5f6c8f5 OF |
3990 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
3991 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3992 | } |
3993 | } | |
3994 | ||
3995 | static void | |
a5f6c8f5 OF |
3996 | set_cris_version (char *ignore_args, int from_tty, |
3997 | struct cmd_list_element *c) | |
29134980 OF |
3998 | { |
3999 | struct gdbarch_info info; | |
4000 | ||
a5f6c8f5 | 4001 | usr_cmd_cris_version_valid = 1; |
29134980 | 4002 | |
a5f6c8f5 OF |
4003 | /* Update the current architecture, if needed. */ |
4004 | gdbarch_info_init (&info); | |
4005 | if (!gdbarch_update_p (info)) | |
4006 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4007 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4008 | } |
4009 | ||
0e6bdb31 OF |
4010 | static void |
4011 | set_cris_mode (char *ignore_args, int from_tty, | |
4012 | struct cmd_list_element *c) | |
4013 | { | |
4014 | struct gdbarch_info info; | |
4015 | ||
4016 | /* Update the current architecture, if needed. */ | |
4017 | gdbarch_info_init (&info); | |
4018 | if (!gdbarch_update_p (info)) | |
4019 | internal_error (__FILE__, __LINE__, | |
4020 | "cris_gdbarch_update: failed to update architecture."); | |
4021 | } | |
4022 | ||
29134980 | 4023 | static void |
a5f6c8f5 OF |
4024 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4025 | struct cmd_list_element *c) | |
29134980 OF |
4026 | { |
4027 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4028 | |
4029 | /* Update the current architecture, if needed. */ | |
4030 | gdbarch_info_init (&info); | |
4031 | if (!gdbarch_update_p (info)) | |
4032 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4033 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4034 | } |
4035 | ||
29134980 OF |
4036 | static struct gdbarch * |
4037 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4038 | { | |
4039 | struct gdbarch *gdbarch; | |
4040 | struct gdbarch_tdep *tdep; | |
4041 | int cris_version; | |
29134980 OF |
4042 | |
4043 | if (usr_cmd_cris_version_valid) | |
4044 | { | |
4045 | /* Trust the user's CRIS version setting. */ | |
4046 | cris_version = usr_cmd_cris_version; | |
4047 | } | |
c600d464 OF |
4048 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4049 | { | |
4050 | cris_version = 32; | |
4051 | } | |
29134980 OF |
4052 | else |
4053 | { | |
4054 | /* Assume it's CRIS version 10. */ | |
4055 | cris_version = 10; | |
4056 | } | |
4057 | ||
29134980 OF |
4058 | /* Make the current settings visible to the user. */ |
4059 | usr_cmd_cris_version = cris_version; | |
29134980 | 4060 | |
0e6bdb31 | 4061 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4062 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4063 | arches != NULL; | |
4064 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4065 | { | |
a5f6c8f5 OF |
4066 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4067 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4068 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4069 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4070 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4071 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4072 | return arches->gdbarch; |
4073 | } | |
4074 | ||
4075 | /* No matching architecture was found. Create a new one. */ | |
4076 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4077 | gdbarch = gdbarch_alloc (&info, tdep); | |
4078 | ||
a5f6c8f5 | 4079 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4080 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4081 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4082 | |
4083 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4084 | switch (info.byte_order) | |
4085 | { | |
778eb05e | 4086 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4087 | /* Ok. */ |
4088 | break; | |
4089 | ||
d7449b42 | 4090 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4091 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4092 | break; |
4093 | ||
4094 | default: | |
e2e0b3e5 | 4095 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4096 | } |
4097 | ||
b4206d25 | 4098 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4099 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4100 | cris_reg_struct_has_addr); | |
b5622e8d | 4101 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4102 | |
29134980 | 4103 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4104 | |
4105 | /* Length of ordinary registers used in push_word and a few other | |
4106 | places. register_size() is the real way to know how big a | |
4107 | register is. */ | |
a5f6c8f5 | 4108 | |
2e4b5889 OF |
4109 | set_gdbarch_double_bit (gdbarch, 64); |
4110 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
4111 | which means we have to set this explicitly. */ | |
c600d464 | 4112 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4113 | |
29134980 OF |
4114 | /* The total amount of space needed to store (in an array called registers) |
4115 | GDB's copy of the machine's register state. Note: We can not use | |
4116 | cris_register_size at this point, since it relies on current_gdbarch | |
4117 | being set. */ | |
4118 | switch (tdep->cris_version) | |
4119 | { | |
4120 | case 0: | |
4121 | case 1: | |
4122 | case 2: | |
4123 | case 3: | |
29134980 OF |
4124 | case 8: |
4125 | case 9: | |
a5f6c8f5 OF |
4126 | /* Old versions; not supported. */ |
4127 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4128 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4129 | break; |
4130 | ||
4131 | case 10: | |
4132 | case 11: | |
4133 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4134 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4135 | set_gdbarch_pc_regnum (gdbarch, 15); |
4136 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4137 | /* There are 32 registers (some of which may not be implemented). */ | |
4138 | set_gdbarch_num_regs (gdbarch, 32); | |
4139 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4140 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4141 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4142 | ||
4143 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4144 | break; | |
4145 | ||
4146 | case 32: | |
4147 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4148 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4149 | and pseudo-register PC (32 bits). */ | |
4150 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4151 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4152 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4153 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4154 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4155 | ||
4156 | set_gdbarch_cannot_store_register | |
4157 | (gdbarch, crisv32_cannot_store_register); | |
4158 | set_gdbarch_cannot_fetch_register | |
4159 | (gdbarch, crisv32_cannot_fetch_register); | |
4160 | ||
4161 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4162 | ||
4163 | set_gdbarch_single_step_through_delay | |
4164 | (gdbarch, crisv32_single_step_through_delay); | |
4165 | ||
29134980 OF |
4166 | break; |
4167 | ||
4168 | default: | |
c600d464 | 4169 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4170 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4171 | } |
4172 | ||
c600d464 OF |
4173 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4174 | have the same ABI). */ | |
2e4b5889 OF |
4175 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4176 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4177 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4178 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4179 | |
4180 | /* The stack grows downward. */ | |
4181 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4182 | ||
4183 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4184 | ||
2e4b5889 OF |
4185 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4186 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4187 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4188 | ||
a5f6c8f5 OF |
4189 | if (tdep->cris_dwarf2_cfi == 1) |
4190 | { | |
4191 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4192 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4193 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4194 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4195 | } | |
4196 | ||
0e6bdb31 OF |
4197 | if (tdep->cris_mode != cris_mode_guru) |
4198 | { | |
4199 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4200 | } | |
a5f6c8f5 | 4201 | |
2e4b5889 OF |
4202 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4203 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4204 | |
76a9d10f MK |
4205 | set_solib_svr4_fetch_link_map_offsets |
4206 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
dbbff683 | 4207 | |
36482093 AC |
4208 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4209 | disassembler, even when there is no BFD. Does something like | |
4210 | "gdb; target remote; disassmeble *0x123" work? */ | |
4211 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4212 | ||
29134980 OF |
4213 | return gdbarch; |
4214 | } |