Commit | Line | Data |
---|---|---|
29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 AC |
2 | |
3 | Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. | |
4 | ||
29134980 OF |
5 | Contributed by Axis Communications AB. |
6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
7 | ||
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
2e4b5889 OF |
26 | #include "frame-unwind.h" |
27 | #include "frame-base.h" | |
28 | #include "trad-frame.h" | |
29 | #include "dwarf2-frame.h" | |
29134980 OF |
30 | #include "symtab.h" |
31 | #include "inferior.h" | |
32 | #include "gdbtypes.h" | |
33 | #include "gdbcore.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "target.h" | |
36 | #include "value.h" | |
37 | #include "opcode/cris.h" | |
38 | #include "arch-utils.h" | |
39 | #include "regcache.h" | |
36482093 | 40 | #include "gdb_assert.h" |
29134980 OF |
41 | |
42 | /* To get entry_point_address. */ | |
9ab9195f | 43 | #include "objfiles.h" |
29134980 | 44 | |
dbbff683 OF |
45 | #include "solib.h" /* Support for shared libraries. */ |
46 | #include "solib-svr4.h" /* For struct link_map_offsets. */ | |
9bbe19fb | 47 | #include "gdb_string.h" |
a89aa300 | 48 | #include "dis-asm.h" |
dbbff683 OF |
49 | |
50 | ||
29134980 OF |
51 | enum cris_num_regs |
52 | { | |
53 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
54 | NUM_FREGS = 0, | |
55 | ||
56 | /* There are 16 general registers. */ | |
57 | NUM_GENREGS = 16, | |
58 | ||
59 | /* There are 16 special registers. */ | |
60 | NUM_SPECREGS = 16 | |
61 | }; | |
62 | ||
63 | /* Register numbers of various important registers. | |
2e4b5889 | 64 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
65 | STR_REGNUM Contains the address of structure return values. |
66 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
67 | ARG1_REGNUM Contains the first parameter to a function. | |
68 | ARG2_REGNUM Contains the second parameter to a function. | |
69 | ARG3_REGNUM Contains the third parameter to a function. | |
70 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
71 | SP_REGNUM Contains address of top of stack. | |
72 | PC_REGNUM Contains address of next instruction. | |
73 | SRP_REGNUM Subroutine return pointer register. | |
74 | BRP_REGNUM Breakpoint return pointer register. */ | |
75 | ||
29134980 OF |
76 | enum cris_regnums |
77 | { | |
78 | /* Enums with respect to the general registers, valid for all | |
79 | CRIS versions. */ | |
2e4b5889 | 80 | CRIS_FP_REGNUM = 8, |
29134980 OF |
81 | STR_REGNUM = 9, |
82 | RET_REGNUM = 10, | |
83 | ARG1_REGNUM = 10, | |
84 | ARG2_REGNUM = 11, | |
85 | ARG3_REGNUM = 12, | |
86 | ARG4_REGNUM = 13, | |
87 | ||
88 | /* Enums with respect to the special registers, some of which may not be | |
89 | applicable to all CRIS versions. */ | |
90 | P0_REGNUM = 16, | |
91 | VR_REGNUM = 17, | |
92 | P2_REGNUM = 18, | |
93 | P3_REGNUM = 19, | |
94 | P4_REGNUM = 20, | |
95 | CCR_REGNUM = 21, | |
96 | MOF_REGNUM = 23, | |
97 | P8_REGNUM = 24, | |
98 | IBR_REGNUM = 25, | |
99 | IRP_REGNUM = 26, | |
100 | SRP_REGNUM = 27, | |
101 | BAR_REGNUM = 28, | |
2a9ecef2 | 102 | DCCR_REGNUM = 29, |
29134980 OF |
103 | BRP_REGNUM = 30, |
104 | USP_REGNUM = 31 | |
105 | }; | |
106 | ||
107 | extern const struct cris_spec_reg cris_spec_regs[]; | |
108 | ||
109 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
110 | register names and sizes.*/ | |
111 | static int usr_cmd_cris_version; | |
112 | ||
113 | /* Indicates whether to trust the above variable. */ | |
114 | static int usr_cmd_cris_version_valid = 0; | |
115 | ||
116 | /* CRIS mode, set via the user command 'set cris-mode'. Affects availability | |
117 | of some registers. */ | |
118 | static const char *usr_cmd_cris_mode; | |
119 | ||
120 | /* Indicates whether to trust the above variable. */ | |
121 | static int usr_cmd_cris_mode_valid = 0; | |
122 | ||
123 | static const char CRIS_MODE_USER[] = "CRIS_MODE_USER"; | |
124 | static const char CRIS_MODE_SUPERVISOR[] = "CRIS_MODE_SUPERVISOR"; | |
125 | static const char *cris_mode_enums[] = | |
126 | { | |
127 | CRIS_MODE_USER, | |
128 | CRIS_MODE_SUPERVISOR, | |
129 | 0 | |
130 | }; | |
131 | ||
29134980 OF |
132 | /* CRIS architecture specific information. */ |
133 | struct gdbarch_tdep | |
134 | { | |
135 | int cris_version; | |
136 | const char *cris_mode; | |
29134980 OF |
137 | }; |
138 | ||
139 | /* Functions for accessing target dependent data. */ | |
140 | ||
141 | static int | |
142 | cris_version (void) | |
143 | { | |
144 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
145 | } | |
146 | ||
147 | static const char * | |
148 | cris_mode (void) | |
149 | { | |
150 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
151 | } | |
152 | ||
2e4b5889 | 153 | struct cris_unwind_cache |
29134980 | 154 | { |
2e4b5889 OF |
155 | /* The previous frame's inner most stack address. Used as this |
156 | frame ID's stack_addr. */ | |
157 | CORE_ADDR prev_sp; | |
158 | /* The frame's base, optionally used by the high-level debug info. */ | |
159 | CORE_ADDR base; | |
160 | int size; | |
161 | /* How far the SP and r8 (FP) have been offset from the start of | |
162 | the stack frame (as defined by the previous frame's stack | |
163 | pointer). */ | |
164 | LONGEST sp_offset; | |
165 | LONGEST r8_offset; | |
166 | int uses_frame; | |
167 | ||
168 | /* From old frame_extra_info struct. */ | |
29134980 OF |
169 | CORE_ADDR return_pc; |
170 | int leaf_function; | |
2e4b5889 OF |
171 | |
172 | /* Table indicating the location of each and every register. */ | |
173 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
174 | }; |
175 | ||
176 | /* The instruction environment needed to find single-step breakpoints. */ | |
177 | typedef | |
178 | struct instruction_environment | |
179 | { | |
180 | unsigned long reg[NUM_GENREGS]; | |
181 | unsigned long preg[NUM_SPECREGS]; | |
182 | unsigned long branch_break_address; | |
183 | unsigned long delay_slot_pc; | |
184 | unsigned long prefix_value; | |
185 | int branch_found; | |
186 | int prefix_found; | |
187 | int invalid; | |
188 | int slot_needed; | |
189 | int delay_slot_pc_active; | |
190 | int xflag_found; | |
191 | int disable_interrupt; | |
192 | } inst_env_type; | |
193 | ||
194 | /* Save old breakpoints in order to restore the state before a single_step. | |
195 | At most, two breakpoints will have to be remembered. */ | |
196 | typedef | |
197 | char binsn_quantum[BREAKPOINT_MAX]; | |
198 | static binsn_quantum break_mem[2]; | |
199 | static CORE_ADDR next_pc = 0; | |
200 | static CORE_ADDR branch_target_address = 0; | |
201 | static unsigned char branch_break_inserted = 0; | |
202 | ||
203 | /* Machine-dependencies in CRIS for opcodes. */ | |
204 | ||
205 | /* Instruction sizes. */ | |
206 | enum cris_instruction_sizes | |
207 | { | |
208 | INST_BYTE_SIZE = 0, | |
209 | INST_WORD_SIZE = 1, | |
210 | INST_DWORD_SIZE = 2 | |
211 | }; | |
212 | ||
213 | /* Addressing modes. */ | |
214 | enum cris_addressing_modes | |
215 | { | |
216 | REGISTER_MODE = 1, | |
217 | INDIRECT_MODE = 2, | |
218 | AUTOINC_MODE = 3 | |
219 | }; | |
220 | ||
221 | /* Prefix addressing modes. */ | |
222 | enum cris_prefix_addressing_modes | |
223 | { | |
224 | PREFIX_INDEX_MODE = 2, | |
225 | PREFIX_ASSIGN_MODE = 3, | |
226 | ||
227 | /* Handle immediate byte offset addressing mode prefix format. */ | |
228 | PREFIX_OFFSET_MODE = 2 | |
229 | }; | |
230 | ||
231 | /* Masks for opcodes. */ | |
232 | enum cris_opcode_masks | |
233 | { | |
234 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
235 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
236 | SIGNED_BYTE_MASK = 0x80, | |
237 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
238 | SIGNED_WORD_MASK = 0x8000, | |
239 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
240 | SIGNED_DWORD_MASK = 0x80000000, | |
241 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
242 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
243 | }; | |
244 | ||
245 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
246 | Bit 15 - 12 Operand2 | |
247 | 11 - 10 Mode | |
248 | 9 - 6 Opcode | |
249 | 5 - 4 Size | |
250 | 3 - 0 Operand1 */ | |
251 | ||
252 | static int | |
253 | cris_get_operand2 (unsigned short insn) | |
254 | { | |
255 | return ((insn & 0xF000) >> 12); | |
256 | } | |
257 | ||
258 | static int | |
259 | cris_get_mode (unsigned short insn) | |
260 | { | |
261 | return ((insn & 0x0C00) >> 10); | |
262 | } | |
263 | ||
264 | static int | |
265 | cris_get_opcode (unsigned short insn) | |
266 | { | |
267 | return ((insn & 0x03C0) >> 6); | |
268 | } | |
269 | ||
270 | static int | |
271 | cris_get_size (unsigned short insn) | |
272 | { | |
273 | return ((insn & 0x0030) >> 4); | |
274 | } | |
275 | ||
276 | static int | |
277 | cris_get_operand1 (unsigned short insn) | |
278 | { | |
279 | return (insn & 0x000F); | |
280 | } | |
281 | ||
282 | /* Additional functions in order to handle opcodes. */ | |
283 | ||
29134980 OF |
284 | static int |
285 | cris_get_quick_value (unsigned short insn) | |
286 | { | |
287 | return (insn & 0x003F); | |
288 | } | |
289 | ||
290 | static int | |
291 | cris_get_bdap_quick_offset (unsigned short insn) | |
292 | { | |
293 | return (insn & 0x00FF); | |
294 | } | |
295 | ||
296 | static int | |
297 | cris_get_branch_short_offset (unsigned short insn) | |
298 | { | |
299 | return (insn & 0x00FF); | |
300 | } | |
301 | ||
302 | static int | |
303 | cris_get_asr_shift_steps (unsigned long value) | |
304 | { | |
305 | return (value & 0x3F); | |
306 | } | |
307 | ||
29134980 OF |
308 | static int |
309 | cris_get_clear_size (unsigned short insn) | |
310 | { | |
311 | return ((insn) & 0xC000); | |
312 | } | |
313 | ||
314 | static int | |
315 | cris_is_signed_extend_bit_on (unsigned short insn) | |
316 | { | |
317 | return (((insn) & 0x20) == 0x20); | |
318 | } | |
319 | ||
320 | static int | |
321 | cris_is_xflag_bit_on (unsigned short insn) | |
322 | { | |
323 | return (((insn) & 0x1000) == 0x1000); | |
324 | } | |
325 | ||
326 | static void | |
327 | cris_set_size_to_dword (unsigned short *insn) | |
328 | { | |
329 | *insn &= 0xFFCF; | |
330 | *insn |= 0x20; | |
331 | } | |
332 | ||
8535cb38 | 333 | static signed char |
29134980 OF |
334 | cris_get_signed_offset (unsigned short insn) |
335 | { | |
8535cb38 | 336 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
337 | } |
338 | ||
339 | /* Calls an op function given the op-type, working on the insn and the | |
340 | inst_env. */ | |
341 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
342 | ||
29134980 OF |
343 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
344 | struct gdbarch_list *); | |
345 | ||
29134980 OF |
346 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
347 | ||
348 | static void cris_version_update (char *ignore_args, int from_tty, | |
349 | struct cmd_list_element *c); | |
350 | ||
351 | static void cris_mode_update (char *ignore_args, int from_tty, | |
352 | struct cmd_list_element *c); | |
353 | ||
2e4b5889 OF |
354 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
355 | struct frame_info *next_frame, | |
356 | struct cris_unwind_cache *info); | |
357 | ||
358 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, | |
359 | struct frame_info *next_frame); | |
360 | ||
361 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
362 | struct frame_info *next_frame); | |
363 | ||
364 | /* When arguments must be pushed onto the stack, they go on in reverse | |
365 | order. The below implements a FILO (stack) to do this. */ | |
366 | ||
367 | /* Borrowed from d10v-tdep.c. */ | |
368 | ||
369 | struct stack_item | |
370 | { | |
371 | int len; | |
372 | struct stack_item *prev; | |
373 | void *data; | |
374 | }; | |
375 | ||
376 | static struct stack_item * | |
377 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
378 | { | |
379 | struct stack_item *si; | |
380 | si = xmalloc (sizeof (struct stack_item)); | |
381 | si->data = xmalloc (len); | |
382 | si->len = len; | |
383 | si->prev = prev; | |
384 | memcpy (si->data, contents, len); | |
385 | return si; | |
386 | } | |
387 | ||
388 | static struct stack_item * | |
389 | pop_stack_item (struct stack_item *si) | |
390 | { | |
391 | struct stack_item *dead = si; | |
392 | si = si->prev; | |
393 | xfree (dead->data); | |
394 | xfree (dead); | |
395 | return si; | |
396 | } | |
397 | ||
398 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
399 | the saved registers of frame described by FRAME_INFO. This | |
400 | includes special registers such as pc and fp saved in special ways | |
401 | in the stack frame. sp is even more special: the address we return | |
402 | for it IS the sp for the next frame. */ | |
403 | ||
404 | struct cris_unwind_cache * | |
405 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
406 | void **this_prologue_cache) | |
407 | { | |
408 | CORE_ADDR pc; | |
409 | struct cris_unwind_cache *info; | |
410 | int i; | |
411 | ||
412 | if ((*this_prologue_cache)) | |
413 | return (*this_prologue_cache); | |
414 | ||
415 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
416 | (*this_prologue_cache) = info; | |
417 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
418 | ||
419 | /* Zero all fields. */ | |
420 | info->prev_sp = 0; | |
421 | info->base = 0; | |
422 | info->size = 0; | |
423 | info->sp_offset = 0; | |
424 | info->r8_offset = 0; | |
425 | info->uses_frame = 0; | |
426 | info->return_pc = 0; | |
427 | info->leaf_function = 0; | |
428 | ||
429 | /* Prologue analysis does the rest... */ | |
430 | cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info); | |
431 | ||
432 | return info; | |
433 | } | |
434 | ||
435 | /* Given a GDB frame, determine the address of the calling function's | |
436 | frame. This will be used to create a new GDB frame struct. */ | |
437 | ||
438 | static void | |
439 | cris_frame_this_id (struct frame_info *next_frame, | |
440 | void **this_prologue_cache, | |
441 | struct frame_id *this_id) | |
442 | { | |
443 | struct cris_unwind_cache *info | |
444 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
445 | CORE_ADDR base; | |
446 | CORE_ADDR func; | |
447 | struct frame_id id; | |
448 | ||
449 | /* The FUNC is easy. */ | |
450 | func = frame_func_unwind (next_frame); | |
451 | ||
452 | /* Hopefully the prologue analysis either correctly determined the | |
453 | frame's base (which is the SP from the previous frame), or set | |
454 | that base to "NULL". */ | |
455 | base = info->prev_sp; | |
456 | if (base == 0) | |
457 | return; | |
458 | ||
459 | id = frame_id_build (base, func); | |
460 | ||
461 | (*this_id) = id; | |
462 | } | |
463 | ||
464 | static void | |
465 | cris_frame_prev_register (struct frame_info *next_frame, | |
466 | void **this_prologue_cache, | |
467 | int regnum, int *optimizedp, | |
468 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
469 | int *realnump, void *bufferp) | |
470 | { | |
471 | struct cris_unwind_cache *info | |
472 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
473 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
474 | optimizedp, lvalp, addrp, realnump, bufferp); | |
475 | } | |
476 | ||
477 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
478 | dummy frame. The frame ID's base needs to match the TOS value | |
479 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
480 | breakpoint. */ | |
481 | ||
482 | static struct frame_id | |
483 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
484 | { | |
485 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
486 | frame_pc_unwind (next_frame)); | |
487 | } | |
488 | ||
489 | static CORE_ADDR | |
490 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
491 | { | |
492 | /* Align to the size of an instruction (so that they can safely be | |
493 | pushed onto the stack). */ | |
494 | return sp & ~3; | |
495 | } | |
496 | ||
497 | static CORE_ADDR | |
498 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
499 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
500 | struct value **args, int nargs, | |
501 | struct type *value_type, | |
502 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
503 | { | |
504 | /* Allocate space sufficient for a breakpoint. */ | |
505 | sp = (sp - 4) & ~3; | |
506 | /* Store the address of that breakpoint */ | |
507 | *bp_addr = sp; | |
508 | /* CRIS always starts the call at the callee's entry point. */ | |
509 | *real_pc = funaddr; | |
510 | return sp; | |
511 | } | |
512 | ||
513 | static CORE_ADDR | |
514 | cris_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
515 | struct regcache *regcache, CORE_ADDR bp_addr, | |
516 | int nargs, struct value **args, CORE_ADDR sp, | |
517 | int struct_return, CORE_ADDR struct_addr) | |
518 | { | |
519 | int stack_alloc; | |
520 | int stack_offset; | |
521 | int argreg; | |
522 | int argnum; | |
523 | ||
524 | CORE_ADDR regval; | |
525 | ||
526 | /* The function's arguments and memory allocated by gdb for the arguments to | |
527 | point at reside in separate areas on the stack. | |
528 | Both frame pointers grow toward higher addresses. */ | |
529 | CORE_ADDR fp_arg; | |
530 | CORE_ADDR fp_mem; | |
531 | ||
532 | struct stack_item *si = NULL; | |
533 | ||
534 | /* Push the return address. */ | |
535 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); | |
536 | ||
537 | /* Are we returning a value using a structure return or a normal value | |
538 | return? struct_addr is the address of the reserved space for the return | |
539 | structure to be written on the stack. */ | |
540 | if (struct_return) | |
541 | { | |
542 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
543 | } | |
544 | ||
545 | /* Now load as many as possible of the first arguments into registers, | |
546 | and push the rest onto the stack. */ | |
547 | argreg = ARG1_REGNUM; | |
548 | stack_offset = 0; | |
549 | ||
550 | for (argnum = 0; argnum < nargs; argnum++) | |
551 | { | |
552 | int len; | |
553 | char *val; | |
554 | int reg_demand; | |
555 | int i; | |
556 | ||
557 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); | |
558 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
559 | ||
560 | /* How may registers worth of storage do we need for this argument? */ | |
561 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
562 | ||
563 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
564 | { | |
565 | /* Data passed by value. Fits in available register(s). */ | |
566 | for (i = 0; i < reg_demand; i++) | |
567 | { | |
568 | regcache_cooked_write_unsigned (regcache, argreg, | |
569 | *(unsigned long *) val); | |
570 | argreg++; | |
571 | val += 4; | |
572 | } | |
573 | } | |
574 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
575 | { | |
576 | /* Data passed by value. Does not fit in available register(s). | |
577 | Use the register(s) first, then the stack. */ | |
578 | for (i = 0; i < reg_demand; i++) | |
579 | { | |
580 | if (argreg <= ARG4_REGNUM) | |
581 | { | |
582 | regcache_cooked_write_unsigned (regcache, argreg, | |
583 | *(unsigned long *) val); | |
584 | argreg++; | |
585 | val += 4; | |
586 | } | |
587 | else | |
588 | { | |
589 | /* Push item for later so that pushed arguments | |
590 | come in the right order. */ | |
591 | si = push_stack_item (si, val, 4); | |
592 | val += 4; | |
593 | } | |
594 | } | |
595 | } | |
596 | else if (len > (2 * 4)) | |
597 | { | |
598 | /* FIXME */ | |
599 | internal_error (__FILE__, __LINE__, "We don't do this"); | |
600 | } | |
601 | else | |
602 | { | |
603 | /* Data passed by value. No available registers. Put it on | |
604 | the stack. */ | |
605 | si = push_stack_item (si, val, len); | |
606 | } | |
607 | } | |
608 | ||
609 | while (si) | |
610 | { | |
611 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
612 | the function prologue. */ | |
613 | sp = (sp - si->len) & ~3; | |
614 | write_memory (sp, si->data, si->len); | |
615 | si = pop_stack_item (si); | |
616 | } | |
617 | ||
618 | /* Finally, update the SP register. */ | |
619 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
620 | ||
621 | return sp; | |
622 | } | |
623 | ||
624 | static const struct frame_unwind cris_frame_unwind = { | |
625 | NORMAL_FRAME, | |
626 | cris_frame_this_id, | |
627 | cris_frame_prev_register | |
628 | }; | |
629 | ||
630 | const struct frame_unwind * | |
631 | cris_frame_sniffer (struct frame_info *next_frame) | |
632 | { | |
633 | return &cris_frame_unwind; | |
634 | } | |
635 | ||
636 | static CORE_ADDR | |
637 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
638 | { | |
639 | struct cris_unwind_cache *info | |
640 | = cris_frame_unwind_cache (next_frame, this_cache); | |
641 | return info->base; | |
642 | } | |
643 | ||
644 | static const struct frame_base cris_frame_base = { | |
645 | &cris_frame_unwind, | |
646 | cris_frame_base_address, | |
647 | cris_frame_base_address, | |
648 | cris_frame_base_address | |
649 | }; | |
650 | ||
29134980 OF |
651 | /* Frames information. The definition of the struct frame_info is |
652 | ||
653 | CORE_ADDR frame | |
654 | CORE_ADDR pc | |
5a203e44 | 655 | enum frame_type type; |
29134980 OF |
656 | CORE_ADDR return_pc |
657 | int leaf_function | |
658 | ||
659 | If the compilation option -fno-omit-frame-pointer is present the | |
660 | variable frame will be set to the content of R8 which is the frame | |
661 | pointer register. | |
662 | ||
663 | The variable pc contains the address where execution is performed | |
664 | in the present frame. The innermost frame contains the current content | |
665 | of the register PC. All other frames contain the content of the | |
666 | register PC in the next frame. | |
667 | ||
5a203e44 AC |
668 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
669 | (associated with a signal handler), dummy (associated with a dummy | |
670 | frame). | |
29134980 OF |
671 | |
672 | The variable return_pc contains the address where execution should be | |
673 | resumed when the present frame has finished, the return address. | |
674 | ||
675 | The variable leaf_function is 1 if the return address is in the register | |
676 | SRP, and 0 if it is on the stack. | |
677 | ||
678 | Prologue instructions C-code. | |
679 | The prologue may consist of (-fno-omit-frame-pointer) | |
680 | 1) 2) | |
681 | push srp | |
682 | push r8 push r8 | |
683 | move.d sp,r8 move.d sp,r8 | |
684 | subq X,sp subq X,sp | |
685 | movem rY,[sp] movem rY,[sp] | |
686 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
687 | ||
688 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
689 | ||
690 | Note that this assumption is extremely brittle, and will break at the | |
691 | slightest change in GCC's prologue. | |
692 | ||
693 | If local variables are declared or register contents are saved on stack | |
694 | the subq-instruction will be present with X as the number of bytes | |
695 | needed for storage. The reshuffle with respect to r8 may be performed | |
696 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
697 | The offset U should be representable by a signed 8-bit value in all cases. | |
698 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
699 | by another word containing the instruction. | |
700 | ||
701 | Degenerate cases: | |
702 | 3) | |
703 | push r8 | |
704 | move.d sp,r8 | |
705 | move.d r8,sp | |
706 | pop r8 | |
707 | ||
708 | Prologue instructions C++-code. | |
709 | Case 1) and 2) in the C-code may be followed by | |
710 | ||
711 | move.d r10,rS ; this | |
712 | move.d r11,rT ; P1 | |
713 | move.d r12,rU ; P2 | |
714 | move.d r13,rV ; P3 | |
715 | move.S [r8+U],rZ ; P4 | |
716 | ||
717 | if any of the call parameters are stored. The host expects these | |
718 | instructions to be executed in order to get the call parameters right. */ | |
719 | ||
720 | /* Examine the prologue of a function. The variable ip is the address of | |
721 | the first instruction of the prologue. The variable limit is the address | |
722 | of the first instruction after the prologue. The variable fi contains the | |
723 | information in struct frame_info. The variable frameless_p controls whether | |
724 | the entire prologue is examined (0) or just enough instructions to | |
725 | determine that it is a prologue (1). */ | |
726 | ||
a78f21af | 727 | static CORE_ADDR |
2e4b5889 OF |
728 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
729 | struct cris_unwind_cache *info) | |
29134980 OF |
730 | { |
731 | /* Present instruction. */ | |
732 | unsigned short insn; | |
733 | ||
734 | /* Next instruction, lookahead. */ | |
735 | unsigned short insn_next; | |
736 | int regno; | |
737 | ||
738 | /* Is there a push fp? */ | |
739 | int have_fp; | |
740 | ||
741 | /* Number of byte on stack used for local variables and movem. */ | |
742 | int val; | |
743 | ||
744 | /* Highest register number in a movem. */ | |
745 | int regsave; | |
746 | ||
747 | /* move.d r<source_register>,rS */ | |
748 | short source_register; | |
749 | ||
2e4b5889 OF |
750 | /* Scan limit. */ |
751 | int limit; | |
29134980 | 752 | |
2e4b5889 OF |
753 | /* This frame is with respect to a leaf until a push srp is found. */ |
754 | if (info) | |
755 | { | |
756 | info->leaf_function = 1; | |
757 | } | |
29134980 OF |
758 | |
759 | /* Assume nothing on stack. */ | |
760 | val = 0; | |
761 | regsave = -1; | |
762 | ||
2e4b5889 OF |
763 | /* If we were called without a next_frame, that means we were called |
764 | from cris_skip_prologue which already tried to find the end of the | |
765 | prologue through the symbol information. 64 instructions past current | |
766 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
767 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 768 | |
29134980 | 769 | /* Find the prologue instructions. */ |
2e4b5889 | 770 | while (pc < limit) |
29134980 | 771 | { |
2e4b5889 OF |
772 | insn = read_memory_unsigned_integer (pc, 2); |
773 | pc += 2; | |
29134980 OF |
774 | if (insn == 0xE1FC) |
775 | { | |
776 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
777 | insn_next = read_memory_unsigned_integer (pc, 2); |
778 | pc += 2; | |
29134980 | 779 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
780 | if (info) |
781 | { | |
782 | info->sp_offset += 4; | |
783 | } | |
dbbff683 OF |
784 | /* This check, meant to recognize srp, used to be regno == |
785 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
786 | if (insn_next == 0xBE7E) | |
29134980 | 787 | { |
2e4b5889 OF |
788 | if (info) |
789 | { | |
790 | info->leaf_function = 0; | |
791 | } | |
29134980 | 792 | } |
b4206d25 OF |
793 | else if (insn_next == 0x8FEE) |
794 | { | |
795 | /* push $r8 */ | |
796 | if (info) | |
797 | { | |
798 | info->r8_offset = info->sp_offset; | |
799 | } | |
800 | } | |
29134980 OF |
801 | } |
802 | else if (insn == 0x866E) | |
803 | { | |
804 | /* move.d sp,r8 */ | |
2e4b5889 OF |
805 | if (info) |
806 | { | |
807 | info->uses_frame = 1; | |
2e4b5889 | 808 | } |
29134980 OF |
809 | continue; |
810 | } | |
811 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
812 | && cris_get_mode (insn) == 0x0000 | |
813 | && cris_get_opcode (insn) == 0x000A) | |
814 | { | |
815 | /* subq <val>,sp */ | |
2e4b5889 OF |
816 | if (info) |
817 | { | |
818 | info->sp_offset += cris_get_quick_value (insn); | |
819 | } | |
29134980 OF |
820 | } |
821 | else if (cris_get_mode (insn) == 0x0002 | |
822 | && cris_get_opcode (insn) == 0x000F | |
823 | && cris_get_size (insn) == 0x0003 | |
824 | && cris_get_operand1 (insn) == SP_REGNUM) | |
825 | { | |
826 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
827 | regsave = cris_get_operand2 (insn); |
828 | } | |
829 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
830 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
831 | && (cris_get_signed_offset (insn) < 0)) | |
832 | { | |
833 | /* Immediate byte offset addressing prefix word with sp as base | |
834 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
835 | is between 64 and 128. | |
836 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
837 | if (info) |
838 | { | |
839 | info->sp_offset += -cris_get_signed_offset (insn); | |
840 | } | |
841 | insn_next = read_memory_unsigned_integer (pc, 2); | |
842 | pc += 2; | |
29134980 OF |
843 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
844 | && cris_get_opcode (insn_next) == 0x000F | |
845 | && cris_get_size (insn_next) == 0x0003 | |
846 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
847 | { | |
29134980 OF |
848 | regsave = cris_get_operand2 (insn_next); |
849 | } | |
850 | else | |
851 | { | |
852 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 853 | pc -= 4; |
29134980 OF |
854 | break; |
855 | } | |
856 | } | |
857 | else if (cris_get_mode (insn) == 0x0001 | |
858 | && cris_get_opcode (insn) == 0x0009 | |
859 | && cris_get_size (insn) == 0x0002) | |
860 | { | |
861 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 862 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
863 | |
864 | /* FIXME? In the glibc solibs, the prologue might contain something | |
865 | like (this example taken from relocate_doit): | |
866 | move.d $pc,$r0 | |
867 | sub.d 0xfffef426,$r0 | |
868 | which isn't covered by the source_register check below. Question | |
869 | is whether to add a check for this combo, or make better use of | |
870 | the limit variable instead. */ | |
29134980 OF |
871 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
872 | { | |
873 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 874 | pc -= 2; |
29134980 OF |
875 | break; |
876 | } | |
877 | } | |
2e4b5889 | 878 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
879 | /* The size is a fixed-size. */ |
880 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
881 | /* A negative offset. */ | |
882 | && (cris_get_signed_offset (insn) < 0)) | |
883 | { | |
884 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
885 | insn_next = read_memory_unsigned_integer (pc, 2); |
886 | pc += 2; | |
29134980 OF |
887 | regno = cris_get_operand2 (insn_next); |
888 | if ((regno >= 0 && regno < SP_REGNUM) | |
889 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
890 | && cris_get_opcode (insn_next) == 0x000F) | |
891 | { | |
892 | /* move.S rZ,[r8-U] */ | |
893 | continue; | |
894 | } | |
895 | else | |
896 | { | |
897 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 898 | pc -= 4; |
29134980 OF |
899 | break; |
900 | } | |
901 | } | |
2e4b5889 | 902 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
903 | /* The size is a fixed-size. */ |
904 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
905 | /* A positive offset. */ | |
906 | && (cris_get_signed_offset (insn) > 0)) | |
907 | { | |
908 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
909 | insn_next = read_memory_unsigned_integer (pc, 2); |
910 | pc += 2; | |
29134980 OF |
911 | regno = cris_get_operand2 (insn_next); |
912 | if ((regno >= 0 && regno < SP_REGNUM) | |
913 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
914 | && cris_get_opcode (insn_next) == 0x0009 | |
915 | && cris_get_operand1 (insn_next) == regno) | |
916 | { | |
917 | /* move.S [r8+U],rZ */ | |
918 | continue; | |
919 | } | |
920 | else | |
921 | { | |
922 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 923 | pc -= 4; |
29134980 OF |
924 | break; |
925 | } | |
926 | } | |
927 | else | |
928 | { | |
929 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 930 | pc -= 2; |
29134980 OF |
931 | break; |
932 | } | |
933 | } | |
29134980 | 934 | |
2e4b5889 OF |
935 | /* We only want to know the end of the prologue when next_frame and info |
936 | are NULL (called from cris_skip_prologue i.e.). */ | |
937 | if (next_frame == NULL && info == NULL) | |
938 | { | |
939 | return pc; | |
940 | } | |
29134980 | 941 | |
2e4b5889 OF |
942 | info->size = info->sp_offset; |
943 | ||
944 | /* Compute the previous frame's stack pointer (which is also the | |
945 | frame's ID's stack address), and this frame's base pointer. */ | |
946 | if (info->uses_frame) | |
29134980 | 947 | { |
2e4b5889 OF |
948 | ULONGEST this_base; |
949 | /* The SP was moved to the FP. This indicates that a new frame | |
950 | was created. Get THIS frame's FP value by unwinding it from | |
951 | the next frame. */ | |
952 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
953 | &this_base); | |
954 | info->base = this_base; | |
b4206d25 OF |
955 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
956 | ||
2e4b5889 OF |
957 | /* The FP points at the last saved register. Adjust the FP back |
958 | to before the first saved register giving the SP. */ | |
959 | info->prev_sp = info->base + info->r8_offset; | |
960 | } | |
961 | else | |
962 | { | |
963 | ULONGEST this_base; | |
964 | /* Assume that the FP is this frame's SP but with that pushed | |
965 | stack space added back. */ | |
966 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
967 | info->base = this_base; | |
968 | info->prev_sp = info->base + info->size; | |
969 | } | |
29134980 | 970 | |
2e4b5889 OF |
971 | /* Calculate the addresses for the saved registers on the stack. */ |
972 | /* FIXME: The address calculation should really be done on the fly while | |
973 | we're analyzing the prologue (we only hold one regsave value as it is | |
974 | now). */ | |
975 | val = info->sp_offset; | |
976 | ||
977 | for (regno = regsave; regno >= 0; regno--) | |
978 | { | |
979 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
980 | val -= 4; | |
981 | } | |
982 | ||
983 | /* The previous frame's SP needed to be computed. Save the computed | |
984 | value. */ | |
985 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
986 | ||
987 | if (!info->leaf_function) | |
988 | { | |
b4206d25 OF |
989 | /* SRP saved on the stack. But where? */ |
990 | if (info->r8_offset == 0) | |
991 | { | |
992 | /* R8 not pushed yet. */ | |
993 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
994 | } | |
995 | else | |
996 | { | |
997 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
998 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
999 | } | |
29134980 | 1000 | } |
2e4b5889 OF |
1001 | |
1002 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1003 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1004 | ||
1005 | return pc; | |
29134980 OF |
1006 | } |
1007 | ||
1008 | /* Advance pc beyond any function entry prologue instructions at pc | |
1009 | to reach some "real" code. */ | |
1010 | ||
29134980 OF |
1011 | /* Given a PC value corresponding to the start of a function, return the PC |
1012 | of the first instruction after the function prologue. */ | |
1013 | ||
a78f21af | 1014 | static CORE_ADDR |
2e4b5889 | 1015 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1016 | { |
2e4b5889 OF |
1017 | CORE_ADDR func_addr, func_end; |
1018 | struct symtab_and_line sal; | |
29134980 OF |
1019 | CORE_ADDR pc_after_prologue; |
1020 | ||
2e4b5889 OF |
1021 | /* If we have line debugging information, then the end of the prologue |
1022 | should the first assembly instruction of the first source line. */ | |
1023 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1024 | { | |
1025 | sal = find_pc_line (func_addr, 0); | |
1026 | if (sal.end > 0 && sal.end < func_end) | |
1027 | return sal.end; | |
1028 | } | |
29134980 | 1029 | |
2e4b5889 | 1030 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); |
29134980 OF |
1031 | return pc_after_prologue; |
1032 | } | |
1033 | ||
2e4b5889 OF |
1034 | static CORE_ADDR |
1035 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1036 | { | |
1037 | ULONGEST pc; | |
1038 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1039 | return pc; | |
1040 | } | |
1041 | ||
1042 | static CORE_ADDR | |
1043 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1044 | { | |
1045 | ULONGEST sp; | |
1046 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1047 | return sp; | |
1048 | } | |
1049 | ||
29134980 OF |
1050 | /* Use the program counter to determine the contents and size of a breakpoint |
1051 | instruction. It returns a pointer to a string of bytes that encode a | |
1052 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1053 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1054 | the breakpoint should be inserted. */ | |
1055 | ||
a78f21af | 1056 | static const unsigned char * |
29134980 OF |
1057 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1058 | { | |
1059 | static unsigned char break_insn[] = {0x38, 0xe9}; | |
1060 | *lenptr = 2; | |
1061 | ||
1062 | return break_insn; | |
1063 | } | |
1064 | ||
29134980 OF |
1065 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1066 | 0 otherwise. */ | |
1067 | ||
a78f21af | 1068 | static int |
29134980 OF |
1069 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1070 | { | |
1071 | int version = cris_version (); | |
1072 | ||
1073 | switch (spec_reg.applicable_version) | |
1074 | { | |
1075 | case cris_ver_version_all: | |
1076 | return 1; | |
1077 | case cris_ver_warning: | |
1078 | /* Indeterminate/obsolete. */ | |
1079 | return 0; | |
1080 | case cris_ver_sim: | |
1081 | /* Simulator only. */ | |
1082 | return 0; | |
1083 | case cris_ver_v0_3: | |
1084 | return (version >= 0 && version <= 3); | |
1085 | case cris_ver_v3p: | |
1086 | return (version >= 3); | |
1087 | case cris_ver_v8: | |
1088 | return (version == 8 || version == 9); | |
1089 | case cris_ver_v8p: | |
1090 | return (version >= 8); | |
1091 | case cris_ver_v10p: | |
1092 | return (version >= 10); | |
1093 | default: | |
1094 | /* Invalid cris version. */ | |
1095 | return 0; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | /* Returns the register size in unit byte. Returns 0 for an unimplemented | |
1100 | register, -1 for an invalid register. */ | |
1101 | ||
a78f21af | 1102 | static int |
29134980 OF |
1103 | cris_register_size (int regno) |
1104 | { | |
1105 | int i; | |
1106 | int spec_regno; | |
1107 | ||
1108 | if (regno >= 0 && regno < NUM_GENREGS) | |
1109 | { | |
1110 | /* General registers (R0 - R15) are 32 bits. */ | |
1111 | return 4; | |
1112 | } | |
1113 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) | |
1114 | { | |
1115 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1116 | Adjust regno accordingly. */ | |
1117 | spec_regno = regno - NUM_GENREGS; | |
1118 | ||
1119 | /* The entries in cris_spec_regs are stored in register number order, | |
1120 | which means we can shortcut into the array when searching it. */ | |
1121 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
1122 | { | |
1123 | if (cris_spec_regs[i].number == spec_regno | |
1124 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1125 | /* Go with the first applicable register. */ | |
1126 | return cris_spec_regs[i].reg_size; | |
1127 | } | |
1128 | /* Special register not applicable to this CRIS version. */ | |
1129 | return 0; | |
1130 | } | |
1131 | else | |
1132 | { | |
1133 | /* Invalid register. */ | |
1134 | return -1; | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | /* Nonzero if regno should not be fetched from the target. This is the case | |
1139 | for unimplemented (size 0) and non-existant registers. */ | |
1140 | ||
a78f21af | 1141 | static int |
29134980 OF |
1142 | cris_cannot_fetch_register (int regno) |
1143 | { | |
1144 | return ((regno < 0 || regno >= NUM_REGS) | |
1145 | || (cris_register_size (regno) == 0)); | |
1146 | } | |
1147 | ||
1148 | /* Nonzero if regno should not be written to the target, for various | |
1149 | reasons. */ | |
1150 | ||
a78f21af | 1151 | static int |
29134980 OF |
1152 | cris_cannot_store_register (int regno) |
1153 | { | |
1154 | /* There are three kinds of registers we refuse to write to. | |
1155 | 1. Those that not implemented. | |
1156 | 2. Those that are read-only (depends on the processor mode). | |
1157 | 3. Those registers to which a write has no effect. | |
1158 | */ | |
1159 | ||
1160 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1161 | /* Not implemented. */ | |
1162 | return 1; | |
1163 | ||
1164 | else if (regno == VR_REGNUM) | |
1165 | /* Read-only. */ | |
1166 | return 1; | |
1167 | ||
1168 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1169 | /* Writing has no effect. */ | |
1170 | return 1; | |
1171 | ||
1172 | else if (cris_mode () == CRIS_MODE_USER) | |
1173 | { | |
1174 | if (regno == IBR_REGNUM || regno == BAR_REGNUM || regno == BRP_REGNUM | |
1175 | || regno == IRP_REGNUM) | |
1176 | /* Read-only in user mode. */ | |
1177 | return 1; | |
1178 | } | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | /* Returns the register offset for the first byte of register regno's space | |
1184 | in the saved register state. Returns -1 for an invalid or unimplemented | |
1185 | register. */ | |
1186 | ||
a78f21af | 1187 | static int |
29134980 OF |
1188 | cris_register_offset (int regno) |
1189 | { | |
1190 | int i; | |
1191 | int reg_size; | |
1192 | int offset = 0; | |
1193 | ||
1194 | if (regno >= 0 && regno < NUM_REGS) | |
1195 | { | |
1196 | /* FIXME: The offsets should be cached and calculated only once, | |
1197 | when the architecture being debugged has changed. */ | |
1198 | for (i = 0; i < regno; i++) | |
1199 | offset += cris_register_size (i); | |
1200 | ||
1201 | return offset; | |
1202 | } | |
1203 | else | |
1204 | { | |
1205 | /* Invalid register. */ | |
1206 | return -1; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type | |
1211 | of data in register regno. */ | |
1212 | ||
a78f21af | 1213 | static struct type * |
29134980 OF |
1214 | cris_register_virtual_type (int regno) |
1215 | { | |
1216 | if (regno == SP_REGNUM || regno == PC_REGNUM | |
1217 | || (regno > P8_REGNUM && regno < USP_REGNUM)) | |
1218 | { | |
1219 | /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */ | |
1220 | return lookup_pointer_type (builtin_type_void); | |
1221 | } | |
1222 | else if (regno == P8_REGNUM || regno == USP_REGNUM | |
1223 | || (regno >= 0 && regno < SP_REGNUM)) | |
1224 | { | |
1225 | /* R0 - R13, P8, P15 */ | |
1226 | return builtin_type_unsigned_long; | |
1227 | } | |
2e4b5889 | 1228 | else if (regno > P3_REGNUM && regno < P8_REGNUM) |
29134980 | 1229 | { |
2e4b5889 OF |
1230 | /* P4, CCR, DCR0, DCR1 */ |
1231 | return builtin_type_unsigned_short; | |
29134980 | 1232 | } |
2e4b5889 | 1233 | else if (regno > PC_REGNUM && regno < P4_REGNUM) |
29134980 | 1234 | { |
2e4b5889 OF |
1235 | /* P0, P1, P2, P3 */ |
1236 | return builtin_type_unsigned_char; | |
29134980 OF |
1237 | } |
1238 | else | |
1239 | { | |
2e4b5889 OF |
1240 | /* Invalid register. */ |
1241 | return builtin_type_void; | |
29134980 OF |
1242 | } |
1243 | } | |
1244 | ||
2e4b5889 OF |
1245 | /* Stores a function return value of type type, where valbuf is the address |
1246 | of the value to be stored. */ | |
29134980 | 1247 | |
2e4b5889 | 1248 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1249 | |
2e4b5889 OF |
1250 | static void |
1251 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1252 | const void *valbuf) | |
29134980 | 1253 | { |
2e4b5889 OF |
1254 | ULONGEST val; |
1255 | int len = TYPE_LENGTH (type); | |
29134980 | 1256 | |
2e4b5889 | 1257 | if (len <= 4) |
29134980 | 1258 | { |
2e4b5889 OF |
1259 | /* Put the return value in R10. */ |
1260 | val = extract_unsigned_integer (valbuf, len); | |
1261 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1262 | } |
2e4b5889 | 1263 | else if (len <= 8) |
29134980 | 1264 | { |
2e4b5889 OF |
1265 | /* Put the return value in R10 and R11. */ |
1266 | val = extract_unsigned_integer (valbuf, 4); | |
1267 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1268 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1269 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1270 | } |
2e4b5889 OF |
1271 | else |
1272 | error ("cris_store_return_value: type length too large."); | |
29134980 OF |
1273 | } |
1274 | ||
2e4b5889 OF |
1275 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1276 | unimplemented register. */ | |
29134980 | 1277 | |
2e4b5889 OF |
1278 | static const char * |
1279 | cris_register_name (int regno) | |
1280 | { | |
1281 | static char *cris_genreg_names[] = | |
1282 | { "r0", "r1", "r2", "r3", \ | |
1283 | "r4", "r5", "r6", "r7", \ | |
1284 | "r8", "r9", "r10", "r11", \ | |
1285 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1286 | |
2e4b5889 OF |
1287 | int i; |
1288 | int spec_regno; | |
29134980 | 1289 | |
2e4b5889 | 1290 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1291 | { |
2e4b5889 OF |
1292 | /* General register. */ |
1293 | return cris_genreg_names[regno]; | |
29134980 | 1294 | } |
2e4b5889 | 1295 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
29134980 | 1296 | { |
2e4b5889 OF |
1297 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
1298 | Adjust regno accordingly. */ | |
1299 | spec_regno = regno - NUM_GENREGS; | |
29134980 | 1300 | |
2e4b5889 OF |
1301 | /* The entries in cris_spec_regs are stored in register number order, |
1302 | which means we can shortcut into the array when searching it. */ | |
1303 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
29134980 | 1304 | { |
2e4b5889 OF |
1305 | if (cris_spec_regs[i].number == spec_regno |
1306 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1307 | /* Go with the first applicable register. */ | |
1308 | return cris_spec_regs[i].name; | |
29134980 | 1309 | } |
2e4b5889 OF |
1310 | /* Special register not applicable to this CRIS version. */ |
1311 | return NULL; | |
1312 | } | |
1313 | else | |
1314 | { | |
1315 | /* Invalid register. */ | |
1316 | return NULL; | |
29134980 | 1317 | } |
29134980 OF |
1318 | } |
1319 | ||
2e4b5889 OF |
1320 | static int |
1321 | cris_register_bytes_ok (long bytes) | |
29134980 | 1322 | { |
2e4b5889 | 1323 | return (bytes == DEPRECATED_REGISTER_BYTES); |
29134980 OF |
1324 | } |
1325 | ||
2e4b5889 OF |
1326 | /* Extract from an array regbuf containing the raw register state a function |
1327 | return value of type type, and copy that, in virtual format, into | |
1328 | valbuf. */ | |
1329 | ||
1330 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1331 | |
2e4b5889 OF |
1332 | static void |
1333 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1334 | void *valbuf) | |
29134980 | 1335 | { |
2e4b5889 OF |
1336 | ULONGEST val; |
1337 | int len = TYPE_LENGTH (type); | |
29134980 | 1338 | |
2e4b5889 | 1339 | if (len <= 4) |
29134980 | 1340 | { |
2e4b5889 OF |
1341 | /* Get the return value from R10. */ |
1342 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1343 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1344 | } |
2e4b5889 | 1345 | else if (len <= 8) |
29134980 | 1346 | { |
2e4b5889 OF |
1347 | /* Get the return value from R10 and R11. */ |
1348 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1349 | store_unsigned_integer (valbuf, 4, val); | |
1350 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1351 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1352 | } |
2e4b5889 OF |
1353 | else |
1354 | error ("cris_extract_return_value: type length too large"); | |
1355 | } | |
1356 | ||
b4206d25 OF |
1357 | /* Handle the CRIS return value convention. */ |
1358 | ||
1359 | static enum return_value_convention | |
1360 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
1361 | struct regcache *regcache, void *readbuf, | |
1362 | const void *writebuf) | |
1363 | { | |
1364 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1365 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1366 | || TYPE_LENGTH (type) > 8) | |
1367 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1368 | goes on the stack. */ | |
1369 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1370 | ||
1371 | if (readbuf) | |
1372 | cris_extract_return_value (type, regcache, readbuf); | |
1373 | if (writebuf) | |
1374 | cris_store_return_value (type, regcache, writebuf); | |
1375 | ||
1376 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1377 | } | |
1378 | ||
2e4b5889 OF |
1379 | /* Returns 1 if the given type will be passed by pointer rather than |
1380 | directly. */ | |
1381 | ||
1382 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1383 | by value. */ | |
1384 | ||
1385 | static int | |
1386 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1387 | { | |
1388 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1389 | } |
1390 | ||
1391 | /* Calculates a value that measures how good inst_args constraints an | |
1392 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1393 | ||
1394 | static int | |
1395 | constraint (unsigned int insn, const signed char *inst_args, | |
1396 | inst_env_type *inst_env) | |
1397 | { | |
1398 | int retval = 0; | |
1399 | int tmp, i; | |
1400 | ||
1401 | const char *s = inst_args; | |
1402 | ||
1403 | for (; *s; s++) | |
1404 | switch (*s) | |
1405 | { | |
1406 | case 'm': | |
1407 | if ((insn & 0x30) == 0x30) | |
1408 | return -1; | |
1409 | break; | |
1410 | ||
1411 | case 'S': | |
1412 | /* A prefix operand. */ | |
1413 | if (inst_env->prefix_found) | |
1414 | break; | |
1415 | else | |
1416 | return -1; | |
1417 | ||
1418 | case 'B': | |
1419 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1420 | valid "push" size. In case of special register, it may be != 4. */ | |
1421 | if (inst_env->prefix_found) | |
1422 | break; | |
1423 | else | |
1424 | return -1; | |
1425 | ||
1426 | case 'D': | |
1427 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1428 | if (!retval) | |
1429 | return -1; | |
1430 | else | |
1431 | retval += 4; | |
1432 | break; | |
1433 | ||
1434 | case 'P': | |
1435 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1436 | |
1437 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1438 | { | |
1439 | /* Since we match four bits, we will give a value of | |
1440 | 4 - 1 = 3 in a match. If there is a corresponding | |
1441 | exact match of a special register in another pattern, it | |
1442 | will get a value of 4, which will be higher. This should | |
1443 | be correct in that an exact pattern would match better that | |
1444 | a general pattern. | |
1445 | Note that there is a reason for not returning zero; the | |
1446 | pattern for "clear" is partly matched in the bit-pattern | |
1447 | (the two lower bits must be zero), while the bit-pattern | |
1448 | for a move from a special register is matched in the | |
1449 | register constraint. | |
1450 | This also means we will will have a race condition if | |
1451 | there is a partly match in three bits in the bit pattern. */ | |
1452 | if (tmp == cris_spec_regs[i].number) | |
1453 | { | |
1454 | retval += 3; | |
1455 | break; | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1460 | return -1; |
1461 | break; | |
1462 | } | |
1463 | return retval; | |
1464 | } | |
1465 | ||
1466 | /* Returns the number of bits set in the variable value. */ | |
1467 | ||
1468 | static int | |
1469 | number_of_bits (unsigned int value) | |
1470 | { | |
1471 | int number_of_bits = 0; | |
1472 | ||
1473 | while (value != 0) | |
1474 | { | |
1475 | number_of_bits += 1; | |
1476 | value &= (value - 1); | |
1477 | } | |
1478 | return number_of_bits; | |
1479 | } | |
1480 | ||
1481 | /* Finds the address that should contain the single step breakpoint(s). | |
1482 | It stems from code in cris-dis.c. */ | |
1483 | ||
1484 | static int | |
1485 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1486 | { | |
1487 | int i; | |
1488 | int max_level_of_match = -1; | |
1489 | int max_matched = -1; | |
1490 | int level_of_match; | |
1491 | ||
1492 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1493 | { | |
1494 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
1495 | && ((cris_opcodes[i].lose & insn) == 0)) | |
1496 | { | |
1497 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1498 | if (level_of_match >= 0) | |
1499 | { | |
1500 | level_of_match += | |
1501 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1502 | if (level_of_match > max_level_of_match) | |
1503 | { | |
1504 | max_matched = i; | |
1505 | max_level_of_match = level_of_match; | |
1506 | if (level_of_match == 16) | |
1507 | { | |
1508 | /* All bits matched, cannot find better. */ | |
1509 | break; | |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | } | |
1514 | } | |
1515 | return max_matched; | |
1516 | } | |
1517 | ||
1518 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1519 | actually an internal error. */ | |
1520 | ||
1521 | static int | |
1522 | find_step_target (inst_env_type *inst_env) | |
1523 | { | |
1524 | int i; | |
1525 | int offset; | |
1526 | unsigned short insn; | |
1527 | ||
1528 | /* Create a local register image and set the initial state. */ | |
1529 | for (i = 0; i < NUM_GENREGS; i++) | |
1530 | { | |
1531 | inst_env->reg[i] = (unsigned long) read_register (i); | |
1532 | } | |
1533 | offset = NUM_GENREGS; | |
1534 | for (i = 0; i < NUM_SPECREGS; i++) | |
1535 | { | |
1536 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
1537 | } | |
1538 | inst_env->branch_found = 0; | |
1539 | inst_env->slot_needed = 0; | |
1540 | inst_env->delay_slot_pc_active = 0; | |
1541 | inst_env->prefix_found = 0; | |
1542 | inst_env->invalid = 0; | |
1543 | inst_env->xflag_found = 0; | |
1544 | inst_env->disable_interrupt = 0; | |
1545 | ||
1546 | /* Look for a step target. */ | |
1547 | do | |
1548 | { | |
1549 | /* Read an instruction from the client. */ | |
1550 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
1551 | ||
1552 | /* If the instruction is not in a delay slot the new content of the | |
1553 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
1554 | that simple. Since a instruction in a delay slot cannot change | |
1555 | the content of the PC, it does not matter what value PC will have. | |
1556 | Just make sure it is a valid instruction. */ | |
1557 | if (!inst_env->delay_slot_pc_active) | |
1558 | { | |
1559 | inst_env->reg[PC_REGNUM] += 2; | |
1560 | } | |
1561 | else | |
1562 | { | |
1563 | inst_env->delay_slot_pc_active = 0; | |
1564 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
1565 | } | |
1566 | /* Analyse the present instruction. */ | |
1567 | i = find_cris_op (insn, inst_env); | |
1568 | if (i == -1) | |
1569 | { | |
1570 | inst_env->invalid = 1; | |
1571 | } | |
1572 | else | |
1573 | { | |
1574 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
1575 | } | |
1576 | } while (!inst_env->invalid | |
1577 | && (inst_env->prefix_found || inst_env->xflag_found | |
1578 | || inst_env->slot_needed)); | |
1579 | return i; | |
1580 | } | |
1581 | ||
1582 | /* There is no hardware single-step support. The function find_step_target | |
1583 | digs through the opcodes in order to find all possible targets. | |
1584 | Either one ordinary target or two targets for branches may be found. */ | |
1585 | ||
a78f21af | 1586 | static void |
29134980 OF |
1587 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) |
1588 | { | |
1589 | inst_env_type inst_env; | |
1590 | ||
1591 | if (insert_breakpoints) | |
1592 | { | |
1593 | /* Analyse the present instruction environment and insert | |
1594 | breakpoints. */ | |
1595 | int status = find_step_target (&inst_env); | |
1596 | if (status == -1) | |
1597 | { | |
1598 | /* Could not find a target. FIXME: Should do something. */ | |
1599 | } | |
1600 | else | |
1601 | { | |
1602 | /* Insert at most two breakpoints. One for the next PC content | |
1603 | and possibly another one for a branch, jump, etc. */ | |
1604 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
1605 | target_insert_breakpoint (next_pc, break_mem[0]); | |
1606 | if (inst_env.branch_found | |
1607 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
1608 | { | |
1609 | branch_target_address = | |
1610 | (CORE_ADDR) inst_env.branch_break_address; | |
1611 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
1612 | branch_break_inserted = 1; | |
1613 | } | |
1614 | } | |
1615 | } | |
1616 | else | |
1617 | { | |
1618 | /* Remove breakpoints. */ | |
1619 | target_remove_breakpoint (next_pc, break_mem[0]); | |
1620 | if (branch_break_inserted) | |
1621 | { | |
1622 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
1623 | branch_break_inserted = 0; | |
1624 | } | |
1625 | } | |
1626 | } | |
1627 | ||
1628 | /* Calculates the prefix value for quick offset addressing mode. */ | |
1629 | ||
a78f21af | 1630 | static void |
29134980 OF |
1631 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
1632 | { | |
1633 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
1634 | instruction (not 100% sure). */ | |
1635 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1636 | { | |
1637 | inst_env->invalid = 1; | |
1638 | return; | |
1639 | } | |
1640 | ||
1641 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
1642 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
1643 | ||
1644 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1645 | need updating. */ | |
1646 | inst_env->slot_needed = 0; | |
1647 | inst_env->prefix_found = 1; | |
1648 | } | |
1649 | ||
1650 | /* Updates the autoincrement register. The size of the increment is derived | |
1651 | from the size of the operation. The PC is always kept aligned on even | |
1652 | word addresses. */ | |
1653 | ||
a78f21af | 1654 | static void |
29134980 OF |
1655 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
1656 | { | |
1657 | if (size == INST_BYTE_SIZE) | |
1658 | { | |
1659 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
1660 | ||
1661 | /* The PC must be word aligned, so increase the PC with one | |
1662 | word even if the size is byte. */ | |
1663 | if (cris_get_operand1 (inst) == REG_PC) | |
1664 | { | |
1665 | inst_env->reg[REG_PC] += 1; | |
1666 | } | |
1667 | } | |
1668 | else if (size == INST_WORD_SIZE) | |
1669 | { | |
1670 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
1671 | } | |
1672 | else if (size == INST_DWORD_SIZE) | |
1673 | { | |
1674 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1675 | } | |
1676 | else | |
1677 | { | |
1678 | /* Invalid size. */ | |
1679 | inst_env->invalid = 1; | |
1680 | } | |
1681 | } | |
1682 | ||
2a9ecef2 OF |
1683 | /* Just a forward declaration. */ |
1684 | ||
a78f21af AC |
1685 | static unsigned long get_data_from_address (unsigned short *inst, |
1686 | CORE_ADDR address); | |
2a9ecef2 | 1687 | |
29134980 OF |
1688 | /* Calculates the prefix value for the general case of offset addressing |
1689 | mode. */ | |
1690 | ||
a78f21af | 1691 | static void |
29134980 OF |
1692 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
1693 | { | |
1694 | ||
1695 | long offset; | |
1696 | ||
1697 | /* It's invalid to be in a delay slot. */ | |
1698 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1699 | { | |
1700 | inst_env->invalid = 1; | |
1701 | return; | |
1702 | } | |
1703 | ||
fa4e4598 OF |
1704 | /* The calculation of prefix_value used to be after process_autoincrement, |
1705 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
1706 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
1707 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
1708 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
1709 | ||
1710 | /* The offset is an indirection of the contents of the operand1 register. */ | |
1711 | inst_env->prefix_value += | |
2a9ecef2 OF |
1712 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
1713 | ||
fa4e4598 OF |
1714 | if (cris_get_mode (inst) == AUTOINC_MODE) |
1715 | { | |
1716 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
1717 | } | |
1718 | ||
29134980 OF |
1719 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
1720 | need updating. */ | |
1721 | inst_env->slot_needed = 0; | |
1722 | inst_env->prefix_found = 1; | |
1723 | } | |
1724 | ||
1725 | /* Calculates the prefix value for the index addressing mode. */ | |
1726 | ||
a78f21af | 1727 | static void |
29134980 OF |
1728 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
1729 | { | |
1730 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
1731 | have a prefix to this instruction. So I will treat this as invalid. */ | |
1732 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1733 | { | |
1734 | inst_env->invalid = 1; | |
1735 | return; | |
1736 | } | |
1737 | ||
1738 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
1739 | ||
1740 | /* The offset is the operand2 value shifted the size of the instruction | |
1741 | to the left. */ | |
1742 | inst_env->prefix_value += | |
1743 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
1744 | ||
1745 | /* If the PC is operand1 (base) the address used is the address after | |
1746 | the main instruction, i.e. address + 2 (the PC is already compensated | |
1747 | for the prefix operation). */ | |
1748 | if (cris_get_operand1 (inst) == REG_PC) | |
1749 | { | |
1750 | inst_env->prefix_value += 2; | |
1751 | } | |
1752 | ||
1753 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1754 | need updating. */ | |
1755 | inst_env->slot_needed = 0; | |
1756 | inst_env->xflag_found = 0; | |
1757 | inst_env->prefix_found = 1; | |
1758 | } | |
1759 | ||
1760 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
1761 | ||
a78f21af | 1762 | static void |
29134980 OF |
1763 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
1764 | { | |
1765 | ||
1766 | CORE_ADDR address; | |
1767 | ||
1768 | /* It's invalid to be in a delay slot. */ | |
1769 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1770 | { | |
1771 | inst_env->invalid = 1; | |
1772 | return; | |
1773 | } | |
1774 | ||
1775 | /* The prefix value is one dereference of the contents of the operand1 | |
1776 | register. */ | |
1777 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
1778 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
1779 | ||
1780 | /* Check if the mode is autoincrement. */ | |
1781 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
1782 | { | |
1783 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1784 | } | |
1785 | ||
1786 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1787 | need updating. */ | |
1788 | inst_env->slot_needed = 0; | |
1789 | inst_env->xflag_found = 0; | |
1790 | inst_env->prefix_found = 1; | |
1791 | } | |
1792 | ||
1793 | /* Finds the destination for a branch with 8-bits offset. */ | |
1794 | ||
a78f21af | 1795 | static void |
29134980 OF |
1796 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
1797 | { | |
1798 | ||
1799 | short offset; | |
1800 | ||
1801 | /* If we have a prefix or are in a delay slot it's bad. */ | |
1802 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1803 | { | |
1804 | inst_env->invalid = 1; | |
1805 | return; | |
1806 | } | |
1807 | ||
1808 | /* We have a branch, find out where the branch will land. */ | |
1809 | offset = cris_get_branch_short_offset (inst); | |
1810 | ||
1811 | /* Check if the offset is signed. */ | |
1812 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
1813 | { | |
1814 | offset |= 0xFF00; | |
1815 | } | |
1816 | ||
1817 | /* The offset ends with the sign bit, set it to zero. The address | |
1818 | should always be word aligned. */ | |
1819 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
1820 | ||
1821 | inst_env->branch_found = 1; | |
1822 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
1823 | ||
1824 | inst_env->slot_needed = 1; | |
1825 | inst_env->prefix_found = 0; | |
1826 | inst_env->xflag_found = 0; | |
1827 | inst_env->disable_interrupt = 1; | |
1828 | } | |
1829 | ||
1830 | /* Finds the destination for a branch with 16-bits offset. */ | |
1831 | ||
a78f21af | 1832 | static void |
29134980 OF |
1833 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
1834 | { | |
1835 | short offset; | |
1836 | ||
1837 | /* If we have a prefix or is in a delay slot it's bad. */ | |
1838 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1839 | { | |
1840 | inst_env->invalid = 1; | |
1841 | return; | |
1842 | } | |
1843 | ||
1844 | /* We have a branch, find out the offset for the branch. */ | |
1845 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
1846 | ||
1847 | /* The instruction is one word longer than normal, so add one word | |
1848 | to the PC. */ | |
1849 | inst_env->reg[REG_PC] += 2; | |
1850 | ||
1851 | inst_env->branch_found = 1; | |
1852 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
1853 | ||
1854 | ||
1855 | inst_env->slot_needed = 1; | |
1856 | inst_env->prefix_found = 0; | |
1857 | inst_env->xflag_found = 0; | |
1858 | inst_env->disable_interrupt = 1; | |
1859 | } | |
1860 | ||
1861 | /* Handles the ABS instruction. */ | |
1862 | ||
a78f21af | 1863 | static void |
29134980 OF |
1864 | abs_op (unsigned short inst, inst_env_type *inst_env) |
1865 | { | |
1866 | ||
1867 | long value; | |
1868 | ||
1869 | /* ABS can't have a prefix, so it's bad if it does. */ | |
1870 | if (inst_env->prefix_found) | |
1871 | { | |
1872 | inst_env->invalid = 1; | |
1873 | return; | |
1874 | } | |
1875 | ||
1876 | /* Check if the operation affects the PC. */ | |
1877 | if (cris_get_operand2 (inst) == REG_PC) | |
1878 | { | |
1879 | ||
1880 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
1881 | if (inst_env->slot_needed) | |
1882 | { | |
1883 | inst_env->invalid = 1; | |
1884 | return; | |
1885 | } | |
1886 | ||
1887 | value = (long) inst_env->reg[REG_PC]; | |
1888 | ||
1889 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
1890 | if (value != SIGNED_DWORD_MASK) | |
1891 | { | |
1892 | value = -value; | |
1893 | inst_env->reg[REG_PC] = (long) value; | |
1894 | } | |
1895 | } | |
1896 | ||
1897 | inst_env->slot_needed = 0; | |
1898 | inst_env->prefix_found = 0; | |
1899 | inst_env->xflag_found = 0; | |
1900 | inst_env->disable_interrupt = 0; | |
1901 | } | |
1902 | ||
1903 | /* Handles the ADDI instruction. */ | |
1904 | ||
a78f21af | 1905 | static void |
29134980 OF |
1906 | addi_op (unsigned short inst, inst_env_type *inst_env) |
1907 | { | |
1908 | /* It's invalid to have the PC as base register. And ADDI can't have | |
1909 | a prefix. */ | |
1910 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
1911 | { | |
1912 | inst_env->invalid = 1; | |
1913 | return; | |
1914 | } | |
1915 | ||
1916 | inst_env->slot_needed = 0; | |
1917 | inst_env->prefix_found = 0; | |
1918 | inst_env->xflag_found = 0; | |
1919 | inst_env->disable_interrupt = 0; | |
1920 | } | |
1921 | ||
1922 | /* Handles the ASR instruction. */ | |
1923 | ||
a78f21af | 1924 | static void |
29134980 OF |
1925 | asr_op (unsigned short inst, inst_env_type *inst_env) |
1926 | { | |
1927 | int shift_steps; | |
1928 | unsigned long value; | |
1929 | unsigned long signed_extend_mask = 0; | |
1930 | ||
1931 | /* ASR can't have a prefix, so check that it doesn't. */ | |
1932 | if (inst_env->prefix_found) | |
1933 | { | |
1934 | inst_env->invalid = 1; | |
1935 | return; | |
1936 | } | |
1937 | ||
1938 | /* Check if the PC is the target register. */ | |
1939 | if (cris_get_operand2 (inst) == REG_PC) | |
1940 | { | |
1941 | /* It's invalid to change the PC in a delay slot. */ | |
1942 | if (inst_env->slot_needed) | |
1943 | { | |
1944 | inst_env->invalid = 1; | |
1945 | return; | |
1946 | } | |
1947 | /* Get the number of bits to shift. */ | |
1948 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
1949 | value = inst_env->reg[REG_PC]; | |
1950 | ||
1951 | /* Find out how many bits the operation should apply to. */ | |
1952 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
1953 | { | |
1954 | if (value & SIGNED_BYTE_MASK) | |
1955 | { | |
1956 | signed_extend_mask = 0xFF; | |
1957 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
1958 | signed_extend_mask = ~signed_extend_mask; | |
1959 | } | |
1960 | value = value >> shift_steps; | |
1961 | value |= signed_extend_mask; | |
1962 | value &= 0xFF; | |
1963 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
1964 | inst_env->reg[REG_PC] |= value; | |
1965 | } | |
1966 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
1967 | { | |
1968 | if (value & SIGNED_WORD_MASK) | |
1969 | { | |
1970 | signed_extend_mask = 0xFFFF; | |
1971 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
1972 | signed_extend_mask = ~signed_extend_mask; | |
1973 | } | |
1974 | value = value >> shift_steps; | |
1975 | value |= signed_extend_mask; | |
1976 | value &= 0xFFFF; | |
1977 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
1978 | inst_env->reg[REG_PC] |= value; | |
1979 | } | |
1980 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
1981 | { | |
1982 | if (value & SIGNED_DWORD_MASK) | |
1983 | { | |
1984 | signed_extend_mask = 0xFFFFFFFF; | |
1985 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
1986 | signed_extend_mask = ~signed_extend_mask; | |
1987 | } | |
1988 | value = value >> shift_steps; | |
1989 | value |= signed_extend_mask; | |
1990 | inst_env->reg[REG_PC] = value; | |
1991 | } | |
1992 | } | |
1993 | inst_env->slot_needed = 0; | |
1994 | inst_env->prefix_found = 0; | |
1995 | inst_env->xflag_found = 0; | |
1996 | inst_env->disable_interrupt = 0; | |
1997 | } | |
1998 | ||
1999 | /* Handles the ASRQ instruction. */ | |
2000 | ||
a78f21af | 2001 | static void |
29134980 OF |
2002 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2003 | { | |
2004 | ||
2005 | int shift_steps; | |
2006 | unsigned long value; | |
2007 | unsigned long signed_extend_mask = 0; | |
2008 | ||
2009 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2010 | if (inst_env->prefix_found) | |
2011 | { | |
2012 | inst_env->invalid = 1; | |
2013 | return; | |
2014 | } | |
2015 | ||
2016 | /* Check if the PC is the target register. */ | |
2017 | if (cris_get_operand2 (inst) == REG_PC) | |
2018 | { | |
2019 | ||
2020 | /* It's invalid to change the PC in a delay slot. */ | |
2021 | if (inst_env->slot_needed) | |
2022 | { | |
2023 | inst_env->invalid = 1; | |
2024 | return; | |
2025 | } | |
2026 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2027 | want the the sign bit of the quick value. */ | |
2028 | shift_steps = cris_get_asr_shift_steps (inst); | |
2029 | value = inst_env->reg[REG_PC]; | |
2030 | if (value & SIGNED_DWORD_MASK) | |
2031 | { | |
2032 | signed_extend_mask = 0xFFFFFFFF; | |
2033 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2034 | signed_extend_mask = ~signed_extend_mask; | |
2035 | } | |
2036 | value = value >> shift_steps; | |
2037 | value |= signed_extend_mask; | |
2038 | inst_env->reg[REG_PC] = value; | |
2039 | } | |
2040 | inst_env->slot_needed = 0; | |
2041 | inst_env->prefix_found = 0; | |
2042 | inst_env->xflag_found = 0; | |
2043 | inst_env->disable_interrupt = 0; | |
2044 | } | |
2045 | ||
2046 | /* Handles the AX, EI and SETF instruction. */ | |
2047 | ||
a78f21af | 2048 | static void |
29134980 OF |
2049 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2050 | { | |
2051 | if (inst_env->prefix_found) | |
2052 | { | |
2053 | inst_env->invalid = 1; | |
2054 | return; | |
2055 | } | |
2056 | /* Check if the instruction is setting the X flag. */ | |
2057 | if (cris_is_xflag_bit_on (inst)) | |
2058 | { | |
2059 | inst_env->xflag_found = 1; | |
2060 | } | |
2061 | else | |
2062 | { | |
2063 | inst_env->xflag_found = 0; | |
2064 | } | |
2065 | inst_env->slot_needed = 0; | |
2066 | inst_env->prefix_found = 0; | |
2067 | inst_env->disable_interrupt = 1; | |
2068 | } | |
2069 | ||
2070 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2071 | register. Note that check_assign assumes that the caller has checked that | |
2072 | there is a prefix to this instruction. The mode check depends on this. */ | |
2073 | ||
a78f21af | 2074 | static void |
29134980 OF |
2075 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2076 | { | |
2077 | /* Check if it's an assign addressing mode. */ | |
2078 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2079 | { | |
2080 | /* Assign the prefix value to operand 1. */ | |
2081 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2082 | } | |
2083 | } | |
2084 | ||
2085 | /* Handles the 2-operand BOUND instruction. */ | |
2086 | ||
a78f21af | 2087 | static void |
29134980 OF |
2088 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2089 | { | |
2090 | /* It's invalid to have the PC as the index operand. */ | |
2091 | if (cris_get_operand2 (inst) == REG_PC) | |
2092 | { | |
2093 | inst_env->invalid = 1; | |
2094 | return; | |
2095 | } | |
2096 | /* Check if we have a prefix. */ | |
2097 | if (inst_env->prefix_found) | |
2098 | { | |
2099 | check_assign (inst, inst_env); | |
2100 | } | |
2101 | /* Check if this is an autoincrement mode. */ | |
2102 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2103 | { | |
2104 | /* It's invalid to change the PC in a delay slot. */ | |
2105 | if (inst_env->slot_needed) | |
2106 | { | |
2107 | inst_env->invalid = 1; | |
2108 | return; | |
2109 | } | |
2110 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2111 | } | |
2112 | inst_env->slot_needed = 0; | |
2113 | inst_env->prefix_found = 0; | |
2114 | inst_env->xflag_found = 0; | |
2115 | inst_env->disable_interrupt = 0; | |
2116 | } | |
2117 | ||
2118 | /* Handles the 3-operand BOUND instruction. */ | |
2119 | ||
a78f21af | 2120 | static void |
29134980 OF |
2121 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2122 | { | |
2123 | /* It's an error if we haven't got a prefix. And it's also an error | |
2124 | if the PC is the destination register. */ | |
2125 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2126 | { | |
2127 | inst_env->invalid = 1; | |
2128 | return; | |
2129 | } | |
2130 | inst_env->slot_needed = 0; | |
2131 | inst_env->prefix_found = 0; | |
2132 | inst_env->xflag_found = 0; | |
2133 | inst_env->disable_interrupt = 0; | |
2134 | } | |
2135 | ||
2136 | /* Clears the status flags in inst_env. */ | |
2137 | ||
a78f21af | 2138 | static void |
29134980 OF |
2139 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2140 | { | |
2141 | /* It's an error if we have got a prefix. */ | |
2142 | if (inst_env->prefix_found) | |
2143 | { | |
2144 | inst_env->invalid = 1; | |
2145 | return; | |
2146 | } | |
2147 | ||
2148 | inst_env->slot_needed = 0; | |
2149 | inst_env->prefix_found = 0; | |
2150 | inst_env->xflag_found = 0; | |
2151 | inst_env->disable_interrupt = 0; | |
2152 | } | |
2153 | ||
2154 | /* Clears the status flags in inst_env. */ | |
2155 | ||
a78f21af | 2156 | static void |
29134980 OF |
2157 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2158 | { | |
2159 | /* It's an error if we have got a prefix. */ | |
2160 | if (inst_env->prefix_found) | |
2161 | { | |
2162 | inst_env->invalid = 1; | |
2163 | return; | |
2164 | } | |
2165 | ||
2166 | inst_env->slot_needed = 0; | |
2167 | inst_env->prefix_found = 0; | |
2168 | inst_env->xflag_found = 0; | |
2169 | inst_env->disable_interrupt = 1; | |
2170 | } | |
2171 | ||
2172 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2173 | ||
a78f21af | 2174 | static void |
29134980 OF |
2175 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2176 | { | |
2177 | /* Check if the target is the PC. */ | |
2178 | if (cris_get_operand2 (inst) == REG_PC) | |
2179 | { | |
2180 | /* The instruction will clear the instruction's size bits. */ | |
2181 | int clear_size = cris_get_clear_size (inst); | |
2182 | if (clear_size == INST_BYTE_SIZE) | |
2183 | { | |
2184 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2185 | } | |
2186 | if (clear_size == INST_WORD_SIZE) | |
2187 | { | |
2188 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2189 | } | |
2190 | if (clear_size == INST_DWORD_SIZE) | |
2191 | { | |
2192 | inst_env->delay_slot_pc = 0x0; | |
2193 | } | |
2194 | /* The jump will be delayed with one delay slot. So we need a delay | |
2195 | slot. */ | |
2196 | inst_env->slot_needed = 1; | |
2197 | inst_env->delay_slot_pc_active = 1; | |
2198 | } | |
2199 | else | |
2200 | { | |
2201 | /* The PC will not change => no delay slot. */ | |
2202 | inst_env->slot_needed = 0; | |
2203 | } | |
2204 | inst_env->prefix_found = 0; | |
2205 | inst_env->xflag_found = 0; | |
2206 | inst_env->disable_interrupt = 0; | |
2207 | } | |
2208 | ||
2209 | /* Handles the TEST instruction if it's in register mode. */ | |
2210 | ||
a78f21af | 2211 | static void |
29134980 OF |
2212 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2213 | { | |
2214 | /* It's an error if we have got a prefix. */ | |
2215 | if (inst_env->prefix_found) | |
2216 | { | |
2217 | inst_env->invalid = 1; | |
2218 | return; | |
2219 | } | |
2220 | inst_env->slot_needed = 0; | |
2221 | inst_env->prefix_found = 0; | |
2222 | inst_env->xflag_found = 0; | |
2223 | inst_env->disable_interrupt = 0; | |
2224 | ||
2225 | } | |
2226 | ||
2227 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2228 | in register mode. */ | |
2229 | ||
a78f21af | 2230 | static void |
29134980 OF |
2231 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2232 | { | |
2233 | /* Check if we are in a prefix mode. */ | |
2234 | if (inst_env->prefix_found) | |
2235 | { | |
2236 | /* The only way the PC can change is if this instruction is in | |
2237 | assign addressing mode. */ | |
2238 | check_assign (inst, inst_env); | |
2239 | } | |
2240 | /* Indirect mode can't change the PC so just check if the mode is | |
2241 | autoincrement. */ | |
2242 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2243 | { | |
2244 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2245 | } | |
2246 | inst_env->slot_needed = 0; | |
2247 | inst_env->prefix_found = 0; | |
2248 | inst_env->xflag_found = 0; | |
2249 | inst_env->disable_interrupt = 0; | |
2250 | } | |
2251 | ||
2252 | /* Checks that the PC isn't the destination register or the instructions has | |
2253 | a prefix. */ | |
2254 | ||
a78f21af | 2255 | static void |
29134980 OF |
2256 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2257 | { | |
2258 | /* It's invalid to have the PC as the destination. The instruction can't | |
2259 | have a prefix. */ | |
2260 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2261 | { | |
2262 | inst_env->invalid = 1; | |
2263 | return; | |
2264 | } | |
2265 | ||
2266 | inst_env->slot_needed = 0; | |
2267 | inst_env->prefix_found = 0; | |
2268 | inst_env->xflag_found = 0; | |
2269 | inst_env->disable_interrupt = 0; | |
2270 | } | |
2271 | ||
2272 | /* Checks that the instruction doesn't have a prefix. */ | |
2273 | ||
a78f21af | 2274 | static void |
29134980 OF |
2275 | break_op (unsigned short inst, inst_env_type *inst_env) |
2276 | { | |
2277 | /* The instruction can't have a prefix. */ | |
2278 | if (inst_env->prefix_found) | |
2279 | { | |
2280 | inst_env->invalid = 1; | |
2281 | return; | |
2282 | } | |
2283 | ||
2284 | inst_env->slot_needed = 0; | |
2285 | inst_env->prefix_found = 0; | |
2286 | inst_env->xflag_found = 0; | |
2287 | inst_env->disable_interrupt = 1; | |
2288 | } | |
2289 | ||
2290 | /* Checks that the PC isn't the destination register and that the instruction | |
2291 | doesn't have a prefix. */ | |
2292 | ||
a78f21af | 2293 | static void |
29134980 OF |
2294 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2295 | { | |
2296 | /* It's invalid to have the PC as the destination. The instruction can't | |
2297 | have a prefix. */ | |
2298 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2299 | { | |
2300 | inst_env->invalid = 1; | |
2301 | return; | |
2302 | } | |
2303 | ||
2304 | inst_env->slot_needed = 0; | |
2305 | inst_env->prefix_found = 0; | |
2306 | inst_env->xflag_found = 0; | |
2307 | inst_env->disable_interrupt = 1; | |
2308 | } | |
2309 | ||
2310 | /* Handles the register mode JUMP instruction. */ | |
2311 | ||
a78f21af | 2312 | static void |
29134980 OF |
2313 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2314 | { | |
2315 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2316 | you can't have a prefix. */ | |
2317 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2318 | { | |
2319 | inst_env->invalid = 1; | |
2320 | return; | |
2321 | } | |
2322 | ||
2323 | /* Just change the PC. */ | |
2324 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2325 | inst_env->slot_needed = 0; | |
2326 | inst_env->prefix_found = 0; | |
2327 | inst_env->xflag_found = 0; | |
2328 | inst_env->disable_interrupt = 1; | |
2329 | } | |
2330 | ||
2331 | /* Handles the JUMP instruction for all modes except register. */ | |
2332 | ||
a78f21af AC |
2333 | static void |
2334 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2335 | { |
2336 | unsigned long newpc; | |
2337 | CORE_ADDR address; | |
2338 | ||
2339 | /* It's invalid to do a JUMP in a delay slot. */ | |
2340 | if (inst_env->slot_needed) | |
2341 | { | |
2342 | inst_env->invalid = 1; | |
2343 | } | |
2344 | else | |
2345 | { | |
2346 | /* Check if we have a prefix. */ | |
2347 | if (inst_env->prefix_found) | |
2348 | { | |
2349 | check_assign (inst, inst_env); | |
2350 | ||
2351 | /* Get the new value for the the PC. */ | |
2352 | newpc = | |
2353 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2354 | 4); | |
2355 | } | |
2356 | else | |
2357 | { | |
2358 | /* Get the new value for the PC. */ | |
2359 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2360 | newpc = read_memory_unsigned_integer (address, 4); | |
2361 | ||
2362 | /* Check if we should increment a register. */ | |
2363 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2364 | { | |
2365 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2366 | } | |
2367 | } | |
2368 | inst_env->reg[REG_PC] = newpc; | |
2369 | } | |
2370 | inst_env->slot_needed = 0; | |
2371 | inst_env->prefix_found = 0; | |
2372 | inst_env->xflag_found = 0; | |
2373 | inst_env->disable_interrupt = 1; | |
2374 | } | |
2375 | ||
2376 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2377 | ||
a78f21af | 2378 | static void |
29134980 OF |
2379 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2380 | { | |
2381 | if (inst_env->prefix_found) | |
2382 | { | |
2383 | /* The instruction has a prefix that means we are only interested if | |
2384 | the instruction is in assign mode. */ | |
2385 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2386 | { | |
2387 | /* The prefix handles the problem if we are in a delay slot. */ | |
2388 | if (cris_get_operand1 (inst) == REG_PC) | |
2389 | { | |
2390 | /* Just take care of the assign. */ | |
2391 | check_assign (inst, inst_env); | |
2392 | } | |
2393 | } | |
2394 | } | |
2395 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2396 | { | |
2397 | /* The instruction doesn't have a prefix, the only case left that we | |
2398 | are interested in is the autoincrement mode. */ | |
2399 | if (cris_get_operand1 (inst) == REG_PC) | |
2400 | { | |
2401 | /* If the PC is to be incremented it's invalid to be in a | |
2402 | delay slot. */ | |
2403 | if (inst_env->slot_needed) | |
2404 | { | |
2405 | inst_env->invalid = 1; | |
2406 | return; | |
2407 | } | |
2a9ecef2 OF |
2408 | |
2409 | /* The increment depends on the size of the special register. */ | |
2410 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2411 | { |
2412 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2413 | } | |
2a9ecef2 | 2414 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2415 | { |
2416 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2417 | } | |
2418 | else | |
2419 | { | |
2420 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2421 | } | |
2422 | } | |
2423 | } | |
2424 | inst_env->slot_needed = 0; | |
2425 | inst_env->prefix_found = 0; | |
2426 | inst_env->xflag_found = 0; | |
2427 | inst_env->disable_interrupt = 1; | |
2428 | } | |
2429 | ||
2430 | /* Handles moves from special registers (aka P-register) for all modes | |
2431 | except register. */ | |
2432 | ||
a78f21af | 2433 | static void |
29134980 OF |
2434 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2435 | { | |
2436 | if (inst_env->prefix_found) | |
2437 | { | |
2438 | /* The instruction has a prefix that means we are only interested if | |
2439 | the instruction is in assign mode. */ | |
2440 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2441 | { | |
2442 | /* The prefix handles the problem if we are in a delay slot. */ | |
2443 | if (cris_get_operand1 (inst) == REG_PC) | |
2444 | { | |
2445 | /* Just take care of the assign. */ | |
2446 | check_assign (inst, inst_env); | |
2447 | } | |
2448 | } | |
2449 | } | |
2450 | /* The instruction doesn't have a prefix, the only case left that we | |
2451 | are interested in is the autoincrement mode. */ | |
2452 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2453 | { | |
2454 | if (cris_get_operand1 (inst) == REG_PC) | |
2455 | { | |
2456 | /* If the PC is to be incremented it's invalid to be in a | |
2457 | delay slot. */ | |
2458 | if (inst_env->slot_needed) | |
2459 | { | |
2460 | inst_env->invalid = 1; | |
2461 | return; | |
2462 | } | |
2a9ecef2 OF |
2463 | |
2464 | /* The increment depends on the size of the special register. */ | |
2465 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2466 | { |
2467 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2468 | } | |
2a9ecef2 | 2469 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2470 | { |
2471 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2472 | } | |
2473 | else | |
2474 | { | |
2475 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2476 | } | |
2477 | } | |
2478 | } | |
2479 | inst_env->slot_needed = 0; | |
2480 | inst_env->prefix_found = 0; | |
2481 | inst_env->xflag_found = 0; | |
2482 | inst_env->disable_interrupt = 1; | |
2483 | } | |
2484 | ||
2485 | /* Handles moves from special registers (aka P-register) when the mode | |
2486 | is register. */ | |
2487 | ||
a78f21af | 2488 | static void |
29134980 OF |
2489 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2490 | { | |
2491 | /* Register mode move from special register can't have a prefix. */ | |
2492 | if (inst_env->prefix_found) | |
2493 | { | |
2494 | inst_env->invalid = 1; | |
2495 | return; | |
2496 | } | |
2497 | ||
2498 | if (cris_get_operand1 (inst) == REG_PC) | |
2499 | { | |
2500 | /* It's invalid to change the PC in a delay slot. */ | |
2501 | if (inst_env->slot_needed) | |
2502 | { | |
2503 | inst_env->invalid = 1; | |
2504 | return; | |
2505 | } | |
2506 | /* The destination is the PC, the jump will have a delay slot. */ | |
2507 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2508 | inst_env->slot_needed = 1; | |
2509 | inst_env->delay_slot_pc_active = 1; | |
2510 | } | |
2511 | else | |
2512 | { | |
2513 | /* If the destination isn't PC, there will be no jump. */ | |
2514 | inst_env->slot_needed = 0; | |
2515 | } | |
2516 | inst_env->prefix_found = 0; | |
2517 | inst_env->xflag_found = 0; | |
2518 | inst_env->disable_interrupt = 1; | |
2519 | } | |
2520 | ||
2521 | /* Handles the MOVEM from memory to general register instruction. */ | |
2522 | ||
a78f21af | 2523 | static void |
29134980 OF |
2524 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
2525 | { | |
2526 | if (inst_env->prefix_found) | |
2527 | { | |
2528 | /* The prefix handles the problem if we are in a delay slot. Is the | |
2529 | MOVEM instruction going to change the PC? */ | |
2530 | if (cris_get_operand2 (inst) >= REG_PC) | |
2531 | { | |
2532 | inst_env->reg[REG_PC] = | |
2533 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
2534 | } | |
2535 | /* The assign value is the value after the increment. Normally, the | |
2536 | assign value is the value before the increment. */ | |
2537 | if ((cris_get_operand1 (inst) == REG_PC) | |
2538 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2539 | { | |
2540 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2541 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2542 | } | |
2543 | } | |
2544 | else | |
2545 | { | |
2546 | /* Is the MOVEM instruction going to change the PC? */ | |
2547 | if (cris_get_operand2 (inst) == REG_PC) | |
2548 | { | |
2549 | /* It's invalid to change the PC in a delay slot. */ | |
2550 | if (inst_env->slot_needed) | |
2551 | { | |
2552 | inst_env->invalid = 1; | |
2553 | return; | |
2554 | } | |
2555 | inst_env->reg[REG_PC] = | |
2556 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
2557 | 4); | |
2558 | } | |
2559 | /* The increment is not depending on the size, instead it's depending | |
2560 | on the number of registers loaded from memory. */ | |
2561 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2562 | { | |
2563 | /* It's invalid to change the PC in a delay slot. */ | |
2564 | if (inst_env->slot_needed) | |
2565 | { | |
2566 | inst_env->invalid = 1; | |
2567 | return; | |
2568 | } | |
2569 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2570 | } | |
2571 | } | |
2572 | inst_env->slot_needed = 0; | |
2573 | inst_env->prefix_found = 0; | |
2574 | inst_env->xflag_found = 0; | |
2575 | inst_env->disable_interrupt = 0; | |
2576 | } | |
2577 | ||
2578 | /* Handles the MOVEM to memory from general register instruction. */ | |
2579 | ||
a78f21af | 2580 | static void |
29134980 OF |
2581 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
2582 | { | |
2583 | if (inst_env->prefix_found) | |
2584 | { | |
2585 | /* The assign value is the value after the increment. Normally, the | |
2586 | assign value is the value before the increment. */ | |
2587 | if ((cris_get_operand1 (inst) == REG_PC) && | |
2588 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2589 | { | |
2590 | /* The prefix handles the problem if we are in a delay slot. */ | |
2591 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2592 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2593 | } | |
2594 | } | |
2595 | else | |
2596 | { | |
2597 | /* The increment is not depending on the size, instead it's depending | |
2598 | on the number of registers loaded to memory. */ | |
2599 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2600 | { | |
2601 | /* It's invalid to change the PC in a delay slot. */ | |
2602 | if (inst_env->slot_needed) | |
2603 | { | |
2604 | inst_env->invalid = 1; | |
2605 | return; | |
2606 | } | |
2607 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2608 | } | |
2609 | } | |
2610 | inst_env->slot_needed = 0; | |
2611 | inst_env->prefix_found = 0; | |
2612 | inst_env->xflag_found = 0; | |
2613 | inst_env->disable_interrupt = 0; | |
2614 | } | |
2615 | ||
29134980 OF |
2616 | /* Handles the intructions that's not yet implemented, by setting |
2617 | inst_env->invalid to true. */ | |
2618 | ||
a78f21af | 2619 | static void |
29134980 OF |
2620 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
2621 | { | |
2622 | inst_env->invalid = 1; | |
2623 | } | |
2624 | ||
2625 | /* Handles the XOR instruction. */ | |
2626 | ||
a78f21af | 2627 | static void |
29134980 OF |
2628 | xor_op (unsigned short inst, inst_env_type *inst_env) |
2629 | { | |
2630 | /* XOR can't have a prefix. */ | |
2631 | if (inst_env->prefix_found) | |
2632 | { | |
2633 | inst_env->invalid = 1; | |
2634 | return; | |
2635 | } | |
2636 | ||
2637 | /* Check if the PC is the target. */ | |
2638 | if (cris_get_operand2 (inst) == REG_PC) | |
2639 | { | |
2640 | /* It's invalid to change the PC in a delay slot. */ | |
2641 | if (inst_env->slot_needed) | |
2642 | { | |
2643 | inst_env->invalid = 1; | |
2644 | return; | |
2645 | } | |
2646 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
2647 | } | |
2648 | inst_env->slot_needed = 0; | |
2649 | inst_env->prefix_found = 0; | |
2650 | inst_env->xflag_found = 0; | |
2651 | inst_env->disable_interrupt = 0; | |
2652 | } | |
2653 | ||
2654 | /* Handles the MULS instruction. */ | |
2655 | ||
a78f21af | 2656 | static void |
29134980 OF |
2657 | muls_op (unsigned short inst, inst_env_type *inst_env) |
2658 | { | |
2659 | /* MULS/U can't have a prefix. */ | |
2660 | if (inst_env->prefix_found) | |
2661 | { | |
2662 | inst_env->invalid = 1; | |
2663 | return; | |
2664 | } | |
2665 | ||
2666 | /* Consider it invalid if the PC is the target. */ | |
2667 | if (cris_get_operand2 (inst) == REG_PC) | |
2668 | { | |
2669 | inst_env->invalid = 1; | |
2670 | return; | |
2671 | } | |
2672 | inst_env->slot_needed = 0; | |
2673 | inst_env->prefix_found = 0; | |
2674 | inst_env->xflag_found = 0; | |
2675 | inst_env->disable_interrupt = 0; | |
2676 | } | |
2677 | ||
2678 | /* Handles the MULU instruction. */ | |
2679 | ||
a78f21af | 2680 | static void |
29134980 OF |
2681 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
2682 | { | |
2683 | /* MULS/U can't have a prefix. */ | |
2684 | if (inst_env->prefix_found) | |
2685 | { | |
2686 | inst_env->invalid = 1; | |
2687 | return; | |
2688 | } | |
2689 | ||
2690 | /* Consider it invalid if the PC is the target. */ | |
2691 | if (cris_get_operand2 (inst) == REG_PC) | |
2692 | { | |
2693 | inst_env->invalid = 1; | |
2694 | return; | |
2695 | } | |
2696 | inst_env->slot_needed = 0; | |
2697 | inst_env->prefix_found = 0; | |
2698 | inst_env->xflag_found = 0; | |
2699 | inst_env->disable_interrupt = 0; | |
2700 | } | |
2701 | ||
2702 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
2703 | The MOVE instruction is the move from source to register. */ | |
2704 | ||
a78f21af | 2705 | static void |
29134980 OF |
2706 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
2707 | unsigned long source1, unsigned long source2) | |
2708 | { | |
2709 | unsigned long pc_mask; | |
2710 | unsigned long operation_mask; | |
2711 | ||
2712 | /* Find out how many bits the operation should apply to. */ | |
2713 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2714 | { | |
2715 | pc_mask = 0xFFFFFF00; | |
2716 | operation_mask = 0xFF; | |
2717 | } | |
2718 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2719 | { | |
2720 | pc_mask = 0xFFFF0000; | |
2721 | operation_mask = 0xFFFF; | |
2722 | } | |
2723 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2724 | { | |
2725 | pc_mask = 0x0; | |
2726 | operation_mask = 0xFFFFFFFF; | |
2727 | } | |
2728 | else | |
2729 | { | |
2730 | /* The size is out of range. */ | |
2731 | inst_env->invalid = 1; | |
2732 | return; | |
2733 | } | |
2734 | ||
2735 | /* The instruction just works on uw_operation_mask bits. */ | |
2736 | source2 &= operation_mask; | |
2737 | source1 &= operation_mask; | |
2738 | ||
2739 | /* Now calculate the result. The opcode's 3 first bits separates | |
2740 | the different actions. */ | |
2741 | switch (cris_get_opcode (inst) & 7) | |
2742 | { | |
2743 | case 0: /* add */ | |
2744 | source1 += source2; | |
2745 | break; | |
2746 | ||
2747 | case 1: /* move */ | |
2748 | source1 = source2; | |
2749 | break; | |
2750 | ||
2751 | case 2: /* subtract */ | |
2752 | source1 -= source2; | |
2753 | break; | |
2754 | ||
2755 | case 3: /* compare */ | |
2756 | break; | |
2757 | ||
2758 | case 4: /* and */ | |
2759 | source1 &= source2; | |
2760 | break; | |
2761 | ||
2762 | case 5: /* or */ | |
2763 | source1 |= source2; | |
2764 | break; | |
2765 | ||
2766 | default: | |
2767 | inst_env->invalid = 1; | |
2768 | return; | |
2769 | ||
2770 | break; | |
2771 | } | |
2772 | ||
2773 | /* Make sure that the result doesn't contain more than the instruction | |
2774 | size bits. */ | |
2775 | source2 &= operation_mask; | |
2776 | ||
2777 | /* Calculate the new breakpoint address. */ | |
2778 | inst_env->reg[REG_PC] &= pc_mask; | |
2779 | inst_env->reg[REG_PC] |= source1; | |
2780 | ||
2781 | } | |
2782 | ||
2783 | /* Extends the value from either byte or word size to a dword. If the mode | |
2784 | is zero extend then the value is extended with zero. If instead the mode | |
2785 | is signed extend the sign bit of the value is taken into consideration. */ | |
2786 | ||
a78f21af | 2787 | static unsigned long |
29134980 OF |
2788 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
2789 | { | |
2790 | /* The size can be either byte or word, check which one it is. | |
2791 | Don't check the highest bit, it's indicating if it's a zero | |
2792 | or sign extend. */ | |
2793 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
2794 | { | |
2795 | /* Word size. */ | |
2796 | value &= 0xFFFF; | |
2797 | ||
2798 | /* Check if the instruction is signed extend. If so, check if value has | |
2799 | the sign bit on. */ | |
2800 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
2801 | { | |
2802 | value |= SIGNED_WORD_EXTEND_MASK; | |
2803 | } | |
2804 | } | |
2805 | else | |
2806 | { | |
2807 | /* Byte size. */ | |
2808 | value &= 0xFF; | |
2809 | ||
2810 | /* Check if the instruction is signed extend. If so, check if value has | |
2811 | the sign bit on. */ | |
2812 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
2813 | { | |
2814 | value |= SIGNED_BYTE_EXTEND_MASK; | |
2815 | } | |
2816 | } | |
2817 | /* The size should now be dword. */ | |
2818 | cris_set_size_to_dword (inst); | |
2819 | return value; | |
2820 | } | |
2821 | ||
2822 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
2823 | instruction. The MOVE instruction is the move from source to register. */ | |
2824 | ||
a78f21af | 2825 | static void |
29134980 OF |
2826 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
2827 | inst_env_type *inst_env) | |
2828 | { | |
2829 | unsigned long operand1; | |
2830 | unsigned long operand2; | |
2831 | ||
2832 | /* It's invalid to have a prefix to the instruction. This is a register | |
2833 | mode instruction and can't have a prefix. */ | |
2834 | if (inst_env->prefix_found) | |
2835 | { | |
2836 | inst_env->invalid = 1; | |
2837 | return; | |
2838 | } | |
2839 | /* Check if the instruction has PC as its target. */ | |
2840 | if (cris_get_operand2 (inst) == REG_PC) | |
2841 | { | |
2842 | if (inst_env->slot_needed) | |
2843 | { | |
2844 | inst_env->invalid = 1; | |
2845 | return; | |
2846 | } | |
2847 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 2848 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
2849 | operand2 = inst_env->reg[REG_PC]; |
2850 | ||
2851 | /* Check if it's a extend, signed or zero instruction. */ | |
2852 | if (cris_get_opcode (inst) < 4) | |
2853 | { | |
2854 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
2855 | } | |
2856 | /* Calculate the PC value after the instruction, i.e. where the | |
2857 | breakpoint should be. The order of the udw_operands is vital. */ | |
2858 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
2859 | } | |
2860 | inst_env->slot_needed = 0; | |
2861 | inst_env->prefix_found = 0; | |
2862 | inst_env->xflag_found = 0; | |
2863 | inst_env->disable_interrupt = 0; | |
2864 | } | |
2865 | ||
2866 | /* Returns the data contained at address. The size of the data is derived from | |
2867 | the size of the operation. If the instruction is a zero or signed | |
2868 | extend instruction, the size field is changed in instruction. */ | |
2869 | ||
a78f21af | 2870 | static unsigned long |
29134980 OF |
2871 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
2872 | { | |
2873 | int size = cris_get_size (*inst); | |
2874 | unsigned long value; | |
2875 | ||
2876 | /* If it's an extend instruction we don't want the signed extend bit, | |
2877 | because it influences the size. */ | |
2878 | if (cris_get_opcode (*inst) < 4) | |
2879 | { | |
2880 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
2881 | } | |
2882 | /* Is there a need for checking the size? Size should contain the number of | |
2883 | bytes to read. */ | |
2884 | size = 1 << size; | |
2885 | value = read_memory_unsigned_integer (address, size); | |
2886 | ||
2887 | /* Check if it's an extend, signed or zero instruction. */ | |
2888 | if (cris_get_opcode (*inst) < 4) | |
2889 | { | |
2890 | value = do_sign_or_zero_extend (value, inst); | |
2891 | } | |
2892 | return value; | |
2893 | } | |
2894 | ||
2895 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
2896 | instructions. The MOVE instruction is the move from source to register. */ | |
2897 | ||
a78f21af | 2898 | static void |
29134980 OF |
2899 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
2900 | inst_env_type *inst_env) | |
2901 | { | |
2902 | unsigned long operand2; | |
2903 | unsigned long operand3; | |
2904 | ||
2905 | check_assign (inst, inst_env); | |
2906 | if (cris_get_operand2 (inst) == REG_PC) | |
2907 | { | |
2908 | operand2 = inst_env->reg[REG_PC]; | |
2909 | ||
2910 | /* Get the value of the third operand. */ | |
2911 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
2912 | ||
2913 | /* Calculate the PC value after the instruction, i.e. where the | |
2914 | breakpoint should be. The order of the udw_operands is vital. */ | |
2915 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
2916 | } | |
2917 | inst_env->slot_needed = 0; | |
2918 | inst_env->prefix_found = 0; | |
2919 | inst_env->xflag_found = 0; | |
2920 | inst_env->disable_interrupt = 0; | |
2921 | } | |
2922 | ||
2923 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
2924 | OR instructions. Note that for this to work as expected, the calling | |
2925 | function must have made sure that there is a prefix to this instruction. */ | |
2926 | ||
a78f21af | 2927 | static void |
29134980 OF |
2928 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
2929 | inst_env_type *inst_env) | |
2930 | { | |
2931 | unsigned long operand2; | |
2932 | unsigned long operand3; | |
2933 | ||
2934 | if (cris_get_operand1 (inst) == REG_PC) | |
2935 | { | |
2936 | /* The PC will be changed by the instruction. */ | |
2937 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
2938 | ||
2939 | /* Get the value of the third operand. */ | |
2940 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
2941 | ||
2942 | /* Calculate the PC value after the instruction, i.e. where the | |
2943 | breakpoint should be. */ | |
2944 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
2945 | } | |
2946 | inst_env->slot_needed = 0; | |
2947 | inst_env->prefix_found = 0; | |
2948 | inst_env->xflag_found = 0; | |
2949 | inst_env->disable_interrupt = 0; | |
2950 | } | |
2951 | ||
2952 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
2953 | instructions. The MOVE instruction is the move from source to register. */ | |
2954 | ||
a78f21af | 2955 | static void |
29134980 OF |
2956 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
2957 | inst_env_type *inst_env) | |
2958 | { | |
2959 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
2960 | { | |
2961 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
2962 | SUB, AND or OR something weird is going on (if everything works these | |
2963 | instructions should end up in the three operand version). */ | |
2964 | inst_env->invalid = 1; | |
2965 | return; | |
2966 | } | |
2967 | else | |
2968 | { | |
2969 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
2970 | so use it. */ | |
2971 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
2972 | } | |
2973 | inst_env->slot_needed = 0; | |
2974 | inst_env->prefix_found = 0; | |
2975 | inst_env->xflag_found = 0; | |
2976 | inst_env->disable_interrupt = 0; | |
2977 | } | |
2978 | ||
2979 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
2980 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
2981 | source to register. */ | |
2982 | ||
a78f21af | 2983 | static void |
29134980 OF |
2984 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
2985 | inst_env_type *inst_env) | |
2986 | { | |
2987 | unsigned long operand1; | |
2988 | unsigned long operand2; | |
2989 | unsigned long operand3; | |
2990 | int size; | |
2991 | ||
2992 | /* The instruction is either an indirect or autoincrement addressing mode. | |
2993 | Check if the destination register is the PC. */ | |
2994 | if (cris_get_operand2 (inst) == REG_PC) | |
2995 | { | |
2996 | /* Must be done here, get_data_from_address may change the size | |
2997 | field. */ | |
2998 | size = cris_get_size (inst); | |
2999 | operand2 = inst_env->reg[REG_PC]; | |
3000 | ||
3001 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3002 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3003 | operand3 = get_data_from_address (&inst, operand1); | |
3004 | ||
3005 | /* Calculate the PC value after the instruction, i.e. where the | |
3006 | breakpoint should be. The order of the udw_operands is vital. */ | |
3007 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3008 | } | |
3009 | /* If this is an autoincrement addressing mode, check if the increment | |
3010 | changes the PC. */ | |
3011 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3012 | { | |
3013 | /* Get the size field. */ | |
3014 | size = cris_get_size (inst); | |
3015 | ||
3016 | /* If it's an extend instruction we don't want the signed extend bit, | |
3017 | because it influences the size. */ | |
3018 | if (cris_get_opcode (inst) < 4) | |
3019 | { | |
3020 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3021 | } | |
3022 | process_autoincrement (size, inst, inst_env); | |
3023 | } | |
3024 | inst_env->slot_needed = 0; | |
3025 | inst_env->prefix_found = 0; | |
3026 | inst_env->xflag_found = 0; | |
3027 | inst_env->disable_interrupt = 0; | |
3028 | } | |
3029 | ||
3030 | /* Handles the two-operand addressing mode, all modes except register, for | |
3031 | the ADD, SUB CMP, AND and OR instruction. */ | |
3032 | ||
a78f21af | 3033 | static void |
29134980 OF |
3034 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3035 | inst_env_type *inst_env) | |
3036 | { | |
3037 | if (inst_env->prefix_found) | |
3038 | { | |
3039 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3040 | { | |
3041 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3042 | } | |
3043 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3044 | { | |
3045 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3046 | } | |
3047 | else | |
3048 | { | |
3049 | /* The mode is invalid for a prefixed base instruction. */ | |
3050 | inst_env->invalid = 1; | |
3051 | return; | |
3052 | } | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3057 | } | |
3058 | } | |
3059 | ||
3060 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3061 | ||
a78f21af | 3062 | static void |
29134980 OF |
3063 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3064 | { | |
3065 | unsigned long operand1; | |
3066 | unsigned long operand2; | |
3067 | ||
3068 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3069 | instruction and can't have a prefix. */ | |
3070 | if (inst_env->prefix_found) | |
3071 | { | |
3072 | inst_env->invalid = 1; | |
3073 | return; | |
3074 | } | |
3075 | ||
3076 | /* Check if the instruction has PC as its target. */ | |
3077 | if (cris_get_operand2 (inst) == REG_PC) | |
3078 | { | |
3079 | if (inst_env->slot_needed) | |
3080 | { | |
3081 | inst_env->invalid = 1; | |
3082 | return; | |
3083 | } | |
3084 | operand1 = cris_get_quick_value (inst); | |
3085 | operand2 = inst_env->reg[REG_PC]; | |
3086 | ||
3087 | /* The size should now be dword. */ | |
3088 | cris_set_size_to_dword (&inst); | |
3089 | ||
3090 | /* Calculate the PC value after the instruction, i.e. where the | |
3091 | breakpoint should be. */ | |
3092 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3093 | } | |
3094 | inst_env->slot_needed = 0; | |
3095 | inst_env->prefix_found = 0; | |
3096 | inst_env->xflag_found = 0; | |
3097 | inst_env->disable_interrupt = 0; | |
3098 | } | |
3099 | ||
3100 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3101 | ||
a78f21af | 3102 | static void |
29134980 OF |
3103 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3104 | { | |
3105 | unsigned long operand1; | |
3106 | unsigned long operand2; | |
3107 | ||
3108 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3109 | instruction and can't have a prefix. */ | |
3110 | if (inst_env->prefix_found) | |
3111 | { | |
3112 | inst_env->invalid = 1; | |
3113 | return; | |
3114 | } | |
3115 | /* Check if the instruction has PC as its target. */ | |
3116 | if (cris_get_operand2 (inst) == REG_PC) | |
3117 | { | |
3118 | if (inst_env->slot_needed) | |
3119 | { | |
3120 | inst_env->invalid = 1; | |
3121 | return; | |
3122 | } | |
3123 | /* The instruction has the PC as its target register. */ | |
3124 | operand1 = cris_get_quick_value (inst); | |
3125 | operand2 = inst_env->reg[REG_PC]; | |
3126 | ||
3127 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3128 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3129 | { | |
3130 | /* sign extend */ | |
3131 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3132 | } | |
3133 | /* The size should now be dword. */ | |
3134 | cris_set_size_to_dword (&inst); | |
3135 | ||
3136 | /* Calculate the PC value after the instruction, i.e. where the | |
3137 | breakpoint should be. */ | |
3138 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3139 | } | |
3140 | inst_env->slot_needed = 0; | |
3141 | inst_env->prefix_found = 0; | |
3142 | inst_env->xflag_found = 0; | |
3143 | inst_env->disable_interrupt = 0; | |
3144 | } | |
3145 | ||
3146 | /* Translate op_type to a function and call it. */ | |
3147 | ||
a78f21af AC |
3148 | static void |
3149 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3150 | inst_env_type *inst_env) | |
29134980 OF |
3151 | { |
3152 | switch (op_type) | |
3153 | { | |
3154 | case cris_not_implemented_op: | |
3155 | not_implemented_op (inst, inst_env); | |
3156 | break; | |
3157 | ||
3158 | case cris_abs_op: | |
3159 | abs_op (inst, inst_env); | |
3160 | break; | |
3161 | ||
3162 | case cris_addi_op: | |
3163 | addi_op (inst, inst_env); | |
3164 | break; | |
3165 | ||
3166 | case cris_asr_op: | |
3167 | asr_op (inst, inst_env); | |
3168 | break; | |
3169 | ||
3170 | case cris_asrq_op: | |
3171 | asrq_op (inst, inst_env); | |
3172 | break; | |
3173 | ||
3174 | case cris_ax_ei_setf_op: | |
3175 | ax_ei_setf_op (inst, inst_env); | |
3176 | break; | |
3177 | ||
3178 | case cris_bdap_prefix: | |
3179 | bdap_prefix (inst, inst_env); | |
3180 | break; | |
3181 | ||
3182 | case cris_biap_prefix: | |
3183 | biap_prefix (inst, inst_env); | |
3184 | break; | |
3185 | ||
3186 | case cris_break_op: | |
3187 | break_op (inst, inst_env); | |
3188 | break; | |
3189 | ||
3190 | case cris_btst_nop_op: | |
3191 | btst_nop_op (inst, inst_env); | |
3192 | break; | |
3193 | ||
3194 | case cris_clearf_di_op: | |
3195 | clearf_di_op (inst, inst_env); | |
3196 | break; | |
3197 | ||
3198 | case cris_dip_prefix: | |
3199 | dip_prefix (inst, inst_env); | |
3200 | break; | |
3201 | ||
3202 | case cris_dstep_logshift_mstep_neg_not_op: | |
3203 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3204 | break; | |
3205 | ||
3206 | case cris_eight_bit_offset_branch_op: | |
3207 | eight_bit_offset_branch_op (inst, inst_env); | |
3208 | break; | |
3209 | ||
3210 | case cris_move_mem_to_reg_movem_op: | |
3211 | move_mem_to_reg_movem_op (inst, inst_env); | |
3212 | break; | |
3213 | ||
3214 | case cris_move_reg_to_mem_movem_op: | |
3215 | move_reg_to_mem_movem_op (inst, inst_env); | |
3216 | break; | |
3217 | ||
3218 | case cris_move_to_preg_op: | |
3219 | move_to_preg_op (inst, inst_env); | |
3220 | break; | |
3221 | ||
3222 | case cris_muls_op: | |
3223 | muls_op (inst, inst_env); | |
3224 | break; | |
3225 | ||
3226 | case cris_mulu_op: | |
3227 | mulu_op (inst, inst_env); | |
3228 | break; | |
3229 | ||
3230 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3231 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3232 | break; | |
3233 | ||
3234 | case cris_none_reg_mode_clear_test_op: | |
3235 | none_reg_mode_clear_test_op (inst, inst_env); | |
3236 | break; | |
3237 | ||
3238 | case cris_none_reg_mode_jump_op: | |
3239 | none_reg_mode_jump_op (inst, inst_env); | |
3240 | break; | |
3241 | ||
3242 | case cris_none_reg_mode_move_from_preg_op: | |
3243 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3244 | break; | |
3245 | ||
3246 | case cris_quick_mode_add_sub_op: | |
3247 | quick_mode_add_sub_op (inst, inst_env); | |
3248 | break; | |
3249 | ||
3250 | case cris_quick_mode_and_cmp_move_or_op: | |
3251 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3252 | break; | |
3253 | ||
3254 | case cris_quick_mode_bdap_prefix: | |
3255 | quick_mode_bdap_prefix (inst, inst_env); | |
3256 | break; | |
3257 | ||
3258 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3259 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3260 | break; | |
3261 | ||
3262 | case cris_reg_mode_clear_op: | |
3263 | reg_mode_clear_op (inst, inst_env); | |
3264 | break; | |
3265 | ||
3266 | case cris_reg_mode_jump_op: | |
3267 | reg_mode_jump_op (inst, inst_env); | |
3268 | break; | |
3269 | ||
3270 | case cris_reg_mode_move_from_preg_op: | |
3271 | reg_mode_move_from_preg_op (inst, inst_env); | |
3272 | break; | |
3273 | ||
3274 | case cris_reg_mode_test_op: | |
3275 | reg_mode_test_op (inst, inst_env); | |
3276 | break; | |
3277 | ||
3278 | case cris_scc_op: | |
3279 | scc_op (inst, inst_env); | |
3280 | break; | |
3281 | ||
3282 | case cris_sixteen_bit_offset_branch_op: | |
3283 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3284 | break; | |
3285 | ||
3286 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3287 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3288 | break; | |
3289 | ||
3290 | case cris_three_operand_bound_op: | |
3291 | three_operand_bound_op (inst, inst_env); | |
3292 | break; | |
3293 | ||
3294 | case cris_two_operand_bound_op: | |
3295 | two_operand_bound_op (inst, inst_env); | |
3296 | break; | |
3297 | ||
3298 | case cris_xor_op: | |
3299 | xor_op (inst, inst_env); | |
3300 | break; | |
3301 | } | |
3302 | } | |
3303 | ||
3304 | /* This wrapper is to avoid cris_get_assembler being called before | |
3305 | exec_bfd has been set. */ | |
3306 | ||
3307 | static int | |
a89aa300 | 3308 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3309 | { |
a89aa300 | 3310 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3311 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3312 | disassembler, even when there is no BFD. Does something like | |
3313 | "gdb; target remote; disassmeble *0x123" work? */ | |
3314 | gdb_assert (exec_bfd != NULL); | |
3315 | print_insn = cris_get_disassembler (exec_bfd); | |
3316 | gdb_assert (print_insn != NULL); | |
3317 | return print_insn (addr, info); | |
29134980 OF |
3318 | } |
3319 | ||
dbbff683 OF |
3320 | /* Copied from <asm/elf.h>. */ |
3321 | typedef unsigned long elf_greg_t; | |
3322 | ||
3323 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
3324 | typedef elf_greg_t elf_gregset_t[35]; | |
3325 | ||
3326 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3327 | ||
a78f21af | 3328 | static void |
dbbff683 OF |
3329 | supply_gregset (elf_gregset_t *gregsetp) |
3330 | { | |
3331 | int i; | |
3332 | elf_greg_t *regp = *gregsetp; | |
3333 | static char zerobuf[4] = {0}; | |
3334 | ||
3335 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3336 | knows about the actual size of each register so that's no problem. */ | |
3337 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3338 | { | |
3339 | supply_register (i, (char *)®p[i]); | |
3340 | } | |
3341 | } | |
3342 | ||
3343 | /* Use a local version of this function to get the correct types for | |
3344 | regsets, until multi-arch core support is ready. */ | |
3345 | ||
3346 | static void | |
3347 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, | |
3348 | int which, CORE_ADDR reg_addr) | |
3349 | { | |
3350 | elf_gregset_t gregset; | |
3351 | ||
3352 | switch (which) | |
3353 | { | |
3354 | case 0: | |
3355 | if (core_reg_size != sizeof (gregset)) | |
3356 | { | |
3357 | warning ("wrong size gregset struct in core file"); | |
3358 | } | |
3359 | else | |
3360 | { | |
3361 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
3362 | supply_gregset (&gregset); | |
3363 | } | |
3364 | ||
3365 | default: | |
3366 | /* We've covered all the kinds of registers we know about here, | |
3367 | so this must be something we wouldn't know what to do with | |
3368 | anyway. Just ignore it. */ | |
3369 | break; | |
3370 | } | |
3371 | } | |
3372 | ||
3373 | static struct core_fns cris_elf_core_fns = | |
3374 | { | |
3375 | bfd_target_elf_flavour, /* core_flavour */ | |
3376 | default_check_format, /* check_format */ | |
3377 | default_core_sniffer, /* core_sniffer */ | |
3378 | fetch_core_registers, /* core_read_registers */ | |
3379 | NULL /* next */ | |
3380 | }; | |
3381 | ||
3382 | /* Fetch (and possibly build) an appropriate link_map_offsets | |
8605d56e AC |
3383 | structure for native GNU/Linux CRIS targets using the struct |
3384 | offsets defined in link.h (but without actual reference to that | |
3385 | file). | |
dbbff683 | 3386 | |
8605d56e AC |
3387 | This makes it possible to access GNU/Linux CRIS shared libraries |
3388 | from a GDB that was not built on an GNU/Linux CRIS host (for cross | |
3389 | debugging). | |
dbbff683 OF |
3390 | |
3391 | See gdb/solib-svr4.h for an explanation of these fields. */ | |
3392 | ||
a78f21af | 3393 | static struct link_map_offsets * |
dbbff683 OF |
3394 | cris_linux_svr4_fetch_link_map_offsets (void) |
3395 | { | |
3396 | static struct link_map_offsets lmo; | |
3397 | static struct link_map_offsets *lmp = NULL; | |
3398 | ||
3399 | if (lmp == NULL) | |
3400 | { | |
3401 | lmp = &lmo; | |
3402 | ||
3403 | lmo.r_debug_size = 8; /* The actual size is 20 bytes, but | |
3404 | this is all we need. */ | |
3405 | lmo.r_map_offset = 4; | |
3406 | lmo.r_map_size = 4; | |
3407 | ||
3408 | lmo.link_map_size = 20; | |
3409 | ||
3410 | lmo.l_addr_offset = 0; | |
3411 | lmo.l_addr_size = 4; | |
3412 | ||
3413 | lmo.l_name_offset = 4; | |
3414 | lmo.l_name_size = 4; | |
3415 | ||
3416 | lmo.l_next_offset = 12; | |
3417 | lmo.l_next_size = 4; | |
3418 | ||
3419 | lmo.l_prev_offset = 16; | |
3420 | lmo.l_prev_size = 4; | |
3421 | } | |
3422 | ||
3423 | return lmp; | |
3424 | } | |
3425 | ||
3426 | static void | |
3427 | cris_fpless_backtrace (char *noargs, int from_tty) | |
3428 | { | |
3429 | /* Points at the instruction after the jsr (except when in innermost frame | |
3430 | where it points at the original pc). */ | |
3431 | CORE_ADDR pc = 0; | |
3432 | ||
3433 | /* Temporary variable, used for parsing from the start of the function that | |
3434 | the pc is in, up to the pc. */ | |
3435 | CORE_ADDR tmp_pc = 0; | |
3436 | CORE_ADDR sp = 0; | |
3437 | ||
3438 | /* Information about current frame. */ | |
3439 | struct symtab_and_line sal; | |
3440 | char* func_name; | |
3441 | ||
3442 | /* Present instruction. */ | |
3443 | unsigned short insn; | |
3444 | ||
3445 | /* Next instruction, lookahead. */ | |
3446 | unsigned short insn_next; | |
3447 | ||
3448 | /* This is to store the offset between sp at start of function and until we | |
3449 | reach push srp (if any). */ | |
3450 | int sp_add_later = 0; | |
3451 | int push_srp_found = 0; | |
3452 | ||
3453 | int val = 0; | |
3454 | ||
3455 | /* Frame counter. */ | |
3456 | int frame = 0; | |
3457 | ||
3458 | /* For the innermost frame, we want to look at srp in case it's a leaf | |
3459 | function (since there's no push srp in that case). */ | |
3460 | int innermost_frame = 1; | |
3461 | ||
4caf0990 AC |
3462 | deprecated_read_register_gen (PC_REGNUM, (char *) &pc); |
3463 | deprecated_read_register_gen (SP_REGNUM, (char *) &sp); | |
dbbff683 OF |
3464 | |
3465 | /* We make an explicit return when we can't find an outer frame. */ | |
3466 | while (1) | |
3467 | { | |
3468 | /* Get file name and line number. */ | |
3469 | sal = find_pc_line (pc, 0); | |
3470 | ||
3471 | /* Get function name. */ | |
3472 | find_pc_partial_function (pc, &func_name, (CORE_ADDR *) NULL, | |
3473 | (CORE_ADDR *) NULL); | |
3474 | ||
3475 | /* Print information about current frame. */ | |
3476 | printf_unfiltered ("#%i 0x%08lx in %s", frame++, pc, func_name); | |
3477 | if (sal.symtab) | |
3478 | { | |
3479 | printf_unfiltered (" at %s:%i", sal.symtab->filename, sal.line); | |
3480 | } | |
3481 | printf_unfiltered ("\n"); | |
3482 | ||
3483 | /* Get the start address of this function. */ | |
3484 | tmp_pc = get_pc_function_start (pc); | |
3485 | ||
3486 | /* Mini parser, only meant to find push sp and sub ...,sp from the start | |
3487 | of the function, up to the pc. */ | |
3488 | while (tmp_pc < pc) | |
3489 | { | |
3490 | insn = read_memory_unsigned_integer (tmp_pc, sizeof (short)); | |
3491 | tmp_pc += sizeof (short); | |
3492 | if (insn == 0xE1FC) | |
3493 | { | |
3494 | /* push <reg> 32 bit instruction */ | |
3495 | insn_next = read_memory_unsigned_integer (tmp_pc, | |
3496 | sizeof (short)); | |
3497 | tmp_pc += sizeof (short); | |
3498 | ||
3499 | /* Recognize srp. */ | |
3500 | if (insn_next == 0xBE7E) | |
3501 | { | |
3502 | /* For subsequent (not this one though) push or sub which | |
3503 | affects sp, adjust sp immediately. */ | |
3504 | push_srp_found = 1; | |
3505 | ||
3506 | /* Note: this will break if we ever encounter a | |
3507 | push vr (1 byte) or push ccr (2 bytes). */ | |
3508 | sp_add_later += 4; | |
3509 | } | |
3510 | else | |
3511 | { | |
3512 | /* Some other register was pushed. */ | |
3513 | if (push_srp_found) | |
3514 | { | |
3515 | sp += 4; | |
3516 | } | |
3517 | else | |
3518 | { | |
3519 | sp_add_later += 4; | |
3520 | } | |
3521 | } | |
3522 | } | |
3523 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
3524 | && cris_get_mode (insn) == 0x0000 | |
3525 | && cris_get_opcode (insn) == 0x000A) | |
3526 | { | |
3527 | /* subq <val>,sp */ | |
3528 | val = cris_get_quick_value (insn); | |
3529 | ||
3530 | if (push_srp_found) | |
3531 | { | |
3532 | sp += val; | |
3533 | } | |
3534 | else | |
3535 | { | |
3536 | sp_add_later += val; | |
3537 | } | |
3538 | ||
3539 | } | |
3540 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
3541 | /* Autoincrement addressing mode. */ | |
3542 | && cris_get_mode (insn) == 0x0003 | |
3543 | /* Opcode. */ | |
3544 | && ((insn) & 0x03E0) >> 5 == 0x0004) | |
3545 | { | |
3546 | /* subu <val>,sp */ | |
3547 | val = get_data_from_address (&insn, tmp_pc); | |
3548 | ||
3549 | if (push_srp_found) | |
3550 | { | |
3551 | sp += val; | |
3552 | } | |
3553 | else | |
3554 | { | |
3555 | sp_add_later += val; | |
3556 | } | |
3557 | } | |
3558 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
3559 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
3560 | && (cris_get_signed_offset (insn) < 0)) | |
3561 | { | |
3562 | /* Immediate byte offset addressing prefix word with sp as base | |
3563 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
3564 | is between 64 and 128. | |
3565 | movem r<regsave>,[sp=sp-<val>] */ | |
3566 | val = -cris_get_signed_offset (insn); | |
3567 | insn_next = read_memory_unsigned_integer (tmp_pc, | |
3568 | sizeof (short)); | |
3569 | tmp_pc += sizeof (short); | |
3570 | ||
3571 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE | |
3572 | && cris_get_opcode (insn_next) == 0x000F | |
3573 | && cris_get_size (insn_next) == 0x0003 | |
3574 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
3575 | { | |
3576 | if (push_srp_found) | |
3577 | { | |
3578 | sp += val; | |
3579 | } | |
3580 | else | |
3581 | { | |
3582 | sp_add_later += val; | |
3583 | } | |
3584 | } | |
3585 | } | |
3586 | } | |
3587 | ||
3588 | if (push_srp_found) | |
3589 | { | |
3590 | /* Reset flag. */ | |
3591 | push_srp_found = 0; | |
3592 | ||
3593 | /* sp should now point at where srp is stored on the stack. Update | |
3594 | the pc to the srp. */ | |
3595 | pc = read_memory_unsigned_integer (sp, 4); | |
3596 | } | |
3597 | else if (innermost_frame) | |
3598 | { | |
3599 | /* We couldn't find a push srp in the prologue, so this must be | |
3600 | a leaf function, and thus we use the srp register directly. | |
3601 | This should happen at most once, for the innermost function. */ | |
4caf0990 | 3602 | deprecated_read_register_gen (SRP_REGNUM, (char *) &pc); |
dbbff683 OF |
3603 | } |
3604 | else | |
3605 | { | |
3606 | /* Couldn't find an outer frame. */ | |
3607 | return; | |
3608 | } | |
3609 | ||
3610 | /* Reset flag. (In case the innermost frame wasn't a leaf, we don't | |
3611 | want to look at the srp register later either). */ | |
3612 | innermost_frame = 0; | |
3613 | ||
3614 | /* Now, add the offset for everything up to, and including push srp, | |
3615 | that was held back during the prologue parsing. */ | |
3616 | sp += sp_add_later; | |
3617 | sp_add_later = 0; | |
3618 | } | |
3619 | } | |
3620 | ||
a78f21af AC |
3621 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3622 | ||
29134980 OF |
3623 | void |
3624 | _initialize_cris_tdep (void) | |
3625 | { | |
3626 | struct cmd_list_element *c; | |
3627 | ||
3628 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3629 | ||
29134980 OF |
3630 | /* CRIS-specific user-commands. */ |
3631 | c = add_set_cmd ("cris-version", class_support, var_integer, | |
3632 | (char *) &usr_cmd_cris_version, | |
3633 | "Set the current CRIS version.", &setlist); | |
9f60d481 | 3634 | set_cmd_sfunc (c, cris_version_update); |
29134980 OF |
3635 | add_show_from_set (c, &showlist); |
3636 | ||
3637 | c = add_set_enum_cmd ("cris-mode", class_support, cris_mode_enums, | |
3638 | &usr_cmd_cris_mode, | |
3639 | "Set the current CRIS mode.", &setlist); | |
9f60d481 | 3640 | set_cmd_sfunc (c, cris_mode_update); |
29134980 OF |
3641 | add_show_from_set (c, &showlist); |
3642 | ||
dbbff683 OF |
3643 | c = add_cmd ("cris-fpless-backtrace", class_support, cris_fpless_backtrace, |
3644 | "Display call chain using the subroutine return pointer.\n" | |
3645 | "Note that this displays the address after the jump to the " | |
3646 | "subroutine.", &cmdlist); | |
3647 | ||
00e32a35 | 3648 | deprecated_add_core_fns (&cris_elf_core_fns); |
dbbff683 | 3649 | |
29134980 OF |
3650 | } |
3651 | ||
3652 | /* Prints out all target specific values. */ | |
3653 | ||
3654 | static void | |
3655 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3656 | { | |
3657 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3658 | if (tdep != NULL) | |
3659 | { | |
3660 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3661 | tdep->cris_version); | |
3662 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", | |
3663 | tdep->cris_mode); | |
29134980 OF |
3664 | } |
3665 | } | |
3666 | ||
3667 | static void | |
3668 | cris_version_update (char *ignore_args, int from_tty, | |
3669 | struct cmd_list_element *c) | |
3670 | { | |
3671 | struct gdbarch_info info; | |
3672 | ||
1868c04e AC |
3673 | /* NOTE: cagney/2002-03-17: The add_show_from_set() function clones |
3674 | the set command passed as a parameter. The clone operation will | |
3675 | include (BUG?) any ``set'' command callback, if present. | |
3676 | Commands like ``info set'' call all the ``show'' command | |
ce2826aa | 3677 | callbacks. Unfortunately, for ``show'' commands cloned from |
1868c04e AC |
3678 | ``set'', this includes callbacks belonging to ``set'' commands. |
3679 | Making this worse, this only occures if add_show_from_set() is | |
3680 | called after add_cmd_sfunc() (BUG?). */ | |
3681 | ||
29134980 | 3682 | /* From here on, trust the user's CRIS version setting. */ |
1868c04e | 3683 | if (cmd_type (c) == set_cmd) |
29134980 OF |
3684 | { |
3685 | usr_cmd_cris_version_valid = 1; | |
3686 | ||
3687 | /* Update the current architecture, if needed. */ | |
fb6ecb0f | 3688 | gdbarch_info_init (&info); |
29134980 OF |
3689 | if (!gdbarch_update_p (info)) |
3690 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3691 | } | |
3692 | } | |
3693 | ||
3694 | static void | |
3695 | cris_mode_update (char *ignore_args, int from_tty, | |
3696 | struct cmd_list_element *c) | |
3697 | { | |
3698 | struct gdbarch_info info; | |
3699 | ||
1868c04e AC |
3700 | /* NOTE: cagney/2002-03-17: The add_show_from_set() function clones |
3701 | the set command passed as a parameter. The clone operation will | |
3702 | include (BUG?) any ``set'' command callback, if present. | |
3703 | Commands like ``info set'' call all the ``show'' command | |
ce2826aa | 3704 | callbacks. Unfortunately, for ``show'' commands cloned from |
1868c04e AC |
3705 | ``set'', this includes callbacks belonging to ``set'' commands. |
3706 | Making this worse, this only occures if add_show_from_set() is | |
3707 | called after add_cmd_sfunc() (BUG?). */ | |
3708 | ||
29134980 | 3709 | /* From here on, trust the user's CRIS mode setting. */ |
1868c04e | 3710 | if (cmd_type (c) == set_cmd) |
29134980 OF |
3711 | { |
3712 | usr_cmd_cris_mode_valid = 1; | |
3713 | ||
3714 | /* Update the current architecture, if needed. */ | |
fb6ecb0f | 3715 | gdbarch_info_init (&info); |
29134980 OF |
3716 | if (!gdbarch_update_p (info)) |
3717 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3718 | } | |
3719 | } | |
3720 | ||
29134980 OF |
3721 | static struct gdbarch * |
3722 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3723 | { | |
3724 | struct gdbarch *gdbarch; | |
3725 | struct gdbarch_tdep *tdep; | |
3726 | int cris_version; | |
3727 | const char *cris_mode; | |
29134980 OF |
3728 | int register_bytes; |
3729 | ||
3730 | if (usr_cmd_cris_version_valid) | |
3731 | { | |
3732 | /* Trust the user's CRIS version setting. */ | |
3733 | cris_version = usr_cmd_cris_version; | |
3734 | } | |
3735 | else | |
3736 | { | |
3737 | /* Assume it's CRIS version 10. */ | |
3738 | cris_version = 10; | |
3739 | } | |
3740 | ||
3741 | if (usr_cmd_cris_mode_valid) | |
3742 | { | |
3743 | /* Trust the user's CRIS mode setting. */ | |
3744 | cris_mode = usr_cmd_cris_mode; | |
3745 | } | |
3746 | else if (cris_version == 10) | |
3747 | { | |
3748 | /* Assume CRIS version 10 is in user mode. */ | |
3749 | cris_mode = CRIS_MODE_USER; | |
3750 | } | |
3751 | else | |
3752 | { | |
3753 | /* Strictly speaking, older CRIS version don't have a supervisor mode, | |
3754 | but we regard its only mode as supervisor mode. */ | |
3755 | cris_mode = CRIS_MODE_SUPERVISOR; | |
3756 | } | |
3757 | ||
29134980 OF |
3758 | /* Make the current settings visible to the user. */ |
3759 | usr_cmd_cris_version = cris_version; | |
3760 | usr_cmd_cris_mode = cris_mode; | |
29134980 OF |
3761 | |
3762 | /* Find a candidate among the list of pre-declared architectures. Both | |
3763 | CRIS version and ABI must match. */ | |
3764 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3765 | arches != NULL; | |
3766 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3767 | { | |
3768 | if ((gdbarch_tdep (arches->gdbarch)->cris_version == cris_version) | |
2e4b5889 | 3769 | && (gdbarch_tdep (arches->gdbarch)->cris_mode == cris_mode)) |
29134980 OF |
3770 | return arches->gdbarch; |
3771 | } | |
3772 | ||
3773 | /* No matching architecture was found. Create a new one. */ | |
3774 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3775 | gdbarch = gdbarch_alloc (&info, tdep); | |
3776 | ||
3777 | tdep->cris_version = cris_version; | |
3778 | tdep->cris_mode = cris_mode; | |
29134980 OF |
3779 | |
3780 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
3781 | switch (info.byte_order) | |
3782 | { | |
778eb05e | 3783 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
3784 | /* Ok. */ |
3785 | break; | |
3786 | ||
d7449b42 | 3787 | case BFD_ENDIAN_BIG: |
29134980 OF |
3788 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); |
3789 | break; | |
3790 | ||
3791 | default: | |
3792 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); | |
3793 | } | |
3794 | ||
b4206d25 | 3795 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
3796 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
3797 | cris_reg_struct_has_addr); | |
3798 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); | |
29134980 | 3799 | |
29134980 OF |
3800 | /* There are 32 registers (some of which may not be implemented). */ |
3801 | set_gdbarch_num_regs (gdbarch, 32); | |
3802 | set_gdbarch_sp_regnum (gdbarch, 14); | |
29134980 | 3803 | set_gdbarch_pc_regnum (gdbarch, 15); |
29134980 OF |
3804 | set_gdbarch_register_name (gdbarch, cris_register_name); |
3805 | ||
12c266ea AC |
3806 | /* Length of ordinary registers used in push_word and a few other |
3807 | places. DEPRECATED_REGISTER_RAW_SIZE is the real way to know how | |
3808 | big a register is. */ | |
b1e29e33 | 3809 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
2e4b5889 OF |
3810 | set_gdbarch_double_bit (gdbarch, 64); |
3811 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
3812 | which means we have to set this explicitly. */ | |
3813 | set_gdbarch_long_double_bit (gdbarch, 64); | |
29134980 | 3814 | set_gdbarch_register_bytes_ok (gdbarch, cris_register_bytes_ok); |
29134980 OF |
3815 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); |
3816 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
3817 | ||
29134980 OF |
3818 | /* The total amount of space needed to store (in an array called registers) |
3819 | GDB's copy of the machine's register state. Note: We can not use | |
3820 | cris_register_size at this point, since it relies on current_gdbarch | |
3821 | being set. */ | |
3822 | switch (tdep->cris_version) | |
3823 | { | |
3824 | case 0: | |
3825 | case 1: | |
3826 | case 2: | |
3827 | case 3: | |
3828 | /* Support for these may be added later. */ | |
3829 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unsupported CRIS version"); | |
3830 | break; | |
3831 | ||
3832 | case 8: | |
3833 | case 9: | |
3834 | /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15 | |
3835 | (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits), | |
3836 | and P8 - P14 (32 bits). */ | |
3837 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4); | |
3838 | break; | |
3839 | ||
3840 | case 10: | |
3841 | case 11: | |
3842 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
3843 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
3844 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4); | |
3845 | break; | |
3846 | ||
3847 | default: | |
3848 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version"); | |
3849 | } | |
3850 | ||
b8b527c5 | 3851 | set_gdbarch_deprecated_register_bytes (gdbarch, register_bytes); |
29134980 OF |
3852 | |
3853 | /* Returns the register offset for the first byte of register regno's space | |
3854 | in the saved register state. */ | |
9c04cab7 | 3855 | set_gdbarch_deprecated_register_byte (gdbarch, cris_register_offset); |
29134980 OF |
3856 | |
3857 | /* The length of the registers in the actual machine representation. */ | |
9c04cab7 | 3858 | set_gdbarch_deprecated_register_raw_size (gdbarch, cris_register_size); |
29134980 | 3859 | |
12c266ea | 3860 | /* The largest value DEPRECATED_REGISTER_RAW_SIZE can have. */ |
a0ed5532 | 3861 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 32); |
29134980 OF |
3862 | |
3863 | /* The length of the registers in the program's representation. */ | |
9c04cab7 | 3864 | set_gdbarch_deprecated_register_virtual_size (gdbarch, cris_register_size); |
29134980 | 3865 | |
f30992d4 | 3866 | /* The largest value DEPRECATED_REGISTER_VIRTUAL_SIZE can have. */ |
a0ed5532 | 3867 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 32); |
29134980 | 3868 | |
9c04cab7 | 3869 | set_gdbarch_deprecated_register_virtual_type (gdbarch, cris_register_virtual_type); |
29134980 | 3870 | |
2e4b5889 OF |
3871 | /* Dummy frame functions. */ |
3872 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); | |
3873 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
3874 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 3875 | |
2e4b5889 | 3876 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); |
29134980 | 3877 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
3878 | |
3879 | /* The stack grows downward. */ | |
3880 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3881 | ||
3882 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
3883 | ||
2e4b5889 OF |
3884 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
3885 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
3886 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
3887 | ||
3888 | /* FIXME: Hook in the DWARF CFI frame unwinder. | |
3889 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
3890 | */ | |
3891 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); | |
3892 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 3893 | |
dbbff683 OF |
3894 | /* Use target_specific function to define link map offsets. */ |
3895 | set_solib_svr4_fetch_link_map_offsets | |
3896 | (gdbarch, cris_linux_svr4_fetch_link_map_offsets); | |
3897 | ||
36482093 AC |
3898 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3899 | disassembler, even when there is no BFD. Does something like | |
3900 | "gdb; target remote; disassmeble *0x123" work? */ | |
3901 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
3902 | ||
29134980 OF |
3903 | return gdbarch; |
3904 | } |