Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
0fb0cc75 | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
76a9d10f | 4 | Free Software Foundation, Inc. |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
a9762ec7 | 9 | This file is part of GDB. |
29134980 | 10 | |
a9762ec7 JB |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 3 of the License, or | |
14 | (at your option) any later version. | |
29134980 | 15 | |
a9762ec7 JB |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
29134980 | 20 | |
a9762ec7 JB |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
29134980 OF |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
2e4b5889 OF |
26 | #include "frame-unwind.h" |
27 | #include "frame-base.h" | |
28 | #include "trad-frame.h" | |
29 | #include "dwarf2-frame.h" | |
29134980 OF |
30 | #include "symtab.h" |
31 | #include "inferior.h" | |
32 | #include "gdbtypes.h" | |
33 | #include "gdbcore.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "target.h" | |
36 | #include "value.h" | |
37 | #include "opcode/cris.h" | |
38 | #include "arch-utils.h" | |
39 | #include "regcache.h" | |
36482093 | 40 | #include "gdb_assert.h" |
29134980 | 41 | |
9ab9195f | 42 | #include "objfiles.h" |
29134980 | 43 | |
a5f6c8f5 | 44 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 45 | #include "solib-svr4.h" |
9bbe19fb | 46 | #include "gdb_string.h" |
a89aa300 | 47 | #include "dis-asm.h" |
dbbff683 | 48 | |
29134980 OF |
49 | enum cris_num_regs |
50 | { | |
51 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
52 | NUM_FREGS = 0, | |
53 | ||
54 | /* There are 16 general registers. */ | |
55 | NUM_GENREGS = 16, | |
56 | ||
57 | /* There are 16 special registers. */ | |
c600d464 OF |
58 | NUM_SPECREGS = 16, |
59 | ||
60 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
61 | ||
62 | /* CRISv32 has 16 support registers. */ | |
63 | NUM_SUPPREGS = 16 | |
29134980 OF |
64 | }; |
65 | ||
66 | /* Register numbers of various important registers. | |
2e4b5889 | 67 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
68 | STR_REGNUM Contains the address of structure return values. |
69 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
70 | ARG1_REGNUM Contains the first parameter to a function. | |
71 | ARG2_REGNUM Contains the second parameter to a function. | |
72 | ARG3_REGNUM Contains the third parameter to a function. | |
73 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
3e8c568d UW |
74 | gdbarch_sp_regnum Contains address of top of stack. |
75 | gdbarch_pc_regnum Contains address of next instruction. | |
29134980 OF |
76 | SRP_REGNUM Subroutine return pointer register. |
77 | BRP_REGNUM Breakpoint return pointer register. */ | |
78 | ||
29134980 OF |
79 | enum cris_regnums |
80 | { | |
81 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 82 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 83 | CRIS_FP_REGNUM = 8, |
c600d464 | 84 | /* ABI related registers. */ |
29134980 OF |
85 | STR_REGNUM = 9, |
86 | RET_REGNUM = 10, | |
87 | ARG1_REGNUM = 10, | |
88 | ARG2_REGNUM = 11, | |
89 | ARG3_REGNUM = 12, | |
90 | ARG4_REGNUM = 13, | |
91 | ||
c600d464 | 92 | /* Registers which happen to be common. */ |
29134980 | 93 | VR_REGNUM = 17, |
c600d464 OF |
94 | MOF_REGNUM = 23, |
95 | SRP_REGNUM = 27, | |
96 | ||
97 | /* CRISv10 et. al. specific registers. */ | |
98 | P0_REGNUM = 16, | |
29134980 OF |
99 | P4_REGNUM = 20, |
100 | CCR_REGNUM = 21, | |
29134980 OF |
101 | P8_REGNUM = 24, |
102 | IBR_REGNUM = 25, | |
103 | IRP_REGNUM = 26, | |
29134980 | 104 | BAR_REGNUM = 28, |
2a9ecef2 | 105 | DCCR_REGNUM = 29, |
29134980 | 106 | BRP_REGNUM = 30, |
c600d464 OF |
107 | USP_REGNUM = 31, |
108 | ||
109 | /* CRISv32 specific registers. */ | |
110 | ACR_REGNUM = 15, | |
111 | BZ_REGNUM = 16, | |
112 | PID_REGNUM = 18, | |
113 | SRS_REGNUM = 19, | |
114 | WZ_REGNUM = 20, | |
115 | EXS_REGNUM = 21, | |
116 | EDA_REGNUM = 22, | |
117 | DZ_REGNUM = 24, | |
118 | EBP_REGNUM = 25, | |
119 | ERP_REGNUM = 26, | |
120 | NRP_REGNUM = 28, | |
121 | CCS_REGNUM = 29, | |
122 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
123 | SPC_REGNUM = 31, | |
124 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
125 | ||
126 | S0_REGNUM = 33, | |
127 | S1_REGNUM = 34, | |
128 | S2_REGNUM = 35, | |
129 | S3_REGNUM = 36, | |
130 | S4_REGNUM = 37, | |
131 | S5_REGNUM = 38, | |
132 | S6_REGNUM = 39, | |
133 | S7_REGNUM = 40, | |
134 | S8_REGNUM = 41, | |
135 | S9_REGNUM = 42, | |
136 | S10_REGNUM = 43, | |
137 | S11_REGNUM = 44, | |
138 | S12_REGNUM = 45, | |
139 | S13_REGNUM = 46, | |
140 | S14_REGNUM = 47, | |
141 | S15_REGNUM = 48, | |
29134980 OF |
142 | }; |
143 | ||
144 | extern const struct cris_spec_reg cris_spec_regs[]; | |
145 | ||
146 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
147 | register names and sizes. */ |
148 | static int usr_cmd_cris_version; | |
29134980 OF |
149 | |
150 | /* Indicates whether to trust the above variable. */ | |
151 | static int usr_cmd_cris_version_valid = 0; | |
152 | ||
41922353 OF |
153 | static const char cris_mode_normal[] = "normal"; |
154 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
155 | static const char *cris_modes[] = { |
156 | cris_mode_normal, | |
157 | cris_mode_guru, | |
158 | 0 | |
159 | }; | |
160 | ||
161 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
162 | type of break instruction among other things. */ | |
163 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
164 | ||
a5f6c8f5 OF |
165 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
166 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 167 | |
29134980 OF |
168 | /* CRIS architecture specific information. */ |
169 | struct gdbarch_tdep | |
170 | { | |
0e6bdb31 OF |
171 | int cris_version; |
172 | const char *cris_mode; | |
a5f6c8f5 | 173 | int cris_dwarf2_cfi; |
29134980 OF |
174 | }; |
175 | ||
a5f6c8f5 OF |
176 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
177 | ||
178 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
179 | #define SIGTRAMP_OFFSET0 0 | |
180 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
181 | #define SIGTRAMP_OFFSET1 4 | |
182 | ||
183 | static const unsigned short sigtramp_code[] = | |
184 | { | |
185 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
186 | SIGTRAMP_INSN1 /* break 13 */ | |
187 | }; | |
188 | ||
189 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
190 | ||
191 | /* Note: same length as normal sigtramp code. */ | |
192 | ||
193 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 194 | { |
a5f6c8f5 OF |
195 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
196 | SIGTRAMP_INSN1 /* break 13 */ | |
197 | }; | |
198 | ||
199 | /* If PC is in a sigtramp routine, return the address of the start of | |
200 | the routine. Otherwise, return 0. */ | |
201 | ||
202 | static CORE_ADDR | |
94afd7a6 | 203 | cris_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 204 | { |
94afd7a6 | 205 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 206 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 207 | |
94afd7a6 | 208 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
209 | return 0; |
210 | ||
e2a2a3e8 | 211 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 212 | { |
e2a2a3e8 | 213 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
214 | return 0; |
215 | ||
216 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 217 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
218 | return 0; |
219 | } | |
220 | ||
221 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
222 | return 0; | |
223 | ||
224 | return pc; | |
225 | } | |
226 | ||
227 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
228 | the routine. Otherwise, return 0. */ | |
229 | ||
230 | static CORE_ADDR | |
94afd7a6 | 231 | cris_rt_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 232 | { |
94afd7a6 | 233 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 234 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 235 | |
94afd7a6 | 236 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
237 | return 0; |
238 | ||
e2a2a3e8 | 239 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 240 | { |
e2a2a3e8 | 241 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
242 | return 0; |
243 | ||
244 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 245 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
246 | return 0; |
247 | } | |
248 | ||
249 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
250 | return 0; | |
251 | ||
252 | return pc; | |
253 | } | |
254 | ||
94afd7a6 UW |
255 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
256 | return the address of the associated sigcontext structure. */ | |
a5f6c8f5 OF |
257 | |
258 | static CORE_ADDR | |
94afd7a6 | 259 | cris_sigcontext_addr (struct frame_info *this_frame) |
a5f6c8f5 | 260 | { |
e17a4113 UW |
261 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
262 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a5f6c8f5 OF |
263 | CORE_ADDR pc; |
264 | CORE_ADDR sp; | |
265 | char buf[4]; | |
266 | ||
e17a4113 UW |
267 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
268 | sp = extract_unsigned_integer (buf, 4, byte_order); | |
a5f6c8f5 OF |
269 | |
270 | /* Look for normal sigtramp frame first. */ | |
94afd7a6 | 271 | pc = cris_sigtramp_start (this_frame); |
a5f6c8f5 OF |
272 | if (pc) |
273 | { | |
274 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
275 | struct sigcontext as its first member, meaning the SP points to | |
276 | it already. */ | |
277 | return sp; | |
278 | } | |
279 | ||
94afd7a6 | 280 | pc = cris_rt_sigtramp_start (this_frame); |
a5f6c8f5 OF |
281 | if (pc) |
282 | { | |
283 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
284 | a struct ucontext, which in turn contains a struct sigcontext. | |
285 | Magic digging: | |
286 | 4 + 4 + 128 to struct ucontext, then | |
287 | 4 + 4 + 12 to struct sigcontext. */ | |
288 | return (sp + 156); | |
289 | } | |
290 | ||
8a3fe4f8 | 291 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 292 | return 0; |
29134980 OF |
293 | } |
294 | ||
2e4b5889 | 295 | struct cris_unwind_cache |
29134980 | 296 | { |
2e4b5889 OF |
297 | /* The previous frame's inner most stack address. Used as this |
298 | frame ID's stack_addr. */ | |
299 | CORE_ADDR prev_sp; | |
300 | /* The frame's base, optionally used by the high-level debug info. */ | |
301 | CORE_ADDR base; | |
302 | int size; | |
303 | /* How far the SP and r8 (FP) have been offset from the start of | |
304 | the stack frame (as defined by the previous frame's stack | |
305 | pointer). */ | |
306 | LONGEST sp_offset; | |
307 | LONGEST r8_offset; | |
308 | int uses_frame; | |
309 | ||
310 | /* From old frame_extra_info struct. */ | |
29134980 OF |
311 | CORE_ADDR return_pc; |
312 | int leaf_function; | |
2e4b5889 OF |
313 | |
314 | /* Table indicating the location of each and every register. */ | |
315 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
316 | }; |
317 | ||
a5f6c8f5 | 318 | static struct cris_unwind_cache * |
94afd7a6 | 319 | cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
a5f6c8f5 OF |
320 | void **this_cache) |
321 | { | |
94afd7a6 | 322 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7fbe2eba | 323 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 324 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
a5f6c8f5 OF |
325 | struct cris_unwind_cache *info; |
326 | CORE_ADDR pc; | |
327 | CORE_ADDR sp; | |
328 | CORE_ADDR addr; | |
329 | char buf[4]; | |
330 | int i; | |
331 | ||
332 | if ((*this_cache)) | |
333 | return (*this_cache); | |
334 | ||
335 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
336 | (*this_cache) = info; | |
94afd7a6 | 337 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
a5f6c8f5 OF |
338 | |
339 | /* Zero all fields. */ | |
340 | info->prev_sp = 0; | |
341 | info->base = 0; | |
342 | info->size = 0; | |
343 | info->sp_offset = 0; | |
344 | info->r8_offset = 0; | |
345 | info->uses_frame = 0; | |
346 | info->return_pc = 0; | |
347 | info->leaf_function = 0; | |
348 | ||
94afd7a6 | 349 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
e17a4113 | 350 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
a5f6c8f5 | 351 | |
94afd7a6 | 352 | addr = cris_sigcontext_addr (this_frame); |
a5f6c8f5 OF |
353 | |
354 | /* Layout of the sigcontext struct: | |
355 | struct sigcontext { | |
356 | struct pt_regs regs; | |
357 | unsigned long oldmask; | |
358 | unsigned long usp; | |
359 | }; */ | |
360 | ||
c600d464 OF |
361 | if (tdep->cris_version == 10) |
362 | { | |
363 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
364 | struct pt_regs. */ | |
365 | for (i = 0; i <= 13; i++) | |
366 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
367 | ||
368 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
369 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
370 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
371 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
372 | it though since that will mean that the backtrace will show a PC | |
373 | different from what is shown when stopped. */ | |
374 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
7fbe2eba | 375 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 376 | = info->saved_regs[IRP_REGNUM]; |
7fbe2eba | 377 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4); |
c600d464 OF |
378 | } |
379 | else | |
380 | { | |
381 | /* CRISv32. */ | |
382 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
383 | struct pt_regs. */ | |
384 | for (i = 0; i <= 13; i++) | |
385 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
386 | ||
387 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
388 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
389 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
390 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
391 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
392 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
393 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
394 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
395 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
396 | ||
397 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
398 | be wrong at this point. This problem manifests itself in the | |
399 | sigaltstack.exp test case, which occasionally generates FAILs when | |
400 | the signal is received while in a delay slot. | |
401 | ||
402 | This could be solved by a couple of read_memory_unsigned_integer and a | |
403 | trad_frame_set_value. */ | |
7fbe2eba | 404 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 405 | = info->saved_regs[ERP_REGNUM]; |
c600d464 | 406 | |
7fbe2eba | 407 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr |
3e8c568d | 408 | = addr + (25 * 4); |
c600d464 | 409 | } |
a5f6c8f5 OF |
410 | |
411 | return info; | |
412 | } | |
413 | ||
414 | static void | |
94afd7a6 | 415 | cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
a5f6c8f5 OF |
416 | struct frame_id *this_id) |
417 | { | |
418 | struct cris_unwind_cache *cache = | |
94afd7a6 UW |
419 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
420 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); | |
a5f6c8f5 OF |
421 | } |
422 | ||
423 | /* Forward declaration. */ | |
424 | ||
94afd7a6 UW |
425 | static struct value *cris_frame_prev_register (struct frame_info *this_frame, |
426 | void **this_cache, int regnum); | |
427 | static struct value * | |
428 | cris_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
429 | void **this_cache, int regnum) | |
a5f6c8f5 OF |
430 | { |
431 | /* Make sure we've initialized the cache. */ | |
94afd7a6 UW |
432 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
433 | return cris_frame_prev_register (this_frame, this_cache, regnum); | |
434 | } | |
435 | ||
436 | static int | |
437 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
438 | struct frame_info *this_frame, | |
439 | void **this_cache) | |
440 | { | |
441 | if (cris_sigtramp_start (this_frame) | |
442 | || cris_rt_sigtramp_start (this_frame)) | |
443 | return 1; | |
444 | ||
445 | return 0; | |
a5f6c8f5 OF |
446 | } |
447 | ||
448 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
449 | { | |
450 | SIGTRAMP_FRAME, | |
451 | cris_sigtramp_frame_this_id, | |
94afd7a6 UW |
452 | cris_sigtramp_frame_prev_register, |
453 | NULL, | |
454 | cris_sigtramp_frame_sniffer | |
a5f6c8f5 OF |
455 | }; |
456 | ||
63807e1d | 457 | static int |
c600d464 OF |
458 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
459 | struct frame_info *this_frame) | |
460 | { | |
7fbe2eba | 461 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c600d464 OF |
462 | ULONGEST erp; |
463 | int ret = 0; | |
c600d464 | 464 | |
35488783 | 465 | if (tdep->cris_mode == cris_mode_guru) |
395f2fc2 | 466 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
0e6bdb31 | 467 | else |
395f2fc2 | 468 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
c600d464 OF |
469 | |
470 | if (erp & 0x1) | |
471 | { | |
472 | /* In delay slot - check if there's a breakpoint at the preceding | |
473 | instruction. */ | |
474 | if (breakpoint_here_p (erp & ~0x1)) | |
475 | ret = 1; | |
476 | } | |
477 | return ret; | |
478 | } | |
479 | ||
480 | /* Hardware watchpoint support. */ | |
481 | ||
482 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
483 | (any combination of read/write is fine). */ | |
484 | ||
485 | int | |
486 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
487 | { | |
1cf3db46 | 488 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
c600d464 OF |
489 | |
490 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
491 | ||
492 | if (tdep->cris_version != 32) | |
493 | return 0; | |
494 | else | |
495 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
496 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
497 | || type == bp_hardware_watchpoint) && count <= 6) | |
498 | || (type == bp_hardware_breakpoint && count <= 1)); | |
499 | } | |
500 | ||
501 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
502 | which have no alignment or length restrictions. */ | |
503 | ||
504 | int | |
505 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
506 | { | |
507 | return 1; | |
508 | } | |
509 | ||
510 | /* If the inferior has some watchpoint that triggered, return the | |
511 | address associated with that watchpoint. Otherwise, return | |
512 | zero. */ | |
513 | ||
514 | CORE_ADDR | |
515 | cris_stopped_data_address (void) | |
516 | { | |
517 | CORE_ADDR eda; | |
1b5a9a8f | 518 | eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM); |
c600d464 OF |
519 | return eda; |
520 | } | |
521 | ||
29134980 | 522 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 523 | |
29134980 OF |
524 | typedef |
525 | struct instruction_environment | |
526 | { | |
527 | unsigned long reg[NUM_GENREGS]; | |
528 | unsigned long preg[NUM_SPECREGS]; | |
529 | unsigned long branch_break_address; | |
530 | unsigned long delay_slot_pc; | |
531 | unsigned long prefix_value; | |
532 | int branch_found; | |
533 | int prefix_found; | |
534 | int invalid; | |
535 | int slot_needed; | |
536 | int delay_slot_pc_active; | |
537 | int xflag_found; | |
538 | int disable_interrupt; | |
e17a4113 | 539 | int byte_order; |
29134980 OF |
540 | } inst_env_type; |
541 | ||
29134980 OF |
542 | /* Machine-dependencies in CRIS for opcodes. */ |
543 | ||
544 | /* Instruction sizes. */ | |
545 | enum cris_instruction_sizes | |
546 | { | |
547 | INST_BYTE_SIZE = 0, | |
548 | INST_WORD_SIZE = 1, | |
549 | INST_DWORD_SIZE = 2 | |
550 | }; | |
551 | ||
552 | /* Addressing modes. */ | |
553 | enum cris_addressing_modes | |
554 | { | |
555 | REGISTER_MODE = 1, | |
556 | INDIRECT_MODE = 2, | |
557 | AUTOINC_MODE = 3 | |
558 | }; | |
559 | ||
560 | /* Prefix addressing modes. */ | |
561 | enum cris_prefix_addressing_modes | |
562 | { | |
563 | PREFIX_INDEX_MODE = 2, | |
564 | PREFIX_ASSIGN_MODE = 3, | |
565 | ||
566 | /* Handle immediate byte offset addressing mode prefix format. */ | |
567 | PREFIX_OFFSET_MODE = 2 | |
568 | }; | |
569 | ||
570 | /* Masks for opcodes. */ | |
571 | enum cris_opcode_masks | |
572 | { | |
573 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
574 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
575 | SIGNED_BYTE_MASK = 0x80, | |
576 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
577 | SIGNED_WORD_MASK = 0x8000, | |
578 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
579 | SIGNED_DWORD_MASK = 0x80000000, | |
580 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
581 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
582 | }; | |
583 | ||
584 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
585 | Bit 15 - 12 Operand2 | |
586 | 11 - 10 Mode | |
587 | 9 - 6 Opcode | |
588 | 5 - 4 Size | |
589 | 3 - 0 Operand1 */ | |
590 | ||
591 | static int | |
592 | cris_get_operand2 (unsigned short insn) | |
593 | { | |
594 | return ((insn & 0xF000) >> 12); | |
595 | } | |
596 | ||
597 | static int | |
598 | cris_get_mode (unsigned short insn) | |
599 | { | |
600 | return ((insn & 0x0C00) >> 10); | |
601 | } | |
602 | ||
603 | static int | |
604 | cris_get_opcode (unsigned short insn) | |
605 | { | |
606 | return ((insn & 0x03C0) >> 6); | |
607 | } | |
608 | ||
609 | static int | |
610 | cris_get_size (unsigned short insn) | |
611 | { | |
612 | return ((insn & 0x0030) >> 4); | |
613 | } | |
614 | ||
615 | static int | |
616 | cris_get_operand1 (unsigned short insn) | |
617 | { | |
618 | return (insn & 0x000F); | |
619 | } | |
620 | ||
621 | /* Additional functions in order to handle opcodes. */ | |
622 | ||
29134980 OF |
623 | static int |
624 | cris_get_quick_value (unsigned short insn) | |
625 | { | |
626 | return (insn & 0x003F); | |
627 | } | |
628 | ||
629 | static int | |
630 | cris_get_bdap_quick_offset (unsigned short insn) | |
631 | { | |
632 | return (insn & 0x00FF); | |
633 | } | |
634 | ||
635 | static int | |
636 | cris_get_branch_short_offset (unsigned short insn) | |
637 | { | |
638 | return (insn & 0x00FF); | |
639 | } | |
640 | ||
641 | static int | |
642 | cris_get_asr_shift_steps (unsigned long value) | |
643 | { | |
644 | return (value & 0x3F); | |
645 | } | |
646 | ||
29134980 OF |
647 | static int |
648 | cris_get_clear_size (unsigned short insn) | |
649 | { | |
650 | return ((insn) & 0xC000); | |
651 | } | |
652 | ||
653 | static int | |
654 | cris_is_signed_extend_bit_on (unsigned short insn) | |
655 | { | |
656 | return (((insn) & 0x20) == 0x20); | |
657 | } | |
658 | ||
659 | static int | |
660 | cris_is_xflag_bit_on (unsigned short insn) | |
661 | { | |
662 | return (((insn) & 0x1000) == 0x1000); | |
663 | } | |
664 | ||
665 | static void | |
666 | cris_set_size_to_dword (unsigned short *insn) | |
667 | { | |
668 | *insn &= 0xFFCF; | |
669 | *insn |= 0x20; | |
670 | } | |
671 | ||
8535cb38 | 672 | static signed char |
29134980 OF |
673 | cris_get_signed_offset (unsigned short insn) |
674 | { | |
8535cb38 | 675 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
676 | } |
677 | ||
678 | /* Calls an op function given the op-type, working on the insn and the | |
679 | inst_env. */ | |
be8626e0 MD |
680 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
681 | inst_env_type *); | |
29134980 | 682 | |
29134980 OF |
683 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
684 | struct gdbarch_list *); | |
685 | ||
29134980 OF |
686 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
687 | ||
a5f6c8f5 OF |
688 | static void set_cris_version (char *ignore_args, int from_tty, |
689 | struct cmd_list_element *c); | |
29134980 | 690 | |
0e6bdb31 OF |
691 | static void set_cris_mode (char *ignore_args, int from_tty, |
692 | struct cmd_list_element *c); | |
693 | ||
a5f6c8f5 OF |
694 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
695 | struct cmd_list_element *c); | |
29134980 | 696 | |
2e4b5889 | 697 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 698 | struct frame_info *this_frame, |
2e4b5889 OF |
699 | struct cris_unwind_cache *info); |
700 | ||
5114e29d | 701 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 702 | struct frame_info *this_frame, |
5114e29d OF |
703 | struct cris_unwind_cache *info); |
704 | ||
2e4b5889 OF |
705 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
706 | struct frame_info *next_frame); | |
707 | ||
708 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
709 | struct frame_info *next_frame); | |
710 | ||
711 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
712 | order. The below implements a FILO (stack) to do this. |
713 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
714 | |
715 | struct stack_item | |
716 | { | |
717 | int len; | |
718 | struct stack_item *prev; | |
719 | void *data; | |
720 | }; | |
721 | ||
722 | static struct stack_item * | |
723 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
724 | { | |
725 | struct stack_item *si; | |
726 | si = xmalloc (sizeof (struct stack_item)); | |
727 | si->data = xmalloc (len); | |
728 | si->len = len; | |
729 | si->prev = prev; | |
730 | memcpy (si->data, contents, len); | |
731 | return si; | |
732 | } | |
733 | ||
734 | static struct stack_item * | |
735 | pop_stack_item (struct stack_item *si) | |
736 | { | |
737 | struct stack_item *dead = si; | |
738 | si = si->prev; | |
739 | xfree (dead->data); | |
740 | xfree (dead); | |
741 | return si; | |
742 | } | |
743 | ||
744 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
745 | the saved registers of frame described by FRAME_INFO. This | |
746 | includes special registers such as pc and fp saved in special ways | |
747 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 748 | for it IS the sp for the next frame. */ |
2e4b5889 | 749 | |
63807e1d | 750 | static struct cris_unwind_cache * |
94afd7a6 | 751 | cris_frame_unwind_cache (struct frame_info *this_frame, |
2e4b5889 OF |
752 | void **this_prologue_cache) |
753 | { | |
35488783 UW |
754 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
755 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2e4b5889 OF |
756 | CORE_ADDR pc; |
757 | struct cris_unwind_cache *info; | |
758 | int i; | |
759 | ||
760 | if ((*this_prologue_cache)) | |
761 | return (*this_prologue_cache); | |
762 | ||
763 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
764 | (*this_prologue_cache) = info; | |
94afd7a6 | 765 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
2e4b5889 OF |
766 | |
767 | /* Zero all fields. */ | |
768 | info->prev_sp = 0; | |
769 | info->base = 0; | |
770 | info->size = 0; | |
771 | info->sp_offset = 0; | |
772 | info->r8_offset = 0; | |
773 | info->uses_frame = 0; | |
774 | info->return_pc = 0; | |
775 | info->leaf_function = 0; | |
776 | ||
777 | /* Prologue analysis does the rest... */ | |
35488783 | 778 | if (tdep->cris_version == 32) |
94afd7a6 | 779 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
5114e29d | 780 | else |
94afd7a6 | 781 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
2e4b5889 OF |
782 | |
783 | return info; | |
784 | } | |
785 | ||
786 | /* Given a GDB frame, determine the address of the calling function's | |
787 | frame. This will be used to create a new GDB frame struct. */ | |
788 | ||
789 | static void | |
94afd7a6 | 790 | cris_frame_this_id (struct frame_info *this_frame, |
2e4b5889 OF |
791 | void **this_prologue_cache, |
792 | struct frame_id *this_id) | |
793 | { | |
794 | struct cris_unwind_cache *info | |
94afd7a6 | 795 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
2e4b5889 OF |
796 | CORE_ADDR base; |
797 | CORE_ADDR func; | |
798 | struct frame_id id; | |
799 | ||
800 | /* The FUNC is easy. */ | |
94afd7a6 | 801 | func = get_frame_func (this_frame); |
2e4b5889 OF |
802 | |
803 | /* Hopefully the prologue analysis either correctly determined the | |
804 | frame's base (which is the SP from the previous frame), or set | |
805 | that base to "NULL". */ | |
806 | base = info->prev_sp; | |
807 | if (base == 0) | |
808 | return; | |
809 | ||
810 | id = frame_id_build (base, func); | |
811 | ||
812 | (*this_id) = id; | |
813 | } | |
814 | ||
94afd7a6 UW |
815 | static struct value * |
816 | cris_frame_prev_register (struct frame_info *this_frame, | |
817 | void **this_prologue_cache, int regnum) | |
2e4b5889 OF |
818 | { |
819 | struct cris_unwind_cache *info | |
94afd7a6 UW |
820 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
821 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2e4b5889 OF |
822 | } |
823 | ||
94afd7a6 UW |
824 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
825 | frame. The frame ID's base needs to match the TOS value saved by | |
826 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
2e4b5889 OF |
827 | |
828 | static struct frame_id | |
94afd7a6 | 829 | cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
2e4b5889 | 830 | { |
94afd7a6 UW |
831 | CORE_ADDR sp; |
832 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
833 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
2e4b5889 OF |
834 | } |
835 | ||
836 | static CORE_ADDR | |
837 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
838 | { | |
839 | /* Align to the size of an instruction (so that they can safely be | |
840 | pushed onto the stack). */ | |
841 | return sp & ~3; | |
842 | } | |
843 | ||
844 | static CORE_ADDR | |
845 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
82585c72 | 846 | CORE_ADDR sp, CORE_ADDR funaddr, |
2e4b5889 OF |
847 | struct value **args, int nargs, |
848 | struct type *value_type, | |
e4fd649a UW |
849 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
850 | struct regcache *regcache) | |
2e4b5889 OF |
851 | { |
852 | /* Allocate space sufficient for a breakpoint. */ | |
853 | sp = (sp - 4) & ~3; | |
854 | /* Store the address of that breakpoint */ | |
855 | *bp_addr = sp; | |
856 | /* CRIS always starts the call at the callee's entry point. */ | |
857 | *real_pc = funaddr; | |
858 | return sp; | |
859 | } | |
860 | ||
861 | static CORE_ADDR | |
7d9b040b | 862 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
863 | struct regcache *regcache, CORE_ADDR bp_addr, |
864 | int nargs, struct value **args, CORE_ADDR sp, | |
865 | int struct_return, CORE_ADDR struct_addr) | |
866 | { | |
e17a4113 | 867 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 OF |
868 | int stack_alloc; |
869 | int stack_offset; | |
870 | int argreg; | |
871 | int argnum; | |
872 | ||
873 | CORE_ADDR regval; | |
874 | ||
875 | /* The function's arguments and memory allocated by gdb for the arguments to | |
876 | point at reside in separate areas on the stack. | |
877 | Both frame pointers grow toward higher addresses. */ | |
878 | CORE_ADDR fp_arg; | |
879 | CORE_ADDR fp_mem; | |
880 | ||
881 | struct stack_item *si = NULL; | |
882 | ||
a5f6c8f5 | 883 | /* Push the return address. */ |
2e4b5889 OF |
884 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
885 | ||
886 | /* Are we returning a value using a structure return or a normal value | |
887 | return? struct_addr is the address of the reserved space for the return | |
888 | structure to be written on the stack. */ | |
889 | if (struct_return) | |
890 | { | |
891 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
892 | } | |
893 | ||
894 | /* Now load as many as possible of the first arguments into registers, | |
895 | and push the rest onto the stack. */ | |
896 | argreg = ARG1_REGNUM; | |
897 | stack_offset = 0; | |
898 | ||
899 | for (argnum = 0; argnum < nargs; argnum++) | |
900 | { | |
901 | int len; | |
902 | char *val; | |
903 | int reg_demand; | |
904 | int i; | |
905 | ||
4991999e | 906 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 907 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
908 | |
909 | /* How may registers worth of storage do we need for this argument? */ | |
910 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
911 | ||
912 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
913 | { | |
914 | /* Data passed by value. Fits in available register(s). */ | |
915 | for (i = 0; i < reg_demand; i++) | |
916 | { | |
f6e56ab3 | 917 | regcache_cooked_write (regcache, argreg, val); |
2e4b5889 OF |
918 | argreg++; |
919 | val += 4; | |
920 | } | |
921 | } | |
922 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
923 | { | |
924 | /* Data passed by value. Does not fit in available register(s). | |
925 | Use the register(s) first, then the stack. */ | |
926 | for (i = 0; i < reg_demand; i++) | |
927 | { | |
928 | if (argreg <= ARG4_REGNUM) | |
929 | { | |
f6e56ab3 | 930 | regcache_cooked_write (regcache, argreg, val); |
2e4b5889 OF |
931 | argreg++; |
932 | val += 4; | |
933 | } | |
934 | else | |
935 | { | |
936 | /* Push item for later so that pushed arguments | |
937 | come in the right order. */ | |
938 | si = push_stack_item (si, val, 4); | |
939 | val += 4; | |
940 | } | |
941 | } | |
942 | } | |
943 | else if (len > (2 * 4)) | |
944 | { | |
f6e56ab3 UW |
945 | /* Data passed by reference. Push copy of data onto stack |
946 | and pass pointer to this copy as argument. */ | |
947 | sp = (sp - len) & ~3; | |
948 | write_memory (sp, val, len); | |
949 | ||
950 | if (argreg <= ARG4_REGNUM) | |
951 | { | |
952 | regcache_cooked_write_unsigned (regcache, argreg, sp); | |
953 | argreg++; | |
954 | } | |
955 | else | |
956 | { | |
957 | gdb_byte buf[4]; | |
e17a4113 | 958 | store_unsigned_integer (buf, 4, byte_order, sp); |
f6e56ab3 UW |
959 | si = push_stack_item (si, buf, 4); |
960 | } | |
2e4b5889 OF |
961 | } |
962 | else | |
963 | { | |
964 | /* Data passed by value. No available registers. Put it on | |
965 | the stack. */ | |
966 | si = push_stack_item (si, val, len); | |
967 | } | |
968 | } | |
969 | ||
970 | while (si) | |
971 | { | |
972 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
973 | the function prologue. */ | |
974 | sp = (sp - si->len) & ~3; | |
975 | write_memory (sp, si->data, si->len); | |
976 | si = pop_stack_item (si); | |
977 | } | |
978 | ||
979 | /* Finally, update the SP register. */ | |
7fbe2eba | 980 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
2e4b5889 OF |
981 | |
982 | return sp; | |
983 | } | |
984 | ||
e2a2a3e8 OF |
985 | static const struct frame_unwind cris_frame_unwind = |
986 | { | |
2e4b5889 OF |
987 | NORMAL_FRAME, |
988 | cris_frame_this_id, | |
94afd7a6 UW |
989 | cris_frame_prev_register, |
990 | NULL, | |
991 | default_frame_sniffer | |
2e4b5889 OF |
992 | }; |
993 | ||
2e4b5889 | 994 | static CORE_ADDR |
94afd7a6 | 995 | cris_frame_base_address (struct frame_info *this_frame, void **this_cache) |
2e4b5889 OF |
996 | { |
997 | struct cris_unwind_cache *info | |
94afd7a6 | 998 | = cris_frame_unwind_cache (this_frame, this_cache); |
2e4b5889 OF |
999 | return info->base; |
1000 | } | |
1001 | ||
e2a2a3e8 OF |
1002 | static const struct frame_base cris_frame_base = |
1003 | { | |
2e4b5889 OF |
1004 | &cris_frame_unwind, |
1005 | cris_frame_base_address, | |
1006 | cris_frame_base_address, | |
1007 | cris_frame_base_address | |
1008 | }; | |
1009 | ||
29134980 OF |
1010 | /* Frames information. The definition of the struct frame_info is |
1011 | ||
1012 | CORE_ADDR frame | |
1013 | CORE_ADDR pc | |
5a203e44 | 1014 | enum frame_type type; |
29134980 OF |
1015 | CORE_ADDR return_pc |
1016 | int leaf_function | |
1017 | ||
1018 | If the compilation option -fno-omit-frame-pointer is present the | |
1019 | variable frame will be set to the content of R8 which is the frame | |
1020 | pointer register. | |
1021 | ||
1022 | The variable pc contains the address where execution is performed | |
1023 | in the present frame. The innermost frame contains the current content | |
1024 | of the register PC. All other frames contain the content of the | |
1025 | register PC in the next frame. | |
1026 | ||
5a203e44 AC |
1027 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1028 | (associated with a signal handler), dummy (associated with a dummy | |
1029 | frame). | |
29134980 OF |
1030 | |
1031 | The variable return_pc contains the address where execution should be | |
1032 | resumed when the present frame has finished, the return address. | |
1033 | ||
1034 | The variable leaf_function is 1 if the return address is in the register | |
1035 | SRP, and 0 if it is on the stack. | |
1036 | ||
1037 | Prologue instructions C-code. | |
1038 | The prologue may consist of (-fno-omit-frame-pointer) | |
1039 | 1) 2) | |
1040 | push srp | |
1041 | push r8 push r8 | |
1042 | move.d sp,r8 move.d sp,r8 | |
1043 | subq X,sp subq X,sp | |
1044 | movem rY,[sp] movem rY,[sp] | |
1045 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1046 | ||
1047 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1048 | ||
1049 | Note that this assumption is extremely brittle, and will break at the | |
1050 | slightest change in GCC's prologue. | |
1051 | ||
1052 | If local variables are declared or register contents are saved on stack | |
1053 | the subq-instruction will be present with X as the number of bytes | |
1054 | needed for storage. The reshuffle with respect to r8 may be performed | |
1055 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1056 | The offset U should be representable by a signed 8-bit value in all cases. | |
1057 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1058 | by another word containing the instruction. | |
1059 | ||
1060 | Degenerate cases: | |
1061 | 3) | |
1062 | push r8 | |
1063 | move.d sp,r8 | |
1064 | move.d r8,sp | |
1065 | pop r8 | |
1066 | ||
1067 | Prologue instructions C++-code. | |
1068 | Case 1) and 2) in the C-code may be followed by | |
1069 | ||
1070 | move.d r10,rS ; this | |
1071 | move.d r11,rT ; P1 | |
1072 | move.d r12,rU ; P2 | |
1073 | move.d r13,rV ; P3 | |
1074 | move.S [r8+U],rZ ; P4 | |
1075 | ||
1076 | if any of the call parameters are stored. The host expects these | |
1077 | instructions to be executed in order to get the call parameters right. */ | |
1078 | ||
1079 | /* Examine the prologue of a function. The variable ip is the address of | |
1080 | the first instruction of the prologue. The variable limit is the address | |
1081 | of the first instruction after the prologue. The variable fi contains the | |
1082 | information in struct frame_info. The variable frameless_p controls whether | |
1083 | the entire prologue is examined (0) or just enough instructions to | |
1084 | determine that it is a prologue (1). */ | |
1085 | ||
a78f21af | 1086 | static CORE_ADDR |
94afd7a6 | 1087 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
2e4b5889 | 1088 | struct cris_unwind_cache *info) |
29134980 | 1089 | { |
94afd7a6 | 1090 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
1091 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1092 | ||
29134980 OF |
1093 | /* Present instruction. */ |
1094 | unsigned short insn; | |
1095 | ||
1096 | /* Next instruction, lookahead. */ | |
1097 | unsigned short insn_next; | |
1098 | int regno; | |
1099 | ||
1100 | /* Is there a push fp? */ | |
1101 | int have_fp; | |
1102 | ||
1103 | /* Number of byte on stack used for local variables and movem. */ | |
1104 | int val; | |
1105 | ||
1106 | /* Highest register number in a movem. */ | |
1107 | int regsave; | |
1108 | ||
1109 | /* move.d r<source_register>,rS */ | |
1110 | short source_register; | |
1111 | ||
2e4b5889 OF |
1112 | /* Scan limit. */ |
1113 | int limit; | |
29134980 | 1114 | |
2e4b5889 OF |
1115 | /* This frame is with respect to a leaf until a push srp is found. */ |
1116 | if (info) | |
1117 | { | |
1118 | info->leaf_function = 1; | |
1119 | } | |
29134980 OF |
1120 | |
1121 | /* Assume nothing on stack. */ | |
1122 | val = 0; | |
1123 | regsave = -1; | |
1124 | ||
94afd7a6 | 1125 | /* If we were called without a this_frame, that means we were called |
2e4b5889 OF |
1126 | from cris_skip_prologue which already tried to find the end of the |
1127 | prologue through the symbol information. 64 instructions past current | |
1128 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
94afd7a6 | 1129 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
29134980 | 1130 | |
29134980 | 1131 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1132 | while (pc > 0 && pc < limit) |
29134980 | 1133 | { |
e17a4113 | 1134 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1135 | pc += 2; |
29134980 OF |
1136 | if (insn == 0xE1FC) |
1137 | { | |
1138 | /* push <reg> 32 bit instruction */ | |
e17a4113 | 1139 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1140 | pc += 2; |
29134980 | 1141 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1142 | if (info) |
1143 | { | |
1144 | info->sp_offset += 4; | |
1145 | } | |
dbbff683 OF |
1146 | /* This check, meant to recognize srp, used to be regno == |
1147 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1148 | if (insn_next == 0xBE7E) | |
29134980 | 1149 | { |
2e4b5889 OF |
1150 | if (info) |
1151 | { | |
1152 | info->leaf_function = 0; | |
1153 | } | |
29134980 | 1154 | } |
b4206d25 OF |
1155 | else if (insn_next == 0x8FEE) |
1156 | { | |
1157 | /* push $r8 */ | |
1158 | if (info) | |
1159 | { | |
1160 | info->r8_offset = info->sp_offset; | |
1161 | } | |
1162 | } | |
29134980 OF |
1163 | } |
1164 | else if (insn == 0x866E) | |
1165 | { | |
1166 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1167 | if (info) |
1168 | { | |
1169 | info->uses_frame = 1; | |
2e4b5889 | 1170 | } |
29134980 OF |
1171 | continue; |
1172 | } | |
7fbe2eba | 1173 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1174 | && cris_get_mode (insn) == 0x0000 |
1175 | && cris_get_opcode (insn) == 0x000A) | |
1176 | { | |
1177 | /* subq <val>,sp */ | |
2e4b5889 OF |
1178 | if (info) |
1179 | { | |
1180 | info->sp_offset += cris_get_quick_value (insn); | |
1181 | } | |
29134980 OF |
1182 | } |
1183 | else if (cris_get_mode (insn) == 0x0002 | |
1184 | && cris_get_opcode (insn) == 0x000F | |
1185 | && cris_get_size (insn) == 0x0003 | |
7fbe2eba | 1186 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1187 | { |
1188 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1189 | regsave = cris_get_operand2 (insn); |
1190 | } | |
7fbe2eba | 1191 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1192 | && ((insn & 0x0F00) >> 8) == 0x0001 |
1193 | && (cris_get_signed_offset (insn) < 0)) | |
1194 | { | |
1195 | /* Immediate byte offset addressing prefix word with sp as base | |
1196 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1197 | is between 64 and 128. | |
1198 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1199 | if (info) |
1200 | { | |
1201 | info->sp_offset += -cris_get_signed_offset (insn); | |
1202 | } | |
e17a4113 | 1203 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1204 | pc += 2; |
29134980 OF |
1205 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1206 | && cris_get_opcode (insn_next) == 0x000F | |
1207 | && cris_get_size (insn_next) == 0x0003 | |
3e8c568d | 1208 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
7fbe2eba | 1209 | (gdbarch)) |
29134980 | 1210 | { |
29134980 OF |
1211 | regsave = cris_get_operand2 (insn_next); |
1212 | } | |
1213 | else | |
1214 | { | |
1215 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1216 | pc -= 4; |
29134980 OF |
1217 | break; |
1218 | } | |
1219 | } | |
1220 | else if (cris_get_mode (insn) == 0x0001 | |
1221 | && cris_get_opcode (insn) == 0x0009 | |
1222 | && cris_get_size (insn) == 0x0002) | |
1223 | { | |
1224 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1225 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1226 | |
1227 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1228 | like (this example taken from relocate_doit): | |
1229 | move.d $pc,$r0 | |
1230 | sub.d 0xfffef426,$r0 | |
1231 | which isn't covered by the source_register check below. Question | |
1232 | is whether to add a check for this combo, or make better use of | |
1233 | the limit variable instead. */ | |
29134980 OF |
1234 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1235 | { | |
1236 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1237 | pc -= 2; |
29134980 OF |
1238 | break; |
1239 | } | |
1240 | } | |
2e4b5889 | 1241 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1242 | /* The size is a fixed-size. */ |
1243 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1244 | /* A negative offset. */ | |
1245 | && (cris_get_signed_offset (insn) < 0)) | |
1246 | { | |
1247 | /* move.S rZ,[r8-U] (?) */ | |
e17a4113 | 1248 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1249 | pc += 2; |
29134980 | 1250 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1251 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1252 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1253 | && cris_get_opcode (insn_next) == 0x000F) | |
1254 | { | |
1255 | /* move.S rZ,[r8-U] */ | |
1256 | continue; | |
1257 | } | |
1258 | else | |
1259 | { | |
1260 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1261 | pc -= 4; |
29134980 OF |
1262 | break; |
1263 | } | |
1264 | } | |
2e4b5889 | 1265 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1266 | /* The size is a fixed-size. */ |
1267 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1268 | /* A positive offset. */ | |
1269 | && (cris_get_signed_offset (insn) > 0)) | |
1270 | { | |
1271 | /* move.S [r8+U],rZ (?) */ | |
e17a4113 | 1272 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1273 | pc += 2; |
29134980 | 1274 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1275 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1276 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1277 | && cris_get_opcode (insn_next) == 0x0009 | |
1278 | && cris_get_operand1 (insn_next) == regno) | |
1279 | { | |
1280 | /* move.S [r8+U],rZ */ | |
1281 | continue; | |
1282 | } | |
1283 | else | |
1284 | { | |
1285 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1286 | pc -= 4; |
29134980 OF |
1287 | break; |
1288 | } | |
1289 | } | |
1290 | else | |
1291 | { | |
1292 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1293 | pc -= 2; |
29134980 OF |
1294 | break; |
1295 | } | |
1296 | } | |
29134980 | 1297 | |
94afd7a6 | 1298 | /* We only want to know the end of the prologue when this_frame and info |
2e4b5889 | 1299 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1300 | if (this_frame == NULL && info == NULL) |
2e4b5889 OF |
1301 | { |
1302 | return pc; | |
1303 | } | |
29134980 | 1304 | |
2e4b5889 OF |
1305 | info->size = info->sp_offset; |
1306 | ||
1307 | /* Compute the previous frame's stack pointer (which is also the | |
1308 | frame's ID's stack address), and this frame's base pointer. */ | |
1309 | if (info->uses_frame) | |
29134980 | 1310 | { |
2e4b5889 OF |
1311 | ULONGEST this_base; |
1312 | /* The SP was moved to the FP. This indicates that a new frame | |
1313 | was created. Get THIS frame's FP value by unwinding it from | |
1314 | the next frame. */ | |
94afd7a6 | 1315 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
2e4b5889 | 1316 | info->base = this_base; |
b4206d25 OF |
1317 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1318 | ||
2e4b5889 OF |
1319 | /* The FP points at the last saved register. Adjust the FP back |
1320 | to before the first saved register giving the SP. */ | |
1321 | info->prev_sp = info->base + info->r8_offset; | |
1322 | } | |
1323 | else | |
1324 | { | |
1325 | ULONGEST this_base; | |
1326 | /* Assume that the FP is this frame's SP but with that pushed | |
1327 | stack space added back. */ | |
94afd7a6 UW |
1328 | this_base = get_frame_register_unsigned (this_frame, |
1329 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1330 | info->base = this_base; |
1331 | info->prev_sp = info->base + info->size; | |
1332 | } | |
29134980 | 1333 | |
2e4b5889 OF |
1334 | /* Calculate the addresses for the saved registers on the stack. */ |
1335 | /* FIXME: The address calculation should really be done on the fly while | |
1336 | we're analyzing the prologue (we only hold one regsave value as it is | |
1337 | now). */ | |
1338 | val = info->sp_offset; | |
1339 | ||
1340 | for (regno = regsave; regno >= 0; regno--) | |
1341 | { | |
1342 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1343 | val -= 4; | |
1344 | } | |
1345 | ||
1346 | /* The previous frame's SP needed to be computed. Save the computed | |
1347 | value. */ | |
3e8c568d | 1348 | trad_frame_set_value (info->saved_regs, |
7fbe2eba | 1349 | gdbarch_sp_regnum (gdbarch), info->prev_sp); |
2e4b5889 OF |
1350 | |
1351 | if (!info->leaf_function) | |
1352 | { | |
b4206d25 OF |
1353 | /* SRP saved on the stack. But where? */ |
1354 | if (info->r8_offset == 0) | |
1355 | { | |
1356 | /* R8 not pushed yet. */ | |
1357 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1358 | } | |
1359 | else | |
1360 | { | |
1361 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1362 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1363 | } | |
29134980 | 1364 | } |
2e4b5889 OF |
1365 | |
1366 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
7fbe2eba | 1367 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1368 | = info->saved_regs[SRP_REGNUM]; |
2e4b5889 OF |
1369 | |
1370 | return pc; | |
29134980 OF |
1371 | } |
1372 | ||
5114e29d | 1373 | static CORE_ADDR |
94afd7a6 | 1374 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
5114e29d OF |
1375 | struct cris_unwind_cache *info) |
1376 | { | |
94afd7a6 | 1377 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5114e29d OF |
1378 | ULONGEST this_base; |
1379 | ||
1380 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1381 | meant to be a full-fledged prologue scanner. It is only needed for | |
1382 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1383 | ||
1384 | * PLT stubs (library calls) | |
1385 | * call dummys | |
1386 | * signal trampolines | |
1387 | ||
1388 | For those cases, it is assumed that there is no actual prologue; that | |
1389 | the stack pointer is not adjusted, and (as a consequence) the return | |
1390 | address is not pushed onto the stack. */ | |
1391 | ||
94afd7a6 | 1392 | /* We only want to know the end of the prologue when this_frame and info |
5114e29d | 1393 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1394 | if (this_frame == NULL && info == NULL) |
5114e29d OF |
1395 | { |
1396 | return pc; | |
1397 | } | |
1398 | ||
1399 | /* The SP is assumed to be unaltered. */ | |
94afd7a6 UW |
1400 | this_base = get_frame_register_unsigned (this_frame, |
1401 | gdbarch_sp_regnum (gdbarch)); | |
5114e29d OF |
1402 | info->base = this_base; |
1403 | info->prev_sp = this_base; | |
1404 | ||
1405 | /* The PC is assumed to be found in SRP. */ | |
7fbe2eba | 1406 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1407 | = info->saved_regs[SRP_REGNUM]; |
5114e29d OF |
1408 | |
1409 | return pc; | |
1410 | } | |
1411 | ||
29134980 OF |
1412 | /* Advance pc beyond any function entry prologue instructions at pc |
1413 | to reach some "real" code. */ | |
1414 | ||
29134980 OF |
1415 | /* Given a PC value corresponding to the start of a function, return the PC |
1416 | of the first instruction after the function prologue. */ | |
1417 | ||
a78f21af | 1418 | static CORE_ADDR |
6093d2eb | 1419 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
29134980 | 1420 | { |
35488783 | 1421 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2e4b5889 OF |
1422 | CORE_ADDR func_addr, func_end; |
1423 | struct symtab_and_line sal; | |
29134980 OF |
1424 | CORE_ADDR pc_after_prologue; |
1425 | ||
2e4b5889 OF |
1426 | /* If we have line debugging information, then the end of the prologue |
1427 | should the first assembly instruction of the first source line. */ | |
1428 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1429 | { | |
1430 | sal = find_pc_line (func_addr, 0); | |
1431 | if (sal.end > 0 && sal.end < func_end) | |
1432 | return sal.end; | |
1433 | } | |
29134980 | 1434 | |
35488783 | 1435 | if (tdep->cris_version == 32) |
5114e29d OF |
1436 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
1437 | else | |
1438 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1439 | ||
29134980 OF |
1440 | return pc_after_prologue; |
1441 | } | |
1442 | ||
2e4b5889 OF |
1443 | static CORE_ADDR |
1444 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1445 | { | |
1446 | ULONGEST pc; | |
11411de3 DJ |
1447 | pc = frame_unwind_register_unsigned (next_frame, |
1448 | gdbarch_pc_regnum (gdbarch)); | |
2e4b5889 OF |
1449 | return pc; |
1450 | } | |
1451 | ||
1452 | static CORE_ADDR | |
1453 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1454 | { | |
1455 | ULONGEST sp; | |
11411de3 DJ |
1456 | sp = frame_unwind_register_unsigned (next_frame, |
1457 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1458 | return sp; |
1459 | } | |
1460 | ||
29134980 OF |
1461 | /* Use the program counter to determine the contents and size of a breakpoint |
1462 | instruction. It returns a pointer to a string of bytes that encode a | |
1463 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1464 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1465 | the breakpoint should be inserted. */ | |
1466 | ||
a78f21af | 1467 | static const unsigned char * |
67d57894 | 1468 | cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
29134980 | 1469 | { |
35488783 | 1470 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
0e6bdb31 OF |
1471 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1472 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1473 | *lenptr = 2; |
1474 | ||
35488783 | 1475 | if (tdep->cris_mode == cris_mode_guru) |
0e6bdb31 OF |
1476 | return break15_insn; |
1477 | else | |
1478 | return break8_insn; | |
29134980 OF |
1479 | } |
1480 | ||
29134980 OF |
1481 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1482 | 0 otherwise. */ | |
1483 | ||
a78f21af | 1484 | static int |
35488783 UW |
1485 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
1486 | struct cris_spec_reg spec_reg) | |
29134980 | 1487 | { |
35488783 UW |
1488 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1489 | int version = tdep->cris_version; | |
29134980 OF |
1490 | |
1491 | switch (spec_reg.applicable_version) | |
1492 | { | |
1493 | case cris_ver_version_all: | |
1494 | return 1; | |
1495 | case cris_ver_warning: | |
1496 | /* Indeterminate/obsolete. */ | |
1497 | return 0; | |
29134980 OF |
1498 | case cris_ver_v0_3: |
1499 | return (version >= 0 && version <= 3); | |
1500 | case cris_ver_v3p: | |
1501 | return (version >= 3); | |
1502 | case cris_ver_v8: | |
1503 | return (version == 8 || version == 9); | |
1504 | case cris_ver_v8p: | |
1505 | return (version >= 8); | |
c600d464 OF |
1506 | case cris_ver_v0_10: |
1507 | return (version >= 0 && version <= 10); | |
1508 | case cris_ver_v3_10: | |
1509 | return (version >= 3 && version <= 10); | |
1510 | case cris_ver_v8_10: | |
1511 | return (version >= 8 && version <= 10); | |
1512 | case cris_ver_v10: | |
1513 | return (version == 10); | |
29134980 OF |
1514 | case cris_ver_v10p: |
1515 | return (version >= 10); | |
c600d464 OF |
1516 | case cris_ver_v32p: |
1517 | return (version >= 32); | |
29134980 OF |
1518 | default: |
1519 | /* Invalid cris version. */ | |
1520 | return 0; | |
1521 | } | |
1522 | } | |
1523 | ||
1d94326f AC |
1524 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1525 | register, -1 for an invalid register. */ | |
1526 | ||
1527 | static int | |
be8626e0 | 1528 | cris_register_size (struct gdbarch *gdbarch, int regno) |
1d94326f | 1529 | { |
be8626e0 | 1530 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1d94326f AC |
1531 | int i; |
1532 | int spec_regno; | |
1533 | ||
1534 | if (regno >= 0 && regno < NUM_GENREGS) | |
1535 | { | |
1536 | /* General registers (R0 - R15) are 32 bits. */ | |
1537 | return 4; | |
1538 | } | |
c600d464 | 1539 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1540 | { |
1541 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1542 | Adjust regno accordingly. */ | |
1543 | spec_regno = regno - NUM_GENREGS; | |
1544 | ||
c600d464 | 1545 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1546 | { |
1547 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1548 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
1d94326f AC |
1549 | /* Go with the first applicable register. */ |
1550 | return cris_spec_regs[i].reg_size; | |
1551 | } | |
1552 | /* Special register not applicable to this CRIS version. */ | |
1553 | return 0; | |
1554 | } | |
be8626e0 MD |
1555 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
1556 | && regno < gdbarch_num_regs (gdbarch)) | |
1d94326f | 1557 | { |
c600d464 OF |
1558 | /* This will apply to CRISv32 only where there are additional registers |
1559 | after the special registers (pseudo PC and support registers). */ | |
1560 | return 4; | |
1d94326f | 1561 | } |
c600d464 OF |
1562 | |
1563 | ||
1564 | return -1; | |
1d94326f AC |
1565 | } |
1566 | ||
29134980 OF |
1567 | /* Nonzero if regno should not be fetched from the target. This is the case |
1568 | for unimplemented (size 0) and non-existant registers. */ | |
1569 | ||
a78f21af | 1570 | static int |
64a3914f | 1571 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
29134980 | 1572 | { |
64a3914f | 1573 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1574 | || (cris_register_size (gdbarch, regno) == 0)); |
29134980 OF |
1575 | } |
1576 | ||
1577 | /* Nonzero if regno should not be written to the target, for various | |
1578 | reasons. */ | |
1579 | ||
a78f21af | 1580 | static int |
64a3914f | 1581 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
29134980 OF |
1582 | { |
1583 | /* There are three kinds of registers we refuse to write to. | |
1584 | 1. Those that not implemented. | |
1585 | 2. Those that are read-only (depends on the processor mode). | |
1586 | 3. Those registers to which a write has no effect. | |
1587 | */ | |
1588 | ||
f57d151a | 1589 | if (regno < 0 |
64a3914f | 1590 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1591 | || cris_register_size (gdbarch, regno) == 0) |
29134980 OF |
1592 | /* Not implemented. */ |
1593 | return 1; | |
1594 | ||
1595 | else if (regno == VR_REGNUM) | |
1596 | /* Read-only. */ | |
1597 | return 1; | |
1598 | ||
1599 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1600 | /* Writing has no effect. */ | |
1601 | return 1; | |
1602 | ||
a5f6c8f5 OF |
1603 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1604 | agent decide whether they are writable. */ | |
29134980 OF |
1605 | |
1606 | return 0; | |
1607 | } | |
1608 | ||
c600d464 OF |
1609 | /* Nonzero if regno should not be fetched from the target. This is the case |
1610 | for unimplemented (size 0) and non-existant registers. */ | |
1611 | ||
1612 | static int | |
64a3914f | 1613 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
c600d464 | 1614 | { |
64a3914f | 1615 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1616 | || (cris_register_size (gdbarch, regno) == 0)); |
c600d464 OF |
1617 | } |
1618 | ||
1619 | /* Nonzero if regno should not be written to the target, for various | |
1620 | reasons. */ | |
1621 | ||
1622 | static int | |
64a3914f | 1623 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1624 | { |
1625 | /* There are three kinds of registers we refuse to write to. | |
1626 | 1. Those that not implemented. | |
1627 | 2. Those that are read-only (depends on the processor mode). | |
1628 | 3. Those registers to which a write has no effect. | |
1629 | */ | |
1630 | ||
f57d151a | 1631 | if (regno < 0 |
64a3914f | 1632 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1633 | || cris_register_size (gdbarch, regno) == 0) |
c600d464 OF |
1634 | /* Not implemented. */ |
1635 | return 1; | |
1636 | ||
1637 | else if (regno == VR_REGNUM) | |
1638 | /* Read-only. */ | |
1639 | return 1; | |
1640 | ||
1641 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1642 | /* Writing has no effect. */ | |
1643 | return 1; | |
1644 | ||
1645 | /* Many special registers are read-only in user mode. Let the debug | |
1646 | agent decide whether they are writable. */ | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
29134980 OF |
1651 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1652 | of data in register regno. */ | |
1653 | ||
a78f21af | 1654 | static struct type * |
c1d546cd | 1655 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1656 | { |
7fbe2eba | 1657 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1658 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1659 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1660 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1661 | return builtin_type (gdbarch)->builtin_data_ptr; |
7fbe2eba | 1662 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 OF |
1663 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
1664 | /* Note: R8 taken care of previous clause. */ | |
df4df182 | 1665 | return builtin_type (gdbarch)->builtin_uint32; |
a5f6c8f5 | 1666 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
df4df182 | 1667 | return builtin_type (gdbarch)->builtin_uint16; |
a5f6c8f5 | 1668 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
df4df182 | 1669 | return builtin_type (gdbarch)->builtin_uint8; |
29134980 | 1670 | else |
a5f6c8f5 | 1671 | /* Invalid (unimplemented) register. */ |
df4df182 | 1672 | return builtin_type (gdbarch)->builtin_int0; |
29134980 OF |
1673 | } |
1674 | ||
c600d464 OF |
1675 | static struct type * |
1676 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1677 | { | |
7fbe2eba | 1678 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1679 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1680 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1681 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1682 | return builtin_type (gdbarch)->builtin_data_ptr; |
c600d464 OF |
1683 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
1684 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1685 | || (regno == PID_REGNUM) | |
1686 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1687 | /* Note: R8 and SP taken care of by previous clause. */ | |
df4df182 | 1688 | return builtin_type (gdbarch)->builtin_uint32; |
c600d464 | 1689 | else if (regno == WZ_REGNUM) |
df4df182 | 1690 | return builtin_type (gdbarch)->builtin_uint16; |
c600d464 | 1691 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
df4df182 | 1692 | return builtin_type (gdbarch)->builtin_uint8; |
c600d464 OF |
1693 | else |
1694 | { | |
1695 | /* Invalid (unimplemented) register. Should not happen as there are | |
1696 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1697 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
df4df182 | 1698 | return builtin_type (gdbarch)->builtin_int0; |
c600d464 OF |
1699 | } |
1700 | } | |
1701 | ||
2e4b5889 OF |
1702 | /* Stores a function return value of type type, where valbuf is the address |
1703 | of the value to be stored. */ | |
29134980 | 1704 | |
2e4b5889 | 1705 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1706 | |
2e4b5889 OF |
1707 | static void |
1708 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1709 | const void *valbuf) | |
29134980 | 1710 | { |
e17a4113 UW |
1711 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1712 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2e4b5889 OF |
1713 | ULONGEST val; |
1714 | int len = TYPE_LENGTH (type); | |
29134980 | 1715 | |
2e4b5889 | 1716 | if (len <= 4) |
29134980 | 1717 | { |
2e4b5889 | 1718 | /* Put the return value in R10. */ |
e17a4113 | 1719 | val = extract_unsigned_integer (valbuf, len, byte_order); |
2e4b5889 | 1720 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
29134980 | 1721 | } |
2e4b5889 | 1722 | else if (len <= 8) |
29134980 | 1723 | { |
2e4b5889 | 1724 | /* Put the return value in R10 and R11. */ |
e17a4113 | 1725 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
2e4b5889 | 1726 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
e17a4113 | 1727 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order); |
2e4b5889 | 1728 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
29134980 | 1729 | } |
2e4b5889 | 1730 | else |
8a3fe4f8 | 1731 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1732 | } |
1733 | ||
2e4b5889 OF |
1734 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1735 | unimplemented register. */ | |
29134980 | 1736 | |
c600d464 | 1737 | static const char * |
35488783 | 1738 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1739 | { |
1740 | int spec_regno; | |
1741 | int i; | |
1742 | ||
1743 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1744 | Adjust regno accordingly. */ | |
1745 | spec_regno = regno - NUM_GENREGS; | |
1746 | ||
1747 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1748 | when searching. */ | |
1749 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1750 | { | |
1751 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1752 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
c600d464 OF |
1753 | /* Go with the first applicable register. */ |
1754 | return cris_spec_regs[i].name; | |
1755 | } | |
1756 | /* Special register not applicable to this CRIS version. */ | |
1757 | return NULL; | |
1758 | } | |
1759 | ||
2e4b5889 | 1760 | static const char * |
d93859e2 | 1761 | cris_register_name (struct gdbarch *gdbarch, int regno) |
2e4b5889 OF |
1762 | { |
1763 | static char *cris_genreg_names[] = | |
1764 | { "r0", "r1", "r2", "r3", \ | |
1765 | "r4", "r5", "r6", "r7", \ | |
1766 | "r8", "r9", "r10", "r11", \ | |
1767 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1768 | |
2e4b5889 | 1769 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1770 | { |
2e4b5889 OF |
1771 | /* General register. */ |
1772 | return cris_genreg_names[regno]; | |
29134980 | 1773 | } |
d93859e2 | 1774 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
29134980 | 1775 | { |
35488783 | 1776 | return cris_special_register_name (gdbarch, regno); |
c600d464 OF |
1777 | } |
1778 | else | |
1779 | { | |
1780 | /* Invalid register. */ | |
2e4b5889 OF |
1781 | return NULL; |
1782 | } | |
c600d464 OF |
1783 | } |
1784 | ||
1785 | static const char * | |
d93859e2 | 1786 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1787 | { |
1788 | static char *crisv32_genreg_names[] = | |
1789 | { "r0", "r1", "r2", "r3", \ | |
1790 | "r4", "r5", "r6", "r7", \ | |
1791 | "r8", "r9", "r10", "r11", \ | |
1792 | "r12", "r13", "sp", "acr" | |
1793 | }; | |
1794 | ||
1795 | static char *crisv32_sreg_names[] = | |
1796 | { "s0", "s1", "s2", "s3", \ | |
1797 | "s4", "s5", "s6", "s7", \ | |
1798 | "s8", "s9", "s10", "s11", \ | |
1799 | "s12", "s13", "s14", "s15" | |
1800 | }; | |
1801 | ||
1802 | if (regno >= 0 && regno < NUM_GENREGS) | |
1803 | { | |
1804 | /* General register. */ | |
1805 | return crisv32_genreg_names[regno]; | |
1806 | } | |
1807 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1808 | { | |
35488783 | 1809 | return cris_special_register_name (gdbarch, regno); |
c600d464 | 1810 | } |
d93859e2 | 1811 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
c600d464 OF |
1812 | { |
1813 | return "pc"; | |
1814 | } | |
1815 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1816 | { | |
1817 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1818 | } | |
2e4b5889 OF |
1819 | else |
1820 | { | |
1821 | /* Invalid register. */ | |
1822 | return NULL; | |
29134980 | 1823 | } |
29134980 OF |
1824 | } |
1825 | ||
a5f6c8f5 OF |
1826 | /* Convert DWARF register number REG to the appropriate register |
1827 | number used by GDB. */ | |
1828 | ||
2e4b5889 | 1829 | static int |
d3f73121 | 1830 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
29134980 | 1831 | { |
a5f6c8f5 OF |
1832 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1833 | numbering, MOF is 18). | |
1834 | Adapted from gcc/config/cris/cris.h. */ | |
1835 | static int cris_dwarf_regmap[] = { | |
1836 | 0, 1, 2, 3, | |
1837 | 4, 5, 6, 7, | |
1838 | 8, 9, 10, 11, | |
1839 | 12, 13, 14, 15, | |
1840 | 27, -1, -1, -1, | |
1841 | -1, -1, -1, 23, | |
1842 | -1, -1, -1, 27, | |
1843 | -1, -1, -1, -1 | |
1844 | }; | |
1845 | int regnum = -1; | |
1846 | ||
1847 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1848 | regnum = cris_dwarf_regmap[reg]; | |
1849 | ||
1850 | if (regnum == -1) | |
8a3fe4f8 | 1851 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1852 | |
1853 | return regnum; | |
1854 | } | |
1855 | ||
1856 | /* DWARF-2 frame support. */ | |
1857 | ||
1858 | static void | |
1859 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1860 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1861 | struct frame_info *this_frame) |
a5f6c8f5 OF |
1862 | { |
1863 | /* The return address column. */ | |
7fbe2eba | 1864 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
a5f6c8f5 OF |
1865 | reg->how = DWARF2_FRAME_REG_RA; |
1866 | ||
1867 | /* The call frame address. */ | |
7fbe2eba | 1868 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 | 1869 | reg->how = DWARF2_FRAME_REG_CFA; |
29134980 OF |
1870 | } |
1871 | ||
2e4b5889 OF |
1872 | /* Extract from an array regbuf containing the raw register state a function |
1873 | return value of type type, and copy that, in virtual format, into | |
1874 | valbuf. */ | |
1875 | ||
1876 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1877 | |
2e4b5889 OF |
1878 | static void |
1879 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1880 | void *valbuf) | |
29134980 | 1881 | { |
e17a4113 UW |
1882 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1883 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2e4b5889 OF |
1884 | ULONGEST val; |
1885 | int len = TYPE_LENGTH (type); | |
29134980 | 1886 | |
2e4b5889 | 1887 | if (len <= 4) |
29134980 | 1888 | { |
2e4b5889 OF |
1889 | /* Get the return value from R10. */ |
1890 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
e17a4113 | 1891 | store_unsigned_integer (valbuf, len, byte_order, val); |
29134980 | 1892 | } |
2e4b5889 | 1893 | else if (len <= 8) |
29134980 | 1894 | { |
2e4b5889 OF |
1895 | /* Get the return value from R10 and R11. */ |
1896 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
e17a4113 | 1897 | store_unsigned_integer (valbuf, 4, byte_order, val); |
2e4b5889 | 1898 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
e17a4113 | 1899 | store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val); |
29134980 | 1900 | } |
2e4b5889 | 1901 | else |
8a3fe4f8 | 1902 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1903 | } |
1904 | ||
b4206d25 OF |
1905 | /* Handle the CRIS return value convention. */ |
1906 | ||
1907 | static enum return_value_convention | |
c055b101 CV |
1908 | cris_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1909 | struct type *type, struct regcache *regcache, | |
1910 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b4206d25 OF |
1911 | { |
1912 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1913 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1914 | || TYPE_LENGTH (type) > 8) | |
1915 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1916 | goes on the stack. */ | |
1917 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1918 | ||
1919 | if (readbuf) | |
1920 | cris_extract_return_value (type, regcache, readbuf); | |
1921 | if (writebuf) | |
1922 | cris_store_return_value (type, regcache, writebuf); | |
1923 | ||
1924 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1925 | } | |
1926 | ||
29134980 OF |
1927 | /* Calculates a value that measures how good inst_args constraints an |
1928 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1929 | ||
1930 | static int | |
1931 | constraint (unsigned int insn, const signed char *inst_args, | |
1932 | inst_env_type *inst_env) | |
1933 | { | |
1934 | int retval = 0; | |
1935 | int tmp, i; | |
1936 | ||
1937 | const char *s = inst_args; | |
1938 | ||
1939 | for (; *s; s++) | |
1940 | switch (*s) | |
1941 | { | |
1942 | case 'm': | |
1943 | if ((insn & 0x30) == 0x30) | |
1944 | return -1; | |
1945 | break; | |
1946 | ||
1947 | case 'S': | |
1948 | /* A prefix operand. */ | |
1949 | if (inst_env->prefix_found) | |
1950 | break; | |
1951 | else | |
1952 | return -1; | |
1953 | ||
1954 | case 'B': | |
1955 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1956 | valid "push" size. In case of special register, it may be != 4. */ | |
1957 | if (inst_env->prefix_found) | |
1958 | break; | |
1959 | else | |
1960 | return -1; | |
1961 | ||
1962 | case 'D': | |
1963 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1964 | if (!retval) | |
1965 | return -1; | |
1966 | else | |
1967 | retval += 4; | |
1968 | break; | |
1969 | ||
1970 | case 'P': | |
1971 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1972 | |
1973 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1974 | { | |
1975 | /* Since we match four bits, we will give a value of | |
1976 | 4 - 1 = 3 in a match. If there is a corresponding | |
1977 | exact match of a special register in another pattern, it | |
1978 | will get a value of 4, which will be higher. This should | |
1979 | be correct in that an exact pattern would match better that | |
1980 | a general pattern. | |
1981 | Note that there is a reason for not returning zero; the | |
1982 | pattern for "clear" is partly matched in the bit-pattern | |
1983 | (the two lower bits must be zero), while the bit-pattern | |
1984 | for a move from a special register is matched in the | |
1985 | register constraint. | |
1986 | This also means we will will have a race condition if | |
1987 | there is a partly match in three bits in the bit pattern. */ | |
1988 | if (tmp == cris_spec_regs[i].number) | |
1989 | { | |
1990 | retval += 3; | |
1991 | break; | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1996 | return -1; |
1997 | break; | |
1998 | } | |
1999 | return retval; | |
2000 | } | |
2001 | ||
2002 | /* Returns the number of bits set in the variable value. */ | |
2003 | ||
2004 | static int | |
2005 | number_of_bits (unsigned int value) | |
2006 | { | |
2007 | int number_of_bits = 0; | |
2008 | ||
2009 | while (value != 0) | |
2010 | { | |
2011 | number_of_bits += 1; | |
2012 | value &= (value - 1); | |
2013 | } | |
2014 | return number_of_bits; | |
2015 | } | |
2016 | ||
2017 | /* Finds the address that should contain the single step breakpoint(s). | |
2018 | It stems from code in cris-dis.c. */ | |
2019 | ||
2020 | static int | |
2021 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
2022 | { | |
2023 | int i; | |
2024 | int max_level_of_match = -1; | |
2025 | int max_matched = -1; | |
2026 | int level_of_match; | |
2027 | ||
2028 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
2029 | { | |
2030 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
2031 | && ((cris_opcodes[i].lose & insn) == 0) |
2032 | /* Only CRISv10 instructions, please. */ | |
2033 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
2034 | { |
2035 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
2036 | if (level_of_match >= 0) | |
2037 | { | |
2038 | level_of_match += | |
2039 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
2040 | if (level_of_match > max_level_of_match) | |
2041 | { | |
2042 | max_matched = i; | |
2043 | max_level_of_match = level_of_match; | |
2044 | if (level_of_match == 16) | |
2045 | { | |
2046 | /* All bits matched, cannot find better. */ | |
2047 | break; | |
2048 | } | |
2049 | } | |
2050 | } | |
2051 | } | |
2052 | } | |
2053 | return max_matched; | |
2054 | } | |
2055 | ||
2056 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2057 | actually an internal error. */ | |
2058 | ||
2059 | static int | |
0b1b3e42 | 2060 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
29134980 OF |
2061 | { |
2062 | int i; | |
2063 | int offset; | |
2064 | unsigned short insn; | |
7fbe2eba | 2065 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2066 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
29134980 OF |
2067 | |
2068 | /* Create a local register image and set the initial state. */ | |
2069 | for (i = 0; i < NUM_GENREGS; i++) | |
2070 | { | |
0b1b3e42 UW |
2071 | inst_env->reg[i] = |
2072 | (unsigned long) get_frame_register_unsigned (frame, i); | |
29134980 OF |
2073 | } |
2074 | offset = NUM_GENREGS; | |
2075 | for (i = 0; i < NUM_SPECREGS; i++) | |
2076 | { | |
0b1b3e42 UW |
2077 | inst_env->preg[i] = |
2078 | (unsigned long) get_frame_register_unsigned (frame, offset + i); | |
29134980 OF |
2079 | } |
2080 | inst_env->branch_found = 0; | |
2081 | inst_env->slot_needed = 0; | |
2082 | inst_env->delay_slot_pc_active = 0; | |
2083 | inst_env->prefix_found = 0; | |
2084 | inst_env->invalid = 0; | |
2085 | inst_env->xflag_found = 0; | |
2086 | inst_env->disable_interrupt = 0; | |
e17a4113 | 2087 | inst_env->byte_order = byte_order; |
29134980 OF |
2088 | |
2089 | /* Look for a step target. */ | |
2090 | do | |
2091 | { | |
2092 | /* Read an instruction from the client. */ | |
3e8c568d | 2093 | insn = read_memory_unsigned_integer |
e17a4113 | 2094 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
29134980 OF |
2095 | |
2096 | /* If the instruction is not in a delay slot the new content of the | |
2097 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2098 | that simple. Since a instruction in a delay slot cannot change | |
2099 | the content of the PC, it does not matter what value PC will have. | |
2100 | Just make sure it is a valid instruction. */ | |
2101 | if (!inst_env->delay_slot_pc_active) | |
2102 | { | |
7fbe2eba | 2103 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; |
29134980 OF |
2104 | } |
2105 | else | |
2106 | { | |
2107 | inst_env->delay_slot_pc_active = 0; | |
7fbe2eba | 2108 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 2109 | = inst_env->delay_slot_pc; |
29134980 OF |
2110 | } |
2111 | /* Analyse the present instruction. */ | |
2112 | i = find_cris_op (insn, inst_env); | |
2113 | if (i == -1) | |
2114 | { | |
2115 | inst_env->invalid = 1; | |
2116 | } | |
2117 | else | |
2118 | { | |
be8626e0 | 2119 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); |
29134980 OF |
2120 | } |
2121 | } while (!inst_env->invalid | |
2122 | && (inst_env->prefix_found || inst_env->xflag_found | |
2123 | || inst_env->slot_needed)); | |
2124 | return i; | |
2125 | } | |
2126 | ||
2127 | /* There is no hardware single-step support. The function find_step_target | |
2128 | digs through the opcodes in order to find all possible targets. | |
2129 | Either one ordinary target or two targets for branches may be found. */ | |
2130 | ||
e6590a1b | 2131 | static int |
0b1b3e42 | 2132 | cris_software_single_step (struct frame_info *frame) |
29134980 | 2133 | { |
a6d9a66e | 2134 | struct gdbarch *gdbarch = get_frame_arch (frame); |
29134980 | 2135 | inst_env_type inst_env; |
8181d85f | 2136 | |
e0cd558a UW |
2137 | /* Analyse the present instruction environment and insert |
2138 | breakpoints. */ | |
0b1b3e42 | 2139 | int status = find_step_target (frame, &inst_env); |
e0cd558a | 2140 | if (status == -1) |
29134980 | 2141 | { |
e0cd558a UW |
2142 | /* Could not find a target. Things are likely to go downhill |
2143 | from here. */ | |
2144 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2145 | } |
2146 | else | |
e0cd558a UW |
2147 | { |
2148 | /* Insert at most two breakpoints. One for the next PC content | |
2149 | and possibly another one for a branch, jump, etc. */ | |
a6d9a66e UW |
2150 | CORE_ADDR next_pc |
2151 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; | |
2152 | insert_single_step_breakpoint (gdbarch, next_pc); | |
e0cd558a UW |
2153 | if (inst_env.branch_found |
2154 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2155 | { | |
2156 | CORE_ADDR branch_target_address | |
2157 | = (CORE_ADDR) inst_env.branch_break_address; | |
a6d9a66e | 2158 | insert_single_step_breakpoint (gdbarch, branch_target_address); |
e0cd558a UW |
2159 | } |
2160 | } | |
e6590a1b UW |
2161 | |
2162 | return 1; | |
29134980 OF |
2163 | } |
2164 | ||
2165 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2166 | ||
a78f21af | 2167 | static void |
29134980 OF |
2168 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2169 | { | |
2170 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2171 | instruction (not 100% sure). */ | |
2172 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2173 | { | |
2174 | inst_env->invalid = 1; | |
2175 | return; | |
2176 | } | |
2177 | ||
2178 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2179 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2180 | ||
2181 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2182 | need updating. */ | |
2183 | inst_env->slot_needed = 0; | |
2184 | inst_env->prefix_found = 1; | |
2185 | } | |
2186 | ||
2187 | /* Updates the autoincrement register. The size of the increment is derived | |
2188 | from the size of the operation. The PC is always kept aligned on even | |
2189 | word addresses. */ | |
2190 | ||
a78f21af | 2191 | static void |
29134980 OF |
2192 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2193 | { | |
2194 | if (size == INST_BYTE_SIZE) | |
2195 | { | |
2196 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2197 | ||
2198 | /* The PC must be word aligned, so increase the PC with one | |
2199 | word even if the size is byte. */ | |
2200 | if (cris_get_operand1 (inst) == REG_PC) | |
2201 | { | |
2202 | inst_env->reg[REG_PC] += 1; | |
2203 | } | |
2204 | } | |
2205 | else if (size == INST_WORD_SIZE) | |
2206 | { | |
2207 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2208 | } | |
2209 | else if (size == INST_DWORD_SIZE) | |
2210 | { | |
2211 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2212 | } | |
2213 | else | |
2214 | { | |
2215 | /* Invalid size. */ | |
2216 | inst_env->invalid = 1; | |
2217 | } | |
2218 | } | |
2219 | ||
2a9ecef2 OF |
2220 | /* Just a forward declaration. */ |
2221 | ||
a78f21af | 2222 | static unsigned long get_data_from_address (unsigned short *inst, |
e17a4113 UW |
2223 | CORE_ADDR address, |
2224 | enum bfd_endian byte_order); | |
2a9ecef2 | 2225 | |
29134980 OF |
2226 | /* Calculates the prefix value for the general case of offset addressing |
2227 | mode. */ | |
2228 | ||
a78f21af | 2229 | static void |
29134980 OF |
2230 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2231 | { | |
2232 | ||
2233 | long offset; | |
2234 | ||
2235 | /* It's invalid to be in a delay slot. */ | |
2236 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2237 | { | |
2238 | inst_env->invalid = 1; | |
2239 | return; | |
2240 | } | |
2241 | ||
fa4e4598 OF |
2242 | /* The calculation of prefix_value used to be after process_autoincrement, |
2243 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2244 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2245 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2246 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2247 | ||
2248 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2249 | inst_env->prefix_value += | |
e17a4113 UW |
2250 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
2251 | inst_env->byte_order); | |
2a9ecef2 | 2252 | |
fa4e4598 OF |
2253 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2254 | { | |
2255 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2256 | } | |
2257 | ||
29134980 OF |
2258 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2259 | need updating. */ | |
2260 | inst_env->slot_needed = 0; | |
2261 | inst_env->prefix_found = 1; | |
2262 | } | |
2263 | ||
2264 | /* Calculates the prefix value for the index addressing mode. */ | |
2265 | ||
a78f21af | 2266 | static void |
29134980 OF |
2267 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2268 | { | |
2269 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2270 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2271 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2272 | { | |
2273 | inst_env->invalid = 1; | |
2274 | return; | |
2275 | } | |
2276 | ||
2277 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2278 | ||
2279 | /* The offset is the operand2 value shifted the size of the instruction | |
2280 | to the left. */ | |
2281 | inst_env->prefix_value += | |
2282 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2283 | ||
2284 | /* If the PC is operand1 (base) the address used is the address after | |
2285 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2286 | for the prefix operation). */ | |
2287 | if (cris_get_operand1 (inst) == REG_PC) | |
2288 | { | |
2289 | inst_env->prefix_value += 2; | |
2290 | } | |
2291 | ||
2292 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2293 | need updating. */ | |
2294 | inst_env->slot_needed = 0; | |
2295 | inst_env->xflag_found = 0; | |
2296 | inst_env->prefix_found = 1; | |
2297 | } | |
2298 | ||
2299 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2300 | ||
a78f21af | 2301 | static void |
29134980 OF |
2302 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2303 | { | |
2304 | ||
2305 | CORE_ADDR address; | |
2306 | ||
2307 | /* It's invalid to be in a delay slot. */ | |
2308 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2309 | { | |
2310 | inst_env->invalid = 1; | |
2311 | return; | |
2312 | } | |
2313 | ||
2314 | /* The prefix value is one dereference of the contents of the operand1 | |
2315 | register. */ | |
2316 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2317 | inst_env->prefix_value |
2318 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); | |
29134980 OF |
2319 | |
2320 | /* Check if the mode is autoincrement. */ | |
2321 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2322 | { | |
2323 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2324 | } | |
2325 | ||
2326 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2327 | need updating. */ | |
2328 | inst_env->slot_needed = 0; | |
2329 | inst_env->xflag_found = 0; | |
2330 | inst_env->prefix_found = 1; | |
2331 | } | |
2332 | ||
2333 | /* Finds the destination for a branch with 8-bits offset. */ | |
2334 | ||
a78f21af | 2335 | static void |
29134980 OF |
2336 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2337 | { | |
2338 | ||
2339 | short offset; | |
2340 | ||
2341 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2342 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2343 | { | |
2344 | inst_env->invalid = 1; | |
2345 | return; | |
2346 | } | |
2347 | ||
2348 | /* We have a branch, find out where the branch will land. */ | |
2349 | offset = cris_get_branch_short_offset (inst); | |
2350 | ||
2351 | /* Check if the offset is signed. */ | |
2352 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2353 | { | |
2354 | offset |= 0xFF00; | |
2355 | } | |
2356 | ||
2357 | /* The offset ends with the sign bit, set it to zero. The address | |
2358 | should always be word aligned. */ | |
2359 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2360 | ||
2361 | inst_env->branch_found = 1; | |
2362 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2363 | ||
2364 | inst_env->slot_needed = 1; | |
2365 | inst_env->prefix_found = 0; | |
2366 | inst_env->xflag_found = 0; | |
2367 | inst_env->disable_interrupt = 1; | |
2368 | } | |
2369 | ||
2370 | /* Finds the destination for a branch with 16-bits offset. */ | |
2371 | ||
a78f21af | 2372 | static void |
29134980 OF |
2373 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2374 | { | |
2375 | short offset; | |
2376 | ||
2377 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2378 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2379 | { | |
2380 | inst_env->invalid = 1; | |
2381 | return; | |
2382 | } | |
2383 | ||
2384 | /* We have a branch, find out the offset for the branch. */ | |
e17a4113 | 2385 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, inst_env->byte_order); |
29134980 OF |
2386 | |
2387 | /* The instruction is one word longer than normal, so add one word | |
2388 | to the PC. */ | |
2389 | inst_env->reg[REG_PC] += 2; | |
2390 | ||
2391 | inst_env->branch_found = 1; | |
2392 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2393 | ||
2394 | ||
2395 | inst_env->slot_needed = 1; | |
2396 | inst_env->prefix_found = 0; | |
2397 | inst_env->xflag_found = 0; | |
2398 | inst_env->disable_interrupt = 1; | |
2399 | } | |
2400 | ||
2401 | /* Handles the ABS instruction. */ | |
2402 | ||
a78f21af | 2403 | static void |
29134980 OF |
2404 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2405 | { | |
2406 | ||
2407 | long value; | |
2408 | ||
2409 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2410 | if (inst_env->prefix_found) | |
2411 | { | |
2412 | inst_env->invalid = 1; | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | /* Check if the operation affects the PC. */ | |
2417 | if (cris_get_operand2 (inst) == REG_PC) | |
2418 | { | |
2419 | ||
2420 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2421 | if (inst_env->slot_needed) | |
2422 | { | |
2423 | inst_env->invalid = 1; | |
2424 | return; | |
2425 | } | |
2426 | ||
2427 | value = (long) inst_env->reg[REG_PC]; | |
2428 | ||
2429 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2430 | if (value != SIGNED_DWORD_MASK) | |
2431 | { | |
2432 | value = -value; | |
2433 | inst_env->reg[REG_PC] = (long) value; | |
2434 | } | |
2435 | } | |
2436 | ||
2437 | inst_env->slot_needed = 0; | |
2438 | inst_env->prefix_found = 0; | |
2439 | inst_env->xflag_found = 0; | |
2440 | inst_env->disable_interrupt = 0; | |
2441 | } | |
2442 | ||
2443 | /* Handles the ADDI instruction. */ | |
2444 | ||
a78f21af | 2445 | static void |
29134980 OF |
2446 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2447 | { | |
2448 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2449 | a prefix. */ | |
2450 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2451 | { | |
2452 | inst_env->invalid = 1; | |
2453 | return; | |
2454 | } | |
2455 | ||
2456 | inst_env->slot_needed = 0; | |
2457 | inst_env->prefix_found = 0; | |
2458 | inst_env->xflag_found = 0; | |
2459 | inst_env->disable_interrupt = 0; | |
2460 | } | |
2461 | ||
2462 | /* Handles the ASR instruction. */ | |
2463 | ||
a78f21af | 2464 | static void |
29134980 OF |
2465 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2466 | { | |
2467 | int shift_steps; | |
2468 | unsigned long value; | |
2469 | unsigned long signed_extend_mask = 0; | |
2470 | ||
2471 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2472 | if (inst_env->prefix_found) | |
2473 | { | |
2474 | inst_env->invalid = 1; | |
2475 | return; | |
2476 | } | |
2477 | ||
2478 | /* Check if the PC is the target register. */ | |
2479 | if (cris_get_operand2 (inst) == REG_PC) | |
2480 | { | |
2481 | /* It's invalid to change the PC in a delay slot. */ | |
2482 | if (inst_env->slot_needed) | |
2483 | { | |
2484 | inst_env->invalid = 1; | |
2485 | return; | |
2486 | } | |
2487 | /* Get the number of bits to shift. */ | |
2488 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2489 | value = inst_env->reg[REG_PC]; | |
2490 | ||
2491 | /* Find out how many bits the operation should apply to. */ | |
2492 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2493 | { | |
2494 | if (value & SIGNED_BYTE_MASK) | |
2495 | { | |
2496 | signed_extend_mask = 0xFF; | |
2497 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2498 | signed_extend_mask = ~signed_extend_mask; | |
2499 | } | |
2500 | value = value >> shift_steps; | |
2501 | value |= signed_extend_mask; | |
2502 | value &= 0xFF; | |
2503 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2504 | inst_env->reg[REG_PC] |= value; | |
2505 | } | |
2506 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2507 | { | |
2508 | if (value & SIGNED_WORD_MASK) | |
2509 | { | |
2510 | signed_extend_mask = 0xFFFF; | |
2511 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2512 | signed_extend_mask = ~signed_extend_mask; | |
2513 | } | |
2514 | value = value >> shift_steps; | |
2515 | value |= signed_extend_mask; | |
2516 | value &= 0xFFFF; | |
2517 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2518 | inst_env->reg[REG_PC] |= value; | |
2519 | } | |
2520 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2521 | { | |
2522 | if (value & SIGNED_DWORD_MASK) | |
2523 | { | |
2524 | signed_extend_mask = 0xFFFFFFFF; | |
2525 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2526 | signed_extend_mask = ~signed_extend_mask; | |
2527 | } | |
2528 | value = value >> shift_steps; | |
2529 | value |= signed_extend_mask; | |
2530 | inst_env->reg[REG_PC] = value; | |
2531 | } | |
2532 | } | |
2533 | inst_env->slot_needed = 0; | |
2534 | inst_env->prefix_found = 0; | |
2535 | inst_env->xflag_found = 0; | |
2536 | inst_env->disable_interrupt = 0; | |
2537 | } | |
2538 | ||
2539 | /* Handles the ASRQ instruction. */ | |
2540 | ||
a78f21af | 2541 | static void |
29134980 OF |
2542 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2543 | { | |
2544 | ||
2545 | int shift_steps; | |
2546 | unsigned long value; | |
2547 | unsigned long signed_extend_mask = 0; | |
2548 | ||
2549 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2550 | if (inst_env->prefix_found) | |
2551 | { | |
2552 | inst_env->invalid = 1; | |
2553 | return; | |
2554 | } | |
2555 | ||
2556 | /* Check if the PC is the target register. */ | |
2557 | if (cris_get_operand2 (inst) == REG_PC) | |
2558 | { | |
2559 | ||
2560 | /* It's invalid to change the PC in a delay slot. */ | |
2561 | if (inst_env->slot_needed) | |
2562 | { | |
2563 | inst_env->invalid = 1; | |
2564 | return; | |
2565 | } | |
2566 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2567 | want the the sign bit of the quick value. */ | |
2568 | shift_steps = cris_get_asr_shift_steps (inst); | |
2569 | value = inst_env->reg[REG_PC]; | |
2570 | if (value & SIGNED_DWORD_MASK) | |
2571 | { | |
2572 | signed_extend_mask = 0xFFFFFFFF; | |
2573 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2574 | signed_extend_mask = ~signed_extend_mask; | |
2575 | } | |
2576 | value = value >> shift_steps; | |
2577 | value |= signed_extend_mask; | |
2578 | inst_env->reg[REG_PC] = value; | |
2579 | } | |
2580 | inst_env->slot_needed = 0; | |
2581 | inst_env->prefix_found = 0; | |
2582 | inst_env->xflag_found = 0; | |
2583 | inst_env->disable_interrupt = 0; | |
2584 | } | |
2585 | ||
2586 | /* Handles the AX, EI and SETF instruction. */ | |
2587 | ||
a78f21af | 2588 | static void |
29134980 OF |
2589 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2590 | { | |
2591 | if (inst_env->prefix_found) | |
2592 | { | |
2593 | inst_env->invalid = 1; | |
2594 | return; | |
2595 | } | |
2596 | /* Check if the instruction is setting the X flag. */ | |
2597 | if (cris_is_xflag_bit_on (inst)) | |
2598 | { | |
2599 | inst_env->xflag_found = 1; | |
2600 | } | |
2601 | else | |
2602 | { | |
2603 | inst_env->xflag_found = 0; | |
2604 | } | |
2605 | inst_env->slot_needed = 0; | |
2606 | inst_env->prefix_found = 0; | |
2607 | inst_env->disable_interrupt = 1; | |
2608 | } | |
2609 | ||
2610 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2611 | register. Note that check_assign assumes that the caller has checked that | |
2612 | there is a prefix to this instruction. The mode check depends on this. */ | |
2613 | ||
a78f21af | 2614 | static void |
29134980 OF |
2615 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2616 | { | |
2617 | /* Check if it's an assign addressing mode. */ | |
2618 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2619 | { | |
2620 | /* Assign the prefix value to operand 1. */ | |
2621 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2622 | } | |
2623 | } | |
2624 | ||
2625 | /* Handles the 2-operand BOUND instruction. */ | |
2626 | ||
a78f21af | 2627 | static void |
29134980 OF |
2628 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2629 | { | |
2630 | /* It's invalid to have the PC as the index operand. */ | |
2631 | if (cris_get_operand2 (inst) == REG_PC) | |
2632 | { | |
2633 | inst_env->invalid = 1; | |
2634 | return; | |
2635 | } | |
2636 | /* Check if we have a prefix. */ | |
2637 | if (inst_env->prefix_found) | |
2638 | { | |
2639 | check_assign (inst, inst_env); | |
2640 | } | |
2641 | /* Check if this is an autoincrement mode. */ | |
2642 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2643 | { | |
2644 | /* It's invalid to change the PC in a delay slot. */ | |
2645 | if (inst_env->slot_needed) | |
2646 | { | |
2647 | inst_env->invalid = 1; | |
2648 | return; | |
2649 | } | |
2650 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2651 | } | |
2652 | inst_env->slot_needed = 0; | |
2653 | inst_env->prefix_found = 0; | |
2654 | inst_env->xflag_found = 0; | |
2655 | inst_env->disable_interrupt = 0; | |
2656 | } | |
2657 | ||
2658 | /* Handles the 3-operand BOUND instruction. */ | |
2659 | ||
a78f21af | 2660 | static void |
29134980 OF |
2661 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2662 | { | |
2663 | /* It's an error if we haven't got a prefix. And it's also an error | |
2664 | if the PC is the destination register. */ | |
2665 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2666 | { | |
2667 | inst_env->invalid = 1; | |
2668 | return; | |
2669 | } | |
2670 | inst_env->slot_needed = 0; | |
2671 | inst_env->prefix_found = 0; | |
2672 | inst_env->xflag_found = 0; | |
2673 | inst_env->disable_interrupt = 0; | |
2674 | } | |
2675 | ||
2676 | /* Clears the status flags in inst_env. */ | |
2677 | ||
a78f21af | 2678 | static void |
29134980 OF |
2679 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2680 | { | |
2681 | /* It's an error if we have got a prefix. */ | |
2682 | if (inst_env->prefix_found) | |
2683 | { | |
2684 | inst_env->invalid = 1; | |
2685 | return; | |
2686 | } | |
2687 | ||
2688 | inst_env->slot_needed = 0; | |
2689 | inst_env->prefix_found = 0; | |
2690 | inst_env->xflag_found = 0; | |
2691 | inst_env->disable_interrupt = 0; | |
2692 | } | |
2693 | ||
2694 | /* Clears the status flags in inst_env. */ | |
2695 | ||
a78f21af | 2696 | static void |
29134980 OF |
2697 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2698 | { | |
2699 | /* It's an error if we have got a prefix. */ | |
2700 | if (inst_env->prefix_found) | |
2701 | { | |
2702 | inst_env->invalid = 1; | |
2703 | return; | |
2704 | } | |
2705 | ||
2706 | inst_env->slot_needed = 0; | |
2707 | inst_env->prefix_found = 0; | |
2708 | inst_env->xflag_found = 0; | |
2709 | inst_env->disable_interrupt = 1; | |
2710 | } | |
2711 | ||
2712 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2713 | ||
a78f21af | 2714 | static void |
29134980 OF |
2715 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2716 | { | |
2717 | /* Check if the target is the PC. */ | |
2718 | if (cris_get_operand2 (inst) == REG_PC) | |
2719 | { | |
2720 | /* The instruction will clear the instruction's size bits. */ | |
2721 | int clear_size = cris_get_clear_size (inst); | |
2722 | if (clear_size == INST_BYTE_SIZE) | |
2723 | { | |
2724 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2725 | } | |
2726 | if (clear_size == INST_WORD_SIZE) | |
2727 | { | |
2728 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2729 | } | |
2730 | if (clear_size == INST_DWORD_SIZE) | |
2731 | { | |
2732 | inst_env->delay_slot_pc = 0x0; | |
2733 | } | |
2734 | /* The jump will be delayed with one delay slot. So we need a delay | |
2735 | slot. */ | |
2736 | inst_env->slot_needed = 1; | |
2737 | inst_env->delay_slot_pc_active = 1; | |
2738 | } | |
2739 | else | |
2740 | { | |
2741 | /* The PC will not change => no delay slot. */ | |
2742 | inst_env->slot_needed = 0; | |
2743 | } | |
2744 | inst_env->prefix_found = 0; | |
2745 | inst_env->xflag_found = 0; | |
2746 | inst_env->disable_interrupt = 0; | |
2747 | } | |
2748 | ||
2749 | /* Handles the TEST instruction if it's in register mode. */ | |
2750 | ||
a78f21af | 2751 | static void |
29134980 OF |
2752 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2753 | { | |
2754 | /* It's an error if we have got a prefix. */ | |
2755 | if (inst_env->prefix_found) | |
2756 | { | |
2757 | inst_env->invalid = 1; | |
2758 | return; | |
2759 | } | |
2760 | inst_env->slot_needed = 0; | |
2761 | inst_env->prefix_found = 0; | |
2762 | inst_env->xflag_found = 0; | |
2763 | inst_env->disable_interrupt = 0; | |
2764 | ||
2765 | } | |
2766 | ||
2767 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2768 | in register mode. */ | |
2769 | ||
a78f21af | 2770 | static void |
29134980 OF |
2771 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2772 | { | |
2773 | /* Check if we are in a prefix mode. */ | |
2774 | if (inst_env->prefix_found) | |
2775 | { | |
2776 | /* The only way the PC can change is if this instruction is in | |
2777 | assign addressing mode. */ | |
2778 | check_assign (inst, inst_env); | |
2779 | } | |
2780 | /* Indirect mode can't change the PC so just check if the mode is | |
2781 | autoincrement. */ | |
2782 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2783 | { | |
2784 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2785 | } | |
2786 | inst_env->slot_needed = 0; | |
2787 | inst_env->prefix_found = 0; | |
2788 | inst_env->xflag_found = 0; | |
2789 | inst_env->disable_interrupt = 0; | |
2790 | } | |
2791 | ||
2792 | /* Checks that the PC isn't the destination register or the instructions has | |
2793 | a prefix. */ | |
2794 | ||
a78f21af | 2795 | static void |
29134980 OF |
2796 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2797 | { | |
2798 | /* It's invalid to have the PC as the destination. The instruction can't | |
2799 | have a prefix. */ | |
2800 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2801 | { | |
2802 | inst_env->invalid = 1; | |
2803 | return; | |
2804 | } | |
2805 | ||
2806 | inst_env->slot_needed = 0; | |
2807 | inst_env->prefix_found = 0; | |
2808 | inst_env->xflag_found = 0; | |
2809 | inst_env->disable_interrupt = 0; | |
2810 | } | |
2811 | ||
2812 | /* Checks that the instruction doesn't have a prefix. */ | |
2813 | ||
a78f21af | 2814 | static void |
29134980 OF |
2815 | break_op (unsigned short inst, inst_env_type *inst_env) |
2816 | { | |
2817 | /* The instruction can't have a prefix. */ | |
2818 | if (inst_env->prefix_found) | |
2819 | { | |
2820 | inst_env->invalid = 1; | |
2821 | return; | |
2822 | } | |
2823 | ||
2824 | inst_env->slot_needed = 0; | |
2825 | inst_env->prefix_found = 0; | |
2826 | inst_env->xflag_found = 0; | |
2827 | inst_env->disable_interrupt = 1; | |
2828 | } | |
2829 | ||
2830 | /* Checks that the PC isn't the destination register and that the instruction | |
2831 | doesn't have a prefix. */ | |
2832 | ||
a78f21af | 2833 | static void |
29134980 OF |
2834 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2835 | { | |
2836 | /* It's invalid to have the PC as the destination. The instruction can't | |
2837 | have a prefix. */ | |
2838 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2839 | { | |
2840 | inst_env->invalid = 1; | |
2841 | return; | |
2842 | } | |
2843 | ||
2844 | inst_env->slot_needed = 0; | |
2845 | inst_env->prefix_found = 0; | |
2846 | inst_env->xflag_found = 0; | |
2847 | inst_env->disable_interrupt = 1; | |
2848 | } | |
2849 | ||
2850 | /* Handles the register mode JUMP instruction. */ | |
2851 | ||
a78f21af | 2852 | static void |
29134980 OF |
2853 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2854 | { | |
2855 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2856 | you can't have a prefix. */ | |
2857 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2858 | { | |
2859 | inst_env->invalid = 1; | |
2860 | return; | |
2861 | } | |
2862 | ||
2863 | /* Just change the PC. */ | |
2864 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2865 | inst_env->slot_needed = 0; | |
2866 | inst_env->prefix_found = 0; | |
2867 | inst_env->xflag_found = 0; | |
2868 | inst_env->disable_interrupt = 1; | |
2869 | } | |
2870 | ||
2871 | /* Handles the JUMP instruction for all modes except register. */ | |
2872 | ||
a78f21af AC |
2873 | static void |
2874 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2875 | { |
2876 | unsigned long newpc; | |
2877 | CORE_ADDR address; | |
2878 | ||
2879 | /* It's invalid to do a JUMP in a delay slot. */ | |
2880 | if (inst_env->slot_needed) | |
2881 | { | |
2882 | inst_env->invalid = 1; | |
2883 | } | |
2884 | else | |
2885 | { | |
2886 | /* Check if we have a prefix. */ | |
2887 | if (inst_env->prefix_found) | |
2888 | { | |
2889 | check_assign (inst, inst_env); | |
2890 | ||
2891 | /* Get the new value for the the PC. */ | |
2892 | newpc = | |
2893 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
e17a4113 | 2894 | 4, inst_env->byte_order); |
29134980 OF |
2895 | } |
2896 | else | |
2897 | { | |
2898 | /* Get the new value for the PC. */ | |
2899 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2900 | newpc = read_memory_unsigned_integer (address, |
2901 | 4, inst_env->byte_order); | |
29134980 OF |
2902 | |
2903 | /* Check if we should increment a register. */ | |
2904 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2905 | { | |
2906 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2907 | } | |
2908 | } | |
2909 | inst_env->reg[REG_PC] = newpc; | |
2910 | } | |
2911 | inst_env->slot_needed = 0; | |
2912 | inst_env->prefix_found = 0; | |
2913 | inst_env->xflag_found = 0; | |
2914 | inst_env->disable_interrupt = 1; | |
2915 | } | |
2916 | ||
2917 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2918 | ||
a78f21af | 2919 | static void |
be8626e0 MD |
2920 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2921 | inst_env_type *inst_env) | |
29134980 OF |
2922 | { |
2923 | if (inst_env->prefix_found) | |
2924 | { | |
2925 | /* The instruction has a prefix that means we are only interested if | |
2926 | the instruction is in assign mode. */ | |
2927 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2928 | { | |
2929 | /* The prefix handles the problem if we are in a delay slot. */ | |
2930 | if (cris_get_operand1 (inst) == REG_PC) | |
2931 | { | |
2932 | /* Just take care of the assign. */ | |
2933 | check_assign (inst, inst_env); | |
2934 | } | |
2935 | } | |
2936 | } | |
2937 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2938 | { | |
2939 | /* The instruction doesn't have a prefix, the only case left that we | |
2940 | are interested in is the autoincrement mode. */ | |
2941 | if (cris_get_operand1 (inst) == REG_PC) | |
2942 | { | |
2943 | /* If the PC is to be incremented it's invalid to be in a | |
2944 | delay slot. */ | |
2945 | if (inst_env->slot_needed) | |
2946 | { | |
2947 | inst_env->invalid = 1; | |
2948 | return; | |
2949 | } | |
2a9ecef2 OF |
2950 | |
2951 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 2952 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
2953 | { |
2954 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2955 | } | |
be8626e0 | 2956 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
2957 | { |
2958 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2959 | } | |
2960 | else | |
2961 | { | |
2962 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2963 | } | |
2964 | } | |
2965 | } | |
2966 | inst_env->slot_needed = 0; | |
2967 | inst_env->prefix_found = 0; | |
2968 | inst_env->xflag_found = 0; | |
2969 | inst_env->disable_interrupt = 1; | |
2970 | } | |
2971 | ||
2972 | /* Handles moves from special registers (aka P-register) for all modes | |
2973 | except register. */ | |
2974 | ||
a78f21af | 2975 | static void |
be8626e0 MD |
2976 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2977 | inst_env_type *inst_env) | |
29134980 OF |
2978 | { |
2979 | if (inst_env->prefix_found) | |
2980 | { | |
2981 | /* The instruction has a prefix that means we are only interested if | |
2982 | the instruction is in assign mode. */ | |
2983 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2984 | { | |
2985 | /* The prefix handles the problem if we are in a delay slot. */ | |
2986 | if (cris_get_operand1 (inst) == REG_PC) | |
2987 | { | |
2988 | /* Just take care of the assign. */ | |
2989 | check_assign (inst, inst_env); | |
2990 | } | |
2991 | } | |
2992 | } | |
2993 | /* The instruction doesn't have a prefix, the only case left that we | |
2994 | are interested in is the autoincrement mode. */ | |
2995 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2996 | { | |
2997 | if (cris_get_operand1 (inst) == REG_PC) | |
2998 | { | |
2999 | /* If the PC is to be incremented it's invalid to be in a | |
3000 | delay slot. */ | |
3001 | if (inst_env->slot_needed) | |
3002 | { | |
3003 | inst_env->invalid = 1; | |
3004 | return; | |
3005 | } | |
2a9ecef2 OF |
3006 | |
3007 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 3008 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
3009 | { |
3010 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
3011 | } | |
be8626e0 | 3012 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
3013 | { |
3014 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
3015 | } | |
3016 | else | |
3017 | { | |
3018 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
3019 | } | |
3020 | } | |
3021 | } | |
3022 | inst_env->slot_needed = 0; | |
3023 | inst_env->prefix_found = 0; | |
3024 | inst_env->xflag_found = 0; | |
3025 | inst_env->disable_interrupt = 1; | |
3026 | } | |
3027 | ||
3028 | /* Handles moves from special registers (aka P-register) when the mode | |
3029 | is register. */ | |
3030 | ||
a78f21af | 3031 | static void |
29134980 OF |
3032 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
3033 | { | |
3034 | /* Register mode move from special register can't have a prefix. */ | |
3035 | if (inst_env->prefix_found) | |
3036 | { | |
3037 | inst_env->invalid = 1; | |
3038 | return; | |
3039 | } | |
3040 | ||
3041 | if (cris_get_operand1 (inst) == REG_PC) | |
3042 | { | |
3043 | /* It's invalid to change the PC in a delay slot. */ | |
3044 | if (inst_env->slot_needed) | |
3045 | { | |
3046 | inst_env->invalid = 1; | |
3047 | return; | |
3048 | } | |
3049 | /* The destination is the PC, the jump will have a delay slot. */ | |
3050 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3051 | inst_env->slot_needed = 1; | |
3052 | inst_env->delay_slot_pc_active = 1; | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | /* If the destination isn't PC, there will be no jump. */ | |
3057 | inst_env->slot_needed = 0; | |
3058 | } | |
3059 | inst_env->prefix_found = 0; | |
3060 | inst_env->xflag_found = 0; | |
3061 | inst_env->disable_interrupt = 1; | |
3062 | } | |
3063 | ||
3064 | /* Handles the MOVEM from memory to general register instruction. */ | |
3065 | ||
a78f21af | 3066 | static void |
29134980 OF |
3067 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3068 | { | |
3069 | if (inst_env->prefix_found) | |
3070 | { | |
3071 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3072 | MOVEM instruction going to change the PC? */ | |
3073 | if (cris_get_operand2 (inst) >= REG_PC) | |
3074 | { | |
3075 | inst_env->reg[REG_PC] = | |
e17a4113 UW |
3076 | read_memory_unsigned_integer (inst_env->prefix_value, |
3077 | 4, inst_env->byte_order); | |
29134980 OF |
3078 | } |
3079 | /* The assign value is the value after the increment. Normally, the | |
3080 | assign value is the value before the increment. */ | |
3081 | if ((cris_get_operand1 (inst) == REG_PC) | |
3082 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3083 | { | |
3084 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3085 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3086 | } | |
3087 | } | |
3088 | else | |
3089 | { | |
3090 | /* Is the MOVEM instruction going to change the PC? */ | |
3091 | if (cris_get_operand2 (inst) == REG_PC) | |
3092 | { | |
3093 | /* It's invalid to change the PC in a delay slot. */ | |
3094 | if (inst_env->slot_needed) | |
3095 | { | |
3096 | inst_env->invalid = 1; | |
3097 | return; | |
3098 | } | |
3099 | inst_env->reg[REG_PC] = | |
3100 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
e17a4113 | 3101 | 4, inst_env->byte_order); |
29134980 OF |
3102 | } |
3103 | /* The increment is not depending on the size, instead it's depending | |
3104 | on the number of registers loaded from memory. */ | |
3105 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3106 | { | |
3107 | /* It's invalid to change the PC in a delay slot. */ | |
3108 | if (inst_env->slot_needed) | |
3109 | { | |
3110 | inst_env->invalid = 1; | |
3111 | return; | |
3112 | } | |
3113 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3114 | } | |
3115 | } | |
3116 | inst_env->slot_needed = 0; | |
3117 | inst_env->prefix_found = 0; | |
3118 | inst_env->xflag_found = 0; | |
3119 | inst_env->disable_interrupt = 0; | |
3120 | } | |
3121 | ||
3122 | /* Handles the MOVEM to memory from general register instruction. */ | |
3123 | ||
a78f21af | 3124 | static void |
29134980 OF |
3125 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3126 | { | |
3127 | if (inst_env->prefix_found) | |
3128 | { | |
3129 | /* The assign value is the value after the increment. Normally, the | |
3130 | assign value is the value before the increment. */ | |
3131 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3132 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3133 | { | |
3134 | /* The prefix handles the problem if we are in a delay slot. */ | |
3135 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3136 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3137 | } | |
3138 | } | |
3139 | else | |
3140 | { | |
3141 | /* The increment is not depending on the size, instead it's depending | |
3142 | on the number of registers loaded to memory. */ | |
3143 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3144 | { | |
3145 | /* It's invalid to change the PC in a delay slot. */ | |
3146 | if (inst_env->slot_needed) | |
3147 | { | |
3148 | inst_env->invalid = 1; | |
3149 | return; | |
3150 | } | |
3151 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3152 | } | |
3153 | } | |
3154 | inst_env->slot_needed = 0; | |
3155 | inst_env->prefix_found = 0; | |
3156 | inst_env->xflag_found = 0; | |
3157 | inst_env->disable_interrupt = 0; | |
3158 | } | |
3159 | ||
29134980 OF |
3160 | /* Handles the intructions that's not yet implemented, by setting |
3161 | inst_env->invalid to true. */ | |
3162 | ||
a78f21af | 3163 | static void |
29134980 OF |
3164 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3165 | { | |
3166 | inst_env->invalid = 1; | |
3167 | } | |
3168 | ||
3169 | /* Handles the XOR instruction. */ | |
3170 | ||
a78f21af | 3171 | static void |
29134980 OF |
3172 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3173 | { | |
3174 | /* XOR can't have a prefix. */ | |
3175 | if (inst_env->prefix_found) | |
3176 | { | |
3177 | inst_env->invalid = 1; | |
3178 | return; | |
3179 | } | |
3180 | ||
3181 | /* Check if the PC is the target. */ | |
3182 | if (cris_get_operand2 (inst) == REG_PC) | |
3183 | { | |
3184 | /* It's invalid to change the PC in a delay slot. */ | |
3185 | if (inst_env->slot_needed) | |
3186 | { | |
3187 | inst_env->invalid = 1; | |
3188 | return; | |
3189 | } | |
3190 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3191 | } | |
3192 | inst_env->slot_needed = 0; | |
3193 | inst_env->prefix_found = 0; | |
3194 | inst_env->xflag_found = 0; | |
3195 | inst_env->disable_interrupt = 0; | |
3196 | } | |
3197 | ||
3198 | /* Handles the MULS instruction. */ | |
3199 | ||
a78f21af | 3200 | static void |
29134980 OF |
3201 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3202 | { | |
3203 | /* MULS/U can't have a prefix. */ | |
3204 | if (inst_env->prefix_found) | |
3205 | { | |
3206 | inst_env->invalid = 1; | |
3207 | return; | |
3208 | } | |
3209 | ||
3210 | /* Consider it invalid if the PC is the target. */ | |
3211 | if (cris_get_operand2 (inst) == REG_PC) | |
3212 | { | |
3213 | inst_env->invalid = 1; | |
3214 | return; | |
3215 | } | |
3216 | inst_env->slot_needed = 0; | |
3217 | inst_env->prefix_found = 0; | |
3218 | inst_env->xflag_found = 0; | |
3219 | inst_env->disable_interrupt = 0; | |
3220 | } | |
3221 | ||
3222 | /* Handles the MULU instruction. */ | |
3223 | ||
a78f21af | 3224 | static void |
29134980 OF |
3225 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3226 | { | |
3227 | /* MULS/U can't have a prefix. */ | |
3228 | if (inst_env->prefix_found) | |
3229 | { | |
3230 | inst_env->invalid = 1; | |
3231 | return; | |
3232 | } | |
3233 | ||
3234 | /* Consider it invalid if the PC is the target. */ | |
3235 | if (cris_get_operand2 (inst) == REG_PC) | |
3236 | { | |
3237 | inst_env->invalid = 1; | |
3238 | return; | |
3239 | } | |
3240 | inst_env->slot_needed = 0; | |
3241 | inst_env->prefix_found = 0; | |
3242 | inst_env->xflag_found = 0; | |
3243 | inst_env->disable_interrupt = 0; | |
3244 | } | |
3245 | ||
3246 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3247 | The MOVE instruction is the move from source to register. */ | |
3248 | ||
a78f21af | 3249 | static void |
29134980 OF |
3250 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3251 | unsigned long source1, unsigned long source2) | |
3252 | { | |
3253 | unsigned long pc_mask; | |
3254 | unsigned long operation_mask; | |
3255 | ||
3256 | /* Find out how many bits the operation should apply to. */ | |
3257 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3258 | { | |
3259 | pc_mask = 0xFFFFFF00; | |
3260 | operation_mask = 0xFF; | |
3261 | } | |
3262 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3263 | { | |
3264 | pc_mask = 0xFFFF0000; | |
3265 | operation_mask = 0xFFFF; | |
3266 | } | |
3267 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3268 | { | |
3269 | pc_mask = 0x0; | |
3270 | operation_mask = 0xFFFFFFFF; | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | /* The size is out of range. */ | |
3275 | inst_env->invalid = 1; | |
3276 | return; | |
3277 | } | |
3278 | ||
3279 | /* The instruction just works on uw_operation_mask bits. */ | |
3280 | source2 &= operation_mask; | |
3281 | source1 &= operation_mask; | |
3282 | ||
3283 | /* Now calculate the result. The opcode's 3 first bits separates | |
3284 | the different actions. */ | |
3285 | switch (cris_get_opcode (inst) & 7) | |
3286 | { | |
3287 | case 0: /* add */ | |
3288 | source1 += source2; | |
3289 | break; | |
3290 | ||
3291 | case 1: /* move */ | |
3292 | source1 = source2; | |
3293 | break; | |
3294 | ||
3295 | case 2: /* subtract */ | |
3296 | source1 -= source2; | |
3297 | break; | |
3298 | ||
3299 | case 3: /* compare */ | |
3300 | break; | |
3301 | ||
3302 | case 4: /* and */ | |
3303 | source1 &= source2; | |
3304 | break; | |
3305 | ||
3306 | case 5: /* or */ | |
3307 | source1 |= source2; | |
3308 | break; | |
3309 | ||
3310 | default: | |
3311 | inst_env->invalid = 1; | |
3312 | return; | |
3313 | ||
3314 | break; | |
3315 | } | |
3316 | ||
3317 | /* Make sure that the result doesn't contain more than the instruction | |
3318 | size bits. */ | |
3319 | source2 &= operation_mask; | |
3320 | ||
3321 | /* Calculate the new breakpoint address. */ | |
3322 | inst_env->reg[REG_PC] &= pc_mask; | |
3323 | inst_env->reg[REG_PC] |= source1; | |
3324 | ||
3325 | } | |
3326 | ||
3327 | /* Extends the value from either byte or word size to a dword. If the mode | |
3328 | is zero extend then the value is extended with zero. If instead the mode | |
3329 | is signed extend the sign bit of the value is taken into consideration. */ | |
3330 | ||
a78f21af | 3331 | static unsigned long |
29134980 OF |
3332 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3333 | { | |
3334 | /* The size can be either byte or word, check which one it is. | |
3335 | Don't check the highest bit, it's indicating if it's a zero | |
3336 | or sign extend. */ | |
3337 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3338 | { | |
3339 | /* Word size. */ | |
3340 | value &= 0xFFFF; | |
3341 | ||
3342 | /* Check if the instruction is signed extend. If so, check if value has | |
3343 | the sign bit on. */ | |
3344 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3345 | { | |
3346 | value |= SIGNED_WORD_EXTEND_MASK; | |
3347 | } | |
3348 | } | |
3349 | else | |
3350 | { | |
3351 | /* Byte size. */ | |
3352 | value &= 0xFF; | |
3353 | ||
3354 | /* Check if the instruction is signed extend. If so, check if value has | |
3355 | the sign bit on. */ | |
3356 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3357 | { | |
3358 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3359 | } | |
3360 | } | |
3361 | /* The size should now be dword. */ | |
3362 | cris_set_size_to_dword (inst); | |
3363 | return value; | |
3364 | } | |
3365 | ||
3366 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3367 | instruction. The MOVE instruction is the move from source to register. */ | |
3368 | ||
a78f21af | 3369 | static void |
29134980 OF |
3370 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3371 | inst_env_type *inst_env) | |
3372 | { | |
3373 | unsigned long operand1; | |
3374 | unsigned long operand2; | |
3375 | ||
3376 | /* It's invalid to have a prefix to the instruction. This is a register | |
3377 | mode instruction and can't have a prefix. */ | |
3378 | if (inst_env->prefix_found) | |
3379 | { | |
3380 | inst_env->invalid = 1; | |
3381 | return; | |
3382 | } | |
3383 | /* Check if the instruction has PC as its target. */ | |
3384 | if (cris_get_operand2 (inst) == REG_PC) | |
3385 | { | |
3386 | if (inst_env->slot_needed) | |
3387 | { | |
3388 | inst_env->invalid = 1; | |
3389 | return; | |
3390 | } | |
3391 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3392 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3393 | operand2 = inst_env->reg[REG_PC]; |
3394 | ||
3395 | /* Check if it's a extend, signed or zero instruction. */ | |
3396 | if (cris_get_opcode (inst) < 4) | |
3397 | { | |
3398 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3399 | } | |
3400 | /* Calculate the PC value after the instruction, i.e. where the | |
3401 | breakpoint should be. The order of the udw_operands is vital. */ | |
3402 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3403 | } | |
3404 | inst_env->slot_needed = 0; | |
3405 | inst_env->prefix_found = 0; | |
3406 | inst_env->xflag_found = 0; | |
3407 | inst_env->disable_interrupt = 0; | |
3408 | } | |
3409 | ||
3410 | /* Returns the data contained at address. The size of the data is derived from | |
3411 | the size of the operation. If the instruction is a zero or signed | |
3412 | extend instruction, the size field is changed in instruction. */ | |
3413 | ||
a78f21af | 3414 | static unsigned long |
e17a4113 | 3415 | get_data_from_address (unsigned short *inst, CORE_ADDR address, enum bfd_endian byte_order) |
29134980 OF |
3416 | { |
3417 | int size = cris_get_size (*inst); | |
3418 | unsigned long value; | |
3419 | ||
3420 | /* If it's an extend instruction we don't want the signed extend bit, | |
3421 | because it influences the size. */ | |
3422 | if (cris_get_opcode (*inst) < 4) | |
3423 | { | |
3424 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3425 | } | |
3426 | /* Is there a need for checking the size? Size should contain the number of | |
3427 | bytes to read. */ | |
3428 | size = 1 << size; | |
e17a4113 | 3429 | value = read_memory_unsigned_integer (address, size, byte_order); |
29134980 OF |
3430 | |
3431 | /* Check if it's an extend, signed or zero instruction. */ | |
3432 | if (cris_get_opcode (*inst) < 4) | |
3433 | { | |
3434 | value = do_sign_or_zero_extend (value, inst); | |
3435 | } | |
3436 | return value; | |
3437 | } | |
3438 | ||
3439 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3440 | instructions. The MOVE instruction is the move from source to register. */ | |
3441 | ||
a78f21af | 3442 | static void |
29134980 OF |
3443 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3444 | inst_env_type *inst_env) | |
3445 | { | |
3446 | unsigned long operand2; | |
3447 | unsigned long operand3; | |
3448 | ||
3449 | check_assign (inst, inst_env); | |
3450 | if (cris_get_operand2 (inst) == REG_PC) | |
3451 | { | |
3452 | operand2 = inst_env->reg[REG_PC]; | |
3453 | ||
3454 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3455 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3456 | inst_env->byte_order); | |
29134980 OF |
3457 | |
3458 | /* Calculate the PC value after the instruction, i.e. where the | |
3459 | breakpoint should be. The order of the udw_operands is vital. */ | |
3460 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3461 | } | |
3462 | inst_env->slot_needed = 0; | |
3463 | inst_env->prefix_found = 0; | |
3464 | inst_env->xflag_found = 0; | |
3465 | inst_env->disable_interrupt = 0; | |
3466 | } | |
3467 | ||
3468 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3469 | OR instructions. Note that for this to work as expected, the calling | |
3470 | function must have made sure that there is a prefix to this instruction. */ | |
3471 | ||
a78f21af | 3472 | static void |
29134980 OF |
3473 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3474 | inst_env_type *inst_env) | |
3475 | { | |
3476 | unsigned long operand2; | |
3477 | unsigned long operand3; | |
3478 | ||
3479 | if (cris_get_operand1 (inst) == REG_PC) | |
3480 | { | |
3481 | /* The PC will be changed by the instruction. */ | |
3482 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3483 | ||
3484 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3485 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3486 | inst_env->byte_order); | |
29134980 OF |
3487 | |
3488 | /* Calculate the PC value after the instruction, i.e. where the | |
3489 | breakpoint should be. */ | |
3490 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3491 | } | |
3492 | inst_env->slot_needed = 0; | |
3493 | inst_env->prefix_found = 0; | |
3494 | inst_env->xflag_found = 0; | |
3495 | inst_env->disable_interrupt = 0; | |
3496 | } | |
3497 | ||
3498 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3499 | instructions. The MOVE instruction is the move from source to register. */ | |
3500 | ||
a78f21af | 3501 | static void |
29134980 OF |
3502 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3503 | inst_env_type *inst_env) | |
3504 | { | |
3505 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3506 | { | |
3507 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3508 | SUB, AND or OR something weird is going on (if everything works these | |
3509 | instructions should end up in the three operand version). */ | |
3510 | inst_env->invalid = 1; | |
3511 | return; | |
3512 | } | |
3513 | else | |
3514 | { | |
3515 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3516 | so use it. */ | |
3517 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3518 | } | |
3519 | inst_env->slot_needed = 0; | |
3520 | inst_env->prefix_found = 0; | |
3521 | inst_env->xflag_found = 0; | |
3522 | inst_env->disable_interrupt = 0; | |
3523 | } | |
3524 | ||
3525 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3526 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3527 | source to register. */ | |
3528 | ||
a78f21af | 3529 | static void |
29134980 OF |
3530 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3531 | inst_env_type *inst_env) | |
3532 | { | |
3533 | unsigned long operand1; | |
3534 | unsigned long operand2; | |
3535 | unsigned long operand3; | |
3536 | int size; | |
3537 | ||
3538 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3539 | Check if the destination register is the PC. */ | |
3540 | if (cris_get_operand2 (inst) == REG_PC) | |
3541 | { | |
3542 | /* Must be done here, get_data_from_address may change the size | |
3543 | field. */ | |
3544 | size = cris_get_size (inst); | |
3545 | operand2 = inst_env->reg[REG_PC]; | |
3546 | ||
3547 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3548 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 | 3549 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
29134980 OF |
3550 | |
3551 | /* Calculate the PC value after the instruction, i.e. where the | |
3552 | breakpoint should be. The order of the udw_operands is vital. */ | |
3553 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3554 | } | |
3555 | /* If this is an autoincrement addressing mode, check if the increment | |
3556 | changes the PC. */ | |
3557 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3558 | { | |
3559 | /* Get the size field. */ | |
3560 | size = cris_get_size (inst); | |
3561 | ||
3562 | /* If it's an extend instruction we don't want the signed extend bit, | |
3563 | because it influences the size. */ | |
3564 | if (cris_get_opcode (inst) < 4) | |
3565 | { | |
3566 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3567 | } | |
3568 | process_autoincrement (size, inst, inst_env); | |
3569 | } | |
3570 | inst_env->slot_needed = 0; | |
3571 | inst_env->prefix_found = 0; | |
3572 | inst_env->xflag_found = 0; | |
3573 | inst_env->disable_interrupt = 0; | |
3574 | } | |
3575 | ||
3576 | /* Handles the two-operand addressing mode, all modes except register, for | |
3577 | the ADD, SUB CMP, AND and OR instruction. */ | |
3578 | ||
a78f21af | 3579 | static void |
29134980 OF |
3580 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3581 | inst_env_type *inst_env) | |
3582 | { | |
3583 | if (inst_env->prefix_found) | |
3584 | { | |
3585 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3586 | { | |
3587 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3588 | } | |
3589 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3590 | { | |
3591 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3592 | } | |
3593 | else | |
3594 | { | |
3595 | /* The mode is invalid for a prefixed base instruction. */ | |
3596 | inst_env->invalid = 1; | |
3597 | return; | |
3598 | } | |
3599 | } | |
3600 | else | |
3601 | { | |
3602 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3603 | } | |
3604 | } | |
3605 | ||
3606 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3607 | ||
a78f21af | 3608 | static void |
29134980 OF |
3609 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3610 | { | |
3611 | unsigned long operand1; | |
3612 | unsigned long operand2; | |
3613 | ||
3614 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3615 | instruction and can't have a prefix. */ | |
3616 | if (inst_env->prefix_found) | |
3617 | { | |
3618 | inst_env->invalid = 1; | |
3619 | return; | |
3620 | } | |
3621 | ||
3622 | /* Check if the instruction has PC as its target. */ | |
3623 | if (cris_get_operand2 (inst) == REG_PC) | |
3624 | { | |
3625 | if (inst_env->slot_needed) | |
3626 | { | |
3627 | inst_env->invalid = 1; | |
3628 | return; | |
3629 | } | |
3630 | operand1 = cris_get_quick_value (inst); | |
3631 | operand2 = inst_env->reg[REG_PC]; | |
3632 | ||
3633 | /* The size should now be dword. */ | |
3634 | cris_set_size_to_dword (&inst); | |
3635 | ||
3636 | /* Calculate the PC value after the instruction, i.e. where the | |
3637 | breakpoint should be. */ | |
3638 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3639 | } | |
3640 | inst_env->slot_needed = 0; | |
3641 | inst_env->prefix_found = 0; | |
3642 | inst_env->xflag_found = 0; | |
3643 | inst_env->disable_interrupt = 0; | |
3644 | } | |
3645 | ||
3646 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3647 | ||
a78f21af | 3648 | static void |
29134980 OF |
3649 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3650 | { | |
3651 | unsigned long operand1; | |
3652 | unsigned long operand2; | |
3653 | ||
3654 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3655 | instruction and can't have a prefix. */ | |
3656 | if (inst_env->prefix_found) | |
3657 | { | |
3658 | inst_env->invalid = 1; | |
3659 | return; | |
3660 | } | |
3661 | /* Check if the instruction has PC as its target. */ | |
3662 | if (cris_get_operand2 (inst) == REG_PC) | |
3663 | { | |
3664 | if (inst_env->slot_needed) | |
3665 | { | |
3666 | inst_env->invalid = 1; | |
3667 | return; | |
3668 | } | |
3669 | /* The instruction has the PC as its target register. */ | |
3670 | operand1 = cris_get_quick_value (inst); | |
3671 | operand2 = inst_env->reg[REG_PC]; | |
3672 | ||
3673 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3674 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3675 | { | |
3676 | /* sign extend */ | |
3677 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3678 | } | |
3679 | /* The size should now be dword. */ | |
3680 | cris_set_size_to_dword (&inst); | |
3681 | ||
3682 | /* Calculate the PC value after the instruction, i.e. where the | |
3683 | breakpoint should be. */ | |
3684 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3685 | } | |
3686 | inst_env->slot_needed = 0; | |
3687 | inst_env->prefix_found = 0; | |
3688 | inst_env->xflag_found = 0; | |
3689 | inst_env->disable_interrupt = 0; | |
3690 | } | |
3691 | ||
3692 | /* Translate op_type to a function and call it. */ | |
3693 | ||
a78f21af | 3694 | static void |
be8626e0 MD |
3695 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
3696 | unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
3697 | { |
3698 | switch (op_type) | |
3699 | { | |
3700 | case cris_not_implemented_op: | |
3701 | not_implemented_op (inst, inst_env); | |
3702 | break; | |
3703 | ||
3704 | case cris_abs_op: | |
3705 | abs_op (inst, inst_env); | |
3706 | break; | |
3707 | ||
3708 | case cris_addi_op: | |
3709 | addi_op (inst, inst_env); | |
3710 | break; | |
3711 | ||
3712 | case cris_asr_op: | |
3713 | asr_op (inst, inst_env); | |
3714 | break; | |
3715 | ||
3716 | case cris_asrq_op: | |
3717 | asrq_op (inst, inst_env); | |
3718 | break; | |
3719 | ||
3720 | case cris_ax_ei_setf_op: | |
3721 | ax_ei_setf_op (inst, inst_env); | |
3722 | break; | |
3723 | ||
3724 | case cris_bdap_prefix: | |
3725 | bdap_prefix (inst, inst_env); | |
3726 | break; | |
3727 | ||
3728 | case cris_biap_prefix: | |
3729 | biap_prefix (inst, inst_env); | |
3730 | break; | |
3731 | ||
3732 | case cris_break_op: | |
3733 | break_op (inst, inst_env); | |
3734 | break; | |
3735 | ||
3736 | case cris_btst_nop_op: | |
3737 | btst_nop_op (inst, inst_env); | |
3738 | break; | |
3739 | ||
3740 | case cris_clearf_di_op: | |
3741 | clearf_di_op (inst, inst_env); | |
3742 | break; | |
3743 | ||
3744 | case cris_dip_prefix: | |
3745 | dip_prefix (inst, inst_env); | |
3746 | break; | |
3747 | ||
3748 | case cris_dstep_logshift_mstep_neg_not_op: | |
3749 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3750 | break; | |
3751 | ||
3752 | case cris_eight_bit_offset_branch_op: | |
3753 | eight_bit_offset_branch_op (inst, inst_env); | |
3754 | break; | |
3755 | ||
3756 | case cris_move_mem_to_reg_movem_op: | |
3757 | move_mem_to_reg_movem_op (inst, inst_env); | |
3758 | break; | |
3759 | ||
3760 | case cris_move_reg_to_mem_movem_op: | |
3761 | move_reg_to_mem_movem_op (inst, inst_env); | |
3762 | break; | |
3763 | ||
3764 | case cris_move_to_preg_op: | |
be8626e0 | 3765 | move_to_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3766 | break; |
3767 | ||
3768 | case cris_muls_op: | |
3769 | muls_op (inst, inst_env); | |
3770 | break; | |
3771 | ||
3772 | case cris_mulu_op: | |
3773 | mulu_op (inst, inst_env); | |
3774 | break; | |
3775 | ||
3776 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3777 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3778 | break; | |
3779 | ||
3780 | case cris_none_reg_mode_clear_test_op: | |
3781 | none_reg_mode_clear_test_op (inst, inst_env); | |
3782 | break; | |
3783 | ||
3784 | case cris_none_reg_mode_jump_op: | |
3785 | none_reg_mode_jump_op (inst, inst_env); | |
3786 | break; | |
3787 | ||
3788 | case cris_none_reg_mode_move_from_preg_op: | |
be8626e0 | 3789 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3790 | break; |
3791 | ||
3792 | case cris_quick_mode_add_sub_op: | |
3793 | quick_mode_add_sub_op (inst, inst_env); | |
3794 | break; | |
3795 | ||
3796 | case cris_quick_mode_and_cmp_move_or_op: | |
3797 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3798 | break; | |
3799 | ||
3800 | case cris_quick_mode_bdap_prefix: | |
3801 | quick_mode_bdap_prefix (inst, inst_env); | |
3802 | break; | |
3803 | ||
3804 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3805 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3806 | break; | |
3807 | ||
3808 | case cris_reg_mode_clear_op: | |
3809 | reg_mode_clear_op (inst, inst_env); | |
3810 | break; | |
3811 | ||
3812 | case cris_reg_mode_jump_op: | |
3813 | reg_mode_jump_op (inst, inst_env); | |
3814 | break; | |
3815 | ||
3816 | case cris_reg_mode_move_from_preg_op: | |
3817 | reg_mode_move_from_preg_op (inst, inst_env); | |
3818 | break; | |
3819 | ||
3820 | case cris_reg_mode_test_op: | |
3821 | reg_mode_test_op (inst, inst_env); | |
3822 | break; | |
3823 | ||
3824 | case cris_scc_op: | |
3825 | scc_op (inst, inst_env); | |
3826 | break; | |
3827 | ||
3828 | case cris_sixteen_bit_offset_branch_op: | |
3829 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3830 | break; | |
3831 | ||
3832 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3833 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3834 | break; | |
3835 | ||
3836 | case cris_three_operand_bound_op: | |
3837 | three_operand_bound_op (inst, inst_env); | |
3838 | break; | |
3839 | ||
3840 | case cris_two_operand_bound_op: | |
3841 | two_operand_bound_op (inst, inst_env); | |
3842 | break; | |
3843 | ||
3844 | case cris_xor_op: | |
3845 | xor_op (inst, inst_env); | |
3846 | break; | |
3847 | } | |
3848 | } | |
3849 | ||
3850 | /* This wrapper is to avoid cris_get_assembler being called before | |
3851 | exec_bfd has been set. */ | |
3852 | ||
3853 | static int | |
a89aa300 | 3854 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3855 | { |
a89aa300 | 3856 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3857 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3858 | disassembler, even when there is no BFD. Does something like | |
3859 | "gdb; target remote; disassmeble *0x123" work? */ | |
3860 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3861 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3862 | gdb_assert (print_insn != NULL); |
3863 | return print_insn (addr, info); | |
29134980 OF |
3864 | } |
3865 | ||
dbbff683 OF |
3866 | /* Copied from <asm/elf.h>. */ |
3867 | typedef unsigned long elf_greg_t; | |
3868 | ||
3869 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3870 | #define CRISV10_ELF_NGREG 35 |
3871 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3872 | ||
3873 | #define CRISV32_ELF_NGREG 32 | |
3874 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3875 | |
3876 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3877 | ||
a78f21af | 3878 | static void |
c6b4e5a2 | 3879 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
dbbff683 | 3880 | { |
7fbe2eba UW |
3881 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3882 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
dbbff683 OF |
3883 | int i; |
3884 | elf_greg_t *regp = *gregsetp; | |
3885 | static char zerobuf[4] = {0}; | |
3886 | ||
3887 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3888 | knows about the actual size of each register so that's no problem. */ | |
3889 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3890 | { | |
c6b4e5a2 | 3891 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
dbbff683 | 3892 | } |
c600d464 OF |
3893 | |
3894 | if (tdep->cris_version == 32) | |
3895 | { | |
3896 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3897 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3898 | be wrong. Issue a warning to alert the user. */ | |
7fbe2eba | 3899 | regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch), |
c600d464 OF |
3900 | (char *)®p[ERP_REGNUM]); |
3901 | ||
3902 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3903 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3904 | } | |
dbbff683 OF |
3905 | } |
3906 | ||
3907 | /* Use a local version of this function to get the correct types for | |
3908 | regsets, until multi-arch core support is ready. */ | |
3909 | ||
3910 | static void | |
9eefc95f UW |
3911 | fetch_core_registers (struct regcache *regcache, |
3912 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3913 | int which, CORE_ADDR reg_addr) |
3914 | { | |
3915 | elf_gregset_t gregset; | |
3916 | ||
3917 | switch (which) | |
3918 | { | |
3919 | case 0: | |
c600d464 OF |
3920 | if (core_reg_size != sizeof (elf_gregset_t) |
3921 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3922 | { |
8a3fe4f8 | 3923 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3924 | } |
3925 | else | |
3926 | { | |
3927 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3928 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3929 | } |
3930 | ||
3931 | default: | |
3932 | /* We've covered all the kinds of registers we know about here, | |
3933 | so this must be something we wouldn't know what to do with | |
3934 | anyway. Just ignore it. */ | |
3935 | break; | |
3936 | } | |
3937 | } | |
3938 | ||
3939 | static struct core_fns cris_elf_core_fns = | |
3940 | { | |
3941 | bfd_target_elf_flavour, /* core_flavour */ | |
3942 | default_check_format, /* check_format */ | |
3943 | default_core_sniffer, /* core_sniffer */ | |
3944 | fetch_core_registers, /* core_read_registers */ | |
3945 | NULL /* next */ | |
3946 | }; | |
3947 | ||
a78f21af AC |
3948 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3949 | ||
29134980 OF |
3950 | void |
3951 | _initialize_cris_tdep (void) | |
3952 | { | |
a5f6c8f5 OF |
3953 | static struct cmd_list_element *cris_set_cmdlist; |
3954 | static struct cmd_list_element *cris_show_cmdlist; | |
3955 | ||
29134980 OF |
3956 | struct cmd_list_element *c; |
3957 | ||
3958 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3959 | ||
29134980 | 3960 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3961 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3962 | &usr_cmd_cris_version, | |
7915a72c AC |
3963 | _("Set the current CRIS version."), |
3964 | _("Show the current CRIS version."), | |
bdd56253 OF |
3965 | _("\ |
3966 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3967 | Defaults to 10. "), | |
2c5b56ce | 3968 | set_cris_version, |
7915a72c | 3969 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3970 | &setlist, &showlist); |
0e6bdb31 OF |
3971 | |
3972 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3973 | cris_modes, &usr_cmd_cris_mode, | |
3974 | _("Set the current CRIS mode."), | |
3975 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3976 | _("\ |
3977 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3978 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3979 | set_cris_mode, |
3980 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3981 | &setlist, &showlist); | |
dbbff683 | 3982 | |
a5f6c8f5 OF |
3983 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3984 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3985 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3986 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3987 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3988 | set_cris_dwarf2_cfi, |
7915a72c | 3989 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3990 | &setlist, &showlist); |
3991 | ||
52bd1401 | 3992 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3993 | } |
3994 | ||
3995 | /* Prints out all target specific values. */ | |
3996 | ||
3997 | static void | |
3998 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3999 | { | |
7fbe2eba | 4000 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29134980 OF |
4001 | if (tdep != NULL) |
4002 | { | |
4003 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
4004 | tdep->cris_version); | |
0e6bdb31 OF |
4005 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
4006 | tdep->cris_mode); | |
a5f6c8f5 OF |
4007 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
4008 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
4009 | } |
4010 | } | |
4011 | ||
4012 | static void | |
a5f6c8f5 OF |
4013 | set_cris_version (char *ignore_args, int from_tty, |
4014 | struct cmd_list_element *c) | |
29134980 OF |
4015 | { |
4016 | struct gdbarch_info info; | |
4017 | ||
a5f6c8f5 | 4018 | usr_cmd_cris_version_valid = 1; |
29134980 | 4019 | |
a5f6c8f5 OF |
4020 | /* Update the current architecture, if needed. */ |
4021 | gdbarch_info_init (&info); | |
4022 | if (!gdbarch_update_p (info)) | |
4023 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4024 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4025 | } |
4026 | ||
0e6bdb31 OF |
4027 | static void |
4028 | set_cris_mode (char *ignore_args, int from_tty, | |
4029 | struct cmd_list_element *c) | |
4030 | { | |
4031 | struct gdbarch_info info; | |
4032 | ||
4033 | /* Update the current architecture, if needed. */ | |
4034 | gdbarch_info_init (&info); | |
4035 | if (!gdbarch_update_p (info)) | |
4036 | internal_error (__FILE__, __LINE__, | |
4037 | "cris_gdbarch_update: failed to update architecture."); | |
4038 | } | |
4039 | ||
29134980 | 4040 | static void |
a5f6c8f5 OF |
4041 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4042 | struct cmd_list_element *c) | |
29134980 OF |
4043 | { |
4044 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4045 | |
4046 | /* Update the current architecture, if needed. */ | |
4047 | gdbarch_info_init (&info); | |
4048 | if (!gdbarch_update_p (info)) | |
4049 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4050 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4051 | } |
4052 | ||
29134980 OF |
4053 | static struct gdbarch * |
4054 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4055 | { | |
4056 | struct gdbarch *gdbarch; | |
4057 | struct gdbarch_tdep *tdep; | |
4058 | int cris_version; | |
29134980 OF |
4059 | |
4060 | if (usr_cmd_cris_version_valid) | |
4061 | { | |
4062 | /* Trust the user's CRIS version setting. */ | |
4063 | cris_version = usr_cmd_cris_version; | |
4064 | } | |
c600d464 OF |
4065 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4066 | { | |
4067 | cris_version = 32; | |
4068 | } | |
29134980 OF |
4069 | else |
4070 | { | |
4071 | /* Assume it's CRIS version 10. */ | |
4072 | cris_version = 10; | |
4073 | } | |
4074 | ||
29134980 OF |
4075 | /* Make the current settings visible to the user. */ |
4076 | usr_cmd_cris_version = cris_version; | |
29134980 | 4077 | |
0e6bdb31 | 4078 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4079 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4080 | arches != NULL; | |
4081 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4082 | { | |
a5f6c8f5 OF |
4083 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4084 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4085 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4086 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4087 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4088 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4089 | return arches->gdbarch; |
4090 | } | |
4091 | ||
4092 | /* No matching architecture was found. Create a new one. */ | |
4093 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4094 | gdbarch = gdbarch_alloc (&info, tdep); | |
4095 | ||
a5f6c8f5 | 4096 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4097 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4098 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4099 | |
4100 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4101 | switch (info.byte_order) | |
4102 | { | |
778eb05e | 4103 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4104 | /* Ok. */ |
4105 | break; | |
4106 | ||
d7449b42 | 4107 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4108 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4109 | break; |
4110 | ||
4111 | default: | |
e2e0b3e5 | 4112 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4113 | } |
4114 | ||
b4206d25 | 4115 | set_gdbarch_return_value (gdbarch, cris_return_value); |
29134980 | 4116 | |
29134980 | 4117 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4118 | |
4119 | /* Length of ordinary registers used in push_word and a few other | |
4120 | places. register_size() is the real way to know how big a | |
4121 | register is. */ | |
a5f6c8f5 | 4122 | |
2e4b5889 | 4123 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 4124 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 4125 | which means we have to set this explicitly. */ |
c600d464 | 4126 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4127 | |
29134980 OF |
4128 | /* The total amount of space needed to store (in an array called registers) |
4129 | GDB's copy of the machine's register state. Note: We can not use | |
d93859e2 | 4130 | cris_register_size at this point, since it relies on gdbarch |
29134980 OF |
4131 | being set. */ |
4132 | switch (tdep->cris_version) | |
4133 | { | |
4134 | case 0: | |
4135 | case 1: | |
4136 | case 2: | |
4137 | case 3: | |
29134980 OF |
4138 | case 8: |
4139 | case 9: | |
a5f6c8f5 OF |
4140 | /* Old versions; not supported. */ |
4141 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4142 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4143 | break; |
4144 | ||
4145 | case 10: | |
4146 | case 11: | |
4147 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4148 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4149 | set_gdbarch_pc_regnum (gdbarch, 15); |
4150 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4151 | /* There are 32 registers (some of which may not be implemented). */ | |
4152 | set_gdbarch_num_regs (gdbarch, 32); | |
4153 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4154 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4155 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4156 | ||
4157 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4158 | break; | |
4159 | ||
4160 | case 32: | |
4161 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4162 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4163 | and pseudo-register PC (32 bits). */ | |
4164 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4165 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4166 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4167 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4168 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4169 | ||
4170 | set_gdbarch_cannot_store_register | |
4171 | (gdbarch, crisv32_cannot_store_register); | |
4172 | set_gdbarch_cannot_fetch_register | |
4173 | (gdbarch, crisv32_cannot_fetch_register); | |
4174 | ||
4175 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4176 | ||
4177 | set_gdbarch_single_step_through_delay | |
4178 | (gdbarch, crisv32_single_step_through_delay); | |
4179 | ||
29134980 OF |
4180 | break; |
4181 | ||
4182 | default: | |
c600d464 | 4183 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4184 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4185 | } |
4186 | ||
c600d464 OF |
4187 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4188 | have the same ABI). */ | |
2e4b5889 OF |
4189 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4190 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4191 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4192 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4193 | |
4194 | /* The stack grows downward. */ | |
4195 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4196 | ||
4197 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4198 | ||
2e4b5889 OF |
4199 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4200 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
94afd7a6 | 4201 | set_gdbarch_dummy_id (gdbarch, cris_dummy_id); |
2e4b5889 | 4202 | |
a5f6c8f5 OF |
4203 | if (tdep->cris_dwarf2_cfi == 1) |
4204 | { | |
4205 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4206 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4207 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
94afd7a6 | 4208 | dwarf2_append_unwinders (gdbarch); |
a5f6c8f5 OF |
4209 | } |
4210 | ||
0e6bdb31 OF |
4211 | if (tdep->cris_mode != cris_mode_guru) |
4212 | { | |
94afd7a6 | 4213 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
0e6bdb31 | 4214 | } |
a5f6c8f5 | 4215 | |
94afd7a6 | 4216 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
2e4b5889 | 4217 | frame_base_set_default (gdbarch, &cris_frame_base); |
6c0e89ed | 4218 | |
76a9d10f MK |
4219 | set_solib_svr4_fetch_link_map_offsets |
4220 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
dbbff683 | 4221 | |
36482093 AC |
4222 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4223 | disassembler, even when there is no BFD. Does something like | |
4224 | "gdb; target remote; disassmeble *0x123" work? */ | |
4225 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4226 | ||
29134980 OF |
4227 | return gdbarch; |
4228 | } |