Commit | Line | Data |
---|---|---|
29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 AC |
2 | |
3 | Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. | |
4 | ||
29134980 OF |
5 | Contributed by Axis Communications AB. |
6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
7 | ||
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
2e4b5889 OF |
26 | #include "frame-unwind.h" |
27 | #include "frame-base.h" | |
28 | #include "trad-frame.h" | |
29 | #include "dwarf2-frame.h" | |
29134980 OF |
30 | #include "symtab.h" |
31 | #include "inferior.h" | |
32 | #include "gdbtypes.h" | |
33 | #include "gdbcore.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "target.h" | |
36 | #include "value.h" | |
37 | #include "opcode/cris.h" | |
38 | #include "arch-utils.h" | |
39 | #include "regcache.h" | |
36482093 | 40 | #include "gdb_assert.h" |
29134980 OF |
41 | |
42 | /* To get entry_point_address. */ | |
9ab9195f | 43 | #include "objfiles.h" |
29134980 | 44 | |
a5f6c8f5 | 45 | #include "solib.h" /* Support for shared libraries. */ |
dbbff683 | 46 | #include "solib-svr4.h" /* For struct link_map_offsets. */ |
9bbe19fb | 47 | #include "gdb_string.h" |
a89aa300 | 48 | #include "dis-asm.h" |
dbbff683 | 49 | |
29134980 OF |
50 | enum cris_num_regs |
51 | { | |
52 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
53 | NUM_FREGS = 0, | |
54 | ||
55 | /* There are 16 general registers. */ | |
56 | NUM_GENREGS = 16, | |
57 | ||
58 | /* There are 16 special registers. */ | |
c600d464 OF |
59 | NUM_SPECREGS = 16, |
60 | ||
61 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
62 | ||
63 | /* CRISv32 has 16 support registers. */ | |
64 | NUM_SUPPREGS = 16 | |
29134980 OF |
65 | }; |
66 | ||
67 | /* Register numbers of various important registers. | |
2e4b5889 | 68 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
69 | STR_REGNUM Contains the address of structure return values. |
70 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
71 | ARG1_REGNUM Contains the first parameter to a function. | |
72 | ARG2_REGNUM Contains the second parameter to a function. | |
73 | ARG3_REGNUM Contains the third parameter to a function. | |
74 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
75 | SP_REGNUM Contains address of top of stack. | |
76 | PC_REGNUM Contains address of next instruction. | |
77 | SRP_REGNUM Subroutine return pointer register. | |
78 | BRP_REGNUM Breakpoint return pointer register. */ | |
79 | ||
29134980 OF |
80 | enum cris_regnums |
81 | { | |
82 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 83 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 84 | CRIS_FP_REGNUM = 8, |
c600d464 | 85 | /* ABI related registers. */ |
29134980 OF |
86 | STR_REGNUM = 9, |
87 | RET_REGNUM = 10, | |
88 | ARG1_REGNUM = 10, | |
89 | ARG2_REGNUM = 11, | |
90 | ARG3_REGNUM = 12, | |
91 | ARG4_REGNUM = 13, | |
92 | ||
c600d464 | 93 | /* Registers which happen to be common. */ |
29134980 | 94 | VR_REGNUM = 17, |
c600d464 OF |
95 | MOF_REGNUM = 23, |
96 | SRP_REGNUM = 27, | |
97 | ||
98 | /* CRISv10 et. al. specific registers. */ | |
99 | P0_REGNUM = 16, | |
29134980 OF |
100 | P4_REGNUM = 20, |
101 | CCR_REGNUM = 21, | |
29134980 OF |
102 | P8_REGNUM = 24, |
103 | IBR_REGNUM = 25, | |
104 | IRP_REGNUM = 26, | |
29134980 | 105 | BAR_REGNUM = 28, |
2a9ecef2 | 106 | DCCR_REGNUM = 29, |
29134980 | 107 | BRP_REGNUM = 30, |
c600d464 OF |
108 | USP_REGNUM = 31, |
109 | ||
110 | /* CRISv32 specific registers. */ | |
111 | ACR_REGNUM = 15, | |
112 | BZ_REGNUM = 16, | |
113 | PID_REGNUM = 18, | |
114 | SRS_REGNUM = 19, | |
115 | WZ_REGNUM = 20, | |
116 | EXS_REGNUM = 21, | |
117 | EDA_REGNUM = 22, | |
118 | DZ_REGNUM = 24, | |
119 | EBP_REGNUM = 25, | |
120 | ERP_REGNUM = 26, | |
121 | NRP_REGNUM = 28, | |
122 | CCS_REGNUM = 29, | |
123 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
124 | SPC_REGNUM = 31, | |
125 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
126 | ||
127 | S0_REGNUM = 33, | |
128 | S1_REGNUM = 34, | |
129 | S2_REGNUM = 35, | |
130 | S3_REGNUM = 36, | |
131 | S4_REGNUM = 37, | |
132 | S5_REGNUM = 38, | |
133 | S6_REGNUM = 39, | |
134 | S7_REGNUM = 40, | |
135 | S8_REGNUM = 41, | |
136 | S9_REGNUM = 42, | |
137 | S10_REGNUM = 43, | |
138 | S11_REGNUM = 44, | |
139 | S12_REGNUM = 45, | |
140 | S13_REGNUM = 46, | |
141 | S14_REGNUM = 47, | |
142 | S15_REGNUM = 48, | |
29134980 OF |
143 | }; |
144 | ||
145 | extern const struct cris_spec_reg cris_spec_regs[]; | |
146 | ||
147 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
148 | register names and sizes.*/ | |
a5f6c8f5 | 149 | static unsigned int usr_cmd_cris_version; |
29134980 OF |
150 | |
151 | /* Indicates whether to trust the above variable. */ | |
152 | static int usr_cmd_cris_version_valid = 0; | |
153 | ||
a5f6c8f5 OF |
154 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
155 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 156 | |
29134980 OF |
157 | /* CRIS architecture specific information. */ |
158 | struct gdbarch_tdep | |
159 | { | |
a5f6c8f5 OF |
160 | unsigned int cris_version; |
161 | int cris_dwarf2_cfi; | |
29134980 OF |
162 | }; |
163 | ||
164 | /* Functions for accessing target dependent data. */ | |
165 | ||
166 | static int | |
167 | cris_version (void) | |
168 | { | |
169 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
170 | } | |
171 | ||
a5f6c8f5 OF |
172 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
173 | ||
174 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
175 | #define SIGTRAMP_OFFSET0 0 | |
176 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
177 | #define SIGTRAMP_OFFSET1 4 | |
178 | ||
179 | static const unsigned short sigtramp_code[] = | |
180 | { | |
181 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
182 | SIGTRAMP_INSN1 /* break 13 */ | |
183 | }; | |
184 | ||
185 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
186 | ||
187 | /* Note: same length as normal sigtramp code. */ | |
188 | ||
189 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 190 | { |
a5f6c8f5 OF |
191 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
192 | SIGTRAMP_INSN1 /* break 13 */ | |
193 | }; | |
194 | ||
195 | /* If PC is in a sigtramp routine, return the address of the start of | |
196 | the routine. Otherwise, return 0. */ | |
197 | ||
198 | static CORE_ADDR | |
199 | cris_sigtramp_start (struct frame_info *next_frame) | |
200 | { | |
201 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
202 | unsigned short buf[SIGTRAMP_LEN]; | |
203 | ||
204 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
205 | return 0; | |
206 | ||
207 | if (buf[0] != SIGTRAMP_INSN0) | |
208 | { | |
209 | if (buf[0] != SIGTRAMP_INSN1) | |
210 | return 0; | |
211 | ||
212 | pc -= SIGTRAMP_OFFSET1; | |
213 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
214 | return 0; | |
215 | } | |
216 | ||
217 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
218 | return 0; | |
219 | ||
220 | return pc; | |
221 | } | |
222 | ||
223 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
224 | the routine. Otherwise, return 0. */ | |
225 | ||
226 | static CORE_ADDR | |
227 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
228 | { | |
229 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
230 | unsigned short buf[SIGTRAMP_LEN]; | |
231 | ||
232 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
233 | return 0; | |
234 | ||
235 | if (buf[0] != SIGTRAMP_INSN0) | |
236 | { | |
237 | if (buf[0] != SIGTRAMP_INSN1) | |
238 | return 0; | |
239 | ||
240 | pc -= SIGTRAMP_OFFSET1; | |
241 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
242 | return 0; | |
243 | } | |
244 | ||
245 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
246 | return 0; | |
247 | ||
248 | return pc; | |
249 | } | |
250 | ||
251 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
252 | routine, return the address of the associated sigcontext structure. */ | |
253 | ||
254 | static CORE_ADDR | |
255 | cris_sigcontext_addr (struct frame_info *next_frame) | |
256 | { | |
257 | CORE_ADDR pc; | |
258 | CORE_ADDR sp; | |
259 | char buf[4]; | |
260 | ||
261 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
262 | sp = extract_unsigned_integer (buf, 4); | |
263 | ||
264 | /* Look for normal sigtramp frame first. */ | |
265 | pc = cris_sigtramp_start (next_frame); | |
266 | if (pc) | |
267 | { | |
268 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
269 | struct sigcontext as its first member, meaning the SP points to | |
270 | it already. */ | |
271 | return sp; | |
272 | } | |
273 | ||
274 | pc = cris_rt_sigtramp_start (next_frame); | |
275 | if (pc) | |
276 | { | |
277 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
278 | a struct ucontext, which in turn contains a struct sigcontext. | |
279 | Magic digging: | |
280 | 4 + 4 + 128 to struct ucontext, then | |
281 | 4 + 4 + 12 to struct sigcontext. */ | |
282 | return (sp + 156); | |
283 | } | |
284 | ||
285 | error ("Couldn't recognize signal trampoline."); | |
286 | return 0; | |
29134980 OF |
287 | } |
288 | ||
2e4b5889 | 289 | struct cris_unwind_cache |
29134980 | 290 | { |
2e4b5889 OF |
291 | /* The previous frame's inner most stack address. Used as this |
292 | frame ID's stack_addr. */ | |
293 | CORE_ADDR prev_sp; | |
294 | /* The frame's base, optionally used by the high-level debug info. */ | |
295 | CORE_ADDR base; | |
296 | int size; | |
297 | /* How far the SP and r8 (FP) have been offset from the start of | |
298 | the stack frame (as defined by the previous frame's stack | |
299 | pointer). */ | |
300 | LONGEST sp_offset; | |
301 | LONGEST r8_offset; | |
302 | int uses_frame; | |
303 | ||
304 | /* From old frame_extra_info struct. */ | |
29134980 OF |
305 | CORE_ADDR return_pc; |
306 | int leaf_function; | |
2e4b5889 OF |
307 | |
308 | /* Table indicating the location of each and every register. */ | |
309 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
310 | }; |
311 | ||
a5f6c8f5 OF |
312 | static struct cris_unwind_cache * |
313 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
314 | void **this_cache) | |
315 | { | |
316 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
317 | struct cris_unwind_cache *info; | |
318 | CORE_ADDR pc; | |
319 | CORE_ADDR sp; | |
320 | CORE_ADDR addr; | |
321 | char buf[4]; | |
322 | int i; | |
323 | ||
324 | if ((*this_cache)) | |
325 | return (*this_cache); | |
326 | ||
327 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
328 | (*this_cache) = info; | |
329 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
330 | ||
331 | /* Zero all fields. */ | |
332 | info->prev_sp = 0; | |
333 | info->base = 0; | |
334 | info->size = 0; | |
335 | info->sp_offset = 0; | |
336 | info->r8_offset = 0; | |
337 | info->uses_frame = 0; | |
338 | info->return_pc = 0; | |
339 | info->leaf_function = 0; | |
340 | ||
341 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
342 | info->base = extract_unsigned_integer (buf, 4); | |
343 | ||
344 | addr = cris_sigcontext_addr (next_frame); | |
345 | ||
346 | /* Layout of the sigcontext struct: | |
347 | struct sigcontext { | |
348 | struct pt_regs regs; | |
349 | unsigned long oldmask; | |
350 | unsigned long usp; | |
351 | }; */ | |
352 | ||
c600d464 OF |
353 | if (tdep->cris_version == 10) |
354 | { | |
355 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
356 | struct pt_regs. */ | |
357 | for (i = 0; i <= 13; i++) | |
358 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
359 | ||
360 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
361 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
362 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
363 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
364 | it though since that will mean that the backtrace will show a PC | |
365 | different from what is shown when stopped. */ | |
366 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
367 | info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; | |
368 | info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); | |
369 | } | |
370 | else | |
371 | { | |
372 | /* CRISv32. */ | |
373 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
374 | struct pt_regs. */ | |
375 | for (i = 0; i <= 13; i++) | |
376 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
377 | ||
378 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
379 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
380 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
381 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
382 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
383 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
384 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
385 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
386 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
387 | ||
388 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
389 | be wrong at this point. This problem manifests itself in the | |
390 | sigaltstack.exp test case, which occasionally generates FAILs when | |
391 | the signal is received while in a delay slot. | |
392 | ||
393 | This could be solved by a couple of read_memory_unsigned_integer and a | |
394 | trad_frame_set_value. */ | |
395 | info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM]; | |
396 | ||
397 | info->saved_regs[SP_REGNUM].addr = addr + (25 * 4); | |
398 | } | |
a5f6c8f5 OF |
399 | |
400 | return info; | |
401 | } | |
402 | ||
403 | static void | |
404 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
405 | struct frame_id *this_id) | |
406 | { | |
407 | struct cris_unwind_cache *cache = | |
408 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
409 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
410 | } | |
411 | ||
412 | /* Forward declaration. */ | |
413 | ||
414 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
415 | void **this_prologue_cache, | |
416 | int regnum, int *optimizedp, | |
417 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
418 | int *realnump, void *bufferp); | |
419 | static void | |
420 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
421 | void **this_cache, | |
422 | int regnum, int *optimizedp, | |
423 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
424 | int *realnump, void *valuep) | |
425 | { | |
426 | /* Make sure we've initialized the cache. */ | |
427 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
428 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
429 | optimizedp, lvalp, addrp, realnump, valuep); | |
430 | } | |
431 | ||
432 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
433 | { | |
434 | SIGTRAMP_FRAME, | |
435 | cris_sigtramp_frame_this_id, | |
436 | cris_sigtramp_frame_prev_register | |
437 | }; | |
438 | ||
439 | static const struct frame_unwind * | |
440 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
441 | { | |
442 | if (cris_sigtramp_start (next_frame) | |
443 | || cris_rt_sigtramp_start (next_frame)) | |
444 | return &cris_sigtramp_frame_unwind; | |
445 | ||
446 | return NULL; | |
447 | } | |
448 | ||
c600d464 OF |
449 | int |
450 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
451 | struct frame_info *this_frame) | |
452 | { | |
453 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
454 | ULONGEST erp; | |
455 | int ret = 0; | |
456 | char buf[4]; | |
457 | ||
458 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
459 | erp = extract_unsigned_integer (buf, 4); | |
460 | ||
461 | if (erp & 0x1) | |
462 | { | |
463 | /* In delay slot - check if there's a breakpoint at the preceding | |
464 | instruction. */ | |
465 | if (breakpoint_here_p (erp & ~0x1)) | |
466 | ret = 1; | |
467 | } | |
468 | return ret; | |
469 | } | |
470 | ||
471 | /* Hardware watchpoint support. */ | |
472 | ||
473 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
474 | (any combination of read/write is fine). */ | |
475 | ||
476 | int | |
477 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
478 | { | |
479 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
480 | ||
481 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
482 | ||
483 | if (tdep->cris_version != 32) | |
484 | return 0; | |
485 | else | |
486 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
487 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
488 | || type == bp_hardware_watchpoint) && count <= 6) | |
489 | || (type == bp_hardware_breakpoint && count <= 1)); | |
490 | } | |
491 | ||
492 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
493 | which have no alignment or length restrictions. */ | |
494 | ||
495 | int | |
496 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
497 | { | |
498 | return 1; | |
499 | } | |
500 | ||
501 | /* If the inferior has some watchpoint that triggered, return the | |
502 | address associated with that watchpoint. Otherwise, return | |
503 | zero. */ | |
504 | ||
505 | CORE_ADDR | |
506 | cris_stopped_data_address (void) | |
507 | { | |
508 | CORE_ADDR eda; | |
509 | eda = read_register (EDA_REGNUM); | |
510 | return eda; | |
511 | } | |
512 | ||
29134980 | 513 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 514 | |
29134980 OF |
515 | typedef |
516 | struct instruction_environment | |
517 | { | |
518 | unsigned long reg[NUM_GENREGS]; | |
519 | unsigned long preg[NUM_SPECREGS]; | |
520 | unsigned long branch_break_address; | |
521 | unsigned long delay_slot_pc; | |
522 | unsigned long prefix_value; | |
523 | int branch_found; | |
524 | int prefix_found; | |
525 | int invalid; | |
526 | int slot_needed; | |
527 | int delay_slot_pc_active; | |
528 | int xflag_found; | |
529 | int disable_interrupt; | |
530 | } inst_env_type; | |
531 | ||
532 | /* Save old breakpoints in order to restore the state before a single_step. | |
533 | At most, two breakpoints will have to be remembered. */ | |
534 | typedef | |
535 | char binsn_quantum[BREAKPOINT_MAX]; | |
536 | static binsn_quantum break_mem[2]; | |
537 | static CORE_ADDR next_pc = 0; | |
538 | static CORE_ADDR branch_target_address = 0; | |
539 | static unsigned char branch_break_inserted = 0; | |
540 | ||
541 | /* Machine-dependencies in CRIS for opcodes. */ | |
542 | ||
543 | /* Instruction sizes. */ | |
544 | enum cris_instruction_sizes | |
545 | { | |
546 | INST_BYTE_SIZE = 0, | |
547 | INST_WORD_SIZE = 1, | |
548 | INST_DWORD_SIZE = 2 | |
549 | }; | |
550 | ||
551 | /* Addressing modes. */ | |
552 | enum cris_addressing_modes | |
553 | { | |
554 | REGISTER_MODE = 1, | |
555 | INDIRECT_MODE = 2, | |
556 | AUTOINC_MODE = 3 | |
557 | }; | |
558 | ||
559 | /* Prefix addressing modes. */ | |
560 | enum cris_prefix_addressing_modes | |
561 | { | |
562 | PREFIX_INDEX_MODE = 2, | |
563 | PREFIX_ASSIGN_MODE = 3, | |
564 | ||
565 | /* Handle immediate byte offset addressing mode prefix format. */ | |
566 | PREFIX_OFFSET_MODE = 2 | |
567 | }; | |
568 | ||
569 | /* Masks for opcodes. */ | |
570 | enum cris_opcode_masks | |
571 | { | |
572 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
573 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
574 | SIGNED_BYTE_MASK = 0x80, | |
575 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
576 | SIGNED_WORD_MASK = 0x8000, | |
577 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
578 | SIGNED_DWORD_MASK = 0x80000000, | |
579 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
580 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
581 | }; | |
582 | ||
583 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
584 | Bit 15 - 12 Operand2 | |
585 | 11 - 10 Mode | |
586 | 9 - 6 Opcode | |
587 | 5 - 4 Size | |
588 | 3 - 0 Operand1 */ | |
589 | ||
590 | static int | |
591 | cris_get_operand2 (unsigned short insn) | |
592 | { | |
593 | return ((insn & 0xF000) >> 12); | |
594 | } | |
595 | ||
596 | static int | |
597 | cris_get_mode (unsigned short insn) | |
598 | { | |
599 | return ((insn & 0x0C00) >> 10); | |
600 | } | |
601 | ||
602 | static int | |
603 | cris_get_opcode (unsigned short insn) | |
604 | { | |
605 | return ((insn & 0x03C0) >> 6); | |
606 | } | |
607 | ||
608 | static int | |
609 | cris_get_size (unsigned short insn) | |
610 | { | |
611 | return ((insn & 0x0030) >> 4); | |
612 | } | |
613 | ||
614 | static int | |
615 | cris_get_operand1 (unsigned short insn) | |
616 | { | |
617 | return (insn & 0x000F); | |
618 | } | |
619 | ||
620 | /* Additional functions in order to handle opcodes. */ | |
621 | ||
29134980 OF |
622 | static int |
623 | cris_get_quick_value (unsigned short insn) | |
624 | { | |
625 | return (insn & 0x003F); | |
626 | } | |
627 | ||
628 | static int | |
629 | cris_get_bdap_quick_offset (unsigned short insn) | |
630 | { | |
631 | return (insn & 0x00FF); | |
632 | } | |
633 | ||
634 | static int | |
635 | cris_get_branch_short_offset (unsigned short insn) | |
636 | { | |
637 | return (insn & 0x00FF); | |
638 | } | |
639 | ||
640 | static int | |
641 | cris_get_asr_shift_steps (unsigned long value) | |
642 | { | |
643 | return (value & 0x3F); | |
644 | } | |
645 | ||
29134980 OF |
646 | static int |
647 | cris_get_clear_size (unsigned short insn) | |
648 | { | |
649 | return ((insn) & 0xC000); | |
650 | } | |
651 | ||
652 | static int | |
653 | cris_is_signed_extend_bit_on (unsigned short insn) | |
654 | { | |
655 | return (((insn) & 0x20) == 0x20); | |
656 | } | |
657 | ||
658 | static int | |
659 | cris_is_xflag_bit_on (unsigned short insn) | |
660 | { | |
661 | return (((insn) & 0x1000) == 0x1000); | |
662 | } | |
663 | ||
664 | static void | |
665 | cris_set_size_to_dword (unsigned short *insn) | |
666 | { | |
667 | *insn &= 0xFFCF; | |
668 | *insn |= 0x20; | |
669 | } | |
670 | ||
8535cb38 | 671 | static signed char |
29134980 OF |
672 | cris_get_signed_offset (unsigned short insn) |
673 | { | |
8535cb38 | 674 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
675 | } |
676 | ||
677 | /* Calls an op function given the op-type, working on the insn and the | |
678 | inst_env. */ | |
679 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
680 | ||
29134980 OF |
681 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
682 | struct gdbarch_list *); | |
683 | ||
29134980 OF |
684 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
685 | ||
a5f6c8f5 OF |
686 | static void set_cris_version (char *ignore_args, int from_tty, |
687 | struct cmd_list_element *c); | |
29134980 | 688 | |
a5f6c8f5 OF |
689 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
690 | struct cmd_list_element *c); | |
29134980 | 691 | |
2e4b5889 OF |
692 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
693 | struct frame_info *next_frame, | |
694 | struct cris_unwind_cache *info); | |
695 | ||
696 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, | |
697 | struct frame_info *next_frame); | |
698 | ||
699 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
700 | struct frame_info *next_frame); | |
701 | ||
702 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
703 | order. The below implements a FILO (stack) to do this. |
704 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
705 | |
706 | struct stack_item | |
707 | { | |
708 | int len; | |
709 | struct stack_item *prev; | |
710 | void *data; | |
711 | }; | |
712 | ||
713 | static struct stack_item * | |
714 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
715 | { | |
716 | struct stack_item *si; | |
717 | si = xmalloc (sizeof (struct stack_item)); | |
718 | si->data = xmalloc (len); | |
719 | si->len = len; | |
720 | si->prev = prev; | |
721 | memcpy (si->data, contents, len); | |
722 | return si; | |
723 | } | |
724 | ||
725 | static struct stack_item * | |
726 | pop_stack_item (struct stack_item *si) | |
727 | { | |
728 | struct stack_item *dead = si; | |
729 | si = si->prev; | |
730 | xfree (dead->data); | |
731 | xfree (dead); | |
732 | return si; | |
733 | } | |
734 | ||
735 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
736 | the saved registers of frame described by FRAME_INFO. This | |
737 | includes special registers such as pc and fp saved in special ways | |
738 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 739 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
740 | |
741 | struct cris_unwind_cache * | |
742 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
743 | void **this_prologue_cache) | |
744 | { | |
745 | CORE_ADDR pc; | |
746 | struct cris_unwind_cache *info; | |
747 | int i; | |
748 | ||
749 | if ((*this_prologue_cache)) | |
750 | return (*this_prologue_cache); | |
751 | ||
752 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
753 | (*this_prologue_cache) = info; | |
754 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
755 | ||
756 | /* Zero all fields. */ | |
757 | info->prev_sp = 0; | |
758 | info->base = 0; | |
759 | info->size = 0; | |
760 | info->sp_offset = 0; | |
761 | info->r8_offset = 0; | |
762 | info->uses_frame = 0; | |
763 | info->return_pc = 0; | |
764 | info->leaf_function = 0; | |
765 | ||
766 | /* Prologue analysis does the rest... */ | |
767 | cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info); | |
768 | ||
769 | return info; | |
770 | } | |
771 | ||
772 | /* Given a GDB frame, determine the address of the calling function's | |
773 | frame. This will be used to create a new GDB frame struct. */ | |
774 | ||
775 | static void | |
776 | cris_frame_this_id (struct frame_info *next_frame, | |
777 | void **this_prologue_cache, | |
778 | struct frame_id *this_id) | |
779 | { | |
780 | struct cris_unwind_cache *info | |
781 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
782 | CORE_ADDR base; | |
783 | CORE_ADDR func; | |
784 | struct frame_id id; | |
785 | ||
786 | /* The FUNC is easy. */ | |
787 | func = frame_func_unwind (next_frame); | |
788 | ||
789 | /* Hopefully the prologue analysis either correctly determined the | |
790 | frame's base (which is the SP from the previous frame), or set | |
791 | that base to "NULL". */ | |
792 | base = info->prev_sp; | |
793 | if (base == 0) | |
794 | return; | |
795 | ||
796 | id = frame_id_build (base, func); | |
797 | ||
798 | (*this_id) = id; | |
799 | } | |
800 | ||
801 | static void | |
802 | cris_frame_prev_register (struct frame_info *next_frame, | |
803 | void **this_prologue_cache, | |
804 | int regnum, int *optimizedp, | |
805 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
806 | int *realnump, void *bufferp) | |
807 | { | |
808 | struct cris_unwind_cache *info | |
809 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
810 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
811 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
812 | } |
813 | ||
814 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
815 | dummy frame. The frame ID's base needs to match the TOS value | |
816 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
817 | breakpoint. */ | |
818 | ||
819 | static struct frame_id | |
820 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
821 | { | |
822 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
823 | frame_pc_unwind (next_frame)); | |
824 | } | |
825 | ||
826 | static CORE_ADDR | |
827 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
828 | { | |
829 | /* Align to the size of an instruction (so that they can safely be | |
830 | pushed onto the stack). */ | |
831 | return sp & ~3; | |
832 | } | |
833 | ||
834 | static CORE_ADDR | |
835 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
836 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
837 | struct value **args, int nargs, | |
838 | struct type *value_type, | |
839 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
840 | { | |
841 | /* Allocate space sufficient for a breakpoint. */ | |
842 | sp = (sp - 4) & ~3; | |
843 | /* Store the address of that breakpoint */ | |
844 | *bp_addr = sp; | |
845 | /* CRIS always starts the call at the callee's entry point. */ | |
846 | *real_pc = funaddr; | |
847 | return sp; | |
848 | } | |
849 | ||
850 | static CORE_ADDR | |
7d9b040b | 851 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
852 | struct regcache *regcache, CORE_ADDR bp_addr, |
853 | int nargs, struct value **args, CORE_ADDR sp, | |
854 | int struct_return, CORE_ADDR struct_addr) | |
855 | { | |
856 | int stack_alloc; | |
857 | int stack_offset; | |
858 | int argreg; | |
859 | int argnum; | |
860 | ||
861 | CORE_ADDR regval; | |
862 | ||
863 | /* The function's arguments and memory allocated by gdb for the arguments to | |
864 | point at reside in separate areas on the stack. | |
865 | Both frame pointers grow toward higher addresses. */ | |
866 | CORE_ADDR fp_arg; | |
867 | CORE_ADDR fp_mem; | |
868 | ||
869 | struct stack_item *si = NULL; | |
870 | ||
a5f6c8f5 | 871 | /* Push the return address. */ |
2e4b5889 OF |
872 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
873 | ||
874 | /* Are we returning a value using a structure return or a normal value | |
875 | return? struct_addr is the address of the reserved space for the return | |
876 | structure to be written on the stack. */ | |
877 | if (struct_return) | |
878 | { | |
879 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
880 | } | |
881 | ||
882 | /* Now load as many as possible of the first arguments into registers, | |
883 | and push the rest onto the stack. */ | |
884 | argreg = ARG1_REGNUM; | |
885 | stack_offset = 0; | |
886 | ||
887 | for (argnum = 0; argnum < nargs; argnum++) | |
888 | { | |
889 | int len; | |
890 | char *val; | |
891 | int reg_demand; | |
892 | int i; | |
893 | ||
4991999e | 894 | len = TYPE_LENGTH (value_type (args[argnum])); |
2e4b5889 OF |
895 | val = (char *) VALUE_CONTENTS (args[argnum]); |
896 | ||
897 | /* How may registers worth of storage do we need for this argument? */ | |
898 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
899 | ||
900 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
901 | { | |
902 | /* Data passed by value. Fits in available register(s). */ | |
903 | for (i = 0; i < reg_demand; i++) | |
904 | { | |
905 | regcache_cooked_write_unsigned (regcache, argreg, | |
906 | *(unsigned long *) val); | |
907 | argreg++; | |
908 | val += 4; | |
909 | } | |
910 | } | |
911 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
912 | { | |
913 | /* Data passed by value. Does not fit in available register(s). | |
914 | Use the register(s) first, then the stack. */ | |
915 | for (i = 0; i < reg_demand; i++) | |
916 | { | |
917 | if (argreg <= ARG4_REGNUM) | |
918 | { | |
919 | regcache_cooked_write_unsigned (regcache, argreg, | |
920 | *(unsigned long *) val); | |
921 | argreg++; | |
922 | val += 4; | |
923 | } | |
924 | else | |
925 | { | |
926 | /* Push item for later so that pushed arguments | |
927 | come in the right order. */ | |
928 | si = push_stack_item (si, val, 4); | |
929 | val += 4; | |
930 | } | |
931 | } | |
932 | } | |
933 | else if (len > (2 * 4)) | |
934 | { | |
935 | /* FIXME */ | |
936 | internal_error (__FILE__, __LINE__, "We don't do this"); | |
937 | } | |
938 | else | |
939 | { | |
940 | /* Data passed by value. No available registers. Put it on | |
941 | the stack. */ | |
942 | si = push_stack_item (si, val, len); | |
943 | } | |
944 | } | |
945 | ||
946 | while (si) | |
947 | { | |
948 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
949 | the function prologue. */ | |
950 | sp = (sp - si->len) & ~3; | |
951 | write_memory (sp, si->data, si->len); | |
952 | si = pop_stack_item (si); | |
953 | } | |
954 | ||
955 | /* Finally, update the SP register. */ | |
956 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
957 | ||
958 | return sp; | |
959 | } | |
960 | ||
961 | static const struct frame_unwind cris_frame_unwind = { | |
962 | NORMAL_FRAME, | |
963 | cris_frame_this_id, | |
964 | cris_frame_prev_register | |
965 | }; | |
966 | ||
967 | const struct frame_unwind * | |
968 | cris_frame_sniffer (struct frame_info *next_frame) | |
969 | { | |
970 | return &cris_frame_unwind; | |
971 | } | |
972 | ||
973 | static CORE_ADDR | |
974 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
975 | { | |
976 | struct cris_unwind_cache *info | |
977 | = cris_frame_unwind_cache (next_frame, this_cache); | |
978 | return info->base; | |
979 | } | |
980 | ||
981 | static const struct frame_base cris_frame_base = { | |
982 | &cris_frame_unwind, | |
983 | cris_frame_base_address, | |
984 | cris_frame_base_address, | |
985 | cris_frame_base_address | |
986 | }; | |
987 | ||
29134980 OF |
988 | /* Frames information. The definition of the struct frame_info is |
989 | ||
990 | CORE_ADDR frame | |
991 | CORE_ADDR pc | |
5a203e44 | 992 | enum frame_type type; |
29134980 OF |
993 | CORE_ADDR return_pc |
994 | int leaf_function | |
995 | ||
996 | If the compilation option -fno-omit-frame-pointer is present the | |
997 | variable frame will be set to the content of R8 which is the frame | |
998 | pointer register. | |
999 | ||
1000 | The variable pc contains the address where execution is performed | |
1001 | in the present frame. The innermost frame contains the current content | |
1002 | of the register PC. All other frames contain the content of the | |
1003 | register PC in the next frame. | |
1004 | ||
5a203e44 AC |
1005 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1006 | (associated with a signal handler), dummy (associated with a dummy | |
1007 | frame). | |
29134980 OF |
1008 | |
1009 | The variable return_pc contains the address where execution should be | |
1010 | resumed when the present frame has finished, the return address. | |
1011 | ||
1012 | The variable leaf_function is 1 if the return address is in the register | |
1013 | SRP, and 0 if it is on the stack. | |
1014 | ||
1015 | Prologue instructions C-code. | |
1016 | The prologue may consist of (-fno-omit-frame-pointer) | |
1017 | 1) 2) | |
1018 | push srp | |
1019 | push r8 push r8 | |
1020 | move.d sp,r8 move.d sp,r8 | |
1021 | subq X,sp subq X,sp | |
1022 | movem rY,[sp] movem rY,[sp] | |
1023 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1024 | ||
1025 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1026 | ||
1027 | Note that this assumption is extremely brittle, and will break at the | |
1028 | slightest change in GCC's prologue. | |
1029 | ||
1030 | If local variables are declared or register contents are saved on stack | |
1031 | the subq-instruction will be present with X as the number of bytes | |
1032 | needed for storage. The reshuffle with respect to r8 may be performed | |
1033 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1034 | The offset U should be representable by a signed 8-bit value in all cases. | |
1035 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1036 | by another word containing the instruction. | |
1037 | ||
1038 | Degenerate cases: | |
1039 | 3) | |
1040 | push r8 | |
1041 | move.d sp,r8 | |
1042 | move.d r8,sp | |
1043 | pop r8 | |
1044 | ||
1045 | Prologue instructions C++-code. | |
1046 | Case 1) and 2) in the C-code may be followed by | |
1047 | ||
1048 | move.d r10,rS ; this | |
1049 | move.d r11,rT ; P1 | |
1050 | move.d r12,rU ; P2 | |
1051 | move.d r13,rV ; P3 | |
1052 | move.S [r8+U],rZ ; P4 | |
1053 | ||
1054 | if any of the call parameters are stored. The host expects these | |
1055 | instructions to be executed in order to get the call parameters right. */ | |
1056 | ||
1057 | /* Examine the prologue of a function. The variable ip is the address of | |
1058 | the first instruction of the prologue. The variable limit is the address | |
1059 | of the first instruction after the prologue. The variable fi contains the | |
1060 | information in struct frame_info. The variable frameless_p controls whether | |
1061 | the entire prologue is examined (0) or just enough instructions to | |
1062 | determine that it is a prologue (1). */ | |
1063 | ||
a78f21af | 1064 | static CORE_ADDR |
2e4b5889 OF |
1065 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1066 | struct cris_unwind_cache *info) | |
29134980 OF |
1067 | { |
1068 | /* Present instruction. */ | |
1069 | unsigned short insn; | |
1070 | ||
1071 | /* Next instruction, lookahead. */ | |
1072 | unsigned short insn_next; | |
1073 | int regno; | |
1074 | ||
1075 | /* Is there a push fp? */ | |
1076 | int have_fp; | |
1077 | ||
1078 | /* Number of byte on stack used for local variables and movem. */ | |
1079 | int val; | |
1080 | ||
1081 | /* Highest register number in a movem. */ | |
1082 | int regsave; | |
1083 | ||
1084 | /* move.d r<source_register>,rS */ | |
1085 | short source_register; | |
1086 | ||
2e4b5889 OF |
1087 | /* Scan limit. */ |
1088 | int limit; | |
29134980 | 1089 | |
2e4b5889 OF |
1090 | /* This frame is with respect to a leaf until a push srp is found. */ |
1091 | if (info) | |
1092 | { | |
1093 | info->leaf_function = 1; | |
1094 | } | |
29134980 OF |
1095 | |
1096 | /* Assume nothing on stack. */ | |
1097 | val = 0; | |
1098 | regsave = -1; | |
1099 | ||
2e4b5889 OF |
1100 | /* If we were called without a next_frame, that means we were called |
1101 | from cris_skip_prologue which already tried to find the end of the | |
1102 | prologue through the symbol information. 64 instructions past current | |
1103 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1104 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1105 | |
29134980 | 1106 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1107 | while (pc > 0 && pc < limit) |
29134980 | 1108 | { |
2e4b5889 OF |
1109 | insn = read_memory_unsigned_integer (pc, 2); |
1110 | pc += 2; | |
29134980 OF |
1111 | if (insn == 0xE1FC) |
1112 | { | |
1113 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1114 | insn_next = read_memory_unsigned_integer (pc, 2); |
1115 | pc += 2; | |
29134980 | 1116 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1117 | if (info) |
1118 | { | |
1119 | info->sp_offset += 4; | |
1120 | } | |
dbbff683 OF |
1121 | /* This check, meant to recognize srp, used to be regno == |
1122 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1123 | if (insn_next == 0xBE7E) | |
29134980 | 1124 | { |
2e4b5889 OF |
1125 | if (info) |
1126 | { | |
1127 | info->leaf_function = 0; | |
1128 | } | |
29134980 | 1129 | } |
b4206d25 OF |
1130 | else if (insn_next == 0x8FEE) |
1131 | { | |
1132 | /* push $r8 */ | |
1133 | if (info) | |
1134 | { | |
1135 | info->r8_offset = info->sp_offset; | |
1136 | } | |
1137 | } | |
29134980 OF |
1138 | } |
1139 | else if (insn == 0x866E) | |
1140 | { | |
1141 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1142 | if (info) |
1143 | { | |
1144 | info->uses_frame = 1; | |
2e4b5889 | 1145 | } |
29134980 OF |
1146 | continue; |
1147 | } | |
1148 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1149 | && cris_get_mode (insn) == 0x0000 | |
1150 | && cris_get_opcode (insn) == 0x000A) | |
1151 | { | |
1152 | /* subq <val>,sp */ | |
2e4b5889 OF |
1153 | if (info) |
1154 | { | |
1155 | info->sp_offset += cris_get_quick_value (insn); | |
1156 | } | |
29134980 OF |
1157 | } |
1158 | else if (cris_get_mode (insn) == 0x0002 | |
1159 | && cris_get_opcode (insn) == 0x000F | |
1160 | && cris_get_size (insn) == 0x0003 | |
1161 | && cris_get_operand1 (insn) == SP_REGNUM) | |
1162 | { | |
1163 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1164 | regsave = cris_get_operand2 (insn); |
1165 | } | |
1166 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1167 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1168 | && (cris_get_signed_offset (insn) < 0)) | |
1169 | { | |
1170 | /* Immediate byte offset addressing prefix word with sp as base | |
1171 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1172 | is between 64 and 128. | |
1173 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1174 | if (info) |
1175 | { | |
1176 | info->sp_offset += -cris_get_signed_offset (insn); | |
1177 | } | |
1178 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1179 | pc += 2; | |
29134980 OF |
1180 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1181 | && cris_get_opcode (insn_next) == 0x000F | |
1182 | && cris_get_size (insn_next) == 0x0003 | |
1183 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
1184 | { | |
29134980 OF |
1185 | regsave = cris_get_operand2 (insn_next); |
1186 | } | |
1187 | else | |
1188 | { | |
1189 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1190 | pc -= 4; |
29134980 OF |
1191 | break; |
1192 | } | |
1193 | } | |
1194 | else if (cris_get_mode (insn) == 0x0001 | |
1195 | && cris_get_opcode (insn) == 0x0009 | |
1196 | && cris_get_size (insn) == 0x0002) | |
1197 | { | |
1198 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1199 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1200 | |
1201 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1202 | like (this example taken from relocate_doit): | |
1203 | move.d $pc,$r0 | |
1204 | sub.d 0xfffef426,$r0 | |
1205 | which isn't covered by the source_register check below. Question | |
1206 | is whether to add a check for this combo, or make better use of | |
1207 | the limit variable instead. */ | |
29134980 OF |
1208 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1209 | { | |
1210 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1211 | pc -= 2; |
29134980 OF |
1212 | break; |
1213 | } | |
1214 | } | |
2e4b5889 | 1215 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1216 | /* The size is a fixed-size. */ |
1217 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1218 | /* A negative offset. */ | |
1219 | && (cris_get_signed_offset (insn) < 0)) | |
1220 | { | |
1221 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1222 | insn_next = read_memory_unsigned_integer (pc, 2); |
1223 | pc += 2; | |
29134980 OF |
1224 | regno = cris_get_operand2 (insn_next); |
1225 | if ((regno >= 0 && regno < SP_REGNUM) | |
1226 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1227 | && cris_get_opcode (insn_next) == 0x000F) | |
1228 | { | |
1229 | /* move.S rZ,[r8-U] */ | |
1230 | continue; | |
1231 | } | |
1232 | else | |
1233 | { | |
1234 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1235 | pc -= 4; |
29134980 OF |
1236 | break; |
1237 | } | |
1238 | } | |
2e4b5889 | 1239 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1240 | /* The size is a fixed-size. */ |
1241 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1242 | /* A positive offset. */ | |
1243 | && (cris_get_signed_offset (insn) > 0)) | |
1244 | { | |
1245 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1246 | insn_next = read_memory_unsigned_integer (pc, 2); |
1247 | pc += 2; | |
29134980 OF |
1248 | regno = cris_get_operand2 (insn_next); |
1249 | if ((regno >= 0 && regno < SP_REGNUM) | |
1250 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1251 | && cris_get_opcode (insn_next) == 0x0009 | |
1252 | && cris_get_operand1 (insn_next) == regno) | |
1253 | { | |
1254 | /* move.S [r8+U],rZ */ | |
1255 | continue; | |
1256 | } | |
1257 | else | |
1258 | { | |
1259 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1260 | pc -= 4; |
29134980 OF |
1261 | break; |
1262 | } | |
1263 | } | |
1264 | else | |
1265 | { | |
1266 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1267 | pc -= 2; |
29134980 OF |
1268 | break; |
1269 | } | |
1270 | } | |
29134980 | 1271 | |
2e4b5889 OF |
1272 | /* We only want to know the end of the prologue when next_frame and info |
1273 | are NULL (called from cris_skip_prologue i.e.). */ | |
1274 | if (next_frame == NULL && info == NULL) | |
1275 | { | |
1276 | return pc; | |
1277 | } | |
29134980 | 1278 | |
2e4b5889 OF |
1279 | info->size = info->sp_offset; |
1280 | ||
1281 | /* Compute the previous frame's stack pointer (which is also the | |
1282 | frame's ID's stack address), and this frame's base pointer. */ | |
1283 | if (info->uses_frame) | |
29134980 | 1284 | { |
2e4b5889 OF |
1285 | ULONGEST this_base; |
1286 | /* The SP was moved to the FP. This indicates that a new frame | |
1287 | was created. Get THIS frame's FP value by unwinding it from | |
1288 | the next frame. */ | |
1289 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1290 | &this_base); | |
1291 | info->base = this_base; | |
b4206d25 OF |
1292 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1293 | ||
2e4b5889 OF |
1294 | /* The FP points at the last saved register. Adjust the FP back |
1295 | to before the first saved register giving the SP. */ | |
1296 | info->prev_sp = info->base + info->r8_offset; | |
1297 | } | |
1298 | else | |
1299 | { | |
1300 | ULONGEST this_base; | |
1301 | /* Assume that the FP is this frame's SP but with that pushed | |
1302 | stack space added back. */ | |
1303 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1304 | info->base = this_base; | |
1305 | info->prev_sp = info->base + info->size; | |
1306 | } | |
29134980 | 1307 | |
2e4b5889 OF |
1308 | /* Calculate the addresses for the saved registers on the stack. */ |
1309 | /* FIXME: The address calculation should really be done on the fly while | |
1310 | we're analyzing the prologue (we only hold one regsave value as it is | |
1311 | now). */ | |
1312 | val = info->sp_offset; | |
1313 | ||
1314 | for (regno = regsave; regno >= 0; regno--) | |
1315 | { | |
1316 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1317 | val -= 4; | |
1318 | } | |
1319 | ||
1320 | /* The previous frame's SP needed to be computed. Save the computed | |
1321 | value. */ | |
1322 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
1323 | ||
1324 | if (!info->leaf_function) | |
1325 | { | |
b4206d25 OF |
1326 | /* SRP saved on the stack. But where? */ |
1327 | if (info->r8_offset == 0) | |
1328 | { | |
1329 | /* R8 not pushed yet. */ | |
1330 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1331 | } | |
1332 | else | |
1333 | { | |
1334 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1335 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1336 | } | |
29134980 | 1337 | } |
2e4b5889 OF |
1338 | |
1339 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1340 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1341 | ||
1342 | return pc; | |
29134980 OF |
1343 | } |
1344 | ||
1345 | /* Advance pc beyond any function entry prologue instructions at pc | |
1346 | to reach some "real" code. */ | |
1347 | ||
29134980 OF |
1348 | /* Given a PC value corresponding to the start of a function, return the PC |
1349 | of the first instruction after the function prologue. */ | |
1350 | ||
a78f21af | 1351 | static CORE_ADDR |
2e4b5889 | 1352 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1353 | { |
2e4b5889 OF |
1354 | CORE_ADDR func_addr, func_end; |
1355 | struct symtab_and_line sal; | |
29134980 OF |
1356 | CORE_ADDR pc_after_prologue; |
1357 | ||
2e4b5889 OF |
1358 | /* If we have line debugging information, then the end of the prologue |
1359 | should the first assembly instruction of the first source line. */ | |
1360 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1361 | { | |
1362 | sal = find_pc_line (func_addr, 0); | |
1363 | if (sal.end > 0 && sal.end < func_end) | |
1364 | return sal.end; | |
1365 | } | |
29134980 | 1366 | |
2e4b5889 | 1367 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); |
29134980 OF |
1368 | return pc_after_prologue; |
1369 | } | |
1370 | ||
2e4b5889 OF |
1371 | static CORE_ADDR |
1372 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1373 | { | |
1374 | ULONGEST pc; | |
1375 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1376 | return pc; | |
1377 | } | |
1378 | ||
1379 | static CORE_ADDR | |
1380 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1381 | { | |
1382 | ULONGEST sp; | |
1383 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1384 | return sp; | |
1385 | } | |
1386 | ||
29134980 OF |
1387 | /* Use the program counter to determine the contents and size of a breakpoint |
1388 | instruction. It returns a pointer to a string of bytes that encode a | |
1389 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1390 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1391 | the breakpoint should be inserted. */ | |
1392 | ||
a78f21af | 1393 | static const unsigned char * |
29134980 OF |
1394 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1395 | { | |
1396 | static unsigned char break_insn[] = {0x38, 0xe9}; | |
1397 | *lenptr = 2; | |
1398 | ||
1399 | return break_insn; | |
1400 | } | |
1401 | ||
29134980 OF |
1402 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1403 | 0 otherwise. */ | |
1404 | ||
a78f21af | 1405 | static int |
29134980 OF |
1406 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1407 | { | |
1408 | int version = cris_version (); | |
1409 | ||
1410 | switch (spec_reg.applicable_version) | |
1411 | { | |
1412 | case cris_ver_version_all: | |
1413 | return 1; | |
1414 | case cris_ver_warning: | |
1415 | /* Indeterminate/obsolete. */ | |
1416 | return 0; | |
29134980 OF |
1417 | case cris_ver_v0_3: |
1418 | return (version >= 0 && version <= 3); | |
1419 | case cris_ver_v3p: | |
1420 | return (version >= 3); | |
1421 | case cris_ver_v8: | |
1422 | return (version == 8 || version == 9); | |
1423 | case cris_ver_v8p: | |
1424 | return (version >= 8); | |
c600d464 OF |
1425 | case cris_ver_v0_10: |
1426 | return (version >= 0 && version <= 10); | |
1427 | case cris_ver_v3_10: | |
1428 | return (version >= 3 && version <= 10); | |
1429 | case cris_ver_v8_10: | |
1430 | return (version >= 8 && version <= 10); | |
1431 | case cris_ver_v10: | |
1432 | return (version == 10); | |
29134980 OF |
1433 | case cris_ver_v10p: |
1434 | return (version >= 10); | |
c600d464 OF |
1435 | case cris_ver_v32p: |
1436 | return (version >= 32); | |
29134980 OF |
1437 | default: |
1438 | /* Invalid cris version. */ | |
1439 | return 0; | |
1440 | } | |
1441 | } | |
1442 | ||
1d94326f AC |
1443 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1444 | register, -1 for an invalid register. */ | |
1445 | ||
1446 | static int | |
1447 | cris_register_size (int regno) | |
1448 | { | |
c600d464 | 1449 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1450 | int i; |
1451 | int spec_regno; | |
1452 | ||
1453 | if (regno >= 0 && regno < NUM_GENREGS) | |
1454 | { | |
1455 | /* General registers (R0 - R15) are 32 bits. */ | |
1456 | return 4; | |
1457 | } | |
c600d464 | 1458 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1459 | { |
1460 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1461 | Adjust regno accordingly. */ | |
1462 | spec_regno = regno - NUM_GENREGS; | |
1463 | ||
c600d464 | 1464 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1465 | { |
1466 | if (cris_spec_regs[i].number == spec_regno | |
1467 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1468 | /* Go with the first applicable register. */ | |
1469 | return cris_spec_regs[i].reg_size; | |
1470 | } | |
1471 | /* Special register not applicable to this CRIS version. */ | |
1472 | return 0; | |
1473 | } | |
c600d464 | 1474 | else if (regno >= PC_REGNUM && regno < NUM_REGS) |
1d94326f | 1475 | { |
c600d464 OF |
1476 | /* This will apply to CRISv32 only where there are additional registers |
1477 | after the special registers (pseudo PC and support registers). */ | |
1478 | return 4; | |
1d94326f | 1479 | } |
c600d464 OF |
1480 | |
1481 | ||
1482 | return -1; | |
1d94326f AC |
1483 | } |
1484 | ||
29134980 OF |
1485 | /* Nonzero if regno should not be fetched from the target. This is the case |
1486 | for unimplemented (size 0) and non-existant registers. */ | |
1487 | ||
a78f21af | 1488 | static int |
29134980 OF |
1489 | cris_cannot_fetch_register (int regno) |
1490 | { | |
1491 | return ((regno < 0 || regno >= NUM_REGS) | |
1492 | || (cris_register_size (regno) == 0)); | |
1493 | } | |
1494 | ||
1495 | /* Nonzero if regno should not be written to the target, for various | |
1496 | reasons. */ | |
1497 | ||
a78f21af | 1498 | static int |
29134980 OF |
1499 | cris_cannot_store_register (int regno) |
1500 | { | |
1501 | /* There are three kinds of registers we refuse to write to. | |
1502 | 1. Those that not implemented. | |
1503 | 2. Those that are read-only (depends on the processor mode). | |
1504 | 3. Those registers to which a write has no effect. | |
1505 | */ | |
1506 | ||
1507 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1508 | /* Not implemented. */ | |
1509 | return 1; | |
1510 | ||
1511 | else if (regno == VR_REGNUM) | |
1512 | /* Read-only. */ | |
1513 | return 1; | |
1514 | ||
1515 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1516 | /* Writing has no effect. */ | |
1517 | return 1; | |
1518 | ||
a5f6c8f5 OF |
1519 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1520 | agent decide whether they are writable. */ | |
29134980 OF |
1521 | |
1522 | return 0; | |
1523 | } | |
1524 | ||
c600d464 OF |
1525 | /* Nonzero if regno should not be fetched from the target. This is the case |
1526 | for unimplemented (size 0) and non-existant registers. */ | |
1527 | ||
1528 | static int | |
1529 | crisv32_cannot_fetch_register (int regno) | |
1530 | { | |
1531 | return ((regno < 0 || regno >= NUM_REGS) | |
1532 | || (cris_register_size (regno) == 0)); | |
1533 | } | |
1534 | ||
1535 | /* Nonzero if regno should not be written to the target, for various | |
1536 | reasons. */ | |
1537 | ||
1538 | static int | |
1539 | crisv32_cannot_store_register (int regno) | |
1540 | { | |
1541 | /* There are three kinds of registers we refuse to write to. | |
1542 | 1. Those that not implemented. | |
1543 | 2. Those that are read-only (depends on the processor mode). | |
1544 | 3. Those registers to which a write has no effect. | |
1545 | */ | |
1546 | ||
1547 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1548 | /* Not implemented. */ | |
1549 | return 1; | |
1550 | ||
1551 | else if (regno == VR_REGNUM) | |
1552 | /* Read-only. */ | |
1553 | return 1; | |
1554 | ||
1555 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1556 | /* Writing has no effect. */ | |
1557 | return 1; | |
1558 | ||
1559 | /* Many special registers are read-only in user mode. Let the debug | |
1560 | agent decide whether they are writable. */ | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
29134980 OF |
1565 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1566 | of data in register regno. */ | |
1567 | ||
a78f21af | 1568 | static struct type * |
c1d546cd | 1569 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1570 | { |
a5f6c8f5 OF |
1571 | if (regno == PC_REGNUM) |
1572 | return builtin_type_void_func_ptr; | |
1573 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1574 | return builtin_type_void_data_ptr; | |
1575 | else if ((regno >= 0 && regno < SP_REGNUM) | |
1576 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) | |
1577 | /* Note: R8 taken care of previous clause. */ | |
1578 | return builtin_type_uint32; | |
1579 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1580 | return builtin_type_uint16; | |
1581 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1582 | return builtin_type_uint8; | |
29134980 | 1583 | else |
a5f6c8f5 OF |
1584 | /* Invalid (unimplemented) register. */ |
1585 | return builtin_type_int0; | |
29134980 OF |
1586 | } |
1587 | ||
c600d464 OF |
1588 | static struct type * |
1589 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1590 | { | |
1591 | if (regno == PC_REGNUM) | |
1592 | return builtin_type_void_func_ptr; | |
1593 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1594 | return builtin_type_void_data_ptr; | |
1595 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1596 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1597 | || (regno == PID_REGNUM) | |
1598 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1599 | /* Note: R8 and SP taken care of by previous clause. */ | |
1600 | return builtin_type_uint32; | |
1601 | else if (regno == WZ_REGNUM) | |
1602 | return builtin_type_uint16; | |
1603 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1604 | return builtin_type_uint8; | |
1605 | else | |
1606 | { | |
1607 | /* Invalid (unimplemented) register. Should not happen as there are | |
1608 | no unimplemented CRISv32 registers. */ | |
1609 | warning ("crisv32_register_type: unknown regno %d", regno); | |
1610 | return builtin_type_int0; | |
1611 | } | |
1612 | } | |
1613 | ||
2e4b5889 OF |
1614 | /* Stores a function return value of type type, where valbuf is the address |
1615 | of the value to be stored. */ | |
29134980 | 1616 | |
2e4b5889 | 1617 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1618 | |
2e4b5889 OF |
1619 | static void |
1620 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1621 | const void *valbuf) | |
29134980 | 1622 | { |
2e4b5889 OF |
1623 | ULONGEST val; |
1624 | int len = TYPE_LENGTH (type); | |
29134980 | 1625 | |
2e4b5889 | 1626 | if (len <= 4) |
29134980 | 1627 | { |
2e4b5889 OF |
1628 | /* Put the return value in R10. */ |
1629 | val = extract_unsigned_integer (valbuf, len); | |
1630 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1631 | } |
2e4b5889 | 1632 | else if (len <= 8) |
29134980 | 1633 | { |
2e4b5889 OF |
1634 | /* Put the return value in R10 and R11. */ |
1635 | val = extract_unsigned_integer (valbuf, 4); | |
1636 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1637 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1638 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1639 | } |
2e4b5889 OF |
1640 | else |
1641 | error ("cris_store_return_value: type length too large."); | |
29134980 OF |
1642 | } |
1643 | ||
2e4b5889 OF |
1644 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1645 | unimplemented register. */ | |
29134980 | 1646 | |
c600d464 OF |
1647 | static const char * |
1648 | cris_special_register_name (int regno) | |
1649 | { | |
1650 | int spec_regno; | |
1651 | int i; | |
1652 | ||
1653 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1654 | Adjust regno accordingly. */ | |
1655 | spec_regno = regno - NUM_GENREGS; | |
1656 | ||
1657 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1658 | when searching. */ | |
1659 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1660 | { | |
1661 | if (cris_spec_regs[i].number == spec_regno | |
1662 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1663 | /* Go with the first applicable register. */ | |
1664 | return cris_spec_regs[i].name; | |
1665 | } | |
1666 | /* Special register not applicable to this CRIS version. */ | |
1667 | return NULL; | |
1668 | } | |
1669 | ||
2e4b5889 OF |
1670 | static const char * |
1671 | cris_register_name (int regno) | |
1672 | { | |
1673 | static char *cris_genreg_names[] = | |
1674 | { "r0", "r1", "r2", "r3", \ | |
1675 | "r4", "r5", "r6", "r7", \ | |
1676 | "r8", "r9", "r10", "r11", \ | |
1677 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1678 | |
2e4b5889 | 1679 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1680 | { |
2e4b5889 OF |
1681 | /* General register. */ |
1682 | return cris_genreg_names[regno]; | |
29134980 | 1683 | } |
2e4b5889 | 1684 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
29134980 | 1685 | { |
c600d464 OF |
1686 | return cris_special_register_name (regno); |
1687 | } | |
1688 | else | |
1689 | { | |
1690 | /* Invalid register. */ | |
2e4b5889 OF |
1691 | return NULL; |
1692 | } | |
c600d464 OF |
1693 | } |
1694 | ||
1695 | static const char * | |
1696 | crisv32_register_name (int regno) | |
1697 | { | |
1698 | static char *crisv32_genreg_names[] = | |
1699 | { "r0", "r1", "r2", "r3", \ | |
1700 | "r4", "r5", "r6", "r7", \ | |
1701 | "r8", "r9", "r10", "r11", \ | |
1702 | "r12", "r13", "sp", "acr" | |
1703 | }; | |
1704 | ||
1705 | static char *crisv32_sreg_names[] = | |
1706 | { "s0", "s1", "s2", "s3", \ | |
1707 | "s4", "s5", "s6", "s7", \ | |
1708 | "s8", "s9", "s10", "s11", \ | |
1709 | "s12", "s13", "s14", "s15" | |
1710 | }; | |
1711 | ||
1712 | if (regno >= 0 && regno < NUM_GENREGS) | |
1713 | { | |
1714 | /* General register. */ | |
1715 | return crisv32_genreg_names[regno]; | |
1716 | } | |
1717 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1718 | { | |
1719 | return cris_special_register_name (regno); | |
1720 | } | |
1721 | else if (regno == PC_REGNUM) | |
1722 | { | |
1723 | return "pc"; | |
1724 | } | |
1725 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1726 | { | |
1727 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1728 | } | |
2e4b5889 OF |
1729 | else |
1730 | { | |
1731 | /* Invalid register. */ | |
1732 | return NULL; | |
29134980 | 1733 | } |
29134980 OF |
1734 | } |
1735 | ||
a5f6c8f5 OF |
1736 | /* Convert DWARF register number REG to the appropriate register |
1737 | number used by GDB. */ | |
1738 | ||
2e4b5889 | 1739 | static int |
a5f6c8f5 | 1740 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1741 | { |
a5f6c8f5 OF |
1742 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1743 | numbering, MOF is 18). | |
1744 | Adapted from gcc/config/cris/cris.h. */ | |
1745 | static int cris_dwarf_regmap[] = { | |
1746 | 0, 1, 2, 3, | |
1747 | 4, 5, 6, 7, | |
1748 | 8, 9, 10, 11, | |
1749 | 12, 13, 14, 15, | |
1750 | 27, -1, -1, -1, | |
1751 | -1, -1, -1, 23, | |
1752 | -1, -1, -1, 27, | |
1753 | -1, -1, -1, -1 | |
1754 | }; | |
1755 | int regnum = -1; | |
1756 | ||
1757 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1758 | regnum = cris_dwarf_regmap[reg]; | |
1759 | ||
1760 | if (regnum == -1) | |
1761 | warning ("Unmapped DWARF Register #%d encountered\n", reg); | |
1762 | ||
1763 | return regnum; | |
1764 | } | |
1765 | ||
1766 | /* DWARF-2 frame support. */ | |
1767 | ||
1768 | static void | |
1769 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1770 | struct dwarf2_frame_state_reg *reg) | |
1771 | { | |
1772 | /* The return address column. */ | |
1773 | if (regnum == PC_REGNUM) | |
1774 | reg->how = DWARF2_FRAME_REG_RA; | |
1775 | ||
1776 | /* The call frame address. */ | |
1777 | else if (regnum == SP_REGNUM) | |
1778 | reg->how = DWARF2_FRAME_REG_CFA; | |
29134980 OF |
1779 | } |
1780 | ||
2e4b5889 OF |
1781 | /* Extract from an array regbuf containing the raw register state a function |
1782 | return value of type type, and copy that, in virtual format, into | |
1783 | valbuf. */ | |
1784 | ||
1785 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1786 | |
2e4b5889 OF |
1787 | static void |
1788 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1789 | void *valbuf) | |
29134980 | 1790 | { |
2e4b5889 OF |
1791 | ULONGEST val; |
1792 | int len = TYPE_LENGTH (type); | |
29134980 | 1793 | |
2e4b5889 | 1794 | if (len <= 4) |
29134980 | 1795 | { |
2e4b5889 OF |
1796 | /* Get the return value from R10. */ |
1797 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1798 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1799 | } |
2e4b5889 | 1800 | else if (len <= 8) |
29134980 | 1801 | { |
2e4b5889 OF |
1802 | /* Get the return value from R10 and R11. */ |
1803 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1804 | store_unsigned_integer (valbuf, 4, val); | |
1805 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1806 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1807 | } |
2e4b5889 OF |
1808 | else |
1809 | error ("cris_extract_return_value: type length too large"); | |
1810 | } | |
1811 | ||
b4206d25 OF |
1812 | /* Handle the CRIS return value convention. */ |
1813 | ||
1814 | static enum return_value_convention | |
1815 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
1816 | struct regcache *regcache, void *readbuf, | |
1817 | const void *writebuf) | |
1818 | { | |
1819 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1820 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1821 | || TYPE_LENGTH (type) > 8) | |
1822 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1823 | goes on the stack. */ | |
1824 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1825 | ||
1826 | if (readbuf) | |
1827 | cris_extract_return_value (type, regcache, readbuf); | |
1828 | if (writebuf) | |
1829 | cris_store_return_value (type, regcache, writebuf); | |
1830 | ||
1831 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1832 | } | |
1833 | ||
2e4b5889 OF |
1834 | /* Returns 1 if the given type will be passed by pointer rather than |
1835 | directly. */ | |
1836 | ||
1837 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1838 | by value. */ | |
1839 | ||
1840 | static int | |
1841 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1842 | { | |
1843 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1844 | } |
1845 | ||
1846 | /* Calculates a value that measures how good inst_args constraints an | |
1847 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1848 | ||
1849 | static int | |
1850 | constraint (unsigned int insn, const signed char *inst_args, | |
1851 | inst_env_type *inst_env) | |
1852 | { | |
1853 | int retval = 0; | |
1854 | int tmp, i; | |
1855 | ||
1856 | const char *s = inst_args; | |
1857 | ||
1858 | for (; *s; s++) | |
1859 | switch (*s) | |
1860 | { | |
1861 | case 'm': | |
1862 | if ((insn & 0x30) == 0x30) | |
1863 | return -1; | |
1864 | break; | |
1865 | ||
1866 | case 'S': | |
1867 | /* A prefix operand. */ | |
1868 | if (inst_env->prefix_found) | |
1869 | break; | |
1870 | else | |
1871 | return -1; | |
1872 | ||
1873 | case 'B': | |
1874 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1875 | valid "push" size. In case of special register, it may be != 4. */ | |
1876 | if (inst_env->prefix_found) | |
1877 | break; | |
1878 | else | |
1879 | return -1; | |
1880 | ||
1881 | case 'D': | |
1882 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1883 | if (!retval) | |
1884 | return -1; | |
1885 | else | |
1886 | retval += 4; | |
1887 | break; | |
1888 | ||
1889 | case 'P': | |
1890 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1891 | |
1892 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1893 | { | |
1894 | /* Since we match four bits, we will give a value of | |
1895 | 4 - 1 = 3 in a match. If there is a corresponding | |
1896 | exact match of a special register in another pattern, it | |
1897 | will get a value of 4, which will be higher. This should | |
1898 | be correct in that an exact pattern would match better that | |
1899 | a general pattern. | |
1900 | Note that there is a reason for not returning zero; the | |
1901 | pattern for "clear" is partly matched in the bit-pattern | |
1902 | (the two lower bits must be zero), while the bit-pattern | |
1903 | for a move from a special register is matched in the | |
1904 | register constraint. | |
1905 | This also means we will will have a race condition if | |
1906 | there is a partly match in three bits in the bit pattern. */ | |
1907 | if (tmp == cris_spec_regs[i].number) | |
1908 | { | |
1909 | retval += 3; | |
1910 | break; | |
1911 | } | |
1912 | } | |
1913 | ||
1914 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1915 | return -1; |
1916 | break; | |
1917 | } | |
1918 | return retval; | |
1919 | } | |
1920 | ||
1921 | /* Returns the number of bits set in the variable value. */ | |
1922 | ||
1923 | static int | |
1924 | number_of_bits (unsigned int value) | |
1925 | { | |
1926 | int number_of_bits = 0; | |
1927 | ||
1928 | while (value != 0) | |
1929 | { | |
1930 | number_of_bits += 1; | |
1931 | value &= (value - 1); | |
1932 | } | |
1933 | return number_of_bits; | |
1934 | } | |
1935 | ||
1936 | /* Finds the address that should contain the single step breakpoint(s). | |
1937 | It stems from code in cris-dis.c. */ | |
1938 | ||
1939 | static int | |
1940 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1941 | { | |
1942 | int i; | |
1943 | int max_level_of_match = -1; | |
1944 | int max_matched = -1; | |
1945 | int level_of_match; | |
1946 | ||
1947 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1948 | { | |
1949 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
1950 | && ((cris_opcodes[i].lose & insn) == 0) |
1951 | /* Only CRISv10 instructions, please. */ | |
1952 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
1953 | { |
1954 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1955 | if (level_of_match >= 0) | |
1956 | { | |
1957 | level_of_match += | |
1958 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1959 | if (level_of_match > max_level_of_match) | |
1960 | { | |
1961 | max_matched = i; | |
1962 | max_level_of_match = level_of_match; | |
1963 | if (level_of_match == 16) | |
1964 | { | |
1965 | /* All bits matched, cannot find better. */ | |
1966 | break; | |
1967 | } | |
1968 | } | |
1969 | } | |
1970 | } | |
1971 | } | |
1972 | return max_matched; | |
1973 | } | |
1974 | ||
1975 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1976 | actually an internal error. */ | |
1977 | ||
1978 | static int | |
1979 | find_step_target (inst_env_type *inst_env) | |
1980 | { | |
1981 | int i; | |
1982 | int offset; | |
1983 | unsigned short insn; | |
1984 | ||
1985 | /* Create a local register image and set the initial state. */ | |
1986 | for (i = 0; i < NUM_GENREGS; i++) | |
1987 | { | |
1988 | inst_env->reg[i] = (unsigned long) read_register (i); | |
1989 | } | |
1990 | offset = NUM_GENREGS; | |
1991 | for (i = 0; i < NUM_SPECREGS; i++) | |
1992 | { | |
1993 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
1994 | } | |
1995 | inst_env->branch_found = 0; | |
1996 | inst_env->slot_needed = 0; | |
1997 | inst_env->delay_slot_pc_active = 0; | |
1998 | inst_env->prefix_found = 0; | |
1999 | inst_env->invalid = 0; | |
2000 | inst_env->xflag_found = 0; | |
2001 | inst_env->disable_interrupt = 0; | |
2002 | ||
2003 | /* Look for a step target. */ | |
2004 | do | |
2005 | { | |
2006 | /* Read an instruction from the client. */ | |
2007 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
2008 | ||
2009 | /* If the instruction is not in a delay slot the new content of the | |
2010 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2011 | that simple. Since a instruction in a delay slot cannot change | |
2012 | the content of the PC, it does not matter what value PC will have. | |
2013 | Just make sure it is a valid instruction. */ | |
2014 | if (!inst_env->delay_slot_pc_active) | |
2015 | { | |
2016 | inst_env->reg[PC_REGNUM] += 2; | |
2017 | } | |
2018 | else | |
2019 | { | |
2020 | inst_env->delay_slot_pc_active = 0; | |
2021 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
2022 | } | |
2023 | /* Analyse the present instruction. */ | |
2024 | i = find_cris_op (insn, inst_env); | |
2025 | if (i == -1) | |
2026 | { | |
2027 | inst_env->invalid = 1; | |
2028 | } | |
2029 | else | |
2030 | { | |
2031 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2032 | } | |
2033 | } while (!inst_env->invalid | |
2034 | && (inst_env->prefix_found || inst_env->xflag_found | |
2035 | || inst_env->slot_needed)); | |
2036 | return i; | |
2037 | } | |
2038 | ||
2039 | /* There is no hardware single-step support. The function find_step_target | |
2040 | digs through the opcodes in order to find all possible targets. | |
2041 | Either one ordinary target or two targets for branches may be found. */ | |
2042 | ||
a78f21af | 2043 | static void |
29134980 OF |
2044 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) |
2045 | { | |
2046 | inst_env_type inst_env; | |
2047 | ||
2048 | if (insert_breakpoints) | |
2049 | { | |
2050 | /* Analyse the present instruction environment and insert | |
2051 | breakpoints. */ | |
2052 | int status = find_step_target (&inst_env); | |
2053 | if (status == -1) | |
2054 | { | |
c600d464 OF |
2055 | /* Could not find a target. Things are likely to go downhill |
2056 | from here. */ | |
2057 | warning ("CRIS software single step could not find a step target."); | |
29134980 OF |
2058 | } |
2059 | else | |
2060 | { | |
2061 | /* Insert at most two breakpoints. One for the next PC content | |
2062 | and possibly another one for a branch, jump, etc. */ | |
2063 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
2064 | target_insert_breakpoint (next_pc, break_mem[0]); | |
2065 | if (inst_env.branch_found | |
2066 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2067 | { | |
2068 | branch_target_address = | |
2069 | (CORE_ADDR) inst_env.branch_break_address; | |
2070 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
2071 | branch_break_inserted = 1; | |
2072 | } | |
2073 | } | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | /* Remove breakpoints. */ | |
2078 | target_remove_breakpoint (next_pc, break_mem[0]); | |
2079 | if (branch_break_inserted) | |
2080 | { | |
2081 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
2082 | branch_break_inserted = 0; | |
2083 | } | |
2084 | } | |
2085 | } | |
2086 | ||
2087 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2088 | ||
a78f21af | 2089 | static void |
29134980 OF |
2090 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2091 | { | |
2092 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2093 | instruction (not 100% sure). */ | |
2094 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2095 | { | |
2096 | inst_env->invalid = 1; | |
2097 | return; | |
2098 | } | |
2099 | ||
2100 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2101 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2102 | ||
2103 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2104 | need updating. */ | |
2105 | inst_env->slot_needed = 0; | |
2106 | inst_env->prefix_found = 1; | |
2107 | } | |
2108 | ||
2109 | /* Updates the autoincrement register. The size of the increment is derived | |
2110 | from the size of the operation. The PC is always kept aligned on even | |
2111 | word addresses. */ | |
2112 | ||
a78f21af | 2113 | static void |
29134980 OF |
2114 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2115 | { | |
2116 | if (size == INST_BYTE_SIZE) | |
2117 | { | |
2118 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2119 | ||
2120 | /* The PC must be word aligned, so increase the PC with one | |
2121 | word even if the size is byte. */ | |
2122 | if (cris_get_operand1 (inst) == REG_PC) | |
2123 | { | |
2124 | inst_env->reg[REG_PC] += 1; | |
2125 | } | |
2126 | } | |
2127 | else if (size == INST_WORD_SIZE) | |
2128 | { | |
2129 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2130 | } | |
2131 | else if (size == INST_DWORD_SIZE) | |
2132 | { | |
2133 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2134 | } | |
2135 | else | |
2136 | { | |
2137 | /* Invalid size. */ | |
2138 | inst_env->invalid = 1; | |
2139 | } | |
2140 | } | |
2141 | ||
2a9ecef2 OF |
2142 | /* Just a forward declaration. */ |
2143 | ||
a78f21af AC |
2144 | static unsigned long get_data_from_address (unsigned short *inst, |
2145 | CORE_ADDR address); | |
2a9ecef2 | 2146 | |
29134980 OF |
2147 | /* Calculates the prefix value for the general case of offset addressing |
2148 | mode. */ | |
2149 | ||
a78f21af | 2150 | static void |
29134980 OF |
2151 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2152 | { | |
2153 | ||
2154 | long offset; | |
2155 | ||
2156 | /* It's invalid to be in a delay slot. */ | |
2157 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2158 | { | |
2159 | inst_env->invalid = 1; | |
2160 | return; | |
2161 | } | |
2162 | ||
fa4e4598 OF |
2163 | /* The calculation of prefix_value used to be after process_autoincrement, |
2164 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2165 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2166 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2167 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2168 | ||
2169 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2170 | inst_env->prefix_value += | |
2a9ecef2 OF |
2171 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2172 | ||
fa4e4598 OF |
2173 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2174 | { | |
2175 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2176 | } | |
2177 | ||
29134980 OF |
2178 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2179 | need updating. */ | |
2180 | inst_env->slot_needed = 0; | |
2181 | inst_env->prefix_found = 1; | |
2182 | } | |
2183 | ||
2184 | /* Calculates the prefix value for the index addressing mode. */ | |
2185 | ||
a78f21af | 2186 | static void |
29134980 OF |
2187 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2188 | { | |
2189 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2190 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2191 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2192 | { | |
2193 | inst_env->invalid = 1; | |
2194 | return; | |
2195 | } | |
2196 | ||
2197 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2198 | ||
2199 | /* The offset is the operand2 value shifted the size of the instruction | |
2200 | to the left. */ | |
2201 | inst_env->prefix_value += | |
2202 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2203 | ||
2204 | /* If the PC is operand1 (base) the address used is the address after | |
2205 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2206 | for the prefix operation). */ | |
2207 | if (cris_get_operand1 (inst) == REG_PC) | |
2208 | { | |
2209 | inst_env->prefix_value += 2; | |
2210 | } | |
2211 | ||
2212 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2213 | need updating. */ | |
2214 | inst_env->slot_needed = 0; | |
2215 | inst_env->xflag_found = 0; | |
2216 | inst_env->prefix_found = 1; | |
2217 | } | |
2218 | ||
2219 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2220 | ||
a78f21af | 2221 | static void |
29134980 OF |
2222 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2223 | { | |
2224 | ||
2225 | CORE_ADDR address; | |
2226 | ||
2227 | /* It's invalid to be in a delay slot. */ | |
2228 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2229 | { | |
2230 | inst_env->invalid = 1; | |
2231 | return; | |
2232 | } | |
2233 | ||
2234 | /* The prefix value is one dereference of the contents of the operand1 | |
2235 | register. */ | |
2236 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2237 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2238 | ||
2239 | /* Check if the mode is autoincrement. */ | |
2240 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2241 | { | |
2242 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2243 | } | |
2244 | ||
2245 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2246 | need updating. */ | |
2247 | inst_env->slot_needed = 0; | |
2248 | inst_env->xflag_found = 0; | |
2249 | inst_env->prefix_found = 1; | |
2250 | } | |
2251 | ||
2252 | /* Finds the destination for a branch with 8-bits offset. */ | |
2253 | ||
a78f21af | 2254 | static void |
29134980 OF |
2255 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2256 | { | |
2257 | ||
2258 | short offset; | |
2259 | ||
2260 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2261 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2262 | { | |
2263 | inst_env->invalid = 1; | |
2264 | return; | |
2265 | } | |
2266 | ||
2267 | /* We have a branch, find out where the branch will land. */ | |
2268 | offset = cris_get_branch_short_offset (inst); | |
2269 | ||
2270 | /* Check if the offset is signed. */ | |
2271 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2272 | { | |
2273 | offset |= 0xFF00; | |
2274 | } | |
2275 | ||
2276 | /* The offset ends with the sign bit, set it to zero. The address | |
2277 | should always be word aligned. */ | |
2278 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2279 | ||
2280 | inst_env->branch_found = 1; | |
2281 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2282 | ||
2283 | inst_env->slot_needed = 1; | |
2284 | inst_env->prefix_found = 0; | |
2285 | inst_env->xflag_found = 0; | |
2286 | inst_env->disable_interrupt = 1; | |
2287 | } | |
2288 | ||
2289 | /* Finds the destination for a branch with 16-bits offset. */ | |
2290 | ||
a78f21af | 2291 | static void |
29134980 OF |
2292 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2293 | { | |
2294 | short offset; | |
2295 | ||
2296 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2297 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2298 | { | |
2299 | inst_env->invalid = 1; | |
2300 | return; | |
2301 | } | |
2302 | ||
2303 | /* We have a branch, find out the offset for the branch. */ | |
2304 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2305 | ||
2306 | /* The instruction is one word longer than normal, so add one word | |
2307 | to the PC. */ | |
2308 | inst_env->reg[REG_PC] += 2; | |
2309 | ||
2310 | inst_env->branch_found = 1; | |
2311 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2312 | ||
2313 | ||
2314 | inst_env->slot_needed = 1; | |
2315 | inst_env->prefix_found = 0; | |
2316 | inst_env->xflag_found = 0; | |
2317 | inst_env->disable_interrupt = 1; | |
2318 | } | |
2319 | ||
2320 | /* Handles the ABS instruction. */ | |
2321 | ||
a78f21af | 2322 | static void |
29134980 OF |
2323 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2324 | { | |
2325 | ||
2326 | long value; | |
2327 | ||
2328 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2329 | if (inst_env->prefix_found) | |
2330 | { | |
2331 | inst_env->invalid = 1; | |
2332 | return; | |
2333 | } | |
2334 | ||
2335 | /* Check if the operation affects the PC. */ | |
2336 | if (cris_get_operand2 (inst) == REG_PC) | |
2337 | { | |
2338 | ||
2339 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2340 | if (inst_env->slot_needed) | |
2341 | { | |
2342 | inst_env->invalid = 1; | |
2343 | return; | |
2344 | } | |
2345 | ||
2346 | value = (long) inst_env->reg[REG_PC]; | |
2347 | ||
2348 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2349 | if (value != SIGNED_DWORD_MASK) | |
2350 | { | |
2351 | value = -value; | |
2352 | inst_env->reg[REG_PC] = (long) value; | |
2353 | } | |
2354 | } | |
2355 | ||
2356 | inst_env->slot_needed = 0; | |
2357 | inst_env->prefix_found = 0; | |
2358 | inst_env->xflag_found = 0; | |
2359 | inst_env->disable_interrupt = 0; | |
2360 | } | |
2361 | ||
2362 | /* Handles the ADDI instruction. */ | |
2363 | ||
a78f21af | 2364 | static void |
29134980 OF |
2365 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2366 | { | |
2367 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2368 | a prefix. */ | |
2369 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2370 | { | |
2371 | inst_env->invalid = 1; | |
2372 | return; | |
2373 | } | |
2374 | ||
2375 | inst_env->slot_needed = 0; | |
2376 | inst_env->prefix_found = 0; | |
2377 | inst_env->xflag_found = 0; | |
2378 | inst_env->disable_interrupt = 0; | |
2379 | } | |
2380 | ||
2381 | /* Handles the ASR instruction. */ | |
2382 | ||
a78f21af | 2383 | static void |
29134980 OF |
2384 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2385 | { | |
2386 | int shift_steps; | |
2387 | unsigned long value; | |
2388 | unsigned long signed_extend_mask = 0; | |
2389 | ||
2390 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2391 | if (inst_env->prefix_found) | |
2392 | { | |
2393 | inst_env->invalid = 1; | |
2394 | return; | |
2395 | } | |
2396 | ||
2397 | /* Check if the PC is the target register. */ | |
2398 | if (cris_get_operand2 (inst) == REG_PC) | |
2399 | { | |
2400 | /* It's invalid to change the PC in a delay slot. */ | |
2401 | if (inst_env->slot_needed) | |
2402 | { | |
2403 | inst_env->invalid = 1; | |
2404 | return; | |
2405 | } | |
2406 | /* Get the number of bits to shift. */ | |
2407 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2408 | value = inst_env->reg[REG_PC]; | |
2409 | ||
2410 | /* Find out how many bits the operation should apply to. */ | |
2411 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2412 | { | |
2413 | if (value & SIGNED_BYTE_MASK) | |
2414 | { | |
2415 | signed_extend_mask = 0xFF; | |
2416 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2417 | signed_extend_mask = ~signed_extend_mask; | |
2418 | } | |
2419 | value = value >> shift_steps; | |
2420 | value |= signed_extend_mask; | |
2421 | value &= 0xFF; | |
2422 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2423 | inst_env->reg[REG_PC] |= value; | |
2424 | } | |
2425 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2426 | { | |
2427 | if (value & SIGNED_WORD_MASK) | |
2428 | { | |
2429 | signed_extend_mask = 0xFFFF; | |
2430 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2431 | signed_extend_mask = ~signed_extend_mask; | |
2432 | } | |
2433 | value = value >> shift_steps; | |
2434 | value |= signed_extend_mask; | |
2435 | value &= 0xFFFF; | |
2436 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2437 | inst_env->reg[REG_PC] |= value; | |
2438 | } | |
2439 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2440 | { | |
2441 | if (value & SIGNED_DWORD_MASK) | |
2442 | { | |
2443 | signed_extend_mask = 0xFFFFFFFF; | |
2444 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2445 | signed_extend_mask = ~signed_extend_mask; | |
2446 | } | |
2447 | value = value >> shift_steps; | |
2448 | value |= signed_extend_mask; | |
2449 | inst_env->reg[REG_PC] = value; | |
2450 | } | |
2451 | } | |
2452 | inst_env->slot_needed = 0; | |
2453 | inst_env->prefix_found = 0; | |
2454 | inst_env->xflag_found = 0; | |
2455 | inst_env->disable_interrupt = 0; | |
2456 | } | |
2457 | ||
2458 | /* Handles the ASRQ instruction. */ | |
2459 | ||
a78f21af | 2460 | static void |
29134980 OF |
2461 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2462 | { | |
2463 | ||
2464 | int shift_steps; | |
2465 | unsigned long value; | |
2466 | unsigned long signed_extend_mask = 0; | |
2467 | ||
2468 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2469 | if (inst_env->prefix_found) | |
2470 | { | |
2471 | inst_env->invalid = 1; | |
2472 | return; | |
2473 | } | |
2474 | ||
2475 | /* Check if the PC is the target register. */ | |
2476 | if (cris_get_operand2 (inst) == REG_PC) | |
2477 | { | |
2478 | ||
2479 | /* It's invalid to change the PC in a delay slot. */ | |
2480 | if (inst_env->slot_needed) | |
2481 | { | |
2482 | inst_env->invalid = 1; | |
2483 | return; | |
2484 | } | |
2485 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2486 | want the the sign bit of the quick value. */ | |
2487 | shift_steps = cris_get_asr_shift_steps (inst); | |
2488 | value = inst_env->reg[REG_PC]; | |
2489 | if (value & SIGNED_DWORD_MASK) | |
2490 | { | |
2491 | signed_extend_mask = 0xFFFFFFFF; | |
2492 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2493 | signed_extend_mask = ~signed_extend_mask; | |
2494 | } | |
2495 | value = value >> shift_steps; | |
2496 | value |= signed_extend_mask; | |
2497 | inst_env->reg[REG_PC] = value; | |
2498 | } | |
2499 | inst_env->slot_needed = 0; | |
2500 | inst_env->prefix_found = 0; | |
2501 | inst_env->xflag_found = 0; | |
2502 | inst_env->disable_interrupt = 0; | |
2503 | } | |
2504 | ||
2505 | /* Handles the AX, EI and SETF instruction. */ | |
2506 | ||
a78f21af | 2507 | static void |
29134980 OF |
2508 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2509 | { | |
2510 | if (inst_env->prefix_found) | |
2511 | { | |
2512 | inst_env->invalid = 1; | |
2513 | return; | |
2514 | } | |
2515 | /* Check if the instruction is setting the X flag. */ | |
2516 | if (cris_is_xflag_bit_on (inst)) | |
2517 | { | |
2518 | inst_env->xflag_found = 1; | |
2519 | } | |
2520 | else | |
2521 | { | |
2522 | inst_env->xflag_found = 0; | |
2523 | } | |
2524 | inst_env->slot_needed = 0; | |
2525 | inst_env->prefix_found = 0; | |
2526 | inst_env->disable_interrupt = 1; | |
2527 | } | |
2528 | ||
2529 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2530 | register. Note that check_assign assumes that the caller has checked that | |
2531 | there is a prefix to this instruction. The mode check depends on this. */ | |
2532 | ||
a78f21af | 2533 | static void |
29134980 OF |
2534 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2535 | { | |
2536 | /* Check if it's an assign addressing mode. */ | |
2537 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2538 | { | |
2539 | /* Assign the prefix value to operand 1. */ | |
2540 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2541 | } | |
2542 | } | |
2543 | ||
2544 | /* Handles the 2-operand BOUND instruction. */ | |
2545 | ||
a78f21af | 2546 | static void |
29134980 OF |
2547 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2548 | { | |
2549 | /* It's invalid to have the PC as the index operand. */ | |
2550 | if (cris_get_operand2 (inst) == REG_PC) | |
2551 | { | |
2552 | inst_env->invalid = 1; | |
2553 | return; | |
2554 | } | |
2555 | /* Check if we have a prefix. */ | |
2556 | if (inst_env->prefix_found) | |
2557 | { | |
2558 | check_assign (inst, inst_env); | |
2559 | } | |
2560 | /* Check if this is an autoincrement mode. */ | |
2561 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2562 | { | |
2563 | /* It's invalid to change the PC in a delay slot. */ | |
2564 | if (inst_env->slot_needed) | |
2565 | { | |
2566 | inst_env->invalid = 1; | |
2567 | return; | |
2568 | } | |
2569 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2570 | } | |
2571 | inst_env->slot_needed = 0; | |
2572 | inst_env->prefix_found = 0; | |
2573 | inst_env->xflag_found = 0; | |
2574 | inst_env->disable_interrupt = 0; | |
2575 | } | |
2576 | ||
2577 | /* Handles the 3-operand BOUND instruction. */ | |
2578 | ||
a78f21af | 2579 | static void |
29134980 OF |
2580 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2581 | { | |
2582 | /* It's an error if we haven't got a prefix. And it's also an error | |
2583 | if the PC is the destination register. */ | |
2584 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2585 | { | |
2586 | inst_env->invalid = 1; | |
2587 | return; | |
2588 | } | |
2589 | inst_env->slot_needed = 0; | |
2590 | inst_env->prefix_found = 0; | |
2591 | inst_env->xflag_found = 0; | |
2592 | inst_env->disable_interrupt = 0; | |
2593 | } | |
2594 | ||
2595 | /* Clears the status flags in inst_env. */ | |
2596 | ||
a78f21af | 2597 | static void |
29134980 OF |
2598 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2599 | { | |
2600 | /* It's an error if we have got a prefix. */ | |
2601 | if (inst_env->prefix_found) | |
2602 | { | |
2603 | inst_env->invalid = 1; | |
2604 | return; | |
2605 | } | |
2606 | ||
2607 | inst_env->slot_needed = 0; | |
2608 | inst_env->prefix_found = 0; | |
2609 | inst_env->xflag_found = 0; | |
2610 | inst_env->disable_interrupt = 0; | |
2611 | } | |
2612 | ||
2613 | /* Clears the status flags in inst_env. */ | |
2614 | ||
a78f21af | 2615 | static void |
29134980 OF |
2616 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2617 | { | |
2618 | /* It's an error if we have got a prefix. */ | |
2619 | if (inst_env->prefix_found) | |
2620 | { | |
2621 | inst_env->invalid = 1; | |
2622 | return; | |
2623 | } | |
2624 | ||
2625 | inst_env->slot_needed = 0; | |
2626 | inst_env->prefix_found = 0; | |
2627 | inst_env->xflag_found = 0; | |
2628 | inst_env->disable_interrupt = 1; | |
2629 | } | |
2630 | ||
2631 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2632 | ||
a78f21af | 2633 | static void |
29134980 OF |
2634 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2635 | { | |
2636 | /* Check if the target is the PC. */ | |
2637 | if (cris_get_operand2 (inst) == REG_PC) | |
2638 | { | |
2639 | /* The instruction will clear the instruction's size bits. */ | |
2640 | int clear_size = cris_get_clear_size (inst); | |
2641 | if (clear_size == INST_BYTE_SIZE) | |
2642 | { | |
2643 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2644 | } | |
2645 | if (clear_size == INST_WORD_SIZE) | |
2646 | { | |
2647 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2648 | } | |
2649 | if (clear_size == INST_DWORD_SIZE) | |
2650 | { | |
2651 | inst_env->delay_slot_pc = 0x0; | |
2652 | } | |
2653 | /* The jump will be delayed with one delay slot. So we need a delay | |
2654 | slot. */ | |
2655 | inst_env->slot_needed = 1; | |
2656 | inst_env->delay_slot_pc_active = 1; | |
2657 | } | |
2658 | else | |
2659 | { | |
2660 | /* The PC will not change => no delay slot. */ | |
2661 | inst_env->slot_needed = 0; | |
2662 | } | |
2663 | inst_env->prefix_found = 0; | |
2664 | inst_env->xflag_found = 0; | |
2665 | inst_env->disable_interrupt = 0; | |
2666 | } | |
2667 | ||
2668 | /* Handles the TEST instruction if it's in register mode. */ | |
2669 | ||
a78f21af | 2670 | static void |
29134980 OF |
2671 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2672 | { | |
2673 | /* It's an error if we have got a prefix. */ | |
2674 | if (inst_env->prefix_found) | |
2675 | { | |
2676 | inst_env->invalid = 1; | |
2677 | return; | |
2678 | } | |
2679 | inst_env->slot_needed = 0; | |
2680 | inst_env->prefix_found = 0; | |
2681 | inst_env->xflag_found = 0; | |
2682 | inst_env->disable_interrupt = 0; | |
2683 | ||
2684 | } | |
2685 | ||
2686 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2687 | in register mode. */ | |
2688 | ||
a78f21af | 2689 | static void |
29134980 OF |
2690 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2691 | { | |
2692 | /* Check if we are in a prefix mode. */ | |
2693 | if (inst_env->prefix_found) | |
2694 | { | |
2695 | /* The only way the PC can change is if this instruction is in | |
2696 | assign addressing mode. */ | |
2697 | check_assign (inst, inst_env); | |
2698 | } | |
2699 | /* Indirect mode can't change the PC so just check if the mode is | |
2700 | autoincrement. */ | |
2701 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2702 | { | |
2703 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2704 | } | |
2705 | inst_env->slot_needed = 0; | |
2706 | inst_env->prefix_found = 0; | |
2707 | inst_env->xflag_found = 0; | |
2708 | inst_env->disable_interrupt = 0; | |
2709 | } | |
2710 | ||
2711 | /* Checks that the PC isn't the destination register or the instructions has | |
2712 | a prefix. */ | |
2713 | ||
a78f21af | 2714 | static void |
29134980 OF |
2715 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2716 | { | |
2717 | /* It's invalid to have the PC as the destination. The instruction can't | |
2718 | have a prefix. */ | |
2719 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2720 | { | |
2721 | inst_env->invalid = 1; | |
2722 | return; | |
2723 | } | |
2724 | ||
2725 | inst_env->slot_needed = 0; | |
2726 | inst_env->prefix_found = 0; | |
2727 | inst_env->xflag_found = 0; | |
2728 | inst_env->disable_interrupt = 0; | |
2729 | } | |
2730 | ||
2731 | /* Checks that the instruction doesn't have a prefix. */ | |
2732 | ||
a78f21af | 2733 | static void |
29134980 OF |
2734 | break_op (unsigned short inst, inst_env_type *inst_env) |
2735 | { | |
2736 | /* The instruction can't have a prefix. */ | |
2737 | if (inst_env->prefix_found) | |
2738 | { | |
2739 | inst_env->invalid = 1; | |
2740 | return; | |
2741 | } | |
2742 | ||
2743 | inst_env->slot_needed = 0; | |
2744 | inst_env->prefix_found = 0; | |
2745 | inst_env->xflag_found = 0; | |
2746 | inst_env->disable_interrupt = 1; | |
2747 | } | |
2748 | ||
2749 | /* Checks that the PC isn't the destination register and that the instruction | |
2750 | doesn't have a prefix. */ | |
2751 | ||
a78f21af | 2752 | static void |
29134980 OF |
2753 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2754 | { | |
2755 | /* It's invalid to have the PC as the destination. The instruction can't | |
2756 | have a prefix. */ | |
2757 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2758 | { | |
2759 | inst_env->invalid = 1; | |
2760 | return; | |
2761 | } | |
2762 | ||
2763 | inst_env->slot_needed = 0; | |
2764 | inst_env->prefix_found = 0; | |
2765 | inst_env->xflag_found = 0; | |
2766 | inst_env->disable_interrupt = 1; | |
2767 | } | |
2768 | ||
2769 | /* Handles the register mode JUMP instruction. */ | |
2770 | ||
a78f21af | 2771 | static void |
29134980 OF |
2772 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2773 | { | |
2774 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2775 | you can't have a prefix. */ | |
2776 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2777 | { | |
2778 | inst_env->invalid = 1; | |
2779 | return; | |
2780 | } | |
2781 | ||
2782 | /* Just change the PC. */ | |
2783 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2784 | inst_env->slot_needed = 0; | |
2785 | inst_env->prefix_found = 0; | |
2786 | inst_env->xflag_found = 0; | |
2787 | inst_env->disable_interrupt = 1; | |
2788 | } | |
2789 | ||
2790 | /* Handles the JUMP instruction for all modes except register. */ | |
2791 | ||
a78f21af AC |
2792 | static void |
2793 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2794 | { |
2795 | unsigned long newpc; | |
2796 | CORE_ADDR address; | |
2797 | ||
2798 | /* It's invalid to do a JUMP in a delay slot. */ | |
2799 | if (inst_env->slot_needed) | |
2800 | { | |
2801 | inst_env->invalid = 1; | |
2802 | } | |
2803 | else | |
2804 | { | |
2805 | /* Check if we have a prefix. */ | |
2806 | if (inst_env->prefix_found) | |
2807 | { | |
2808 | check_assign (inst, inst_env); | |
2809 | ||
2810 | /* Get the new value for the the PC. */ | |
2811 | newpc = | |
2812 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2813 | 4); | |
2814 | } | |
2815 | else | |
2816 | { | |
2817 | /* Get the new value for the PC. */ | |
2818 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2819 | newpc = read_memory_unsigned_integer (address, 4); | |
2820 | ||
2821 | /* Check if we should increment a register. */ | |
2822 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2823 | { | |
2824 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2825 | } | |
2826 | } | |
2827 | inst_env->reg[REG_PC] = newpc; | |
2828 | } | |
2829 | inst_env->slot_needed = 0; | |
2830 | inst_env->prefix_found = 0; | |
2831 | inst_env->xflag_found = 0; | |
2832 | inst_env->disable_interrupt = 1; | |
2833 | } | |
2834 | ||
2835 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2836 | ||
a78f21af | 2837 | static void |
29134980 OF |
2838 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2839 | { | |
2840 | if (inst_env->prefix_found) | |
2841 | { | |
2842 | /* The instruction has a prefix that means we are only interested if | |
2843 | the instruction is in assign mode. */ | |
2844 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2845 | { | |
2846 | /* The prefix handles the problem if we are in a delay slot. */ | |
2847 | if (cris_get_operand1 (inst) == REG_PC) | |
2848 | { | |
2849 | /* Just take care of the assign. */ | |
2850 | check_assign (inst, inst_env); | |
2851 | } | |
2852 | } | |
2853 | } | |
2854 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2855 | { | |
2856 | /* The instruction doesn't have a prefix, the only case left that we | |
2857 | are interested in is the autoincrement mode. */ | |
2858 | if (cris_get_operand1 (inst) == REG_PC) | |
2859 | { | |
2860 | /* If the PC is to be incremented it's invalid to be in a | |
2861 | delay slot. */ | |
2862 | if (inst_env->slot_needed) | |
2863 | { | |
2864 | inst_env->invalid = 1; | |
2865 | return; | |
2866 | } | |
2a9ecef2 OF |
2867 | |
2868 | /* The increment depends on the size of the special register. */ | |
2869 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2870 | { |
2871 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2872 | } | |
2a9ecef2 | 2873 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2874 | { |
2875 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2876 | } | |
2877 | else | |
2878 | { | |
2879 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2880 | } | |
2881 | } | |
2882 | } | |
2883 | inst_env->slot_needed = 0; | |
2884 | inst_env->prefix_found = 0; | |
2885 | inst_env->xflag_found = 0; | |
2886 | inst_env->disable_interrupt = 1; | |
2887 | } | |
2888 | ||
2889 | /* Handles moves from special registers (aka P-register) for all modes | |
2890 | except register. */ | |
2891 | ||
a78f21af | 2892 | static void |
29134980 OF |
2893 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2894 | { | |
2895 | if (inst_env->prefix_found) | |
2896 | { | |
2897 | /* The instruction has a prefix that means we are only interested if | |
2898 | the instruction is in assign mode. */ | |
2899 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2900 | { | |
2901 | /* The prefix handles the problem if we are in a delay slot. */ | |
2902 | if (cris_get_operand1 (inst) == REG_PC) | |
2903 | { | |
2904 | /* Just take care of the assign. */ | |
2905 | check_assign (inst, inst_env); | |
2906 | } | |
2907 | } | |
2908 | } | |
2909 | /* The instruction doesn't have a prefix, the only case left that we | |
2910 | are interested in is the autoincrement mode. */ | |
2911 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2912 | { | |
2913 | if (cris_get_operand1 (inst) == REG_PC) | |
2914 | { | |
2915 | /* If the PC is to be incremented it's invalid to be in a | |
2916 | delay slot. */ | |
2917 | if (inst_env->slot_needed) | |
2918 | { | |
2919 | inst_env->invalid = 1; | |
2920 | return; | |
2921 | } | |
2a9ecef2 OF |
2922 | |
2923 | /* The increment depends on the size of the special register. */ | |
2924 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2925 | { |
2926 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2927 | } | |
2a9ecef2 | 2928 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2929 | { |
2930 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2931 | } | |
2932 | else | |
2933 | { | |
2934 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2935 | } | |
2936 | } | |
2937 | } | |
2938 | inst_env->slot_needed = 0; | |
2939 | inst_env->prefix_found = 0; | |
2940 | inst_env->xflag_found = 0; | |
2941 | inst_env->disable_interrupt = 1; | |
2942 | } | |
2943 | ||
2944 | /* Handles moves from special registers (aka P-register) when the mode | |
2945 | is register. */ | |
2946 | ||
a78f21af | 2947 | static void |
29134980 OF |
2948 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2949 | { | |
2950 | /* Register mode move from special register can't have a prefix. */ | |
2951 | if (inst_env->prefix_found) | |
2952 | { | |
2953 | inst_env->invalid = 1; | |
2954 | return; | |
2955 | } | |
2956 | ||
2957 | if (cris_get_operand1 (inst) == REG_PC) | |
2958 | { | |
2959 | /* It's invalid to change the PC in a delay slot. */ | |
2960 | if (inst_env->slot_needed) | |
2961 | { | |
2962 | inst_env->invalid = 1; | |
2963 | return; | |
2964 | } | |
2965 | /* The destination is the PC, the jump will have a delay slot. */ | |
2966 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2967 | inst_env->slot_needed = 1; | |
2968 | inst_env->delay_slot_pc_active = 1; | |
2969 | } | |
2970 | else | |
2971 | { | |
2972 | /* If the destination isn't PC, there will be no jump. */ | |
2973 | inst_env->slot_needed = 0; | |
2974 | } | |
2975 | inst_env->prefix_found = 0; | |
2976 | inst_env->xflag_found = 0; | |
2977 | inst_env->disable_interrupt = 1; | |
2978 | } | |
2979 | ||
2980 | /* Handles the MOVEM from memory to general register instruction. */ | |
2981 | ||
a78f21af | 2982 | static void |
29134980 OF |
2983 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
2984 | { | |
2985 | if (inst_env->prefix_found) | |
2986 | { | |
2987 | /* The prefix handles the problem if we are in a delay slot. Is the | |
2988 | MOVEM instruction going to change the PC? */ | |
2989 | if (cris_get_operand2 (inst) >= REG_PC) | |
2990 | { | |
2991 | inst_env->reg[REG_PC] = | |
2992 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
2993 | } | |
2994 | /* The assign value is the value after the increment. Normally, the | |
2995 | assign value is the value before the increment. */ | |
2996 | if ((cris_get_operand1 (inst) == REG_PC) | |
2997 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2998 | { | |
2999 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3000 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3001 | } | |
3002 | } | |
3003 | else | |
3004 | { | |
3005 | /* Is the MOVEM instruction going to change the PC? */ | |
3006 | if (cris_get_operand2 (inst) == REG_PC) | |
3007 | { | |
3008 | /* It's invalid to change the PC in a delay slot. */ | |
3009 | if (inst_env->slot_needed) | |
3010 | { | |
3011 | inst_env->invalid = 1; | |
3012 | return; | |
3013 | } | |
3014 | inst_env->reg[REG_PC] = | |
3015 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3016 | 4); | |
3017 | } | |
3018 | /* The increment is not depending on the size, instead it's depending | |
3019 | on the number of registers loaded from memory. */ | |
3020 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3021 | { | |
3022 | /* It's invalid to change the PC in a delay slot. */ | |
3023 | if (inst_env->slot_needed) | |
3024 | { | |
3025 | inst_env->invalid = 1; | |
3026 | return; | |
3027 | } | |
3028 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3029 | } | |
3030 | } | |
3031 | inst_env->slot_needed = 0; | |
3032 | inst_env->prefix_found = 0; | |
3033 | inst_env->xflag_found = 0; | |
3034 | inst_env->disable_interrupt = 0; | |
3035 | } | |
3036 | ||
3037 | /* Handles the MOVEM to memory from general register instruction. */ | |
3038 | ||
a78f21af | 3039 | static void |
29134980 OF |
3040 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3041 | { | |
3042 | if (inst_env->prefix_found) | |
3043 | { | |
3044 | /* The assign value is the value after the increment. Normally, the | |
3045 | assign value is the value before the increment. */ | |
3046 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3047 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3048 | { | |
3049 | /* The prefix handles the problem if we are in a delay slot. */ | |
3050 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3051 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3052 | } | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | /* The increment is not depending on the size, instead it's depending | |
3057 | on the number of registers loaded to memory. */ | |
3058 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3059 | { | |
3060 | /* It's invalid to change the PC in a delay slot. */ | |
3061 | if (inst_env->slot_needed) | |
3062 | { | |
3063 | inst_env->invalid = 1; | |
3064 | return; | |
3065 | } | |
3066 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3067 | } | |
3068 | } | |
3069 | inst_env->slot_needed = 0; | |
3070 | inst_env->prefix_found = 0; | |
3071 | inst_env->xflag_found = 0; | |
3072 | inst_env->disable_interrupt = 0; | |
3073 | } | |
3074 | ||
29134980 OF |
3075 | /* Handles the intructions that's not yet implemented, by setting |
3076 | inst_env->invalid to true. */ | |
3077 | ||
a78f21af | 3078 | static void |
29134980 OF |
3079 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3080 | { | |
3081 | inst_env->invalid = 1; | |
3082 | } | |
3083 | ||
3084 | /* Handles the XOR instruction. */ | |
3085 | ||
a78f21af | 3086 | static void |
29134980 OF |
3087 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3088 | { | |
3089 | /* XOR can't have a prefix. */ | |
3090 | if (inst_env->prefix_found) | |
3091 | { | |
3092 | inst_env->invalid = 1; | |
3093 | return; | |
3094 | } | |
3095 | ||
3096 | /* Check if the PC is the target. */ | |
3097 | if (cris_get_operand2 (inst) == REG_PC) | |
3098 | { | |
3099 | /* It's invalid to change the PC in a delay slot. */ | |
3100 | if (inst_env->slot_needed) | |
3101 | { | |
3102 | inst_env->invalid = 1; | |
3103 | return; | |
3104 | } | |
3105 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3106 | } | |
3107 | inst_env->slot_needed = 0; | |
3108 | inst_env->prefix_found = 0; | |
3109 | inst_env->xflag_found = 0; | |
3110 | inst_env->disable_interrupt = 0; | |
3111 | } | |
3112 | ||
3113 | /* Handles the MULS instruction. */ | |
3114 | ||
a78f21af | 3115 | static void |
29134980 OF |
3116 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3117 | { | |
3118 | /* MULS/U can't have a prefix. */ | |
3119 | if (inst_env->prefix_found) | |
3120 | { | |
3121 | inst_env->invalid = 1; | |
3122 | return; | |
3123 | } | |
3124 | ||
3125 | /* Consider it invalid if the PC is the target. */ | |
3126 | if (cris_get_operand2 (inst) == REG_PC) | |
3127 | { | |
3128 | inst_env->invalid = 1; | |
3129 | return; | |
3130 | } | |
3131 | inst_env->slot_needed = 0; | |
3132 | inst_env->prefix_found = 0; | |
3133 | inst_env->xflag_found = 0; | |
3134 | inst_env->disable_interrupt = 0; | |
3135 | } | |
3136 | ||
3137 | /* Handles the MULU instruction. */ | |
3138 | ||
a78f21af | 3139 | static void |
29134980 OF |
3140 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3141 | { | |
3142 | /* MULS/U can't have a prefix. */ | |
3143 | if (inst_env->prefix_found) | |
3144 | { | |
3145 | inst_env->invalid = 1; | |
3146 | return; | |
3147 | } | |
3148 | ||
3149 | /* Consider it invalid if the PC is the target. */ | |
3150 | if (cris_get_operand2 (inst) == REG_PC) | |
3151 | { | |
3152 | inst_env->invalid = 1; | |
3153 | return; | |
3154 | } | |
3155 | inst_env->slot_needed = 0; | |
3156 | inst_env->prefix_found = 0; | |
3157 | inst_env->xflag_found = 0; | |
3158 | inst_env->disable_interrupt = 0; | |
3159 | } | |
3160 | ||
3161 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3162 | The MOVE instruction is the move from source to register. */ | |
3163 | ||
a78f21af | 3164 | static void |
29134980 OF |
3165 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3166 | unsigned long source1, unsigned long source2) | |
3167 | { | |
3168 | unsigned long pc_mask; | |
3169 | unsigned long operation_mask; | |
3170 | ||
3171 | /* Find out how many bits the operation should apply to. */ | |
3172 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3173 | { | |
3174 | pc_mask = 0xFFFFFF00; | |
3175 | operation_mask = 0xFF; | |
3176 | } | |
3177 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3178 | { | |
3179 | pc_mask = 0xFFFF0000; | |
3180 | operation_mask = 0xFFFF; | |
3181 | } | |
3182 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3183 | { | |
3184 | pc_mask = 0x0; | |
3185 | operation_mask = 0xFFFFFFFF; | |
3186 | } | |
3187 | else | |
3188 | { | |
3189 | /* The size is out of range. */ | |
3190 | inst_env->invalid = 1; | |
3191 | return; | |
3192 | } | |
3193 | ||
3194 | /* The instruction just works on uw_operation_mask bits. */ | |
3195 | source2 &= operation_mask; | |
3196 | source1 &= operation_mask; | |
3197 | ||
3198 | /* Now calculate the result. The opcode's 3 first bits separates | |
3199 | the different actions. */ | |
3200 | switch (cris_get_opcode (inst) & 7) | |
3201 | { | |
3202 | case 0: /* add */ | |
3203 | source1 += source2; | |
3204 | break; | |
3205 | ||
3206 | case 1: /* move */ | |
3207 | source1 = source2; | |
3208 | break; | |
3209 | ||
3210 | case 2: /* subtract */ | |
3211 | source1 -= source2; | |
3212 | break; | |
3213 | ||
3214 | case 3: /* compare */ | |
3215 | break; | |
3216 | ||
3217 | case 4: /* and */ | |
3218 | source1 &= source2; | |
3219 | break; | |
3220 | ||
3221 | case 5: /* or */ | |
3222 | source1 |= source2; | |
3223 | break; | |
3224 | ||
3225 | default: | |
3226 | inst_env->invalid = 1; | |
3227 | return; | |
3228 | ||
3229 | break; | |
3230 | } | |
3231 | ||
3232 | /* Make sure that the result doesn't contain more than the instruction | |
3233 | size bits. */ | |
3234 | source2 &= operation_mask; | |
3235 | ||
3236 | /* Calculate the new breakpoint address. */ | |
3237 | inst_env->reg[REG_PC] &= pc_mask; | |
3238 | inst_env->reg[REG_PC] |= source1; | |
3239 | ||
3240 | } | |
3241 | ||
3242 | /* Extends the value from either byte or word size to a dword. If the mode | |
3243 | is zero extend then the value is extended with zero. If instead the mode | |
3244 | is signed extend the sign bit of the value is taken into consideration. */ | |
3245 | ||
a78f21af | 3246 | static unsigned long |
29134980 OF |
3247 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3248 | { | |
3249 | /* The size can be either byte or word, check which one it is. | |
3250 | Don't check the highest bit, it's indicating if it's a zero | |
3251 | or sign extend. */ | |
3252 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3253 | { | |
3254 | /* Word size. */ | |
3255 | value &= 0xFFFF; | |
3256 | ||
3257 | /* Check if the instruction is signed extend. If so, check if value has | |
3258 | the sign bit on. */ | |
3259 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3260 | { | |
3261 | value |= SIGNED_WORD_EXTEND_MASK; | |
3262 | } | |
3263 | } | |
3264 | else | |
3265 | { | |
3266 | /* Byte size. */ | |
3267 | value &= 0xFF; | |
3268 | ||
3269 | /* Check if the instruction is signed extend. If so, check if value has | |
3270 | the sign bit on. */ | |
3271 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3272 | { | |
3273 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3274 | } | |
3275 | } | |
3276 | /* The size should now be dword. */ | |
3277 | cris_set_size_to_dword (inst); | |
3278 | return value; | |
3279 | } | |
3280 | ||
3281 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3282 | instruction. The MOVE instruction is the move from source to register. */ | |
3283 | ||
a78f21af | 3284 | static void |
29134980 OF |
3285 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3286 | inst_env_type *inst_env) | |
3287 | { | |
3288 | unsigned long operand1; | |
3289 | unsigned long operand2; | |
3290 | ||
3291 | /* It's invalid to have a prefix to the instruction. This is a register | |
3292 | mode instruction and can't have a prefix. */ | |
3293 | if (inst_env->prefix_found) | |
3294 | { | |
3295 | inst_env->invalid = 1; | |
3296 | return; | |
3297 | } | |
3298 | /* Check if the instruction has PC as its target. */ | |
3299 | if (cris_get_operand2 (inst) == REG_PC) | |
3300 | { | |
3301 | if (inst_env->slot_needed) | |
3302 | { | |
3303 | inst_env->invalid = 1; | |
3304 | return; | |
3305 | } | |
3306 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3307 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3308 | operand2 = inst_env->reg[REG_PC]; |
3309 | ||
3310 | /* Check if it's a extend, signed or zero instruction. */ | |
3311 | if (cris_get_opcode (inst) < 4) | |
3312 | { | |
3313 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3314 | } | |
3315 | /* Calculate the PC value after the instruction, i.e. where the | |
3316 | breakpoint should be. The order of the udw_operands is vital. */ | |
3317 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3318 | } | |
3319 | inst_env->slot_needed = 0; | |
3320 | inst_env->prefix_found = 0; | |
3321 | inst_env->xflag_found = 0; | |
3322 | inst_env->disable_interrupt = 0; | |
3323 | } | |
3324 | ||
3325 | /* Returns the data contained at address. The size of the data is derived from | |
3326 | the size of the operation. If the instruction is a zero or signed | |
3327 | extend instruction, the size field is changed in instruction. */ | |
3328 | ||
a78f21af | 3329 | static unsigned long |
29134980 OF |
3330 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3331 | { | |
3332 | int size = cris_get_size (*inst); | |
3333 | unsigned long value; | |
3334 | ||
3335 | /* If it's an extend instruction we don't want the signed extend bit, | |
3336 | because it influences the size. */ | |
3337 | if (cris_get_opcode (*inst) < 4) | |
3338 | { | |
3339 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3340 | } | |
3341 | /* Is there a need for checking the size? Size should contain the number of | |
3342 | bytes to read. */ | |
3343 | size = 1 << size; | |
3344 | value = read_memory_unsigned_integer (address, size); | |
3345 | ||
3346 | /* Check if it's an extend, signed or zero instruction. */ | |
3347 | if (cris_get_opcode (*inst) < 4) | |
3348 | { | |
3349 | value = do_sign_or_zero_extend (value, inst); | |
3350 | } | |
3351 | return value; | |
3352 | } | |
3353 | ||
3354 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3355 | instructions. The MOVE instruction is the move from source to register. */ | |
3356 | ||
a78f21af | 3357 | static void |
29134980 OF |
3358 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3359 | inst_env_type *inst_env) | |
3360 | { | |
3361 | unsigned long operand2; | |
3362 | unsigned long operand3; | |
3363 | ||
3364 | check_assign (inst, inst_env); | |
3365 | if (cris_get_operand2 (inst) == REG_PC) | |
3366 | { | |
3367 | operand2 = inst_env->reg[REG_PC]; | |
3368 | ||
3369 | /* Get the value of the third operand. */ | |
3370 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3371 | ||
3372 | /* Calculate the PC value after the instruction, i.e. where the | |
3373 | breakpoint should be. The order of the udw_operands is vital. */ | |
3374 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3375 | } | |
3376 | inst_env->slot_needed = 0; | |
3377 | inst_env->prefix_found = 0; | |
3378 | inst_env->xflag_found = 0; | |
3379 | inst_env->disable_interrupt = 0; | |
3380 | } | |
3381 | ||
3382 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3383 | OR instructions. Note that for this to work as expected, the calling | |
3384 | function must have made sure that there is a prefix to this instruction. */ | |
3385 | ||
a78f21af | 3386 | static void |
29134980 OF |
3387 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3388 | inst_env_type *inst_env) | |
3389 | { | |
3390 | unsigned long operand2; | |
3391 | unsigned long operand3; | |
3392 | ||
3393 | if (cris_get_operand1 (inst) == REG_PC) | |
3394 | { | |
3395 | /* The PC will be changed by the instruction. */ | |
3396 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3397 | ||
3398 | /* Get the value of the third operand. */ | |
3399 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3400 | ||
3401 | /* Calculate the PC value after the instruction, i.e. where the | |
3402 | breakpoint should be. */ | |
3403 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3404 | } | |
3405 | inst_env->slot_needed = 0; | |
3406 | inst_env->prefix_found = 0; | |
3407 | inst_env->xflag_found = 0; | |
3408 | inst_env->disable_interrupt = 0; | |
3409 | } | |
3410 | ||
3411 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3412 | instructions. The MOVE instruction is the move from source to register. */ | |
3413 | ||
a78f21af | 3414 | static void |
29134980 OF |
3415 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3416 | inst_env_type *inst_env) | |
3417 | { | |
3418 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3419 | { | |
3420 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3421 | SUB, AND or OR something weird is going on (if everything works these | |
3422 | instructions should end up in the three operand version). */ | |
3423 | inst_env->invalid = 1; | |
3424 | return; | |
3425 | } | |
3426 | else | |
3427 | { | |
3428 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3429 | so use it. */ | |
3430 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3431 | } | |
3432 | inst_env->slot_needed = 0; | |
3433 | inst_env->prefix_found = 0; | |
3434 | inst_env->xflag_found = 0; | |
3435 | inst_env->disable_interrupt = 0; | |
3436 | } | |
3437 | ||
3438 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3439 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3440 | source to register. */ | |
3441 | ||
a78f21af | 3442 | static void |
29134980 OF |
3443 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3444 | inst_env_type *inst_env) | |
3445 | { | |
3446 | unsigned long operand1; | |
3447 | unsigned long operand2; | |
3448 | unsigned long operand3; | |
3449 | int size; | |
3450 | ||
3451 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3452 | Check if the destination register is the PC. */ | |
3453 | if (cris_get_operand2 (inst) == REG_PC) | |
3454 | { | |
3455 | /* Must be done here, get_data_from_address may change the size | |
3456 | field. */ | |
3457 | size = cris_get_size (inst); | |
3458 | operand2 = inst_env->reg[REG_PC]; | |
3459 | ||
3460 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3461 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3462 | operand3 = get_data_from_address (&inst, operand1); | |
3463 | ||
3464 | /* Calculate the PC value after the instruction, i.e. where the | |
3465 | breakpoint should be. The order of the udw_operands is vital. */ | |
3466 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3467 | } | |
3468 | /* If this is an autoincrement addressing mode, check if the increment | |
3469 | changes the PC. */ | |
3470 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3471 | { | |
3472 | /* Get the size field. */ | |
3473 | size = cris_get_size (inst); | |
3474 | ||
3475 | /* If it's an extend instruction we don't want the signed extend bit, | |
3476 | because it influences the size. */ | |
3477 | if (cris_get_opcode (inst) < 4) | |
3478 | { | |
3479 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3480 | } | |
3481 | process_autoincrement (size, inst, inst_env); | |
3482 | } | |
3483 | inst_env->slot_needed = 0; | |
3484 | inst_env->prefix_found = 0; | |
3485 | inst_env->xflag_found = 0; | |
3486 | inst_env->disable_interrupt = 0; | |
3487 | } | |
3488 | ||
3489 | /* Handles the two-operand addressing mode, all modes except register, for | |
3490 | the ADD, SUB CMP, AND and OR instruction. */ | |
3491 | ||
a78f21af | 3492 | static void |
29134980 OF |
3493 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3494 | inst_env_type *inst_env) | |
3495 | { | |
3496 | if (inst_env->prefix_found) | |
3497 | { | |
3498 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3499 | { | |
3500 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3501 | } | |
3502 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3503 | { | |
3504 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3505 | } | |
3506 | else | |
3507 | { | |
3508 | /* The mode is invalid for a prefixed base instruction. */ | |
3509 | inst_env->invalid = 1; | |
3510 | return; | |
3511 | } | |
3512 | } | |
3513 | else | |
3514 | { | |
3515 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3516 | } | |
3517 | } | |
3518 | ||
3519 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3520 | ||
a78f21af | 3521 | static void |
29134980 OF |
3522 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3523 | { | |
3524 | unsigned long operand1; | |
3525 | unsigned long operand2; | |
3526 | ||
3527 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3528 | instruction and can't have a prefix. */ | |
3529 | if (inst_env->prefix_found) | |
3530 | { | |
3531 | inst_env->invalid = 1; | |
3532 | return; | |
3533 | } | |
3534 | ||
3535 | /* Check if the instruction has PC as its target. */ | |
3536 | if (cris_get_operand2 (inst) == REG_PC) | |
3537 | { | |
3538 | if (inst_env->slot_needed) | |
3539 | { | |
3540 | inst_env->invalid = 1; | |
3541 | return; | |
3542 | } | |
3543 | operand1 = cris_get_quick_value (inst); | |
3544 | operand2 = inst_env->reg[REG_PC]; | |
3545 | ||
3546 | /* The size should now be dword. */ | |
3547 | cris_set_size_to_dword (&inst); | |
3548 | ||
3549 | /* Calculate the PC value after the instruction, i.e. where the | |
3550 | breakpoint should be. */ | |
3551 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3552 | } | |
3553 | inst_env->slot_needed = 0; | |
3554 | inst_env->prefix_found = 0; | |
3555 | inst_env->xflag_found = 0; | |
3556 | inst_env->disable_interrupt = 0; | |
3557 | } | |
3558 | ||
3559 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3560 | ||
a78f21af | 3561 | static void |
29134980 OF |
3562 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3563 | { | |
3564 | unsigned long operand1; | |
3565 | unsigned long operand2; | |
3566 | ||
3567 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3568 | instruction and can't have a prefix. */ | |
3569 | if (inst_env->prefix_found) | |
3570 | { | |
3571 | inst_env->invalid = 1; | |
3572 | return; | |
3573 | } | |
3574 | /* Check if the instruction has PC as its target. */ | |
3575 | if (cris_get_operand2 (inst) == REG_PC) | |
3576 | { | |
3577 | if (inst_env->slot_needed) | |
3578 | { | |
3579 | inst_env->invalid = 1; | |
3580 | return; | |
3581 | } | |
3582 | /* The instruction has the PC as its target register. */ | |
3583 | operand1 = cris_get_quick_value (inst); | |
3584 | operand2 = inst_env->reg[REG_PC]; | |
3585 | ||
3586 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3587 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3588 | { | |
3589 | /* sign extend */ | |
3590 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3591 | } | |
3592 | /* The size should now be dword. */ | |
3593 | cris_set_size_to_dword (&inst); | |
3594 | ||
3595 | /* Calculate the PC value after the instruction, i.e. where the | |
3596 | breakpoint should be. */ | |
3597 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3598 | } | |
3599 | inst_env->slot_needed = 0; | |
3600 | inst_env->prefix_found = 0; | |
3601 | inst_env->xflag_found = 0; | |
3602 | inst_env->disable_interrupt = 0; | |
3603 | } | |
3604 | ||
3605 | /* Translate op_type to a function and call it. */ | |
3606 | ||
a78f21af AC |
3607 | static void |
3608 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3609 | inst_env_type *inst_env) | |
29134980 OF |
3610 | { |
3611 | switch (op_type) | |
3612 | { | |
3613 | case cris_not_implemented_op: | |
3614 | not_implemented_op (inst, inst_env); | |
3615 | break; | |
3616 | ||
3617 | case cris_abs_op: | |
3618 | abs_op (inst, inst_env); | |
3619 | break; | |
3620 | ||
3621 | case cris_addi_op: | |
3622 | addi_op (inst, inst_env); | |
3623 | break; | |
3624 | ||
3625 | case cris_asr_op: | |
3626 | asr_op (inst, inst_env); | |
3627 | break; | |
3628 | ||
3629 | case cris_asrq_op: | |
3630 | asrq_op (inst, inst_env); | |
3631 | break; | |
3632 | ||
3633 | case cris_ax_ei_setf_op: | |
3634 | ax_ei_setf_op (inst, inst_env); | |
3635 | break; | |
3636 | ||
3637 | case cris_bdap_prefix: | |
3638 | bdap_prefix (inst, inst_env); | |
3639 | break; | |
3640 | ||
3641 | case cris_biap_prefix: | |
3642 | biap_prefix (inst, inst_env); | |
3643 | break; | |
3644 | ||
3645 | case cris_break_op: | |
3646 | break_op (inst, inst_env); | |
3647 | break; | |
3648 | ||
3649 | case cris_btst_nop_op: | |
3650 | btst_nop_op (inst, inst_env); | |
3651 | break; | |
3652 | ||
3653 | case cris_clearf_di_op: | |
3654 | clearf_di_op (inst, inst_env); | |
3655 | break; | |
3656 | ||
3657 | case cris_dip_prefix: | |
3658 | dip_prefix (inst, inst_env); | |
3659 | break; | |
3660 | ||
3661 | case cris_dstep_logshift_mstep_neg_not_op: | |
3662 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3663 | break; | |
3664 | ||
3665 | case cris_eight_bit_offset_branch_op: | |
3666 | eight_bit_offset_branch_op (inst, inst_env); | |
3667 | break; | |
3668 | ||
3669 | case cris_move_mem_to_reg_movem_op: | |
3670 | move_mem_to_reg_movem_op (inst, inst_env); | |
3671 | break; | |
3672 | ||
3673 | case cris_move_reg_to_mem_movem_op: | |
3674 | move_reg_to_mem_movem_op (inst, inst_env); | |
3675 | break; | |
3676 | ||
3677 | case cris_move_to_preg_op: | |
3678 | move_to_preg_op (inst, inst_env); | |
3679 | break; | |
3680 | ||
3681 | case cris_muls_op: | |
3682 | muls_op (inst, inst_env); | |
3683 | break; | |
3684 | ||
3685 | case cris_mulu_op: | |
3686 | mulu_op (inst, inst_env); | |
3687 | break; | |
3688 | ||
3689 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3690 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3691 | break; | |
3692 | ||
3693 | case cris_none_reg_mode_clear_test_op: | |
3694 | none_reg_mode_clear_test_op (inst, inst_env); | |
3695 | break; | |
3696 | ||
3697 | case cris_none_reg_mode_jump_op: | |
3698 | none_reg_mode_jump_op (inst, inst_env); | |
3699 | break; | |
3700 | ||
3701 | case cris_none_reg_mode_move_from_preg_op: | |
3702 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3703 | break; | |
3704 | ||
3705 | case cris_quick_mode_add_sub_op: | |
3706 | quick_mode_add_sub_op (inst, inst_env); | |
3707 | break; | |
3708 | ||
3709 | case cris_quick_mode_and_cmp_move_or_op: | |
3710 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3711 | break; | |
3712 | ||
3713 | case cris_quick_mode_bdap_prefix: | |
3714 | quick_mode_bdap_prefix (inst, inst_env); | |
3715 | break; | |
3716 | ||
3717 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3718 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3719 | break; | |
3720 | ||
3721 | case cris_reg_mode_clear_op: | |
3722 | reg_mode_clear_op (inst, inst_env); | |
3723 | break; | |
3724 | ||
3725 | case cris_reg_mode_jump_op: | |
3726 | reg_mode_jump_op (inst, inst_env); | |
3727 | break; | |
3728 | ||
3729 | case cris_reg_mode_move_from_preg_op: | |
3730 | reg_mode_move_from_preg_op (inst, inst_env); | |
3731 | break; | |
3732 | ||
3733 | case cris_reg_mode_test_op: | |
3734 | reg_mode_test_op (inst, inst_env); | |
3735 | break; | |
3736 | ||
3737 | case cris_scc_op: | |
3738 | scc_op (inst, inst_env); | |
3739 | break; | |
3740 | ||
3741 | case cris_sixteen_bit_offset_branch_op: | |
3742 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3743 | break; | |
3744 | ||
3745 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3746 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3747 | break; | |
3748 | ||
3749 | case cris_three_operand_bound_op: | |
3750 | three_operand_bound_op (inst, inst_env); | |
3751 | break; | |
3752 | ||
3753 | case cris_two_operand_bound_op: | |
3754 | two_operand_bound_op (inst, inst_env); | |
3755 | break; | |
3756 | ||
3757 | case cris_xor_op: | |
3758 | xor_op (inst, inst_env); | |
3759 | break; | |
3760 | } | |
3761 | } | |
3762 | ||
3763 | /* This wrapper is to avoid cris_get_assembler being called before | |
3764 | exec_bfd has been set. */ | |
3765 | ||
3766 | static int | |
a89aa300 | 3767 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3768 | { |
a89aa300 | 3769 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3770 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3771 | disassembler, even when there is no BFD. Does something like | |
3772 | "gdb; target remote; disassmeble *0x123" work? */ | |
3773 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3774 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3775 | gdb_assert (print_insn != NULL); |
3776 | return print_insn (addr, info); | |
29134980 OF |
3777 | } |
3778 | ||
dbbff683 OF |
3779 | /* Copied from <asm/elf.h>. */ |
3780 | typedef unsigned long elf_greg_t; | |
3781 | ||
3782 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3783 | #define CRISV10_ELF_NGREG 35 |
3784 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3785 | ||
3786 | #define CRISV32_ELF_NGREG 32 | |
3787 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3788 | |
3789 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3790 | ||
a78f21af | 3791 | static void |
dbbff683 OF |
3792 | supply_gregset (elf_gregset_t *gregsetp) |
3793 | { | |
c600d464 | 3794 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3795 | int i; |
3796 | elf_greg_t *regp = *gregsetp; | |
3797 | static char zerobuf[4] = {0}; | |
3798 | ||
3799 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3800 | knows about the actual size of each register so that's no problem. */ | |
3801 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3802 | { | |
23a6d369 | 3803 | regcache_raw_supply (current_regcache, i, (char *)®p[i]); |
dbbff683 | 3804 | } |
c600d464 OF |
3805 | |
3806 | if (tdep->cris_version == 32) | |
3807 | { | |
3808 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3809 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3810 | be wrong. Issue a warning to alert the user. */ | |
3811 | regcache_raw_supply (current_regcache, PC_REGNUM, | |
3812 | (char *)®p[ERP_REGNUM]); | |
3813 | ||
3814 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3815 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3816 | } | |
dbbff683 OF |
3817 | } |
3818 | ||
3819 | /* Use a local version of this function to get the correct types for | |
3820 | regsets, until multi-arch core support is ready. */ | |
3821 | ||
3822 | static void | |
3823 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, | |
3824 | int which, CORE_ADDR reg_addr) | |
3825 | { | |
3826 | elf_gregset_t gregset; | |
3827 | ||
3828 | switch (which) | |
3829 | { | |
3830 | case 0: | |
c600d464 OF |
3831 | if (core_reg_size != sizeof (elf_gregset_t) |
3832 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 OF |
3833 | { |
3834 | warning ("wrong size gregset struct in core file"); | |
3835 | } | |
3836 | else | |
3837 | { | |
3838 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
3839 | supply_gregset (&gregset); | |
3840 | } | |
3841 | ||
3842 | default: | |
3843 | /* We've covered all the kinds of registers we know about here, | |
3844 | so this must be something we wouldn't know what to do with | |
3845 | anyway. Just ignore it. */ | |
3846 | break; | |
3847 | } | |
3848 | } | |
3849 | ||
3850 | static struct core_fns cris_elf_core_fns = | |
3851 | { | |
3852 | bfd_target_elf_flavour, /* core_flavour */ | |
3853 | default_check_format, /* check_format */ | |
3854 | default_core_sniffer, /* core_sniffer */ | |
3855 | fetch_core_registers, /* core_read_registers */ | |
3856 | NULL /* next */ | |
3857 | }; | |
3858 | ||
3859 | /* Fetch (and possibly build) an appropriate link_map_offsets | |
8605d56e AC |
3860 | structure for native GNU/Linux CRIS targets using the struct |
3861 | offsets defined in link.h (but without actual reference to that | |
3862 | file). | |
dbbff683 | 3863 | |
8605d56e AC |
3864 | This makes it possible to access GNU/Linux CRIS shared libraries |
3865 | from a GDB that was not built on an GNU/Linux CRIS host (for cross | |
3866 | debugging). | |
dbbff683 OF |
3867 | |
3868 | See gdb/solib-svr4.h for an explanation of these fields. */ | |
3869 | ||
a78f21af | 3870 | static struct link_map_offsets * |
dbbff683 OF |
3871 | cris_linux_svr4_fetch_link_map_offsets (void) |
3872 | { | |
3873 | static struct link_map_offsets lmo; | |
3874 | static struct link_map_offsets *lmp = NULL; | |
3875 | ||
3876 | if (lmp == NULL) | |
3877 | { | |
3878 | lmp = &lmo; | |
3879 | ||
3880 | lmo.r_debug_size = 8; /* The actual size is 20 bytes, but | |
3881 | this is all we need. */ | |
3882 | lmo.r_map_offset = 4; | |
3883 | lmo.r_map_size = 4; | |
3884 | ||
3885 | lmo.link_map_size = 20; | |
3886 | ||
3887 | lmo.l_addr_offset = 0; | |
3888 | lmo.l_addr_size = 4; | |
3889 | ||
3890 | lmo.l_name_offset = 4; | |
3891 | lmo.l_name_size = 4; | |
3892 | ||
3893 | lmo.l_next_offset = 12; | |
3894 | lmo.l_next_size = 4; | |
3895 | ||
3896 | lmo.l_prev_offset = 16; | |
3897 | lmo.l_prev_size = 4; | |
3898 | } | |
3899 | ||
3900 | return lmp; | |
3901 | } | |
3902 | ||
a78f21af AC |
3903 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3904 | ||
29134980 OF |
3905 | void |
3906 | _initialize_cris_tdep (void) | |
3907 | { | |
a5f6c8f5 OF |
3908 | static struct cmd_list_element *cris_set_cmdlist; |
3909 | static struct cmd_list_element *cris_show_cmdlist; | |
3910 | ||
29134980 OF |
3911 | struct cmd_list_element *c; |
3912 | ||
3913 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3914 | ||
29134980 | 3915 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3916 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3917 | &usr_cmd_cris_version, | |
3918 | "Set the current CRIS version.", | |
3919 | "Show the current CRIS version.", | |
3920 | "Set if autodetection fails.", | |
3921 | "Current CRIS version is %s.", | |
3922 | set_cris_version, NULL, | |
3923 | &setlist, &showlist); | |
dbbff683 | 3924 | |
a5f6c8f5 OF |
3925 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3926 | &usr_cmd_cris_dwarf2_cfi, | |
3927 | "Set the usage of Dwarf-2 CFI for CRIS.", | |
3928 | "Show the usage of Dwarf-2 CFI for CRIS.", | |
3929 | "Set to \"off\" if using gcc-cris < R59.", | |
3930 | "Usage of Dwarf-2 CFI for CRIS is %d.", | |
3931 | set_cris_dwarf2_cfi, NULL, | |
3932 | &setlist, &showlist); | |
3933 | ||
52bd1401 | 3934 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3935 | } |
3936 | ||
3937 | /* Prints out all target specific values. */ | |
3938 | ||
3939 | static void | |
3940 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3941 | { | |
3942 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3943 | if (tdep != NULL) | |
3944 | { | |
3945 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3946 | tdep->cris_version); | |
a5f6c8f5 OF |
3947 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
3948 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3949 | } |
3950 | } | |
3951 | ||
3952 | static void | |
a5f6c8f5 OF |
3953 | set_cris_version (char *ignore_args, int from_tty, |
3954 | struct cmd_list_element *c) | |
29134980 OF |
3955 | { |
3956 | struct gdbarch_info info; | |
3957 | ||
a5f6c8f5 | 3958 | usr_cmd_cris_version_valid = 1; |
29134980 | 3959 | |
a5f6c8f5 OF |
3960 | /* Update the current architecture, if needed. */ |
3961 | gdbarch_info_init (&info); | |
3962 | if (!gdbarch_update_p (info)) | |
3963 | internal_error (__FILE__, __LINE__, | |
3964 | "cris_gdbarch_update: failed to update architecture."); | |
29134980 OF |
3965 | } |
3966 | ||
3967 | static void | |
a5f6c8f5 OF |
3968 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
3969 | struct cmd_list_element *c) | |
29134980 OF |
3970 | { |
3971 | struct gdbarch_info info; | |
a5f6c8f5 OF |
3972 | |
3973 | /* Update the current architecture, if needed. */ | |
3974 | gdbarch_info_init (&info); | |
3975 | if (!gdbarch_update_p (info)) | |
3976 | internal_error (__FILE__, __LINE__, | |
3977 | "cris_gdbarch_update: failed to update architecture."); | |
29134980 OF |
3978 | } |
3979 | ||
29134980 OF |
3980 | static struct gdbarch * |
3981 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3982 | { | |
3983 | struct gdbarch *gdbarch; | |
3984 | struct gdbarch_tdep *tdep; | |
3985 | int cris_version; | |
29134980 OF |
3986 | |
3987 | if (usr_cmd_cris_version_valid) | |
3988 | { | |
3989 | /* Trust the user's CRIS version setting. */ | |
3990 | cris_version = usr_cmd_cris_version; | |
3991 | } | |
c600d464 OF |
3992 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
3993 | { | |
3994 | cris_version = 32; | |
3995 | } | |
29134980 OF |
3996 | else |
3997 | { | |
3998 | /* Assume it's CRIS version 10. */ | |
3999 | cris_version = 10; | |
4000 | } | |
4001 | ||
29134980 OF |
4002 | /* Make the current settings visible to the user. */ |
4003 | usr_cmd_cris_version = cris_version; | |
29134980 OF |
4004 | |
4005 | /* Find a candidate among the list of pre-declared architectures. Both | |
4006 | CRIS version and ABI must match. */ | |
4007 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4008 | arches != NULL; | |
4009 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4010 | { | |
a5f6c8f5 OF |
4011 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4012 | == usr_cmd_cris_version) | |
4013 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi | |
4014 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4015 | return arches->gdbarch; |
4016 | } | |
4017 | ||
4018 | /* No matching architecture was found. Create a new one. */ | |
4019 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4020 | gdbarch = gdbarch_alloc (&info, tdep); | |
4021 | ||
a5f6c8f5 OF |
4022 | tdep->cris_version = usr_cmd_cris_version; |
4023 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; | |
29134980 OF |
4024 | |
4025 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4026 | switch (info.byte_order) | |
4027 | { | |
778eb05e | 4028 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4029 | /* Ok. */ |
4030 | break; | |
4031 | ||
d7449b42 | 4032 | case BFD_ENDIAN_BIG: |
29134980 OF |
4033 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); |
4034 | break; | |
4035 | ||
4036 | default: | |
4037 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); | |
4038 | } | |
4039 | ||
b4206d25 | 4040 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4041 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4042 | cris_reg_struct_has_addr); | |
b5622e8d | 4043 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4044 | |
29134980 | 4045 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4046 | |
4047 | /* Length of ordinary registers used in push_word and a few other | |
4048 | places. register_size() is the real way to know how big a | |
4049 | register is. */ | |
a5f6c8f5 | 4050 | |
2e4b5889 OF |
4051 | set_gdbarch_double_bit (gdbarch, 64); |
4052 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
4053 | which means we have to set this explicitly. */ | |
c600d464 | 4054 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4055 | |
29134980 OF |
4056 | /* The total amount of space needed to store (in an array called registers) |
4057 | GDB's copy of the machine's register state. Note: We can not use | |
4058 | cris_register_size at this point, since it relies on current_gdbarch | |
4059 | being set. */ | |
4060 | switch (tdep->cris_version) | |
4061 | { | |
4062 | case 0: | |
4063 | case 1: | |
4064 | case 2: | |
4065 | case 3: | |
29134980 OF |
4066 | case 8: |
4067 | case 9: | |
a5f6c8f5 OF |
4068 | /* Old versions; not supported. */ |
4069 | internal_error (__FILE__, __LINE__, | |
4070 | "cris_gdbarch_init: unsupported CRIS version"); | |
29134980 OF |
4071 | break; |
4072 | ||
4073 | case 10: | |
4074 | case 11: | |
4075 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4076 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4077 | set_gdbarch_pc_regnum (gdbarch, 15); |
4078 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4079 | /* There are 32 registers (some of which may not be implemented). */ | |
4080 | set_gdbarch_num_regs (gdbarch, 32); | |
4081 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4082 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4083 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4084 | ||
4085 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4086 | break; | |
4087 | ||
4088 | case 32: | |
4089 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4090 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4091 | and pseudo-register PC (32 bits). */ | |
4092 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4093 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4094 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4095 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4096 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4097 | ||
4098 | set_gdbarch_cannot_store_register | |
4099 | (gdbarch, crisv32_cannot_store_register); | |
4100 | set_gdbarch_cannot_fetch_register | |
4101 | (gdbarch, crisv32_cannot_fetch_register); | |
4102 | ||
4103 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4104 | ||
4105 | set_gdbarch_single_step_through_delay | |
4106 | (gdbarch, crisv32_single_step_through_delay); | |
4107 | ||
29134980 OF |
4108 | break; |
4109 | ||
4110 | default: | |
c600d464 OF |
4111 | internal_error (__FILE__, __LINE__, |
4112 | "cris_gdbarch_init: unknown CRIS version"); | |
29134980 OF |
4113 | } |
4114 | ||
c600d464 OF |
4115 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4116 | have the same ABI). */ | |
2e4b5889 OF |
4117 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4118 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4119 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4120 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4121 | |
4122 | /* The stack grows downward. */ | |
4123 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4124 | ||
4125 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4126 | ||
2e4b5889 OF |
4127 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4128 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4129 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4130 | ||
a5f6c8f5 OF |
4131 | if (tdep->cris_dwarf2_cfi == 1) |
4132 | { | |
4133 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4134 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4135 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4136 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4137 | } | |
4138 | ||
4139 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4140 | ||
2e4b5889 OF |
4141 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4142 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4143 | |
dbbff683 OF |
4144 | /* Use target_specific function to define link map offsets. */ |
4145 | set_solib_svr4_fetch_link_map_offsets | |
4146 | (gdbarch, cris_linux_svr4_fetch_link_map_offsets); | |
4147 | ||
36482093 AC |
4148 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4149 | disassembler, even when there is no BFD. Does something like | |
4150 | "gdb; target remote; disassmeble *0x123" work? */ | |
4151 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4152 | ||
29134980 OF |
4153 | return gdbarch; |
4154 | } |