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29134980 OF |
1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
2 | Copyright 2001 Free Software Foundation, Inc. | |
3 | Contributed by Axis Communications AB. | |
4 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "symtab.h" | |
25 | #include "inferior.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcore.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "target.h" | |
30 | #include "value.h" | |
31 | #include "opcode/cris.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | ||
35 | /* To get entry_point_address. */ | |
36 | #include "symfile.h" | |
37 | ||
38 | enum cris_num_regs | |
39 | { | |
40 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
41 | NUM_FREGS = 0, | |
42 | ||
43 | /* There are 16 general registers. */ | |
44 | NUM_GENREGS = 16, | |
45 | ||
46 | /* There are 16 special registers. */ | |
47 | NUM_SPECREGS = 16 | |
48 | }; | |
49 | ||
50 | /* Register numbers of various important registers. | |
51 | FP_REGNUM Contains address of executing stack frame. | |
52 | STR_REGNUM Contains the address of structure return values. | |
53 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
54 | ARG1_REGNUM Contains the first parameter to a function. | |
55 | ARG2_REGNUM Contains the second parameter to a function. | |
56 | ARG3_REGNUM Contains the third parameter to a function. | |
57 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
58 | SP_REGNUM Contains address of top of stack. | |
59 | PC_REGNUM Contains address of next instruction. | |
60 | SRP_REGNUM Subroutine return pointer register. | |
61 | BRP_REGNUM Breakpoint return pointer register. */ | |
62 | ||
63 | /* FP_REGNUM = 8, SP_REGNUM = 14, and PC_REGNUM = 15 have been incorporated | |
64 | into the multi-arch framework. */ | |
65 | ||
66 | enum cris_regnums | |
67 | { | |
68 | /* Enums with respect to the general registers, valid for all | |
69 | CRIS versions. */ | |
70 | STR_REGNUM = 9, | |
71 | RET_REGNUM = 10, | |
72 | ARG1_REGNUM = 10, | |
73 | ARG2_REGNUM = 11, | |
74 | ARG3_REGNUM = 12, | |
75 | ARG4_REGNUM = 13, | |
76 | ||
77 | /* Enums with respect to the special registers, some of which may not be | |
78 | applicable to all CRIS versions. */ | |
79 | P0_REGNUM = 16, | |
80 | VR_REGNUM = 17, | |
81 | P2_REGNUM = 18, | |
82 | P3_REGNUM = 19, | |
83 | P4_REGNUM = 20, | |
84 | CCR_REGNUM = 21, | |
85 | MOF_REGNUM = 23, | |
86 | P8_REGNUM = 24, | |
87 | IBR_REGNUM = 25, | |
88 | IRP_REGNUM = 26, | |
89 | SRP_REGNUM = 27, | |
90 | BAR_REGNUM = 28, | |
91 | BRP_REGNUM = 30, | |
92 | USP_REGNUM = 31 | |
93 | }; | |
94 | ||
95 | extern const struct cris_spec_reg cris_spec_regs[]; | |
96 | ||
97 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
98 | register names and sizes.*/ | |
99 | static int usr_cmd_cris_version; | |
100 | ||
101 | /* Indicates whether to trust the above variable. */ | |
102 | static int usr_cmd_cris_version_valid = 0; | |
103 | ||
104 | /* CRIS mode, set via the user command 'set cris-mode'. Affects availability | |
105 | of some registers. */ | |
106 | static const char *usr_cmd_cris_mode; | |
107 | ||
108 | /* Indicates whether to trust the above variable. */ | |
109 | static int usr_cmd_cris_mode_valid = 0; | |
110 | ||
111 | static const char CRIS_MODE_USER[] = "CRIS_MODE_USER"; | |
112 | static const char CRIS_MODE_SUPERVISOR[] = "CRIS_MODE_SUPERVISOR"; | |
113 | static const char *cris_mode_enums[] = | |
114 | { | |
115 | CRIS_MODE_USER, | |
116 | CRIS_MODE_SUPERVISOR, | |
117 | 0 | |
118 | }; | |
119 | ||
120 | /* CRIS ABI, set via the user command 'set cris-abi'. | |
121 | There are two flavours: | |
122 | 1. Original ABI with 32-bit doubles, where arguments <= 4 bytes are | |
123 | passed by value. | |
124 | 2. New ABI with 64-bit doubles, where arguments <= 8 bytes are passed by | |
125 | value. */ | |
126 | static const char *usr_cmd_cris_abi; | |
127 | ||
128 | /* Indicates whether to trust the above variable. */ | |
129 | static int usr_cmd_cris_abi_valid = 0; | |
130 | ||
131 | /* These variables are strings instead of enums to make them usable as | |
132 | parameters to add_set_enum_cmd. */ | |
133 | static const char CRIS_ABI_ORIGINAL[] = "CRIS_ABI_ORIGINAL"; | |
134 | static const char CRIS_ABI_V2[] = "CRIS_ABI_V2"; | |
135 | static const char CRIS_ABI_SYMBOL[] = ".$CRIS_ABI_V2"; | |
136 | static const char *cris_abi_enums[] = | |
137 | { | |
138 | CRIS_ABI_ORIGINAL, | |
139 | CRIS_ABI_V2, | |
140 | 0 | |
141 | }; | |
142 | ||
143 | /* CRIS architecture specific information. */ | |
144 | struct gdbarch_tdep | |
145 | { | |
146 | int cris_version; | |
147 | const char *cris_mode; | |
148 | const char *cris_abi; | |
149 | }; | |
150 | ||
151 | /* Functions for accessing target dependent data. */ | |
152 | ||
153 | static int | |
154 | cris_version (void) | |
155 | { | |
156 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
157 | } | |
158 | ||
159 | static const char * | |
160 | cris_mode (void) | |
161 | { | |
162 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
163 | } | |
164 | ||
165 | static const char * | |
166 | cris_abi (void) | |
167 | { | |
168 | return (gdbarch_tdep (current_gdbarch)->cris_abi); | |
169 | } | |
170 | ||
171 | /* For saving call-clobbered contents in R9 when returning structs. */ | |
172 | static CORE_ADDR struct_return_address; | |
173 | ||
174 | struct frame_extra_info | |
175 | { | |
176 | CORE_ADDR return_pc; | |
177 | int leaf_function; | |
178 | }; | |
179 | ||
180 | /* The instruction environment needed to find single-step breakpoints. */ | |
181 | typedef | |
182 | struct instruction_environment | |
183 | { | |
184 | unsigned long reg[NUM_GENREGS]; | |
185 | unsigned long preg[NUM_SPECREGS]; | |
186 | unsigned long branch_break_address; | |
187 | unsigned long delay_slot_pc; | |
188 | unsigned long prefix_value; | |
189 | int branch_found; | |
190 | int prefix_found; | |
191 | int invalid; | |
192 | int slot_needed; | |
193 | int delay_slot_pc_active; | |
194 | int xflag_found; | |
195 | int disable_interrupt; | |
196 | } inst_env_type; | |
197 | ||
198 | /* Save old breakpoints in order to restore the state before a single_step. | |
199 | At most, two breakpoints will have to be remembered. */ | |
200 | typedef | |
201 | char binsn_quantum[BREAKPOINT_MAX]; | |
202 | static binsn_quantum break_mem[2]; | |
203 | static CORE_ADDR next_pc = 0; | |
204 | static CORE_ADDR branch_target_address = 0; | |
205 | static unsigned char branch_break_inserted = 0; | |
206 | ||
207 | /* Machine-dependencies in CRIS for opcodes. */ | |
208 | ||
209 | /* Instruction sizes. */ | |
210 | enum cris_instruction_sizes | |
211 | { | |
212 | INST_BYTE_SIZE = 0, | |
213 | INST_WORD_SIZE = 1, | |
214 | INST_DWORD_SIZE = 2 | |
215 | }; | |
216 | ||
217 | /* Addressing modes. */ | |
218 | enum cris_addressing_modes | |
219 | { | |
220 | REGISTER_MODE = 1, | |
221 | INDIRECT_MODE = 2, | |
222 | AUTOINC_MODE = 3 | |
223 | }; | |
224 | ||
225 | /* Prefix addressing modes. */ | |
226 | enum cris_prefix_addressing_modes | |
227 | { | |
228 | PREFIX_INDEX_MODE = 2, | |
229 | PREFIX_ASSIGN_MODE = 3, | |
230 | ||
231 | /* Handle immediate byte offset addressing mode prefix format. */ | |
232 | PREFIX_OFFSET_MODE = 2 | |
233 | }; | |
234 | ||
235 | /* Masks for opcodes. */ | |
236 | enum cris_opcode_masks | |
237 | { | |
238 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
239 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
240 | SIGNED_BYTE_MASK = 0x80, | |
241 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
242 | SIGNED_WORD_MASK = 0x8000, | |
243 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
244 | SIGNED_DWORD_MASK = 0x80000000, | |
245 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
246 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
247 | }; | |
248 | ||
249 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
250 | Bit 15 - 12 Operand2 | |
251 | 11 - 10 Mode | |
252 | 9 - 6 Opcode | |
253 | 5 - 4 Size | |
254 | 3 - 0 Operand1 */ | |
255 | ||
256 | static int | |
257 | cris_get_operand2 (unsigned short insn) | |
258 | { | |
259 | return ((insn & 0xF000) >> 12); | |
260 | } | |
261 | ||
262 | static int | |
263 | cris_get_mode (unsigned short insn) | |
264 | { | |
265 | return ((insn & 0x0C00) >> 10); | |
266 | } | |
267 | ||
268 | static int | |
269 | cris_get_opcode (unsigned short insn) | |
270 | { | |
271 | return ((insn & 0x03C0) >> 6); | |
272 | } | |
273 | ||
274 | static int | |
275 | cris_get_size (unsigned short insn) | |
276 | { | |
277 | return ((insn & 0x0030) >> 4); | |
278 | } | |
279 | ||
280 | static int | |
281 | cris_get_operand1 (unsigned short insn) | |
282 | { | |
283 | return (insn & 0x000F); | |
284 | } | |
285 | ||
286 | /* Additional functions in order to handle opcodes. */ | |
287 | ||
288 | static int | |
289 | cris_get_wide_opcode (unsigned short insn) | |
290 | { | |
291 | return ((insn & 0x03E0) >> 5); | |
292 | } | |
293 | ||
294 | static int | |
295 | cris_get_short_size (unsigned short insn) | |
296 | { | |
297 | return ((insn & 0x0010) >> 4); | |
298 | } | |
299 | ||
300 | static int | |
301 | cris_get_quick_value (unsigned short insn) | |
302 | { | |
303 | return (insn & 0x003F); | |
304 | } | |
305 | ||
306 | static int | |
307 | cris_get_bdap_quick_offset (unsigned short insn) | |
308 | { | |
309 | return (insn & 0x00FF); | |
310 | } | |
311 | ||
312 | static int | |
313 | cris_get_branch_short_offset (unsigned short insn) | |
314 | { | |
315 | return (insn & 0x00FF); | |
316 | } | |
317 | ||
318 | static int | |
319 | cris_get_asr_shift_steps (unsigned long value) | |
320 | { | |
321 | return (value & 0x3F); | |
322 | } | |
323 | ||
324 | static int | |
325 | cris_get_asr_quick_shift_steps (unsigned short insn) | |
326 | { | |
327 | return (insn & 0x1F); | |
328 | } | |
329 | ||
330 | static int | |
331 | cris_get_clear_size (unsigned short insn) | |
332 | { | |
333 | return ((insn) & 0xC000); | |
334 | } | |
335 | ||
336 | static int | |
337 | cris_is_signed_extend_bit_on (unsigned short insn) | |
338 | { | |
339 | return (((insn) & 0x20) == 0x20); | |
340 | } | |
341 | ||
342 | static int | |
343 | cris_is_xflag_bit_on (unsigned short insn) | |
344 | { | |
345 | return (((insn) & 0x1000) == 0x1000); | |
346 | } | |
347 | ||
348 | static void | |
349 | cris_set_size_to_dword (unsigned short *insn) | |
350 | { | |
351 | *insn &= 0xFFCF; | |
352 | *insn |= 0x20; | |
353 | } | |
354 | ||
8535cb38 | 355 | static signed char |
29134980 OF |
356 | cris_get_signed_offset (unsigned short insn) |
357 | { | |
8535cb38 | 358 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
359 | } |
360 | ||
361 | /* Calls an op function given the op-type, working on the insn and the | |
362 | inst_env. */ | |
363 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
364 | ||
365 | static CORE_ADDR cris_skip_prologue_main (CORE_ADDR pc, int frameless_p); | |
366 | ||
367 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, | |
368 | struct gdbarch_list *); | |
369 | ||
370 | static int cris_delayed_get_disassembler (bfd_vma, disassemble_info *); | |
371 | ||
372 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); | |
373 | ||
374 | static void cris_version_update (char *ignore_args, int from_tty, | |
375 | struct cmd_list_element *c); | |
376 | ||
377 | static void cris_mode_update (char *ignore_args, int from_tty, | |
378 | struct cmd_list_element *c); | |
379 | ||
380 | static void cris_abi_update (char *ignore_args, int from_tty, | |
381 | struct cmd_list_element *c); | |
382 | ||
383 | static CORE_ADDR bfd_lookup_symbol (bfd *, const char *); | |
384 | ||
385 | /* Frames information. The definition of the struct frame_info is | |
386 | ||
387 | CORE_ADDR frame | |
388 | CORE_ADDR pc | |
389 | int signal_handler_caller | |
390 | CORE_ADDR return_pc | |
391 | int leaf_function | |
392 | ||
393 | If the compilation option -fno-omit-frame-pointer is present the | |
394 | variable frame will be set to the content of R8 which is the frame | |
395 | pointer register. | |
396 | ||
397 | The variable pc contains the address where execution is performed | |
398 | in the present frame. The innermost frame contains the current content | |
399 | of the register PC. All other frames contain the content of the | |
400 | register PC in the next frame. | |
401 | ||
402 | The variable signal_handler_caller is non-zero when the frame is | |
403 | associated with the call of a signal handler. | |
404 | ||
405 | The variable return_pc contains the address where execution should be | |
406 | resumed when the present frame has finished, the return address. | |
407 | ||
408 | The variable leaf_function is 1 if the return address is in the register | |
409 | SRP, and 0 if it is on the stack. | |
410 | ||
411 | Prologue instructions C-code. | |
412 | The prologue may consist of (-fno-omit-frame-pointer) | |
413 | 1) 2) | |
414 | push srp | |
415 | push r8 push r8 | |
416 | move.d sp,r8 move.d sp,r8 | |
417 | subq X,sp subq X,sp | |
418 | movem rY,[sp] movem rY,[sp] | |
419 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
420 | ||
421 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
422 | ||
423 | Note that this assumption is extremely brittle, and will break at the | |
424 | slightest change in GCC's prologue. | |
425 | ||
426 | If local variables are declared or register contents are saved on stack | |
427 | the subq-instruction will be present with X as the number of bytes | |
428 | needed for storage. The reshuffle with respect to r8 may be performed | |
429 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
430 | The offset U should be representable by a signed 8-bit value in all cases. | |
431 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
432 | by another word containing the instruction. | |
433 | ||
434 | Degenerate cases: | |
435 | 3) | |
436 | push r8 | |
437 | move.d sp,r8 | |
438 | move.d r8,sp | |
439 | pop r8 | |
440 | ||
441 | Prologue instructions C++-code. | |
442 | Case 1) and 2) in the C-code may be followed by | |
443 | ||
444 | move.d r10,rS ; this | |
445 | move.d r11,rT ; P1 | |
446 | move.d r12,rU ; P2 | |
447 | move.d r13,rV ; P3 | |
448 | move.S [r8+U],rZ ; P4 | |
449 | ||
450 | if any of the call parameters are stored. The host expects these | |
451 | instructions to be executed in order to get the call parameters right. */ | |
452 | ||
453 | /* Examine the prologue of a function. The variable ip is the address of | |
454 | the first instruction of the prologue. The variable limit is the address | |
455 | of the first instruction after the prologue. The variable fi contains the | |
456 | information in struct frame_info. The variable frameless_p controls whether | |
457 | the entire prologue is examined (0) or just enough instructions to | |
458 | determine that it is a prologue (1). */ | |
459 | ||
460 | CORE_ADDR | |
461 | cris_examine (CORE_ADDR ip, CORE_ADDR limit, struct frame_info *fi, | |
462 | int frameless_p) | |
463 | { | |
464 | /* Present instruction. */ | |
465 | unsigned short insn; | |
466 | ||
467 | /* Next instruction, lookahead. */ | |
468 | unsigned short insn_next; | |
469 | int regno; | |
470 | ||
471 | /* Is there a push fp? */ | |
472 | int have_fp; | |
473 | ||
474 | /* Number of byte on stack used for local variables and movem. */ | |
475 | int val; | |
476 | ||
477 | /* Highest register number in a movem. */ | |
478 | int regsave; | |
479 | ||
480 | /* move.d r<source_register>,rS */ | |
481 | short source_register; | |
482 | ||
483 | /* This frame is with respect to a leaf until a push srp is found. */ | |
484 | fi->extra_info->leaf_function = 1; | |
485 | ||
486 | /* This frame is without the FP until a push fp is found. */ | |
487 | have_fp = 0; | |
488 | ||
489 | /* Assume nothing on stack. */ | |
490 | val = 0; | |
491 | regsave = -1; | |
492 | ||
493 | /* No information about register contents so far. */ | |
494 | ||
495 | /* We only want to know the end of the prologue when fi->saved_regs == 0. | |
496 | When the saved registers are allocated full information is required. */ | |
497 | if (fi->saved_regs) | |
498 | { | |
499 | for (regno = 0; regno < NUM_REGS; regno++) | |
500 | fi->saved_regs[regno] = 0; | |
501 | } | |
502 | ||
503 | /* Find the prologue instructions. */ | |
504 | do | |
505 | { | |
506 | insn = read_memory_unsigned_integer (ip, sizeof (short)); | |
507 | ip += sizeof (short); | |
508 | if (insn == 0xE1FC) | |
509 | { | |
510 | /* push <reg> 32 bit instruction */ | |
511 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
512 | ip += sizeof (short); | |
513 | regno = cris_get_operand2 (insn_next); | |
514 | if (regno == (SRP_REGNUM - NUM_GENREGS)) | |
515 | { | |
516 | if (frameless_p) | |
517 | { | |
518 | return ip; | |
519 | } | |
520 | fi->extra_info->leaf_function = 0; | |
521 | } | |
522 | else if (regno == FP_REGNUM) | |
523 | { | |
524 | have_fp = 1; | |
525 | } | |
526 | } | |
527 | else if (insn == 0x866E) | |
528 | { | |
529 | /* move.d sp,r8 */ | |
530 | if (frameless_p) | |
531 | { | |
532 | return ip; | |
533 | } | |
534 | continue; | |
535 | } | |
536 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
537 | && cris_get_mode (insn) == 0x0000 | |
538 | && cris_get_opcode (insn) == 0x000A) | |
539 | { | |
540 | /* subq <val>,sp */ | |
541 | val = cris_get_quick_value (insn); | |
542 | } | |
543 | else if (cris_get_mode (insn) == 0x0002 | |
544 | && cris_get_opcode (insn) == 0x000F | |
545 | && cris_get_size (insn) == 0x0003 | |
546 | && cris_get_operand1 (insn) == SP_REGNUM) | |
547 | { | |
548 | /* movem r<regsave>,[sp] */ | |
549 | if (frameless_p) | |
550 | { | |
551 | return ip; | |
552 | } | |
553 | regsave = cris_get_operand2 (insn); | |
554 | } | |
555 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
556 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
557 | && (cris_get_signed_offset (insn) < 0)) | |
558 | { | |
559 | /* Immediate byte offset addressing prefix word with sp as base | |
560 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
561 | is between 64 and 128. | |
562 | movem r<regsave>,[sp=sp-<val>] */ | |
563 | val = -cris_get_signed_offset (insn); | |
564 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
565 | ip += sizeof (short); | |
566 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE | |
567 | && cris_get_opcode (insn_next) == 0x000F | |
568 | && cris_get_size (insn_next) == 0x0003 | |
569 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
570 | { | |
571 | if (frameless_p) | |
572 | { | |
573 | return ip; | |
574 | } | |
575 | regsave = cris_get_operand2 (insn_next); | |
576 | } | |
577 | else | |
578 | { | |
579 | /* The prologue ended before the limit was reached. */ | |
580 | ip -= 2 * sizeof (short); | |
581 | break; | |
582 | } | |
583 | } | |
584 | else if (cris_get_mode (insn) == 0x0001 | |
585 | && cris_get_opcode (insn) == 0x0009 | |
586 | && cris_get_size (insn) == 0x0002) | |
587 | { | |
588 | /* move.d r<10..13>,r<0..15> */ | |
589 | if (frameless_p) | |
590 | { | |
591 | return ip; | |
592 | } | |
593 | source_register = cris_get_operand1 (insn); | |
594 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) | |
595 | { | |
596 | /* The prologue ended before the limit was reached. */ | |
597 | ip -= sizeof (short); | |
598 | break; | |
599 | } | |
600 | } | |
601 | else if (cris_get_operand2 (insn) == FP_REGNUM | |
602 | /* The size is a fixed-size. */ | |
603 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
604 | /* A negative offset. */ | |
605 | && (cris_get_signed_offset (insn) < 0)) | |
606 | { | |
607 | /* move.S rZ,[r8-U] (?) */ | |
608 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
609 | ip += sizeof (short); | |
610 | regno = cris_get_operand2 (insn_next); | |
611 | if ((regno >= 0 && regno < SP_REGNUM) | |
612 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
613 | && cris_get_opcode (insn_next) == 0x000F) | |
614 | { | |
615 | /* move.S rZ,[r8-U] */ | |
616 | continue; | |
617 | } | |
618 | else | |
619 | { | |
620 | /* The prologue ended before the limit was reached. */ | |
621 | ip -= 2 * sizeof (short); | |
622 | break; | |
623 | } | |
624 | } | |
625 | else if (cris_get_operand2 (insn) == FP_REGNUM | |
626 | /* The size is a fixed-size. */ | |
627 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
628 | /* A positive offset. */ | |
629 | && (cris_get_signed_offset (insn) > 0)) | |
630 | { | |
631 | /* move.S [r8+U],rZ (?) */ | |
632 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
633 | ip += sizeof (short); | |
634 | regno = cris_get_operand2 (insn_next); | |
635 | if ((regno >= 0 && regno < SP_REGNUM) | |
636 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
637 | && cris_get_opcode (insn_next) == 0x0009 | |
638 | && cris_get_operand1 (insn_next) == regno) | |
639 | { | |
640 | /* move.S [r8+U],rZ */ | |
641 | continue; | |
642 | } | |
643 | else | |
644 | { | |
645 | /* The prologue ended before the limit was reached. */ | |
646 | ip -= 2 * sizeof (short); | |
647 | break; | |
648 | } | |
649 | } | |
650 | else | |
651 | { | |
652 | /* The prologue ended before the limit was reached. */ | |
653 | ip -= sizeof (short); | |
654 | break; | |
655 | } | |
656 | } | |
657 | while (ip < limit); | |
658 | ||
659 | /* We only want to know the end of the prologue when | |
660 | fi->saved_regs == 0. */ | |
661 | if (!fi->saved_regs) | |
662 | return ip; | |
663 | ||
664 | if (have_fp) | |
665 | { | |
666 | fi->saved_regs[FP_REGNUM] = FRAME_FP (fi); | |
667 | ||
668 | /* Calculate the addresses. */ | |
669 | for (regno = regsave; regno >= 0; regno--) | |
670 | { | |
671 | fi->saved_regs[regno] = FRAME_FP (fi) - val; | |
672 | val -= 4; | |
673 | } | |
674 | if (fi->extra_info->leaf_function) | |
675 | { | |
676 | /* Set the register SP to contain the stack pointer of | |
677 | the caller. */ | |
678 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 4; | |
679 | } | |
680 | else | |
681 | { | |
682 | /* Set the register SP to contain the stack pointer of | |
683 | the caller. */ | |
684 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 8; | |
685 | ||
686 | /* Set the register SRP to contain the return address of | |
687 | the caller. */ | |
688 | fi->saved_regs[SRP_REGNUM] = FRAME_FP (fi) + 4; | |
689 | } | |
690 | } | |
691 | return ip; | |
692 | } | |
693 | ||
694 | /* Advance pc beyond any function entry prologue instructions at pc | |
695 | to reach some "real" code. */ | |
696 | ||
697 | CORE_ADDR | |
698 | cris_skip_prologue (CORE_ADDR pc) | |
699 | { | |
700 | return cris_skip_prologue_main (pc, 0); | |
701 | } | |
702 | ||
703 | /* As cris_skip_prologue, but stops as soon as it knows that the function | |
704 | has a frame. Its result is equal to its input pc if the function is | |
705 | frameless, unequal otherwise. */ | |
706 | ||
707 | CORE_ADDR | |
708 | cris_skip_prologue_frameless_p (CORE_ADDR pc) | |
709 | { | |
710 | return cris_skip_prologue_main (pc, 1); | |
711 | } | |
712 | ||
713 | /* Given a PC value corresponding to the start of a function, return the PC | |
714 | of the first instruction after the function prologue. */ | |
715 | ||
716 | CORE_ADDR | |
717 | cris_skip_prologue_main (CORE_ADDR pc, int frameless_p) | |
718 | { | |
719 | struct frame_info fi; | |
720 | static struct frame_extra_info fei; | |
721 | struct symtab_and_line sal = find_pc_line (pc, 0); | |
722 | int best_limit; | |
723 | CORE_ADDR pc_after_prologue; | |
724 | ||
725 | /* frame_info now contains dynamic memory. Since fi is a dummy here, | |
726 | I use static memory for extra_info, and don't bother allocating | |
727 | memory for saved_regs. */ | |
728 | fi.saved_regs = 0; | |
729 | fi.extra_info = &fei; | |
730 | ||
731 | /* If there is no symbol information then sal.end == 0, and we end up | |
732 | examining only the first instruction in the function prologue. | |
733 | Exaggerating the limit seems to be harmless. */ | |
734 | if (sal.end > 0) | |
735 | best_limit = sal.end; | |
736 | else | |
737 | best_limit = pc + 100; | |
738 | ||
739 | pc_after_prologue = cris_examine (pc, best_limit, &fi, frameless_p); | |
740 | return pc_after_prologue; | |
741 | } | |
742 | ||
743 | /* Use the program counter to determine the contents and size of a breakpoint | |
744 | instruction. It returns a pointer to a string of bytes that encode a | |
745 | breakpoint instruction, stores the length of the string to *lenptr, and | |
746 | adjusts pcptr (if necessary) to point to the actual memory location where | |
747 | the breakpoint should be inserted. */ | |
748 | ||
749 | unsigned char * | |
750 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
751 | { | |
752 | static unsigned char break_insn[] = {0x38, 0xe9}; | |
753 | *lenptr = 2; | |
754 | ||
755 | return break_insn; | |
756 | } | |
757 | ||
758 | /* Returns the register SRP (subroutine return pointer) which must contain | |
759 | the content of the register PC after a function call. */ | |
760 | ||
761 | CORE_ADDR | |
762 | cris_saved_pc_after_call () | |
763 | { | |
764 | return read_register (SRP_REGNUM); | |
765 | } | |
766 | ||
767 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, | |
768 | 0 otherwise. */ | |
769 | ||
770 | int | |
771 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) | |
772 | { | |
773 | int version = cris_version (); | |
774 | ||
775 | switch (spec_reg.applicable_version) | |
776 | { | |
777 | case cris_ver_version_all: | |
778 | return 1; | |
779 | case cris_ver_warning: | |
780 | /* Indeterminate/obsolete. */ | |
781 | return 0; | |
782 | case cris_ver_sim: | |
783 | /* Simulator only. */ | |
784 | return 0; | |
785 | case cris_ver_v0_3: | |
786 | return (version >= 0 && version <= 3); | |
787 | case cris_ver_v3p: | |
788 | return (version >= 3); | |
789 | case cris_ver_v8: | |
790 | return (version == 8 || version == 9); | |
791 | case cris_ver_v8p: | |
792 | return (version >= 8); | |
793 | case cris_ver_v10p: | |
794 | return (version >= 10); | |
795 | default: | |
796 | /* Invalid cris version. */ | |
797 | return 0; | |
798 | } | |
799 | } | |
800 | ||
801 | /* Returns the register size in unit byte. Returns 0 for an unimplemented | |
802 | register, -1 for an invalid register. */ | |
803 | ||
804 | int | |
805 | cris_register_size (int regno) | |
806 | { | |
807 | int i; | |
808 | int spec_regno; | |
809 | ||
810 | if (regno >= 0 && regno < NUM_GENREGS) | |
811 | { | |
812 | /* General registers (R0 - R15) are 32 bits. */ | |
813 | return 4; | |
814 | } | |
815 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) | |
816 | { | |
817 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
818 | Adjust regno accordingly. */ | |
819 | spec_regno = regno - NUM_GENREGS; | |
820 | ||
821 | /* The entries in cris_spec_regs are stored in register number order, | |
822 | which means we can shortcut into the array when searching it. */ | |
823 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
824 | { | |
825 | if (cris_spec_regs[i].number == spec_regno | |
826 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
827 | /* Go with the first applicable register. */ | |
828 | return cris_spec_regs[i].reg_size; | |
829 | } | |
830 | /* Special register not applicable to this CRIS version. */ | |
831 | return 0; | |
832 | } | |
833 | else | |
834 | { | |
835 | /* Invalid register. */ | |
836 | return -1; | |
837 | } | |
838 | } | |
839 | ||
840 | /* Nonzero if regno should not be fetched from the target. This is the case | |
841 | for unimplemented (size 0) and non-existant registers. */ | |
842 | ||
843 | int | |
844 | cris_cannot_fetch_register (int regno) | |
845 | { | |
846 | return ((regno < 0 || regno >= NUM_REGS) | |
847 | || (cris_register_size (regno) == 0)); | |
848 | } | |
849 | ||
850 | /* Nonzero if regno should not be written to the target, for various | |
851 | reasons. */ | |
852 | ||
853 | int | |
854 | cris_cannot_store_register (int regno) | |
855 | { | |
856 | /* There are three kinds of registers we refuse to write to. | |
857 | 1. Those that not implemented. | |
858 | 2. Those that are read-only (depends on the processor mode). | |
859 | 3. Those registers to which a write has no effect. | |
860 | */ | |
861 | ||
862 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
863 | /* Not implemented. */ | |
864 | return 1; | |
865 | ||
866 | else if (regno == VR_REGNUM) | |
867 | /* Read-only. */ | |
868 | return 1; | |
869 | ||
870 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
871 | /* Writing has no effect. */ | |
872 | return 1; | |
873 | ||
874 | else if (cris_mode () == CRIS_MODE_USER) | |
875 | { | |
876 | if (regno == IBR_REGNUM || regno == BAR_REGNUM || regno == BRP_REGNUM | |
877 | || regno == IRP_REGNUM) | |
878 | /* Read-only in user mode. */ | |
879 | return 1; | |
880 | } | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | /* Returns the register offset for the first byte of register regno's space | |
886 | in the saved register state. Returns -1 for an invalid or unimplemented | |
887 | register. */ | |
888 | ||
889 | int | |
890 | cris_register_offset (int regno) | |
891 | { | |
892 | int i; | |
893 | int reg_size; | |
894 | int offset = 0; | |
895 | ||
896 | if (regno >= 0 && regno < NUM_REGS) | |
897 | { | |
898 | /* FIXME: The offsets should be cached and calculated only once, | |
899 | when the architecture being debugged has changed. */ | |
900 | for (i = 0; i < regno; i++) | |
901 | offset += cris_register_size (i); | |
902 | ||
903 | return offset; | |
904 | } | |
905 | else | |
906 | { | |
907 | /* Invalid register. */ | |
908 | return -1; | |
909 | } | |
910 | } | |
911 | ||
912 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type | |
913 | of data in register regno. */ | |
914 | ||
915 | struct type * | |
916 | cris_register_virtual_type (int regno) | |
917 | { | |
918 | if (regno == SP_REGNUM || regno == PC_REGNUM | |
919 | || (regno > P8_REGNUM && regno < USP_REGNUM)) | |
920 | { | |
921 | /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */ | |
922 | return lookup_pointer_type (builtin_type_void); | |
923 | } | |
924 | else if (regno == P8_REGNUM || regno == USP_REGNUM | |
925 | || (regno >= 0 && regno < SP_REGNUM)) | |
926 | { | |
927 | /* R0 - R13, P8, P15 */ | |
928 | return builtin_type_unsigned_long; | |
929 | } | |
930 | else if (regno > P3_REGNUM && regno < P8_REGNUM) | |
931 | { | |
932 | /* P4, CCR, DCR0, DCR1 */ | |
933 | return builtin_type_unsigned_short; | |
934 | } | |
935 | else if (regno > PC_REGNUM && regno < P4_REGNUM) | |
936 | { | |
937 | /* P0, P1, P2, P3 */ | |
938 | return builtin_type_unsigned_char; | |
939 | } | |
940 | else | |
941 | { | |
942 | /* Invalid register. */ | |
943 | return builtin_type_void; | |
944 | } | |
945 | } | |
946 | ||
947 | /* Stores a function return value of type type, where valbuf is the address | |
948 | of the value to be stored. */ | |
949 | ||
950 | /* In the original CRIS ABI, R10 is used to store return values. */ | |
951 | ||
952 | void | |
953 | cris_abi_original_store_return_value (struct type *type, char *valbuf) | |
954 | { | |
955 | int len = TYPE_LENGTH (type); | |
956 | ||
957 | if (len <= REGISTER_SIZE) | |
958 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); | |
959 | else | |
960 | internal_error (__FILE__, __LINE__, "cris_abi_original_store_return_value: type length too large."); | |
961 | } | |
962 | ||
963 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ | |
964 | ||
965 | void | |
966 | cris_abi_v2_store_return_value (struct type *type, char *valbuf) | |
967 | { | |
968 | int len = TYPE_LENGTH (type); | |
969 | ||
970 | if (len <= 2 * REGISTER_SIZE) | |
971 | { | |
972 | /* Note that this works since R10 and R11 are consecutive registers. */ | |
973 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); | |
974 | } | |
975 | else | |
976 | internal_error (__FILE__, __LINE__, "cris_abi_v2_store_return_value: type length too large."); | |
977 | } | |
978 | ||
979 | /* Return the name of register regno as a string. Return NULL for an invalid or | |
980 | unimplemented register. */ | |
981 | ||
982 | char * | |
983 | cris_register_name (int regno) | |
984 | { | |
985 | static char *cris_genreg_names[] = | |
986 | { "r0", "r1", "r2", "r3", \ | |
987 | "r4", "r5", "r6", "r7", \ | |
988 | "r8", "r9", "r10", "r11", \ | |
989 | "r12", "r13", "sp", "pc" }; | |
990 | ||
991 | int i; | |
992 | int spec_regno; | |
993 | ||
994 | if (regno >= 0 && regno < NUM_GENREGS) | |
995 | { | |
996 | /* General register. */ | |
997 | return cris_genreg_names[regno]; | |
998 | } | |
999 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) | |
1000 | { | |
1001 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1002 | Adjust regno accordingly. */ | |
1003 | spec_regno = regno - NUM_GENREGS; | |
1004 | ||
1005 | /* The entries in cris_spec_regs are stored in register number order, | |
1006 | which means we can shortcut into the array when searching it. */ | |
1007 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
1008 | { | |
1009 | if (cris_spec_regs[i].number == spec_regno | |
1010 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1011 | /* Go with the first applicable register. */ | |
1012 | return cris_spec_regs[i].name; | |
1013 | } | |
1014 | /* Special register not applicable to this CRIS version. */ | |
1015 | return NULL; | |
1016 | } | |
1017 | else | |
1018 | { | |
1019 | /* Invalid register. */ | |
1020 | return NULL; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | int | |
1025 | cris_register_bytes_ok (long bytes) | |
1026 | { | |
1027 | return (bytes == REGISTER_BYTES); | |
1028 | } | |
1029 | ||
1030 | /* Extract from an array regbuf containing the raw register state a function | |
1031 | return value of type type, and copy that, in virtual format, into | |
1032 | valbuf. */ | |
1033 | ||
1034 | /* In the original CRIS ABI, R10 is used to return values. */ | |
1035 | ||
1036 | void | |
1037 | cris_abi_original_extract_return_value (struct type *type, char *regbuf, | |
1038 | char *valbuf) | |
1039 | { | |
1040 | int len = TYPE_LENGTH (type); | |
1041 | ||
1042 | if (len <= REGISTER_SIZE) | |
1043 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); | |
1044 | else | |
1045 | internal_error (__FILE__, __LINE__, "cris_abi_original_extract_return_value: type length too large"); | |
1046 | } | |
1047 | ||
1048 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ | |
1049 | ||
1050 | void | |
1051 | cris_abi_v2_extract_return_value (struct type *type, char *regbuf, | |
1052 | char *valbuf) | |
1053 | { | |
1054 | int len = TYPE_LENGTH (type); | |
1055 | ||
1056 | if (len <= 2 * REGISTER_SIZE) | |
1057 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); | |
1058 | else | |
1059 | internal_error (__FILE__, __LINE__, "cris_abi_v2_extract_return_value: type length too large"); | |
1060 | } | |
1061 | ||
1062 | /* Store the address of the place in which to copy the structure the | |
1063 | subroutine will return. In the CRIS ABI, R9 is used in order to pass | |
1064 | the address of the allocated area where a structure return value must | |
1065 | be stored. R9 is call-clobbered, which means we must save it here for | |
1066 | later use. */ | |
1067 | ||
1068 | void | |
1069 | cris_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1070 | { | |
1071 | write_register (STR_REGNUM, addr); | |
1072 | struct_return_address = addr; | |
1073 | } | |
1074 | ||
1075 | /* Extract from regbuf the address where a function should return a | |
1076 | structure value. It's not there in the CRIS ABI, so we must do it another | |
1077 | way. */ | |
1078 | ||
1079 | CORE_ADDR | |
1080 | cris_extract_struct_value_address (char *regbuf) | |
1081 | { | |
1082 | return struct_return_address; | |
1083 | } | |
1084 | ||
1085 | /* Returns 1 if a value of the given type being returned from a function | |
1086 | must have space allocated for it on the stack. gcc_p is true if the | |
1087 | function being considered is known to have been compiled by GCC. | |
1088 | In the CRIS ABI, structure return values are passed to the called | |
1089 | function by reference in register R9 to a caller-allocated area, so | |
1090 | this is always true. */ | |
1091 | ||
1092 | int | |
1093 | cris_use_struct_convention (int gcc_p, struct type *type) | |
1094 | { | |
1095 | return 1; | |
1096 | } | |
1097 | ||
1098 | /* Returns 1 if the given type will be passed by pointer rather than | |
1099 | directly. */ | |
1100 | ||
1101 | /* In the original CRIS ABI, arguments shorter than or equal to 32 bits are | |
1102 | passed by value. */ | |
1103 | ||
1104 | int | |
1105 | cris_abi_original_reg_struct_has_addr (int gcc_p, struct type *type) | |
1106 | { | |
1107 | return (TYPE_LENGTH (type) > 4); | |
1108 | } | |
1109 | ||
1110 | /* In the CRIS ABI V2, arguments shorter than or equal to 64 bits are passed | |
1111 | by value. */ | |
1112 | ||
1113 | int | |
1114 | cris_abi_v2_reg_struct_has_addr (int gcc_p, struct type *type) | |
1115 | { | |
1116 | return (TYPE_LENGTH (type) > 8); | |
1117 | } | |
1118 | ||
1119 | /* Returns 1 if the function invocation represented by fi does not have a | |
1120 | stack frame associated with it. Otherwise return 0. */ | |
1121 | ||
1122 | int | |
1123 | cris_frameless_function_invocation (struct frame_info *fi) | |
1124 | { | |
1125 | if (fi->signal_handler_caller) | |
1126 | return 0; | |
1127 | else | |
1128 | return frameless_look_for_prologue (fi); | |
1129 | } | |
1130 | ||
1131 | /* See frame.h. Determines the address of all registers in the current stack | |
1132 | frame storing each in frame->saved_regs. Space for frame->saved_regs shall | |
1133 | be allocated by FRAME_INIT_SAVED_REGS using either frame_saved_regs_zalloc | |
1134 | or frame_obstack_alloc. */ | |
1135 | ||
1136 | void | |
1137 | cris_frame_init_saved_regs (struct frame_info *fi) | |
1138 | { | |
1139 | CORE_ADDR ip; | |
1140 | struct symtab_and_line sal; | |
1141 | int best_limit; | |
1142 | char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); | |
1143 | ||
1144 | /* Examine the entire prologue. */ | |
1145 | register int frameless_p = 0; | |
1146 | ||
1147 | /* Has this frame's registers already been initialized? */ | |
1148 | if (fi->saved_regs) | |
1149 | return; | |
1150 | ||
1151 | frame_saved_regs_zalloc (fi); | |
1152 | ||
1153 | if (dummy_regs) | |
1154 | { | |
1155 | /* I don't see this ever happening, considering the context in which | |
1156 | cris_frame_init_saved_regs is called (always when we're not in | |
1157 | a dummy frame). */ | |
1158 | memcpy (&fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); | |
1159 | } | |
1160 | else | |
1161 | { | |
1162 | ip = get_pc_function_start (fi->pc); | |
1163 | sal = find_pc_line (ip, 0); | |
1164 | ||
1165 | /* If there is no symbol information then sal.end == 0, and we end up | |
1166 | examining only the first instruction in the function prologue. | |
1167 | Exaggerating the limit seems to be harmless. */ | |
1168 | if (sal.end > 0) | |
1169 | best_limit = sal.end; | |
1170 | else | |
1171 | best_limit = ip + 100; | |
1172 | ||
1173 | cris_examine (ip, best_limit, fi, frameless_p); | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | /* Initialises the extra frame information at the creation of a new frame. | |
1178 | The inparameter fromleaf is 0 when the call is from create_new_frame. | |
1179 | When the call is from get_prev_frame_info, fromleaf is determined by | |
1180 | cris_frameless_function_invocation. */ | |
1181 | ||
1182 | void | |
1183 | cris_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1184 | { | |
1185 | if (fi->next) | |
1186 | { | |
1187 | /* Called from get_prev_frame. */ | |
1188 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1189 | } | |
1190 | ||
1191 | fi->extra_info = (struct frame_extra_info *) | |
1192 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1193 | ||
1194 | fi->extra_info->return_pc = 0; | |
1195 | fi->extra_info->leaf_function = 0; | |
1196 | ||
1197 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1198 | { | |
1199 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
1200 | by assuming it's always FP. */ | |
1201 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
1202 | fi->extra_info->return_pc = | |
1203 | generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
1204 | ||
1205 | /* FIXME: Is this necessarily true? */ | |
1206 | fi->extra_info->leaf_function = 0; | |
1207 | } | |
1208 | else | |
1209 | { | |
1210 | cris_frame_init_saved_regs (fi); | |
1211 | ||
1212 | /* Check fromleaf/frameless_function_invocation. (FIXME) */ | |
1213 | ||
1214 | if (fi->saved_regs[SRP_REGNUM] != 0) | |
1215 | { | |
1216 | /* SRP was saved on the stack; non-leaf function. */ | |
1217 | fi->extra_info->return_pc = | |
1218 | read_memory_integer (fi->saved_regs[SRP_REGNUM], | |
1219 | REGISTER_RAW_SIZE (SRP_REGNUM)); | |
1220 | } | |
1221 | else | |
1222 | { | |
1223 | /* SRP is still in a register; leaf function. */ | |
1224 | fi->extra_info->return_pc = read_register (SRP_REGNUM); | |
1225 | /* FIXME: Should leaf_function be set to 1 here? */ | |
1226 | fi->extra_info->leaf_function = 1; | |
1227 | } | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | /* Return the content of the frame pointer in the present frame. In other | |
1232 | words, determine the address of the calling function's frame. */ | |
1233 | ||
1234 | CORE_ADDR | |
1235 | cris_frame_chain (struct frame_info *fi) | |
1236 | { | |
1237 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1238 | { | |
1239 | return fi->frame; | |
1240 | } | |
1241 | else if (!inside_entry_file (fi->pc)) | |
1242 | { | |
1243 | return read_memory_unsigned_integer (FRAME_FP (fi), 4); | |
1244 | } | |
1245 | else | |
1246 | { | |
1247 | return 0; | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | /* Return the saved PC (which equals the return address) of this frame. */ | |
1252 | ||
1253 | CORE_ADDR | |
1254 | cris_frame_saved_pc (struct frame_info *fi) | |
1255 | { | |
1256 | return fi->extra_info->return_pc; | |
1257 | } | |
1258 | ||
1259 | /* Return the address of the argument block for the frame described | |
1260 | by struct frame_info. */ | |
1261 | ||
1262 | CORE_ADDR | |
1263 | cris_frame_args_address (struct frame_info *fi) | |
1264 | { | |
1265 | return FRAME_FP (fi); | |
1266 | } | |
1267 | ||
1268 | /* Return the address of the locals block for the frame | |
1269 | described by struct frame_info. */ | |
1270 | ||
1271 | CORE_ADDR | |
1272 | cris_frame_locals_address (struct frame_info *fi) | |
1273 | { | |
1274 | return FRAME_FP (fi); | |
1275 | } | |
1276 | ||
1277 | /* Setup the function arguments for calling a function in the inferior. */ | |
1278 | ||
1279 | CORE_ADDR | |
1280 | cris_abi_original_push_arguments (int nargs, struct value **args, | |
1281 | CORE_ADDR sp, int struct_return, | |
1282 | CORE_ADDR struct_addr) | |
1283 | { | |
1284 | int stack_alloc; | |
1285 | int stack_offset; | |
1286 | int argreg; | |
1287 | int argnum; | |
1288 | struct type *type; | |
1289 | int len; | |
1290 | CORE_ADDR regval; | |
1291 | char *val; | |
1292 | ||
1293 | /* Data and parameters reside in different areas on the stack. | |
1294 | Both frame pointers grow toward higher addresses. */ | |
1295 | CORE_ADDR fp_params; | |
1296 | CORE_ADDR fp_data; | |
1297 | ||
1298 | /* Are we returning a value using a structure return or a normal value | |
1299 | return? struct_addr is the address of the reserved space for the return | |
1300 | structure to be written on the stack. */ | |
1301 | if (struct_return) | |
1302 | { | |
1303 | write_register (STR_REGNUM, struct_addr); | |
1304 | } | |
1305 | ||
1306 | /* Make sure there's space on the stack. Allocate space for data and a | |
1307 | parameter to refer to that data. */ | |
1308 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
1309 | stack_alloc += (TYPE_LENGTH (VALUE_TYPE (args[argnum])) + REGISTER_SIZE); | |
1310 | sp -= stack_alloc; | |
1311 | /* We may over-allocate a little here, but that won't hurt anything. */ | |
1312 | ||
1313 | /* Initialize stack frame pointers. */ | |
1314 | fp_params = sp; | |
1315 | fp_data = sp + (nargs * REGISTER_SIZE); | |
1316 | ||
1317 | /* Now load as many as possible of the first arguments into | |
1318 | registers, and push the rest onto the stack. */ | |
1319 | argreg = ARG1_REGNUM; | |
1320 | stack_offset = 0; | |
1321 | ||
1322 | for (argnum = 0; argnum < nargs; argnum++) | |
1323 | { | |
1324 | type = VALUE_TYPE (args[argnum]); | |
1325 | len = TYPE_LENGTH (type); | |
1326 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1327 | ||
1328 | if (len <= REGISTER_SIZE && argreg <= ARG4_REGNUM) | |
1329 | { | |
1330 | /* Data fits in a register; put it in the first available | |
1331 | register. */ | |
1332 | write_register (argreg, *(unsigned long *) val); | |
1333 | argreg++; | |
1334 | } | |
1335 | else if (len > REGISTER_SIZE && argreg <= ARG4_REGNUM) | |
1336 | { | |
1337 | /* Data does not fit in register; pass it on the stack and | |
1338 | put its address in the first available register. */ | |
1339 | write_memory (fp_data, val, len); | |
1340 | write_register (argreg, fp_data); | |
1341 | fp_data += len; | |
1342 | argreg++; | |
1343 | } | |
1344 | else if (len > REGISTER_SIZE) | |
1345 | { | |
1346 | /* Data does not fit in register; put both data and | |
1347 | parameter on the stack. */ | |
1348 | write_memory (fp_data, val, len); | |
1349 | write_memory (fp_params, (char *) (&fp_data), REGISTER_SIZE); | |
1350 | fp_data += len; | |
1351 | fp_params += REGISTER_SIZE; | |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | /* Data fits in a register, but we are out of registers; | |
1356 | put the parameter on the stack. */ | |
1357 | write_memory (fp_params, val, REGISTER_SIZE); | |
1358 | fp_params += REGISTER_SIZE; | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | return sp; | |
1363 | } | |
1364 | ||
1365 | CORE_ADDR | |
1366 | cris_abi_v2_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
1367 | int struct_return, CORE_ADDR struct_addr) | |
1368 | { | |
1369 | int stack_alloc; | |
1370 | int stack_offset; | |
1371 | int argreg; | |
1372 | int argnum; | |
1373 | ||
1374 | CORE_ADDR regval; | |
1375 | ||
1376 | /* The function's arguments and memory allocated by gdb for the arguments to | |
1377 | point at reside in separate areas on the stack. | |
1378 | Both frame pointers grow toward higher addresses. */ | |
1379 | CORE_ADDR fp_arg; | |
1380 | CORE_ADDR fp_mem; | |
1381 | ||
1382 | /* Are we returning a value using a structure return or a normal value | |
1383 | return? struct_addr is the address of the reserved space for the return | |
1384 | structure to be written on the stack. */ | |
1385 | if (struct_return) | |
1386 | { | |
1387 | write_register (STR_REGNUM, struct_addr); | |
1388 | } | |
1389 | ||
1390 | /* Allocate enough to keep things word-aligned on both parts of the | |
1391 | stack. */ | |
1392 | stack_alloc = 0; | |
1393 | for (argnum = 0; argnum < nargs; argnum++) | |
1394 | { | |
1395 | int len; | |
1396 | int reg_demand; | |
1397 | ||
1398 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); | |
1399 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); | |
1400 | ||
1401 | /* reg_demand * REGISTER_SIZE is the amount of memory we might need to | |
1402 | allocate for this argument. 2 * REGISTER_SIZE is the amount of stack | |
1403 | space we might need to pass the argument itself (either by value or by | |
1404 | reference). */ | |
1405 | stack_alloc += (reg_demand * REGISTER_SIZE + 2 * REGISTER_SIZE); | |
1406 | } | |
1407 | sp -= stack_alloc; | |
1408 | /* We may over-allocate a little here, but that won't hurt anything. */ | |
1409 | ||
1410 | /* Initialize frame pointers. */ | |
1411 | fp_arg = sp; | |
1412 | fp_mem = sp + (nargs * (2 * REGISTER_SIZE)); | |
1413 | ||
1414 | /* Now load as many as possible of the first arguments into registers, | |
1415 | and push the rest onto the stack. */ | |
1416 | argreg = ARG1_REGNUM; | |
1417 | stack_offset = 0; | |
1418 | ||
1419 | for (argnum = 0; argnum < nargs; argnum++) | |
1420 | { | |
1421 | int len; | |
1422 | char *val; | |
1423 | int reg_demand; | |
1424 | int i; | |
1425 | ||
1426 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); | |
1427 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1428 | ||
1429 | /* How may registers worth of storage do we need for this argument? */ | |
1430 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); | |
1431 | ||
1432 | if (len <= (2 * REGISTER_SIZE) | |
1433 | && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
1434 | { | |
1435 | /* Data passed by value. Fits in available register(s). */ | |
1436 | for (i = 0; i < reg_demand; i++) | |
1437 | { | |
1438 | write_register (argreg, *(unsigned long *) val); | |
1439 | argreg++; | |
1440 | val += REGISTER_SIZE; | |
1441 | } | |
1442 | } | |
1443 | else if (len <= (2 * REGISTER_SIZE) && argreg <= ARG4_REGNUM) | |
1444 | { | |
1445 | /* Data passed by value. Does not fit in available register(s). | |
1446 | Use the register(s) first, then the stack. */ | |
1447 | for (i = 0; i < reg_demand; i++) | |
1448 | { | |
1449 | if (argreg <= ARG4_REGNUM) | |
1450 | { | |
1451 | write_register (argreg, *(unsigned long *) val); | |
1452 | argreg++; | |
1453 | val += REGISTER_SIZE; | |
1454 | } | |
1455 | else | |
1456 | { | |
1457 | /* I guess this memory write could write the remaining data | |
1458 | all at once instead of in REGISTER_SIZE chunks. */ | |
1459 | write_memory (fp_arg, val, REGISTER_SIZE); | |
1460 | fp_arg += REGISTER_SIZE; | |
1461 | val += REGISTER_SIZE; | |
1462 | } | |
1463 | } | |
1464 | } | |
1465 | else if (len > (2 * REGISTER_SIZE)) | |
1466 | { | |
1467 | /* Data passed by reference. Put it on the stack. */ | |
1468 | write_memory (fp_mem, val, len); | |
1469 | write_memory (fp_arg, (char *) (&fp_mem), REGISTER_SIZE); | |
1470 | ||
1471 | /* fp_mem need not be word-aligned since it's just a chunk of | |
1472 | memory being pointed at. That is, += len would do. */ | |
1473 | fp_mem += reg_demand * REGISTER_SIZE; | |
1474 | fp_arg += REGISTER_SIZE; | |
1475 | } | |
1476 | else | |
1477 | { | |
1478 | /* Data passed by value. No available registers. Put it on | |
1479 | the stack. */ | |
1480 | write_memory (fp_arg, val, len); | |
1481 | ||
1482 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
1483 | the function prologue. */ | |
1484 | fp_arg += reg_demand * REGISTER_SIZE; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | return sp; | |
1489 | } | |
1490 | ||
1491 | /* Never put the return address on the stack. The register SRP is pushed | |
1492 | by the called function unless it is a leaf-function. Due to the BRP | |
1493 | register the PC will change when continue is sent. */ | |
1494 | ||
1495 | CORE_ADDR | |
1496 | cris_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1497 | { | |
1498 | write_register (SRP_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1499 | return sp; | |
1500 | } | |
1501 | ||
1502 | /* Restore the machine to the state it had before the current frame | |
1503 | was created. Discard the innermost frame from the stack and restore | |
1504 | all saved registers. */ | |
1505 | ||
1506 | void | |
1507 | cris_pop_frame () | |
1508 | { | |
1509 | register struct frame_info *fi = get_current_frame (); | |
1510 | register int regno; | |
1511 | register int stack_offset = 0; | |
1512 | ||
1513 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1514 | { | |
1515 | /* This happens when we hit a breakpoint set at the entry point, | |
1516 | when returning from a dummy frame. */ | |
1517 | generic_pop_dummy_frame (); | |
1518 | } | |
1519 | else | |
1520 | { | |
1521 | cris_frame_init_saved_regs (fi); | |
1522 | ||
1523 | /* For each register, the address of where it was saved on entry to | |
1524 | the frame now lies in fi->saved_regs[regno], or zero if it was not | |
1525 | saved. This includes special registers such as PC and FP saved in | |
1526 | special ways in the stack frame. The SP_REGNUM is even more | |
1527 | special, the address here is the SP for the next frame, not the | |
1528 | address where the SP was saved. */ | |
1529 | ||
1530 | /* Restore general registers R0 - R7. They were pushed on the stack | |
1531 | after SP was saved. */ | |
1532 | for (regno = 0; regno < FP_REGNUM; regno++) | |
1533 | { | |
1534 | if (fi->saved_regs[regno]) | |
1535 | { | |
1536 | write_register (regno, | |
1537 | read_memory_integer (fi->saved_regs[regno], 4)); | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | if (fi->saved_regs[FP_REGNUM]) | |
1542 | { | |
1543 | /* Pop the frame pointer (R8). It was pushed before SP | |
1544 | was saved. */ | |
1545 | write_register (FP_REGNUM, | |
1546 | read_memory_integer (fi->saved_regs[FP_REGNUM], 4)); | |
1547 | stack_offset += 4; | |
1548 | ||
1549 | /* Not a leaf function. */ | |
1550 | if (fi->saved_regs[SRP_REGNUM]) | |
1551 | { | |
1552 | /* SRP was pushed before SP was saved. */ | |
1553 | stack_offset += 4; | |
1554 | } | |
1555 | ||
1556 | /* Restore the SP and adjust for R8 and (possibly) SRP. */ | |
1557 | write_register (SP_REGNUM, fi->saved_regs[FP_REGNUM] + stack_offset); | |
1558 | } | |
1559 | else | |
1560 | { | |
1561 | /* Currently, we can't get the correct info into fi->saved_regs | |
1562 | without a frame pointer. */ | |
1563 | } | |
1564 | ||
1565 | /* Restore the PC. */ | |
1566 | write_register (PC_REGNUM, fi->extra_info->return_pc); | |
1567 | } | |
1568 | flush_cached_frames (); | |
1569 | } | |
1570 | ||
1571 | /* Calculates a value that measures how good inst_args constraints an | |
1572 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1573 | ||
1574 | static int | |
1575 | constraint (unsigned int insn, const signed char *inst_args, | |
1576 | inst_env_type *inst_env) | |
1577 | { | |
1578 | int retval = 0; | |
1579 | int tmp, i; | |
1580 | ||
1581 | const char *s = inst_args; | |
1582 | ||
1583 | for (; *s; s++) | |
1584 | switch (*s) | |
1585 | { | |
1586 | case 'm': | |
1587 | if ((insn & 0x30) == 0x30) | |
1588 | return -1; | |
1589 | break; | |
1590 | ||
1591 | case 'S': | |
1592 | /* A prefix operand. */ | |
1593 | if (inst_env->prefix_found) | |
1594 | break; | |
1595 | else | |
1596 | return -1; | |
1597 | ||
1598 | case 'B': | |
1599 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1600 | valid "push" size. In case of special register, it may be != 4. */ | |
1601 | if (inst_env->prefix_found) | |
1602 | break; | |
1603 | else | |
1604 | return -1; | |
1605 | ||
1606 | case 'D': | |
1607 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1608 | if (!retval) | |
1609 | return -1; | |
1610 | else | |
1611 | retval += 4; | |
1612 | break; | |
1613 | ||
1614 | case 'P': | |
1615 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1616 | |
1617 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1618 | { | |
1619 | /* Since we match four bits, we will give a value of | |
1620 | 4 - 1 = 3 in a match. If there is a corresponding | |
1621 | exact match of a special register in another pattern, it | |
1622 | will get a value of 4, which will be higher. This should | |
1623 | be correct in that an exact pattern would match better that | |
1624 | a general pattern. | |
1625 | Note that there is a reason for not returning zero; the | |
1626 | pattern for "clear" is partly matched in the bit-pattern | |
1627 | (the two lower bits must be zero), while the bit-pattern | |
1628 | for a move from a special register is matched in the | |
1629 | register constraint. | |
1630 | This also means we will will have a race condition if | |
1631 | there is a partly match in three bits in the bit pattern. */ | |
1632 | if (tmp == cris_spec_regs[i].number) | |
1633 | { | |
1634 | retval += 3; | |
1635 | break; | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1640 | return -1; |
1641 | break; | |
1642 | } | |
1643 | return retval; | |
1644 | } | |
1645 | ||
1646 | /* Returns the number of bits set in the variable value. */ | |
1647 | ||
1648 | static int | |
1649 | number_of_bits (unsigned int value) | |
1650 | { | |
1651 | int number_of_bits = 0; | |
1652 | ||
1653 | while (value != 0) | |
1654 | { | |
1655 | number_of_bits += 1; | |
1656 | value &= (value - 1); | |
1657 | } | |
1658 | return number_of_bits; | |
1659 | } | |
1660 | ||
1661 | /* Finds the address that should contain the single step breakpoint(s). | |
1662 | It stems from code in cris-dis.c. */ | |
1663 | ||
1664 | static int | |
1665 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1666 | { | |
1667 | int i; | |
1668 | int max_level_of_match = -1; | |
1669 | int max_matched = -1; | |
1670 | int level_of_match; | |
1671 | ||
1672 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1673 | { | |
1674 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
1675 | && ((cris_opcodes[i].lose & insn) == 0)) | |
1676 | { | |
1677 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1678 | if (level_of_match >= 0) | |
1679 | { | |
1680 | level_of_match += | |
1681 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1682 | if (level_of_match > max_level_of_match) | |
1683 | { | |
1684 | max_matched = i; | |
1685 | max_level_of_match = level_of_match; | |
1686 | if (level_of_match == 16) | |
1687 | { | |
1688 | /* All bits matched, cannot find better. */ | |
1689 | break; | |
1690 | } | |
1691 | } | |
1692 | } | |
1693 | } | |
1694 | } | |
1695 | return max_matched; | |
1696 | } | |
1697 | ||
1698 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1699 | actually an internal error. */ | |
1700 | ||
1701 | static int | |
1702 | find_step_target (inst_env_type *inst_env) | |
1703 | { | |
1704 | int i; | |
1705 | int offset; | |
1706 | unsigned short insn; | |
1707 | ||
1708 | /* Create a local register image and set the initial state. */ | |
1709 | for (i = 0; i < NUM_GENREGS; i++) | |
1710 | { | |
1711 | inst_env->reg[i] = (unsigned long) read_register (i); | |
1712 | } | |
1713 | offset = NUM_GENREGS; | |
1714 | for (i = 0; i < NUM_SPECREGS; i++) | |
1715 | { | |
1716 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
1717 | } | |
1718 | inst_env->branch_found = 0; | |
1719 | inst_env->slot_needed = 0; | |
1720 | inst_env->delay_slot_pc_active = 0; | |
1721 | inst_env->prefix_found = 0; | |
1722 | inst_env->invalid = 0; | |
1723 | inst_env->xflag_found = 0; | |
1724 | inst_env->disable_interrupt = 0; | |
1725 | ||
1726 | /* Look for a step target. */ | |
1727 | do | |
1728 | { | |
1729 | /* Read an instruction from the client. */ | |
1730 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
1731 | ||
1732 | /* If the instruction is not in a delay slot the new content of the | |
1733 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
1734 | that simple. Since a instruction in a delay slot cannot change | |
1735 | the content of the PC, it does not matter what value PC will have. | |
1736 | Just make sure it is a valid instruction. */ | |
1737 | if (!inst_env->delay_slot_pc_active) | |
1738 | { | |
1739 | inst_env->reg[PC_REGNUM] += 2; | |
1740 | } | |
1741 | else | |
1742 | { | |
1743 | inst_env->delay_slot_pc_active = 0; | |
1744 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
1745 | } | |
1746 | /* Analyse the present instruction. */ | |
1747 | i = find_cris_op (insn, inst_env); | |
1748 | if (i == -1) | |
1749 | { | |
1750 | inst_env->invalid = 1; | |
1751 | } | |
1752 | else | |
1753 | { | |
1754 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
1755 | } | |
1756 | } while (!inst_env->invalid | |
1757 | && (inst_env->prefix_found || inst_env->xflag_found | |
1758 | || inst_env->slot_needed)); | |
1759 | return i; | |
1760 | } | |
1761 | ||
1762 | /* There is no hardware single-step support. The function find_step_target | |
1763 | digs through the opcodes in order to find all possible targets. | |
1764 | Either one ordinary target or two targets for branches may be found. */ | |
1765 | ||
1766 | void | |
1767 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) | |
1768 | { | |
1769 | inst_env_type inst_env; | |
1770 | ||
1771 | if (insert_breakpoints) | |
1772 | { | |
1773 | /* Analyse the present instruction environment and insert | |
1774 | breakpoints. */ | |
1775 | int status = find_step_target (&inst_env); | |
1776 | if (status == -1) | |
1777 | { | |
1778 | /* Could not find a target. FIXME: Should do something. */ | |
1779 | } | |
1780 | else | |
1781 | { | |
1782 | /* Insert at most two breakpoints. One for the next PC content | |
1783 | and possibly another one for a branch, jump, etc. */ | |
1784 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
1785 | target_insert_breakpoint (next_pc, break_mem[0]); | |
1786 | if (inst_env.branch_found | |
1787 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
1788 | { | |
1789 | branch_target_address = | |
1790 | (CORE_ADDR) inst_env.branch_break_address; | |
1791 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
1792 | branch_break_inserted = 1; | |
1793 | } | |
1794 | } | |
1795 | } | |
1796 | else | |
1797 | { | |
1798 | /* Remove breakpoints. */ | |
1799 | target_remove_breakpoint (next_pc, break_mem[0]); | |
1800 | if (branch_break_inserted) | |
1801 | { | |
1802 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
1803 | branch_break_inserted = 0; | |
1804 | } | |
1805 | } | |
1806 | } | |
1807 | ||
1808 | /* Calculates the prefix value for quick offset addressing mode. */ | |
1809 | ||
1810 | void | |
1811 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1812 | { | |
1813 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
1814 | instruction (not 100% sure). */ | |
1815 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1816 | { | |
1817 | inst_env->invalid = 1; | |
1818 | return; | |
1819 | } | |
1820 | ||
1821 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
1822 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
1823 | ||
1824 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1825 | need updating. */ | |
1826 | inst_env->slot_needed = 0; | |
1827 | inst_env->prefix_found = 1; | |
1828 | } | |
1829 | ||
1830 | /* Updates the autoincrement register. The size of the increment is derived | |
1831 | from the size of the operation. The PC is always kept aligned on even | |
1832 | word addresses. */ | |
1833 | ||
1834 | void | |
1835 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) | |
1836 | { | |
1837 | if (size == INST_BYTE_SIZE) | |
1838 | { | |
1839 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
1840 | ||
1841 | /* The PC must be word aligned, so increase the PC with one | |
1842 | word even if the size is byte. */ | |
1843 | if (cris_get_operand1 (inst) == REG_PC) | |
1844 | { | |
1845 | inst_env->reg[REG_PC] += 1; | |
1846 | } | |
1847 | } | |
1848 | else if (size == INST_WORD_SIZE) | |
1849 | { | |
1850 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
1851 | } | |
1852 | else if (size == INST_DWORD_SIZE) | |
1853 | { | |
1854 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1855 | } | |
1856 | else | |
1857 | { | |
1858 | /* Invalid size. */ | |
1859 | inst_env->invalid = 1; | |
1860 | } | |
1861 | } | |
1862 | ||
1863 | /* Calculates the prefix value for the general case of offset addressing | |
1864 | mode. */ | |
1865 | ||
1866 | void | |
1867 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1868 | { | |
1869 | ||
1870 | long offset; | |
1871 | ||
1872 | /* It's invalid to be in a delay slot. */ | |
1873 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1874 | { | |
1875 | inst_env->invalid = 1; | |
1876 | return; | |
1877 | } | |
1878 | ||
fa4e4598 OF |
1879 | /* The calculation of prefix_value used to be after process_autoincrement, |
1880 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
1881 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
1882 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
1883 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
1884 | ||
1885 | /* The offset is an indirection of the contents of the operand1 register. */ | |
1886 | inst_env->prefix_value += | |
fa4e4598 OF |
1887 | read_memory_integer (inst_env->reg[cris_get_operand1 (inst)], |
1888 | cris_get_size (inst)); | |
1889 | ||
1890 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
1891 | { | |
1892 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
1893 | } | |
1894 | ||
29134980 OF |
1895 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
1896 | need updating. */ | |
1897 | inst_env->slot_needed = 0; | |
1898 | inst_env->prefix_found = 1; | |
1899 | } | |
1900 | ||
1901 | /* Calculates the prefix value for the index addressing mode. */ | |
1902 | ||
1903 | void | |
1904 | biap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1905 | { | |
1906 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
1907 | have a prefix to this instruction. So I will treat this as invalid. */ | |
1908 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1909 | { | |
1910 | inst_env->invalid = 1; | |
1911 | return; | |
1912 | } | |
1913 | ||
1914 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
1915 | ||
1916 | /* The offset is the operand2 value shifted the size of the instruction | |
1917 | to the left. */ | |
1918 | inst_env->prefix_value += | |
1919 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
1920 | ||
1921 | /* If the PC is operand1 (base) the address used is the address after | |
1922 | the main instruction, i.e. address + 2 (the PC is already compensated | |
1923 | for the prefix operation). */ | |
1924 | if (cris_get_operand1 (inst) == REG_PC) | |
1925 | { | |
1926 | inst_env->prefix_value += 2; | |
1927 | } | |
1928 | ||
1929 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1930 | need updating. */ | |
1931 | inst_env->slot_needed = 0; | |
1932 | inst_env->xflag_found = 0; | |
1933 | inst_env->prefix_found = 1; | |
1934 | } | |
1935 | ||
1936 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
1937 | ||
1938 | void | |
1939 | dip_prefix (unsigned short inst, inst_env_type *inst_env) | |
1940 | { | |
1941 | ||
1942 | CORE_ADDR address; | |
1943 | ||
1944 | /* It's invalid to be in a delay slot. */ | |
1945 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1946 | { | |
1947 | inst_env->invalid = 1; | |
1948 | return; | |
1949 | } | |
1950 | ||
1951 | /* The prefix value is one dereference of the contents of the operand1 | |
1952 | register. */ | |
1953 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
1954 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
1955 | ||
1956 | /* Check if the mode is autoincrement. */ | |
1957 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
1958 | { | |
1959 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1960 | } | |
1961 | ||
1962 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1963 | need updating. */ | |
1964 | inst_env->slot_needed = 0; | |
1965 | inst_env->xflag_found = 0; | |
1966 | inst_env->prefix_found = 1; | |
1967 | } | |
1968 | ||
1969 | /* Finds the destination for a branch with 8-bits offset. */ | |
1970 | ||
1971 | void | |
1972 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) | |
1973 | { | |
1974 | ||
1975 | short offset; | |
1976 | ||
1977 | /* If we have a prefix or are in a delay slot it's bad. */ | |
1978 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1979 | { | |
1980 | inst_env->invalid = 1; | |
1981 | return; | |
1982 | } | |
1983 | ||
1984 | /* We have a branch, find out where the branch will land. */ | |
1985 | offset = cris_get_branch_short_offset (inst); | |
1986 | ||
1987 | /* Check if the offset is signed. */ | |
1988 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
1989 | { | |
1990 | offset |= 0xFF00; | |
1991 | } | |
1992 | ||
1993 | /* The offset ends with the sign bit, set it to zero. The address | |
1994 | should always be word aligned. */ | |
1995 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
1996 | ||
1997 | inst_env->branch_found = 1; | |
1998 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
1999 | ||
2000 | inst_env->slot_needed = 1; | |
2001 | inst_env->prefix_found = 0; | |
2002 | inst_env->xflag_found = 0; | |
2003 | inst_env->disable_interrupt = 1; | |
2004 | } | |
2005 | ||
2006 | /* Finds the destination for a branch with 16-bits offset. */ | |
2007 | ||
2008 | void | |
2009 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) | |
2010 | { | |
2011 | short offset; | |
2012 | ||
2013 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2014 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2015 | { | |
2016 | inst_env->invalid = 1; | |
2017 | return; | |
2018 | } | |
2019 | ||
2020 | /* We have a branch, find out the offset for the branch. */ | |
2021 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2022 | ||
2023 | /* The instruction is one word longer than normal, so add one word | |
2024 | to the PC. */ | |
2025 | inst_env->reg[REG_PC] += 2; | |
2026 | ||
2027 | inst_env->branch_found = 1; | |
2028 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2029 | ||
2030 | ||
2031 | inst_env->slot_needed = 1; | |
2032 | inst_env->prefix_found = 0; | |
2033 | inst_env->xflag_found = 0; | |
2034 | inst_env->disable_interrupt = 1; | |
2035 | } | |
2036 | ||
2037 | /* Handles the ABS instruction. */ | |
2038 | ||
2039 | void | |
2040 | abs_op (unsigned short inst, inst_env_type *inst_env) | |
2041 | { | |
2042 | ||
2043 | long value; | |
2044 | ||
2045 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2046 | if (inst_env->prefix_found) | |
2047 | { | |
2048 | inst_env->invalid = 1; | |
2049 | return; | |
2050 | } | |
2051 | ||
2052 | /* Check if the operation affects the PC. */ | |
2053 | if (cris_get_operand2 (inst) == REG_PC) | |
2054 | { | |
2055 | ||
2056 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2057 | if (inst_env->slot_needed) | |
2058 | { | |
2059 | inst_env->invalid = 1; | |
2060 | return; | |
2061 | } | |
2062 | ||
2063 | value = (long) inst_env->reg[REG_PC]; | |
2064 | ||
2065 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2066 | if (value != SIGNED_DWORD_MASK) | |
2067 | { | |
2068 | value = -value; | |
2069 | inst_env->reg[REG_PC] = (long) value; | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | inst_env->slot_needed = 0; | |
2074 | inst_env->prefix_found = 0; | |
2075 | inst_env->xflag_found = 0; | |
2076 | inst_env->disable_interrupt = 0; | |
2077 | } | |
2078 | ||
2079 | /* Handles the ADDI instruction. */ | |
2080 | ||
2081 | void | |
2082 | addi_op (unsigned short inst, inst_env_type *inst_env) | |
2083 | { | |
2084 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2085 | a prefix. */ | |
2086 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2087 | { | |
2088 | inst_env->invalid = 1; | |
2089 | return; | |
2090 | } | |
2091 | ||
2092 | inst_env->slot_needed = 0; | |
2093 | inst_env->prefix_found = 0; | |
2094 | inst_env->xflag_found = 0; | |
2095 | inst_env->disable_interrupt = 0; | |
2096 | } | |
2097 | ||
2098 | /* Handles the ASR instruction. */ | |
2099 | ||
2100 | void | |
2101 | asr_op (unsigned short inst, inst_env_type *inst_env) | |
2102 | { | |
2103 | int shift_steps; | |
2104 | unsigned long value; | |
2105 | unsigned long signed_extend_mask = 0; | |
2106 | ||
2107 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2108 | if (inst_env->prefix_found) | |
2109 | { | |
2110 | inst_env->invalid = 1; | |
2111 | return; | |
2112 | } | |
2113 | ||
2114 | /* Check if the PC is the target register. */ | |
2115 | if (cris_get_operand2 (inst) == REG_PC) | |
2116 | { | |
2117 | /* It's invalid to change the PC in a delay slot. */ | |
2118 | if (inst_env->slot_needed) | |
2119 | { | |
2120 | inst_env->invalid = 1; | |
2121 | return; | |
2122 | } | |
2123 | /* Get the number of bits to shift. */ | |
2124 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2125 | value = inst_env->reg[REG_PC]; | |
2126 | ||
2127 | /* Find out how many bits the operation should apply to. */ | |
2128 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2129 | { | |
2130 | if (value & SIGNED_BYTE_MASK) | |
2131 | { | |
2132 | signed_extend_mask = 0xFF; | |
2133 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2134 | signed_extend_mask = ~signed_extend_mask; | |
2135 | } | |
2136 | value = value >> shift_steps; | |
2137 | value |= signed_extend_mask; | |
2138 | value &= 0xFF; | |
2139 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2140 | inst_env->reg[REG_PC] |= value; | |
2141 | } | |
2142 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2143 | { | |
2144 | if (value & SIGNED_WORD_MASK) | |
2145 | { | |
2146 | signed_extend_mask = 0xFFFF; | |
2147 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2148 | signed_extend_mask = ~signed_extend_mask; | |
2149 | } | |
2150 | value = value >> shift_steps; | |
2151 | value |= signed_extend_mask; | |
2152 | value &= 0xFFFF; | |
2153 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2154 | inst_env->reg[REG_PC] |= value; | |
2155 | } | |
2156 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2157 | { | |
2158 | if (value & SIGNED_DWORD_MASK) | |
2159 | { | |
2160 | signed_extend_mask = 0xFFFFFFFF; | |
2161 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2162 | signed_extend_mask = ~signed_extend_mask; | |
2163 | } | |
2164 | value = value >> shift_steps; | |
2165 | value |= signed_extend_mask; | |
2166 | inst_env->reg[REG_PC] = value; | |
2167 | } | |
2168 | } | |
2169 | inst_env->slot_needed = 0; | |
2170 | inst_env->prefix_found = 0; | |
2171 | inst_env->xflag_found = 0; | |
2172 | inst_env->disable_interrupt = 0; | |
2173 | } | |
2174 | ||
2175 | /* Handles the ASRQ instruction. */ | |
2176 | ||
2177 | void | |
2178 | asrq_op (unsigned short inst, inst_env_type *inst_env) | |
2179 | { | |
2180 | ||
2181 | int shift_steps; | |
2182 | unsigned long value; | |
2183 | unsigned long signed_extend_mask = 0; | |
2184 | ||
2185 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2186 | if (inst_env->prefix_found) | |
2187 | { | |
2188 | inst_env->invalid = 1; | |
2189 | return; | |
2190 | } | |
2191 | ||
2192 | /* Check if the PC is the target register. */ | |
2193 | if (cris_get_operand2 (inst) == REG_PC) | |
2194 | { | |
2195 | ||
2196 | /* It's invalid to change the PC in a delay slot. */ | |
2197 | if (inst_env->slot_needed) | |
2198 | { | |
2199 | inst_env->invalid = 1; | |
2200 | return; | |
2201 | } | |
2202 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2203 | want the the sign bit of the quick value. */ | |
2204 | shift_steps = cris_get_asr_shift_steps (inst); | |
2205 | value = inst_env->reg[REG_PC]; | |
2206 | if (value & SIGNED_DWORD_MASK) | |
2207 | { | |
2208 | signed_extend_mask = 0xFFFFFFFF; | |
2209 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2210 | signed_extend_mask = ~signed_extend_mask; | |
2211 | } | |
2212 | value = value >> shift_steps; | |
2213 | value |= signed_extend_mask; | |
2214 | inst_env->reg[REG_PC] = value; | |
2215 | } | |
2216 | inst_env->slot_needed = 0; | |
2217 | inst_env->prefix_found = 0; | |
2218 | inst_env->xflag_found = 0; | |
2219 | inst_env->disable_interrupt = 0; | |
2220 | } | |
2221 | ||
2222 | /* Handles the AX, EI and SETF instruction. */ | |
2223 | ||
2224 | void | |
2225 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) | |
2226 | { | |
2227 | if (inst_env->prefix_found) | |
2228 | { | |
2229 | inst_env->invalid = 1; | |
2230 | return; | |
2231 | } | |
2232 | /* Check if the instruction is setting the X flag. */ | |
2233 | if (cris_is_xflag_bit_on (inst)) | |
2234 | { | |
2235 | inst_env->xflag_found = 1; | |
2236 | } | |
2237 | else | |
2238 | { | |
2239 | inst_env->xflag_found = 0; | |
2240 | } | |
2241 | inst_env->slot_needed = 0; | |
2242 | inst_env->prefix_found = 0; | |
2243 | inst_env->disable_interrupt = 1; | |
2244 | } | |
2245 | ||
2246 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2247 | register. Note that check_assign assumes that the caller has checked that | |
2248 | there is a prefix to this instruction. The mode check depends on this. */ | |
2249 | ||
2250 | void | |
2251 | check_assign (unsigned short inst, inst_env_type *inst_env) | |
2252 | { | |
2253 | /* Check if it's an assign addressing mode. */ | |
2254 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2255 | { | |
2256 | /* Assign the prefix value to operand 1. */ | |
2257 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2258 | } | |
2259 | } | |
2260 | ||
2261 | /* Handles the 2-operand BOUND instruction. */ | |
2262 | ||
2263 | void | |
2264 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) | |
2265 | { | |
2266 | /* It's invalid to have the PC as the index operand. */ | |
2267 | if (cris_get_operand2 (inst) == REG_PC) | |
2268 | { | |
2269 | inst_env->invalid = 1; | |
2270 | return; | |
2271 | } | |
2272 | /* Check if we have a prefix. */ | |
2273 | if (inst_env->prefix_found) | |
2274 | { | |
2275 | check_assign (inst, inst_env); | |
2276 | } | |
2277 | /* Check if this is an autoincrement mode. */ | |
2278 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2279 | { | |
2280 | /* It's invalid to change the PC in a delay slot. */ | |
2281 | if (inst_env->slot_needed) | |
2282 | { | |
2283 | inst_env->invalid = 1; | |
2284 | return; | |
2285 | } | |
2286 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2287 | } | |
2288 | inst_env->slot_needed = 0; | |
2289 | inst_env->prefix_found = 0; | |
2290 | inst_env->xflag_found = 0; | |
2291 | inst_env->disable_interrupt = 0; | |
2292 | } | |
2293 | ||
2294 | /* Handles the 3-operand BOUND instruction. */ | |
2295 | ||
2296 | void | |
2297 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) | |
2298 | { | |
2299 | /* It's an error if we haven't got a prefix. And it's also an error | |
2300 | if the PC is the destination register. */ | |
2301 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2302 | { | |
2303 | inst_env->invalid = 1; | |
2304 | return; | |
2305 | } | |
2306 | inst_env->slot_needed = 0; | |
2307 | inst_env->prefix_found = 0; | |
2308 | inst_env->xflag_found = 0; | |
2309 | inst_env->disable_interrupt = 0; | |
2310 | } | |
2311 | ||
2312 | /* Clears the status flags in inst_env. */ | |
2313 | ||
2314 | void | |
2315 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) | |
2316 | { | |
2317 | /* It's an error if we have got a prefix. */ | |
2318 | if (inst_env->prefix_found) | |
2319 | { | |
2320 | inst_env->invalid = 1; | |
2321 | return; | |
2322 | } | |
2323 | ||
2324 | inst_env->slot_needed = 0; | |
2325 | inst_env->prefix_found = 0; | |
2326 | inst_env->xflag_found = 0; | |
2327 | inst_env->disable_interrupt = 0; | |
2328 | } | |
2329 | ||
2330 | /* Clears the status flags in inst_env. */ | |
2331 | ||
2332 | void | |
2333 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) | |
2334 | { | |
2335 | /* It's an error if we have got a prefix. */ | |
2336 | if (inst_env->prefix_found) | |
2337 | { | |
2338 | inst_env->invalid = 1; | |
2339 | return; | |
2340 | } | |
2341 | ||
2342 | inst_env->slot_needed = 0; | |
2343 | inst_env->prefix_found = 0; | |
2344 | inst_env->xflag_found = 0; | |
2345 | inst_env->disable_interrupt = 1; | |
2346 | } | |
2347 | ||
2348 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2349 | ||
2350 | void | |
2351 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) | |
2352 | { | |
2353 | /* Check if the target is the PC. */ | |
2354 | if (cris_get_operand2 (inst) == REG_PC) | |
2355 | { | |
2356 | /* The instruction will clear the instruction's size bits. */ | |
2357 | int clear_size = cris_get_clear_size (inst); | |
2358 | if (clear_size == INST_BYTE_SIZE) | |
2359 | { | |
2360 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2361 | } | |
2362 | if (clear_size == INST_WORD_SIZE) | |
2363 | { | |
2364 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2365 | } | |
2366 | if (clear_size == INST_DWORD_SIZE) | |
2367 | { | |
2368 | inst_env->delay_slot_pc = 0x0; | |
2369 | } | |
2370 | /* The jump will be delayed with one delay slot. So we need a delay | |
2371 | slot. */ | |
2372 | inst_env->slot_needed = 1; | |
2373 | inst_env->delay_slot_pc_active = 1; | |
2374 | } | |
2375 | else | |
2376 | { | |
2377 | /* The PC will not change => no delay slot. */ | |
2378 | inst_env->slot_needed = 0; | |
2379 | } | |
2380 | inst_env->prefix_found = 0; | |
2381 | inst_env->xflag_found = 0; | |
2382 | inst_env->disable_interrupt = 0; | |
2383 | } | |
2384 | ||
2385 | /* Handles the TEST instruction if it's in register mode. */ | |
2386 | ||
2387 | void | |
2388 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) | |
2389 | { | |
2390 | /* It's an error if we have got a prefix. */ | |
2391 | if (inst_env->prefix_found) | |
2392 | { | |
2393 | inst_env->invalid = 1; | |
2394 | return; | |
2395 | } | |
2396 | inst_env->slot_needed = 0; | |
2397 | inst_env->prefix_found = 0; | |
2398 | inst_env->xflag_found = 0; | |
2399 | inst_env->disable_interrupt = 0; | |
2400 | ||
2401 | } | |
2402 | ||
2403 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2404 | in register mode. */ | |
2405 | ||
2406 | void | |
2407 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) | |
2408 | { | |
2409 | /* Check if we are in a prefix mode. */ | |
2410 | if (inst_env->prefix_found) | |
2411 | { | |
2412 | /* The only way the PC can change is if this instruction is in | |
2413 | assign addressing mode. */ | |
2414 | check_assign (inst, inst_env); | |
2415 | } | |
2416 | /* Indirect mode can't change the PC so just check if the mode is | |
2417 | autoincrement. */ | |
2418 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2419 | { | |
2420 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2421 | } | |
2422 | inst_env->slot_needed = 0; | |
2423 | inst_env->prefix_found = 0; | |
2424 | inst_env->xflag_found = 0; | |
2425 | inst_env->disable_interrupt = 0; | |
2426 | } | |
2427 | ||
2428 | /* Checks that the PC isn't the destination register or the instructions has | |
2429 | a prefix. */ | |
2430 | ||
2431 | void | |
2432 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) | |
2433 | { | |
2434 | /* It's invalid to have the PC as the destination. The instruction can't | |
2435 | have a prefix. */ | |
2436 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2437 | { | |
2438 | inst_env->invalid = 1; | |
2439 | return; | |
2440 | } | |
2441 | ||
2442 | inst_env->slot_needed = 0; | |
2443 | inst_env->prefix_found = 0; | |
2444 | inst_env->xflag_found = 0; | |
2445 | inst_env->disable_interrupt = 0; | |
2446 | } | |
2447 | ||
2448 | /* Checks that the instruction doesn't have a prefix. */ | |
2449 | ||
2450 | void | |
2451 | break_op (unsigned short inst, inst_env_type *inst_env) | |
2452 | { | |
2453 | /* The instruction can't have a prefix. */ | |
2454 | if (inst_env->prefix_found) | |
2455 | { | |
2456 | inst_env->invalid = 1; | |
2457 | return; | |
2458 | } | |
2459 | ||
2460 | inst_env->slot_needed = 0; | |
2461 | inst_env->prefix_found = 0; | |
2462 | inst_env->xflag_found = 0; | |
2463 | inst_env->disable_interrupt = 1; | |
2464 | } | |
2465 | ||
2466 | /* Checks that the PC isn't the destination register and that the instruction | |
2467 | doesn't have a prefix. */ | |
2468 | ||
2469 | void | |
2470 | scc_op (unsigned short inst, inst_env_type *inst_env) | |
2471 | { | |
2472 | /* It's invalid to have the PC as the destination. The instruction can't | |
2473 | have a prefix. */ | |
2474 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2475 | { | |
2476 | inst_env->invalid = 1; | |
2477 | return; | |
2478 | } | |
2479 | ||
2480 | inst_env->slot_needed = 0; | |
2481 | inst_env->prefix_found = 0; | |
2482 | inst_env->xflag_found = 0; | |
2483 | inst_env->disable_interrupt = 1; | |
2484 | } | |
2485 | ||
2486 | /* Handles the register mode JUMP instruction. */ | |
2487 | ||
2488 | void | |
2489 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
2490 | { | |
2491 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2492 | you can't have a prefix. */ | |
2493 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2494 | { | |
2495 | inst_env->invalid = 1; | |
2496 | return; | |
2497 | } | |
2498 | ||
2499 | /* Just change the PC. */ | |
2500 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2501 | inst_env->slot_needed = 0; | |
2502 | inst_env->prefix_found = 0; | |
2503 | inst_env->xflag_found = 0; | |
2504 | inst_env->disable_interrupt = 1; | |
2505 | } | |
2506 | ||
2507 | /* Handles the JUMP instruction for all modes except register. */ | |
2508 | ||
2509 | void none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
2510 | { | |
2511 | unsigned long newpc; | |
2512 | CORE_ADDR address; | |
2513 | ||
2514 | /* It's invalid to do a JUMP in a delay slot. */ | |
2515 | if (inst_env->slot_needed) | |
2516 | { | |
2517 | inst_env->invalid = 1; | |
2518 | } | |
2519 | else | |
2520 | { | |
2521 | /* Check if we have a prefix. */ | |
2522 | if (inst_env->prefix_found) | |
2523 | { | |
2524 | check_assign (inst, inst_env); | |
2525 | ||
2526 | /* Get the new value for the the PC. */ | |
2527 | newpc = | |
2528 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2529 | 4); | |
2530 | } | |
2531 | else | |
2532 | { | |
2533 | /* Get the new value for the PC. */ | |
2534 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2535 | newpc = read_memory_unsigned_integer (address, 4); | |
2536 | ||
2537 | /* Check if we should increment a register. */ | |
2538 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2539 | { | |
2540 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2541 | } | |
2542 | } | |
2543 | inst_env->reg[REG_PC] = newpc; | |
2544 | } | |
2545 | inst_env->slot_needed = 0; | |
2546 | inst_env->prefix_found = 0; | |
2547 | inst_env->xflag_found = 0; | |
2548 | inst_env->disable_interrupt = 1; | |
2549 | } | |
2550 | ||
2551 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2552 | ||
2553 | void | |
2554 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2555 | { | |
2556 | if (inst_env->prefix_found) | |
2557 | { | |
2558 | /* The instruction has a prefix that means we are only interested if | |
2559 | the instruction is in assign mode. */ | |
2560 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2561 | { | |
2562 | /* The prefix handles the problem if we are in a delay slot. */ | |
2563 | if (cris_get_operand1 (inst) == REG_PC) | |
2564 | { | |
2565 | /* Just take care of the assign. */ | |
2566 | check_assign (inst, inst_env); | |
2567 | } | |
2568 | } | |
2569 | } | |
2570 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2571 | { | |
2572 | /* The instruction doesn't have a prefix, the only case left that we | |
2573 | are interested in is the autoincrement mode. */ | |
2574 | if (cris_get_operand1 (inst) == REG_PC) | |
2575 | { | |
2576 | /* If the PC is to be incremented it's invalid to be in a | |
2577 | delay slot. */ | |
2578 | if (inst_env->slot_needed) | |
2579 | { | |
2580 | inst_env->invalid = 1; | |
2581 | return; | |
2582 | } | |
2583 | /* The increment depends on the size of the special register. | |
2584 | Register P0 to P3 has the size byte, register P4 to P7 has the | |
2585 | size word and register P8 to P15 has the size dword. */ | |
2586 | if (cris_get_operand2 (inst) < 4) | |
2587 | { | |
2588 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2589 | } | |
2590 | if (cris_get_operand2 (inst) < 8) | |
2591 | { | |
2592 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2593 | } | |
2594 | else | |
2595 | { | |
2596 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2597 | } | |
2598 | } | |
2599 | } | |
2600 | inst_env->slot_needed = 0; | |
2601 | inst_env->prefix_found = 0; | |
2602 | inst_env->xflag_found = 0; | |
2603 | inst_env->disable_interrupt = 1; | |
2604 | } | |
2605 | ||
2606 | /* Handles moves from special registers (aka P-register) for all modes | |
2607 | except register. */ | |
2608 | ||
2609 | void | |
2610 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2611 | { | |
2612 | if (inst_env->prefix_found) | |
2613 | { | |
2614 | /* The instruction has a prefix that means we are only interested if | |
2615 | the instruction is in assign mode. */ | |
2616 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2617 | { | |
2618 | /* The prefix handles the problem if we are in a delay slot. */ | |
2619 | if (cris_get_operand1 (inst) == REG_PC) | |
2620 | { | |
2621 | /* Just take care of the assign. */ | |
2622 | check_assign (inst, inst_env); | |
2623 | } | |
2624 | } | |
2625 | } | |
2626 | /* The instruction doesn't have a prefix, the only case left that we | |
2627 | are interested in is the autoincrement mode. */ | |
2628 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2629 | { | |
2630 | if (cris_get_operand1 (inst) == REG_PC) | |
2631 | { | |
2632 | /* If the PC is to be incremented it's invalid to be in a | |
2633 | delay slot. */ | |
2634 | if (inst_env->slot_needed) | |
2635 | { | |
2636 | inst_env->invalid = 1; | |
2637 | return; | |
2638 | } | |
2639 | /* The increment depends on the size of the special register. | |
2640 | Register P0 to P3 has the size byte, register P4 to P7 has | |
2641 | the size word and register P8 to P15 has the size dword. */ | |
2642 | if (cris_get_operand2 (inst) < 4) | |
2643 | { | |
2644 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2645 | } | |
2646 | if (cris_get_operand2 (inst) < 8) | |
2647 | { | |
2648 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2649 | } | |
2650 | else | |
2651 | { | |
2652 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2653 | } | |
2654 | } | |
2655 | } | |
2656 | inst_env->slot_needed = 0; | |
2657 | inst_env->prefix_found = 0; | |
2658 | inst_env->xflag_found = 0; | |
2659 | inst_env->disable_interrupt = 1; | |
2660 | } | |
2661 | ||
2662 | /* Handles moves from special registers (aka P-register) when the mode | |
2663 | is register. */ | |
2664 | ||
2665 | void | |
2666 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2667 | { | |
2668 | /* Register mode move from special register can't have a prefix. */ | |
2669 | if (inst_env->prefix_found) | |
2670 | { | |
2671 | inst_env->invalid = 1; | |
2672 | return; | |
2673 | } | |
2674 | ||
2675 | if (cris_get_operand1 (inst) == REG_PC) | |
2676 | { | |
2677 | /* It's invalid to change the PC in a delay slot. */ | |
2678 | if (inst_env->slot_needed) | |
2679 | { | |
2680 | inst_env->invalid = 1; | |
2681 | return; | |
2682 | } | |
2683 | /* The destination is the PC, the jump will have a delay slot. */ | |
2684 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2685 | inst_env->slot_needed = 1; | |
2686 | inst_env->delay_slot_pc_active = 1; | |
2687 | } | |
2688 | else | |
2689 | { | |
2690 | /* If the destination isn't PC, there will be no jump. */ | |
2691 | inst_env->slot_needed = 0; | |
2692 | } | |
2693 | inst_env->prefix_found = 0; | |
2694 | inst_env->xflag_found = 0; | |
2695 | inst_env->disable_interrupt = 1; | |
2696 | } | |
2697 | ||
2698 | /* Handles the MOVEM from memory to general register instruction. */ | |
2699 | ||
2700 | void | |
2701 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) | |
2702 | { | |
2703 | if (inst_env->prefix_found) | |
2704 | { | |
2705 | /* The prefix handles the problem if we are in a delay slot. Is the | |
2706 | MOVEM instruction going to change the PC? */ | |
2707 | if (cris_get_operand2 (inst) >= REG_PC) | |
2708 | { | |
2709 | inst_env->reg[REG_PC] = | |
2710 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
2711 | } | |
2712 | /* The assign value is the value after the increment. Normally, the | |
2713 | assign value is the value before the increment. */ | |
2714 | if ((cris_get_operand1 (inst) == REG_PC) | |
2715 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2716 | { | |
2717 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2718 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2719 | } | |
2720 | } | |
2721 | else | |
2722 | { | |
2723 | /* Is the MOVEM instruction going to change the PC? */ | |
2724 | if (cris_get_operand2 (inst) == REG_PC) | |
2725 | { | |
2726 | /* It's invalid to change the PC in a delay slot. */ | |
2727 | if (inst_env->slot_needed) | |
2728 | { | |
2729 | inst_env->invalid = 1; | |
2730 | return; | |
2731 | } | |
2732 | inst_env->reg[REG_PC] = | |
2733 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
2734 | 4); | |
2735 | } | |
2736 | /* The increment is not depending on the size, instead it's depending | |
2737 | on the number of registers loaded from memory. */ | |
2738 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2739 | { | |
2740 | /* It's invalid to change the PC in a delay slot. */ | |
2741 | if (inst_env->slot_needed) | |
2742 | { | |
2743 | inst_env->invalid = 1; | |
2744 | return; | |
2745 | } | |
2746 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2747 | } | |
2748 | } | |
2749 | inst_env->slot_needed = 0; | |
2750 | inst_env->prefix_found = 0; | |
2751 | inst_env->xflag_found = 0; | |
2752 | inst_env->disable_interrupt = 0; | |
2753 | } | |
2754 | ||
2755 | /* Handles the MOVEM to memory from general register instruction. */ | |
2756 | ||
2757 | void | |
2758 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) | |
2759 | { | |
2760 | if (inst_env->prefix_found) | |
2761 | { | |
2762 | /* The assign value is the value after the increment. Normally, the | |
2763 | assign value is the value before the increment. */ | |
2764 | if ((cris_get_operand1 (inst) == REG_PC) && | |
2765 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2766 | { | |
2767 | /* The prefix handles the problem if we are in a delay slot. */ | |
2768 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2769 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2770 | } | |
2771 | } | |
2772 | else | |
2773 | { | |
2774 | /* The increment is not depending on the size, instead it's depending | |
2775 | on the number of registers loaded to memory. */ | |
2776 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2777 | { | |
2778 | /* It's invalid to change the PC in a delay slot. */ | |
2779 | if (inst_env->slot_needed) | |
2780 | { | |
2781 | inst_env->invalid = 1; | |
2782 | return; | |
2783 | } | |
2784 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2785 | } | |
2786 | } | |
2787 | inst_env->slot_needed = 0; | |
2788 | inst_env->prefix_found = 0; | |
2789 | inst_env->xflag_found = 0; | |
2790 | inst_env->disable_interrupt = 0; | |
2791 | } | |
2792 | ||
2793 | /* Handles the pop instruction to a general register. | |
2794 | POP is a assembler macro for MOVE.D [SP+], Rd. */ | |
2795 | ||
2796 | void | |
2797 | reg_pop_op (unsigned short inst, inst_env_type *inst_env) | |
2798 | { | |
2799 | /* POP can't have a prefix. */ | |
2800 | if (inst_env->prefix_found) | |
2801 | { | |
2802 | inst_env->invalid = 1; | |
2803 | return; | |
2804 | } | |
2805 | if (cris_get_operand2 (inst) == REG_PC) | |
2806 | { | |
2807 | /* It's invalid to change the PC in a delay slot. */ | |
2808 | if (inst_env->slot_needed) | |
2809 | { | |
2810 | inst_env->invalid = 1; | |
2811 | return; | |
2812 | } | |
2813 | inst_env->reg[REG_PC] = | |
2814 | read_memory_unsigned_integer (inst_env->reg[REG_SP], 4); | |
2815 | } | |
2816 | inst_env->slot_needed = 0; | |
2817 | inst_env->prefix_found = 0; | |
2818 | inst_env->xflag_found = 0; | |
2819 | inst_env->disable_interrupt = 0; | |
2820 | } | |
2821 | ||
2822 | /* Handles moves from register to memory. */ | |
2823 | ||
2824 | void | |
2825 | move_reg_to_mem_index_inc_op (unsigned short inst, inst_env_type *inst_env) | |
2826 | { | |
2827 | /* Check if we have a prefix. */ | |
2828 | if (inst_env->prefix_found) | |
2829 | { | |
2830 | /* The only thing that can change the PC is an assign. */ | |
2831 | check_assign (inst, inst_env); | |
2832 | } | |
2833 | else if ((cris_get_operand1 (inst) == REG_PC) | |
2834 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2835 | { | |
2836 | /* It's invalid to change the PC in a delay slot. */ | |
2837 | if (inst_env->slot_needed) | |
2838 | { | |
2839 | inst_env->invalid = 1; | |
2840 | return; | |
2841 | } | |
2842 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2843 | } | |
2844 | inst_env->slot_needed = 0; | |
2845 | inst_env->prefix_found = 0; | |
2846 | inst_env->xflag_found = 0; | |
2847 | inst_env->disable_interrupt = 0; | |
2848 | } | |
2849 | ||
2850 | /* Handles the intructions that's not yet implemented, by setting | |
2851 | inst_env->invalid to true. */ | |
2852 | ||
2853 | void | |
2854 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) | |
2855 | { | |
2856 | inst_env->invalid = 1; | |
2857 | } | |
2858 | ||
2859 | /* Handles the XOR instruction. */ | |
2860 | ||
2861 | void | |
2862 | xor_op (unsigned short inst, inst_env_type *inst_env) | |
2863 | { | |
2864 | /* XOR can't have a prefix. */ | |
2865 | if (inst_env->prefix_found) | |
2866 | { | |
2867 | inst_env->invalid = 1; | |
2868 | return; | |
2869 | } | |
2870 | ||
2871 | /* Check if the PC is the target. */ | |
2872 | if (cris_get_operand2 (inst) == REG_PC) | |
2873 | { | |
2874 | /* It's invalid to change the PC in a delay slot. */ | |
2875 | if (inst_env->slot_needed) | |
2876 | { | |
2877 | inst_env->invalid = 1; | |
2878 | return; | |
2879 | } | |
2880 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
2881 | } | |
2882 | inst_env->slot_needed = 0; | |
2883 | inst_env->prefix_found = 0; | |
2884 | inst_env->xflag_found = 0; | |
2885 | inst_env->disable_interrupt = 0; | |
2886 | } | |
2887 | ||
2888 | /* Handles the MULS instruction. */ | |
2889 | ||
2890 | void | |
2891 | muls_op (unsigned short inst, inst_env_type *inst_env) | |
2892 | { | |
2893 | /* MULS/U can't have a prefix. */ | |
2894 | if (inst_env->prefix_found) | |
2895 | { | |
2896 | inst_env->invalid = 1; | |
2897 | return; | |
2898 | } | |
2899 | ||
2900 | /* Consider it invalid if the PC is the target. */ | |
2901 | if (cris_get_operand2 (inst) == REG_PC) | |
2902 | { | |
2903 | inst_env->invalid = 1; | |
2904 | return; | |
2905 | } | |
2906 | inst_env->slot_needed = 0; | |
2907 | inst_env->prefix_found = 0; | |
2908 | inst_env->xflag_found = 0; | |
2909 | inst_env->disable_interrupt = 0; | |
2910 | } | |
2911 | ||
2912 | /* Handles the MULU instruction. */ | |
2913 | ||
2914 | void | |
2915 | mulu_op (unsigned short inst, inst_env_type *inst_env) | |
2916 | { | |
2917 | /* MULS/U can't have a prefix. */ | |
2918 | if (inst_env->prefix_found) | |
2919 | { | |
2920 | inst_env->invalid = 1; | |
2921 | return; | |
2922 | } | |
2923 | ||
2924 | /* Consider it invalid if the PC is the target. */ | |
2925 | if (cris_get_operand2 (inst) == REG_PC) | |
2926 | { | |
2927 | inst_env->invalid = 1; | |
2928 | return; | |
2929 | } | |
2930 | inst_env->slot_needed = 0; | |
2931 | inst_env->prefix_found = 0; | |
2932 | inst_env->xflag_found = 0; | |
2933 | inst_env->disable_interrupt = 0; | |
2934 | } | |
2935 | ||
2936 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
2937 | The MOVE instruction is the move from source to register. */ | |
2938 | ||
2939 | void | |
2940 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, | |
2941 | unsigned long source1, unsigned long source2) | |
2942 | { | |
2943 | unsigned long pc_mask; | |
2944 | unsigned long operation_mask; | |
2945 | ||
2946 | /* Find out how many bits the operation should apply to. */ | |
2947 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2948 | { | |
2949 | pc_mask = 0xFFFFFF00; | |
2950 | operation_mask = 0xFF; | |
2951 | } | |
2952 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2953 | { | |
2954 | pc_mask = 0xFFFF0000; | |
2955 | operation_mask = 0xFFFF; | |
2956 | } | |
2957 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2958 | { | |
2959 | pc_mask = 0x0; | |
2960 | operation_mask = 0xFFFFFFFF; | |
2961 | } | |
2962 | else | |
2963 | { | |
2964 | /* The size is out of range. */ | |
2965 | inst_env->invalid = 1; | |
2966 | return; | |
2967 | } | |
2968 | ||
2969 | /* The instruction just works on uw_operation_mask bits. */ | |
2970 | source2 &= operation_mask; | |
2971 | source1 &= operation_mask; | |
2972 | ||
2973 | /* Now calculate the result. The opcode's 3 first bits separates | |
2974 | the different actions. */ | |
2975 | switch (cris_get_opcode (inst) & 7) | |
2976 | { | |
2977 | case 0: /* add */ | |
2978 | source1 += source2; | |
2979 | break; | |
2980 | ||
2981 | case 1: /* move */ | |
2982 | source1 = source2; | |
2983 | break; | |
2984 | ||
2985 | case 2: /* subtract */ | |
2986 | source1 -= source2; | |
2987 | break; | |
2988 | ||
2989 | case 3: /* compare */ | |
2990 | break; | |
2991 | ||
2992 | case 4: /* and */ | |
2993 | source1 &= source2; | |
2994 | break; | |
2995 | ||
2996 | case 5: /* or */ | |
2997 | source1 |= source2; | |
2998 | break; | |
2999 | ||
3000 | default: | |
3001 | inst_env->invalid = 1; | |
3002 | return; | |
3003 | ||
3004 | break; | |
3005 | } | |
3006 | ||
3007 | /* Make sure that the result doesn't contain more than the instruction | |
3008 | size bits. */ | |
3009 | source2 &= operation_mask; | |
3010 | ||
3011 | /* Calculate the new breakpoint address. */ | |
3012 | inst_env->reg[REG_PC] &= pc_mask; | |
3013 | inst_env->reg[REG_PC] |= source1; | |
3014 | ||
3015 | } | |
3016 | ||
3017 | /* Extends the value from either byte or word size to a dword. If the mode | |
3018 | is zero extend then the value is extended with zero. If instead the mode | |
3019 | is signed extend the sign bit of the value is taken into consideration. */ | |
3020 | ||
3021 | unsigned long | |
3022 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) | |
3023 | { | |
3024 | /* The size can be either byte or word, check which one it is. | |
3025 | Don't check the highest bit, it's indicating if it's a zero | |
3026 | or sign extend. */ | |
3027 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3028 | { | |
3029 | /* Word size. */ | |
3030 | value &= 0xFFFF; | |
3031 | ||
3032 | /* Check if the instruction is signed extend. If so, check if value has | |
3033 | the sign bit on. */ | |
3034 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3035 | { | |
3036 | value |= SIGNED_WORD_EXTEND_MASK; | |
3037 | } | |
3038 | } | |
3039 | else | |
3040 | { | |
3041 | /* Byte size. */ | |
3042 | value &= 0xFF; | |
3043 | ||
3044 | /* Check if the instruction is signed extend. If so, check if value has | |
3045 | the sign bit on. */ | |
3046 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3047 | { | |
3048 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3049 | } | |
3050 | } | |
3051 | /* The size should now be dword. */ | |
3052 | cris_set_size_to_dword (inst); | |
3053 | return value; | |
3054 | } | |
3055 | ||
3056 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3057 | instruction. The MOVE instruction is the move from source to register. */ | |
3058 | ||
3059 | void | |
3060 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, | |
3061 | inst_env_type *inst_env) | |
3062 | { | |
3063 | unsigned long operand1; | |
3064 | unsigned long operand2; | |
3065 | ||
3066 | /* It's invalid to have a prefix to the instruction. This is a register | |
3067 | mode instruction and can't have a prefix. */ | |
3068 | if (inst_env->prefix_found) | |
3069 | { | |
3070 | inst_env->invalid = 1; | |
3071 | return; | |
3072 | } | |
3073 | /* Check if the instruction has PC as its target. */ | |
3074 | if (cris_get_operand2 (inst) == REG_PC) | |
3075 | { | |
3076 | if (inst_env->slot_needed) | |
3077 | { | |
3078 | inst_env->invalid = 1; | |
3079 | return; | |
3080 | } | |
3081 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3082 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3083 | operand2 = inst_env->reg[REG_PC]; |
3084 | ||
3085 | /* Check if it's a extend, signed or zero instruction. */ | |
3086 | if (cris_get_opcode (inst) < 4) | |
3087 | { | |
3088 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3089 | } | |
3090 | /* Calculate the PC value after the instruction, i.e. where the | |
3091 | breakpoint should be. The order of the udw_operands is vital. */ | |
3092 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3093 | } | |
3094 | inst_env->slot_needed = 0; | |
3095 | inst_env->prefix_found = 0; | |
3096 | inst_env->xflag_found = 0; | |
3097 | inst_env->disable_interrupt = 0; | |
3098 | } | |
3099 | ||
3100 | /* Returns the data contained at address. The size of the data is derived from | |
3101 | the size of the operation. If the instruction is a zero or signed | |
3102 | extend instruction, the size field is changed in instruction. */ | |
3103 | ||
3104 | unsigned long | |
3105 | get_data_from_address (unsigned short *inst, CORE_ADDR address) | |
3106 | { | |
3107 | int size = cris_get_size (*inst); | |
3108 | unsigned long value; | |
3109 | ||
3110 | /* If it's an extend instruction we don't want the signed extend bit, | |
3111 | because it influences the size. */ | |
3112 | if (cris_get_opcode (*inst) < 4) | |
3113 | { | |
3114 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3115 | } | |
3116 | /* Is there a need for checking the size? Size should contain the number of | |
3117 | bytes to read. */ | |
3118 | size = 1 << size; | |
3119 | value = read_memory_unsigned_integer (address, size); | |
3120 | ||
3121 | /* Check if it's an extend, signed or zero instruction. */ | |
3122 | if (cris_get_opcode (*inst) < 4) | |
3123 | { | |
3124 | value = do_sign_or_zero_extend (value, inst); | |
3125 | } | |
3126 | return value; | |
3127 | } | |
3128 | ||
3129 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3130 | instructions. The MOVE instruction is the move from source to register. */ | |
3131 | ||
3132 | void | |
3133 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, | |
3134 | inst_env_type *inst_env) | |
3135 | { | |
3136 | unsigned long operand2; | |
3137 | unsigned long operand3; | |
3138 | ||
3139 | check_assign (inst, inst_env); | |
3140 | if (cris_get_operand2 (inst) == REG_PC) | |
3141 | { | |
3142 | operand2 = inst_env->reg[REG_PC]; | |
3143 | ||
3144 | /* Get the value of the third operand. */ | |
3145 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3146 | ||
3147 | /* Calculate the PC value after the instruction, i.e. where the | |
3148 | breakpoint should be. The order of the udw_operands is vital. */ | |
3149 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3150 | } | |
3151 | inst_env->slot_needed = 0; | |
3152 | inst_env->prefix_found = 0; | |
3153 | inst_env->xflag_found = 0; | |
3154 | inst_env->disable_interrupt = 0; | |
3155 | } | |
3156 | ||
3157 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3158 | OR instructions. Note that for this to work as expected, the calling | |
3159 | function must have made sure that there is a prefix to this instruction. */ | |
3160 | ||
3161 | void | |
3162 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, | |
3163 | inst_env_type *inst_env) | |
3164 | { | |
3165 | unsigned long operand2; | |
3166 | unsigned long operand3; | |
3167 | ||
3168 | if (cris_get_operand1 (inst) == REG_PC) | |
3169 | { | |
3170 | /* The PC will be changed by the instruction. */ | |
3171 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3172 | ||
3173 | /* Get the value of the third operand. */ | |
3174 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3175 | ||
3176 | /* Calculate the PC value after the instruction, i.e. where the | |
3177 | breakpoint should be. */ | |
3178 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3179 | } | |
3180 | inst_env->slot_needed = 0; | |
3181 | inst_env->prefix_found = 0; | |
3182 | inst_env->xflag_found = 0; | |
3183 | inst_env->disable_interrupt = 0; | |
3184 | } | |
3185 | ||
3186 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3187 | instructions. The MOVE instruction is the move from source to register. */ | |
3188 | ||
3189 | void | |
3190 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, | |
3191 | inst_env_type *inst_env) | |
3192 | { | |
3193 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3194 | { | |
3195 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3196 | SUB, AND or OR something weird is going on (if everything works these | |
3197 | instructions should end up in the three operand version). */ | |
3198 | inst_env->invalid = 1; | |
3199 | return; | |
3200 | } | |
3201 | else | |
3202 | { | |
3203 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3204 | so use it. */ | |
3205 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3206 | } | |
3207 | inst_env->slot_needed = 0; | |
3208 | inst_env->prefix_found = 0; | |
3209 | inst_env->xflag_found = 0; | |
3210 | inst_env->disable_interrupt = 0; | |
3211 | } | |
3212 | ||
3213 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3214 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3215 | source to register. */ | |
3216 | ||
3217 | void | |
3218 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, | |
3219 | inst_env_type *inst_env) | |
3220 | { | |
3221 | unsigned long operand1; | |
3222 | unsigned long operand2; | |
3223 | unsigned long operand3; | |
3224 | int size; | |
3225 | ||
3226 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3227 | Check if the destination register is the PC. */ | |
3228 | if (cris_get_operand2 (inst) == REG_PC) | |
3229 | { | |
3230 | /* Must be done here, get_data_from_address may change the size | |
3231 | field. */ | |
3232 | size = cris_get_size (inst); | |
3233 | operand2 = inst_env->reg[REG_PC]; | |
3234 | ||
3235 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3236 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3237 | operand3 = get_data_from_address (&inst, operand1); | |
3238 | ||
3239 | /* Calculate the PC value after the instruction, i.e. where the | |
3240 | breakpoint should be. The order of the udw_operands is vital. */ | |
3241 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3242 | } | |
3243 | /* If this is an autoincrement addressing mode, check if the increment | |
3244 | changes the PC. */ | |
3245 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3246 | { | |
3247 | /* Get the size field. */ | |
3248 | size = cris_get_size (inst); | |
3249 | ||
3250 | /* If it's an extend instruction we don't want the signed extend bit, | |
3251 | because it influences the size. */ | |
3252 | if (cris_get_opcode (inst) < 4) | |
3253 | { | |
3254 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3255 | } | |
3256 | process_autoincrement (size, inst, inst_env); | |
3257 | } | |
3258 | inst_env->slot_needed = 0; | |
3259 | inst_env->prefix_found = 0; | |
3260 | inst_env->xflag_found = 0; | |
3261 | inst_env->disable_interrupt = 0; | |
3262 | } | |
3263 | ||
3264 | /* Handles the two-operand addressing mode, all modes except register, for | |
3265 | the ADD, SUB CMP, AND and OR instruction. */ | |
3266 | ||
3267 | void | |
3268 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, | |
3269 | inst_env_type *inst_env) | |
3270 | { | |
3271 | if (inst_env->prefix_found) | |
3272 | { | |
3273 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3274 | { | |
3275 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3276 | } | |
3277 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3278 | { | |
3279 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3280 | } | |
3281 | else | |
3282 | { | |
3283 | /* The mode is invalid for a prefixed base instruction. */ | |
3284 | inst_env->invalid = 1; | |
3285 | return; | |
3286 | } | |
3287 | } | |
3288 | else | |
3289 | { | |
3290 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3291 | } | |
3292 | } | |
3293 | ||
3294 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3295 | ||
3296 | void | |
3297 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) | |
3298 | { | |
3299 | unsigned long operand1; | |
3300 | unsigned long operand2; | |
3301 | ||
3302 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3303 | instruction and can't have a prefix. */ | |
3304 | if (inst_env->prefix_found) | |
3305 | { | |
3306 | inst_env->invalid = 1; | |
3307 | return; | |
3308 | } | |
3309 | ||
3310 | /* Check if the instruction has PC as its target. */ | |
3311 | if (cris_get_operand2 (inst) == REG_PC) | |
3312 | { | |
3313 | if (inst_env->slot_needed) | |
3314 | { | |
3315 | inst_env->invalid = 1; | |
3316 | return; | |
3317 | } | |
3318 | operand1 = cris_get_quick_value (inst); | |
3319 | operand2 = inst_env->reg[REG_PC]; | |
3320 | ||
3321 | /* The size should now be dword. */ | |
3322 | cris_set_size_to_dword (&inst); | |
3323 | ||
3324 | /* Calculate the PC value after the instruction, i.e. where the | |
3325 | breakpoint should be. */ | |
3326 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3327 | } | |
3328 | inst_env->slot_needed = 0; | |
3329 | inst_env->prefix_found = 0; | |
3330 | inst_env->xflag_found = 0; | |
3331 | inst_env->disable_interrupt = 0; | |
3332 | } | |
3333 | ||
3334 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3335 | ||
3336 | void | |
3337 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) | |
3338 | { | |
3339 | unsigned long operand1; | |
3340 | unsigned long operand2; | |
3341 | ||
3342 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3343 | instruction and can't have a prefix. */ | |
3344 | if (inst_env->prefix_found) | |
3345 | { | |
3346 | inst_env->invalid = 1; | |
3347 | return; | |
3348 | } | |
3349 | /* Check if the instruction has PC as its target. */ | |
3350 | if (cris_get_operand2 (inst) == REG_PC) | |
3351 | { | |
3352 | if (inst_env->slot_needed) | |
3353 | { | |
3354 | inst_env->invalid = 1; | |
3355 | return; | |
3356 | } | |
3357 | /* The instruction has the PC as its target register. */ | |
3358 | operand1 = cris_get_quick_value (inst); | |
3359 | operand2 = inst_env->reg[REG_PC]; | |
3360 | ||
3361 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3362 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3363 | { | |
3364 | /* sign extend */ | |
3365 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3366 | } | |
3367 | /* The size should now be dword. */ | |
3368 | cris_set_size_to_dword (&inst); | |
3369 | ||
3370 | /* Calculate the PC value after the instruction, i.e. where the | |
3371 | breakpoint should be. */ | |
3372 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3373 | } | |
3374 | inst_env->slot_needed = 0; | |
3375 | inst_env->prefix_found = 0; | |
3376 | inst_env->xflag_found = 0; | |
3377 | inst_env->disable_interrupt = 0; | |
3378 | } | |
3379 | ||
3380 | /* Translate op_type to a function and call it. */ | |
3381 | ||
3382 | static void cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3383 | inst_env_type *inst_env) | |
3384 | { | |
3385 | switch (op_type) | |
3386 | { | |
3387 | case cris_not_implemented_op: | |
3388 | not_implemented_op (inst, inst_env); | |
3389 | break; | |
3390 | ||
3391 | case cris_abs_op: | |
3392 | abs_op (inst, inst_env); | |
3393 | break; | |
3394 | ||
3395 | case cris_addi_op: | |
3396 | addi_op (inst, inst_env); | |
3397 | break; | |
3398 | ||
3399 | case cris_asr_op: | |
3400 | asr_op (inst, inst_env); | |
3401 | break; | |
3402 | ||
3403 | case cris_asrq_op: | |
3404 | asrq_op (inst, inst_env); | |
3405 | break; | |
3406 | ||
3407 | case cris_ax_ei_setf_op: | |
3408 | ax_ei_setf_op (inst, inst_env); | |
3409 | break; | |
3410 | ||
3411 | case cris_bdap_prefix: | |
3412 | bdap_prefix (inst, inst_env); | |
3413 | break; | |
3414 | ||
3415 | case cris_biap_prefix: | |
3416 | biap_prefix (inst, inst_env); | |
3417 | break; | |
3418 | ||
3419 | case cris_break_op: | |
3420 | break_op (inst, inst_env); | |
3421 | break; | |
3422 | ||
3423 | case cris_btst_nop_op: | |
3424 | btst_nop_op (inst, inst_env); | |
3425 | break; | |
3426 | ||
3427 | case cris_clearf_di_op: | |
3428 | clearf_di_op (inst, inst_env); | |
3429 | break; | |
3430 | ||
3431 | case cris_dip_prefix: | |
3432 | dip_prefix (inst, inst_env); | |
3433 | break; | |
3434 | ||
3435 | case cris_dstep_logshift_mstep_neg_not_op: | |
3436 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3437 | break; | |
3438 | ||
3439 | case cris_eight_bit_offset_branch_op: | |
3440 | eight_bit_offset_branch_op (inst, inst_env); | |
3441 | break; | |
3442 | ||
3443 | case cris_move_mem_to_reg_movem_op: | |
3444 | move_mem_to_reg_movem_op (inst, inst_env); | |
3445 | break; | |
3446 | ||
3447 | case cris_move_reg_to_mem_movem_op: | |
3448 | move_reg_to_mem_movem_op (inst, inst_env); | |
3449 | break; | |
3450 | ||
3451 | case cris_move_to_preg_op: | |
3452 | move_to_preg_op (inst, inst_env); | |
3453 | break; | |
3454 | ||
3455 | case cris_muls_op: | |
3456 | muls_op (inst, inst_env); | |
3457 | break; | |
3458 | ||
3459 | case cris_mulu_op: | |
3460 | mulu_op (inst, inst_env); | |
3461 | break; | |
3462 | ||
3463 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3464 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3465 | break; | |
3466 | ||
3467 | case cris_none_reg_mode_clear_test_op: | |
3468 | none_reg_mode_clear_test_op (inst, inst_env); | |
3469 | break; | |
3470 | ||
3471 | case cris_none_reg_mode_jump_op: | |
3472 | none_reg_mode_jump_op (inst, inst_env); | |
3473 | break; | |
3474 | ||
3475 | case cris_none_reg_mode_move_from_preg_op: | |
3476 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3477 | break; | |
3478 | ||
3479 | case cris_quick_mode_add_sub_op: | |
3480 | quick_mode_add_sub_op (inst, inst_env); | |
3481 | break; | |
3482 | ||
3483 | case cris_quick_mode_and_cmp_move_or_op: | |
3484 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3485 | break; | |
3486 | ||
3487 | case cris_quick_mode_bdap_prefix: | |
3488 | quick_mode_bdap_prefix (inst, inst_env); | |
3489 | break; | |
3490 | ||
3491 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3492 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3493 | break; | |
3494 | ||
3495 | case cris_reg_mode_clear_op: | |
3496 | reg_mode_clear_op (inst, inst_env); | |
3497 | break; | |
3498 | ||
3499 | case cris_reg_mode_jump_op: | |
3500 | reg_mode_jump_op (inst, inst_env); | |
3501 | break; | |
3502 | ||
3503 | case cris_reg_mode_move_from_preg_op: | |
3504 | reg_mode_move_from_preg_op (inst, inst_env); | |
3505 | break; | |
3506 | ||
3507 | case cris_reg_mode_test_op: | |
3508 | reg_mode_test_op (inst, inst_env); | |
3509 | break; | |
3510 | ||
3511 | case cris_scc_op: | |
3512 | scc_op (inst, inst_env); | |
3513 | break; | |
3514 | ||
3515 | case cris_sixteen_bit_offset_branch_op: | |
3516 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3517 | break; | |
3518 | ||
3519 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3520 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3521 | break; | |
3522 | ||
3523 | case cris_three_operand_bound_op: | |
3524 | three_operand_bound_op (inst, inst_env); | |
3525 | break; | |
3526 | ||
3527 | case cris_two_operand_bound_op: | |
3528 | two_operand_bound_op (inst, inst_env); | |
3529 | break; | |
3530 | ||
3531 | case cris_xor_op: | |
3532 | xor_op (inst, inst_env); | |
3533 | break; | |
3534 | } | |
3535 | } | |
3536 | ||
3537 | /* This wrapper is to avoid cris_get_assembler being called before | |
3538 | exec_bfd has been set. */ | |
3539 | ||
3540 | static int | |
3541 | cris_delayed_get_disassembler (bfd_vma addr, disassemble_info *info) | |
3542 | { | |
3543 | tm_print_insn = cris_get_disassembler (exec_bfd); | |
2bf0cb65 | 3544 | return TARGET_PRINT_INSN (addr, info); |
29134980 OF |
3545 | } |
3546 | ||
3547 | void | |
3548 | _initialize_cris_tdep (void) | |
3549 | { | |
3550 | struct cmd_list_element *c; | |
3551 | ||
3552 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3553 | ||
3554 | /* Used in disassembly. */ | |
3555 | tm_print_insn = cris_delayed_get_disassembler; | |
3556 | ||
3557 | /* CRIS-specific user-commands. */ | |
3558 | c = add_set_cmd ("cris-version", class_support, var_integer, | |
3559 | (char *) &usr_cmd_cris_version, | |
3560 | "Set the current CRIS version.", &setlist); | |
3561 | c->function.sfunc = cris_version_update; | |
3562 | add_show_from_set (c, &showlist); | |
3563 | ||
3564 | c = add_set_enum_cmd ("cris-mode", class_support, cris_mode_enums, | |
3565 | &usr_cmd_cris_mode, | |
3566 | "Set the current CRIS mode.", &setlist); | |
3567 | c->function.sfunc = cris_mode_update; | |
3568 | add_show_from_set (c, &showlist); | |
3569 | ||
3570 | c = add_set_enum_cmd ("cris-abi", class_support, cris_abi_enums, | |
3571 | &usr_cmd_cris_abi, | |
3572 | "Set the current CRIS ABI version.", &setlist); | |
3573 | c->function.sfunc = cris_abi_update; | |
3574 | add_show_from_set (c, &showlist); | |
3575 | } | |
3576 | ||
3577 | /* Prints out all target specific values. */ | |
3578 | ||
3579 | static void | |
3580 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3581 | { | |
3582 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3583 | if (tdep != NULL) | |
3584 | { | |
3585 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3586 | tdep->cris_version); | |
3587 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", | |
3588 | tdep->cris_mode); | |
3589 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_abi = %s\n", | |
3590 | tdep->cris_abi); | |
3591 | ||
3592 | } | |
3593 | } | |
3594 | ||
3595 | static void | |
3596 | cris_version_update (char *ignore_args, int from_tty, | |
3597 | struct cmd_list_element *c) | |
3598 | { | |
3599 | struct gdbarch_info info; | |
3600 | ||
3601 | /* From here on, trust the user's CRIS version setting. */ | |
3602 | if (c->type == set_cmd) | |
3603 | { | |
3604 | usr_cmd_cris_version_valid = 1; | |
3605 | ||
3606 | /* Update the current architecture, if needed. */ | |
3607 | memset (&info, 0, sizeof info); | |
3608 | if (!gdbarch_update_p (info)) | |
3609 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3610 | } | |
3611 | } | |
3612 | ||
3613 | static void | |
3614 | cris_mode_update (char *ignore_args, int from_tty, | |
3615 | struct cmd_list_element *c) | |
3616 | { | |
3617 | struct gdbarch_info info; | |
3618 | ||
3619 | /* From here on, trust the user's CRIS mode setting. */ | |
3620 | if (c->type == set_cmd) | |
3621 | { | |
3622 | usr_cmd_cris_mode_valid = 1; | |
3623 | ||
3624 | /* Update the current architecture, if needed. */ | |
3625 | memset (&info, 0, sizeof info); | |
3626 | if (!gdbarch_update_p (info)) | |
3627 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3628 | } | |
3629 | } | |
3630 | ||
3631 | static void | |
3632 | cris_abi_update (char *ignore_args, int from_tty, | |
3633 | struct cmd_list_element *c) | |
3634 | { | |
3635 | struct gdbarch_info info; | |
3636 | ||
3637 | /* From here on, trust the user's CRIS ABI setting. */ | |
3638 | if (c->type == set_cmd) | |
3639 | { | |
3640 | usr_cmd_cris_abi_valid = 1; | |
3641 | ||
3642 | /* Update the current architecture, if needed. */ | |
3643 | memset (&info, 0, sizeof info); | |
3644 | if (!gdbarch_update_p (info)) | |
3645 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3646 | } | |
3647 | } | |
3648 | ||
3649 | /* Copied from pa64solib.c, with a couple of minor changes. */ | |
3650 | ||
3651 | static CORE_ADDR | |
3652 | bfd_lookup_symbol (bfd *abfd, const char *symname) | |
3653 | { | |
3654 | unsigned int storage_needed; | |
3655 | asymbol *sym; | |
3656 | asymbol **symbol_table; | |
3657 | unsigned int number_of_symbols; | |
3658 | unsigned int i; | |
3659 | struct cleanup *back_to; | |
3660 | CORE_ADDR symaddr = 0; | |
3661 | ||
3662 | storage_needed = bfd_get_symtab_upper_bound (abfd); | |
3663 | ||
3664 | if (storage_needed > 0) | |
3665 | { | |
3666 | symbol_table = (asymbol **) xmalloc (storage_needed); | |
3667 | back_to = make_cleanup (free, (PTR) symbol_table); | |
3668 | number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); | |
3669 | ||
3670 | for (i = 0; i < number_of_symbols; i++) | |
3671 | { | |
3672 | sym = *symbol_table++; | |
3673 | if (!strcmp (sym->name, symname)) | |
3674 | { | |
3675 | /* Bfd symbols are section relative. */ | |
3676 | symaddr = sym->value + sym->section->vma; | |
3677 | break; | |
3678 | } | |
3679 | } | |
3680 | do_cleanups (back_to); | |
3681 | } | |
3682 | return (symaddr); | |
3683 | } | |
3684 | ||
3685 | static struct gdbarch * | |
3686 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3687 | { | |
3688 | struct gdbarch *gdbarch; | |
3689 | struct gdbarch_tdep *tdep; | |
3690 | int cris_version; | |
3691 | const char *cris_mode; | |
3692 | const char *cris_abi; | |
3693 | CORE_ADDR cris_abi_sym = 0; | |
3694 | int register_bytes; | |
3695 | ||
3696 | if (usr_cmd_cris_version_valid) | |
3697 | { | |
3698 | /* Trust the user's CRIS version setting. */ | |
3699 | cris_version = usr_cmd_cris_version; | |
3700 | } | |
3701 | else | |
3702 | { | |
3703 | /* Assume it's CRIS version 10. */ | |
3704 | cris_version = 10; | |
3705 | } | |
3706 | ||
3707 | if (usr_cmd_cris_mode_valid) | |
3708 | { | |
3709 | /* Trust the user's CRIS mode setting. */ | |
3710 | cris_mode = usr_cmd_cris_mode; | |
3711 | } | |
3712 | else if (cris_version == 10) | |
3713 | { | |
3714 | /* Assume CRIS version 10 is in user mode. */ | |
3715 | cris_mode = CRIS_MODE_USER; | |
3716 | } | |
3717 | else | |
3718 | { | |
3719 | /* Strictly speaking, older CRIS version don't have a supervisor mode, | |
3720 | but we regard its only mode as supervisor mode. */ | |
3721 | cris_mode = CRIS_MODE_SUPERVISOR; | |
3722 | } | |
3723 | ||
3724 | if (usr_cmd_cris_abi_valid) | |
3725 | { | |
3726 | /* Trust the user's ABI setting. */ | |
3727 | cris_abi = usr_cmd_cris_abi; | |
3728 | } | |
3729 | else if (info.abfd) | |
3730 | { | |
3731 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3732 | { | |
3733 | /* An elf target uses the new ABI. */ | |
3734 | cris_abi = CRIS_ABI_V2; | |
3735 | } | |
3736 | else if (bfd_get_flavour (info.abfd) == bfd_target_aout_flavour) | |
3737 | { | |
3738 | /* An a.out target may use either ABI. Look for hints in the | |
3739 | symbol table. */ | |
3740 | cris_abi_sym = bfd_lookup_symbol (info.abfd, CRIS_ABI_SYMBOL); | |
3741 | cris_abi = cris_abi_sym ? CRIS_ABI_V2 : CRIS_ABI_ORIGINAL; | |
3742 | } | |
3743 | else | |
3744 | { | |
3745 | /* Unknown bfd flavour. Assume it's the new ABI. */ | |
3746 | cris_abi = CRIS_ABI_V2; | |
3747 | } | |
3748 | } | |
3749 | else if (gdbarch_tdep (current_gdbarch)) | |
3750 | { | |
3751 | /* No bfd available. Stick with whatever ABI we're currently using. | |
3752 | (This is to avoid changing the ABI when the user updates the | |
3753 | architecture with the 'set cris-version' command.) */ | |
3754 | cris_abi = gdbarch_tdep (current_gdbarch)->cris_abi; | |
3755 | } | |
3756 | else | |
3757 | { | |
3758 | /* No bfd, and no current architecture available. Assume it's the | |
3759 | new ABI. */ | |
3760 | cris_abi = CRIS_ABI_V2; | |
3761 | } | |
3762 | ||
3763 | /* Make the current settings visible to the user. */ | |
3764 | usr_cmd_cris_version = cris_version; | |
3765 | usr_cmd_cris_mode = cris_mode; | |
3766 | usr_cmd_cris_abi = cris_abi; | |
3767 | ||
3768 | /* Find a candidate among the list of pre-declared architectures. Both | |
3769 | CRIS version and ABI must match. */ | |
3770 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3771 | arches != NULL; | |
3772 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3773 | { | |
3774 | if ((gdbarch_tdep (arches->gdbarch)->cris_version == cris_version) | |
3775 | && (gdbarch_tdep (arches->gdbarch)->cris_mode == cris_mode) | |
3776 | && (gdbarch_tdep (arches->gdbarch)->cris_abi == cris_abi)) | |
3777 | return arches->gdbarch; | |
3778 | } | |
3779 | ||
3780 | /* No matching architecture was found. Create a new one. */ | |
3781 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3782 | gdbarch = gdbarch_alloc (&info, tdep); | |
3783 | ||
3784 | tdep->cris_version = cris_version; | |
3785 | tdep->cris_mode = cris_mode; | |
3786 | tdep->cris_abi = cris_abi; | |
3787 | ||
3788 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
3789 | switch (info.byte_order) | |
3790 | { | |
3791 | case LITTLE_ENDIAN: | |
3792 | /* Ok. */ | |
3793 | break; | |
3794 | ||
3795 | case BIG_ENDIAN: | |
3796 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); | |
3797 | break; | |
3798 | ||
3799 | default: | |
3800 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); | |
3801 | } | |
3802 | ||
3803 | /* Initialize the ABI dependent things. */ | |
3804 | if (tdep->cris_abi == CRIS_ABI_ORIGINAL) | |
3805 | { | |
3806 | set_gdbarch_double_bit (gdbarch, 32); | |
3807 | set_gdbarch_push_arguments (gdbarch, cris_abi_original_push_arguments); | |
3808 | set_gdbarch_store_return_value (gdbarch, | |
3809 | cris_abi_original_store_return_value); | |
3810 | set_gdbarch_extract_return_value | |
3811 | (gdbarch, cris_abi_original_extract_return_value); | |
3812 | set_gdbarch_reg_struct_has_addr | |
3813 | (gdbarch, cris_abi_original_reg_struct_has_addr); | |
3814 | } | |
3815 | else if (tdep->cris_abi == CRIS_ABI_V2) | |
3816 | { | |
3817 | set_gdbarch_double_bit (gdbarch, 64); | |
3818 | set_gdbarch_push_arguments (gdbarch, cris_abi_v2_push_arguments); | |
3819 | set_gdbarch_store_return_value (gdbarch, cris_abi_v2_store_return_value); | |
3820 | set_gdbarch_extract_return_value (gdbarch, | |
3821 | cris_abi_v2_extract_return_value); | |
3822 | set_gdbarch_reg_struct_has_addr (gdbarch, | |
3823 | cris_abi_v2_reg_struct_has_addr); | |
3824 | } | |
3825 | else | |
3826 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS ABI"); | |
3827 | ||
3828 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
3829 | which means we have to set this explicitly. */ | |
3830 | set_gdbarch_long_double_bit (gdbarch, 64); | |
3831 | ||
3832 | /* Floating point is IEEE compatible. */ | |
3833 | set_gdbarch_ieee_float (gdbarch, 1); | |
3834 | ||
3835 | /* There are 32 registers (some of which may not be implemented). */ | |
3836 | set_gdbarch_num_regs (gdbarch, 32); | |
3837 | set_gdbarch_sp_regnum (gdbarch, 14); | |
3838 | set_gdbarch_fp_regnum (gdbarch, 8); | |
3839 | set_gdbarch_pc_regnum (gdbarch, 15); | |
3840 | ||
3841 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
3842 | ||
3843 | /* Length of ordinary registers used in push_word and a few other places. | |
3844 | REGISTER_RAW_SIZE is the real way to know how big a register is. */ | |
3845 | set_gdbarch_register_size (gdbarch, 4); | |
3846 | ||
3847 | /* NEW */ | |
3848 | set_gdbarch_register_bytes_ok (gdbarch, cris_register_bytes_ok); | |
3849 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
3850 | ||
3851 | ||
3852 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
3853 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
3854 | ||
3855 | ||
3856 | /* The total amount of space needed to store (in an array called registers) | |
3857 | GDB's copy of the machine's register state. Note: We can not use | |
3858 | cris_register_size at this point, since it relies on current_gdbarch | |
3859 | being set. */ | |
3860 | switch (tdep->cris_version) | |
3861 | { | |
3862 | case 0: | |
3863 | case 1: | |
3864 | case 2: | |
3865 | case 3: | |
3866 | /* Support for these may be added later. */ | |
3867 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unsupported CRIS version"); | |
3868 | break; | |
3869 | ||
3870 | case 8: | |
3871 | case 9: | |
3872 | /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15 | |
3873 | (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits), | |
3874 | and P8 - P14 (32 bits). */ | |
3875 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4); | |
3876 | break; | |
3877 | ||
3878 | case 10: | |
3879 | case 11: | |
3880 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
3881 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
3882 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4); | |
3883 | break; | |
3884 | ||
3885 | default: | |
3886 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version"); | |
3887 | } | |
3888 | ||
3889 | set_gdbarch_register_bytes (gdbarch, register_bytes); | |
3890 | ||
3891 | /* Returns the register offset for the first byte of register regno's space | |
3892 | in the saved register state. */ | |
3893 | set_gdbarch_register_byte (gdbarch, cris_register_offset); | |
3894 | ||
3895 | /* The length of the registers in the actual machine representation. */ | |
3896 | set_gdbarch_register_raw_size (gdbarch, cris_register_size); | |
3897 | ||
3898 | /* The largest value REGISTER_RAW_SIZE can have. */ | |
3899 | set_gdbarch_max_register_raw_size (gdbarch, 32); | |
3900 | ||
3901 | /* The length of the registers in the program's representation. */ | |
3902 | set_gdbarch_register_virtual_size (gdbarch, cris_register_size); | |
3903 | ||
3904 | /* The largest value REGISTER_VIRTUAL_SIZE can have. */ | |
3905 | set_gdbarch_max_register_virtual_size (gdbarch, 32); | |
3906 | ||
3907 | set_gdbarch_register_virtual_type (gdbarch, cris_register_virtual_type); | |
3908 | ||
3909 | /* Use generic dummy frames. */ | |
3910 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
3911 | ||
3912 | /* Where to execute the call in the memory segments. */ | |
3913 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
3914 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
3915 | ||
3916 | /* Start execution at the beginning of dummy. */ | |
3917 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
3918 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
3919 | ||
3920 | /* Set to 1 since call_dummy_breakpoint_offset was defined. */ | |
3921 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
3922 | ||
3923 | /* Read all about dummy frames in blockframe.c. */ | |
3924 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
3925 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
3926 | ||
3927 | /* Defined to 1 to indicate that the target supports inferior function | |
3928 | calls. */ | |
3929 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
3930 | set_gdbarch_call_dummy_words (gdbarch, 0); | |
3931 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
3932 | ||
3933 | /* No stack adjustment needed when peforming an inferior function call. */ | |
3934 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
3935 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
3936 | ||
3937 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
3938 | ||
3939 | /* No register requires conversion from raw format to virtual format. */ | |
3940 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
3941 | ||
3942 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
3943 | set_gdbarch_push_return_address (gdbarch, cris_push_return_address); | |
3944 | set_gdbarch_pop_frame (gdbarch, cris_pop_frame); | |
3945 | ||
3946 | set_gdbarch_store_struct_return (gdbarch, cris_store_struct_return); | |
3947 | set_gdbarch_extract_struct_value_address (gdbarch, | |
3948 | cris_extract_struct_value_address); | |
3949 | set_gdbarch_use_struct_convention (gdbarch, cris_use_struct_convention); | |
3950 | ||
3951 | set_gdbarch_frame_init_saved_regs (gdbarch, cris_frame_init_saved_regs); | |
3952 | set_gdbarch_init_extra_frame_info (gdbarch, cris_init_extra_frame_info); | |
3953 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); | |
3954 | set_gdbarch_prologue_frameless_p (gdbarch, generic_prologue_frameless_p); | |
3955 | ||
3956 | /* The stack grows downward. */ | |
3957 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3958 | ||
3959 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
3960 | ||
3961 | /* The PC must not be decremented after a breakpoint. (The breakpoint | |
3962 | handler takes care of that.) */ | |
3963 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3964 | ||
3965 | /* Offset from address of function to start of its code. */ | |
3966 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3967 | ||
3968 | /* The number of bytes at the start of arglist that are not really args, | |
3969 | 0 in the CRIS ABI. */ | |
3970 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3971 | set_gdbarch_frameless_function_invocation | |
3972 | (gdbarch, cris_frameless_function_invocation); | |
3973 | set_gdbarch_frame_chain (gdbarch, cris_frame_chain); | |
3974 | set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid); | |
3975 | ||
3976 | set_gdbarch_frame_saved_pc (gdbarch, cris_frame_saved_pc); | |
3977 | set_gdbarch_frame_args_address (gdbarch, cris_frame_args_address); | |
3978 | set_gdbarch_frame_locals_address (gdbarch, cris_frame_locals_address); | |
3979 | set_gdbarch_saved_pc_after_call (gdbarch, cris_saved_pc_after_call); | |
3980 | ||
3981 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
3982 | ||
3983 | /* No extra stack alignment needed. Set to 1 by default. */ | |
3984 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); | |
3985 | ||
3986 | /* Helpful for backtracing and returning in a call dummy. */ | |
3987 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
3988 | ||
3989 | return gdbarch; | |
3990 | } |