Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
23 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
24 | Boston, MA 02110-1301, USA. */ | |
29134980 OF |
25 | |
26 | #include "defs.h" | |
27 | #include "frame.h" | |
2e4b5889 OF |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
30 | #include "trad-frame.h" | |
31 | #include "dwarf2-frame.h" | |
29134980 OF |
32 | #include "symtab.h" |
33 | #include "inferior.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "gdbcore.h" | |
36 | #include "gdbcmd.h" | |
37 | #include "target.h" | |
38 | #include "value.h" | |
39 | #include "opcode/cris.h" | |
40 | #include "arch-utils.h" | |
41 | #include "regcache.h" | |
36482093 | 42 | #include "gdb_assert.h" |
29134980 OF |
43 | |
44 | /* To get entry_point_address. */ | |
9ab9195f | 45 | #include "objfiles.h" |
29134980 | 46 | |
a5f6c8f5 | 47 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 48 | #include "solib-svr4.h" |
9bbe19fb | 49 | #include "gdb_string.h" |
a89aa300 | 50 | #include "dis-asm.h" |
dbbff683 | 51 | |
29134980 OF |
52 | enum cris_num_regs |
53 | { | |
54 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
55 | NUM_FREGS = 0, | |
56 | ||
57 | /* There are 16 general registers. */ | |
58 | NUM_GENREGS = 16, | |
59 | ||
60 | /* There are 16 special registers. */ | |
c600d464 OF |
61 | NUM_SPECREGS = 16, |
62 | ||
63 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
64 | ||
65 | /* CRISv32 has 16 support registers. */ | |
66 | NUM_SUPPREGS = 16 | |
29134980 OF |
67 | }; |
68 | ||
69 | /* Register numbers of various important registers. | |
2e4b5889 | 70 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
71 | STR_REGNUM Contains the address of structure return values. |
72 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
73 | ARG1_REGNUM Contains the first parameter to a function. | |
74 | ARG2_REGNUM Contains the second parameter to a function. | |
75 | ARG3_REGNUM Contains the third parameter to a function. | |
76 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
3e8c568d UW |
77 | gdbarch_sp_regnum Contains address of top of stack. |
78 | gdbarch_pc_regnum Contains address of next instruction. | |
29134980 OF |
79 | SRP_REGNUM Subroutine return pointer register. |
80 | BRP_REGNUM Breakpoint return pointer register. */ | |
81 | ||
29134980 OF |
82 | enum cris_regnums |
83 | { | |
84 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 85 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 86 | CRIS_FP_REGNUM = 8, |
c600d464 | 87 | /* ABI related registers. */ |
29134980 OF |
88 | STR_REGNUM = 9, |
89 | RET_REGNUM = 10, | |
90 | ARG1_REGNUM = 10, | |
91 | ARG2_REGNUM = 11, | |
92 | ARG3_REGNUM = 12, | |
93 | ARG4_REGNUM = 13, | |
94 | ||
c600d464 | 95 | /* Registers which happen to be common. */ |
29134980 | 96 | VR_REGNUM = 17, |
c600d464 OF |
97 | MOF_REGNUM = 23, |
98 | SRP_REGNUM = 27, | |
99 | ||
100 | /* CRISv10 et. al. specific registers. */ | |
101 | P0_REGNUM = 16, | |
29134980 OF |
102 | P4_REGNUM = 20, |
103 | CCR_REGNUM = 21, | |
29134980 OF |
104 | P8_REGNUM = 24, |
105 | IBR_REGNUM = 25, | |
106 | IRP_REGNUM = 26, | |
29134980 | 107 | BAR_REGNUM = 28, |
2a9ecef2 | 108 | DCCR_REGNUM = 29, |
29134980 | 109 | BRP_REGNUM = 30, |
c600d464 OF |
110 | USP_REGNUM = 31, |
111 | ||
112 | /* CRISv32 specific registers. */ | |
113 | ACR_REGNUM = 15, | |
114 | BZ_REGNUM = 16, | |
115 | PID_REGNUM = 18, | |
116 | SRS_REGNUM = 19, | |
117 | WZ_REGNUM = 20, | |
118 | EXS_REGNUM = 21, | |
119 | EDA_REGNUM = 22, | |
120 | DZ_REGNUM = 24, | |
121 | EBP_REGNUM = 25, | |
122 | ERP_REGNUM = 26, | |
123 | NRP_REGNUM = 28, | |
124 | CCS_REGNUM = 29, | |
125 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
126 | SPC_REGNUM = 31, | |
127 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
128 | ||
129 | S0_REGNUM = 33, | |
130 | S1_REGNUM = 34, | |
131 | S2_REGNUM = 35, | |
132 | S3_REGNUM = 36, | |
133 | S4_REGNUM = 37, | |
134 | S5_REGNUM = 38, | |
135 | S6_REGNUM = 39, | |
136 | S7_REGNUM = 40, | |
137 | S8_REGNUM = 41, | |
138 | S9_REGNUM = 42, | |
139 | S10_REGNUM = 43, | |
140 | S11_REGNUM = 44, | |
141 | S12_REGNUM = 45, | |
142 | S13_REGNUM = 46, | |
143 | S14_REGNUM = 47, | |
144 | S15_REGNUM = 48, | |
29134980 OF |
145 | }; |
146 | ||
147 | extern const struct cris_spec_reg cris_spec_regs[]; | |
148 | ||
149 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
150 | register names and sizes. */ |
151 | static int usr_cmd_cris_version; | |
29134980 OF |
152 | |
153 | /* Indicates whether to trust the above variable. */ | |
154 | static int usr_cmd_cris_version_valid = 0; | |
155 | ||
41922353 OF |
156 | static const char cris_mode_normal[] = "normal"; |
157 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
158 | static const char *cris_modes[] = { |
159 | cris_mode_normal, | |
160 | cris_mode_guru, | |
161 | 0 | |
162 | }; | |
163 | ||
164 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
165 | type of break instruction among other things. */ | |
166 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
167 | ||
a5f6c8f5 OF |
168 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
169 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 170 | |
29134980 OF |
171 | /* CRIS architecture specific information. */ |
172 | struct gdbarch_tdep | |
173 | { | |
0e6bdb31 OF |
174 | int cris_version; |
175 | const char *cris_mode; | |
a5f6c8f5 | 176 | int cris_dwarf2_cfi; |
29134980 OF |
177 | }; |
178 | ||
179 | /* Functions for accessing target dependent data. */ | |
180 | ||
181 | static int | |
182 | cris_version (void) | |
183 | { | |
184 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
185 | } | |
186 | ||
0e6bdb31 OF |
187 | static const char * |
188 | cris_mode (void) | |
189 | { | |
190 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
191 | } | |
192 | ||
a5f6c8f5 OF |
193 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
194 | ||
195 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
196 | #define SIGTRAMP_OFFSET0 0 | |
197 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
198 | #define SIGTRAMP_OFFSET1 4 | |
199 | ||
200 | static const unsigned short sigtramp_code[] = | |
201 | { | |
202 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
203 | SIGTRAMP_INSN1 /* break 13 */ | |
204 | }; | |
205 | ||
206 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
207 | ||
208 | /* Note: same length as normal sigtramp code. */ | |
209 | ||
210 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 211 | { |
a5f6c8f5 OF |
212 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
213 | SIGTRAMP_INSN1 /* break 13 */ | |
214 | }; | |
215 | ||
216 | /* If PC is in a sigtramp routine, return the address of the start of | |
217 | the routine. Otherwise, return 0. */ | |
218 | ||
219 | static CORE_ADDR | |
220 | cris_sigtramp_start (struct frame_info *next_frame) | |
221 | { | |
222 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 223 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
224 | |
225 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
226 | return 0; | |
227 | ||
e2a2a3e8 | 228 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 229 | { |
e2a2a3e8 | 230 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
231 | return 0; |
232 | ||
233 | pc -= SIGTRAMP_OFFSET1; | |
234 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
235 | return 0; | |
236 | } | |
237 | ||
238 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
239 | return 0; | |
240 | ||
241 | return pc; | |
242 | } | |
243 | ||
244 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
245 | the routine. Otherwise, return 0. */ | |
246 | ||
247 | static CORE_ADDR | |
248 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
249 | { | |
250 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 251 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
252 | |
253 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
254 | return 0; | |
255 | ||
e2a2a3e8 | 256 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 257 | { |
e2a2a3e8 | 258 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
259 | return 0; |
260 | ||
261 | pc -= SIGTRAMP_OFFSET1; | |
262 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
263 | return 0; | |
264 | } | |
265 | ||
266 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
267 | return 0; | |
268 | ||
269 | return pc; | |
270 | } | |
271 | ||
272 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
273 | routine, return the address of the associated sigcontext structure. */ | |
274 | ||
275 | static CORE_ADDR | |
276 | cris_sigcontext_addr (struct frame_info *next_frame) | |
277 | { | |
278 | CORE_ADDR pc; | |
279 | CORE_ADDR sp; | |
280 | char buf[4]; | |
281 | ||
3e8c568d | 282 | frame_unwind_register (next_frame, gdbarch_sp_regnum (current_gdbarch), buf); |
a5f6c8f5 OF |
283 | sp = extract_unsigned_integer (buf, 4); |
284 | ||
285 | /* Look for normal sigtramp frame first. */ | |
286 | pc = cris_sigtramp_start (next_frame); | |
287 | if (pc) | |
288 | { | |
289 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
290 | struct sigcontext as its first member, meaning the SP points to | |
291 | it already. */ | |
292 | return sp; | |
293 | } | |
294 | ||
295 | pc = cris_rt_sigtramp_start (next_frame); | |
296 | if (pc) | |
297 | { | |
298 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
299 | a struct ucontext, which in turn contains a struct sigcontext. | |
300 | Magic digging: | |
301 | 4 + 4 + 128 to struct ucontext, then | |
302 | 4 + 4 + 12 to struct sigcontext. */ | |
303 | return (sp + 156); | |
304 | } | |
305 | ||
8a3fe4f8 | 306 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 307 | return 0; |
29134980 OF |
308 | } |
309 | ||
2e4b5889 | 310 | struct cris_unwind_cache |
29134980 | 311 | { |
2e4b5889 OF |
312 | /* The previous frame's inner most stack address. Used as this |
313 | frame ID's stack_addr. */ | |
314 | CORE_ADDR prev_sp; | |
315 | /* The frame's base, optionally used by the high-level debug info. */ | |
316 | CORE_ADDR base; | |
317 | int size; | |
318 | /* How far the SP and r8 (FP) have been offset from the start of | |
319 | the stack frame (as defined by the previous frame's stack | |
320 | pointer). */ | |
321 | LONGEST sp_offset; | |
322 | LONGEST r8_offset; | |
323 | int uses_frame; | |
324 | ||
325 | /* From old frame_extra_info struct. */ | |
29134980 OF |
326 | CORE_ADDR return_pc; |
327 | int leaf_function; | |
2e4b5889 OF |
328 | |
329 | /* Table indicating the location of each and every register. */ | |
330 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
331 | }; |
332 | ||
a5f6c8f5 OF |
333 | static struct cris_unwind_cache * |
334 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
335 | void **this_cache) | |
336 | { | |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
338 | struct cris_unwind_cache *info; | |
339 | CORE_ADDR pc; | |
340 | CORE_ADDR sp; | |
341 | CORE_ADDR addr; | |
342 | char buf[4]; | |
343 | int i; | |
344 | ||
345 | if ((*this_cache)) | |
346 | return (*this_cache); | |
347 | ||
348 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
349 | (*this_cache) = info; | |
350 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
351 | ||
352 | /* Zero all fields. */ | |
353 | info->prev_sp = 0; | |
354 | info->base = 0; | |
355 | info->size = 0; | |
356 | info->sp_offset = 0; | |
357 | info->r8_offset = 0; | |
358 | info->uses_frame = 0; | |
359 | info->return_pc = 0; | |
360 | info->leaf_function = 0; | |
361 | ||
3e8c568d | 362 | frame_unwind_register (next_frame, gdbarch_sp_regnum (current_gdbarch), buf); |
a5f6c8f5 OF |
363 | info->base = extract_unsigned_integer (buf, 4); |
364 | ||
365 | addr = cris_sigcontext_addr (next_frame); | |
366 | ||
367 | /* Layout of the sigcontext struct: | |
368 | struct sigcontext { | |
369 | struct pt_regs regs; | |
370 | unsigned long oldmask; | |
371 | unsigned long usp; | |
372 | }; */ | |
373 | ||
c600d464 OF |
374 | if (tdep->cris_version == 10) |
375 | { | |
376 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
377 | struct pt_regs. */ | |
378 | for (i = 0; i <= 13; i++) | |
379 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
380 | ||
381 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
382 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
383 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
384 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
385 | it though since that will mean that the backtrace will show a PC | |
386 | different from what is shown when stopped. */ | |
387 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
3e8c568d UW |
388 | info->saved_regs[gdbarch_pc_regnum (current_gdbarch)] |
389 | = info->saved_regs[IRP_REGNUM]; | |
390 | info->saved_regs[gdbarch_sp_regnum (current_gdbarch)].addr | |
391 | = addr + (24 * 4); | |
c600d464 OF |
392 | } |
393 | else | |
394 | { | |
395 | /* CRISv32. */ | |
396 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
397 | struct pt_regs. */ | |
398 | for (i = 0; i <= 13; i++) | |
399 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
400 | ||
401 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
402 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
403 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
404 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
405 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
406 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
407 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
408 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
409 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
410 | ||
411 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
412 | be wrong at this point. This problem manifests itself in the | |
413 | sigaltstack.exp test case, which occasionally generates FAILs when | |
414 | the signal is received while in a delay slot. | |
415 | ||
416 | This could be solved by a couple of read_memory_unsigned_integer and a | |
417 | trad_frame_set_value. */ | |
3e8c568d UW |
418 | info->saved_regs[gdbarch_pc_regnum (current_gdbarch)] |
419 | = info->saved_regs[ERP_REGNUM]; | |
c600d464 | 420 | |
3e8c568d UW |
421 | info->saved_regs[gdbarch_sp_regnum (current_gdbarch)].addr |
422 | = addr + (25 * 4); | |
c600d464 | 423 | } |
a5f6c8f5 OF |
424 | |
425 | return info; | |
426 | } | |
427 | ||
428 | static void | |
429 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
430 | struct frame_id *this_id) | |
431 | { | |
432 | struct cris_unwind_cache *cache = | |
433 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
434 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
435 | } | |
436 | ||
437 | /* Forward declaration. */ | |
438 | ||
439 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
440 | void **this_prologue_cache, | |
441 | int regnum, int *optimizedp, | |
442 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 443 | int *realnump, gdb_byte *bufferp); |
a5f6c8f5 OF |
444 | static void |
445 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
446 | void **this_cache, | |
447 | int regnum, int *optimizedp, | |
448 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 449 | int *realnump, gdb_byte *valuep) |
a5f6c8f5 OF |
450 | { |
451 | /* Make sure we've initialized the cache. */ | |
452 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
453 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
454 | optimizedp, lvalp, addrp, realnump, valuep); | |
455 | } | |
456 | ||
457 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
458 | { | |
459 | SIGTRAMP_FRAME, | |
460 | cris_sigtramp_frame_this_id, | |
461 | cris_sigtramp_frame_prev_register | |
462 | }; | |
463 | ||
464 | static const struct frame_unwind * | |
465 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
466 | { | |
467 | if (cris_sigtramp_start (next_frame) | |
468 | || cris_rt_sigtramp_start (next_frame)) | |
469 | return &cris_sigtramp_frame_unwind; | |
470 | ||
471 | return NULL; | |
472 | } | |
473 | ||
c600d464 OF |
474 | int |
475 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
476 | struct frame_info *this_frame) | |
477 | { | |
478 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
479 | ULONGEST erp; | |
480 | int ret = 0; | |
481 | char buf[4]; | |
482 | ||
0e6bdb31 OF |
483 | if (cris_mode () == cris_mode_guru) |
484 | { | |
485 | frame_unwind_register (this_frame, NRP_REGNUM, buf); | |
486 | } | |
487 | else | |
488 | { | |
489 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
490 | } | |
491 | ||
c600d464 OF |
492 | erp = extract_unsigned_integer (buf, 4); |
493 | ||
494 | if (erp & 0x1) | |
495 | { | |
496 | /* In delay slot - check if there's a breakpoint at the preceding | |
497 | instruction. */ | |
498 | if (breakpoint_here_p (erp & ~0x1)) | |
499 | ret = 1; | |
500 | } | |
501 | return ret; | |
502 | } | |
503 | ||
504 | /* Hardware watchpoint support. */ | |
505 | ||
506 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
507 | (any combination of read/write is fine). */ | |
508 | ||
509 | int | |
510 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
511 | { | |
512 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
513 | ||
514 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
515 | ||
516 | if (tdep->cris_version != 32) | |
517 | return 0; | |
518 | else | |
519 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
520 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
521 | || type == bp_hardware_watchpoint) && count <= 6) | |
522 | || (type == bp_hardware_breakpoint && count <= 1)); | |
523 | } | |
524 | ||
525 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
526 | which have no alignment or length restrictions. */ | |
527 | ||
528 | int | |
529 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
530 | { | |
531 | return 1; | |
532 | } | |
533 | ||
534 | /* If the inferior has some watchpoint that triggered, return the | |
535 | address associated with that watchpoint. Otherwise, return | |
536 | zero. */ | |
537 | ||
538 | CORE_ADDR | |
539 | cris_stopped_data_address (void) | |
540 | { | |
541 | CORE_ADDR eda; | |
1b5a9a8f | 542 | eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM); |
c600d464 OF |
543 | return eda; |
544 | } | |
545 | ||
29134980 | 546 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 547 | |
29134980 OF |
548 | typedef |
549 | struct instruction_environment | |
550 | { | |
551 | unsigned long reg[NUM_GENREGS]; | |
552 | unsigned long preg[NUM_SPECREGS]; | |
553 | unsigned long branch_break_address; | |
554 | unsigned long delay_slot_pc; | |
555 | unsigned long prefix_value; | |
556 | int branch_found; | |
557 | int prefix_found; | |
558 | int invalid; | |
559 | int slot_needed; | |
560 | int delay_slot_pc_active; | |
561 | int xflag_found; | |
562 | int disable_interrupt; | |
563 | } inst_env_type; | |
564 | ||
29134980 OF |
565 | /* Machine-dependencies in CRIS for opcodes. */ |
566 | ||
567 | /* Instruction sizes. */ | |
568 | enum cris_instruction_sizes | |
569 | { | |
570 | INST_BYTE_SIZE = 0, | |
571 | INST_WORD_SIZE = 1, | |
572 | INST_DWORD_SIZE = 2 | |
573 | }; | |
574 | ||
575 | /* Addressing modes. */ | |
576 | enum cris_addressing_modes | |
577 | { | |
578 | REGISTER_MODE = 1, | |
579 | INDIRECT_MODE = 2, | |
580 | AUTOINC_MODE = 3 | |
581 | }; | |
582 | ||
583 | /* Prefix addressing modes. */ | |
584 | enum cris_prefix_addressing_modes | |
585 | { | |
586 | PREFIX_INDEX_MODE = 2, | |
587 | PREFIX_ASSIGN_MODE = 3, | |
588 | ||
589 | /* Handle immediate byte offset addressing mode prefix format. */ | |
590 | PREFIX_OFFSET_MODE = 2 | |
591 | }; | |
592 | ||
593 | /* Masks for opcodes. */ | |
594 | enum cris_opcode_masks | |
595 | { | |
596 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
597 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
598 | SIGNED_BYTE_MASK = 0x80, | |
599 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
600 | SIGNED_WORD_MASK = 0x8000, | |
601 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
602 | SIGNED_DWORD_MASK = 0x80000000, | |
603 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
604 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
605 | }; | |
606 | ||
607 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
608 | Bit 15 - 12 Operand2 | |
609 | 11 - 10 Mode | |
610 | 9 - 6 Opcode | |
611 | 5 - 4 Size | |
612 | 3 - 0 Operand1 */ | |
613 | ||
614 | static int | |
615 | cris_get_operand2 (unsigned short insn) | |
616 | { | |
617 | return ((insn & 0xF000) >> 12); | |
618 | } | |
619 | ||
620 | static int | |
621 | cris_get_mode (unsigned short insn) | |
622 | { | |
623 | return ((insn & 0x0C00) >> 10); | |
624 | } | |
625 | ||
626 | static int | |
627 | cris_get_opcode (unsigned short insn) | |
628 | { | |
629 | return ((insn & 0x03C0) >> 6); | |
630 | } | |
631 | ||
632 | static int | |
633 | cris_get_size (unsigned short insn) | |
634 | { | |
635 | return ((insn & 0x0030) >> 4); | |
636 | } | |
637 | ||
638 | static int | |
639 | cris_get_operand1 (unsigned short insn) | |
640 | { | |
641 | return (insn & 0x000F); | |
642 | } | |
643 | ||
644 | /* Additional functions in order to handle opcodes. */ | |
645 | ||
29134980 OF |
646 | static int |
647 | cris_get_quick_value (unsigned short insn) | |
648 | { | |
649 | return (insn & 0x003F); | |
650 | } | |
651 | ||
652 | static int | |
653 | cris_get_bdap_quick_offset (unsigned short insn) | |
654 | { | |
655 | return (insn & 0x00FF); | |
656 | } | |
657 | ||
658 | static int | |
659 | cris_get_branch_short_offset (unsigned short insn) | |
660 | { | |
661 | return (insn & 0x00FF); | |
662 | } | |
663 | ||
664 | static int | |
665 | cris_get_asr_shift_steps (unsigned long value) | |
666 | { | |
667 | return (value & 0x3F); | |
668 | } | |
669 | ||
29134980 OF |
670 | static int |
671 | cris_get_clear_size (unsigned short insn) | |
672 | { | |
673 | return ((insn) & 0xC000); | |
674 | } | |
675 | ||
676 | static int | |
677 | cris_is_signed_extend_bit_on (unsigned short insn) | |
678 | { | |
679 | return (((insn) & 0x20) == 0x20); | |
680 | } | |
681 | ||
682 | static int | |
683 | cris_is_xflag_bit_on (unsigned short insn) | |
684 | { | |
685 | return (((insn) & 0x1000) == 0x1000); | |
686 | } | |
687 | ||
688 | static void | |
689 | cris_set_size_to_dword (unsigned short *insn) | |
690 | { | |
691 | *insn &= 0xFFCF; | |
692 | *insn |= 0x20; | |
693 | } | |
694 | ||
8535cb38 | 695 | static signed char |
29134980 OF |
696 | cris_get_signed_offset (unsigned short insn) |
697 | { | |
8535cb38 | 698 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
699 | } |
700 | ||
701 | /* Calls an op function given the op-type, working on the insn and the | |
702 | inst_env. */ | |
703 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
704 | ||
29134980 OF |
705 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
706 | struct gdbarch_list *); | |
707 | ||
29134980 OF |
708 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
709 | ||
a5f6c8f5 OF |
710 | static void set_cris_version (char *ignore_args, int from_tty, |
711 | struct cmd_list_element *c); | |
29134980 | 712 | |
0e6bdb31 OF |
713 | static void set_cris_mode (char *ignore_args, int from_tty, |
714 | struct cmd_list_element *c); | |
715 | ||
a5f6c8f5 OF |
716 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
717 | struct cmd_list_element *c); | |
29134980 | 718 | |
2e4b5889 OF |
719 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
720 | struct frame_info *next_frame, | |
721 | struct cris_unwind_cache *info); | |
722 | ||
5114e29d OF |
723 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
724 | struct frame_info *next_frame, | |
725 | struct cris_unwind_cache *info); | |
726 | ||
2e4b5889 OF |
727 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
728 | struct frame_info *next_frame); | |
729 | ||
730 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
731 | struct frame_info *next_frame); | |
732 | ||
733 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
734 | order. The below implements a FILO (stack) to do this. |
735 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
736 | |
737 | struct stack_item | |
738 | { | |
739 | int len; | |
740 | struct stack_item *prev; | |
741 | void *data; | |
742 | }; | |
743 | ||
744 | static struct stack_item * | |
745 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
746 | { | |
747 | struct stack_item *si; | |
748 | si = xmalloc (sizeof (struct stack_item)); | |
749 | si->data = xmalloc (len); | |
750 | si->len = len; | |
751 | si->prev = prev; | |
752 | memcpy (si->data, contents, len); | |
753 | return si; | |
754 | } | |
755 | ||
756 | static struct stack_item * | |
757 | pop_stack_item (struct stack_item *si) | |
758 | { | |
759 | struct stack_item *dead = si; | |
760 | si = si->prev; | |
761 | xfree (dead->data); | |
762 | xfree (dead); | |
763 | return si; | |
764 | } | |
765 | ||
766 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
767 | the saved registers of frame described by FRAME_INFO. This | |
768 | includes special registers such as pc and fp saved in special ways | |
769 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 770 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
771 | |
772 | struct cris_unwind_cache * | |
773 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
774 | void **this_prologue_cache) | |
775 | { | |
776 | CORE_ADDR pc; | |
777 | struct cris_unwind_cache *info; | |
778 | int i; | |
779 | ||
780 | if ((*this_prologue_cache)) | |
781 | return (*this_prologue_cache); | |
782 | ||
783 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
784 | (*this_prologue_cache) = info; | |
785 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
786 | ||
787 | /* Zero all fields. */ | |
788 | info->prev_sp = 0; | |
789 | info->base = 0; | |
790 | info->size = 0; | |
791 | info->sp_offset = 0; | |
792 | info->r8_offset = 0; | |
793 | info->uses_frame = 0; | |
794 | info->return_pc = 0; | |
795 | info->leaf_function = 0; | |
796 | ||
797 | /* Prologue analysis does the rest... */ | |
5114e29d | 798 | if (cris_version () == 32) |
93d42b30 DJ |
799 | crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
800 | next_frame, info); | |
5114e29d | 801 | else |
93d42b30 DJ |
802 | cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
803 | next_frame, info); | |
2e4b5889 OF |
804 | |
805 | return info; | |
806 | } | |
807 | ||
808 | /* Given a GDB frame, determine the address of the calling function's | |
809 | frame. This will be used to create a new GDB frame struct. */ | |
810 | ||
811 | static void | |
812 | cris_frame_this_id (struct frame_info *next_frame, | |
813 | void **this_prologue_cache, | |
814 | struct frame_id *this_id) | |
815 | { | |
816 | struct cris_unwind_cache *info | |
817 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
818 | CORE_ADDR base; | |
819 | CORE_ADDR func; | |
820 | struct frame_id id; | |
821 | ||
822 | /* The FUNC is easy. */ | |
93d42b30 | 823 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
2e4b5889 OF |
824 | |
825 | /* Hopefully the prologue analysis either correctly determined the | |
826 | frame's base (which is the SP from the previous frame), or set | |
827 | that base to "NULL". */ | |
828 | base = info->prev_sp; | |
829 | if (base == 0) | |
830 | return; | |
831 | ||
832 | id = frame_id_build (base, func); | |
833 | ||
834 | (*this_id) = id; | |
835 | } | |
836 | ||
837 | static void | |
838 | cris_frame_prev_register (struct frame_info *next_frame, | |
839 | void **this_prologue_cache, | |
840 | int regnum, int *optimizedp, | |
841 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 842 | int *realnump, gdb_byte *bufferp) |
2e4b5889 OF |
843 | { |
844 | struct cris_unwind_cache *info | |
845 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
846 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
847 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
848 | } |
849 | ||
850 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
851 | dummy frame. The frame ID's base needs to match the TOS value | |
852 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
853 | breakpoint. */ | |
854 | ||
855 | static struct frame_id | |
856 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
857 | { | |
858 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
859 | frame_pc_unwind (next_frame)); | |
860 | } | |
861 | ||
862 | static CORE_ADDR | |
863 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
864 | { | |
865 | /* Align to the size of an instruction (so that they can safely be | |
866 | pushed onto the stack). */ | |
867 | return sp & ~3; | |
868 | } | |
869 | ||
870 | static CORE_ADDR | |
871 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
872 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
873 | struct value **args, int nargs, | |
874 | struct type *value_type, | |
e4fd649a UW |
875 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
876 | struct regcache *regcache) | |
2e4b5889 OF |
877 | { |
878 | /* Allocate space sufficient for a breakpoint. */ | |
879 | sp = (sp - 4) & ~3; | |
880 | /* Store the address of that breakpoint */ | |
881 | *bp_addr = sp; | |
882 | /* CRIS always starts the call at the callee's entry point. */ | |
883 | *real_pc = funaddr; | |
884 | return sp; | |
885 | } | |
886 | ||
887 | static CORE_ADDR | |
7d9b040b | 888 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
889 | struct regcache *regcache, CORE_ADDR bp_addr, |
890 | int nargs, struct value **args, CORE_ADDR sp, | |
891 | int struct_return, CORE_ADDR struct_addr) | |
892 | { | |
893 | int stack_alloc; | |
894 | int stack_offset; | |
895 | int argreg; | |
896 | int argnum; | |
897 | ||
898 | CORE_ADDR regval; | |
899 | ||
900 | /* The function's arguments and memory allocated by gdb for the arguments to | |
901 | point at reside in separate areas on the stack. | |
902 | Both frame pointers grow toward higher addresses. */ | |
903 | CORE_ADDR fp_arg; | |
904 | CORE_ADDR fp_mem; | |
905 | ||
906 | struct stack_item *si = NULL; | |
907 | ||
a5f6c8f5 | 908 | /* Push the return address. */ |
2e4b5889 OF |
909 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
910 | ||
911 | /* Are we returning a value using a structure return or a normal value | |
912 | return? struct_addr is the address of the reserved space for the return | |
913 | structure to be written on the stack. */ | |
914 | if (struct_return) | |
915 | { | |
916 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
917 | } | |
918 | ||
919 | /* Now load as many as possible of the first arguments into registers, | |
920 | and push the rest onto the stack. */ | |
921 | argreg = ARG1_REGNUM; | |
922 | stack_offset = 0; | |
923 | ||
924 | for (argnum = 0; argnum < nargs; argnum++) | |
925 | { | |
926 | int len; | |
927 | char *val; | |
928 | int reg_demand; | |
929 | int i; | |
930 | ||
4991999e | 931 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 932 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
933 | |
934 | /* How may registers worth of storage do we need for this argument? */ | |
935 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
936 | ||
937 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
938 | { | |
939 | /* Data passed by value. Fits in available register(s). */ | |
940 | for (i = 0; i < reg_demand; i++) | |
941 | { | |
942 | regcache_cooked_write_unsigned (regcache, argreg, | |
943 | *(unsigned long *) val); | |
944 | argreg++; | |
945 | val += 4; | |
946 | } | |
947 | } | |
948 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
949 | { | |
950 | /* Data passed by value. Does not fit in available register(s). | |
951 | Use the register(s) first, then the stack. */ | |
952 | for (i = 0; i < reg_demand; i++) | |
953 | { | |
954 | if (argreg <= ARG4_REGNUM) | |
955 | { | |
956 | regcache_cooked_write_unsigned (regcache, argreg, | |
957 | *(unsigned long *) val); | |
958 | argreg++; | |
959 | val += 4; | |
960 | } | |
961 | else | |
962 | { | |
963 | /* Push item for later so that pushed arguments | |
964 | come in the right order. */ | |
965 | si = push_stack_item (si, val, 4); | |
966 | val += 4; | |
967 | } | |
968 | } | |
969 | } | |
970 | else if (len > (2 * 4)) | |
971 | { | |
972 | /* FIXME */ | |
e2e0b3e5 | 973 | internal_error (__FILE__, __LINE__, _("We don't do this")); |
2e4b5889 OF |
974 | } |
975 | else | |
976 | { | |
977 | /* Data passed by value. No available registers. Put it on | |
978 | the stack. */ | |
979 | si = push_stack_item (si, val, len); | |
980 | } | |
981 | } | |
982 | ||
983 | while (si) | |
984 | { | |
985 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
986 | the function prologue. */ | |
987 | sp = (sp - si->len) & ~3; | |
988 | write_memory (sp, si->data, si->len); | |
989 | si = pop_stack_item (si); | |
990 | } | |
991 | ||
992 | /* Finally, update the SP register. */ | |
3e8c568d UW |
993 | regcache_cooked_write_unsigned (regcache, |
994 | gdbarch_sp_regnum (current_gdbarch), sp); | |
2e4b5889 OF |
995 | |
996 | return sp; | |
997 | } | |
998 | ||
e2a2a3e8 OF |
999 | static const struct frame_unwind cris_frame_unwind = |
1000 | { | |
2e4b5889 OF |
1001 | NORMAL_FRAME, |
1002 | cris_frame_this_id, | |
1003 | cris_frame_prev_register | |
1004 | }; | |
1005 | ||
1006 | const struct frame_unwind * | |
1007 | cris_frame_sniffer (struct frame_info *next_frame) | |
1008 | { | |
1009 | return &cris_frame_unwind; | |
1010 | } | |
1011 | ||
1012 | static CORE_ADDR | |
1013 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1014 | { | |
1015 | struct cris_unwind_cache *info | |
1016 | = cris_frame_unwind_cache (next_frame, this_cache); | |
1017 | return info->base; | |
1018 | } | |
1019 | ||
e2a2a3e8 OF |
1020 | static const struct frame_base cris_frame_base = |
1021 | { | |
2e4b5889 OF |
1022 | &cris_frame_unwind, |
1023 | cris_frame_base_address, | |
1024 | cris_frame_base_address, | |
1025 | cris_frame_base_address | |
1026 | }; | |
1027 | ||
29134980 OF |
1028 | /* Frames information. The definition of the struct frame_info is |
1029 | ||
1030 | CORE_ADDR frame | |
1031 | CORE_ADDR pc | |
5a203e44 | 1032 | enum frame_type type; |
29134980 OF |
1033 | CORE_ADDR return_pc |
1034 | int leaf_function | |
1035 | ||
1036 | If the compilation option -fno-omit-frame-pointer is present the | |
1037 | variable frame will be set to the content of R8 which is the frame | |
1038 | pointer register. | |
1039 | ||
1040 | The variable pc contains the address where execution is performed | |
1041 | in the present frame. The innermost frame contains the current content | |
1042 | of the register PC. All other frames contain the content of the | |
1043 | register PC in the next frame. | |
1044 | ||
5a203e44 AC |
1045 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1046 | (associated with a signal handler), dummy (associated with a dummy | |
1047 | frame). | |
29134980 OF |
1048 | |
1049 | The variable return_pc contains the address where execution should be | |
1050 | resumed when the present frame has finished, the return address. | |
1051 | ||
1052 | The variable leaf_function is 1 if the return address is in the register | |
1053 | SRP, and 0 if it is on the stack. | |
1054 | ||
1055 | Prologue instructions C-code. | |
1056 | The prologue may consist of (-fno-omit-frame-pointer) | |
1057 | 1) 2) | |
1058 | push srp | |
1059 | push r8 push r8 | |
1060 | move.d sp,r8 move.d sp,r8 | |
1061 | subq X,sp subq X,sp | |
1062 | movem rY,[sp] movem rY,[sp] | |
1063 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1064 | ||
1065 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1066 | ||
1067 | Note that this assumption is extremely brittle, and will break at the | |
1068 | slightest change in GCC's prologue. | |
1069 | ||
1070 | If local variables are declared or register contents are saved on stack | |
1071 | the subq-instruction will be present with X as the number of bytes | |
1072 | needed for storage. The reshuffle with respect to r8 may be performed | |
1073 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1074 | The offset U should be representable by a signed 8-bit value in all cases. | |
1075 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1076 | by another word containing the instruction. | |
1077 | ||
1078 | Degenerate cases: | |
1079 | 3) | |
1080 | push r8 | |
1081 | move.d sp,r8 | |
1082 | move.d r8,sp | |
1083 | pop r8 | |
1084 | ||
1085 | Prologue instructions C++-code. | |
1086 | Case 1) and 2) in the C-code may be followed by | |
1087 | ||
1088 | move.d r10,rS ; this | |
1089 | move.d r11,rT ; P1 | |
1090 | move.d r12,rU ; P2 | |
1091 | move.d r13,rV ; P3 | |
1092 | move.S [r8+U],rZ ; P4 | |
1093 | ||
1094 | if any of the call parameters are stored. The host expects these | |
1095 | instructions to be executed in order to get the call parameters right. */ | |
1096 | ||
1097 | /* Examine the prologue of a function. The variable ip is the address of | |
1098 | the first instruction of the prologue. The variable limit is the address | |
1099 | of the first instruction after the prologue. The variable fi contains the | |
1100 | information in struct frame_info. The variable frameless_p controls whether | |
1101 | the entire prologue is examined (0) or just enough instructions to | |
1102 | determine that it is a prologue (1). */ | |
1103 | ||
a78f21af | 1104 | static CORE_ADDR |
2e4b5889 OF |
1105 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1106 | struct cris_unwind_cache *info) | |
29134980 OF |
1107 | { |
1108 | /* Present instruction. */ | |
1109 | unsigned short insn; | |
1110 | ||
1111 | /* Next instruction, lookahead. */ | |
1112 | unsigned short insn_next; | |
1113 | int regno; | |
1114 | ||
1115 | /* Is there a push fp? */ | |
1116 | int have_fp; | |
1117 | ||
1118 | /* Number of byte on stack used for local variables and movem. */ | |
1119 | int val; | |
1120 | ||
1121 | /* Highest register number in a movem. */ | |
1122 | int regsave; | |
1123 | ||
1124 | /* move.d r<source_register>,rS */ | |
1125 | short source_register; | |
1126 | ||
2e4b5889 OF |
1127 | /* Scan limit. */ |
1128 | int limit; | |
29134980 | 1129 | |
2e4b5889 OF |
1130 | /* This frame is with respect to a leaf until a push srp is found. */ |
1131 | if (info) | |
1132 | { | |
1133 | info->leaf_function = 1; | |
1134 | } | |
29134980 OF |
1135 | |
1136 | /* Assume nothing on stack. */ | |
1137 | val = 0; | |
1138 | regsave = -1; | |
1139 | ||
2e4b5889 OF |
1140 | /* If we were called without a next_frame, that means we were called |
1141 | from cris_skip_prologue which already tried to find the end of the | |
1142 | prologue through the symbol information. 64 instructions past current | |
1143 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1144 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1145 | |
29134980 | 1146 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1147 | while (pc > 0 && pc < limit) |
29134980 | 1148 | { |
2e4b5889 OF |
1149 | insn = read_memory_unsigned_integer (pc, 2); |
1150 | pc += 2; | |
29134980 OF |
1151 | if (insn == 0xE1FC) |
1152 | { | |
1153 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1154 | insn_next = read_memory_unsigned_integer (pc, 2); |
1155 | pc += 2; | |
29134980 | 1156 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1157 | if (info) |
1158 | { | |
1159 | info->sp_offset += 4; | |
1160 | } | |
dbbff683 OF |
1161 | /* This check, meant to recognize srp, used to be regno == |
1162 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1163 | if (insn_next == 0xBE7E) | |
29134980 | 1164 | { |
2e4b5889 OF |
1165 | if (info) |
1166 | { | |
1167 | info->leaf_function = 0; | |
1168 | } | |
29134980 | 1169 | } |
b4206d25 OF |
1170 | else if (insn_next == 0x8FEE) |
1171 | { | |
1172 | /* push $r8 */ | |
1173 | if (info) | |
1174 | { | |
1175 | info->r8_offset = info->sp_offset; | |
1176 | } | |
1177 | } | |
29134980 OF |
1178 | } |
1179 | else if (insn == 0x866E) | |
1180 | { | |
1181 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1182 | if (info) |
1183 | { | |
1184 | info->uses_frame = 1; | |
2e4b5889 | 1185 | } |
29134980 OF |
1186 | continue; |
1187 | } | |
3e8c568d | 1188 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (current_gdbarch) |
29134980 OF |
1189 | && cris_get_mode (insn) == 0x0000 |
1190 | && cris_get_opcode (insn) == 0x000A) | |
1191 | { | |
1192 | /* subq <val>,sp */ | |
2e4b5889 OF |
1193 | if (info) |
1194 | { | |
1195 | info->sp_offset += cris_get_quick_value (insn); | |
1196 | } | |
29134980 OF |
1197 | } |
1198 | else if (cris_get_mode (insn) == 0x0002 | |
1199 | && cris_get_opcode (insn) == 0x000F | |
1200 | && cris_get_size (insn) == 0x0003 | |
3e8c568d UW |
1201 | && cris_get_operand1 (insn) == gdbarch_sp_regnum |
1202 | (current_gdbarch)) | |
29134980 OF |
1203 | { |
1204 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1205 | regsave = cris_get_operand2 (insn); |
1206 | } | |
3e8c568d | 1207 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (current_gdbarch) |
29134980 OF |
1208 | && ((insn & 0x0F00) >> 8) == 0x0001 |
1209 | && (cris_get_signed_offset (insn) < 0)) | |
1210 | { | |
1211 | /* Immediate byte offset addressing prefix word with sp as base | |
1212 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1213 | is between 64 and 128. | |
1214 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1215 | if (info) |
1216 | { | |
1217 | info->sp_offset += -cris_get_signed_offset (insn); | |
1218 | } | |
1219 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1220 | pc += 2; | |
29134980 OF |
1221 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1222 | && cris_get_opcode (insn_next) == 0x000F | |
1223 | && cris_get_size (insn_next) == 0x0003 | |
3e8c568d UW |
1224 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
1225 | (current_gdbarch)) | |
29134980 | 1226 | { |
29134980 OF |
1227 | regsave = cris_get_operand2 (insn_next); |
1228 | } | |
1229 | else | |
1230 | { | |
1231 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1232 | pc -= 4; |
29134980 OF |
1233 | break; |
1234 | } | |
1235 | } | |
1236 | else if (cris_get_mode (insn) == 0x0001 | |
1237 | && cris_get_opcode (insn) == 0x0009 | |
1238 | && cris_get_size (insn) == 0x0002) | |
1239 | { | |
1240 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1241 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1242 | |
1243 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1244 | like (this example taken from relocate_doit): | |
1245 | move.d $pc,$r0 | |
1246 | sub.d 0xfffef426,$r0 | |
1247 | which isn't covered by the source_register check below. Question | |
1248 | is whether to add a check for this combo, or make better use of | |
1249 | the limit variable instead. */ | |
29134980 OF |
1250 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1251 | { | |
1252 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1253 | pc -= 2; |
29134980 OF |
1254 | break; |
1255 | } | |
1256 | } | |
2e4b5889 | 1257 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1258 | /* The size is a fixed-size. */ |
1259 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1260 | /* A negative offset. */ | |
1261 | && (cris_get_signed_offset (insn) < 0)) | |
1262 | { | |
1263 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1264 | insn_next = read_memory_unsigned_integer (pc, 2); |
1265 | pc += 2; | |
29134980 | 1266 | regno = cris_get_operand2 (insn_next); |
3e8c568d | 1267 | if ((regno >= 0 && regno < gdbarch_sp_regnum (current_gdbarch)) |
29134980 OF |
1268 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1269 | && cris_get_opcode (insn_next) == 0x000F) | |
1270 | { | |
1271 | /* move.S rZ,[r8-U] */ | |
1272 | continue; | |
1273 | } | |
1274 | else | |
1275 | { | |
1276 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1277 | pc -= 4; |
29134980 OF |
1278 | break; |
1279 | } | |
1280 | } | |
2e4b5889 | 1281 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1282 | /* The size is a fixed-size. */ |
1283 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1284 | /* A positive offset. */ | |
1285 | && (cris_get_signed_offset (insn) > 0)) | |
1286 | { | |
1287 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1288 | insn_next = read_memory_unsigned_integer (pc, 2); |
1289 | pc += 2; | |
29134980 | 1290 | regno = cris_get_operand2 (insn_next); |
3e8c568d | 1291 | if ((regno >= 0 && regno < gdbarch_sp_regnum (current_gdbarch)) |
29134980 OF |
1292 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1293 | && cris_get_opcode (insn_next) == 0x0009 | |
1294 | && cris_get_operand1 (insn_next) == regno) | |
1295 | { | |
1296 | /* move.S [r8+U],rZ */ | |
1297 | continue; | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1302 | pc -= 4; |
29134980 OF |
1303 | break; |
1304 | } | |
1305 | } | |
1306 | else | |
1307 | { | |
1308 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1309 | pc -= 2; |
29134980 OF |
1310 | break; |
1311 | } | |
1312 | } | |
29134980 | 1313 | |
2e4b5889 OF |
1314 | /* We only want to know the end of the prologue when next_frame and info |
1315 | are NULL (called from cris_skip_prologue i.e.). */ | |
1316 | if (next_frame == NULL && info == NULL) | |
1317 | { | |
1318 | return pc; | |
1319 | } | |
29134980 | 1320 | |
2e4b5889 OF |
1321 | info->size = info->sp_offset; |
1322 | ||
1323 | /* Compute the previous frame's stack pointer (which is also the | |
1324 | frame's ID's stack address), and this frame's base pointer. */ | |
1325 | if (info->uses_frame) | |
29134980 | 1326 | { |
2e4b5889 OF |
1327 | ULONGEST this_base; |
1328 | /* The SP was moved to the FP. This indicates that a new frame | |
1329 | was created. Get THIS frame's FP value by unwinding it from | |
1330 | the next frame. */ | |
1331 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1332 | &this_base); | |
1333 | info->base = this_base; | |
b4206d25 OF |
1334 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1335 | ||
2e4b5889 OF |
1336 | /* The FP points at the last saved register. Adjust the FP back |
1337 | to before the first saved register giving the SP. */ | |
1338 | info->prev_sp = info->base + info->r8_offset; | |
1339 | } | |
1340 | else | |
1341 | { | |
1342 | ULONGEST this_base; | |
1343 | /* Assume that the FP is this frame's SP but with that pushed | |
1344 | stack space added back. */ | |
3e8c568d UW |
1345 | frame_unwind_unsigned_register (next_frame, |
1346 | gdbarch_sp_regnum (current_gdbarch), | |
1347 | &this_base); | |
2e4b5889 OF |
1348 | info->base = this_base; |
1349 | info->prev_sp = info->base + info->size; | |
1350 | } | |
29134980 | 1351 | |
2e4b5889 OF |
1352 | /* Calculate the addresses for the saved registers on the stack. */ |
1353 | /* FIXME: The address calculation should really be done on the fly while | |
1354 | we're analyzing the prologue (we only hold one regsave value as it is | |
1355 | now). */ | |
1356 | val = info->sp_offset; | |
1357 | ||
1358 | for (regno = regsave; regno >= 0; regno--) | |
1359 | { | |
1360 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1361 | val -= 4; | |
1362 | } | |
1363 | ||
1364 | /* The previous frame's SP needed to be computed. Save the computed | |
1365 | value. */ | |
3e8c568d UW |
1366 | trad_frame_set_value (info->saved_regs, |
1367 | gdbarch_sp_regnum (current_gdbarch), info->prev_sp); | |
2e4b5889 OF |
1368 | |
1369 | if (!info->leaf_function) | |
1370 | { | |
b4206d25 OF |
1371 | /* SRP saved on the stack. But where? */ |
1372 | if (info->r8_offset == 0) | |
1373 | { | |
1374 | /* R8 not pushed yet. */ | |
1375 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1376 | } | |
1377 | else | |
1378 | { | |
1379 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1380 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1381 | } | |
29134980 | 1382 | } |
2e4b5889 OF |
1383 | |
1384 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
3e8c568d UW |
1385 | info->saved_regs[gdbarch_pc_regnum (current_gdbarch)] |
1386 | = info->saved_regs[SRP_REGNUM]; | |
2e4b5889 OF |
1387 | |
1388 | return pc; | |
29134980 OF |
1389 | } |
1390 | ||
5114e29d OF |
1391 | static CORE_ADDR |
1392 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, | |
1393 | struct cris_unwind_cache *info) | |
1394 | { | |
1395 | ULONGEST this_base; | |
1396 | ||
1397 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1398 | meant to be a full-fledged prologue scanner. It is only needed for | |
1399 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1400 | ||
1401 | * PLT stubs (library calls) | |
1402 | * call dummys | |
1403 | * signal trampolines | |
1404 | ||
1405 | For those cases, it is assumed that there is no actual prologue; that | |
1406 | the stack pointer is not adjusted, and (as a consequence) the return | |
1407 | address is not pushed onto the stack. */ | |
1408 | ||
1409 | /* We only want to know the end of the prologue when next_frame and info | |
1410 | are NULL (called from cris_skip_prologue i.e.). */ | |
1411 | if (next_frame == NULL && info == NULL) | |
1412 | { | |
1413 | return pc; | |
1414 | } | |
1415 | ||
1416 | /* The SP is assumed to be unaltered. */ | |
3e8c568d UW |
1417 | frame_unwind_unsigned_register (next_frame, |
1418 | gdbarch_sp_regnum (current_gdbarch), | |
1419 | &this_base); | |
5114e29d OF |
1420 | info->base = this_base; |
1421 | info->prev_sp = this_base; | |
1422 | ||
1423 | /* The PC is assumed to be found in SRP. */ | |
3e8c568d UW |
1424 | info->saved_regs[gdbarch_pc_regnum (current_gdbarch)] |
1425 | = info->saved_regs[SRP_REGNUM]; | |
5114e29d OF |
1426 | |
1427 | return pc; | |
1428 | } | |
1429 | ||
29134980 OF |
1430 | /* Advance pc beyond any function entry prologue instructions at pc |
1431 | to reach some "real" code. */ | |
1432 | ||
29134980 OF |
1433 | /* Given a PC value corresponding to the start of a function, return the PC |
1434 | of the first instruction after the function prologue. */ | |
1435 | ||
a78f21af | 1436 | static CORE_ADDR |
2e4b5889 | 1437 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1438 | { |
2e4b5889 OF |
1439 | CORE_ADDR func_addr, func_end; |
1440 | struct symtab_and_line sal; | |
29134980 OF |
1441 | CORE_ADDR pc_after_prologue; |
1442 | ||
2e4b5889 OF |
1443 | /* If we have line debugging information, then the end of the prologue |
1444 | should the first assembly instruction of the first source line. */ | |
1445 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1446 | { | |
1447 | sal = find_pc_line (func_addr, 0); | |
1448 | if (sal.end > 0 && sal.end < func_end) | |
1449 | return sal.end; | |
1450 | } | |
29134980 | 1451 | |
5114e29d OF |
1452 | if (cris_version () == 32) |
1453 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); | |
1454 | else | |
1455 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1456 | ||
29134980 OF |
1457 | return pc_after_prologue; |
1458 | } | |
1459 | ||
2e4b5889 OF |
1460 | static CORE_ADDR |
1461 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1462 | { | |
1463 | ULONGEST pc; | |
3e8c568d UW |
1464 | frame_unwind_unsigned_register (next_frame, |
1465 | gdbarch_pc_regnum (current_gdbarch), &pc); | |
2e4b5889 OF |
1466 | return pc; |
1467 | } | |
1468 | ||
1469 | static CORE_ADDR | |
1470 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1471 | { | |
1472 | ULONGEST sp; | |
3e8c568d UW |
1473 | frame_unwind_unsigned_register (next_frame, |
1474 | gdbarch_sp_regnum (current_gdbarch), &sp); | |
2e4b5889 OF |
1475 | return sp; |
1476 | } | |
1477 | ||
29134980 OF |
1478 | /* Use the program counter to determine the contents and size of a breakpoint |
1479 | instruction. It returns a pointer to a string of bytes that encode a | |
1480 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1481 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1482 | the breakpoint should be inserted. */ | |
1483 | ||
a78f21af | 1484 | static const unsigned char * |
29134980 OF |
1485 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1486 | { | |
0e6bdb31 OF |
1487 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1488 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1489 | *lenptr = 2; |
1490 | ||
0e6bdb31 OF |
1491 | if (cris_mode () == cris_mode_guru) |
1492 | return break15_insn; | |
1493 | else | |
1494 | return break8_insn; | |
29134980 OF |
1495 | } |
1496 | ||
29134980 OF |
1497 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1498 | 0 otherwise. */ | |
1499 | ||
a78f21af | 1500 | static int |
29134980 OF |
1501 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1502 | { | |
1503 | int version = cris_version (); | |
1504 | ||
1505 | switch (spec_reg.applicable_version) | |
1506 | { | |
1507 | case cris_ver_version_all: | |
1508 | return 1; | |
1509 | case cris_ver_warning: | |
1510 | /* Indeterminate/obsolete. */ | |
1511 | return 0; | |
29134980 OF |
1512 | case cris_ver_v0_3: |
1513 | return (version >= 0 && version <= 3); | |
1514 | case cris_ver_v3p: | |
1515 | return (version >= 3); | |
1516 | case cris_ver_v8: | |
1517 | return (version == 8 || version == 9); | |
1518 | case cris_ver_v8p: | |
1519 | return (version >= 8); | |
c600d464 OF |
1520 | case cris_ver_v0_10: |
1521 | return (version >= 0 && version <= 10); | |
1522 | case cris_ver_v3_10: | |
1523 | return (version >= 3 && version <= 10); | |
1524 | case cris_ver_v8_10: | |
1525 | return (version >= 8 && version <= 10); | |
1526 | case cris_ver_v10: | |
1527 | return (version == 10); | |
29134980 OF |
1528 | case cris_ver_v10p: |
1529 | return (version >= 10); | |
c600d464 OF |
1530 | case cris_ver_v32p: |
1531 | return (version >= 32); | |
29134980 OF |
1532 | default: |
1533 | /* Invalid cris version. */ | |
1534 | return 0; | |
1535 | } | |
1536 | } | |
1537 | ||
1d94326f AC |
1538 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1539 | register, -1 for an invalid register. */ | |
1540 | ||
1541 | static int | |
1542 | cris_register_size (int regno) | |
1543 | { | |
c600d464 | 1544 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1545 | int i; |
1546 | int spec_regno; | |
1547 | ||
1548 | if (regno >= 0 && regno < NUM_GENREGS) | |
1549 | { | |
1550 | /* General registers (R0 - R15) are 32 bits. */ | |
1551 | return 4; | |
1552 | } | |
c600d464 | 1553 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1554 | { |
1555 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1556 | Adjust regno accordingly. */ | |
1557 | spec_regno = regno - NUM_GENREGS; | |
1558 | ||
c600d464 | 1559 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1560 | { |
1561 | if (cris_spec_regs[i].number == spec_regno | |
1562 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1563 | /* Go with the first applicable register. */ | |
1564 | return cris_spec_regs[i].reg_size; | |
1565 | } | |
1566 | /* Special register not applicable to this CRIS version. */ | |
1567 | return 0; | |
1568 | } | |
3e8c568d UW |
1569 | else if (regno >= gdbarch_pc_regnum (current_gdbarch) |
1570 | && regno < gdbarch_num_regs (current_gdbarch)) | |
1d94326f | 1571 | { |
c600d464 OF |
1572 | /* This will apply to CRISv32 only where there are additional registers |
1573 | after the special registers (pseudo PC and support registers). */ | |
1574 | return 4; | |
1d94326f | 1575 | } |
c600d464 OF |
1576 | |
1577 | ||
1578 | return -1; | |
1d94326f AC |
1579 | } |
1580 | ||
29134980 OF |
1581 | /* Nonzero if regno should not be fetched from the target. This is the case |
1582 | for unimplemented (size 0) and non-existant registers. */ | |
1583 | ||
a78f21af | 1584 | static int |
29134980 OF |
1585 | cris_cannot_fetch_register (int regno) |
1586 | { | |
f57d151a | 1587 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
29134980 OF |
1588 | || (cris_register_size (regno) == 0)); |
1589 | } | |
1590 | ||
1591 | /* Nonzero if regno should not be written to the target, for various | |
1592 | reasons. */ | |
1593 | ||
a78f21af | 1594 | static int |
29134980 OF |
1595 | cris_cannot_store_register (int regno) |
1596 | { | |
1597 | /* There are three kinds of registers we refuse to write to. | |
1598 | 1. Those that not implemented. | |
1599 | 2. Those that are read-only (depends on the processor mode). | |
1600 | 3. Those registers to which a write has no effect. | |
1601 | */ | |
1602 | ||
f57d151a UW |
1603 | if (regno < 0 |
1604 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1605 | || cris_register_size (regno) == 0) | |
29134980 OF |
1606 | /* Not implemented. */ |
1607 | return 1; | |
1608 | ||
1609 | else if (regno == VR_REGNUM) | |
1610 | /* Read-only. */ | |
1611 | return 1; | |
1612 | ||
1613 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1614 | /* Writing has no effect. */ | |
1615 | return 1; | |
1616 | ||
a5f6c8f5 OF |
1617 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1618 | agent decide whether they are writable. */ | |
29134980 OF |
1619 | |
1620 | return 0; | |
1621 | } | |
1622 | ||
c600d464 OF |
1623 | /* Nonzero if regno should not be fetched from the target. This is the case |
1624 | for unimplemented (size 0) and non-existant registers. */ | |
1625 | ||
1626 | static int | |
1627 | crisv32_cannot_fetch_register (int regno) | |
1628 | { | |
f57d151a | 1629 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
c600d464 OF |
1630 | || (cris_register_size (regno) == 0)); |
1631 | } | |
1632 | ||
1633 | /* Nonzero if regno should not be written to the target, for various | |
1634 | reasons. */ | |
1635 | ||
1636 | static int | |
1637 | crisv32_cannot_store_register (int regno) | |
1638 | { | |
1639 | /* There are three kinds of registers we refuse to write to. | |
1640 | 1. Those that not implemented. | |
1641 | 2. Those that are read-only (depends on the processor mode). | |
1642 | 3. Those registers to which a write has no effect. | |
1643 | */ | |
1644 | ||
f57d151a UW |
1645 | if (regno < 0 |
1646 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1647 | || cris_register_size (regno) == 0) | |
c600d464 OF |
1648 | /* Not implemented. */ |
1649 | return 1; | |
1650 | ||
1651 | else if (regno == VR_REGNUM) | |
1652 | /* Read-only. */ | |
1653 | return 1; | |
1654 | ||
1655 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1656 | /* Writing has no effect. */ | |
1657 | return 1; | |
1658 | ||
1659 | /* Many special registers are read-only in user mode. Let the debug | |
1660 | agent decide whether they are writable. */ | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
29134980 OF |
1665 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1666 | of data in register regno. */ | |
1667 | ||
a78f21af | 1668 | static struct type * |
c1d546cd | 1669 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1670 | { |
3e8c568d | 1671 | if (regno == gdbarch_pc_regnum (current_gdbarch)) |
a5f6c8f5 | 1672 | return builtin_type_void_func_ptr; |
3e8c568d UW |
1673 | else if (regno == gdbarch_sp_regnum (current_gdbarch) |
1674 | || regno == CRIS_FP_REGNUM) | |
a5f6c8f5 | 1675 | return builtin_type_void_data_ptr; |
3e8c568d | 1676 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (current_gdbarch)) |
a5f6c8f5 OF |
1677 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
1678 | /* Note: R8 taken care of previous clause. */ | |
1679 | return builtin_type_uint32; | |
1680 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1681 | return builtin_type_uint16; | |
1682 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1683 | return builtin_type_uint8; | |
29134980 | 1684 | else |
a5f6c8f5 OF |
1685 | /* Invalid (unimplemented) register. */ |
1686 | return builtin_type_int0; | |
29134980 OF |
1687 | } |
1688 | ||
c600d464 OF |
1689 | static struct type * |
1690 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1691 | { | |
3e8c568d | 1692 | if (regno == gdbarch_pc_regnum (current_gdbarch)) |
c600d464 | 1693 | return builtin_type_void_func_ptr; |
3e8c568d UW |
1694 | else if (regno == gdbarch_sp_regnum (current_gdbarch) |
1695 | || regno == CRIS_FP_REGNUM) | |
c600d464 OF |
1696 | return builtin_type_void_data_ptr; |
1697 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1698 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1699 | || (regno == PID_REGNUM) | |
1700 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1701 | /* Note: R8 and SP taken care of by previous clause. */ | |
1702 | return builtin_type_uint32; | |
1703 | else if (regno == WZ_REGNUM) | |
1704 | return builtin_type_uint16; | |
1705 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1706 | return builtin_type_uint8; | |
1707 | else | |
1708 | { | |
1709 | /* Invalid (unimplemented) register. Should not happen as there are | |
1710 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1711 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
c600d464 OF |
1712 | return builtin_type_int0; |
1713 | } | |
1714 | } | |
1715 | ||
2e4b5889 OF |
1716 | /* Stores a function return value of type type, where valbuf is the address |
1717 | of the value to be stored. */ | |
29134980 | 1718 | |
2e4b5889 | 1719 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1720 | |
2e4b5889 OF |
1721 | static void |
1722 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1723 | const void *valbuf) | |
29134980 | 1724 | { |
2e4b5889 OF |
1725 | ULONGEST val; |
1726 | int len = TYPE_LENGTH (type); | |
29134980 | 1727 | |
2e4b5889 | 1728 | if (len <= 4) |
29134980 | 1729 | { |
2e4b5889 OF |
1730 | /* Put the return value in R10. */ |
1731 | val = extract_unsigned_integer (valbuf, len); | |
1732 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1733 | } |
2e4b5889 | 1734 | else if (len <= 8) |
29134980 | 1735 | { |
2e4b5889 OF |
1736 | /* Put the return value in R10 and R11. */ |
1737 | val = extract_unsigned_integer (valbuf, 4); | |
1738 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1739 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1740 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1741 | } |
2e4b5889 | 1742 | else |
8a3fe4f8 | 1743 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1744 | } |
1745 | ||
2e4b5889 OF |
1746 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1747 | unimplemented register. */ | |
29134980 | 1748 | |
c600d464 OF |
1749 | static const char * |
1750 | cris_special_register_name (int regno) | |
1751 | { | |
1752 | int spec_regno; | |
1753 | int i; | |
1754 | ||
1755 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1756 | Adjust regno accordingly. */ | |
1757 | spec_regno = regno - NUM_GENREGS; | |
1758 | ||
1759 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1760 | when searching. */ | |
1761 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1762 | { | |
1763 | if (cris_spec_regs[i].number == spec_regno | |
1764 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1765 | /* Go with the first applicable register. */ | |
1766 | return cris_spec_regs[i].name; | |
1767 | } | |
1768 | /* Special register not applicable to this CRIS version. */ | |
1769 | return NULL; | |
1770 | } | |
1771 | ||
2e4b5889 OF |
1772 | static const char * |
1773 | cris_register_name (int regno) | |
1774 | { | |
1775 | static char *cris_genreg_names[] = | |
1776 | { "r0", "r1", "r2", "r3", \ | |
1777 | "r4", "r5", "r6", "r7", \ | |
1778 | "r8", "r9", "r10", "r11", \ | |
1779 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1780 | |
2e4b5889 | 1781 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1782 | { |
2e4b5889 OF |
1783 | /* General register. */ |
1784 | return cris_genreg_names[regno]; | |
29134980 | 1785 | } |
f57d151a | 1786 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (current_gdbarch)) |
29134980 | 1787 | { |
c600d464 OF |
1788 | return cris_special_register_name (regno); |
1789 | } | |
1790 | else | |
1791 | { | |
1792 | /* Invalid register. */ | |
2e4b5889 OF |
1793 | return NULL; |
1794 | } | |
c600d464 OF |
1795 | } |
1796 | ||
1797 | static const char * | |
1798 | crisv32_register_name (int regno) | |
1799 | { | |
1800 | static char *crisv32_genreg_names[] = | |
1801 | { "r0", "r1", "r2", "r3", \ | |
1802 | "r4", "r5", "r6", "r7", \ | |
1803 | "r8", "r9", "r10", "r11", \ | |
1804 | "r12", "r13", "sp", "acr" | |
1805 | }; | |
1806 | ||
1807 | static char *crisv32_sreg_names[] = | |
1808 | { "s0", "s1", "s2", "s3", \ | |
1809 | "s4", "s5", "s6", "s7", \ | |
1810 | "s8", "s9", "s10", "s11", \ | |
1811 | "s12", "s13", "s14", "s15" | |
1812 | }; | |
1813 | ||
1814 | if (regno >= 0 && regno < NUM_GENREGS) | |
1815 | { | |
1816 | /* General register. */ | |
1817 | return crisv32_genreg_names[regno]; | |
1818 | } | |
1819 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1820 | { | |
1821 | return cris_special_register_name (regno); | |
1822 | } | |
3e8c568d | 1823 | else if (regno == gdbarch_pc_regnum (current_gdbarch)) |
c600d464 OF |
1824 | { |
1825 | return "pc"; | |
1826 | } | |
1827 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1828 | { | |
1829 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1830 | } | |
2e4b5889 OF |
1831 | else |
1832 | { | |
1833 | /* Invalid register. */ | |
1834 | return NULL; | |
29134980 | 1835 | } |
29134980 OF |
1836 | } |
1837 | ||
a5f6c8f5 OF |
1838 | /* Convert DWARF register number REG to the appropriate register |
1839 | number used by GDB. */ | |
1840 | ||
2e4b5889 | 1841 | static int |
a5f6c8f5 | 1842 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1843 | { |
a5f6c8f5 OF |
1844 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1845 | numbering, MOF is 18). | |
1846 | Adapted from gcc/config/cris/cris.h. */ | |
1847 | static int cris_dwarf_regmap[] = { | |
1848 | 0, 1, 2, 3, | |
1849 | 4, 5, 6, 7, | |
1850 | 8, 9, 10, 11, | |
1851 | 12, 13, 14, 15, | |
1852 | 27, -1, -1, -1, | |
1853 | -1, -1, -1, 23, | |
1854 | -1, -1, -1, 27, | |
1855 | -1, -1, -1, -1 | |
1856 | }; | |
1857 | int regnum = -1; | |
1858 | ||
1859 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1860 | regnum = cris_dwarf_regmap[reg]; | |
1861 | ||
1862 | if (regnum == -1) | |
8a3fe4f8 | 1863 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1864 | |
1865 | return regnum; | |
1866 | } | |
1867 | ||
1868 | /* DWARF-2 frame support. */ | |
1869 | ||
1870 | static void | |
1871 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1872 | struct dwarf2_frame_state_reg *reg, |
1873 | struct frame_info *next_frame) | |
a5f6c8f5 OF |
1874 | { |
1875 | /* The return address column. */ | |
3e8c568d | 1876 | if (regnum == gdbarch_pc_regnum (current_gdbarch)) |
a5f6c8f5 OF |
1877 | reg->how = DWARF2_FRAME_REG_RA; |
1878 | ||
1879 | /* The call frame address. */ | |
3e8c568d | 1880 | else if (regnum == gdbarch_sp_regnum (current_gdbarch)) |
a5f6c8f5 | 1881 | reg->how = DWARF2_FRAME_REG_CFA; |
29134980 OF |
1882 | } |
1883 | ||
2e4b5889 OF |
1884 | /* Extract from an array regbuf containing the raw register state a function |
1885 | return value of type type, and copy that, in virtual format, into | |
1886 | valbuf. */ | |
1887 | ||
1888 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1889 | |
2e4b5889 OF |
1890 | static void |
1891 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1892 | void *valbuf) | |
29134980 | 1893 | { |
2e4b5889 OF |
1894 | ULONGEST val; |
1895 | int len = TYPE_LENGTH (type); | |
29134980 | 1896 | |
2e4b5889 | 1897 | if (len <= 4) |
29134980 | 1898 | { |
2e4b5889 OF |
1899 | /* Get the return value from R10. */ |
1900 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1901 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1902 | } |
2e4b5889 | 1903 | else if (len <= 8) |
29134980 | 1904 | { |
2e4b5889 OF |
1905 | /* Get the return value from R10 and R11. */ |
1906 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1907 | store_unsigned_integer (valbuf, 4, val); | |
1908 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1909 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1910 | } |
2e4b5889 | 1911 | else |
8a3fe4f8 | 1912 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1913 | } |
1914 | ||
b4206d25 OF |
1915 | /* Handle the CRIS return value convention. */ |
1916 | ||
1917 | static enum return_value_convention | |
1918 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
e2a2a3e8 OF |
1919 | struct regcache *regcache, gdb_byte *readbuf, |
1920 | const gdb_byte *writebuf) | |
b4206d25 OF |
1921 | { |
1922 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1923 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1924 | || TYPE_LENGTH (type) > 8) | |
1925 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1926 | goes on the stack. */ | |
1927 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1928 | ||
1929 | if (readbuf) | |
1930 | cris_extract_return_value (type, regcache, readbuf); | |
1931 | if (writebuf) | |
1932 | cris_store_return_value (type, regcache, writebuf); | |
1933 | ||
1934 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1935 | } | |
1936 | ||
2e4b5889 OF |
1937 | /* Returns 1 if the given type will be passed by pointer rather than |
1938 | directly. */ | |
1939 | ||
1940 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1941 | by value. */ | |
1942 | ||
1943 | static int | |
1944 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1945 | { | |
1946 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1947 | } |
1948 | ||
1949 | /* Calculates a value that measures how good inst_args constraints an | |
1950 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1951 | ||
1952 | static int | |
1953 | constraint (unsigned int insn, const signed char *inst_args, | |
1954 | inst_env_type *inst_env) | |
1955 | { | |
1956 | int retval = 0; | |
1957 | int tmp, i; | |
1958 | ||
1959 | const char *s = inst_args; | |
1960 | ||
1961 | for (; *s; s++) | |
1962 | switch (*s) | |
1963 | { | |
1964 | case 'm': | |
1965 | if ((insn & 0x30) == 0x30) | |
1966 | return -1; | |
1967 | break; | |
1968 | ||
1969 | case 'S': | |
1970 | /* A prefix operand. */ | |
1971 | if (inst_env->prefix_found) | |
1972 | break; | |
1973 | else | |
1974 | return -1; | |
1975 | ||
1976 | case 'B': | |
1977 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1978 | valid "push" size. In case of special register, it may be != 4. */ | |
1979 | if (inst_env->prefix_found) | |
1980 | break; | |
1981 | else | |
1982 | return -1; | |
1983 | ||
1984 | case 'D': | |
1985 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1986 | if (!retval) | |
1987 | return -1; | |
1988 | else | |
1989 | retval += 4; | |
1990 | break; | |
1991 | ||
1992 | case 'P': | |
1993 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1994 | |
1995 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1996 | { | |
1997 | /* Since we match four bits, we will give a value of | |
1998 | 4 - 1 = 3 in a match. If there is a corresponding | |
1999 | exact match of a special register in another pattern, it | |
2000 | will get a value of 4, which will be higher. This should | |
2001 | be correct in that an exact pattern would match better that | |
2002 | a general pattern. | |
2003 | Note that there is a reason for not returning zero; the | |
2004 | pattern for "clear" is partly matched in the bit-pattern | |
2005 | (the two lower bits must be zero), while the bit-pattern | |
2006 | for a move from a special register is matched in the | |
2007 | register constraint. | |
2008 | This also means we will will have a race condition if | |
2009 | there is a partly match in three bits in the bit pattern. */ | |
2010 | if (tmp == cris_spec_regs[i].number) | |
2011 | { | |
2012 | retval += 3; | |
2013 | break; | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
2018 | return -1; |
2019 | break; | |
2020 | } | |
2021 | return retval; | |
2022 | } | |
2023 | ||
2024 | /* Returns the number of bits set in the variable value. */ | |
2025 | ||
2026 | static int | |
2027 | number_of_bits (unsigned int value) | |
2028 | { | |
2029 | int number_of_bits = 0; | |
2030 | ||
2031 | while (value != 0) | |
2032 | { | |
2033 | number_of_bits += 1; | |
2034 | value &= (value - 1); | |
2035 | } | |
2036 | return number_of_bits; | |
2037 | } | |
2038 | ||
2039 | /* Finds the address that should contain the single step breakpoint(s). | |
2040 | It stems from code in cris-dis.c. */ | |
2041 | ||
2042 | static int | |
2043 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
2044 | { | |
2045 | int i; | |
2046 | int max_level_of_match = -1; | |
2047 | int max_matched = -1; | |
2048 | int level_of_match; | |
2049 | ||
2050 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
2051 | { | |
2052 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
2053 | && ((cris_opcodes[i].lose & insn) == 0) |
2054 | /* Only CRISv10 instructions, please. */ | |
2055 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
2056 | { |
2057 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
2058 | if (level_of_match >= 0) | |
2059 | { | |
2060 | level_of_match += | |
2061 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
2062 | if (level_of_match > max_level_of_match) | |
2063 | { | |
2064 | max_matched = i; | |
2065 | max_level_of_match = level_of_match; | |
2066 | if (level_of_match == 16) | |
2067 | { | |
2068 | /* All bits matched, cannot find better. */ | |
2069 | break; | |
2070 | } | |
2071 | } | |
2072 | } | |
2073 | } | |
2074 | } | |
2075 | return max_matched; | |
2076 | } | |
2077 | ||
2078 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2079 | actually an internal error. */ | |
2080 | ||
2081 | static int | |
0b1b3e42 | 2082 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
29134980 OF |
2083 | { |
2084 | int i; | |
2085 | int offset; | |
2086 | unsigned short insn; | |
2087 | ||
2088 | /* Create a local register image and set the initial state. */ | |
2089 | for (i = 0; i < NUM_GENREGS; i++) | |
2090 | { | |
0b1b3e42 UW |
2091 | inst_env->reg[i] = |
2092 | (unsigned long) get_frame_register_unsigned (frame, i); | |
29134980 OF |
2093 | } |
2094 | offset = NUM_GENREGS; | |
2095 | for (i = 0; i < NUM_SPECREGS; i++) | |
2096 | { | |
0b1b3e42 UW |
2097 | inst_env->preg[i] = |
2098 | (unsigned long) get_frame_register_unsigned (frame, offset + i); | |
29134980 OF |
2099 | } |
2100 | inst_env->branch_found = 0; | |
2101 | inst_env->slot_needed = 0; | |
2102 | inst_env->delay_slot_pc_active = 0; | |
2103 | inst_env->prefix_found = 0; | |
2104 | inst_env->invalid = 0; | |
2105 | inst_env->xflag_found = 0; | |
2106 | inst_env->disable_interrupt = 0; | |
2107 | ||
2108 | /* Look for a step target. */ | |
2109 | do | |
2110 | { | |
2111 | /* Read an instruction from the client. */ | |
3e8c568d UW |
2112 | insn = read_memory_unsigned_integer |
2113 | (inst_env->reg[gdbarch_pc_regnum (current_gdbarch)], 2); | |
29134980 OF |
2114 | |
2115 | /* If the instruction is not in a delay slot the new content of the | |
2116 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2117 | that simple. Since a instruction in a delay slot cannot change | |
2118 | the content of the PC, it does not matter what value PC will have. | |
2119 | Just make sure it is a valid instruction. */ | |
2120 | if (!inst_env->delay_slot_pc_active) | |
2121 | { | |
3e8c568d | 2122 | inst_env->reg[gdbarch_pc_regnum (current_gdbarch)] += 2; |
29134980 OF |
2123 | } |
2124 | else | |
2125 | { | |
2126 | inst_env->delay_slot_pc_active = 0; | |
3e8c568d UW |
2127 | inst_env->reg[gdbarch_pc_regnum (current_gdbarch)] |
2128 | = inst_env->delay_slot_pc; | |
29134980 OF |
2129 | } |
2130 | /* Analyse the present instruction. */ | |
2131 | i = find_cris_op (insn, inst_env); | |
2132 | if (i == -1) | |
2133 | { | |
2134 | inst_env->invalid = 1; | |
2135 | } | |
2136 | else | |
2137 | { | |
2138 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2139 | } | |
2140 | } while (!inst_env->invalid | |
2141 | && (inst_env->prefix_found || inst_env->xflag_found | |
2142 | || inst_env->slot_needed)); | |
2143 | return i; | |
2144 | } | |
2145 | ||
2146 | /* There is no hardware single-step support. The function find_step_target | |
2147 | digs through the opcodes in order to find all possible targets. | |
2148 | Either one ordinary target or two targets for branches may be found. */ | |
2149 | ||
e6590a1b | 2150 | static int |
0b1b3e42 | 2151 | cris_software_single_step (struct frame_info *frame) |
29134980 OF |
2152 | { |
2153 | inst_env_type inst_env; | |
8181d85f | 2154 | |
e0cd558a UW |
2155 | /* Analyse the present instruction environment and insert |
2156 | breakpoints. */ | |
0b1b3e42 | 2157 | int status = find_step_target (frame, &inst_env); |
e0cd558a | 2158 | if (status == -1) |
29134980 | 2159 | { |
e0cd558a UW |
2160 | /* Could not find a target. Things are likely to go downhill |
2161 | from here. */ | |
2162 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2163 | } |
2164 | else | |
e0cd558a UW |
2165 | { |
2166 | /* Insert at most two breakpoints. One for the next PC content | |
2167 | and possibly another one for a branch, jump, etc. */ | |
3e8c568d UW |
2168 | CORE_ADDR next_pc = |
2169 | (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (current_gdbarch)]; | |
e0cd558a UW |
2170 | insert_single_step_breakpoint (next_pc); |
2171 | if (inst_env.branch_found | |
2172 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2173 | { | |
2174 | CORE_ADDR branch_target_address | |
2175 | = (CORE_ADDR) inst_env.branch_break_address; | |
2176 | insert_single_step_breakpoint (branch_target_address); | |
2177 | } | |
2178 | } | |
e6590a1b UW |
2179 | |
2180 | return 1; | |
29134980 OF |
2181 | } |
2182 | ||
2183 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2184 | ||
a78f21af | 2185 | static void |
29134980 OF |
2186 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2187 | { | |
2188 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2189 | instruction (not 100% sure). */ | |
2190 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2191 | { | |
2192 | inst_env->invalid = 1; | |
2193 | return; | |
2194 | } | |
2195 | ||
2196 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2197 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2198 | ||
2199 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2200 | need updating. */ | |
2201 | inst_env->slot_needed = 0; | |
2202 | inst_env->prefix_found = 1; | |
2203 | } | |
2204 | ||
2205 | /* Updates the autoincrement register. The size of the increment is derived | |
2206 | from the size of the operation. The PC is always kept aligned on even | |
2207 | word addresses. */ | |
2208 | ||
a78f21af | 2209 | static void |
29134980 OF |
2210 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2211 | { | |
2212 | if (size == INST_BYTE_SIZE) | |
2213 | { | |
2214 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2215 | ||
2216 | /* The PC must be word aligned, so increase the PC with one | |
2217 | word even if the size is byte. */ | |
2218 | if (cris_get_operand1 (inst) == REG_PC) | |
2219 | { | |
2220 | inst_env->reg[REG_PC] += 1; | |
2221 | } | |
2222 | } | |
2223 | else if (size == INST_WORD_SIZE) | |
2224 | { | |
2225 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2226 | } | |
2227 | else if (size == INST_DWORD_SIZE) | |
2228 | { | |
2229 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | /* Invalid size. */ | |
2234 | inst_env->invalid = 1; | |
2235 | } | |
2236 | } | |
2237 | ||
2a9ecef2 OF |
2238 | /* Just a forward declaration. */ |
2239 | ||
a78f21af AC |
2240 | static unsigned long get_data_from_address (unsigned short *inst, |
2241 | CORE_ADDR address); | |
2a9ecef2 | 2242 | |
29134980 OF |
2243 | /* Calculates the prefix value for the general case of offset addressing |
2244 | mode. */ | |
2245 | ||
a78f21af | 2246 | static void |
29134980 OF |
2247 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2248 | { | |
2249 | ||
2250 | long offset; | |
2251 | ||
2252 | /* It's invalid to be in a delay slot. */ | |
2253 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2254 | { | |
2255 | inst_env->invalid = 1; | |
2256 | return; | |
2257 | } | |
2258 | ||
fa4e4598 OF |
2259 | /* The calculation of prefix_value used to be after process_autoincrement, |
2260 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2261 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2262 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2263 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2264 | ||
2265 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2266 | inst_env->prefix_value += | |
2a9ecef2 OF |
2267 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2268 | ||
fa4e4598 OF |
2269 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2270 | { | |
2271 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2272 | } | |
2273 | ||
29134980 OF |
2274 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2275 | need updating. */ | |
2276 | inst_env->slot_needed = 0; | |
2277 | inst_env->prefix_found = 1; | |
2278 | } | |
2279 | ||
2280 | /* Calculates the prefix value for the index addressing mode. */ | |
2281 | ||
a78f21af | 2282 | static void |
29134980 OF |
2283 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2284 | { | |
2285 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2286 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2287 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2288 | { | |
2289 | inst_env->invalid = 1; | |
2290 | return; | |
2291 | } | |
2292 | ||
2293 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2294 | ||
2295 | /* The offset is the operand2 value shifted the size of the instruction | |
2296 | to the left. */ | |
2297 | inst_env->prefix_value += | |
2298 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2299 | ||
2300 | /* If the PC is operand1 (base) the address used is the address after | |
2301 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2302 | for the prefix operation). */ | |
2303 | if (cris_get_operand1 (inst) == REG_PC) | |
2304 | { | |
2305 | inst_env->prefix_value += 2; | |
2306 | } | |
2307 | ||
2308 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2309 | need updating. */ | |
2310 | inst_env->slot_needed = 0; | |
2311 | inst_env->xflag_found = 0; | |
2312 | inst_env->prefix_found = 1; | |
2313 | } | |
2314 | ||
2315 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2316 | ||
a78f21af | 2317 | static void |
29134980 OF |
2318 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2319 | { | |
2320 | ||
2321 | CORE_ADDR address; | |
2322 | ||
2323 | /* It's invalid to be in a delay slot. */ | |
2324 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2325 | { | |
2326 | inst_env->invalid = 1; | |
2327 | return; | |
2328 | } | |
2329 | ||
2330 | /* The prefix value is one dereference of the contents of the operand1 | |
2331 | register. */ | |
2332 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2333 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2334 | ||
2335 | /* Check if the mode is autoincrement. */ | |
2336 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2337 | { | |
2338 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2339 | } | |
2340 | ||
2341 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2342 | need updating. */ | |
2343 | inst_env->slot_needed = 0; | |
2344 | inst_env->xflag_found = 0; | |
2345 | inst_env->prefix_found = 1; | |
2346 | } | |
2347 | ||
2348 | /* Finds the destination for a branch with 8-bits offset. */ | |
2349 | ||
a78f21af | 2350 | static void |
29134980 OF |
2351 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2352 | { | |
2353 | ||
2354 | short offset; | |
2355 | ||
2356 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2357 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2358 | { | |
2359 | inst_env->invalid = 1; | |
2360 | return; | |
2361 | } | |
2362 | ||
2363 | /* We have a branch, find out where the branch will land. */ | |
2364 | offset = cris_get_branch_short_offset (inst); | |
2365 | ||
2366 | /* Check if the offset is signed. */ | |
2367 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2368 | { | |
2369 | offset |= 0xFF00; | |
2370 | } | |
2371 | ||
2372 | /* The offset ends with the sign bit, set it to zero. The address | |
2373 | should always be word aligned. */ | |
2374 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2375 | ||
2376 | inst_env->branch_found = 1; | |
2377 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2378 | ||
2379 | inst_env->slot_needed = 1; | |
2380 | inst_env->prefix_found = 0; | |
2381 | inst_env->xflag_found = 0; | |
2382 | inst_env->disable_interrupt = 1; | |
2383 | } | |
2384 | ||
2385 | /* Finds the destination for a branch with 16-bits offset. */ | |
2386 | ||
a78f21af | 2387 | static void |
29134980 OF |
2388 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2389 | { | |
2390 | short offset; | |
2391 | ||
2392 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2393 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2394 | { | |
2395 | inst_env->invalid = 1; | |
2396 | return; | |
2397 | } | |
2398 | ||
2399 | /* We have a branch, find out the offset for the branch. */ | |
2400 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2401 | ||
2402 | /* The instruction is one word longer than normal, so add one word | |
2403 | to the PC. */ | |
2404 | inst_env->reg[REG_PC] += 2; | |
2405 | ||
2406 | inst_env->branch_found = 1; | |
2407 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2408 | ||
2409 | ||
2410 | inst_env->slot_needed = 1; | |
2411 | inst_env->prefix_found = 0; | |
2412 | inst_env->xflag_found = 0; | |
2413 | inst_env->disable_interrupt = 1; | |
2414 | } | |
2415 | ||
2416 | /* Handles the ABS instruction. */ | |
2417 | ||
a78f21af | 2418 | static void |
29134980 OF |
2419 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2420 | { | |
2421 | ||
2422 | long value; | |
2423 | ||
2424 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2425 | if (inst_env->prefix_found) | |
2426 | { | |
2427 | inst_env->invalid = 1; | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | /* Check if the operation affects the PC. */ | |
2432 | if (cris_get_operand2 (inst) == REG_PC) | |
2433 | { | |
2434 | ||
2435 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2436 | if (inst_env->slot_needed) | |
2437 | { | |
2438 | inst_env->invalid = 1; | |
2439 | return; | |
2440 | } | |
2441 | ||
2442 | value = (long) inst_env->reg[REG_PC]; | |
2443 | ||
2444 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2445 | if (value != SIGNED_DWORD_MASK) | |
2446 | { | |
2447 | value = -value; | |
2448 | inst_env->reg[REG_PC] = (long) value; | |
2449 | } | |
2450 | } | |
2451 | ||
2452 | inst_env->slot_needed = 0; | |
2453 | inst_env->prefix_found = 0; | |
2454 | inst_env->xflag_found = 0; | |
2455 | inst_env->disable_interrupt = 0; | |
2456 | } | |
2457 | ||
2458 | /* Handles the ADDI instruction. */ | |
2459 | ||
a78f21af | 2460 | static void |
29134980 OF |
2461 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2462 | { | |
2463 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2464 | a prefix. */ | |
2465 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2466 | { | |
2467 | inst_env->invalid = 1; | |
2468 | return; | |
2469 | } | |
2470 | ||
2471 | inst_env->slot_needed = 0; | |
2472 | inst_env->prefix_found = 0; | |
2473 | inst_env->xflag_found = 0; | |
2474 | inst_env->disable_interrupt = 0; | |
2475 | } | |
2476 | ||
2477 | /* Handles the ASR instruction. */ | |
2478 | ||
a78f21af | 2479 | static void |
29134980 OF |
2480 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2481 | { | |
2482 | int shift_steps; | |
2483 | unsigned long value; | |
2484 | unsigned long signed_extend_mask = 0; | |
2485 | ||
2486 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2487 | if (inst_env->prefix_found) | |
2488 | { | |
2489 | inst_env->invalid = 1; | |
2490 | return; | |
2491 | } | |
2492 | ||
2493 | /* Check if the PC is the target register. */ | |
2494 | if (cris_get_operand2 (inst) == REG_PC) | |
2495 | { | |
2496 | /* It's invalid to change the PC in a delay slot. */ | |
2497 | if (inst_env->slot_needed) | |
2498 | { | |
2499 | inst_env->invalid = 1; | |
2500 | return; | |
2501 | } | |
2502 | /* Get the number of bits to shift. */ | |
2503 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2504 | value = inst_env->reg[REG_PC]; | |
2505 | ||
2506 | /* Find out how many bits the operation should apply to. */ | |
2507 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2508 | { | |
2509 | if (value & SIGNED_BYTE_MASK) | |
2510 | { | |
2511 | signed_extend_mask = 0xFF; | |
2512 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2513 | signed_extend_mask = ~signed_extend_mask; | |
2514 | } | |
2515 | value = value >> shift_steps; | |
2516 | value |= signed_extend_mask; | |
2517 | value &= 0xFF; | |
2518 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2519 | inst_env->reg[REG_PC] |= value; | |
2520 | } | |
2521 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2522 | { | |
2523 | if (value & SIGNED_WORD_MASK) | |
2524 | { | |
2525 | signed_extend_mask = 0xFFFF; | |
2526 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2527 | signed_extend_mask = ~signed_extend_mask; | |
2528 | } | |
2529 | value = value >> shift_steps; | |
2530 | value |= signed_extend_mask; | |
2531 | value &= 0xFFFF; | |
2532 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2533 | inst_env->reg[REG_PC] |= value; | |
2534 | } | |
2535 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2536 | { | |
2537 | if (value & SIGNED_DWORD_MASK) | |
2538 | { | |
2539 | signed_extend_mask = 0xFFFFFFFF; | |
2540 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2541 | signed_extend_mask = ~signed_extend_mask; | |
2542 | } | |
2543 | value = value >> shift_steps; | |
2544 | value |= signed_extend_mask; | |
2545 | inst_env->reg[REG_PC] = value; | |
2546 | } | |
2547 | } | |
2548 | inst_env->slot_needed = 0; | |
2549 | inst_env->prefix_found = 0; | |
2550 | inst_env->xflag_found = 0; | |
2551 | inst_env->disable_interrupt = 0; | |
2552 | } | |
2553 | ||
2554 | /* Handles the ASRQ instruction. */ | |
2555 | ||
a78f21af | 2556 | static void |
29134980 OF |
2557 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2558 | { | |
2559 | ||
2560 | int shift_steps; | |
2561 | unsigned long value; | |
2562 | unsigned long signed_extend_mask = 0; | |
2563 | ||
2564 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2565 | if (inst_env->prefix_found) | |
2566 | { | |
2567 | inst_env->invalid = 1; | |
2568 | return; | |
2569 | } | |
2570 | ||
2571 | /* Check if the PC is the target register. */ | |
2572 | if (cris_get_operand2 (inst) == REG_PC) | |
2573 | { | |
2574 | ||
2575 | /* It's invalid to change the PC in a delay slot. */ | |
2576 | if (inst_env->slot_needed) | |
2577 | { | |
2578 | inst_env->invalid = 1; | |
2579 | return; | |
2580 | } | |
2581 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2582 | want the the sign bit of the quick value. */ | |
2583 | shift_steps = cris_get_asr_shift_steps (inst); | |
2584 | value = inst_env->reg[REG_PC]; | |
2585 | if (value & SIGNED_DWORD_MASK) | |
2586 | { | |
2587 | signed_extend_mask = 0xFFFFFFFF; | |
2588 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2589 | signed_extend_mask = ~signed_extend_mask; | |
2590 | } | |
2591 | value = value >> shift_steps; | |
2592 | value |= signed_extend_mask; | |
2593 | inst_env->reg[REG_PC] = value; | |
2594 | } | |
2595 | inst_env->slot_needed = 0; | |
2596 | inst_env->prefix_found = 0; | |
2597 | inst_env->xflag_found = 0; | |
2598 | inst_env->disable_interrupt = 0; | |
2599 | } | |
2600 | ||
2601 | /* Handles the AX, EI and SETF instruction. */ | |
2602 | ||
a78f21af | 2603 | static void |
29134980 OF |
2604 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2605 | { | |
2606 | if (inst_env->prefix_found) | |
2607 | { | |
2608 | inst_env->invalid = 1; | |
2609 | return; | |
2610 | } | |
2611 | /* Check if the instruction is setting the X flag. */ | |
2612 | if (cris_is_xflag_bit_on (inst)) | |
2613 | { | |
2614 | inst_env->xflag_found = 1; | |
2615 | } | |
2616 | else | |
2617 | { | |
2618 | inst_env->xflag_found = 0; | |
2619 | } | |
2620 | inst_env->slot_needed = 0; | |
2621 | inst_env->prefix_found = 0; | |
2622 | inst_env->disable_interrupt = 1; | |
2623 | } | |
2624 | ||
2625 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2626 | register. Note that check_assign assumes that the caller has checked that | |
2627 | there is a prefix to this instruction. The mode check depends on this. */ | |
2628 | ||
a78f21af | 2629 | static void |
29134980 OF |
2630 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2631 | { | |
2632 | /* Check if it's an assign addressing mode. */ | |
2633 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2634 | { | |
2635 | /* Assign the prefix value to operand 1. */ | |
2636 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2637 | } | |
2638 | } | |
2639 | ||
2640 | /* Handles the 2-operand BOUND instruction. */ | |
2641 | ||
a78f21af | 2642 | static void |
29134980 OF |
2643 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2644 | { | |
2645 | /* It's invalid to have the PC as the index operand. */ | |
2646 | if (cris_get_operand2 (inst) == REG_PC) | |
2647 | { | |
2648 | inst_env->invalid = 1; | |
2649 | return; | |
2650 | } | |
2651 | /* Check if we have a prefix. */ | |
2652 | if (inst_env->prefix_found) | |
2653 | { | |
2654 | check_assign (inst, inst_env); | |
2655 | } | |
2656 | /* Check if this is an autoincrement mode. */ | |
2657 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2658 | { | |
2659 | /* It's invalid to change the PC in a delay slot. */ | |
2660 | if (inst_env->slot_needed) | |
2661 | { | |
2662 | inst_env->invalid = 1; | |
2663 | return; | |
2664 | } | |
2665 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2666 | } | |
2667 | inst_env->slot_needed = 0; | |
2668 | inst_env->prefix_found = 0; | |
2669 | inst_env->xflag_found = 0; | |
2670 | inst_env->disable_interrupt = 0; | |
2671 | } | |
2672 | ||
2673 | /* Handles the 3-operand BOUND instruction. */ | |
2674 | ||
a78f21af | 2675 | static void |
29134980 OF |
2676 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2677 | { | |
2678 | /* It's an error if we haven't got a prefix. And it's also an error | |
2679 | if the PC is the destination register. */ | |
2680 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2681 | { | |
2682 | inst_env->invalid = 1; | |
2683 | return; | |
2684 | } | |
2685 | inst_env->slot_needed = 0; | |
2686 | inst_env->prefix_found = 0; | |
2687 | inst_env->xflag_found = 0; | |
2688 | inst_env->disable_interrupt = 0; | |
2689 | } | |
2690 | ||
2691 | /* Clears the status flags in inst_env. */ | |
2692 | ||
a78f21af | 2693 | static void |
29134980 OF |
2694 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2695 | { | |
2696 | /* It's an error if we have got a prefix. */ | |
2697 | if (inst_env->prefix_found) | |
2698 | { | |
2699 | inst_env->invalid = 1; | |
2700 | return; | |
2701 | } | |
2702 | ||
2703 | inst_env->slot_needed = 0; | |
2704 | inst_env->prefix_found = 0; | |
2705 | inst_env->xflag_found = 0; | |
2706 | inst_env->disable_interrupt = 0; | |
2707 | } | |
2708 | ||
2709 | /* Clears the status flags in inst_env. */ | |
2710 | ||
a78f21af | 2711 | static void |
29134980 OF |
2712 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2713 | { | |
2714 | /* It's an error if we have got a prefix. */ | |
2715 | if (inst_env->prefix_found) | |
2716 | { | |
2717 | inst_env->invalid = 1; | |
2718 | return; | |
2719 | } | |
2720 | ||
2721 | inst_env->slot_needed = 0; | |
2722 | inst_env->prefix_found = 0; | |
2723 | inst_env->xflag_found = 0; | |
2724 | inst_env->disable_interrupt = 1; | |
2725 | } | |
2726 | ||
2727 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2728 | ||
a78f21af | 2729 | static void |
29134980 OF |
2730 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2731 | { | |
2732 | /* Check if the target is the PC. */ | |
2733 | if (cris_get_operand2 (inst) == REG_PC) | |
2734 | { | |
2735 | /* The instruction will clear the instruction's size bits. */ | |
2736 | int clear_size = cris_get_clear_size (inst); | |
2737 | if (clear_size == INST_BYTE_SIZE) | |
2738 | { | |
2739 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2740 | } | |
2741 | if (clear_size == INST_WORD_SIZE) | |
2742 | { | |
2743 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2744 | } | |
2745 | if (clear_size == INST_DWORD_SIZE) | |
2746 | { | |
2747 | inst_env->delay_slot_pc = 0x0; | |
2748 | } | |
2749 | /* The jump will be delayed with one delay slot. So we need a delay | |
2750 | slot. */ | |
2751 | inst_env->slot_needed = 1; | |
2752 | inst_env->delay_slot_pc_active = 1; | |
2753 | } | |
2754 | else | |
2755 | { | |
2756 | /* The PC will not change => no delay slot. */ | |
2757 | inst_env->slot_needed = 0; | |
2758 | } | |
2759 | inst_env->prefix_found = 0; | |
2760 | inst_env->xflag_found = 0; | |
2761 | inst_env->disable_interrupt = 0; | |
2762 | } | |
2763 | ||
2764 | /* Handles the TEST instruction if it's in register mode. */ | |
2765 | ||
a78f21af | 2766 | static void |
29134980 OF |
2767 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2768 | { | |
2769 | /* It's an error if we have got a prefix. */ | |
2770 | if (inst_env->prefix_found) | |
2771 | { | |
2772 | inst_env->invalid = 1; | |
2773 | return; | |
2774 | } | |
2775 | inst_env->slot_needed = 0; | |
2776 | inst_env->prefix_found = 0; | |
2777 | inst_env->xflag_found = 0; | |
2778 | inst_env->disable_interrupt = 0; | |
2779 | ||
2780 | } | |
2781 | ||
2782 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2783 | in register mode. */ | |
2784 | ||
a78f21af | 2785 | static void |
29134980 OF |
2786 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2787 | { | |
2788 | /* Check if we are in a prefix mode. */ | |
2789 | if (inst_env->prefix_found) | |
2790 | { | |
2791 | /* The only way the PC can change is if this instruction is in | |
2792 | assign addressing mode. */ | |
2793 | check_assign (inst, inst_env); | |
2794 | } | |
2795 | /* Indirect mode can't change the PC so just check if the mode is | |
2796 | autoincrement. */ | |
2797 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2798 | { | |
2799 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2800 | } | |
2801 | inst_env->slot_needed = 0; | |
2802 | inst_env->prefix_found = 0; | |
2803 | inst_env->xflag_found = 0; | |
2804 | inst_env->disable_interrupt = 0; | |
2805 | } | |
2806 | ||
2807 | /* Checks that the PC isn't the destination register or the instructions has | |
2808 | a prefix. */ | |
2809 | ||
a78f21af | 2810 | static void |
29134980 OF |
2811 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2812 | { | |
2813 | /* It's invalid to have the PC as the destination. The instruction can't | |
2814 | have a prefix. */ | |
2815 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2816 | { | |
2817 | inst_env->invalid = 1; | |
2818 | return; | |
2819 | } | |
2820 | ||
2821 | inst_env->slot_needed = 0; | |
2822 | inst_env->prefix_found = 0; | |
2823 | inst_env->xflag_found = 0; | |
2824 | inst_env->disable_interrupt = 0; | |
2825 | } | |
2826 | ||
2827 | /* Checks that the instruction doesn't have a prefix. */ | |
2828 | ||
a78f21af | 2829 | static void |
29134980 OF |
2830 | break_op (unsigned short inst, inst_env_type *inst_env) |
2831 | { | |
2832 | /* The instruction can't have a prefix. */ | |
2833 | if (inst_env->prefix_found) | |
2834 | { | |
2835 | inst_env->invalid = 1; | |
2836 | return; | |
2837 | } | |
2838 | ||
2839 | inst_env->slot_needed = 0; | |
2840 | inst_env->prefix_found = 0; | |
2841 | inst_env->xflag_found = 0; | |
2842 | inst_env->disable_interrupt = 1; | |
2843 | } | |
2844 | ||
2845 | /* Checks that the PC isn't the destination register and that the instruction | |
2846 | doesn't have a prefix. */ | |
2847 | ||
a78f21af | 2848 | static void |
29134980 OF |
2849 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2850 | { | |
2851 | /* It's invalid to have the PC as the destination. The instruction can't | |
2852 | have a prefix. */ | |
2853 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2854 | { | |
2855 | inst_env->invalid = 1; | |
2856 | return; | |
2857 | } | |
2858 | ||
2859 | inst_env->slot_needed = 0; | |
2860 | inst_env->prefix_found = 0; | |
2861 | inst_env->xflag_found = 0; | |
2862 | inst_env->disable_interrupt = 1; | |
2863 | } | |
2864 | ||
2865 | /* Handles the register mode JUMP instruction. */ | |
2866 | ||
a78f21af | 2867 | static void |
29134980 OF |
2868 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2869 | { | |
2870 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2871 | you can't have a prefix. */ | |
2872 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2873 | { | |
2874 | inst_env->invalid = 1; | |
2875 | return; | |
2876 | } | |
2877 | ||
2878 | /* Just change the PC. */ | |
2879 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2880 | inst_env->slot_needed = 0; | |
2881 | inst_env->prefix_found = 0; | |
2882 | inst_env->xflag_found = 0; | |
2883 | inst_env->disable_interrupt = 1; | |
2884 | } | |
2885 | ||
2886 | /* Handles the JUMP instruction for all modes except register. */ | |
2887 | ||
a78f21af AC |
2888 | static void |
2889 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2890 | { |
2891 | unsigned long newpc; | |
2892 | CORE_ADDR address; | |
2893 | ||
2894 | /* It's invalid to do a JUMP in a delay slot. */ | |
2895 | if (inst_env->slot_needed) | |
2896 | { | |
2897 | inst_env->invalid = 1; | |
2898 | } | |
2899 | else | |
2900 | { | |
2901 | /* Check if we have a prefix. */ | |
2902 | if (inst_env->prefix_found) | |
2903 | { | |
2904 | check_assign (inst, inst_env); | |
2905 | ||
2906 | /* Get the new value for the the PC. */ | |
2907 | newpc = | |
2908 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2909 | 4); | |
2910 | } | |
2911 | else | |
2912 | { | |
2913 | /* Get the new value for the PC. */ | |
2914 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2915 | newpc = read_memory_unsigned_integer (address, 4); | |
2916 | ||
2917 | /* Check if we should increment a register. */ | |
2918 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2919 | { | |
2920 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2921 | } | |
2922 | } | |
2923 | inst_env->reg[REG_PC] = newpc; | |
2924 | } | |
2925 | inst_env->slot_needed = 0; | |
2926 | inst_env->prefix_found = 0; | |
2927 | inst_env->xflag_found = 0; | |
2928 | inst_env->disable_interrupt = 1; | |
2929 | } | |
2930 | ||
2931 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2932 | ||
a78f21af | 2933 | static void |
29134980 OF |
2934 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2935 | { | |
2936 | if (inst_env->prefix_found) | |
2937 | { | |
2938 | /* The instruction has a prefix that means we are only interested if | |
2939 | the instruction is in assign mode. */ | |
2940 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2941 | { | |
2942 | /* The prefix handles the problem if we are in a delay slot. */ | |
2943 | if (cris_get_operand1 (inst) == REG_PC) | |
2944 | { | |
2945 | /* Just take care of the assign. */ | |
2946 | check_assign (inst, inst_env); | |
2947 | } | |
2948 | } | |
2949 | } | |
2950 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2951 | { | |
2952 | /* The instruction doesn't have a prefix, the only case left that we | |
2953 | are interested in is the autoincrement mode. */ | |
2954 | if (cris_get_operand1 (inst) == REG_PC) | |
2955 | { | |
2956 | /* If the PC is to be incremented it's invalid to be in a | |
2957 | delay slot. */ | |
2958 | if (inst_env->slot_needed) | |
2959 | { | |
2960 | inst_env->invalid = 1; | |
2961 | return; | |
2962 | } | |
2a9ecef2 OF |
2963 | |
2964 | /* The increment depends on the size of the special register. */ | |
2965 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2966 | { |
2967 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2968 | } | |
2a9ecef2 | 2969 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2970 | { |
2971 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2972 | } | |
2973 | else | |
2974 | { | |
2975 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2976 | } | |
2977 | } | |
2978 | } | |
2979 | inst_env->slot_needed = 0; | |
2980 | inst_env->prefix_found = 0; | |
2981 | inst_env->xflag_found = 0; | |
2982 | inst_env->disable_interrupt = 1; | |
2983 | } | |
2984 | ||
2985 | /* Handles moves from special registers (aka P-register) for all modes | |
2986 | except register. */ | |
2987 | ||
a78f21af | 2988 | static void |
29134980 OF |
2989 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2990 | { | |
2991 | if (inst_env->prefix_found) | |
2992 | { | |
2993 | /* The instruction has a prefix that means we are only interested if | |
2994 | the instruction is in assign mode. */ | |
2995 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2996 | { | |
2997 | /* The prefix handles the problem if we are in a delay slot. */ | |
2998 | if (cris_get_operand1 (inst) == REG_PC) | |
2999 | { | |
3000 | /* Just take care of the assign. */ | |
3001 | check_assign (inst, inst_env); | |
3002 | } | |
3003 | } | |
3004 | } | |
3005 | /* The instruction doesn't have a prefix, the only case left that we | |
3006 | are interested in is the autoincrement mode. */ | |
3007 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
3008 | { | |
3009 | if (cris_get_operand1 (inst) == REG_PC) | |
3010 | { | |
3011 | /* If the PC is to be incremented it's invalid to be in a | |
3012 | delay slot. */ | |
3013 | if (inst_env->slot_needed) | |
3014 | { | |
3015 | inst_env->invalid = 1; | |
3016 | return; | |
3017 | } | |
2a9ecef2 OF |
3018 | |
3019 | /* The increment depends on the size of the special register. */ | |
3020 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
3021 | { |
3022 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
3023 | } | |
2a9ecef2 | 3024 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
3025 | { |
3026 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
3027 | } | |
3028 | else | |
3029 | { | |
3030 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
3031 | } | |
3032 | } | |
3033 | } | |
3034 | inst_env->slot_needed = 0; | |
3035 | inst_env->prefix_found = 0; | |
3036 | inst_env->xflag_found = 0; | |
3037 | inst_env->disable_interrupt = 1; | |
3038 | } | |
3039 | ||
3040 | /* Handles moves from special registers (aka P-register) when the mode | |
3041 | is register. */ | |
3042 | ||
a78f21af | 3043 | static void |
29134980 OF |
3044 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
3045 | { | |
3046 | /* Register mode move from special register can't have a prefix. */ | |
3047 | if (inst_env->prefix_found) | |
3048 | { | |
3049 | inst_env->invalid = 1; | |
3050 | return; | |
3051 | } | |
3052 | ||
3053 | if (cris_get_operand1 (inst) == REG_PC) | |
3054 | { | |
3055 | /* It's invalid to change the PC in a delay slot. */ | |
3056 | if (inst_env->slot_needed) | |
3057 | { | |
3058 | inst_env->invalid = 1; | |
3059 | return; | |
3060 | } | |
3061 | /* The destination is the PC, the jump will have a delay slot. */ | |
3062 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3063 | inst_env->slot_needed = 1; | |
3064 | inst_env->delay_slot_pc_active = 1; | |
3065 | } | |
3066 | else | |
3067 | { | |
3068 | /* If the destination isn't PC, there will be no jump. */ | |
3069 | inst_env->slot_needed = 0; | |
3070 | } | |
3071 | inst_env->prefix_found = 0; | |
3072 | inst_env->xflag_found = 0; | |
3073 | inst_env->disable_interrupt = 1; | |
3074 | } | |
3075 | ||
3076 | /* Handles the MOVEM from memory to general register instruction. */ | |
3077 | ||
a78f21af | 3078 | static void |
29134980 OF |
3079 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3080 | { | |
3081 | if (inst_env->prefix_found) | |
3082 | { | |
3083 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3084 | MOVEM instruction going to change the PC? */ | |
3085 | if (cris_get_operand2 (inst) >= REG_PC) | |
3086 | { | |
3087 | inst_env->reg[REG_PC] = | |
3088 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
3089 | } | |
3090 | /* The assign value is the value after the increment. Normally, the | |
3091 | assign value is the value before the increment. */ | |
3092 | if ((cris_get_operand1 (inst) == REG_PC) | |
3093 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3094 | { | |
3095 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3096 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3097 | } | |
3098 | } | |
3099 | else | |
3100 | { | |
3101 | /* Is the MOVEM instruction going to change the PC? */ | |
3102 | if (cris_get_operand2 (inst) == REG_PC) | |
3103 | { | |
3104 | /* It's invalid to change the PC in a delay slot. */ | |
3105 | if (inst_env->slot_needed) | |
3106 | { | |
3107 | inst_env->invalid = 1; | |
3108 | return; | |
3109 | } | |
3110 | inst_env->reg[REG_PC] = | |
3111 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3112 | 4); | |
3113 | } | |
3114 | /* The increment is not depending on the size, instead it's depending | |
3115 | on the number of registers loaded from memory. */ | |
3116 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3117 | { | |
3118 | /* It's invalid to change the PC in a delay slot. */ | |
3119 | if (inst_env->slot_needed) | |
3120 | { | |
3121 | inst_env->invalid = 1; | |
3122 | return; | |
3123 | } | |
3124 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3125 | } | |
3126 | } | |
3127 | inst_env->slot_needed = 0; | |
3128 | inst_env->prefix_found = 0; | |
3129 | inst_env->xflag_found = 0; | |
3130 | inst_env->disable_interrupt = 0; | |
3131 | } | |
3132 | ||
3133 | /* Handles the MOVEM to memory from general register instruction. */ | |
3134 | ||
a78f21af | 3135 | static void |
29134980 OF |
3136 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3137 | { | |
3138 | if (inst_env->prefix_found) | |
3139 | { | |
3140 | /* The assign value is the value after the increment. Normally, the | |
3141 | assign value is the value before the increment. */ | |
3142 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3143 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3144 | { | |
3145 | /* The prefix handles the problem if we are in a delay slot. */ | |
3146 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3147 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3148 | } | |
3149 | } | |
3150 | else | |
3151 | { | |
3152 | /* The increment is not depending on the size, instead it's depending | |
3153 | on the number of registers loaded to memory. */ | |
3154 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3155 | { | |
3156 | /* It's invalid to change the PC in a delay slot. */ | |
3157 | if (inst_env->slot_needed) | |
3158 | { | |
3159 | inst_env->invalid = 1; | |
3160 | return; | |
3161 | } | |
3162 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3163 | } | |
3164 | } | |
3165 | inst_env->slot_needed = 0; | |
3166 | inst_env->prefix_found = 0; | |
3167 | inst_env->xflag_found = 0; | |
3168 | inst_env->disable_interrupt = 0; | |
3169 | } | |
3170 | ||
29134980 OF |
3171 | /* Handles the intructions that's not yet implemented, by setting |
3172 | inst_env->invalid to true. */ | |
3173 | ||
a78f21af | 3174 | static void |
29134980 OF |
3175 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3176 | { | |
3177 | inst_env->invalid = 1; | |
3178 | } | |
3179 | ||
3180 | /* Handles the XOR instruction. */ | |
3181 | ||
a78f21af | 3182 | static void |
29134980 OF |
3183 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3184 | { | |
3185 | /* XOR can't have a prefix. */ | |
3186 | if (inst_env->prefix_found) | |
3187 | { | |
3188 | inst_env->invalid = 1; | |
3189 | return; | |
3190 | } | |
3191 | ||
3192 | /* Check if the PC is the target. */ | |
3193 | if (cris_get_operand2 (inst) == REG_PC) | |
3194 | { | |
3195 | /* It's invalid to change the PC in a delay slot. */ | |
3196 | if (inst_env->slot_needed) | |
3197 | { | |
3198 | inst_env->invalid = 1; | |
3199 | return; | |
3200 | } | |
3201 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3202 | } | |
3203 | inst_env->slot_needed = 0; | |
3204 | inst_env->prefix_found = 0; | |
3205 | inst_env->xflag_found = 0; | |
3206 | inst_env->disable_interrupt = 0; | |
3207 | } | |
3208 | ||
3209 | /* Handles the MULS instruction. */ | |
3210 | ||
a78f21af | 3211 | static void |
29134980 OF |
3212 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3213 | { | |
3214 | /* MULS/U can't have a prefix. */ | |
3215 | if (inst_env->prefix_found) | |
3216 | { | |
3217 | inst_env->invalid = 1; | |
3218 | return; | |
3219 | } | |
3220 | ||
3221 | /* Consider it invalid if the PC is the target. */ | |
3222 | if (cris_get_operand2 (inst) == REG_PC) | |
3223 | { | |
3224 | inst_env->invalid = 1; | |
3225 | return; | |
3226 | } | |
3227 | inst_env->slot_needed = 0; | |
3228 | inst_env->prefix_found = 0; | |
3229 | inst_env->xflag_found = 0; | |
3230 | inst_env->disable_interrupt = 0; | |
3231 | } | |
3232 | ||
3233 | /* Handles the MULU instruction. */ | |
3234 | ||
a78f21af | 3235 | static void |
29134980 OF |
3236 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3237 | { | |
3238 | /* MULS/U can't have a prefix. */ | |
3239 | if (inst_env->prefix_found) | |
3240 | { | |
3241 | inst_env->invalid = 1; | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | /* Consider it invalid if the PC is the target. */ | |
3246 | if (cris_get_operand2 (inst) == REG_PC) | |
3247 | { | |
3248 | inst_env->invalid = 1; | |
3249 | return; | |
3250 | } | |
3251 | inst_env->slot_needed = 0; | |
3252 | inst_env->prefix_found = 0; | |
3253 | inst_env->xflag_found = 0; | |
3254 | inst_env->disable_interrupt = 0; | |
3255 | } | |
3256 | ||
3257 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3258 | The MOVE instruction is the move from source to register. */ | |
3259 | ||
a78f21af | 3260 | static void |
29134980 OF |
3261 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3262 | unsigned long source1, unsigned long source2) | |
3263 | { | |
3264 | unsigned long pc_mask; | |
3265 | unsigned long operation_mask; | |
3266 | ||
3267 | /* Find out how many bits the operation should apply to. */ | |
3268 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3269 | { | |
3270 | pc_mask = 0xFFFFFF00; | |
3271 | operation_mask = 0xFF; | |
3272 | } | |
3273 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3274 | { | |
3275 | pc_mask = 0xFFFF0000; | |
3276 | operation_mask = 0xFFFF; | |
3277 | } | |
3278 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3279 | { | |
3280 | pc_mask = 0x0; | |
3281 | operation_mask = 0xFFFFFFFF; | |
3282 | } | |
3283 | else | |
3284 | { | |
3285 | /* The size is out of range. */ | |
3286 | inst_env->invalid = 1; | |
3287 | return; | |
3288 | } | |
3289 | ||
3290 | /* The instruction just works on uw_operation_mask bits. */ | |
3291 | source2 &= operation_mask; | |
3292 | source1 &= operation_mask; | |
3293 | ||
3294 | /* Now calculate the result. The opcode's 3 first bits separates | |
3295 | the different actions. */ | |
3296 | switch (cris_get_opcode (inst) & 7) | |
3297 | { | |
3298 | case 0: /* add */ | |
3299 | source1 += source2; | |
3300 | break; | |
3301 | ||
3302 | case 1: /* move */ | |
3303 | source1 = source2; | |
3304 | break; | |
3305 | ||
3306 | case 2: /* subtract */ | |
3307 | source1 -= source2; | |
3308 | break; | |
3309 | ||
3310 | case 3: /* compare */ | |
3311 | break; | |
3312 | ||
3313 | case 4: /* and */ | |
3314 | source1 &= source2; | |
3315 | break; | |
3316 | ||
3317 | case 5: /* or */ | |
3318 | source1 |= source2; | |
3319 | break; | |
3320 | ||
3321 | default: | |
3322 | inst_env->invalid = 1; | |
3323 | return; | |
3324 | ||
3325 | break; | |
3326 | } | |
3327 | ||
3328 | /* Make sure that the result doesn't contain more than the instruction | |
3329 | size bits. */ | |
3330 | source2 &= operation_mask; | |
3331 | ||
3332 | /* Calculate the new breakpoint address. */ | |
3333 | inst_env->reg[REG_PC] &= pc_mask; | |
3334 | inst_env->reg[REG_PC] |= source1; | |
3335 | ||
3336 | } | |
3337 | ||
3338 | /* Extends the value from either byte or word size to a dword. If the mode | |
3339 | is zero extend then the value is extended with zero. If instead the mode | |
3340 | is signed extend the sign bit of the value is taken into consideration. */ | |
3341 | ||
a78f21af | 3342 | static unsigned long |
29134980 OF |
3343 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3344 | { | |
3345 | /* The size can be either byte or word, check which one it is. | |
3346 | Don't check the highest bit, it's indicating if it's a zero | |
3347 | or sign extend. */ | |
3348 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3349 | { | |
3350 | /* Word size. */ | |
3351 | value &= 0xFFFF; | |
3352 | ||
3353 | /* Check if the instruction is signed extend. If so, check if value has | |
3354 | the sign bit on. */ | |
3355 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3356 | { | |
3357 | value |= SIGNED_WORD_EXTEND_MASK; | |
3358 | } | |
3359 | } | |
3360 | else | |
3361 | { | |
3362 | /* Byte size. */ | |
3363 | value &= 0xFF; | |
3364 | ||
3365 | /* Check if the instruction is signed extend. If so, check if value has | |
3366 | the sign bit on. */ | |
3367 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3368 | { | |
3369 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3370 | } | |
3371 | } | |
3372 | /* The size should now be dword. */ | |
3373 | cris_set_size_to_dword (inst); | |
3374 | return value; | |
3375 | } | |
3376 | ||
3377 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3378 | instruction. The MOVE instruction is the move from source to register. */ | |
3379 | ||
a78f21af | 3380 | static void |
29134980 OF |
3381 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3382 | inst_env_type *inst_env) | |
3383 | { | |
3384 | unsigned long operand1; | |
3385 | unsigned long operand2; | |
3386 | ||
3387 | /* It's invalid to have a prefix to the instruction. This is a register | |
3388 | mode instruction and can't have a prefix. */ | |
3389 | if (inst_env->prefix_found) | |
3390 | { | |
3391 | inst_env->invalid = 1; | |
3392 | return; | |
3393 | } | |
3394 | /* Check if the instruction has PC as its target. */ | |
3395 | if (cris_get_operand2 (inst) == REG_PC) | |
3396 | { | |
3397 | if (inst_env->slot_needed) | |
3398 | { | |
3399 | inst_env->invalid = 1; | |
3400 | return; | |
3401 | } | |
3402 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3403 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3404 | operand2 = inst_env->reg[REG_PC]; |
3405 | ||
3406 | /* Check if it's a extend, signed or zero instruction. */ | |
3407 | if (cris_get_opcode (inst) < 4) | |
3408 | { | |
3409 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3410 | } | |
3411 | /* Calculate the PC value after the instruction, i.e. where the | |
3412 | breakpoint should be. The order of the udw_operands is vital. */ | |
3413 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3414 | } | |
3415 | inst_env->slot_needed = 0; | |
3416 | inst_env->prefix_found = 0; | |
3417 | inst_env->xflag_found = 0; | |
3418 | inst_env->disable_interrupt = 0; | |
3419 | } | |
3420 | ||
3421 | /* Returns the data contained at address. The size of the data is derived from | |
3422 | the size of the operation. If the instruction is a zero or signed | |
3423 | extend instruction, the size field is changed in instruction. */ | |
3424 | ||
a78f21af | 3425 | static unsigned long |
29134980 OF |
3426 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3427 | { | |
3428 | int size = cris_get_size (*inst); | |
3429 | unsigned long value; | |
3430 | ||
3431 | /* If it's an extend instruction we don't want the signed extend bit, | |
3432 | because it influences the size. */ | |
3433 | if (cris_get_opcode (*inst) < 4) | |
3434 | { | |
3435 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3436 | } | |
3437 | /* Is there a need for checking the size? Size should contain the number of | |
3438 | bytes to read. */ | |
3439 | size = 1 << size; | |
3440 | value = read_memory_unsigned_integer (address, size); | |
3441 | ||
3442 | /* Check if it's an extend, signed or zero instruction. */ | |
3443 | if (cris_get_opcode (*inst) < 4) | |
3444 | { | |
3445 | value = do_sign_or_zero_extend (value, inst); | |
3446 | } | |
3447 | return value; | |
3448 | } | |
3449 | ||
3450 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3451 | instructions. The MOVE instruction is the move from source to register. */ | |
3452 | ||
a78f21af | 3453 | static void |
29134980 OF |
3454 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3455 | inst_env_type *inst_env) | |
3456 | { | |
3457 | unsigned long operand2; | |
3458 | unsigned long operand3; | |
3459 | ||
3460 | check_assign (inst, inst_env); | |
3461 | if (cris_get_operand2 (inst) == REG_PC) | |
3462 | { | |
3463 | operand2 = inst_env->reg[REG_PC]; | |
3464 | ||
3465 | /* Get the value of the third operand. */ | |
3466 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3467 | ||
3468 | /* Calculate the PC value after the instruction, i.e. where the | |
3469 | breakpoint should be. The order of the udw_operands is vital. */ | |
3470 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3471 | } | |
3472 | inst_env->slot_needed = 0; | |
3473 | inst_env->prefix_found = 0; | |
3474 | inst_env->xflag_found = 0; | |
3475 | inst_env->disable_interrupt = 0; | |
3476 | } | |
3477 | ||
3478 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3479 | OR instructions. Note that for this to work as expected, the calling | |
3480 | function must have made sure that there is a prefix to this instruction. */ | |
3481 | ||
a78f21af | 3482 | static void |
29134980 OF |
3483 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3484 | inst_env_type *inst_env) | |
3485 | { | |
3486 | unsigned long operand2; | |
3487 | unsigned long operand3; | |
3488 | ||
3489 | if (cris_get_operand1 (inst) == REG_PC) | |
3490 | { | |
3491 | /* The PC will be changed by the instruction. */ | |
3492 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3493 | ||
3494 | /* Get the value of the third operand. */ | |
3495 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3496 | ||
3497 | /* Calculate the PC value after the instruction, i.e. where the | |
3498 | breakpoint should be. */ | |
3499 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3500 | } | |
3501 | inst_env->slot_needed = 0; | |
3502 | inst_env->prefix_found = 0; | |
3503 | inst_env->xflag_found = 0; | |
3504 | inst_env->disable_interrupt = 0; | |
3505 | } | |
3506 | ||
3507 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3508 | instructions. The MOVE instruction is the move from source to register. */ | |
3509 | ||
a78f21af | 3510 | static void |
29134980 OF |
3511 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3512 | inst_env_type *inst_env) | |
3513 | { | |
3514 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3515 | { | |
3516 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3517 | SUB, AND or OR something weird is going on (if everything works these | |
3518 | instructions should end up in the three operand version). */ | |
3519 | inst_env->invalid = 1; | |
3520 | return; | |
3521 | } | |
3522 | else | |
3523 | { | |
3524 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3525 | so use it. */ | |
3526 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3527 | } | |
3528 | inst_env->slot_needed = 0; | |
3529 | inst_env->prefix_found = 0; | |
3530 | inst_env->xflag_found = 0; | |
3531 | inst_env->disable_interrupt = 0; | |
3532 | } | |
3533 | ||
3534 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3535 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3536 | source to register. */ | |
3537 | ||
a78f21af | 3538 | static void |
29134980 OF |
3539 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3540 | inst_env_type *inst_env) | |
3541 | { | |
3542 | unsigned long operand1; | |
3543 | unsigned long operand2; | |
3544 | unsigned long operand3; | |
3545 | int size; | |
3546 | ||
3547 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3548 | Check if the destination register is the PC. */ | |
3549 | if (cris_get_operand2 (inst) == REG_PC) | |
3550 | { | |
3551 | /* Must be done here, get_data_from_address may change the size | |
3552 | field. */ | |
3553 | size = cris_get_size (inst); | |
3554 | operand2 = inst_env->reg[REG_PC]; | |
3555 | ||
3556 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3557 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3558 | operand3 = get_data_from_address (&inst, operand1); | |
3559 | ||
3560 | /* Calculate the PC value after the instruction, i.e. where the | |
3561 | breakpoint should be. The order of the udw_operands is vital. */ | |
3562 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3563 | } | |
3564 | /* If this is an autoincrement addressing mode, check if the increment | |
3565 | changes the PC. */ | |
3566 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3567 | { | |
3568 | /* Get the size field. */ | |
3569 | size = cris_get_size (inst); | |
3570 | ||
3571 | /* If it's an extend instruction we don't want the signed extend bit, | |
3572 | because it influences the size. */ | |
3573 | if (cris_get_opcode (inst) < 4) | |
3574 | { | |
3575 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3576 | } | |
3577 | process_autoincrement (size, inst, inst_env); | |
3578 | } | |
3579 | inst_env->slot_needed = 0; | |
3580 | inst_env->prefix_found = 0; | |
3581 | inst_env->xflag_found = 0; | |
3582 | inst_env->disable_interrupt = 0; | |
3583 | } | |
3584 | ||
3585 | /* Handles the two-operand addressing mode, all modes except register, for | |
3586 | the ADD, SUB CMP, AND and OR instruction. */ | |
3587 | ||
a78f21af | 3588 | static void |
29134980 OF |
3589 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3590 | inst_env_type *inst_env) | |
3591 | { | |
3592 | if (inst_env->prefix_found) | |
3593 | { | |
3594 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3595 | { | |
3596 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3597 | } | |
3598 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3599 | { | |
3600 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3601 | } | |
3602 | else | |
3603 | { | |
3604 | /* The mode is invalid for a prefixed base instruction. */ | |
3605 | inst_env->invalid = 1; | |
3606 | return; | |
3607 | } | |
3608 | } | |
3609 | else | |
3610 | { | |
3611 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3612 | } | |
3613 | } | |
3614 | ||
3615 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3616 | ||
a78f21af | 3617 | static void |
29134980 OF |
3618 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3619 | { | |
3620 | unsigned long operand1; | |
3621 | unsigned long operand2; | |
3622 | ||
3623 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3624 | instruction and can't have a prefix. */ | |
3625 | if (inst_env->prefix_found) | |
3626 | { | |
3627 | inst_env->invalid = 1; | |
3628 | return; | |
3629 | } | |
3630 | ||
3631 | /* Check if the instruction has PC as its target. */ | |
3632 | if (cris_get_operand2 (inst) == REG_PC) | |
3633 | { | |
3634 | if (inst_env->slot_needed) | |
3635 | { | |
3636 | inst_env->invalid = 1; | |
3637 | return; | |
3638 | } | |
3639 | operand1 = cris_get_quick_value (inst); | |
3640 | operand2 = inst_env->reg[REG_PC]; | |
3641 | ||
3642 | /* The size should now be dword. */ | |
3643 | cris_set_size_to_dword (&inst); | |
3644 | ||
3645 | /* Calculate the PC value after the instruction, i.e. where the | |
3646 | breakpoint should be. */ | |
3647 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3648 | } | |
3649 | inst_env->slot_needed = 0; | |
3650 | inst_env->prefix_found = 0; | |
3651 | inst_env->xflag_found = 0; | |
3652 | inst_env->disable_interrupt = 0; | |
3653 | } | |
3654 | ||
3655 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3656 | ||
a78f21af | 3657 | static void |
29134980 OF |
3658 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3659 | { | |
3660 | unsigned long operand1; | |
3661 | unsigned long operand2; | |
3662 | ||
3663 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3664 | instruction and can't have a prefix. */ | |
3665 | if (inst_env->prefix_found) | |
3666 | { | |
3667 | inst_env->invalid = 1; | |
3668 | return; | |
3669 | } | |
3670 | /* Check if the instruction has PC as its target. */ | |
3671 | if (cris_get_operand2 (inst) == REG_PC) | |
3672 | { | |
3673 | if (inst_env->slot_needed) | |
3674 | { | |
3675 | inst_env->invalid = 1; | |
3676 | return; | |
3677 | } | |
3678 | /* The instruction has the PC as its target register. */ | |
3679 | operand1 = cris_get_quick_value (inst); | |
3680 | operand2 = inst_env->reg[REG_PC]; | |
3681 | ||
3682 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3683 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3684 | { | |
3685 | /* sign extend */ | |
3686 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3687 | } | |
3688 | /* The size should now be dword. */ | |
3689 | cris_set_size_to_dword (&inst); | |
3690 | ||
3691 | /* Calculate the PC value after the instruction, i.e. where the | |
3692 | breakpoint should be. */ | |
3693 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3694 | } | |
3695 | inst_env->slot_needed = 0; | |
3696 | inst_env->prefix_found = 0; | |
3697 | inst_env->xflag_found = 0; | |
3698 | inst_env->disable_interrupt = 0; | |
3699 | } | |
3700 | ||
3701 | /* Translate op_type to a function and call it. */ | |
3702 | ||
a78f21af AC |
3703 | static void |
3704 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3705 | inst_env_type *inst_env) | |
29134980 OF |
3706 | { |
3707 | switch (op_type) | |
3708 | { | |
3709 | case cris_not_implemented_op: | |
3710 | not_implemented_op (inst, inst_env); | |
3711 | break; | |
3712 | ||
3713 | case cris_abs_op: | |
3714 | abs_op (inst, inst_env); | |
3715 | break; | |
3716 | ||
3717 | case cris_addi_op: | |
3718 | addi_op (inst, inst_env); | |
3719 | break; | |
3720 | ||
3721 | case cris_asr_op: | |
3722 | asr_op (inst, inst_env); | |
3723 | break; | |
3724 | ||
3725 | case cris_asrq_op: | |
3726 | asrq_op (inst, inst_env); | |
3727 | break; | |
3728 | ||
3729 | case cris_ax_ei_setf_op: | |
3730 | ax_ei_setf_op (inst, inst_env); | |
3731 | break; | |
3732 | ||
3733 | case cris_bdap_prefix: | |
3734 | bdap_prefix (inst, inst_env); | |
3735 | break; | |
3736 | ||
3737 | case cris_biap_prefix: | |
3738 | biap_prefix (inst, inst_env); | |
3739 | break; | |
3740 | ||
3741 | case cris_break_op: | |
3742 | break_op (inst, inst_env); | |
3743 | break; | |
3744 | ||
3745 | case cris_btst_nop_op: | |
3746 | btst_nop_op (inst, inst_env); | |
3747 | break; | |
3748 | ||
3749 | case cris_clearf_di_op: | |
3750 | clearf_di_op (inst, inst_env); | |
3751 | break; | |
3752 | ||
3753 | case cris_dip_prefix: | |
3754 | dip_prefix (inst, inst_env); | |
3755 | break; | |
3756 | ||
3757 | case cris_dstep_logshift_mstep_neg_not_op: | |
3758 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3759 | break; | |
3760 | ||
3761 | case cris_eight_bit_offset_branch_op: | |
3762 | eight_bit_offset_branch_op (inst, inst_env); | |
3763 | break; | |
3764 | ||
3765 | case cris_move_mem_to_reg_movem_op: | |
3766 | move_mem_to_reg_movem_op (inst, inst_env); | |
3767 | break; | |
3768 | ||
3769 | case cris_move_reg_to_mem_movem_op: | |
3770 | move_reg_to_mem_movem_op (inst, inst_env); | |
3771 | break; | |
3772 | ||
3773 | case cris_move_to_preg_op: | |
3774 | move_to_preg_op (inst, inst_env); | |
3775 | break; | |
3776 | ||
3777 | case cris_muls_op: | |
3778 | muls_op (inst, inst_env); | |
3779 | break; | |
3780 | ||
3781 | case cris_mulu_op: | |
3782 | mulu_op (inst, inst_env); | |
3783 | break; | |
3784 | ||
3785 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3786 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3787 | break; | |
3788 | ||
3789 | case cris_none_reg_mode_clear_test_op: | |
3790 | none_reg_mode_clear_test_op (inst, inst_env); | |
3791 | break; | |
3792 | ||
3793 | case cris_none_reg_mode_jump_op: | |
3794 | none_reg_mode_jump_op (inst, inst_env); | |
3795 | break; | |
3796 | ||
3797 | case cris_none_reg_mode_move_from_preg_op: | |
3798 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3799 | break; | |
3800 | ||
3801 | case cris_quick_mode_add_sub_op: | |
3802 | quick_mode_add_sub_op (inst, inst_env); | |
3803 | break; | |
3804 | ||
3805 | case cris_quick_mode_and_cmp_move_or_op: | |
3806 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3807 | break; | |
3808 | ||
3809 | case cris_quick_mode_bdap_prefix: | |
3810 | quick_mode_bdap_prefix (inst, inst_env); | |
3811 | break; | |
3812 | ||
3813 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3814 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3815 | break; | |
3816 | ||
3817 | case cris_reg_mode_clear_op: | |
3818 | reg_mode_clear_op (inst, inst_env); | |
3819 | break; | |
3820 | ||
3821 | case cris_reg_mode_jump_op: | |
3822 | reg_mode_jump_op (inst, inst_env); | |
3823 | break; | |
3824 | ||
3825 | case cris_reg_mode_move_from_preg_op: | |
3826 | reg_mode_move_from_preg_op (inst, inst_env); | |
3827 | break; | |
3828 | ||
3829 | case cris_reg_mode_test_op: | |
3830 | reg_mode_test_op (inst, inst_env); | |
3831 | break; | |
3832 | ||
3833 | case cris_scc_op: | |
3834 | scc_op (inst, inst_env); | |
3835 | break; | |
3836 | ||
3837 | case cris_sixteen_bit_offset_branch_op: | |
3838 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3839 | break; | |
3840 | ||
3841 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3842 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3843 | break; | |
3844 | ||
3845 | case cris_three_operand_bound_op: | |
3846 | three_operand_bound_op (inst, inst_env); | |
3847 | break; | |
3848 | ||
3849 | case cris_two_operand_bound_op: | |
3850 | two_operand_bound_op (inst, inst_env); | |
3851 | break; | |
3852 | ||
3853 | case cris_xor_op: | |
3854 | xor_op (inst, inst_env); | |
3855 | break; | |
3856 | } | |
3857 | } | |
3858 | ||
3859 | /* This wrapper is to avoid cris_get_assembler being called before | |
3860 | exec_bfd has been set. */ | |
3861 | ||
3862 | static int | |
a89aa300 | 3863 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3864 | { |
a89aa300 | 3865 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3866 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3867 | disassembler, even when there is no BFD. Does something like | |
3868 | "gdb; target remote; disassmeble *0x123" work? */ | |
3869 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3870 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3871 | gdb_assert (print_insn != NULL); |
3872 | return print_insn (addr, info); | |
29134980 OF |
3873 | } |
3874 | ||
dbbff683 OF |
3875 | /* Copied from <asm/elf.h>. */ |
3876 | typedef unsigned long elf_greg_t; | |
3877 | ||
3878 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3879 | #define CRISV10_ELF_NGREG 35 |
3880 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3881 | ||
3882 | #define CRISV32_ELF_NGREG 32 | |
3883 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3884 | |
3885 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3886 | ||
a78f21af | 3887 | static void |
c6b4e5a2 | 3888 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
dbbff683 | 3889 | { |
c600d464 | 3890 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3891 | int i; |
3892 | elf_greg_t *regp = *gregsetp; | |
3893 | static char zerobuf[4] = {0}; | |
3894 | ||
3895 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3896 | knows about the actual size of each register so that's no problem. */ | |
3897 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3898 | { | |
c6b4e5a2 | 3899 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
dbbff683 | 3900 | } |
c600d464 OF |
3901 | |
3902 | if (tdep->cris_version == 32) | |
3903 | { | |
3904 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3905 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3906 | be wrong. Issue a warning to alert the user. */ | |
3e8c568d | 3907 | regcache_raw_supply (regcache, gdbarch_pc_regnum (current_gdbarch), |
c600d464 OF |
3908 | (char *)®p[ERP_REGNUM]); |
3909 | ||
3910 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3911 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3912 | } | |
dbbff683 OF |
3913 | } |
3914 | ||
3915 | /* Use a local version of this function to get the correct types for | |
3916 | regsets, until multi-arch core support is ready. */ | |
3917 | ||
3918 | static void | |
9eefc95f UW |
3919 | fetch_core_registers (struct regcache *regcache, |
3920 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3921 | int which, CORE_ADDR reg_addr) |
3922 | { | |
3923 | elf_gregset_t gregset; | |
3924 | ||
3925 | switch (which) | |
3926 | { | |
3927 | case 0: | |
c600d464 OF |
3928 | if (core_reg_size != sizeof (elf_gregset_t) |
3929 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3930 | { |
8a3fe4f8 | 3931 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3932 | } |
3933 | else | |
3934 | { | |
3935 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3936 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3937 | } |
3938 | ||
3939 | default: | |
3940 | /* We've covered all the kinds of registers we know about here, | |
3941 | so this must be something we wouldn't know what to do with | |
3942 | anyway. Just ignore it. */ | |
3943 | break; | |
3944 | } | |
3945 | } | |
3946 | ||
3947 | static struct core_fns cris_elf_core_fns = | |
3948 | { | |
3949 | bfd_target_elf_flavour, /* core_flavour */ | |
3950 | default_check_format, /* check_format */ | |
3951 | default_core_sniffer, /* core_sniffer */ | |
3952 | fetch_core_registers, /* core_read_registers */ | |
3953 | NULL /* next */ | |
3954 | }; | |
3955 | ||
a78f21af AC |
3956 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3957 | ||
29134980 OF |
3958 | void |
3959 | _initialize_cris_tdep (void) | |
3960 | { | |
a5f6c8f5 OF |
3961 | static struct cmd_list_element *cris_set_cmdlist; |
3962 | static struct cmd_list_element *cris_show_cmdlist; | |
3963 | ||
29134980 OF |
3964 | struct cmd_list_element *c; |
3965 | ||
3966 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3967 | ||
29134980 | 3968 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3969 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3970 | &usr_cmd_cris_version, | |
7915a72c AC |
3971 | _("Set the current CRIS version."), |
3972 | _("Show the current CRIS version."), | |
bdd56253 OF |
3973 | _("\ |
3974 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3975 | Defaults to 10. "), | |
2c5b56ce | 3976 | set_cris_version, |
7915a72c | 3977 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3978 | &setlist, &showlist); |
0e6bdb31 OF |
3979 | |
3980 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3981 | cris_modes, &usr_cmd_cris_mode, | |
3982 | _("Set the current CRIS mode."), | |
3983 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3984 | _("\ |
3985 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3986 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3987 | set_cris_mode, |
3988 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3989 | &setlist, &showlist); | |
dbbff683 | 3990 | |
a5f6c8f5 OF |
3991 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3992 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3993 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3994 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3995 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3996 | set_cris_dwarf2_cfi, |
7915a72c | 3997 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3998 | &setlist, &showlist); |
3999 | ||
52bd1401 | 4000 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
4001 | } |
4002 | ||
4003 | /* Prints out all target specific values. */ | |
4004 | ||
4005 | static void | |
4006 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
4007 | { | |
4008 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4009 | if (tdep != NULL) | |
4010 | { | |
4011 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
4012 | tdep->cris_version); | |
0e6bdb31 OF |
4013 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
4014 | tdep->cris_mode); | |
a5f6c8f5 OF |
4015 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
4016 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
4017 | } |
4018 | } | |
4019 | ||
4020 | static void | |
a5f6c8f5 OF |
4021 | set_cris_version (char *ignore_args, int from_tty, |
4022 | struct cmd_list_element *c) | |
29134980 OF |
4023 | { |
4024 | struct gdbarch_info info; | |
4025 | ||
a5f6c8f5 | 4026 | usr_cmd_cris_version_valid = 1; |
29134980 | 4027 | |
a5f6c8f5 OF |
4028 | /* Update the current architecture, if needed. */ |
4029 | gdbarch_info_init (&info); | |
4030 | if (!gdbarch_update_p (info)) | |
4031 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4032 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4033 | } |
4034 | ||
0e6bdb31 OF |
4035 | static void |
4036 | set_cris_mode (char *ignore_args, int from_tty, | |
4037 | struct cmd_list_element *c) | |
4038 | { | |
4039 | struct gdbarch_info info; | |
4040 | ||
4041 | /* Update the current architecture, if needed. */ | |
4042 | gdbarch_info_init (&info); | |
4043 | if (!gdbarch_update_p (info)) | |
4044 | internal_error (__FILE__, __LINE__, | |
4045 | "cris_gdbarch_update: failed to update architecture."); | |
4046 | } | |
4047 | ||
29134980 | 4048 | static void |
a5f6c8f5 OF |
4049 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4050 | struct cmd_list_element *c) | |
29134980 OF |
4051 | { |
4052 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4053 | |
4054 | /* Update the current architecture, if needed. */ | |
4055 | gdbarch_info_init (&info); | |
4056 | if (!gdbarch_update_p (info)) | |
4057 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4058 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4059 | } |
4060 | ||
29134980 OF |
4061 | static struct gdbarch * |
4062 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4063 | { | |
4064 | struct gdbarch *gdbarch; | |
4065 | struct gdbarch_tdep *tdep; | |
4066 | int cris_version; | |
29134980 OF |
4067 | |
4068 | if (usr_cmd_cris_version_valid) | |
4069 | { | |
4070 | /* Trust the user's CRIS version setting. */ | |
4071 | cris_version = usr_cmd_cris_version; | |
4072 | } | |
c600d464 OF |
4073 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4074 | { | |
4075 | cris_version = 32; | |
4076 | } | |
29134980 OF |
4077 | else |
4078 | { | |
4079 | /* Assume it's CRIS version 10. */ | |
4080 | cris_version = 10; | |
4081 | } | |
4082 | ||
29134980 OF |
4083 | /* Make the current settings visible to the user. */ |
4084 | usr_cmd_cris_version = cris_version; | |
29134980 | 4085 | |
0e6bdb31 | 4086 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4087 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4088 | arches != NULL; | |
4089 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4090 | { | |
a5f6c8f5 OF |
4091 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4092 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4093 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4094 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4095 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4096 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4097 | return arches->gdbarch; |
4098 | } | |
4099 | ||
4100 | /* No matching architecture was found. Create a new one. */ | |
4101 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4102 | gdbarch = gdbarch_alloc (&info, tdep); | |
4103 | ||
a5f6c8f5 | 4104 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4105 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4106 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4107 | |
4108 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4109 | switch (info.byte_order) | |
4110 | { | |
778eb05e | 4111 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4112 | /* Ok. */ |
4113 | break; | |
4114 | ||
d7449b42 | 4115 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4116 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4117 | break; |
4118 | ||
4119 | default: | |
e2e0b3e5 | 4120 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4121 | } |
4122 | ||
b4206d25 | 4123 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4124 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4125 | cris_reg_struct_has_addr); | |
b5622e8d | 4126 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4127 | |
29134980 | 4128 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4129 | |
4130 | /* Length of ordinary registers used in push_word and a few other | |
4131 | places. register_size() is the real way to know how big a | |
4132 | register is. */ | |
a5f6c8f5 | 4133 | |
2e4b5889 | 4134 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 4135 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 4136 | which means we have to set this explicitly. */ |
c600d464 | 4137 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4138 | |
29134980 OF |
4139 | /* The total amount of space needed to store (in an array called registers) |
4140 | GDB's copy of the machine's register state. Note: We can not use | |
4141 | cris_register_size at this point, since it relies on current_gdbarch | |
4142 | being set. */ | |
4143 | switch (tdep->cris_version) | |
4144 | { | |
4145 | case 0: | |
4146 | case 1: | |
4147 | case 2: | |
4148 | case 3: | |
29134980 OF |
4149 | case 8: |
4150 | case 9: | |
a5f6c8f5 OF |
4151 | /* Old versions; not supported. */ |
4152 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4153 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4154 | break; |
4155 | ||
4156 | case 10: | |
4157 | case 11: | |
4158 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4159 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4160 | set_gdbarch_pc_regnum (gdbarch, 15); |
4161 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4162 | /* There are 32 registers (some of which may not be implemented). */ | |
4163 | set_gdbarch_num_regs (gdbarch, 32); | |
4164 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4165 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4166 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4167 | ||
4168 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4169 | break; | |
4170 | ||
4171 | case 32: | |
4172 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4173 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4174 | and pseudo-register PC (32 bits). */ | |
4175 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4176 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4177 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4178 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4179 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4180 | ||
4181 | set_gdbarch_cannot_store_register | |
4182 | (gdbarch, crisv32_cannot_store_register); | |
4183 | set_gdbarch_cannot_fetch_register | |
4184 | (gdbarch, crisv32_cannot_fetch_register); | |
4185 | ||
4186 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4187 | ||
4188 | set_gdbarch_single_step_through_delay | |
4189 | (gdbarch, crisv32_single_step_through_delay); | |
4190 | ||
29134980 OF |
4191 | break; |
4192 | ||
4193 | default: | |
c600d464 | 4194 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4195 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4196 | } |
4197 | ||
c600d464 OF |
4198 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4199 | have the same ABI). */ | |
2e4b5889 OF |
4200 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4201 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4202 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4203 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4204 | |
4205 | /* The stack grows downward. */ | |
4206 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4207 | ||
4208 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4209 | ||
2e4b5889 OF |
4210 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4211 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4212 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4213 | ||
a5f6c8f5 OF |
4214 | if (tdep->cris_dwarf2_cfi == 1) |
4215 | { | |
4216 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4217 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4218 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4219 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4220 | } | |
4221 | ||
0e6bdb31 OF |
4222 | if (tdep->cris_mode != cris_mode_guru) |
4223 | { | |
4224 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4225 | } | |
a5f6c8f5 | 4226 | |
2e4b5889 OF |
4227 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4228 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4229 | |
76a9d10f MK |
4230 | set_solib_svr4_fetch_link_map_offsets |
4231 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
dbbff683 | 4232 | |
36482093 AC |
4233 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4234 | disassembler, even when there is no BFD. Does something like | |
4235 | "gdb; target remote; disassmeble *0x123" work? */ | |
4236 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4237 | ||
29134980 OF |
4238 | return gdbarch; |
4239 | } |