Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
6b4d5c91 | 4 | |
29134980 OF |
5 | Contributed by Axis Communications AB. |
6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
7 | ||
a9762ec7 | 8 | This file is part of GDB. |
29134980 | 9 | |
a9762ec7 JB |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. | |
29134980 | 14 | |
a9762ec7 JB |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
29134980 | 19 | |
a9762ec7 JB |
20 | You should have received a copy of the GNU General Public License |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
29134980 OF |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
2e4b5889 OF |
25 | #include "frame-unwind.h" |
26 | #include "frame-base.h" | |
27 | #include "trad-frame.h" | |
28 | #include "dwarf2-frame.h" | |
29134980 OF |
29 | #include "symtab.h" |
30 | #include "inferior.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "target.h" | |
35 | #include "value.h" | |
36 | #include "opcode/cris.h" | |
749c8b38 | 37 | #include "osabi.h" |
29134980 OF |
38 | #include "arch-utils.h" |
39 | #include "regcache.h" | |
40 | ||
9ab9195f | 41 | #include "objfiles.h" |
29134980 | 42 | |
a5f6c8f5 | 43 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 44 | #include "solib-svr4.h" |
a89aa300 | 45 | #include "dis-asm.h" |
dbbff683 | 46 | |
749c8b38 RW |
47 | #include "cris-tdep.h" |
48 | ||
29134980 OF |
49 | enum cris_num_regs |
50 | { | |
51 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
52 | NUM_FREGS = 0, | |
53 | ||
54 | /* There are 16 general registers. */ | |
55 | NUM_GENREGS = 16, | |
56 | ||
57 | /* There are 16 special registers. */ | |
c600d464 OF |
58 | NUM_SPECREGS = 16, |
59 | ||
60 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
61 | ||
62 | /* CRISv32 has 16 support registers. */ | |
63 | NUM_SUPPREGS = 16 | |
29134980 OF |
64 | }; |
65 | ||
66 | /* Register numbers of various important registers. | |
2e4b5889 | 67 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
68 | STR_REGNUM Contains the address of structure return values. |
69 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
70 | ARG1_REGNUM Contains the first parameter to a function. | |
71 | ARG2_REGNUM Contains the second parameter to a function. | |
72 | ARG3_REGNUM Contains the third parameter to a function. | |
0963b4bd | 73 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
3e8c568d UW |
74 | gdbarch_sp_regnum Contains address of top of stack. |
75 | gdbarch_pc_regnum Contains address of next instruction. | |
29134980 OF |
76 | SRP_REGNUM Subroutine return pointer register. |
77 | BRP_REGNUM Breakpoint return pointer register. */ | |
78 | ||
29134980 OF |
79 | enum cris_regnums |
80 | { | |
81 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 82 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 83 | CRIS_FP_REGNUM = 8, |
c600d464 | 84 | /* ABI related registers. */ |
29134980 OF |
85 | STR_REGNUM = 9, |
86 | RET_REGNUM = 10, | |
87 | ARG1_REGNUM = 10, | |
88 | ARG2_REGNUM = 11, | |
89 | ARG3_REGNUM = 12, | |
90 | ARG4_REGNUM = 13, | |
91 | ||
c600d464 | 92 | /* Registers which happen to be common. */ |
29134980 | 93 | VR_REGNUM = 17, |
c600d464 OF |
94 | MOF_REGNUM = 23, |
95 | SRP_REGNUM = 27, | |
96 | ||
0963b4bd | 97 | /* CRISv10 et al. specific registers. */ |
c600d464 | 98 | P0_REGNUM = 16, |
29134980 OF |
99 | P4_REGNUM = 20, |
100 | CCR_REGNUM = 21, | |
29134980 OF |
101 | P8_REGNUM = 24, |
102 | IBR_REGNUM = 25, | |
103 | IRP_REGNUM = 26, | |
29134980 | 104 | BAR_REGNUM = 28, |
2a9ecef2 | 105 | DCCR_REGNUM = 29, |
29134980 | 106 | BRP_REGNUM = 30, |
c600d464 OF |
107 | USP_REGNUM = 31, |
108 | ||
109 | /* CRISv32 specific registers. */ | |
110 | ACR_REGNUM = 15, | |
111 | BZ_REGNUM = 16, | |
112 | PID_REGNUM = 18, | |
113 | SRS_REGNUM = 19, | |
114 | WZ_REGNUM = 20, | |
115 | EXS_REGNUM = 21, | |
116 | EDA_REGNUM = 22, | |
117 | DZ_REGNUM = 24, | |
118 | EBP_REGNUM = 25, | |
119 | ERP_REGNUM = 26, | |
120 | NRP_REGNUM = 28, | |
121 | CCS_REGNUM = 29, | |
122 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
123 | SPC_REGNUM = 31, | |
124 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
125 | ||
126 | S0_REGNUM = 33, | |
127 | S1_REGNUM = 34, | |
128 | S2_REGNUM = 35, | |
129 | S3_REGNUM = 36, | |
130 | S4_REGNUM = 37, | |
131 | S5_REGNUM = 38, | |
132 | S6_REGNUM = 39, | |
133 | S7_REGNUM = 40, | |
134 | S8_REGNUM = 41, | |
135 | S9_REGNUM = 42, | |
136 | S10_REGNUM = 43, | |
137 | S11_REGNUM = 44, | |
138 | S12_REGNUM = 45, | |
139 | S13_REGNUM = 46, | |
140 | S14_REGNUM = 47, | |
141 | S15_REGNUM = 48, | |
29134980 OF |
142 | }; |
143 | ||
144 | extern const struct cris_spec_reg cris_spec_regs[]; | |
145 | ||
146 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 | 147 | register names and sizes. */ |
e4286e57 | 148 | static unsigned int usr_cmd_cris_version; |
29134980 OF |
149 | |
150 | /* Indicates whether to trust the above variable. */ | |
151 | static int usr_cmd_cris_version_valid = 0; | |
152 | ||
41922353 OF |
153 | static const char cris_mode_normal[] = "normal"; |
154 | static const char cris_mode_guru[] = "guru"; | |
40478521 | 155 | static const char *const cris_modes[] = { |
0e6bdb31 OF |
156 | cris_mode_normal, |
157 | cris_mode_guru, | |
158 | 0 | |
159 | }; | |
160 | ||
161 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
162 | type of break instruction among other things. */ | |
163 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
164 | ||
a5f6c8f5 OF |
165 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
166 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 167 | |
a5f6c8f5 OF |
168 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
169 | ||
170 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
171 | #define SIGTRAMP_OFFSET0 0 | |
172 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
173 | #define SIGTRAMP_OFFSET1 4 | |
174 | ||
175 | static const unsigned short sigtramp_code[] = | |
176 | { | |
177 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
178 | SIGTRAMP_INSN1 /* break 13 */ | |
179 | }; | |
180 | ||
181 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
182 | ||
183 | /* Note: same length as normal sigtramp code. */ | |
184 | ||
185 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 186 | { |
a5f6c8f5 OF |
187 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
188 | SIGTRAMP_INSN1 /* break 13 */ | |
189 | }; | |
190 | ||
191 | /* If PC is in a sigtramp routine, return the address of the start of | |
192 | the routine. Otherwise, return 0. */ | |
193 | ||
194 | static CORE_ADDR | |
94afd7a6 | 195 | cris_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 196 | { |
94afd7a6 | 197 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 198 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 199 | |
94afd7a6 | 200 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
201 | return 0; |
202 | ||
e2a2a3e8 | 203 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 204 | { |
e2a2a3e8 | 205 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
206 | return 0; |
207 | ||
208 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 209 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
210 | return 0; |
211 | } | |
212 | ||
213 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
214 | return 0; | |
215 | ||
216 | return pc; | |
217 | } | |
218 | ||
219 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
220 | the routine. Otherwise, return 0. */ | |
221 | ||
222 | static CORE_ADDR | |
94afd7a6 | 223 | cris_rt_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 224 | { |
94afd7a6 | 225 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 226 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 227 | |
94afd7a6 | 228 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
229 | return 0; |
230 | ||
e2a2a3e8 | 231 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 232 | { |
e2a2a3e8 | 233 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
234 | return 0; |
235 | ||
236 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 237 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
238 | return 0; |
239 | } | |
240 | ||
241 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
242 | return 0; | |
243 | ||
244 | return pc; | |
245 | } | |
246 | ||
94afd7a6 UW |
247 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
248 | return the address of the associated sigcontext structure. */ | |
a5f6c8f5 OF |
249 | |
250 | static CORE_ADDR | |
94afd7a6 | 251 | cris_sigcontext_addr (struct frame_info *this_frame) |
a5f6c8f5 | 252 | { |
e17a4113 UW |
253 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
254 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a5f6c8f5 OF |
255 | CORE_ADDR pc; |
256 | CORE_ADDR sp; | |
e362b510 | 257 | gdb_byte buf[4]; |
a5f6c8f5 | 258 | |
e17a4113 UW |
259 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
260 | sp = extract_unsigned_integer (buf, 4, byte_order); | |
a5f6c8f5 OF |
261 | |
262 | /* Look for normal sigtramp frame first. */ | |
94afd7a6 | 263 | pc = cris_sigtramp_start (this_frame); |
a5f6c8f5 OF |
264 | if (pc) |
265 | { | |
266 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
267 | struct sigcontext as its first member, meaning the SP points to | |
268 | it already. */ | |
269 | return sp; | |
270 | } | |
271 | ||
94afd7a6 | 272 | pc = cris_rt_sigtramp_start (this_frame); |
a5f6c8f5 OF |
273 | if (pc) |
274 | { | |
275 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
276 | a struct ucontext, which in turn contains a struct sigcontext. | |
277 | Magic digging: | |
278 | 4 + 4 + 128 to struct ucontext, then | |
279 | 4 + 4 + 12 to struct sigcontext. */ | |
280 | return (sp + 156); | |
281 | } | |
282 | ||
8a3fe4f8 | 283 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 284 | return 0; |
29134980 OF |
285 | } |
286 | ||
2e4b5889 | 287 | struct cris_unwind_cache |
29134980 | 288 | { |
2e4b5889 OF |
289 | /* The previous frame's inner most stack address. Used as this |
290 | frame ID's stack_addr. */ | |
291 | CORE_ADDR prev_sp; | |
292 | /* The frame's base, optionally used by the high-level debug info. */ | |
293 | CORE_ADDR base; | |
294 | int size; | |
295 | /* How far the SP and r8 (FP) have been offset from the start of | |
296 | the stack frame (as defined by the previous frame's stack | |
297 | pointer). */ | |
298 | LONGEST sp_offset; | |
299 | LONGEST r8_offset; | |
300 | int uses_frame; | |
301 | ||
302 | /* From old frame_extra_info struct. */ | |
29134980 OF |
303 | CORE_ADDR return_pc; |
304 | int leaf_function; | |
2e4b5889 OF |
305 | |
306 | /* Table indicating the location of each and every register. */ | |
307 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
308 | }; |
309 | ||
a5f6c8f5 | 310 | static struct cris_unwind_cache * |
94afd7a6 | 311 | cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
a5f6c8f5 OF |
312 | void **this_cache) |
313 | { | |
94afd7a6 | 314 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7fbe2eba | 315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 316 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
a5f6c8f5 | 317 | struct cris_unwind_cache *info; |
a5f6c8f5 | 318 | CORE_ADDR addr; |
e362b510 | 319 | gdb_byte buf[4]; |
a5f6c8f5 OF |
320 | int i; |
321 | ||
322 | if ((*this_cache)) | |
323 | return (*this_cache); | |
324 | ||
325 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
326 | (*this_cache) = info; | |
94afd7a6 | 327 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
a5f6c8f5 OF |
328 | |
329 | /* Zero all fields. */ | |
330 | info->prev_sp = 0; | |
331 | info->base = 0; | |
332 | info->size = 0; | |
333 | info->sp_offset = 0; | |
334 | info->r8_offset = 0; | |
335 | info->uses_frame = 0; | |
336 | info->return_pc = 0; | |
337 | info->leaf_function = 0; | |
338 | ||
94afd7a6 | 339 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
e17a4113 | 340 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
a5f6c8f5 | 341 | |
94afd7a6 | 342 | addr = cris_sigcontext_addr (this_frame); |
a5f6c8f5 OF |
343 | |
344 | /* Layout of the sigcontext struct: | |
345 | struct sigcontext { | |
346 | struct pt_regs regs; | |
347 | unsigned long oldmask; | |
348 | unsigned long usp; | |
349 | }; */ | |
350 | ||
c600d464 OF |
351 | if (tdep->cris_version == 10) |
352 | { | |
353 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
354 | struct pt_regs. */ | |
355 | for (i = 0; i <= 13; i++) | |
356 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
357 | ||
358 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
359 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
360 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
361 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
362 | it though since that will mean that the backtrace will show a PC | |
363 | different from what is shown when stopped. */ | |
364 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
7fbe2eba | 365 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 366 | = info->saved_regs[IRP_REGNUM]; |
7fbe2eba | 367 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4); |
c600d464 OF |
368 | } |
369 | else | |
370 | { | |
371 | /* CRISv32. */ | |
372 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
373 | struct pt_regs. */ | |
374 | for (i = 0; i <= 13; i++) | |
375 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
376 | ||
377 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
378 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
379 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
380 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
381 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
382 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
383 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
384 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
385 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
386 | ||
387 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
388 | be wrong at this point. This problem manifests itself in the | |
389 | sigaltstack.exp test case, which occasionally generates FAILs when | |
0963b4bd | 390 | the signal is received while in a delay slot. |
c600d464 OF |
391 | |
392 | This could be solved by a couple of read_memory_unsigned_integer and a | |
393 | trad_frame_set_value. */ | |
7fbe2eba | 394 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 395 | = info->saved_regs[ERP_REGNUM]; |
c600d464 | 396 | |
7fbe2eba | 397 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr |
3e8c568d | 398 | = addr + (25 * 4); |
c600d464 | 399 | } |
a5f6c8f5 OF |
400 | |
401 | return info; | |
402 | } | |
403 | ||
404 | static void | |
94afd7a6 | 405 | cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
a5f6c8f5 OF |
406 | struct frame_id *this_id) |
407 | { | |
408 | struct cris_unwind_cache *cache = | |
94afd7a6 UW |
409 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
410 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); | |
a5f6c8f5 OF |
411 | } |
412 | ||
413 | /* Forward declaration. */ | |
414 | ||
94afd7a6 UW |
415 | static struct value *cris_frame_prev_register (struct frame_info *this_frame, |
416 | void **this_cache, int regnum); | |
417 | static struct value * | |
418 | cris_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
419 | void **this_cache, int regnum) | |
a5f6c8f5 OF |
420 | { |
421 | /* Make sure we've initialized the cache. */ | |
94afd7a6 UW |
422 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
423 | return cris_frame_prev_register (this_frame, this_cache, regnum); | |
424 | } | |
425 | ||
426 | static int | |
427 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
428 | struct frame_info *this_frame, | |
429 | void **this_cache) | |
430 | { | |
431 | if (cris_sigtramp_start (this_frame) | |
432 | || cris_rt_sigtramp_start (this_frame)) | |
433 | return 1; | |
434 | ||
435 | return 0; | |
a5f6c8f5 OF |
436 | } |
437 | ||
438 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
439 | { | |
440 | SIGTRAMP_FRAME, | |
8fbca658 | 441 | default_frame_unwind_stop_reason, |
a5f6c8f5 | 442 | cris_sigtramp_frame_this_id, |
94afd7a6 UW |
443 | cris_sigtramp_frame_prev_register, |
444 | NULL, | |
445 | cris_sigtramp_frame_sniffer | |
a5f6c8f5 OF |
446 | }; |
447 | ||
63807e1d | 448 | static int |
c600d464 OF |
449 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
450 | struct frame_info *this_frame) | |
451 | { | |
7fbe2eba | 452 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c600d464 OF |
453 | ULONGEST erp; |
454 | int ret = 0; | |
c600d464 | 455 | |
35488783 | 456 | if (tdep->cris_mode == cris_mode_guru) |
395f2fc2 | 457 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
0e6bdb31 | 458 | else |
395f2fc2 | 459 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
c600d464 OF |
460 | |
461 | if (erp & 0x1) | |
462 | { | |
463 | /* In delay slot - check if there's a breakpoint at the preceding | |
464 | instruction. */ | |
6c95b8df | 465 | if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1)) |
c600d464 OF |
466 | ret = 1; |
467 | } | |
468 | return ret; | |
469 | } | |
470 | ||
29134980 | 471 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 472 | |
29134980 OF |
473 | typedef |
474 | struct instruction_environment | |
475 | { | |
476 | unsigned long reg[NUM_GENREGS]; | |
477 | unsigned long preg[NUM_SPECREGS]; | |
478 | unsigned long branch_break_address; | |
479 | unsigned long delay_slot_pc; | |
480 | unsigned long prefix_value; | |
481 | int branch_found; | |
482 | int prefix_found; | |
483 | int invalid; | |
484 | int slot_needed; | |
485 | int delay_slot_pc_active; | |
486 | int xflag_found; | |
487 | int disable_interrupt; | |
e17a4113 | 488 | int byte_order; |
29134980 OF |
489 | } inst_env_type; |
490 | ||
29134980 OF |
491 | /* Machine-dependencies in CRIS for opcodes. */ |
492 | ||
493 | /* Instruction sizes. */ | |
494 | enum cris_instruction_sizes | |
495 | { | |
496 | INST_BYTE_SIZE = 0, | |
497 | INST_WORD_SIZE = 1, | |
498 | INST_DWORD_SIZE = 2 | |
499 | }; | |
500 | ||
501 | /* Addressing modes. */ | |
502 | enum cris_addressing_modes | |
503 | { | |
504 | REGISTER_MODE = 1, | |
505 | INDIRECT_MODE = 2, | |
506 | AUTOINC_MODE = 3 | |
507 | }; | |
508 | ||
509 | /* Prefix addressing modes. */ | |
510 | enum cris_prefix_addressing_modes | |
511 | { | |
512 | PREFIX_INDEX_MODE = 2, | |
513 | PREFIX_ASSIGN_MODE = 3, | |
514 | ||
515 | /* Handle immediate byte offset addressing mode prefix format. */ | |
516 | PREFIX_OFFSET_MODE = 2 | |
517 | }; | |
518 | ||
519 | /* Masks for opcodes. */ | |
520 | enum cris_opcode_masks | |
521 | { | |
522 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
523 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
524 | SIGNED_BYTE_MASK = 0x80, | |
525 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
526 | SIGNED_WORD_MASK = 0x8000, | |
527 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
528 | SIGNED_DWORD_MASK = 0x80000000, | |
529 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
530 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
531 | }; | |
532 | ||
533 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
534 | Bit 15 - 12 Operand2 | |
535 | 11 - 10 Mode | |
536 | 9 - 6 Opcode | |
537 | 5 - 4 Size | |
538 | 3 - 0 Operand1 */ | |
539 | ||
540 | static int | |
541 | cris_get_operand2 (unsigned short insn) | |
542 | { | |
543 | return ((insn & 0xF000) >> 12); | |
544 | } | |
545 | ||
546 | static int | |
547 | cris_get_mode (unsigned short insn) | |
548 | { | |
549 | return ((insn & 0x0C00) >> 10); | |
550 | } | |
551 | ||
552 | static int | |
553 | cris_get_opcode (unsigned short insn) | |
554 | { | |
555 | return ((insn & 0x03C0) >> 6); | |
556 | } | |
557 | ||
558 | static int | |
559 | cris_get_size (unsigned short insn) | |
560 | { | |
561 | return ((insn & 0x0030) >> 4); | |
562 | } | |
563 | ||
564 | static int | |
565 | cris_get_operand1 (unsigned short insn) | |
566 | { | |
567 | return (insn & 0x000F); | |
568 | } | |
569 | ||
570 | /* Additional functions in order to handle opcodes. */ | |
571 | ||
29134980 OF |
572 | static int |
573 | cris_get_quick_value (unsigned short insn) | |
574 | { | |
575 | return (insn & 0x003F); | |
576 | } | |
577 | ||
578 | static int | |
579 | cris_get_bdap_quick_offset (unsigned short insn) | |
580 | { | |
581 | return (insn & 0x00FF); | |
582 | } | |
583 | ||
584 | static int | |
585 | cris_get_branch_short_offset (unsigned short insn) | |
586 | { | |
587 | return (insn & 0x00FF); | |
588 | } | |
589 | ||
590 | static int | |
591 | cris_get_asr_shift_steps (unsigned long value) | |
592 | { | |
593 | return (value & 0x3F); | |
594 | } | |
595 | ||
29134980 OF |
596 | static int |
597 | cris_get_clear_size (unsigned short insn) | |
598 | { | |
599 | return ((insn) & 0xC000); | |
600 | } | |
601 | ||
602 | static int | |
603 | cris_is_signed_extend_bit_on (unsigned short insn) | |
604 | { | |
605 | return (((insn) & 0x20) == 0x20); | |
606 | } | |
607 | ||
608 | static int | |
609 | cris_is_xflag_bit_on (unsigned short insn) | |
610 | { | |
611 | return (((insn) & 0x1000) == 0x1000); | |
612 | } | |
613 | ||
614 | static void | |
615 | cris_set_size_to_dword (unsigned short *insn) | |
616 | { | |
617 | *insn &= 0xFFCF; | |
618 | *insn |= 0x20; | |
619 | } | |
620 | ||
8535cb38 | 621 | static signed char |
29134980 OF |
622 | cris_get_signed_offset (unsigned short insn) |
623 | { | |
8535cb38 | 624 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
625 | } |
626 | ||
627 | /* Calls an op function given the op-type, working on the insn and the | |
628 | inst_env. */ | |
be8626e0 MD |
629 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
630 | inst_env_type *); | |
29134980 | 631 | |
29134980 OF |
632 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
633 | struct gdbarch_list *); | |
634 | ||
29134980 OF |
635 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
636 | ||
a5f6c8f5 OF |
637 | static void set_cris_version (char *ignore_args, int from_tty, |
638 | struct cmd_list_element *c); | |
29134980 | 639 | |
0e6bdb31 OF |
640 | static void set_cris_mode (char *ignore_args, int from_tty, |
641 | struct cmd_list_element *c); | |
642 | ||
a5f6c8f5 OF |
643 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
644 | struct cmd_list_element *c); | |
29134980 | 645 | |
2e4b5889 | 646 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 647 | struct frame_info *this_frame, |
2e4b5889 OF |
648 | struct cris_unwind_cache *info); |
649 | ||
5114e29d | 650 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 651 | struct frame_info *this_frame, |
5114e29d OF |
652 | struct cris_unwind_cache *info); |
653 | ||
2e4b5889 OF |
654 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
655 | struct frame_info *next_frame); | |
656 | ||
657 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
658 | struct frame_info *next_frame); | |
659 | ||
660 | /* When arguments must be pushed onto the stack, they go on in reverse | |
0963b4bd | 661 | order. The below implements a FILO (stack) to do this. |
a5f6c8f5 | 662 | Copied from d10v-tdep.c. */ |
2e4b5889 OF |
663 | |
664 | struct stack_item | |
665 | { | |
666 | int len; | |
667 | struct stack_item *prev; | |
668 | void *data; | |
669 | }; | |
670 | ||
671 | static struct stack_item * | |
948f8e3d | 672 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2e4b5889 OF |
673 | { |
674 | struct stack_item *si; | |
675 | si = xmalloc (sizeof (struct stack_item)); | |
676 | si->data = xmalloc (len); | |
677 | si->len = len; | |
678 | si->prev = prev; | |
679 | memcpy (si->data, contents, len); | |
680 | return si; | |
681 | } | |
682 | ||
683 | static struct stack_item * | |
684 | pop_stack_item (struct stack_item *si) | |
685 | { | |
686 | struct stack_item *dead = si; | |
687 | si = si->prev; | |
688 | xfree (dead->data); | |
689 | xfree (dead); | |
690 | return si; | |
691 | } | |
692 | ||
693 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
694 | the saved registers of frame described by FRAME_INFO. This | |
695 | includes special registers such as pc and fp saved in special ways | |
696 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 697 | for it IS the sp for the next frame. */ |
2e4b5889 | 698 | |
63807e1d | 699 | static struct cris_unwind_cache * |
94afd7a6 | 700 | cris_frame_unwind_cache (struct frame_info *this_frame, |
2e4b5889 OF |
701 | void **this_prologue_cache) |
702 | { | |
35488783 UW |
703 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
704 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2e4b5889 | 705 | struct cris_unwind_cache *info; |
2e4b5889 OF |
706 | |
707 | if ((*this_prologue_cache)) | |
708 | return (*this_prologue_cache); | |
709 | ||
710 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
711 | (*this_prologue_cache) = info; | |
94afd7a6 | 712 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
2e4b5889 OF |
713 | |
714 | /* Zero all fields. */ | |
715 | info->prev_sp = 0; | |
716 | info->base = 0; | |
717 | info->size = 0; | |
718 | info->sp_offset = 0; | |
719 | info->r8_offset = 0; | |
720 | info->uses_frame = 0; | |
721 | info->return_pc = 0; | |
722 | info->leaf_function = 0; | |
723 | ||
724 | /* Prologue analysis does the rest... */ | |
35488783 | 725 | if (tdep->cris_version == 32) |
94afd7a6 | 726 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
5114e29d | 727 | else |
94afd7a6 | 728 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
2e4b5889 OF |
729 | |
730 | return info; | |
731 | } | |
732 | ||
733 | /* Given a GDB frame, determine the address of the calling function's | |
734 | frame. This will be used to create a new GDB frame struct. */ | |
735 | ||
736 | static void | |
94afd7a6 | 737 | cris_frame_this_id (struct frame_info *this_frame, |
2e4b5889 OF |
738 | void **this_prologue_cache, |
739 | struct frame_id *this_id) | |
740 | { | |
741 | struct cris_unwind_cache *info | |
94afd7a6 | 742 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
2e4b5889 OF |
743 | CORE_ADDR base; |
744 | CORE_ADDR func; | |
745 | struct frame_id id; | |
746 | ||
747 | /* The FUNC is easy. */ | |
94afd7a6 | 748 | func = get_frame_func (this_frame); |
2e4b5889 OF |
749 | |
750 | /* Hopefully the prologue analysis either correctly determined the | |
751 | frame's base (which is the SP from the previous frame), or set | |
752 | that base to "NULL". */ | |
753 | base = info->prev_sp; | |
754 | if (base == 0) | |
755 | return; | |
756 | ||
757 | id = frame_id_build (base, func); | |
758 | ||
759 | (*this_id) = id; | |
760 | } | |
761 | ||
94afd7a6 UW |
762 | static struct value * |
763 | cris_frame_prev_register (struct frame_info *this_frame, | |
764 | void **this_prologue_cache, int regnum) | |
2e4b5889 OF |
765 | { |
766 | struct cris_unwind_cache *info | |
94afd7a6 UW |
767 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
768 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2e4b5889 OF |
769 | } |
770 | ||
94afd7a6 UW |
771 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
772 | frame. The frame ID's base needs to match the TOS value saved by | |
773 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
2e4b5889 OF |
774 | |
775 | static struct frame_id | |
94afd7a6 | 776 | cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
2e4b5889 | 777 | { |
94afd7a6 UW |
778 | CORE_ADDR sp; |
779 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
780 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
2e4b5889 OF |
781 | } |
782 | ||
783 | static CORE_ADDR | |
784 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
785 | { | |
786 | /* Align to the size of an instruction (so that they can safely be | |
787 | pushed onto the stack). */ | |
788 | return sp & ~3; | |
789 | } | |
790 | ||
791 | static CORE_ADDR | |
792 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
82585c72 | 793 | CORE_ADDR sp, CORE_ADDR funaddr, |
2e4b5889 OF |
794 | struct value **args, int nargs, |
795 | struct type *value_type, | |
e4fd649a UW |
796 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
797 | struct regcache *regcache) | |
2e4b5889 OF |
798 | { |
799 | /* Allocate space sufficient for a breakpoint. */ | |
800 | sp = (sp - 4) & ~3; | |
801 | /* Store the address of that breakpoint */ | |
802 | *bp_addr = sp; | |
803 | /* CRIS always starts the call at the callee's entry point. */ | |
804 | *real_pc = funaddr; | |
805 | return sp; | |
806 | } | |
807 | ||
808 | static CORE_ADDR | |
7d9b040b | 809 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
810 | struct regcache *regcache, CORE_ADDR bp_addr, |
811 | int nargs, struct value **args, CORE_ADDR sp, | |
812 | int struct_return, CORE_ADDR struct_addr) | |
813 | { | |
e17a4113 | 814 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 OF |
815 | int stack_offset; |
816 | int argreg; | |
817 | int argnum; | |
818 | ||
2e4b5889 OF |
819 | /* The function's arguments and memory allocated by gdb for the arguments to |
820 | point at reside in separate areas on the stack. | |
821 | Both frame pointers grow toward higher addresses. */ | |
822 | CORE_ADDR fp_arg; | |
823 | CORE_ADDR fp_mem; | |
824 | ||
825 | struct stack_item *si = NULL; | |
826 | ||
a5f6c8f5 | 827 | /* Push the return address. */ |
2e4b5889 OF |
828 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
829 | ||
830 | /* Are we returning a value using a structure return or a normal value | |
831 | return? struct_addr is the address of the reserved space for the return | |
832 | structure to be written on the stack. */ | |
833 | if (struct_return) | |
834 | { | |
835 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
836 | } | |
837 | ||
838 | /* Now load as many as possible of the first arguments into registers, | |
839 | and push the rest onto the stack. */ | |
840 | argreg = ARG1_REGNUM; | |
841 | stack_offset = 0; | |
842 | ||
843 | for (argnum = 0; argnum < nargs; argnum++) | |
844 | { | |
845 | int len; | |
948f8e3d | 846 | const gdb_byte *val; |
2e4b5889 OF |
847 | int reg_demand; |
848 | int i; | |
849 | ||
4991999e | 850 | len = TYPE_LENGTH (value_type (args[argnum])); |
948f8e3d | 851 | val = value_contents (args[argnum]); |
2e4b5889 OF |
852 | |
853 | /* How may registers worth of storage do we need for this argument? */ | |
854 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
855 | ||
856 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
857 | { | |
858 | /* Data passed by value. Fits in available register(s). */ | |
859 | for (i = 0; i < reg_demand; i++) | |
860 | { | |
f6e56ab3 | 861 | regcache_cooked_write (regcache, argreg, val); |
2e4b5889 OF |
862 | argreg++; |
863 | val += 4; | |
864 | } | |
865 | } | |
866 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
867 | { | |
868 | /* Data passed by value. Does not fit in available register(s). | |
869 | Use the register(s) first, then the stack. */ | |
870 | for (i = 0; i < reg_demand; i++) | |
871 | { | |
872 | if (argreg <= ARG4_REGNUM) | |
873 | { | |
f6e56ab3 | 874 | regcache_cooked_write (regcache, argreg, val); |
2e4b5889 OF |
875 | argreg++; |
876 | val += 4; | |
877 | } | |
878 | else | |
879 | { | |
880 | /* Push item for later so that pushed arguments | |
881 | come in the right order. */ | |
882 | si = push_stack_item (si, val, 4); | |
883 | val += 4; | |
884 | } | |
885 | } | |
886 | } | |
887 | else if (len > (2 * 4)) | |
888 | { | |
f6e56ab3 UW |
889 | /* Data passed by reference. Push copy of data onto stack |
890 | and pass pointer to this copy as argument. */ | |
891 | sp = (sp - len) & ~3; | |
892 | write_memory (sp, val, len); | |
893 | ||
894 | if (argreg <= ARG4_REGNUM) | |
895 | { | |
896 | regcache_cooked_write_unsigned (regcache, argreg, sp); | |
897 | argreg++; | |
898 | } | |
899 | else | |
900 | { | |
901 | gdb_byte buf[4]; | |
e17a4113 | 902 | store_unsigned_integer (buf, 4, byte_order, sp); |
f6e56ab3 UW |
903 | si = push_stack_item (si, buf, 4); |
904 | } | |
2e4b5889 OF |
905 | } |
906 | else | |
907 | { | |
908 | /* Data passed by value. No available registers. Put it on | |
909 | the stack. */ | |
910 | si = push_stack_item (si, val, len); | |
911 | } | |
912 | } | |
913 | ||
914 | while (si) | |
915 | { | |
916 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
917 | the function prologue. */ | |
918 | sp = (sp - si->len) & ~3; | |
919 | write_memory (sp, si->data, si->len); | |
920 | si = pop_stack_item (si); | |
921 | } | |
922 | ||
923 | /* Finally, update the SP register. */ | |
7fbe2eba | 924 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
2e4b5889 OF |
925 | |
926 | return sp; | |
927 | } | |
928 | ||
e2a2a3e8 OF |
929 | static const struct frame_unwind cris_frame_unwind = |
930 | { | |
2e4b5889 | 931 | NORMAL_FRAME, |
8fbca658 | 932 | default_frame_unwind_stop_reason, |
2e4b5889 | 933 | cris_frame_this_id, |
94afd7a6 UW |
934 | cris_frame_prev_register, |
935 | NULL, | |
936 | default_frame_sniffer | |
2e4b5889 OF |
937 | }; |
938 | ||
2e4b5889 | 939 | static CORE_ADDR |
94afd7a6 | 940 | cris_frame_base_address (struct frame_info *this_frame, void **this_cache) |
2e4b5889 OF |
941 | { |
942 | struct cris_unwind_cache *info | |
94afd7a6 | 943 | = cris_frame_unwind_cache (this_frame, this_cache); |
2e4b5889 OF |
944 | return info->base; |
945 | } | |
946 | ||
e2a2a3e8 OF |
947 | static const struct frame_base cris_frame_base = |
948 | { | |
2e4b5889 OF |
949 | &cris_frame_unwind, |
950 | cris_frame_base_address, | |
951 | cris_frame_base_address, | |
952 | cris_frame_base_address | |
953 | }; | |
954 | ||
29134980 OF |
955 | /* Frames information. The definition of the struct frame_info is |
956 | ||
957 | CORE_ADDR frame | |
958 | CORE_ADDR pc | |
5a203e44 | 959 | enum frame_type type; |
29134980 OF |
960 | CORE_ADDR return_pc |
961 | int leaf_function | |
962 | ||
963 | If the compilation option -fno-omit-frame-pointer is present the | |
964 | variable frame will be set to the content of R8 which is the frame | |
965 | pointer register. | |
966 | ||
967 | The variable pc contains the address where execution is performed | |
968 | in the present frame. The innermost frame contains the current content | |
969 | of the register PC. All other frames contain the content of the | |
970 | register PC in the next frame. | |
971 | ||
5a203e44 AC |
972 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
973 | (associated with a signal handler), dummy (associated with a dummy | |
974 | frame). | |
29134980 OF |
975 | |
976 | The variable return_pc contains the address where execution should be | |
977 | resumed when the present frame has finished, the return address. | |
978 | ||
979 | The variable leaf_function is 1 if the return address is in the register | |
980 | SRP, and 0 if it is on the stack. | |
981 | ||
982 | Prologue instructions C-code. | |
983 | The prologue may consist of (-fno-omit-frame-pointer) | |
984 | 1) 2) | |
985 | push srp | |
986 | push r8 push r8 | |
987 | move.d sp,r8 move.d sp,r8 | |
988 | subq X,sp subq X,sp | |
989 | movem rY,[sp] movem rY,[sp] | |
990 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
991 | ||
992 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
993 | ||
994 | Note that this assumption is extremely brittle, and will break at the | |
995 | slightest change in GCC's prologue. | |
996 | ||
997 | If local variables are declared or register contents are saved on stack | |
998 | the subq-instruction will be present with X as the number of bytes | |
999 | needed for storage. The reshuffle with respect to r8 may be performed | |
1000 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
0963b4bd | 1001 | The offset U should be representable by a signed 8-bit value in all cases. |
29134980 OF |
1002 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
1003 | by another word containing the instruction. | |
1004 | ||
1005 | Degenerate cases: | |
1006 | 3) | |
1007 | push r8 | |
1008 | move.d sp,r8 | |
1009 | move.d r8,sp | |
1010 | pop r8 | |
1011 | ||
1012 | Prologue instructions C++-code. | |
1013 | Case 1) and 2) in the C-code may be followed by | |
1014 | ||
1015 | move.d r10,rS ; this | |
1016 | move.d r11,rT ; P1 | |
1017 | move.d r12,rU ; P2 | |
1018 | move.d r13,rV ; P3 | |
1019 | move.S [r8+U],rZ ; P4 | |
1020 | ||
0963b4bd | 1021 | if any of the call parameters are stored. The host expects these |
29134980 OF |
1022 | instructions to be executed in order to get the call parameters right. */ |
1023 | ||
1024 | /* Examine the prologue of a function. The variable ip is the address of | |
1025 | the first instruction of the prologue. The variable limit is the address | |
1026 | of the first instruction after the prologue. The variable fi contains the | |
1027 | information in struct frame_info. The variable frameless_p controls whether | |
1028 | the entire prologue is examined (0) or just enough instructions to | |
1029 | determine that it is a prologue (1). */ | |
1030 | ||
a78f21af | 1031 | static CORE_ADDR |
94afd7a6 | 1032 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
2e4b5889 | 1033 | struct cris_unwind_cache *info) |
29134980 | 1034 | { |
94afd7a6 | 1035 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
1036 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1037 | ||
29134980 OF |
1038 | /* Present instruction. */ |
1039 | unsigned short insn; | |
1040 | ||
1041 | /* Next instruction, lookahead. */ | |
1042 | unsigned short insn_next; | |
1043 | int regno; | |
1044 | ||
1045 | /* Is there a push fp? */ | |
1046 | int have_fp; | |
1047 | ||
1048 | /* Number of byte on stack used for local variables and movem. */ | |
1049 | int val; | |
1050 | ||
1051 | /* Highest register number in a movem. */ | |
1052 | int regsave; | |
1053 | ||
1054 | /* move.d r<source_register>,rS */ | |
1055 | short source_register; | |
1056 | ||
2e4b5889 OF |
1057 | /* Scan limit. */ |
1058 | int limit; | |
29134980 | 1059 | |
2e4b5889 OF |
1060 | /* This frame is with respect to a leaf until a push srp is found. */ |
1061 | if (info) | |
1062 | { | |
1063 | info->leaf_function = 1; | |
1064 | } | |
29134980 OF |
1065 | |
1066 | /* Assume nothing on stack. */ | |
1067 | val = 0; | |
1068 | regsave = -1; | |
1069 | ||
94afd7a6 | 1070 | /* If we were called without a this_frame, that means we were called |
2e4b5889 OF |
1071 | from cris_skip_prologue which already tried to find the end of the |
1072 | prologue through the symbol information. 64 instructions past current | |
1073 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
94afd7a6 | 1074 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
29134980 | 1075 | |
29134980 | 1076 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1077 | while (pc > 0 && pc < limit) |
29134980 | 1078 | { |
e17a4113 | 1079 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1080 | pc += 2; |
29134980 OF |
1081 | if (insn == 0xE1FC) |
1082 | { | |
0963b4bd | 1083 | /* push <reg> 32 bit instruction. */ |
e17a4113 | 1084 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1085 | pc += 2; |
29134980 | 1086 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1087 | if (info) |
1088 | { | |
1089 | info->sp_offset += 4; | |
1090 | } | |
dbbff683 OF |
1091 | /* This check, meant to recognize srp, used to be regno == |
1092 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1093 | if (insn_next == 0xBE7E) | |
29134980 | 1094 | { |
2e4b5889 OF |
1095 | if (info) |
1096 | { | |
1097 | info->leaf_function = 0; | |
1098 | } | |
29134980 | 1099 | } |
b4206d25 OF |
1100 | else if (insn_next == 0x8FEE) |
1101 | { | |
1102 | /* push $r8 */ | |
1103 | if (info) | |
1104 | { | |
1105 | info->r8_offset = info->sp_offset; | |
1106 | } | |
1107 | } | |
29134980 OF |
1108 | } |
1109 | else if (insn == 0x866E) | |
1110 | { | |
1111 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1112 | if (info) |
1113 | { | |
1114 | info->uses_frame = 1; | |
2e4b5889 | 1115 | } |
29134980 OF |
1116 | continue; |
1117 | } | |
7fbe2eba | 1118 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1119 | && cris_get_mode (insn) == 0x0000 |
1120 | && cris_get_opcode (insn) == 0x000A) | |
1121 | { | |
1122 | /* subq <val>,sp */ | |
2e4b5889 OF |
1123 | if (info) |
1124 | { | |
1125 | info->sp_offset += cris_get_quick_value (insn); | |
1126 | } | |
29134980 OF |
1127 | } |
1128 | else if (cris_get_mode (insn) == 0x0002 | |
1129 | && cris_get_opcode (insn) == 0x000F | |
1130 | && cris_get_size (insn) == 0x0003 | |
7fbe2eba | 1131 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1132 | { |
1133 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1134 | regsave = cris_get_operand2 (insn); |
1135 | } | |
7fbe2eba | 1136 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1137 | && ((insn & 0x0F00) >> 8) == 0x0001 |
1138 | && (cris_get_signed_offset (insn) < 0)) | |
1139 | { | |
1140 | /* Immediate byte offset addressing prefix word with sp as base | |
1141 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1142 | is between 64 and 128. | |
1143 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1144 | if (info) |
1145 | { | |
1146 | info->sp_offset += -cris_get_signed_offset (insn); | |
1147 | } | |
e17a4113 | 1148 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1149 | pc += 2; |
29134980 OF |
1150 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1151 | && cris_get_opcode (insn_next) == 0x000F | |
1152 | && cris_get_size (insn_next) == 0x0003 | |
3e8c568d | 1153 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
7fbe2eba | 1154 | (gdbarch)) |
29134980 | 1155 | { |
29134980 OF |
1156 | regsave = cris_get_operand2 (insn_next); |
1157 | } | |
1158 | else | |
1159 | { | |
1160 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1161 | pc -= 4; |
29134980 OF |
1162 | break; |
1163 | } | |
1164 | } | |
1165 | else if (cris_get_mode (insn) == 0x0001 | |
1166 | && cris_get_opcode (insn) == 0x0009 | |
1167 | && cris_get_size (insn) == 0x0002) | |
1168 | { | |
1169 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1170 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1171 | |
1172 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1173 | like (this example taken from relocate_doit): | |
1174 | move.d $pc,$r0 | |
1175 | sub.d 0xfffef426,$r0 | |
1176 | which isn't covered by the source_register check below. Question | |
1177 | is whether to add a check for this combo, or make better use of | |
1178 | the limit variable instead. */ | |
29134980 OF |
1179 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1180 | { | |
1181 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1182 | pc -= 2; |
29134980 OF |
1183 | break; |
1184 | } | |
1185 | } | |
2e4b5889 | 1186 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1187 | /* The size is a fixed-size. */ |
1188 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1189 | /* A negative offset. */ | |
1190 | && (cris_get_signed_offset (insn) < 0)) | |
1191 | { | |
1192 | /* move.S rZ,[r8-U] (?) */ | |
e17a4113 | 1193 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1194 | pc += 2; |
29134980 | 1195 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1196 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1197 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1198 | && cris_get_opcode (insn_next) == 0x000F) | |
1199 | { | |
1200 | /* move.S rZ,[r8-U] */ | |
1201 | continue; | |
1202 | } | |
1203 | else | |
1204 | { | |
1205 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1206 | pc -= 4; |
29134980 OF |
1207 | break; |
1208 | } | |
1209 | } | |
2e4b5889 | 1210 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1211 | /* The size is a fixed-size. */ |
1212 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1213 | /* A positive offset. */ | |
1214 | && (cris_get_signed_offset (insn) > 0)) | |
1215 | { | |
1216 | /* move.S [r8+U],rZ (?) */ | |
e17a4113 | 1217 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1218 | pc += 2; |
29134980 | 1219 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1220 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1221 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1222 | && cris_get_opcode (insn_next) == 0x0009 | |
1223 | && cris_get_operand1 (insn_next) == regno) | |
1224 | { | |
1225 | /* move.S [r8+U],rZ */ | |
1226 | continue; | |
1227 | } | |
1228 | else | |
1229 | { | |
1230 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1231 | pc -= 4; |
29134980 OF |
1232 | break; |
1233 | } | |
1234 | } | |
1235 | else | |
1236 | { | |
1237 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1238 | pc -= 2; |
29134980 OF |
1239 | break; |
1240 | } | |
1241 | } | |
29134980 | 1242 | |
94afd7a6 | 1243 | /* We only want to know the end of the prologue when this_frame and info |
2e4b5889 | 1244 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1245 | if (this_frame == NULL && info == NULL) |
2e4b5889 OF |
1246 | { |
1247 | return pc; | |
1248 | } | |
29134980 | 1249 | |
2e4b5889 OF |
1250 | info->size = info->sp_offset; |
1251 | ||
1252 | /* Compute the previous frame's stack pointer (which is also the | |
1253 | frame's ID's stack address), and this frame's base pointer. */ | |
1254 | if (info->uses_frame) | |
29134980 | 1255 | { |
2e4b5889 OF |
1256 | ULONGEST this_base; |
1257 | /* The SP was moved to the FP. This indicates that a new frame | |
1258 | was created. Get THIS frame's FP value by unwinding it from | |
1259 | the next frame. */ | |
94afd7a6 | 1260 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
2e4b5889 | 1261 | info->base = this_base; |
b4206d25 OF |
1262 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1263 | ||
2e4b5889 OF |
1264 | /* The FP points at the last saved register. Adjust the FP back |
1265 | to before the first saved register giving the SP. */ | |
1266 | info->prev_sp = info->base + info->r8_offset; | |
1267 | } | |
1268 | else | |
1269 | { | |
1270 | ULONGEST this_base; | |
1271 | /* Assume that the FP is this frame's SP but with that pushed | |
1272 | stack space added back. */ | |
94afd7a6 UW |
1273 | this_base = get_frame_register_unsigned (this_frame, |
1274 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1275 | info->base = this_base; |
1276 | info->prev_sp = info->base + info->size; | |
1277 | } | |
29134980 | 1278 | |
2e4b5889 OF |
1279 | /* Calculate the addresses for the saved registers on the stack. */ |
1280 | /* FIXME: The address calculation should really be done on the fly while | |
1281 | we're analyzing the prologue (we only hold one regsave value as it is | |
1282 | now). */ | |
1283 | val = info->sp_offset; | |
1284 | ||
1285 | for (regno = regsave; regno >= 0; regno--) | |
1286 | { | |
1287 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1288 | val -= 4; | |
1289 | } | |
1290 | ||
1291 | /* The previous frame's SP needed to be computed. Save the computed | |
1292 | value. */ | |
3e8c568d | 1293 | trad_frame_set_value (info->saved_regs, |
7fbe2eba | 1294 | gdbarch_sp_regnum (gdbarch), info->prev_sp); |
2e4b5889 OF |
1295 | |
1296 | if (!info->leaf_function) | |
1297 | { | |
b4206d25 OF |
1298 | /* SRP saved on the stack. But where? */ |
1299 | if (info->r8_offset == 0) | |
1300 | { | |
1301 | /* R8 not pushed yet. */ | |
1302 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1303 | } | |
1304 | else | |
1305 | { | |
1306 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1307 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1308 | } | |
29134980 | 1309 | } |
2e4b5889 OF |
1310 | |
1311 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
7fbe2eba | 1312 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1313 | = info->saved_regs[SRP_REGNUM]; |
2e4b5889 OF |
1314 | |
1315 | return pc; | |
29134980 OF |
1316 | } |
1317 | ||
5114e29d | 1318 | static CORE_ADDR |
94afd7a6 | 1319 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
5114e29d OF |
1320 | struct cris_unwind_cache *info) |
1321 | { | |
94afd7a6 | 1322 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5114e29d OF |
1323 | ULONGEST this_base; |
1324 | ||
1325 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1326 | meant to be a full-fledged prologue scanner. It is only needed for | |
1327 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1328 | ||
1329 | * PLT stubs (library calls) | |
1330 | * call dummys | |
1331 | * signal trampolines | |
1332 | ||
1333 | For those cases, it is assumed that there is no actual prologue; that | |
1334 | the stack pointer is not adjusted, and (as a consequence) the return | |
1335 | address is not pushed onto the stack. */ | |
1336 | ||
94afd7a6 | 1337 | /* We only want to know the end of the prologue when this_frame and info |
5114e29d | 1338 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1339 | if (this_frame == NULL && info == NULL) |
5114e29d OF |
1340 | { |
1341 | return pc; | |
1342 | } | |
1343 | ||
1344 | /* The SP is assumed to be unaltered. */ | |
94afd7a6 UW |
1345 | this_base = get_frame_register_unsigned (this_frame, |
1346 | gdbarch_sp_regnum (gdbarch)); | |
5114e29d OF |
1347 | info->base = this_base; |
1348 | info->prev_sp = this_base; | |
1349 | ||
1350 | /* The PC is assumed to be found in SRP. */ | |
7fbe2eba | 1351 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1352 | = info->saved_regs[SRP_REGNUM]; |
5114e29d OF |
1353 | |
1354 | return pc; | |
1355 | } | |
1356 | ||
29134980 OF |
1357 | /* Advance pc beyond any function entry prologue instructions at pc |
1358 | to reach some "real" code. */ | |
1359 | ||
29134980 OF |
1360 | /* Given a PC value corresponding to the start of a function, return the PC |
1361 | of the first instruction after the function prologue. */ | |
1362 | ||
a78f21af | 1363 | static CORE_ADDR |
6093d2eb | 1364 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
29134980 | 1365 | { |
35488783 | 1366 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2e4b5889 OF |
1367 | CORE_ADDR func_addr, func_end; |
1368 | struct symtab_and_line sal; | |
29134980 OF |
1369 | CORE_ADDR pc_after_prologue; |
1370 | ||
2e4b5889 OF |
1371 | /* If we have line debugging information, then the end of the prologue |
1372 | should the first assembly instruction of the first source line. */ | |
1373 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1374 | { | |
1375 | sal = find_pc_line (func_addr, 0); | |
1376 | if (sal.end > 0 && sal.end < func_end) | |
1377 | return sal.end; | |
1378 | } | |
29134980 | 1379 | |
35488783 | 1380 | if (tdep->cris_version == 32) |
5114e29d OF |
1381 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
1382 | else | |
1383 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1384 | ||
29134980 OF |
1385 | return pc_after_prologue; |
1386 | } | |
1387 | ||
2e4b5889 OF |
1388 | static CORE_ADDR |
1389 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1390 | { | |
1391 | ULONGEST pc; | |
11411de3 DJ |
1392 | pc = frame_unwind_register_unsigned (next_frame, |
1393 | gdbarch_pc_regnum (gdbarch)); | |
2e4b5889 OF |
1394 | return pc; |
1395 | } | |
1396 | ||
1397 | static CORE_ADDR | |
1398 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1399 | { | |
1400 | ULONGEST sp; | |
11411de3 DJ |
1401 | sp = frame_unwind_register_unsigned (next_frame, |
1402 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1403 | return sp; |
1404 | } | |
1405 | ||
29134980 OF |
1406 | /* Use the program counter to determine the contents and size of a breakpoint |
1407 | instruction. It returns a pointer to a string of bytes that encode a | |
1408 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1409 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1410 | the breakpoint should be inserted. */ | |
1411 | ||
a78f21af | 1412 | static const unsigned char * |
0963b4bd MS |
1413 | cris_breakpoint_from_pc (struct gdbarch *gdbarch, |
1414 | CORE_ADDR *pcptr, int *lenptr) | |
29134980 | 1415 | { |
35488783 | 1416 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
0e6bdb31 OF |
1417 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1418 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1419 | *lenptr = 2; |
1420 | ||
35488783 | 1421 | if (tdep->cris_mode == cris_mode_guru) |
0e6bdb31 OF |
1422 | return break15_insn; |
1423 | else | |
1424 | return break8_insn; | |
29134980 OF |
1425 | } |
1426 | ||
29134980 OF |
1427 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1428 | 0 otherwise. */ | |
1429 | ||
a78f21af | 1430 | static int |
35488783 UW |
1431 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
1432 | struct cris_spec_reg spec_reg) | |
29134980 | 1433 | { |
35488783 | 1434 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e4286e57 | 1435 | unsigned int version = tdep->cris_version; |
29134980 OF |
1436 | |
1437 | switch (spec_reg.applicable_version) | |
1438 | { | |
1439 | case cris_ver_version_all: | |
1440 | return 1; | |
1441 | case cris_ver_warning: | |
1442 | /* Indeterminate/obsolete. */ | |
1443 | return 0; | |
29134980 OF |
1444 | case cris_ver_v0_3: |
1445 | return (version >= 0 && version <= 3); | |
1446 | case cris_ver_v3p: | |
1447 | return (version >= 3); | |
1448 | case cris_ver_v8: | |
1449 | return (version == 8 || version == 9); | |
1450 | case cris_ver_v8p: | |
1451 | return (version >= 8); | |
c600d464 OF |
1452 | case cris_ver_v0_10: |
1453 | return (version >= 0 && version <= 10); | |
1454 | case cris_ver_v3_10: | |
1455 | return (version >= 3 && version <= 10); | |
1456 | case cris_ver_v8_10: | |
1457 | return (version >= 8 && version <= 10); | |
1458 | case cris_ver_v10: | |
1459 | return (version == 10); | |
29134980 OF |
1460 | case cris_ver_v10p: |
1461 | return (version >= 10); | |
c600d464 OF |
1462 | case cris_ver_v32p: |
1463 | return (version >= 32); | |
29134980 OF |
1464 | default: |
1465 | /* Invalid cris version. */ | |
1466 | return 0; | |
1467 | } | |
1468 | } | |
1469 | ||
1d94326f AC |
1470 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1471 | register, -1 for an invalid register. */ | |
1472 | ||
1473 | static int | |
be8626e0 | 1474 | cris_register_size (struct gdbarch *gdbarch, int regno) |
1d94326f | 1475 | { |
be8626e0 | 1476 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1d94326f AC |
1477 | int i; |
1478 | int spec_regno; | |
1479 | ||
1480 | if (regno >= 0 && regno < NUM_GENREGS) | |
1481 | { | |
1482 | /* General registers (R0 - R15) are 32 bits. */ | |
1483 | return 4; | |
1484 | } | |
c600d464 | 1485 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1486 | { |
1487 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1488 | Adjust regno accordingly. */ | |
1489 | spec_regno = regno - NUM_GENREGS; | |
1490 | ||
c600d464 | 1491 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1492 | { |
1493 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1494 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
1d94326f AC |
1495 | /* Go with the first applicable register. */ |
1496 | return cris_spec_regs[i].reg_size; | |
1497 | } | |
1498 | /* Special register not applicable to this CRIS version. */ | |
1499 | return 0; | |
1500 | } | |
be8626e0 MD |
1501 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
1502 | && regno < gdbarch_num_regs (gdbarch)) | |
1d94326f | 1503 | { |
c600d464 OF |
1504 | /* This will apply to CRISv32 only where there are additional registers |
1505 | after the special registers (pseudo PC and support registers). */ | |
1506 | return 4; | |
1d94326f | 1507 | } |
c600d464 OF |
1508 | |
1509 | ||
1510 | return -1; | |
1d94326f AC |
1511 | } |
1512 | ||
29134980 OF |
1513 | /* Nonzero if regno should not be fetched from the target. This is the case |
1514 | for unimplemented (size 0) and non-existant registers. */ | |
1515 | ||
a78f21af | 1516 | static int |
64a3914f | 1517 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
29134980 | 1518 | { |
64a3914f | 1519 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1520 | || (cris_register_size (gdbarch, regno) == 0)); |
29134980 OF |
1521 | } |
1522 | ||
1523 | /* Nonzero if regno should not be written to the target, for various | |
1524 | reasons. */ | |
1525 | ||
a78f21af | 1526 | static int |
64a3914f | 1527 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
29134980 OF |
1528 | { |
1529 | /* There are three kinds of registers we refuse to write to. | |
1530 | 1. Those that not implemented. | |
1531 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1532 | 3. Those registers to which a write has no effect. */ |
29134980 | 1533 | |
f57d151a | 1534 | if (regno < 0 |
64a3914f | 1535 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1536 | || cris_register_size (gdbarch, regno) == 0) |
29134980 OF |
1537 | /* Not implemented. */ |
1538 | return 1; | |
1539 | ||
1540 | else if (regno == VR_REGNUM) | |
1541 | /* Read-only. */ | |
1542 | return 1; | |
1543 | ||
1544 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1545 | /* Writing has no effect. */ | |
1546 | return 1; | |
1547 | ||
a5f6c8f5 OF |
1548 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1549 | agent decide whether they are writable. */ | |
29134980 OF |
1550 | |
1551 | return 0; | |
1552 | } | |
1553 | ||
c600d464 OF |
1554 | /* Nonzero if regno should not be fetched from the target. This is the case |
1555 | for unimplemented (size 0) and non-existant registers. */ | |
1556 | ||
1557 | static int | |
64a3914f | 1558 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
c600d464 | 1559 | { |
64a3914f | 1560 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1561 | || (cris_register_size (gdbarch, regno) == 0)); |
c600d464 OF |
1562 | } |
1563 | ||
1564 | /* Nonzero if regno should not be written to the target, for various | |
1565 | reasons. */ | |
1566 | ||
1567 | static int | |
64a3914f | 1568 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1569 | { |
1570 | /* There are three kinds of registers we refuse to write to. | |
1571 | 1. Those that not implemented. | |
1572 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1573 | 3. Those registers to which a write has no effect. */ |
c600d464 | 1574 | |
f57d151a | 1575 | if (regno < 0 |
64a3914f | 1576 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1577 | || cris_register_size (gdbarch, regno) == 0) |
c600d464 OF |
1578 | /* Not implemented. */ |
1579 | return 1; | |
1580 | ||
1581 | else if (regno == VR_REGNUM) | |
1582 | /* Read-only. */ | |
1583 | return 1; | |
1584 | ||
1585 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1586 | /* Writing has no effect. */ | |
1587 | return 1; | |
1588 | ||
1589 | /* Many special registers are read-only in user mode. Let the debug | |
1590 | agent decide whether they are writable. */ | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
29134980 OF |
1595 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1596 | of data in register regno. */ | |
1597 | ||
a78f21af | 1598 | static struct type * |
c1d546cd | 1599 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1600 | { |
7fbe2eba | 1601 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1602 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1603 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1604 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1605 | return builtin_type (gdbarch)->builtin_data_ptr; |
7fbe2eba | 1606 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 OF |
1607 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
1608 | /* Note: R8 taken care of previous clause. */ | |
df4df182 | 1609 | return builtin_type (gdbarch)->builtin_uint32; |
a5f6c8f5 | 1610 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
df4df182 | 1611 | return builtin_type (gdbarch)->builtin_uint16; |
a5f6c8f5 | 1612 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
df4df182 | 1613 | return builtin_type (gdbarch)->builtin_uint8; |
29134980 | 1614 | else |
a5f6c8f5 | 1615 | /* Invalid (unimplemented) register. */ |
df4df182 | 1616 | return builtin_type (gdbarch)->builtin_int0; |
29134980 OF |
1617 | } |
1618 | ||
c600d464 OF |
1619 | static struct type * |
1620 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1621 | { | |
7fbe2eba | 1622 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1623 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1624 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1625 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1626 | return builtin_type (gdbarch)->builtin_data_ptr; |
c600d464 OF |
1627 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
1628 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1629 | || (regno == PID_REGNUM) | |
1630 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1631 | /* Note: R8 and SP taken care of by previous clause. */ | |
df4df182 | 1632 | return builtin_type (gdbarch)->builtin_uint32; |
c600d464 | 1633 | else if (regno == WZ_REGNUM) |
df4df182 | 1634 | return builtin_type (gdbarch)->builtin_uint16; |
c600d464 | 1635 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
df4df182 | 1636 | return builtin_type (gdbarch)->builtin_uint8; |
c600d464 OF |
1637 | else |
1638 | { | |
1639 | /* Invalid (unimplemented) register. Should not happen as there are | |
1640 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1641 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
df4df182 | 1642 | return builtin_type (gdbarch)->builtin_int0; |
c600d464 OF |
1643 | } |
1644 | } | |
1645 | ||
2e4b5889 OF |
1646 | /* Stores a function return value of type type, where valbuf is the address |
1647 | of the value to be stored. */ | |
29134980 | 1648 | |
2e4b5889 | 1649 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1650 | |
2e4b5889 OF |
1651 | static void |
1652 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1653 | const gdb_byte *valbuf) |
29134980 | 1654 | { |
e17a4113 UW |
1655 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1656 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2e4b5889 | 1657 | ULONGEST val; |
bad43aa5 | 1658 | int len = TYPE_LENGTH (type); |
29134980 | 1659 | |
bad43aa5 | 1660 | if (len <= 4) |
29134980 | 1661 | { |
2e4b5889 | 1662 | /* Put the return value in R10. */ |
bad43aa5 | 1663 | val = extract_unsigned_integer (valbuf, len, byte_order); |
2e4b5889 | 1664 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
29134980 | 1665 | } |
bad43aa5 | 1666 | else if (len <= 8) |
29134980 | 1667 | { |
2e4b5889 | 1668 | /* Put the return value in R10 and R11. */ |
e17a4113 | 1669 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
2e4b5889 | 1670 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
948f8e3d | 1671 | val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
2e4b5889 | 1672 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
29134980 | 1673 | } |
2e4b5889 | 1674 | else |
8a3fe4f8 | 1675 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1676 | } |
1677 | ||
0963b4bd MS |
1678 | /* Return the name of register regno as a string. Return NULL for an |
1679 | invalid or unimplemented register. */ | |
29134980 | 1680 | |
c600d464 | 1681 | static const char * |
35488783 | 1682 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1683 | { |
1684 | int spec_regno; | |
1685 | int i; | |
1686 | ||
1687 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1688 | Adjust regno accordingly. */ | |
1689 | spec_regno = regno - NUM_GENREGS; | |
1690 | ||
1691 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1692 | when searching. */ | |
1693 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1694 | { | |
1695 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1696 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
c600d464 OF |
1697 | /* Go with the first applicable register. */ |
1698 | return cris_spec_regs[i].name; | |
1699 | } | |
1700 | /* Special register not applicable to this CRIS version. */ | |
1701 | return NULL; | |
1702 | } | |
1703 | ||
2e4b5889 | 1704 | static const char * |
d93859e2 | 1705 | cris_register_name (struct gdbarch *gdbarch, int regno) |
2e4b5889 OF |
1706 | { |
1707 | static char *cris_genreg_names[] = | |
1708 | { "r0", "r1", "r2", "r3", \ | |
1709 | "r4", "r5", "r6", "r7", \ | |
1710 | "r8", "r9", "r10", "r11", \ | |
1711 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1712 | |
2e4b5889 | 1713 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1714 | { |
2e4b5889 OF |
1715 | /* General register. */ |
1716 | return cris_genreg_names[regno]; | |
29134980 | 1717 | } |
d93859e2 | 1718 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
29134980 | 1719 | { |
35488783 | 1720 | return cris_special_register_name (gdbarch, regno); |
c600d464 OF |
1721 | } |
1722 | else | |
1723 | { | |
1724 | /* Invalid register. */ | |
2e4b5889 OF |
1725 | return NULL; |
1726 | } | |
c600d464 OF |
1727 | } |
1728 | ||
1729 | static const char * | |
d93859e2 | 1730 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1731 | { |
1732 | static char *crisv32_genreg_names[] = | |
1733 | { "r0", "r1", "r2", "r3", \ | |
1734 | "r4", "r5", "r6", "r7", \ | |
1735 | "r8", "r9", "r10", "r11", \ | |
1736 | "r12", "r13", "sp", "acr" | |
1737 | }; | |
1738 | ||
1739 | static char *crisv32_sreg_names[] = | |
1740 | { "s0", "s1", "s2", "s3", \ | |
1741 | "s4", "s5", "s6", "s7", \ | |
1742 | "s8", "s9", "s10", "s11", \ | |
1743 | "s12", "s13", "s14", "s15" | |
1744 | }; | |
1745 | ||
1746 | if (regno >= 0 && regno < NUM_GENREGS) | |
1747 | { | |
1748 | /* General register. */ | |
1749 | return crisv32_genreg_names[regno]; | |
1750 | } | |
1751 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1752 | { | |
35488783 | 1753 | return cris_special_register_name (gdbarch, regno); |
c600d464 | 1754 | } |
d93859e2 | 1755 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
c600d464 OF |
1756 | { |
1757 | return "pc"; | |
1758 | } | |
1759 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1760 | { | |
1761 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1762 | } | |
2e4b5889 OF |
1763 | else |
1764 | { | |
1765 | /* Invalid register. */ | |
1766 | return NULL; | |
29134980 | 1767 | } |
29134980 OF |
1768 | } |
1769 | ||
a5f6c8f5 OF |
1770 | /* Convert DWARF register number REG to the appropriate register |
1771 | number used by GDB. */ | |
1772 | ||
2e4b5889 | 1773 | static int |
d3f73121 | 1774 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
29134980 | 1775 | { |
a5f6c8f5 OF |
1776 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1777 | numbering, MOF is 18). | |
1778 | Adapted from gcc/config/cris/cris.h. */ | |
1779 | static int cris_dwarf_regmap[] = { | |
1780 | 0, 1, 2, 3, | |
1781 | 4, 5, 6, 7, | |
1782 | 8, 9, 10, 11, | |
1783 | 12, 13, 14, 15, | |
1784 | 27, -1, -1, -1, | |
1785 | -1, -1, -1, 23, | |
1786 | -1, -1, -1, 27, | |
1787 | -1, -1, -1, -1 | |
1788 | }; | |
1789 | int regnum = -1; | |
1790 | ||
1791 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1792 | regnum = cris_dwarf_regmap[reg]; | |
1793 | ||
1794 | if (regnum == -1) | |
8a3fe4f8 | 1795 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1796 | |
1797 | return regnum; | |
1798 | } | |
1799 | ||
1800 | /* DWARF-2 frame support. */ | |
1801 | ||
1802 | static void | |
1803 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1804 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1805 | struct frame_info *this_frame) |
a5f6c8f5 OF |
1806 | { |
1807 | /* The return address column. */ | |
7fbe2eba | 1808 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
a5f6c8f5 OF |
1809 | reg->how = DWARF2_FRAME_REG_RA; |
1810 | ||
1811 | /* The call frame address. */ | |
7fbe2eba | 1812 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 | 1813 | reg->how = DWARF2_FRAME_REG_CFA; |
29134980 OF |
1814 | } |
1815 | ||
2e4b5889 OF |
1816 | /* Extract from an array regbuf containing the raw register state a function |
1817 | return value of type type, and copy that, in virtual format, into | |
1818 | valbuf. */ | |
1819 | ||
1820 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1821 | |
2e4b5889 OF |
1822 | static void |
1823 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1824 | gdb_byte *valbuf) |
29134980 | 1825 | { |
e17a4113 UW |
1826 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1827 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2e4b5889 | 1828 | ULONGEST val; |
bad43aa5 | 1829 | int len = TYPE_LENGTH (type); |
29134980 | 1830 | |
bad43aa5 | 1831 | if (len <= 4) |
29134980 | 1832 | { |
2e4b5889 OF |
1833 | /* Get the return value from R10. */ |
1834 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
bad43aa5 | 1835 | store_unsigned_integer (valbuf, len, byte_order, val); |
29134980 | 1836 | } |
bad43aa5 | 1837 | else if (len <= 8) |
29134980 | 1838 | { |
2e4b5889 OF |
1839 | /* Get the return value from R10 and R11. */ |
1840 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
e17a4113 | 1841 | store_unsigned_integer (valbuf, 4, byte_order, val); |
2e4b5889 | 1842 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
948f8e3d | 1843 | store_unsigned_integer (valbuf + 4, len - 4, byte_order, val); |
29134980 | 1844 | } |
2e4b5889 | 1845 | else |
8a3fe4f8 | 1846 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1847 | } |
1848 | ||
b4206d25 OF |
1849 | /* Handle the CRIS return value convention. */ |
1850 | ||
1851 | static enum return_value_convention | |
6a3a010b | 1852 | cris_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1853 | struct type *type, struct regcache *regcache, |
1854 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b4206d25 OF |
1855 | { |
1856 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1857 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1858 | || TYPE_LENGTH (type) > 8) | |
1859 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1860 | goes on the stack. */ | |
1861 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1862 | ||
1863 | if (readbuf) | |
1864 | cris_extract_return_value (type, regcache, readbuf); | |
1865 | if (writebuf) | |
1866 | cris_store_return_value (type, regcache, writebuf); | |
1867 | ||
1868 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1869 | } | |
1870 | ||
29134980 OF |
1871 | /* Calculates a value that measures how good inst_args constraints an |
1872 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1873 | ||
1874 | static int | |
948f8e3d | 1875 | constraint (unsigned int insn, const char *inst_args, |
29134980 OF |
1876 | inst_env_type *inst_env) |
1877 | { | |
1878 | int retval = 0; | |
1879 | int tmp, i; | |
1880 | ||
948f8e3d | 1881 | const gdb_byte *s = (const gdb_byte *) inst_args; |
29134980 OF |
1882 | |
1883 | for (; *s; s++) | |
1884 | switch (*s) | |
1885 | { | |
1886 | case 'm': | |
1887 | if ((insn & 0x30) == 0x30) | |
1888 | return -1; | |
1889 | break; | |
1890 | ||
1891 | case 'S': | |
1892 | /* A prefix operand. */ | |
1893 | if (inst_env->prefix_found) | |
1894 | break; | |
1895 | else | |
1896 | return -1; | |
1897 | ||
1898 | case 'B': | |
1899 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1900 | valid "push" size. In case of special register, it may be != 4. */ | |
1901 | if (inst_env->prefix_found) | |
1902 | break; | |
1903 | else | |
1904 | return -1; | |
1905 | ||
1906 | case 'D': | |
1907 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1908 | if (!retval) | |
1909 | return -1; | |
1910 | else | |
1911 | retval += 4; | |
1912 | break; | |
1913 | ||
1914 | case 'P': | |
1915 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1916 | |
1917 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1918 | { | |
1919 | /* Since we match four bits, we will give a value of | |
1920 | 4 - 1 = 3 in a match. If there is a corresponding | |
1921 | exact match of a special register in another pattern, it | |
1922 | will get a value of 4, which will be higher. This should | |
1923 | be correct in that an exact pattern would match better that | |
1924 | a general pattern. | |
1925 | Note that there is a reason for not returning zero; the | |
1926 | pattern for "clear" is partly matched in the bit-pattern | |
1927 | (the two lower bits must be zero), while the bit-pattern | |
1928 | for a move from a special register is matched in the | |
1929 | register constraint. | |
1930 | This also means we will will have a race condition if | |
1931 | there is a partly match in three bits in the bit pattern. */ | |
1932 | if (tmp == cris_spec_regs[i].number) | |
1933 | { | |
1934 | retval += 3; | |
1935 | break; | |
1936 | } | |
1937 | } | |
1938 | ||
1939 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1940 | return -1; |
1941 | break; | |
1942 | } | |
1943 | return retval; | |
1944 | } | |
1945 | ||
1946 | /* Returns the number of bits set in the variable value. */ | |
1947 | ||
1948 | static int | |
1949 | number_of_bits (unsigned int value) | |
1950 | { | |
1951 | int number_of_bits = 0; | |
1952 | ||
1953 | while (value != 0) | |
1954 | { | |
1955 | number_of_bits += 1; | |
1956 | value &= (value - 1); | |
1957 | } | |
1958 | return number_of_bits; | |
1959 | } | |
1960 | ||
1961 | /* Finds the address that should contain the single step breakpoint(s). | |
1962 | It stems from code in cris-dis.c. */ | |
1963 | ||
1964 | static int | |
1965 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1966 | { | |
1967 | int i; | |
1968 | int max_level_of_match = -1; | |
1969 | int max_matched = -1; | |
1970 | int level_of_match; | |
1971 | ||
1972 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1973 | { | |
1974 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
1975 | && ((cris_opcodes[i].lose & insn) == 0) |
1976 | /* Only CRISv10 instructions, please. */ | |
1977 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
1978 | { |
1979 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1980 | if (level_of_match >= 0) | |
1981 | { | |
1982 | level_of_match += | |
1983 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1984 | if (level_of_match > max_level_of_match) | |
1985 | { | |
1986 | max_matched = i; | |
1987 | max_level_of_match = level_of_match; | |
1988 | if (level_of_match == 16) | |
1989 | { | |
1990 | /* All bits matched, cannot find better. */ | |
1991 | break; | |
1992 | } | |
1993 | } | |
1994 | } | |
1995 | } | |
1996 | } | |
1997 | return max_matched; | |
1998 | } | |
1999 | ||
2000 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2001 | actually an internal error. */ | |
2002 | ||
2003 | static int | |
0b1b3e42 | 2004 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
29134980 OF |
2005 | { |
2006 | int i; | |
2007 | int offset; | |
2008 | unsigned short insn; | |
7fbe2eba | 2009 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2010 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
29134980 OF |
2011 | |
2012 | /* Create a local register image and set the initial state. */ | |
2013 | for (i = 0; i < NUM_GENREGS; i++) | |
2014 | { | |
0b1b3e42 UW |
2015 | inst_env->reg[i] = |
2016 | (unsigned long) get_frame_register_unsigned (frame, i); | |
29134980 OF |
2017 | } |
2018 | offset = NUM_GENREGS; | |
2019 | for (i = 0; i < NUM_SPECREGS; i++) | |
2020 | { | |
0b1b3e42 UW |
2021 | inst_env->preg[i] = |
2022 | (unsigned long) get_frame_register_unsigned (frame, offset + i); | |
29134980 OF |
2023 | } |
2024 | inst_env->branch_found = 0; | |
2025 | inst_env->slot_needed = 0; | |
2026 | inst_env->delay_slot_pc_active = 0; | |
2027 | inst_env->prefix_found = 0; | |
2028 | inst_env->invalid = 0; | |
2029 | inst_env->xflag_found = 0; | |
2030 | inst_env->disable_interrupt = 0; | |
e17a4113 | 2031 | inst_env->byte_order = byte_order; |
29134980 OF |
2032 | |
2033 | /* Look for a step target. */ | |
2034 | do | |
2035 | { | |
2036 | /* Read an instruction from the client. */ | |
3e8c568d | 2037 | insn = read_memory_unsigned_integer |
e17a4113 | 2038 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
29134980 OF |
2039 | |
2040 | /* If the instruction is not in a delay slot the new content of the | |
2041 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2042 | that simple. Since a instruction in a delay slot cannot change | |
2043 | the content of the PC, it does not matter what value PC will have. | |
2044 | Just make sure it is a valid instruction. */ | |
2045 | if (!inst_env->delay_slot_pc_active) | |
2046 | { | |
7fbe2eba | 2047 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; |
29134980 OF |
2048 | } |
2049 | else | |
2050 | { | |
2051 | inst_env->delay_slot_pc_active = 0; | |
7fbe2eba | 2052 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 2053 | = inst_env->delay_slot_pc; |
29134980 OF |
2054 | } |
2055 | /* Analyse the present instruction. */ | |
2056 | i = find_cris_op (insn, inst_env); | |
2057 | if (i == -1) | |
2058 | { | |
2059 | inst_env->invalid = 1; | |
2060 | } | |
2061 | else | |
2062 | { | |
be8626e0 | 2063 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); |
29134980 OF |
2064 | } |
2065 | } while (!inst_env->invalid | |
2066 | && (inst_env->prefix_found || inst_env->xflag_found | |
2067 | || inst_env->slot_needed)); | |
2068 | return i; | |
2069 | } | |
2070 | ||
2071 | /* There is no hardware single-step support. The function find_step_target | |
0963b4bd | 2072 | digs through the opcodes in order to find all possible targets. |
29134980 OF |
2073 | Either one ordinary target or two targets for branches may be found. */ |
2074 | ||
e6590a1b | 2075 | static int |
0b1b3e42 | 2076 | cris_software_single_step (struct frame_info *frame) |
29134980 | 2077 | { |
a6d9a66e | 2078 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2079 | struct address_space *aspace = get_frame_address_space (frame); |
29134980 | 2080 | inst_env_type inst_env; |
8181d85f | 2081 | |
e0cd558a UW |
2082 | /* Analyse the present instruction environment and insert |
2083 | breakpoints. */ | |
0b1b3e42 | 2084 | int status = find_step_target (frame, &inst_env); |
e0cd558a | 2085 | if (status == -1) |
29134980 | 2086 | { |
e0cd558a UW |
2087 | /* Could not find a target. Things are likely to go downhill |
2088 | from here. */ | |
2089 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2090 | } |
2091 | else | |
e0cd558a UW |
2092 | { |
2093 | /* Insert at most two breakpoints. One for the next PC content | |
2094 | and possibly another one for a branch, jump, etc. */ | |
a6d9a66e UW |
2095 | CORE_ADDR next_pc |
2096 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; | |
6c95b8df | 2097 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e0cd558a UW |
2098 | if (inst_env.branch_found |
2099 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2100 | { | |
2101 | CORE_ADDR branch_target_address | |
2102 | = (CORE_ADDR) inst_env.branch_break_address; | |
6c95b8df PA |
2103 | insert_single_step_breakpoint (gdbarch, |
2104 | aspace, branch_target_address); | |
e0cd558a UW |
2105 | } |
2106 | } | |
e6590a1b UW |
2107 | |
2108 | return 1; | |
29134980 OF |
2109 | } |
2110 | ||
2111 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2112 | ||
a78f21af | 2113 | static void |
29134980 OF |
2114 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2115 | { | |
2116 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2117 | instruction (not 100% sure). */ | |
2118 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2119 | { | |
2120 | inst_env->invalid = 1; | |
2121 | return; | |
2122 | } | |
2123 | ||
2124 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2125 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2126 | ||
2127 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2128 | need updating. */ | |
2129 | inst_env->slot_needed = 0; | |
2130 | inst_env->prefix_found = 1; | |
2131 | } | |
2132 | ||
2133 | /* Updates the autoincrement register. The size of the increment is derived | |
2134 | from the size of the operation. The PC is always kept aligned on even | |
2135 | word addresses. */ | |
2136 | ||
a78f21af | 2137 | static void |
29134980 OF |
2138 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2139 | { | |
2140 | if (size == INST_BYTE_SIZE) | |
2141 | { | |
2142 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2143 | ||
2144 | /* The PC must be word aligned, so increase the PC with one | |
2145 | word even if the size is byte. */ | |
2146 | if (cris_get_operand1 (inst) == REG_PC) | |
2147 | { | |
2148 | inst_env->reg[REG_PC] += 1; | |
2149 | } | |
2150 | } | |
2151 | else if (size == INST_WORD_SIZE) | |
2152 | { | |
2153 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2154 | } | |
2155 | else if (size == INST_DWORD_SIZE) | |
2156 | { | |
2157 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2158 | } | |
2159 | else | |
2160 | { | |
2161 | /* Invalid size. */ | |
2162 | inst_env->invalid = 1; | |
2163 | } | |
2164 | } | |
2165 | ||
2a9ecef2 OF |
2166 | /* Just a forward declaration. */ |
2167 | ||
a78f21af | 2168 | static unsigned long get_data_from_address (unsigned short *inst, |
e17a4113 UW |
2169 | CORE_ADDR address, |
2170 | enum bfd_endian byte_order); | |
2a9ecef2 | 2171 | |
29134980 OF |
2172 | /* Calculates the prefix value for the general case of offset addressing |
2173 | mode. */ | |
2174 | ||
a78f21af | 2175 | static void |
29134980 OF |
2176 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2177 | { | |
29134980 OF |
2178 | /* It's invalid to be in a delay slot. */ |
2179 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2180 | { | |
2181 | inst_env->invalid = 1; | |
2182 | return; | |
2183 | } | |
2184 | ||
fa4e4598 OF |
2185 | /* The calculation of prefix_value used to be after process_autoincrement, |
2186 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2187 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2188 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2189 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2190 | ||
2191 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2192 | inst_env->prefix_value += | |
e17a4113 UW |
2193 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
2194 | inst_env->byte_order); | |
2a9ecef2 | 2195 | |
fa4e4598 OF |
2196 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2197 | { | |
2198 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2199 | } | |
2200 | ||
29134980 OF |
2201 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2202 | need updating. */ | |
2203 | inst_env->slot_needed = 0; | |
2204 | inst_env->prefix_found = 1; | |
2205 | } | |
2206 | ||
2207 | /* Calculates the prefix value for the index addressing mode. */ | |
2208 | ||
a78f21af | 2209 | static void |
29134980 OF |
2210 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2211 | { | |
2212 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2213 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2214 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2215 | { | |
2216 | inst_env->invalid = 1; | |
2217 | return; | |
2218 | } | |
2219 | ||
2220 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2221 | ||
2222 | /* The offset is the operand2 value shifted the size of the instruction | |
2223 | to the left. */ | |
2224 | inst_env->prefix_value += | |
2225 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2226 | ||
2227 | /* If the PC is operand1 (base) the address used is the address after | |
2228 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2229 | for the prefix operation). */ | |
2230 | if (cris_get_operand1 (inst) == REG_PC) | |
2231 | { | |
2232 | inst_env->prefix_value += 2; | |
2233 | } | |
2234 | ||
2235 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2236 | need updating. */ | |
2237 | inst_env->slot_needed = 0; | |
2238 | inst_env->xflag_found = 0; | |
2239 | inst_env->prefix_found = 1; | |
2240 | } | |
2241 | ||
2242 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2243 | ||
a78f21af | 2244 | static void |
29134980 OF |
2245 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2246 | { | |
2247 | ||
2248 | CORE_ADDR address; | |
2249 | ||
2250 | /* It's invalid to be in a delay slot. */ | |
2251 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2252 | { | |
2253 | inst_env->invalid = 1; | |
2254 | return; | |
2255 | } | |
2256 | ||
2257 | /* The prefix value is one dereference of the contents of the operand1 | |
2258 | register. */ | |
2259 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2260 | inst_env->prefix_value |
2261 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); | |
29134980 OF |
2262 | |
2263 | /* Check if the mode is autoincrement. */ | |
2264 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2265 | { | |
2266 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2267 | } | |
2268 | ||
2269 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2270 | need updating. */ | |
2271 | inst_env->slot_needed = 0; | |
2272 | inst_env->xflag_found = 0; | |
2273 | inst_env->prefix_found = 1; | |
2274 | } | |
2275 | ||
2276 | /* Finds the destination for a branch with 8-bits offset. */ | |
2277 | ||
a78f21af | 2278 | static void |
29134980 OF |
2279 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2280 | { | |
2281 | ||
2282 | short offset; | |
2283 | ||
2284 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2285 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2286 | { | |
2287 | inst_env->invalid = 1; | |
2288 | return; | |
2289 | } | |
2290 | ||
2291 | /* We have a branch, find out where the branch will land. */ | |
2292 | offset = cris_get_branch_short_offset (inst); | |
2293 | ||
2294 | /* Check if the offset is signed. */ | |
2295 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2296 | { | |
2297 | offset |= 0xFF00; | |
2298 | } | |
2299 | ||
2300 | /* The offset ends with the sign bit, set it to zero. The address | |
2301 | should always be word aligned. */ | |
2302 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2303 | ||
2304 | inst_env->branch_found = 1; | |
2305 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2306 | ||
2307 | inst_env->slot_needed = 1; | |
2308 | inst_env->prefix_found = 0; | |
2309 | inst_env->xflag_found = 0; | |
2310 | inst_env->disable_interrupt = 1; | |
2311 | } | |
2312 | ||
2313 | /* Finds the destination for a branch with 16-bits offset. */ | |
2314 | ||
a78f21af | 2315 | static void |
29134980 OF |
2316 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2317 | { | |
2318 | short offset; | |
2319 | ||
2320 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2321 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2322 | { | |
2323 | inst_env->invalid = 1; | |
2324 | return; | |
2325 | } | |
2326 | ||
2327 | /* We have a branch, find out the offset for the branch. */ | |
0963b4bd MS |
2328 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, |
2329 | inst_env->byte_order); | |
29134980 OF |
2330 | |
2331 | /* The instruction is one word longer than normal, so add one word | |
2332 | to the PC. */ | |
2333 | inst_env->reg[REG_PC] += 2; | |
2334 | ||
2335 | inst_env->branch_found = 1; | |
2336 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2337 | ||
2338 | ||
2339 | inst_env->slot_needed = 1; | |
2340 | inst_env->prefix_found = 0; | |
2341 | inst_env->xflag_found = 0; | |
2342 | inst_env->disable_interrupt = 1; | |
2343 | } | |
2344 | ||
2345 | /* Handles the ABS instruction. */ | |
2346 | ||
a78f21af | 2347 | static void |
29134980 OF |
2348 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2349 | { | |
2350 | ||
2351 | long value; | |
2352 | ||
2353 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2354 | if (inst_env->prefix_found) | |
2355 | { | |
2356 | inst_env->invalid = 1; | |
2357 | return; | |
2358 | } | |
2359 | ||
2360 | /* Check if the operation affects the PC. */ | |
2361 | if (cris_get_operand2 (inst) == REG_PC) | |
2362 | { | |
2363 | ||
2364 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2365 | if (inst_env->slot_needed) | |
2366 | { | |
2367 | inst_env->invalid = 1; | |
2368 | return; | |
2369 | } | |
2370 | ||
2371 | value = (long) inst_env->reg[REG_PC]; | |
2372 | ||
2373 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2374 | if (value != SIGNED_DWORD_MASK) | |
2375 | { | |
2376 | value = -value; | |
2377 | inst_env->reg[REG_PC] = (long) value; | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | inst_env->slot_needed = 0; | |
2382 | inst_env->prefix_found = 0; | |
2383 | inst_env->xflag_found = 0; | |
2384 | inst_env->disable_interrupt = 0; | |
2385 | } | |
2386 | ||
2387 | /* Handles the ADDI instruction. */ | |
2388 | ||
a78f21af | 2389 | static void |
29134980 OF |
2390 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2391 | { | |
2392 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2393 | a prefix. */ | |
2394 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2395 | { | |
2396 | inst_env->invalid = 1; | |
2397 | return; | |
2398 | } | |
2399 | ||
2400 | inst_env->slot_needed = 0; | |
2401 | inst_env->prefix_found = 0; | |
2402 | inst_env->xflag_found = 0; | |
2403 | inst_env->disable_interrupt = 0; | |
2404 | } | |
2405 | ||
2406 | /* Handles the ASR instruction. */ | |
2407 | ||
a78f21af | 2408 | static void |
29134980 OF |
2409 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2410 | { | |
2411 | int shift_steps; | |
2412 | unsigned long value; | |
2413 | unsigned long signed_extend_mask = 0; | |
2414 | ||
2415 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2416 | if (inst_env->prefix_found) | |
2417 | { | |
2418 | inst_env->invalid = 1; | |
2419 | return; | |
2420 | } | |
2421 | ||
2422 | /* Check if the PC is the target register. */ | |
2423 | if (cris_get_operand2 (inst) == REG_PC) | |
2424 | { | |
2425 | /* It's invalid to change the PC in a delay slot. */ | |
2426 | if (inst_env->slot_needed) | |
2427 | { | |
2428 | inst_env->invalid = 1; | |
2429 | return; | |
2430 | } | |
2431 | /* Get the number of bits to shift. */ | |
0963b4bd MS |
2432 | shift_steps |
2433 | = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
29134980 OF |
2434 | value = inst_env->reg[REG_PC]; |
2435 | ||
2436 | /* Find out how many bits the operation should apply to. */ | |
2437 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2438 | { | |
2439 | if (value & SIGNED_BYTE_MASK) | |
2440 | { | |
2441 | signed_extend_mask = 0xFF; | |
2442 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2443 | signed_extend_mask = ~signed_extend_mask; | |
2444 | } | |
2445 | value = value >> shift_steps; | |
2446 | value |= signed_extend_mask; | |
2447 | value &= 0xFF; | |
2448 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2449 | inst_env->reg[REG_PC] |= value; | |
2450 | } | |
2451 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2452 | { | |
2453 | if (value & SIGNED_WORD_MASK) | |
2454 | { | |
2455 | signed_extend_mask = 0xFFFF; | |
2456 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2457 | signed_extend_mask = ~signed_extend_mask; | |
2458 | } | |
2459 | value = value >> shift_steps; | |
2460 | value |= signed_extend_mask; | |
2461 | value &= 0xFFFF; | |
2462 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2463 | inst_env->reg[REG_PC] |= value; | |
2464 | } | |
2465 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2466 | { | |
2467 | if (value & SIGNED_DWORD_MASK) | |
2468 | { | |
2469 | signed_extend_mask = 0xFFFFFFFF; | |
2470 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2471 | signed_extend_mask = ~signed_extend_mask; | |
2472 | } | |
2473 | value = value >> shift_steps; | |
2474 | value |= signed_extend_mask; | |
2475 | inst_env->reg[REG_PC] = value; | |
2476 | } | |
2477 | } | |
2478 | inst_env->slot_needed = 0; | |
2479 | inst_env->prefix_found = 0; | |
2480 | inst_env->xflag_found = 0; | |
2481 | inst_env->disable_interrupt = 0; | |
2482 | } | |
2483 | ||
2484 | /* Handles the ASRQ instruction. */ | |
2485 | ||
a78f21af | 2486 | static void |
29134980 OF |
2487 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2488 | { | |
2489 | ||
2490 | int shift_steps; | |
2491 | unsigned long value; | |
2492 | unsigned long signed_extend_mask = 0; | |
2493 | ||
2494 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2495 | if (inst_env->prefix_found) | |
2496 | { | |
2497 | inst_env->invalid = 1; | |
2498 | return; | |
2499 | } | |
2500 | ||
2501 | /* Check if the PC is the target register. */ | |
2502 | if (cris_get_operand2 (inst) == REG_PC) | |
2503 | { | |
2504 | ||
2505 | /* It's invalid to change the PC in a delay slot. */ | |
2506 | if (inst_env->slot_needed) | |
2507 | { | |
2508 | inst_env->invalid = 1; | |
2509 | return; | |
2510 | } | |
2511 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
b021a221 | 2512 | want the sign bit of the quick value. */ |
29134980 OF |
2513 | shift_steps = cris_get_asr_shift_steps (inst); |
2514 | value = inst_env->reg[REG_PC]; | |
2515 | if (value & SIGNED_DWORD_MASK) | |
2516 | { | |
2517 | signed_extend_mask = 0xFFFFFFFF; | |
2518 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2519 | signed_extend_mask = ~signed_extend_mask; | |
2520 | } | |
2521 | value = value >> shift_steps; | |
2522 | value |= signed_extend_mask; | |
2523 | inst_env->reg[REG_PC] = value; | |
2524 | } | |
2525 | inst_env->slot_needed = 0; | |
2526 | inst_env->prefix_found = 0; | |
2527 | inst_env->xflag_found = 0; | |
2528 | inst_env->disable_interrupt = 0; | |
2529 | } | |
2530 | ||
2531 | /* Handles the AX, EI and SETF instruction. */ | |
2532 | ||
a78f21af | 2533 | static void |
29134980 OF |
2534 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2535 | { | |
2536 | if (inst_env->prefix_found) | |
2537 | { | |
2538 | inst_env->invalid = 1; | |
2539 | return; | |
2540 | } | |
2541 | /* Check if the instruction is setting the X flag. */ | |
2542 | if (cris_is_xflag_bit_on (inst)) | |
2543 | { | |
2544 | inst_env->xflag_found = 1; | |
2545 | } | |
2546 | else | |
2547 | { | |
2548 | inst_env->xflag_found = 0; | |
2549 | } | |
2550 | inst_env->slot_needed = 0; | |
2551 | inst_env->prefix_found = 0; | |
2552 | inst_env->disable_interrupt = 1; | |
2553 | } | |
2554 | ||
2555 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2556 | register. Note that check_assign assumes that the caller has checked that | |
2557 | there is a prefix to this instruction. The mode check depends on this. */ | |
2558 | ||
a78f21af | 2559 | static void |
29134980 OF |
2560 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2561 | { | |
2562 | /* Check if it's an assign addressing mode. */ | |
2563 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2564 | { | |
2565 | /* Assign the prefix value to operand 1. */ | |
2566 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | /* Handles the 2-operand BOUND instruction. */ | |
2571 | ||
a78f21af | 2572 | static void |
29134980 OF |
2573 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2574 | { | |
2575 | /* It's invalid to have the PC as the index operand. */ | |
2576 | if (cris_get_operand2 (inst) == REG_PC) | |
2577 | { | |
2578 | inst_env->invalid = 1; | |
2579 | return; | |
2580 | } | |
2581 | /* Check if we have a prefix. */ | |
2582 | if (inst_env->prefix_found) | |
2583 | { | |
2584 | check_assign (inst, inst_env); | |
2585 | } | |
2586 | /* Check if this is an autoincrement mode. */ | |
2587 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2588 | { | |
2589 | /* It's invalid to change the PC in a delay slot. */ | |
2590 | if (inst_env->slot_needed) | |
2591 | { | |
2592 | inst_env->invalid = 1; | |
2593 | return; | |
2594 | } | |
2595 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2596 | } | |
2597 | inst_env->slot_needed = 0; | |
2598 | inst_env->prefix_found = 0; | |
2599 | inst_env->xflag_found = 0; | |
2600 | inst_env->disable_interrupt = 0; | |
2601 | } | |
2602 | ||
2603 | /* Handles the 3-operand BOUND instruction. */ | |
2604 | ||
a78f21af | 2605 | static void |
29134980 OF |
2606 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2607 | { | |
2608 | /* It's an error if we haven't got a prefix. And it's also an error | |
2609 | if the PC is the destination register. */ | |
2610 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2611 | { | |
2612 | inst_env->invalid = 1; | |
2613 | return; | |
2614 | } | |
2615 | inst_env->slot_needed = 0; | |
2616 | inst_env->prefix_found = 0; | |
2617 | inst_env->xflag_found = 0; | |
2618 | inst_env->disable_interrupt = 0; | |
2619 | } | |
2620 | ||
2621 | /* Clears the status flags in inst_env. */ | |
2622 | ||
a78f21af | 2623 | static void |
29134980 OF |
2624 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2625 | { | |
2626 | /* It's an error if we have got a prefix. */ | |
2627 | if (inst_env->prefix_found) | |
2628 | { | |
2629 | inst_env->invalid = 1; | |
2630 | return; | |
2631 | } | |
2632 | ||
2633 | inst_env->slot_needed = 0; | |
2634 | inst_env->prefix_found = 0; | |
2635 | inst_env->xflag_found = 0; | |
2636 | inst_env->disable_interrupt = 0; | |
2637 | } | |
2638 | ||
2639 | /* Clears the status flags in inst_env. */ | |
2640 | ||
a78f21af | 2641 | static void |
29134980 OF |
2642 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2643 | { | |
2644 | /* It's an error if we have got a prefix. */ | |
2645 | if (inst_env->prefix_found) | |
2646 | { | |
2647 | inst_env->invalid = 1; | |
2648 | return; | |
2649 | } | |
2650 | ||
2651 | inst_env->slot_needed = 0; | |
2652 | inst_env->prefix_found = 0; | |
2653 | inst_env->xflag_found = 0; | |
2654 | inst_env->disable_interrupt = 1; | |
2655 | } | |
2656 | ||
2657 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2658 | ||
a78f21af | 2659 | static void |
29134980 OF |
2660 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2661 | { | |
2662 | /* Check if the target is the PC. */ | |
2663 | if (cris_get_operand2 (inst) == REG_PC) | |
2664 | { | |
2665 | /* The instruction will clear the instruction's size bits. */ | |
2666 | int clear_size = cris_get_clear_size (inst); | |
2667 | if (clear_size == INST_BYTE_SIZE) | |
2668 | { | |
2669 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2670 | } | |
2671 | if (clear_size == INST_WORD_SIZE) | |
2672 | { | |
2673 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2674 | } | |
2675 | if (clear_size == INST_DWORD_SIZE) | |
2676 | { | |
2677 | inst_env->delay_slot_pc = 0x0; | |
2678 | } | |
2679 | /* The jump will be delayed with one delay slot. So we need a delay | |
2680 | slot. */ | |
2681 | inst_env->slot_needed = 1; | |
2682 | inst_env->delay_slot_pc_active = 1; | |
2683 | } | |
2684 | else | |
2685 | { | |
2686 | /* The PC will not change => no delay slot. */ | |
2687 | inst_env->slot_needed = 0; | |
2688 | } | |
2689 | inst_env->prefix_found = 0; | |
2690 | inst_env->xflag_found = 0; | |
2691 | inst_env->disable_interrupt = 0; | |
2692 | } | |
2693 | ||
2694 | /* Handles the TEST instruction if it's in register mode. */ | |
2695 | ||
a78f21af | 2696 | static void |
29134980 OF |
2697 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2698 | { | |
2699 | /* It's an error if we have got a prefix. */ | |
2700 | if (inst_env->prefix_found) | |
2701 | { | |
2702 | inst_env->invalid = 1; | |
2703 | return; | |
2704 | } | |
2705 | inst_env->slot_needed = 0; | |
2706 | inst_env->prefix_found = 0; | |
2707 | inst_env->xflag_found = 0; | |
2708 | inst_env->disable_interrupt = 0; | |
2709 | ||
2710 | } | |
2711 | ||
2712 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2713 | in register mode. */ | |
2714 | ||
a78f21af | 2715 | static void |
29134980 OF |
2716 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2717 | { | |
2718 | /* Check if we are in a prefix mode. */ | |
2719 | if (inst_env->prefix_found) | |
2720 | { | |
2721 | /* The only way the PC can change is if this instruction is in | |
2722 | assign addressing mode. */ | |
2723 | check_assign (inst, inst_env); | |
2724 | } | |
2725 | /* Indirect mode can't change the PC so just check if the mode is | |
2726 | autoincrement. */ | |
2727 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2728 | { | |
2729 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2730 | } | |
2731 | inst_env->slot_needed = 0; | |
2732 | inst_env->prefix_found = 0; | |
2733 | inst_env->xflag_found = 0; | |
2734 | inst_env->disable_interrupt = 0; | |
2735 | } | |
2736 | ||
2737 | /* Checks that the PC isn't the destination register or the instructions has | |
2738 | a prefix. */ | |
2739 | ||
a78f21af | 2740 | static void |
29134980 OF |
2741 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2742 | { | |
2743 | /* It's invalid to have the PC as the destination. The instruction can't | |
2744 | have a prefix. */ | |
2745 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2746 | { | |
2747 | inst_env->invalid = 1; | |
2748 | return; | |
2749 | } | |
2750 | ||
2751 | inst_env->slot_needed = 0; | |
2752 | inst_env->prefix_found = 0; | |
2753 | inst_env->xflag_found = 0; | |
2754 | inst_env->disable_interrupt = 0; | |
2755 | } | |
2756 | ||
2757 | /* Checks that the instruction doesn't have a prefix. */ | |
2758 | ||
a78f21af | 2759 | static void |
29134980 OF |
2760 | break_op (unsigned short inst, inst_env_type *inst_env) |
2761 | { | |
2762 | /* The instruction can't have a prefix. */ | |
2763 | if (inst_env->prefix_found) | |
2764 | { | |
2765 | inst_env->invalid = 1; | |
2766 | return; | |
2767 | } | |
2768 | ||
2769 | inst_env->slot_needed = 0; | |
2770 | inst_env->prefix_found = 0; | |
2771 | inst_env->xflag_found = 0; | |
2772 | inst_env->disable_interrupt = 1; | |
2773 | } | |
2774 | ||
2775 | /* Checks that the PC isn't the destination register and that the instruction | |
2776 | doesn't have a prefix. */ | |
2777 | ||
a78f21af | 2778 | static void |
29134980 OF |
2779 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2780 | { | |
2781 | /* It's invalid to have the PC as the destination. The instruction can't | |
2782 | have a prefix. */ | |
2783 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2784 | { | |
2785 | inst_env->invalid = 1; | |
2786 | return; | |
2787 | } | |
2788 | ||
2789 | inst_env->slot_needed = 0; | |
2790 | inst_env->prefix_found = 0; | |
2791 | inst_env->xflag_found = 0; | |
2792 | inst_env->disable_interrupt = 1; | |
2793 | } | |
2794 | ||
2795 | /* Handles the register mode JUMP instruction. */ | |
2796 | ||
a78f21af | 2797 | static void |
29134980 OF |
2798 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2799 | { | |
2800 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2801 | you can't have a prefix. */ | |
2802 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2803 | { | |
2804 | inst_env->invalid = 1; | |
2805 | return; | |
2806 | } | |
2807 | ||
2808 | /* Just change the PC. */ | |
2809 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2810 | inst_env->slot_needed = 0; | |
2811 | inst_env->prefix_found = 0; | |
2812 | inst_env->xflag_found = 0; | |
2813 | inst_env->disable_interrupt = 1; | |
2814 | } | |
2815 | ||
2816 | /* Handles the JUMP instruction for all modes except register. */ | |
2817 | ||
a78f21af AC |
2818 | static void |
2819 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2820 | { |
2821 | unsigned long newpc; | |
2822 | CORE_ADDR address; | |
2823 | ||
2824 | /* It's invalid to do a JUMP in a delay slot. */ | |
2825 | if (inst_env->slot_needed) | |
2826 | { | |
2827 | inst_env->invalid = 1; | |
2828 | } | |
2829 | else | |
2830 | { | |
2831 | /* Check if we have a prefix. */ | |
2832 | if (inst_env->prefix_found) | |
2833 | { | |
2834 | check_assign (inst, inst_env); | |
2835 | ||
b021a221 | 2836 | /* Get the new value for the PC. */ |
29134980 OF |
2837 | newpc = |
2838 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
e17a4113 | 2839 | 4, inst_env->byte_order); |
29134980 OF |
2840 | } |
2841 | else | |
2842 | { | |
2843 | /* Get the new value for the PC. */ | |
2844 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2845 | newpc = read_memory_unsigned_integer (address, |
2846 | 4, inst_env->byte_order); | |
29134980 OF |
2847 | |
2848 | /* Check if we should increment a register. */ | |
2849 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2850 | { | |
2851 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2852 | } | |
2853 | } | |
2854 | inst_env->reg[REG_PC] = newpc; | |
2855 | } | |
2856 | inst_env->slot_needed = 0; | |
2857 | inst_env->prefix_found = 0; | |
2858 | inst_env->xflag_found = 0; | |
2859 | inst_env->disable_interrupt = 1; | |
2860 | } | |
2861 | ||
2862 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2863 | ||
a78f21af | 2864 | static void |
be8626e0 MD |
2865 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2866 | inst_env_type *inst_env) | |
29134980 OF |
2867 | { |
2868 | if (inst_env->prefix_found) | |
2869 | { | |
2870 | /* The instruction has a prefix that means we are only interested if | |
2871 | the instruction is in assign mode. */ | |
2872 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2873 | { | |
2874 | /* The prefix handles the problem if we are in a delay slot. */ | |
2875 | if (cris_get_operand1 (inst) == REG_PC) | |
2876 | { | |
2877 | /* Just take care of the assign. */ | |
2878 | check_assign (inst, inst_env); | |
2879 | } | |
2880 | } | |
2881 | } | |
2882 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2883 | { | |
2884 | /* The instruction doesn't have a prefix, the only case left that we | |
2885 | are interested in is the autoincrement mode. */ | |
2886 | if (cris_get_operand1 (inst) == REG_PC) | |
2887 | { | |
2888 | /* If the PC is to be incremented it's invalid to be in a | |
2889 | delay slot. */ | |
2890 | if (inst_env->slot_needed) | |
2891 | { | |
2892 | inst_env->invalid = 1; | |
2893 | return; | |
2894 | } | |
2a9ecef2 OF |
2895 | |
2896 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 2897 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
2898 | { |
2899 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2900 | } | |
be8626e0 | 2901 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
2902 | { |
2903 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2904 | } | |
2905 | else | |
2906 | { | |
2907 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2908 | } | |
2909 | } | |
2910 | } | |
2911 | inst_env->slot_needed = 0; | |
2912 | inst_env->prefix_found = 0; | |
2913 | inst_env->xflag_found = 0; | |
2914 | inst_env->disable_interrupt = 1; | |
2915 | } | |
2916 | ||
2917 | /* Handles moves from special registers (aka P-register) for all modes | |
2918 | except register. */ | |
2919 | ||
a78f21af | 2920 | static void |
be8626e0 MD |
2921 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2922 | inst_env_type *inst_env) | |
29134980 OF |
2923 | { |
2924 | if (inst_env->prefix_found) | |
2925 | { | |
2926 | /* The instruction has a prefix that means we are only interested if | |
2927 | the instruction is in assign mode. */ | |
2928 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2929 | { | |
2930 | /* The prefix handles the problem if we are in a delay slot. */ | |
2931 | if (cris_get_operand1 (inst) == REG_PC) | |
2932 | { | |
2933 | /* Just take care of the assign. */ | |
2934 | check_assign (inst, inst_env); | |
2935 | } | |
2936 | } | |
2937 | } | |
2938 | /* The instruction doesn't have a prefix, the only case left that we | |
2939 | are interested in is the autoincrement mode. */ | |
2940 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2941 | { | |
2942 | if (cris_get_operand1 (inst) == REG_PC) | |
2943 | { | |
2944 | /* If the PC is to be incremented it's invalid to be in a | |
2945 | delay slot. */ | |
2946 | if (inst_env->slot_needed) | |
2947 | { | |
2948 | inst_env->invalid = 1; | |
2949 | return; | |
2950 | } | |
2a9ecef2 OF |
2951 | |
2952 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 2953 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
2954 | { |
2955 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2956 | } | |
be8626e0 | 2957 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
2958 | { |
2959 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2960 | } | |
2961 | else | |
2962 | { | |
2963 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2964 | } | |
2965 | } | |
2966 | } | |
2967 | inst_env->slot_needed = 0; | |
2968 | inst_env->prefix_found = 0; | |
2969 | inst_env->xflag_found = 0; | |
2970 | inst_env->disable_interrupt = 1; | |
2971 | } | |
2972 | ||
2973 | /* Handles moves from special registers (aka P-register) when the mode | |
2974 | is register. */ | |
2975 | ||
a78f21af | 2976 | static void |
29134980 OF |
2977 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2978 | { | |
2979 | /* Register mode move from special register can't have a prefix. */ | |
2980 | if (inst_env->prefix_found) | |
2981 | { | |
2982 | inst_env->invalid = 1; | |
2983 | return; | |
2984 | } | |
2985 | ||
2986 | if (cris_get_operand1 (inst) == REG_PC) | |
2987 | { | |
2988 | /* It's invalid to change the PC in a delay slot. */ | |
2989 | if (inst_env->slot_needed) | |
2990 | { | |
2991 | inst_env->invalid = 1; | |
2992 | return; | |
2993 | } | |
2994 | /* The destination is the PC, the jump will have a delay slot. */ | |
2995 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2996 | inst_env->slot_needed = 1; | |
2997 | inst_env->delay_slot_pc_active = 1; | |
2998 | } | |
2999 | else | |
3000 | { | |
3001 | /* If the destination isn't PC, there will be no jump. */ | |
3002 | inst_env->slot_needed = 0; | |
3003 | } | |
3004 | inst_env->prefix_found = 0; | |
3005 | inst_env->xflag_found = 0; | |
3006 | inst_env->disable_interrupt = 1; | |
3007 | } | |
3008 | ||
3009 | /* Handles the MOVEM from memory to general register instruction. */ | |
3010 | ||
a78f21af | 3011 | static void |
29134980 OF |
3012 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3013 | { | |
3014 | if (inst_env->prefix_found) | |
3015 | { | |
3016 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3017 | MOVEM instruction going to change the PC? */ | |
3018 | if (cris_get_operand2 (inst) >= REG_PC) | |
3019 | { | |
3020 | inst_env->reg[REG_PC] = | |
e17a4113 UW |
3021 | read_memory_unsigned_integer (inst_env->prefix_value, |
3022 | 4, inst_env->byte_order); | |
29134980 OF |
3023 | } |
3024 | /* The assign value is the value after the increment. Normally, the | |
3025 | assign value is the value before the increment. */ | |
3026 | if ((cris_get_operand1 (inst) == REG_PC) | |
3027 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3028 | { | |
3029 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3030 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3031 | } | |
3032 | } | |
3033 | else | |
3034 | { | |
3035 | /* Is the MOVEM instruction going to change the PC? */ | |
3036 | if (cris_get_operand2 (inst) == REG_PC) | |
3037 | { | |
3038 | /* It's invalid to change the PC in a delay slot. */ | |
3039 | if (inst_env->slot_needed) | |
3040 | { | |
3041 | inst_env->invalid = 1; | |
3042 | return; | |
3043 | } | |
3044 | inst_env->reg[REG_PC] = | |
3045 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
e17a4113 | 3046 | 4, inst_env->byte_order); |
29134980 OF |
3047 | } |
3048 | /* The increment is not depending on the size, instead it's depending | |
3049 | on the number of registers loaded from memory. */ | |
0963b4bd MS |
3050 | if ((cris_get_operand1 (inst) == REG_PC) |
3051 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3052 | { |
3053 | /* It's invalid to change the PC in a delay slot. */ | |
3054 | if (inst_env->slot_needed) | |
3055 | { | |
3056 | inst_env->invalid = 1; | |
3057 | return; | |
3058 | } | |
3059 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3060 | } | |
3061 | } | |
3062 | inst_env->slot_needed = 0; | |
3063 | inst_env->prefix_found = 0; | |
3064 | inst_env->xflag_found = 0; | |
3065 | inst_env->disable_interrupt = 0; | |
3066 | } | |
3067 | ||
3068 | /* Handles the MOVEM to memory from general register instruction. */ | |
3069 | ||
a78f21af | 3070 | static void |
29134980 OF |
3071 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3072 | { | |
3073 | if (inst_env->prefix_found) | |
3074 | { | |
3075 | /* The assign value is the value after the increment. Normally, the | |
3076 | assign value is the value before the increment. */ | |
5aafa1cc PM |
3077 | if ((cris_get_operand1 (inst) == REG_PC) |
3078 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
29134980 OF |
3079 | { |
3080 | /* The prefix handles the problem if we are in a delay slot. */ | |
3081 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3082 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3083 | } | |
3084 | } | |
3085 | else | |
3086 | { | |
3087 | /* The increment is not depending on the size, instead it's depending | |
3088 | on the number of registers loaded to memory. */ | |
0963b4bd MS |
3089 | if ((cris_get_operand1 (inst) == REG_PC) |
3090 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3091 | { |
3092 | /* It's invalid to change the PC in a delay slot. */ | |
3093 | if (inst_env->slot_needed) | |
3094 | { | |
3095 | inst_env->invalid = 1; | |
3096 | return; | |
3097 | } | |
3098 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3099 | } | |
3100 | } | |
3101 | inst_env->slot_needed = 0; | |
3102 | inst_env->prefix_found = 0; | |
3103 | inst_env->xflag_found = 0; | |
3104 | inst_env->disable_interrupt = 0; | |
3105 | } | |
3106 | ||
29134980 OF |
3107 | /* Handles the intructions that's not yet implemented, by setting |
3108 | inst_env->invalid to true. */ | |
3109 | ||
a78f21af | 3110 | static void |
29134980 OF |
3111 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3112 | { | |
3113 | inst_env->invalid = 1; | |
3114 | } | |
3115 | ||
3116 | /* Handles the XOR instruction. */ | |
3117 | ||
a78f21af | 3118 | static void |
29134980 OF |
3119 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3120 | { | |
3121 | /* XOR can't have a prefix. */ | |
3122 | if (inst_env->prefix_found) | |
3123 | { | |
3124 | inst_env->invalid = 1; | |
3125 | return; | |
3126 | } | |
3127 | ||
3128 | /* Check if the PC is the target. */ | |
3129 | if (cris_get_operand2 (inst) == REG_PC) | |
3130 | { | |
3131 | /* It's invalid to change the PC in a delay slot. */ | |
3132 | if (inst_env->slot_needed) | |
3133 | { | |
3134 | inst_env->invalid = 1; | |
3135 | return; | |
3136 | } | |
3137 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3138 | } | |
3139 | inst_env->slot_needed = 0; | |
3140 | inst_env->prefix_found = 0; | |
3141 | inst_env->xflag_found = 0; | |
3142 | inst_env->disable_interrupt = 0; | |
3143 | } | |
3144 | ||
3145 | /* Handles the MULS instruction. */ | |
3146 | ||
a78f21af | 3147 | static void |
29134980 OF |
3148 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3149 | { | |
3150 | /* MULS/U can't have a prefix. */ | |
3151 | if (inst_env->prefix_found) | |
3152 | { | |
3153 | inst_env->invalid = 1; | |
3154 | return; | |
3155 | } | |
3156 | ||
3157 | /* Consider it invalid if the PC is the target. */ | |
3158 | if (cris_get_operand2 (inst) == REG_PC) | |
3159 | { | |
3160 | inst_env->invalid = 1; | |
3161 | return; | |
3162 | } | |
3163 | inst_env->slot_needed = 0; | |
3164 | inst_env->prefix_found = 0; | |
3165 | inst_env->xflag_found = 0; | |
3166 | inst_env->disable_interrupt = 0; | |
3167 | } | |
3168 | ||
3169 | /* Handles the MULU instruction. */ | |
3170 | ||
a78f21af | 3171 | static void |
29134980 OF |
3172 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3173 | { | |
3174 | /* MULS/U can't have a prefix. */ | |
3175 | if (inst_env->prefix_found) | |
3176 | { | |
3177 | inst_env->invalid = 1; | |
3178 | return; | |
3179 | } | |
3180 | ||
3181 | /* Consider it invalid if the PC is the target. */ | |
3182 | if (cris_get_operand2 (inst) == REG_PC) | |
3183 | { | |
3184 | inst_env->invalid = 1; | |
3185 | return; | |
3186 | } | |
3187 | inst_env->slot_needed = 0; | |
3188 | inst_env->prefix_found = 0; | |
3189 | inst_env->xflag_found = 0; | |
3190 | inst_env->disable_interrupt = 0; | |
3191 | } | |
3192 | ||
0963b4bd | 3193 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
29134980 OF |
3194 | The MOVE instruction is the move from source to register. */ |
3195 | ||
a78f21af | 3196 | static void |
29134980 OF |
3197 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3198 | unsigned long source1, unsigned long source2) | |
3199 | { | |
3200 | unsigned long pc_mask; | |
3201 | unsigned long operation_mask; | |
3202 | ||
3203 | /* Find out how many bits the operation should apply to. */ | |
3204 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3205 | { | |
3206 | pc_mask = 0xFFFFFF00; | |
3207 | operation_mask = 0xFF; | |
3208 | } | |
3209 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3210 | { | |
3211 | pc_mask = 0xFFFF0000; | |
3212 | operation_mask = 0xFFFF; | |
3213 | } | |
3214 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3215 | { | |
3216 | pc_mask = 0x0; | |
3217 | operation_mask = 0xFFFFFFFF; | |
3218 | } | |
3219 | else | |
3220 | { | |
3221 | /* The size is out of range. */ | |
3222 | inst_env->invalid = 1; | |
3223 | return; | |
3224 | } | |
3225 | ||
3226 | /* The instruction just works on uw_operation_mask bits. */ | |
3227 | source2 &= operation_mask; | |
3228 | source1 &= operation_mask; | |
3229 | ||
3230 | /* Now calculate the result. The opcode's 3 first bits separates | |
3231 | the different actions. */ | |
3232 | switch (cris_get_opcode (inst) & 7) | |
3233 | { | |
3234 | case 0: /* add */ | |
3235 | source1 += source2; | |
3236 | break; | |
3237 | ||
3238 | case 1: /* move */ | |
3239 | source1 = source2; | |
3240 | break; | |
3241 | ||
3242 | case 2: /* subtract */ | |
3243 | source1 -= source2; | |
3244 | break; | |
3245 | ||
3246 | case 3: /* compare */ | |
3247 | break; | |
3248 | ||
3249 | case 4: /* and */ | |
3250 | source1 &= source2; | |
3251 | break; | |
3252 | ||
3253 | case 5: /* or */ | |
3254 | source1 |= source2; | |
3255 | break; | |
3256 | ||
3257 | default: | |
3258 | inst_env->invalid = 1; | |
3259 | return; | |
3260 | ||
3261 | break; | |
3262 | } | |
3263 | ||
3264 | /* Make sure that the result doesn't contain more than the instruction | |
3265 | size bits. */ | |
3266 | source2 &= operation_mask; | |
3267 | ||
3268 | /* Calculate the new breakpoint address. */ | |
3269 | inst_env->reg[REG_PC] &= pc_mask; | |
3270 | inst_env->reg[REG_PC] |= source1; | |
3271 | ||
3272 | } | |
3273 | ||
3274 | /* Extends the value from either byte or word size to a dword. If the mode | |
3275 | is zero extend then the value is extended with zero. If instead the mode | |
3276 | is signed extend the sign bit of the value is taken into consideration. */ | |
3277 | ||
a78f21af | 3278 | static unsigned long |
29134980 OF |
3279 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3280 | { | |
3281 | /* The size can be either byte or word, check which one it is. | |
3282 | Don't check the highest bit, it's indicating if it's a zero | |
3283 | or sign extend. */ | |
3284 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3285 | { | |
3286 | /* Word size. */ | |
3287 | value &= 0xFFFF; | |
3288 | ||
3289 | /* Check if the instruction is signed extend. If so, check if value has | |
3290 | the sign bit on. */ | |
3291 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3292 | { | |
3293 | value |= SIGNED_WORD_EXTEND_MASK; | |
3294 | } | |
3295 | } | |
3296 | else | |
3297 | { | |
3298 | /* Byte size. */ | |
3299 | value &= 0xFF; | |
3300 | ||
3301 | /* Check if the instruction is signed extend. If so, check if value has | |
3302 | the sign bit on. */ | |
3303 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3304 | { | |
3305 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3306 | } | |
3307 | } | |
3308 | /* The size should now be dword. */ | |
3309 | cris_set_size_to_dword (inst); | |
3310 | return value; | |
3311 | } | |
3312 | ||
3313 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3314 | instruction. The MOVE instruction is the move from source to register. */ | |
3315 | ||
a78f21af | 3316 | static void |
29134980 OF |
3317 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3318 | inst_env_type *inst_env) | |
3319 | { | |
3320 | unsigned long operand1; | |
3321 | unsigned long operand2; | |
3322 | ||
3323 | /* It's invalid to have a prefix to the instruction. This is a register | |
3324 | mode instruction and can't have a prefix. */ | |
3325 | if (inst_env->prefix_found) | |
3326 | { | |
3327 | inst_env->invalid = 1; | |
3328 | return; | |
3329 | } | |
3330 | /* Check if the instruction has PC as its target. */ | |
3331 | if (cris_get_operand2 (inst) == REG_PC) | |
3332 | { | |
3333 | if (inst_env->slot_needed) | |
3334 | { | |
3335 | inst_env->invalid = 1; | |
3336 | return; | |
3337 | } | |
3338 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3339 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3340 | operand2 = inst_env->reg[REG_PC]; |
3341 | ||
3342 | /* Check if it's a extend, signed or zero instruction. */ | |
3343 | if (cris_get_opcode (inst) < 4) | |
3344 | { | |
3345 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3346 | } | |
3347 | /* Calculate the PC value after the instruction, i.e. where the | |
3348 | breakpoint should be. The order of the udw_operands is vital. */ | |
3349 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3350 | } | |
3351 | inst_env->slot_needed = 0; | |
3352 | inst_env->prefix_found = 0; | |
3353 | inst_env->xflag_found = 0; | |
3354 | inst_env->disable_interrupt = 0; | |
3355 | } | |
3356 | ||
3357 | /* Returns the data contained at address. The size of the data is derived from | |
3358 | the size of the operation. If the instruction is a zero or signed | |
3359 | extend instruction, the size field is changed in instruction. */ | |
3360 | ||
a78f21af | 3361 | static unsigned long |
0963b4bd MS |
3362 | get_data_from_address (unsigned short *inst, CORE_ADDR address, |
3363 | enum bfd_endian byte_order) | |
29134980 OF |
3364 | { |
3365 | int size = cris_get_size (*inst); | |
3366 | unsigned long value; | |
3367 | ||
3368 | /* If it's an extend instruction we don't want the signed extend bit, | |
3369 | because it influences the size. */ | |
3370 | if (cris_get_opcode (*inst) < 4) | |
3371 | { | |
3372 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3373 | } | |
3374 | /* Is there a need for checking the size? Size should contain the number of | |
3375 | bytes to read. */ | |
3376 | size = 1 << size; | |
e17a4113 | 3377 | value = read_memory_unsigned_integer (address, size, byte_order); |
29134980 OF |
3378 | |
3379 | /* Check if it's an extend, signed or zero instruction. */ | |
3380 | if (cris_get_opcode (*inst) < 4) | |
3381 | { | |
3382 | value = do_sign_or_zero_extend (value, inst); | |
3383 | } | |
3384 | return value; | |
3385 | } | |
3386 | ||
3387 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3388 | instructions. The MOVE instruction is the move from source to register. */ | |
3389 | ||
a78f21af | 3390 | static void |
29134980 OF |
3391 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3392 | inst_env_type *inst_env) | |
3393 | { | |
3394 | unsigned long operand2; | |
3395 | unsigned long operand3; | |
3396 | ||
3397 | check_assign (inst, inst_env); | |
3398 | if (cris_get_operand2 (inst) == REG_PC) | |
3399 | { | |
3400 | operand2 = inst_env->reg[REG_PC]; | |
3401 | ||
3402 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3403 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3404 | inst_env->byte_order); | |
29134980 OF |
3405 | |
3406 | /* Calculate the PC value after the instruction, i.e. where the | |
3407 | breakpoint should be. The order of the udw_operands is vital. */ | |
3408 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3409 | } | |
3410 | inst_env->slot_needed = 0; | |
3411 | inst_env->prefix_found = 0; | |
3412 | inst_env->xflag_found = 0; | |
3413 | inst_env->disable_interrupt = 0; | |
3414 | } | |
3415 | ||
3416 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3417 | OR instructions. Note that for this to work as expected, the calling | |
3418 | function must have made sure that there is a prefix to this instruction. */ | |
3419 | ||
a78f21af | 3420 | static void |
29134980 OF |
3421 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3422 | inst_env_type *inst_env) | |
3423 | { | |
3424 | unsigned long operand2; | |
3425 | unsigned long operand3; | |
3426 | ||
3427 | if (cris_get_operand1 (inst) == REG_PC) | |
3428 | { | |
3429 | /* The PC will be changed by the instruction. */ | |
3430 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3431 | ||
3432 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3433 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3434 | inst_env->byte_order); | |
29134980 OF |
3435 | |
3436 | /* Calculate the PC value after the instruction, i.e. where the | |
3437 | breakpoint should be. */ | |
3438 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3439 | } | |
3440 | inst_env->slot_needed = 0; | |
3441 | inst_env->prefix_found = 0; | |
3442 | inst_env->xflag_found = 0; | |
3443 | inst_env->disable_interrupt = 0; | |
3444 | } | |
3445 | ||
3446 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3447 | instructions. The MOVE instruction is the move from source to register. */ | |
3448 | ||
a78f21af | 3449 | static void |
29134980 OF |
3450 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3451 | inst_env_type *inst_env) | |
3452 | { | |
3453 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3454 | { | |
3455 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3456 | SUB, AND or OR something weird is going on (if everything works these | |
3457 | instructions should end up in the three operand version). */ | |
3458 | inst_env->invalid = 1; | |
3459 | return; | |
3460 | } | |
3461 | else | |
3462 | { | |
3463 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3464 | so use it. */ | |
3465 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3466 | } | |
3467 | inst_env->slot_needed = 0; | |
3468 | inst_env->prefix_found = 0; | |
3469 | inst_env->xflag_found = 0; | |
3470 | inst_env->disable_interrupt = 0; | |
3471 | } | |
3472 | ||
3473 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3474 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3475 | source to register. */ | |
3476 | ||
a78f21af | 3477 | static void |
29134980 OF |
3478 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3479 | inst_env_type *inst_env) | |
3480 | { | |
3481 | unsigned long operand1; | |
3482 | unsigned long operand2; | |
3483 | unsigned long operand3; | |
3484 | int size; | |
3485 | ||
0963b4bd | 3486 | /* The instruction is either an indirect or autoincrement addressing mode. |
29134980 OF |
3487 | Check if the destination register is the PC. */ |
3488 | if (cris_get_operand2 (inst) == REG_PC) | |
3489 | { | |
3490 | /* Must be done here, get_data_from_address may change the size | |
3491 | field. */ | |
3492 | size = cris_get_size (inst); | |
3493 | operand2 = inst_env->reg[REG_PC]; | |
3494 | ||
3495 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3496 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 | 3497 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
29134980 OF |
3498 | |
3499 | /* Calculate the PC value after the instruction, i.e. where the | |
3500 | breakpoint should be. The order of the udw_operands is vital. */ | |
3501 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3502 | } | |
3503 | /* If this is an autoincrement addressing mode, check if the increment | |
3504 | changes the PC. */ | |
0963b4bd MS |
3505 | if ((cris_get_operand1 (inst) == REG_PC) |
3506 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3507 | { |
3508 | /* Get the size field. */ | |
3509 | size = cris_get_size (inst); | |
3510 | ||
3511 | /* If it's an extend instruction we don't want the signed extend bit, | |
3512 | because it influences the size. */ | |
3513 | if (cris_get_opcode (inst) < 4) | |
3514 | { | |
3515 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3516 | } | |
3517 | process_autoincrement (size, inst, inst_env); | |
3518 | } | |
3519 | inst_env->slot_needed = 0; | |
3520 | inst_env->prefix_found = 0; | |
3521 | inst_env->xflag_found = 0; | |
3522 | inst_env->disable_interrupt = 0; | |
3523 | } | |
3524 | ||
3525 | /* Handles the two-operand addressing mode, all modes except register, for | |
3526 | the ADD, SUB CMP, AND and OR instruction. */ | |
3527 | ||
a78f21af | 3528 | static void |
29134980 OF |
3529 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3530 | inst_env_type *inst_env) | |
3531 | { | |
3532 | if (inst_env->prefix_found) | |
3533 | { | |
3534 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3535 | { | |
3536 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3537 | } | |
3538 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3539 | { | |
3540 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3541 | } | |
3542 | else | |
3543 | { | |
3544 | /* The mode is invalid for a prefixed base instruction. */ | |
3545 | inst_env->invalid = 1; | |
3546 | return; | |
3547 | } | |
3548 | } | |
3549 | else | |
3550 | { | |
3551 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3552 | } | |
3553 | } | |
3554 | ||
3555 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3556 | ||
a78f21af | 3557 | static void |
29134980 OF |
3558 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3559 | { | |
3560 | unsigned long operand1; | |
3561 | unsigned long operand2; | |
3562 | ||
3563 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3564 | instruction and can't have a prefix. */ | |
3565 | if (inst_env->prefix_found) | |
3566 | { | |
3567 | inst_env->invalid = 1; | |
3568 | return; | |
3569 | } | |
3570 | ||
3571 | /* Check if the instruction has PC as its target. */ | |
3572 | if (cris_get_operand2 (inst) == REG_PC) | |
3573 | { | |
3574 | if (inst_env->slot_needed) | |
3575 | { | |
3576 | inst_env->invalid = 1; | |
3577 | return; | |
3578 | } | |
3579 | operand1 = cris_get_quick_value (inst); | |
3580 | operand2 = inst_env->reg[REG_PC]; | |
3581 | ||
3582 | /* The size should now be dword. */ | |
3583 | cris_set_size_to_dword (&inst); | |
3584 | ||
3585 | /* Calculate the PC value after the instruction, i.e. where the | |
3586 | breakpoint should be. */ | |
3587 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3588 | } | |
3589 | inst_env->slot_needed = 0; | |
3590 | inst_env->prefix_found = 0; | |
3591 | inst_env->xflag_found = 0; | |
3592 | inst_env->disable_interrupt = 0; | |
3593 | } | |
3594 | ||
3595 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3596 | ||
a78f21af | 3597 | static void |
29134980 OF |
3598 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3599 | { | |
3600 | unsigned long operand1; | |
3601 | unsigned long operand2; | |
3602 | ||
3603 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3604 | instruction and can't have a prefix. */ | |
3605 | if (inst_env->prefix_found) | |
3606 | { | |
3607 | inst_env->invalid = 1; | |
3608 | return; | |
3609 | } | |
3610 | /* Check if the instruction has PC as its target. */ | |
3611 | if (cris_get_operand2 (inst) == REG_PC) | |
3612 | { | |
3613 | if (inst_env->slot_needed) | |
3614 | { | |
3615 | inst_env->invalid = 1; | |
3616 | return; | |
3617 | } | |
3618 | /* The instruction has the PC as its target register. */ | |
3619 | operand1 = cris_get_quick_value (inst); | |
3620 | operand2 = inst_env->reg[REG_PC]; | |
3621 | ||
3622 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3623 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3624 | { | |
3625 | /* sign extend */ | |
3626 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3627 | } | |
3628 | /* The size should now be dword. */ | |
3629 | cris_set_size_to_dword (&inst); | |
3630 | ||
3631 | /* Calculate the PC value after the instruction, i.e. where the | |
3632 | breakpoint should be. */ | |
3633 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3634 | } | |
3635 | inst_env->slot_needed = 0; | |
3636 | inst_env->prefix_found = 0; | |
3637 | inst_env->xflag_found = 0; | |
3638 | inst_env->disable_interrupt = 0; | |
3639 | } | |
3640 | ||
3641 | /* Translate op_type to a function and call it. */ | |
3642 | ||
a78f21af | 3643 | static void |
be8626e0 MD |
3644 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
3645 | unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
3646 | { |
3647 | switch (op_type) | |
3648 | { | |
3649 | case cris_not_implemented_op: | |
3650 | not_implemented_op (inst, inst_env); | |
3651 | break; | |
3652 | ||
3653 | case cris_abs_op: | |
3654 | abs_op (inst, inst_env); | |
3655 | break; | |
3656 | ||
3657 | case cris_addi_op: | |
3658 | addi_op (inst, inst_env); | |
3659 | break; | |
3660 | ||
3661 | case cris_asr_op: | |
3662 | asr_op (inst, inst_env); | |
3663 | break; | |
3664 | ||
3665 | case cris_asrq_op: | |
3666 | asrq_op (inst, inst_env); | |
3667 | break; | |
3668 | ||
3669 | case cris_ax_ei_setf_op: | |
3670 | ax_ei_setf_op (inst, inst_env); | |
3671 | break; | |
3672 | ||
3673 | case cris_bdap_prefix: | |
3674 | bdap_prefix (inst, inst_env); | |
3675 | break; | |
3676 | ||
3677 | case cris_biap_prefix: | |
3678 | biap_prefix (inst, inst_env); | |
3679 | break; | |
3680 | ||
3681 | case cris_break_op: | |
3682 | break_op (inst, inst_env); | |
3683 | break; | |
3684 | ||
3685 | case cris_btst_nop_op: | |
3686 | btst_nop_op (inst, inst_env); | |
3687 | break; | |
3688 | ||
3689 | case cris_clearf_di_op: | |
3690 | clearf_di_op (inst, inst_env); | |
3691 | break; | |
3692 | ||
3693 | case cris_dip_prefix: | |
3694 | dip_prefix (inst, inst_env); | |
3695 | break; | |
3696 | ||
3697 | case cris_dstep_logshift_mstep_neg_not_op: | |
3698 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3699 | break; | |
3700 | ||
3701 | case cris_eight_bit_offset_branch_op: | |
3702 | eight_bit_offset_branch_op (inst, inst_env); | |
3703 | break; | |
3704 | ||
3705 | case cris_move_mem_to_reg_movem_op: | |
3706 | move_mem_to_reg_movem_op (inst, inst_env); | |
3707 | break; | |
3708 | ||
3709 | case cris_move_reg_to_mem_movem_op: | |
3710 | move_reg_to_mem_movem_op (inst, inst_env); | |
3711 | break; | |
3712 | ||
3713 | case cris_move_to_preg_op: | |
be8626e0 | 3714 | move_to_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3715 | break; |
3716 | ||
3717 | case cris_muls_op: | |
3718 | muls_op (inst, inst_env); | |
3719 | break; | |
3720 | ||
3721 | case cris_mulu_op: | |
3722 | mulu_op (inst, inst_env); | |
3723 | break; | |
3724 | ||
3725 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3726 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3727 | break; | |
3728 | ||
3729 | case cris_none_reg_mode_clear_test_op: | |
3730 | none_reg_mode_clear_test_op (inst, inst_env); | |
3731 | break; | |
3732 | ||
3733 | case cris_none_reg_mode_jump_op: | |
3734 | none_reg_mode_jump_op (inst, inst_env); | |
3735 | break; | |
3736 | ||
3737 | case cris_none_reg_mode_move_from_preg_op: | |
be8626e0 | 3738 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3739 | break; |
3740 | ||
3741 | case cris_quick_mode_add_sub_op: | |
3742 | quick_mode_add_sub_op (inst, inst_env); | |
3743 | break; | |
3744 | ||
3745 | case cris_quick_mode_and_cmp_move_or_op: | |
3746 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3747 | break; | |
3748 | ||
3749 | case cris_quick_mode_bdap_prefix: | |
3750 | quick_mode_bdap_prefix (inst, inst_env); | |
3751 | break; | |
3752 | ||
3753 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3754 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3755 | break; | |
3756 | ||
3757 | case cris_reg_mode_clear_op: | |
3758 | reg_mode_clear_op (inst, inst_env); | |
3759 | break; | |
3760 | ||
3761 | case cris_reg_mode_jump_op: | |
3762 | reg_mode_jump_op (inst, inst_env); | |
3763 | break; | |
3764 | ||
3765 | case cris_reg_mode_move_from_preg_op: | |
3766 | reg_mode_move_from_preg_op (inst, inst_env); | |
3767 | break; | |
3768 | ||
3769 | case cris_reg_mode_test_op: | |
3770 | reg_mode_test_op (inst, inst_env); | |
3771 | break; | |
3772 | ||
3773 | case cris_scc_op: | |
3774 | scc_op (inst, inst_env); | |
3775 | break; | |
3776 | ||
3777 | case cris_sixteen_bit_offset_branch_op: | |
3778 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3779 | break; | |
3780 | ||
3781 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3782 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3783 | break; | |
3784 | ||
3785 | case cris_three_operand_bound_op: | |
3786 | three_operand_bound_op (inst, inst_env); | |
3787 | break; | |
3788 | ||
3789 | case cris_two_operand_bound_op: | |
3790 | two_operand_bound_op (inst, inst_env); | |
3791 | break; | |
3792 | ||
3793 | case cris_xor_op: | |
3794 | xor_op (inst, inst_env); | |
3795 | break; | |
3796 | } | |
3797 | } | |
3798 | ||
3799 | /* This wrapper is to avoid cris_get_assembler being called before | |
3800 | exec_bfd has been set. */ | |
3801 | ||
3802 | static int | |
a89aa300 | 3803 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3804 | { |
a89aa300 | 3805 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3806 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3807 | disassembler, even when there is no BFD. Does something like | |
3808 | "gdb; target remote; disassmeble *0x123" work? */ | |
3809 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3810 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3811 | gdb_assert (print_insn != NULL); |
3812 | return print_insn (addr, info); | |
29134980 OF |
3813 | } |
3814 | ||
18b3c2f5 RW |
3815 | /* Originally from <asm/elf.h>. */ |
3816 | typedef unsigned char cris_elf_greg_t[4]; | |
dbbff683 OF |
3817 | |
3818 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 | 3819 | #define CRISV10_ELF_NGREG 35 |
18b3c2f5 | 3820 | typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG]; |
c600d464 OF |
3821 | |
3822 | #define CRISV32_ELF_NGREG 32 | |
18b3c2f5 | 3823 | typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; |
dbbff683 | 3824 | |
18b3c2f5 | 3825 | /* Unpack a cris_elf_gregset_t into GDB's register cache. */ |
dbbff683 | 3826 | |
a78f21af | 3827 | static void |
18b3c2f5 | 3828 | cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp) |
dbbff683 | 3829 | { |
7fbe2eba UW |
3830 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3831 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
dbbff683 | 3832 | int i; |
18b3c2f5 | 3833 | cris_elf_greg_t *regp = *gregsetp; |
dbbff683 OF |
3834 | |
3835 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3836 | knows about the actual size of each register so that's no problem. */ | |
3837 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3838 | { | |
c6b4e5a2 | 3839 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
dbbff683 | 3840 | } |
c600d464 OF |
3841 | |
3842 | if (tdep->cris_version == 32) | |
3843 | { | |
3844 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3845 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3846 | be wrong. Issue a warning to alert the user. */ | |
7fbe2eba | 3847 | regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch), |
c600d464 OF |
3848 | (char *)®p[ERP_REGNUM]); |
3849 | ||
3850 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3851 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3852 | } | |
dbbff683 OF |
3853 | } |
3854 | ||
3855 | /* Use a local version of this function to get the correct types for | |
3856 | regsets, until multi-arch core support is ready. */ | |
3857 | ||
3858 | static void | |
9eefc95f UW |
3859 | fetch_core_registers (struct regcache *regcache, |
3860 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3861 | int which, CORE_ADDR reg_addr) |
3862 | { | |
18b3c2f5 | 3863 | cris_elf_gregset_t gregset; |
dbbff683 OF |
3864 | |
3865 | switch (which) | |
3866 | { | |
3867 | case 0: | |
18b3c2f5 | 3868 | if (core_reg_size != sizeof (cris_elf_gregset_t) |
c600d464 | 3869 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) |
dbbff683 | 3870 | { |
8a3fe4f8 | 3871 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3872 | } |
3873 | else | |
3874 | { | |
3875 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3876 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3877 | } |
3878 | ||
3879 | default: | |
3880 | /* We've covered all the kinds of registers we know about here, | |
3881 | so this must be something we wouldn't know what to do with | |
3882 | anyway. Just ignore it. */ | |
3883 | break; | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | static struct core_fns cris_elf_core_fns = | |
3888 | { | |
3889 | bfd_target_elf_flavour, /* core_flavour */ | |
3890 | default_check_format, /* check_format */ | |
3891 | default_core_sniffer, /* core_sniffer */ | |
3892 | fetch_core_registers, /* core_read_registers */ | |
3893 | NULL /* next */ | |
3894 | }; | |
3895 | ||
a78f21af AC |
3896 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3897 | ||
29134980 OF |
3898 | void |
3899 | _initialize_cris_tdep (void) | |
3900 | { | |
3901 | struct cmd_list_element *c; | |
3902 | ||
3903 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3904 | ||
29134980 | 3905 | /* CRIS-specific user-commands. */ |
addb4faf PA |
3906 | add_setshow_zuinteger_cmd ("cris-version", class_support, |
3907 | &usr_cmd_cris_version, | |
3908 | _("Set the current CRIS version."), | |
3909 | _("Show the current CRIS version."), | |
3910 | _("\ | |
bdd56253 OF |
3911 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ |
3912 | Defaults to 10. "), | |
addb4faf PA |
3913 | set_cris_version, |
3914 | NULL, /* FIXME: i18n: Current CRIS version | |
3915 | is %s. */ | |
3916 | &setlist, &showlist); | |
0e6bdb31 OF |
3917 | |
3918 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3919 | cris_modes, &usr_cmd_cris_mode, | |
3920 | _("Set the current CRIS mode."), | |
3921 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3922 | _("\ |
3923 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3924 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3925 | set_cris_mode, |
3926 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3927 | &setlist, &showlist); | |
dbbff683 | 3928 | |
a5f6c8f5 OF |
3929 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3930 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3931 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3932 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3933 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3934 | set_cris_dwarf2_cfi, |
0963b4bd MS |
3935 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI |
3936 | for CRIS is %d. */ | |
a5f6c8f5 OF |
3937 | &setlist, &showlist); |
3938 | ||
52bd1401 | 3939 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3940 | } |
3941 | ||
3942 | /* Prints out all target specific values. */ | |
3943 | ||
3944 | static void | |
3945 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3946 | { | |
7fbe2eba | 3947 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29134980 OF |
3948 | if (tdep != NULL) |
3949 | { | |
3950 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3951 | tdep->cris_version); | |
0e6bdb31 OF |
3952 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
3953 | tdep->cris_mode); | |
a5f6c8f5 OF |
3954 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
3955 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3956 | } |
3957 | } | |
3958 | ||
3959 | static void | |
a5f6c8f5 OF |
3960 | set_cris_version (char *ignore_args, int from_tty, |
3961 | struct cmd_list_element *c) | |
29134980 OF |
3962 | { |
3963 | struct gdbarch_info info; | |
3964 | ||
a5f6c8f5 | 3965 | usr_cmd_cris_version_valid = 1; |
29134980 | 3966 | |
a5f6c8f5 OF |
3967 | /* Update the current architecture, if needed. */ |
3968 | gdbarch_info_init (&info); | |
3969 | if (!gdbarch_update_p (info)) | |
3970 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 3971 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3972 | } |
3973 | ||
0e6bdb31 OF |
3974 | static void |
3975 | set_cris_mode (char *ignore_args, int from_tty, | |
3976 | struct cmd_list_element *c) | |
3977 | { | |
3978 | struct gdbarch_info info; | |
3979 | ||
3980 | /* Update the current architecture, if needed. */ | |
3981 | gdbarch_info_init (&info); | |
3982 | if (!gdbarch_update_p (info)) | |
3983 | internal_error (__FILE__, __LINE__, | |
3984 | "cris_gdbarch_update: failed to update architecture."); | |
3985 | } | |
3986 | ||
29134980 | 3987 | static void |
a5f6c8f5 OF |
3988 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
3989 | struct cmd_list_element *c) | |
29134980 OF |
3990 | { |
3991 | struct gdbarch_info info; | |
a5f6c8f5 OF |
3992 | |
3993 | /* Update the current architecture, if needed. */ | |
3994 | gdbarch_info_init (&info); | |
3995 | if (!gdbarch_update_p (info)) | |
3996 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 3997 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3998 | } |
3999 | ||
29134980 OF |
4000 | static struct gdbarch * |
4001 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4002 | { | |
4003 | struct gdbarch *gdbarch; | |
4004 | struct gdbarch_tdep *tdep; | |
e4286e57 | 4005 | unsigned int cris_version; |
29134980 OF |
4006 | |
4007 | if (usr_cmd_cris_version_valid) | |
4008 | { | |
4009 | /* Trust the user's CRIS version setting. */ | |
4010 | cris_version = usr_cmd_cris_version; | |
4011 | } | |
c600d464 OF |
4012 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4013 | { | |
4014 | cris_version = 32; | |
4015 | } | |
29134980 OF |
4016 | else |
4017 | { | |
4018 | /* Assume it's CRIS version 10. */ | |
4019 | cris_version = 10; | |
4020 | } | |
4021 | ||
29134980 OF |
4022 | /* Make the current settings visible to the user. */ |
4023 | usr_cmd_cris_version = cris_version; | |
29134980 | 4024 | |
0e6bdb31 | 4025 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4026 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4027 | arches != NULL; | |
4028 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4029 | { | |
a5f6c8f5 OF |
4030 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4031 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4032 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4033 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4034 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4035 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4036 | return arches->gdbarch; |
4037 | } | |
4038 | ||
4039 | /* No matching architecture was found. Create a new one. */ | |
4040 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4041 | gdbarch = gdbarch_alloc (&info, tdep); | |
4042 | ||
a5f6c8f5 | 4043 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4044 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4045 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4046 | |
4047 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4048 | switch (info.byte_order) | |
4049 | { | |
778eb05e | 4050 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4051 | /* Ok. */ |
4052 | break; | |
4053 | ||
d7449b42 | 4054 | case BFD_ENDIAN_BIG: |
0963b4bd MS |
4055 | internal_error (__FILE__, __LINE__, |
4056 | _("cris_gdbarch_init: big endian byte order in info")); | |
29134980 OF |
4057 | break; |
4058 | ||
4059 | default: | |
0963b4bd MS |
4060 | internal_error (__FILE__, __LINE__, |
4061 | _("cris_gdbarch_init: unknown byte order in info")); | |
29134980 OF |
4062 | } |
4063 | ||
b4206d25 | 4064 | set_gdbarch_return_value (gdbarch, cris_return_value); |
29134980 | 4065 | |
29134980 | 4066 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4067 | |
4068 | /* Length of ordinary registers used in push_word and a few other | |
4069 | places. register_size() is the real way to know how big a | |
4070 | register is. */ | |
a5f6c8f5 | 4071 | |
2e4b5889 | 4072 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 4073 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 4074 | which means we have to set this explicitly. */ |
c600d464 | 4075 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4076 | |
29134980 OF |
4077 | /* The total amount of space needed to store (in an array called registers) |
4078 | GDB's copy of the machine's register state. Note: We can not use | |
d93859e2 | 4079 | cris_register_size at this point, since it relies on gdbarch |
29134980 OF |
4080 | being set. */ |
4081 | switch (tdep->cris_version) | |
4082 | { | |
4083 | case 0: | |
4084 | case 1: | |
4085 | case 2: | |
4086 | case 3: | |
29134980 OF |
4087 | case 8: |
4088 | case 9: | |
a5f6c8f5 OF |
4089 | /* Old versions; not supported. */ |
4090 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4091 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4092 | break; |
4093 | ||
4094 | case 10: | |
4095 | case 11: | |
4096 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4097 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4098 | set_gdbarch_pc_regnum (gdbarch, 15); |
4099 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4100 | /* There are 32 registers (some of which may not be implemented). */ | |
4101 | set_gdbarch_num_regs (gdbarch, 32); | |
4102 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4103 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4104 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4105 | ||
4106 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4107 | break; | |
4108 | ||
4109 | case 32: | |
4110 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4111 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4112 | and pseudo-register PC (32 bits). */ | |
4113 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4114 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4115 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4116 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4117 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4118 | ||
4119 | set_gdbarch_cannot_store_register | |
4120 | (gdbarch, crisv32_cannot_store_register); | |
4121 | set_gdbarch_cannot_fetch_register | |
4122 | (gdbarch, crisv32_cannot_fetch_register); | |
4123 | ||
4124 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4125 | ||
4126 | set_gdbarch_single_step_through_delay | |
4127 | (gdbarch, crisv32_single_step_through_delay); | |
4128 | ||
29134980 OF |
4129 | break; |
4130 | ||
4131 | default: | |
c600d464 | 4132 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4133 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4134 | } |
4135 | ||
c600d464 OF |
4136 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4137 | have the same ABI). */ | |
2e4b5889 OF |
4138 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4139 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4140 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4141 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4142 | |
4143 | /* The stack grows downward. */ | |
4144 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4145 | ||
4146 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4147 | ||
2e4b5889 OF |
4148 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4149 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
94afd7a6 | 4150 | set_gdbarch_dummy_id (gdbarch, cris_dummy_id); |
2e4b5889 | 4151 | |
a5f6c8f5 OF |
4152 | if (tdep->cris_dwarf2_cfi == 1) |
4153 | { | |
4154 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4155 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4156 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
94afd7a6 | 4157 | dwarf2_append_unwinders (gdbarch); |
a5f6c8f5 OF |
4158 | } |
4159 | ||
0e6bdb31 OF |
4160 | if (tdep->cris_mode != cris_mode_guru) |
4161 | { | |
94afd7a6 | 4162 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
0e6bdb31 | 4163 | } |
a5f6c8f5 | 4164 | |
94afd7a6 | 4165 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
2e4b5889 | 4166 | frame_base_set_default (gdbarch, &cris_frame_base); |
6c0e89ed | 4167 | |
749c8b38 RW |
4168 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4169 | gdbarch_init_osabi (info, gdbarch); | |
4170 | ||
36482093 AC |
4171 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4172 | disassembler, even when there is no BFD. Does something like | |
4173 | "gdb; target remote; disassmeble *0x123" work? */ | |
4174 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4175 | ||
29134980 OF |
4176 | return gdbarch; |
4177 | } |