Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
d9fcf2fb | 2 | Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc. |
c906108c | 3 | |
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "obstack.h" | |
26 | #include "symtab.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdb_string.h" | |
31 | #include "value.h" | |
32 | #include "inferior.h" | |
c5aa993b | 33 | #include "dis-asm.h" |
c906108c SS |
34 | #include "symfile.h" |
35 | #include "objfiles.h" | |
104c1213 | 36 | #include "language.h" |
28d069e6 | 37 | #include "arch-utils.h" |
c906108c | 38 | |
f0d4cc9e | 39 | #include "floatformat.h" |
4ce44c66 JM |
40 | #include "sim-d10v.h" |
41 | ||
42 | #undef XMALLOC | |
43 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
44 | ||
cce74817 | 45 | struct frame_extra_info |
c5aa993b JM |
46 | { |
47 | CORE_ADDR return_pc; | |
48 | int frameless; | |
49 | int size; | |
50 | }; | |
cce74817 | 51 | |
4ce44c66 JM |
52 | struct gdbarch_tdep |
53 | { | |
54 | int a0_regnum; | |
55 | int nr_dmap_regs; | |
56 | unsigned long (*dmap_register) (int nr); | |
57 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
58 | }; |
59 | ||
60 | /* These are the addresses the D10V-EVA board maps data and | |
61 | instruction memory to. */ | |
cce74817 | 62 | |
cff3e48b | 63 | #define DMEM_START 0x2000000 |
cce74817 JM |
64 | #define IMEM_START 0x1000000 |
65 | #define STACK_START 0x0007ffe | |
66 | ||
4ce44c66 JM |
67 | /* d10v register names. */ |
68 | ||
69 | enum | |
70 | { | |
71 | R0_REGNUM = 0, | |
72 | LR_REGNUM = 13, | |
73 | PSW_REGNUM = 16, | |
74 | NR_IMAP_REGS = 2, | |
75 | NR_A_REGS = 2 | |
76 | }; | |
77 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
78 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
79 | ||
80 | /* d10v calling convention. */ | |
cce74817 JM |
81 | |
82 | #define ARG1_REGNUM R0_REGNUM | |
83 | #define ARGN_REGNUM 3 | |
84 | #define RET1_REGNUM R0_REGNUM | |
85 | ||
392a587b JM |
86 | /* Local functions */ |
87 | ||
a14ed312 | 88 | extern void _initialize_d10v_tdep (void); |
392a587b | 89 | |
a14ed312 | 90 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 91 | |
a14ed312 | 92 | static void d10v_eva_get_trace_data (void); |
c906108c | 93 | |
a14ed312 KB |
94 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
95 | CORE_ADDR addr); | |
cce74817 | 96 | |
a14ed312 | 97 | extern void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 98 | |
a14ed312 | 99 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 100 | |
c906108c | 101 | int |
72623009 | 102 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c SS |
103 | { |
104 | return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START); | |
105 | } | |
106 | ||
23964bcd | 107 | static CORE_ADDR |
489137c0 AC |
108 | d10v_stack_align (CORE_ADDR len) |
109 | { | |
110 | return (len + 1) & ~1; | |
111 | } | |
c906108c SS |
112 | |
113 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
114 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
115 | and TYPE is the type (which is known to be struct, union or array). | |
116 | ||
117 | The d10v returns anything less than 8 bytes in size in | |
118 | registers. */ | |
119 | ||
120 | int | |
fba45db2 | 121 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
122 | { |
123 | return (TYPE_LENGTH (type) > 8); | |
124 | } | |
125 | ||
126 | ||
392a587b | 127 | unsigned char * |
fba45db2 | 128 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 129 | { |
c5aa993b JM |
130 | static unsigned char breakpoint[] = |
131 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
132 | *lenptr = sizeof (breakpoint); |
133 | return breakpoint; | |
134 | } | |
135 | ||
4ce44c66 JM |
136 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
137 | when the reg_nr isn't valid. */ | |
138 | ||
139 | enum ts2_regnums | |
140 | { | |
141 | TS2_IMAP0_REGNUM = 32, | |
142 | TS2_DMAP_REGNUM = 34, | |
143 | TS2_NR_DMAP_REGS = 1, | |
144 | TS2_A0_REGNUM = 35 | |
145 | }; | |
146 | ||
147 | static char * | |
148 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 149 | { |
c5aa993b JM |
150 | static char *register_names[] = |
151 | { | |
152 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
153 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
154 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
155 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
156 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
157 | }; |
158 | if (reg_nr < 0) | |
159 | return NULL; | |
160 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
161 | return NULL; | |
c5aa993b | 162 | return register_names[reg_nr]; |
392a587b JM |
163 | } |
164 | ||
4ce44c66 JM |
165 | enum ts3_regnums |
166 | { | |
167 | TS3_IMAP0_REGNUM = 36, | |
168 | TS3_DMAP0_REGNUM = 38, | |
169 | TS3_NR_DMAP_REGS = 4, | |
170 | TS3_A0_REGNUM = 32 | |
171 | }; | |
172 | ||
173 | static char * | |
174 | d10v_ts3_register_name (int reg_nr) | |
175 | { | |
176 | static char *register_names[] = | |
177 | { | |
178 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
179 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
180 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
181 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
182 | "a0", "a1", | |
183 | "spi", "spu", | |
184 | "imap0", "imap1", | |
185 | "dmap0", "dmap1", "dmap2", "dmap3" | |
186 | }; | |
187 | if (reg_nr < 0) | |
188 | return NULL; | |
189 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
190 | return NULL; | |
191 | return register_names[reg_nr]; | |
192 | } | |
193 | ||
114d1f2c | 194 | /* Access the DMAP/IMAP registers in a target independent way. */ |
4ce44c66 JM |
195 | |
196 | static unsigned long | |
197 | d10v_ts2_dmap_register (int reg_nr) | |
198 | { | |
199 | switch (reg_nr) | |
200 | { | |
201 | case 0: | |
202 | case 1: | |
203 | return 0x2000; | |
204 | case 2: | |
205 | return read_register (TS2_DMAP_REGNUM); | |
206 | default: | |
207 | return 0; | |
208 | } | |
209 | } | |
210 | ||
211 | static unsigned long | |
212 | d10v_ts3_dmap_register (int reg_nr) | |
213 | { | |
214 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
215 | } | |
216 | ||
217 | static unsigned long | |
218 | d10v_dmap_register (int reg_nr) | |
219 | { | |
220 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
221 | } | |
222 | ||
223 | static unsigned long | |
224 | d10v_ts2_imap_register (int reg_nr) | |
225 | { | |
226 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
227 | } | |
228 | ||
229 | static unsigned long | |
230 | d10v_ts3_imap_register (int reg_nr) | |
231 | { | |
232 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
233 | } | |
234 | ||
235 | static unsigned long | |
236 | d10v_imap_register (int reg_nr) | |
237 | { | |
238 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
239 | } | |
240 | ||
241 | /* MAP GDB's internal register numbering (determined by the layout fo | |
242 | the REGISTER_BYTE array) onto the simulator's register | |
243 | numbering. */ | |
244 | ||
245 | static int | |
246 | d10v_ts2_register_sim_regno (int nr) | |
247 | { | |
248 | if (nr >= TS2_IMAP0_REGNUM | |
249 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
250 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
251 | if (nr == TS2_DMAP_REGNUM) | |
252 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
253 | if (nr >= TS2_A0_REGNUM | |
254 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
255 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
256 | return nr; | |
257 | } | |
258 | ||
259 | static int | |
260 | d10v_ts3_register_sim_regno (int nr) | |
261 | { | |
262 | if (nr >= TS3_IMAP0_REGNUM | |
263 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
264 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
265 | if (nr >= TS3_DMAP0_REGNUM | |
266 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
267 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
268 | if (nr >= TS3_A0_REGNUM | |
269 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
270 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
271 | return nr; | |
272 | } | |
273 | ||
392a587b JM |
274 | /* Index within `registers' of the first byte of the space for |
275 | register REG_NR. */ | |
276 | ||
277 | int | |
fba45db2 | 278 | d10v_register_byte (int reg_nr) |
392a587b | 279 | { |
4ce44c66 | 280 | if (reg_nr < A0_REGNUM) |
392a587b | 281 | return (reg_nr * 2); |
4ce44c66 JM |
282 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
283 | return (A0_REGNUM * 2 | |
284 | + (reg_nr - A0_REGNUM) * 8); | |
285 | else | |
286 | return (A0_REGNUM * 2 | |
287 | + NR_A_REGS * 8 | |
288 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
289 | } |
290 | ||
291 | /* Number of bytes of storage in the actual machine representation for | |
292 | register REG_NR. */ | |
293 | ||
294 | int | |
fba45db2 | 295 | d10v_register_raw_size (int reg_nr) |
392a587b | 296 | { |
4ce44c66 JM |
297 | if (reg_nr < A0_REGNUM) |
298 | return 2; | |
299 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
300 | return 8; |
301 | else | |
302 | return 2; | |
303 | } | |
304 | ||
305 | /* Number of bytes of storage in the program's representation | |
306 | for register N. */ | |
307 | ||
308 | int | |
fba45db2 | 309 | d10v_register_virtual_size (int reg_nr) |
392a587b | 310 | { |
4ce44c66 | 311 | return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr)); |
392a587b JM |
312 | } |
313 | ||
314 | /* Return the GDB type object for the "standard" data type | |
315 | of data in register N. */ | |
316 | ||
317 | struct type * | |
fba45db2 | 318 | d10v_register_virtual_type (int reg_nr) |
392a587b | 319 | { |
4ce44c66 JM |
320 | if (reg_nr >= A0_REGNUM |
321 | && reg_nr < (A0_REGNUM + NR_A_REGS)) | |
322 | return builtin_type_int64; | |
323 | else if (reg_nr == PC_REGNUM | |
324 | || reg_nr == SP_REGNUM) | |
325 | return builtin_type_int32; | |
392a587b | 326 | else |
4ce44c66 | 327 | return builtin_type_int16; |
392a587b JM |
328 | } |
329 | ||
392a587b | 330 | /* convert $pc and $sp to/from virtual addresses */ |
ac9a91a7 | 331 | int |
fba45db2 | 332 | d10v_register_convertible (int nr) |
ac9a91a7 JM |
333 | { |
334 | return ((nr) == PC_REGNUM || (nr) == SP_REGNUM); | |
335 | } | |
336 | ||
337 | void | |
fba45db2 KB |
338 | d10v_register_convert_to_virtual (int regnum, struct type *type, char *from, |
339 | char *to) | |
ac9a91a7 JM |
340 | { |
341 | ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum)); | |
342 | if (regnum == PC_REGNUM) | |
343 | x = (x << 2) | IMEM_START; | |
344 | else | |
345 | x |= DMEM_START; | |
346 | store_unsigned_integer (to, TYPE_LENGTH (type), x); | |
392a587b | 347 | } |
ac9a91a7 JM |
348 | |
349 | void | |
fba45db2 KB |
350 | d10v_register_convert_to_raw (struct type *type, int regnum, char *from, |
351 | char *to) | |
ac9a91a7 JM |
352 | { |
353 | ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type)); | |
354 | x &= 0x3ffff; | |
355 | if (regnum == PC_REGNUM) | |
356 | x >>= 2; | |
357 | store_unsigned_integer (to, 2, x); | |
392a587b | 358 | } |
ac9a91a7 | 359 | |
392a587b JM |
360 | |
361 | CORE_ADDR | |
fba45db2 | 362 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
363 | { |
364 | return ((x) | DMEM_START); | |
365 | } | |
366 | ||
367 | CORE_ADDR | |
fba45db2 | 368 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
369 | { |
370 | return (((x) << 2) | IMEM_START); | |
371 | } | |
372 | ||
373 | int | |
fba45db2 | 374 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
375 | { |
376 | return (((x) & 0x3000000) == DMEM_START); | |
377 | } | |
378 | ||
379 | int | |
fba45db2 | 380 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
381 | { |
382 | return (((x) & 0x3000000) == IMEM_START); | |
383 | } | |
384 | ||
385 | ||
386 | CORE_ADDR | |
fba45db2 | 387 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
388 | { |
389 | return (((x) >> 2) & 0xffff); | |
390 | } | |
391 | ||
392 | CORE_ADDR | |
fba45db2 | 393 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
394 | { |
395 | return ((x) & 0xffff); | |
396 | } | |
397 | ||
398 | /* Store the address of the place in which to copy the structure the | |
399 | subroutine will return. This is called from call_function. | |
400 | ||
401 | We store structs through a pointer passed in the first Argument | |
402 | register. */ | |
403 | ||
404 | void | |
fba45db2 | 405 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
406 | { |
407 | write_register (ARG1_REGNUM, (addr)); | |
408 | } | |
409 | ||
410 | /* Write into appropriate registers a function return value | |
411 | of type TYPE, given in virtual format. | |
412 | ||
413 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
414 | ||
415 | void | |
fba45db2 | 416 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
417 | { |
418 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
419 | valbuf, | |
420 | TYPE_LENGTH (type)); | |
421 | } | |
422 | ||
423 | /* Extract from an array REGBUF containing the (raw) register state | |
424 | the address in which a function should return its structure value, | |
425 | as a CORE_ADDR (or an expression that can be used as one). */ | |
426 | ||
427 | CORE_ADDR | |
fba45db2 | 428 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
429 | { |
430 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
431 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
432 | | DMEM_START); | |
433 | } | |
434 | ||
435 | CORE_ADDR | |
fba45db2 | 436 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 437 | { |
cce74817 | 438 | return ((frame)->extra_info->return_pc); |
392a587b JM |
439 | } |
440 | ||
441 | CORE_ADDR | |
fba45db2 | 442 | d10v_frame_args_address (struct frame_info *fi) |
392a587b JM |
443 | { |
444 | return (fi)->frame; | |
445 | } | |
446 | ||
447 | CORE_ADDR | |
fba45db2 | 448 | d10v_frame_locals_address (struct frame_info *fi) |
392a587b JM |
449 | { |
450 | return (fi)->frame; | |
451 | } | |
452 | ||
453 | /* Immediately after a function call, return the saved pc. We can't | |
454 | use frame->return_pc beause that is determined by reading R13 off | |
455 | the stack and that may not be written yet. */ | |
456 | ||
457 | CORE_ADDR | |
fba45db2 | 458 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 459 | { |
c5aa993b | 460 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
461 | | IMEM_START); |
462 | } | |
463 | ||
c906108c SS |
464 | /* Discard from the stack the innermost frame, restoring all saved |
465 | registers. */ | |
466 | ||
467 | void | |
fba45db2 | 468 | d10v_pop_frame (void) |
cce74817 JM |
469 | { |
470 | generic_pop_current_frame (do_d10v_pop_frame); | |
471 | } | |
472 | ||
473 | static void | |
fba45db2 | 474 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
475 | { |
476 | CORE_ADDR fp; | |
477 | int regnum; | |
c906108c SS |
478 | char raw_buffer[8]; |
479 | ||
cce74817 | 480 | fp = FRAME_FP (fi); |
c906108c SS |
481 | /* fill out fsr with the address of where each */ |
482 | /* register was stored in the frame */ | |
cce74817 | 483 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 484 | |
c906108c | 485 | /* now update the current registers with the old values */ |
4ce44c66 | 486 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 487 | { |
cce74817 | 488 | if (fi->saved_regs[regnum]) |
c906108c | 489 | { |
c5aa993b JM |
490 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
491 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
492 | } |
493 | } | |
494 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
495 | { | |
cce74817 | 496 | if (fi->saved_regs[regnum]) |
c906108c | 497 | { |
c5aa993b | 498 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
499 | } |
500 | } | |
cce74817 | 501 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 502 | { |
c5aa993b | 503 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
504 | } |
505 | ||
506 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 507 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
508 | target_store_registers (-1); |
509 | flush_cached_frames (); | |
510 | } | |
511 | ||
c5aa993b | 512 | static int |
fba45db2 | 513 | check_prologue (unsigned short op) |
c906108c SS |
514 | { |
515 | /* st rn, @-sp */ | |
516 | if ((op & 0x7E1F) == 0x6C1F) | |
517 | return 1; | |
518 | ||
519 | /* st2w rn, @-sp */ | |
520 | if ((op & 0x7E3F) == 0x6E1F) | |
521 | return 1; | |
522 | ||
523 | /* subi sp, n */ | |
524 | if ((op & 0x7FE1) == 0x01E1) | |
525 | return 1; | |
526 | ||
527 | /* mv r11, sp */ | |
528 | if (op == 0x417E) | |
529 | return 1; | |
530 | ||
531 | /* nop */ | |
532 | if (op == 0x5E00) | |
533 | return 1; | |
534 | ||
535 | /* st rn, @sp */ | |
536 | if ((op & 0x7E1F) == 0x681E) | |
537 | return 1; | |
538 | ||
539 | /* st2w rn, @sp */ | |
c5aa993b JM |
540 | if ((op & 0x7E3F) == 0x3A1E) |
541 | return 1; | |
c906108c SS |
542 | |
543 | return 0; | |
544 | } | |
545 | ||
546 | CORE_ADDR | |
fba45db2 | 547 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
548 | { |
549 | unsigned long op; | |
550 | unsigned short op1, op2; | |
551 | CORE_ADDR func_addr, func_end; | |
552 | struct symtab_and_line sal; | |
553 | ||
554 | /* If we have line debugging information, then the end of the */ | |
555 | /* prologue should the first assembly instruction of the first source line */ | |
556 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
557 | { | |
558 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 559 | if (sal.end && sal.end < func_end) |
c906108c SS |
560 | return sal.end; |
561 | } | |
c5aa993b JM |
562 | |
563 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
564 | return pc; /* Can't access it -- assume no prologue. */ |
565 | ||
566 | while (1) | |
567 | { | |
c5aa993b | 568 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
569 | if ((op & 0xC0000000) == 0xC0000000) |
570 | { | |
571 | /* long instruction */ | |
c5aa993b JM |
572 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
573 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
574 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
575 | break; |
576 | } | |
577 | else | |
578 | { | |
579 | /* short instructions */ | |
580 | if ((op & 0xC0000000) == 0x80000000) | |
581 | { | |
582 | op2 = (op & 0x3FFF8000) >> 15; | |
583 | op1 = op & 0x7FFF; | |
c5aa993b JM |
584 | } |
585 | else | |
c906108c SS |
586 | { |
587 | op1 = (op & 0x3FFF8000) >> 15; | |
588 | op2 = op & 0x7FFF; | |
589 | } | |
c5aa993b | 590 | if (check_prologue (op1)) |
c906108c | 591 | { |
c5aa993b | 592 | if (!check_prologue (op2)) |
c906108c SS |
593 | { |
594 | /* if the previous opcode was really part of the prologue */ | |
595 | /* and not just a NOP, then we want to break after both instructions */ | |
596 | if (op1 != 0x5E00) | |
597 | pc += 4; | |
598 | break; | |
599 | } | |
600 | } | |
601 | else | |
602 | break; | |
603 | } | |
604 | pc += 4; | |
605 | } | |
606 | return pc; | |
607 | } | |
608 | ||
609 | /* Given a GDB frame, determine the address of the calling function's frame. | |
610 | This will be used to create a new GDB frame struct, and then | |
611 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 612 | */ |
c906108c SS |
613 | |
614 | CORE_ADDR | |
fba45db2 | 615 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 616 | { |
cce74817 | 617 | d10v_frame_init_saved_regs (fi); |
c906108c | 618 | |
cce74817 JM |
619 | if (fi->extra_info->return_pc == IMEM_START |
620 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 621 | return (CORE_ADDR) 0; |
c906108c | 622 | |
cce74817 | 623 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 624 | { |
cce74817 JM |
625 | if (!fi->saved_regs[SP_REGNUM] |
626 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
627 | return (CORE_ADDR) 0; |
628 | ||
cce74817 | 629 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
630 | } |
631 | ||
c5aa993b JM |
632 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
633 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
634 | return (CORE_ADDR) 0; | |
c906108c | 635 | |
cce74817 | 636 | return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
637 | REGISTER_RAW_SIZE (FP_REGNUM))); |
638 | } | |
c906108c SS |
639 | |
640 | static int next_addr, uses_frame; | |
641 | ||
c5aa993b | 642 | static int |
fba45db2 | 643 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
644 | { |
645 | int n; | |
646 | ||
647 | /* st rn, @-sp */ | |
648 | if ((op & 0x7E1F) == 0x6C1F) | |
649 | { | |
650 | n = (op & 0x1E0) >> 5; | |
651 | next_addr -= 2; | |
cce74817 | 652 | fi->saved_regs[n] = next_addr; |
c906108c SS |
653 | return 1; |
654 | } | |
655 | ||
656 | /* st2w rn, @-sp */ | |
657 | else if ((op & 0x7E3F) == 0x6E1F) | |
658 | { | |
659 | n = (op & 0x1E0) >> 5; | |
660 | next_addr -= 4; | |
cce74817 | 661 | fi->saved_regs[n] = next_addr; |
c5aa993b | 662 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
663 | return 1; |
664 | } | |
665 | ||
666 | /* subi sp, n */ | |
667 | if ((op & 0x7FE1) == 0x01E1) | |
668 | { | |
669 | n = (op & 0x1E) >> 1; | |
670 | if (n == 0) | |
671 | n = 16; | |
672 | next_addr -= n; | |
673 | return 1; | |
674 | } | |
675 | ||
676 | /* mv r11, sp */ | |
677 | if (op == 0x417E) | |
678 | { | |
679 | uses_frame = 1; | |
680 | return 1; | |
681 | } | |
682 | ||
683 | /* nop */ | |
684 | if (op == 0x5E00) | |
685 | return 1; | |
686 | ||
687 | /* st rn, @sp */ | |
688 | if ((op & 0x7E1F) == 0x681E) | |
689 | { | |
690 | n = (op & 0x1E0) >> 5; | |
cce74817 | 691 | fi->saved_regs[n] = next_addr; |
c906108c SS |
692 | return 1; |
693 | } | |
694 | ||
695 | /* st2w rn, @sp */ | |
696 | if ((op & 0x7E3F) == 0x3A1E) | |
697 | { | |
698 | n = (op & 0x1E0) >> 5; | |
cce74817 | 699 | fi->saved_regs[n] = next_addr; |
c5aa993b | 700 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
701 | return 1; |
702 | } | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
cce74817 JM |
707 | /* Put here the code to store, into fi->saved_regs, the addresses of |
708 | the saved registers of frame described by FRAME_INFO. This | |
709 | includes special registers such as pc and fp saved in special ways | |
710 | in the stack frame. sp is even more special: the address we return | |
711 | for it IS the sp for the next frame. */ | |
712 | ||
c906108c | 713 | void |
fba45db2 | 714 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
715 | { |
716 | CORE_ADDR fp, pc; | |
717 | unsigned long op; | |
718 | unsigned short op1, op2; | |
719 | int i; | |
720 | ||
721 | fp = fi->frame; | |
cce74817 | 722 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
723 | next_addr = 0; |
724 | ||
725 | pc = get_pc_function_start (fi->pc); | |
726 | ||
727 | uses_frame = 0; | |
728 | while (1) | |
729 | { | |
c5aa993b | 730 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
731 | if ((op & 0xC0000000) == 0xC0000000) |
732 | { | |
733 | /* long instruction */ | |
734 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
735 | { | |
736 | /* add3 sp,sp,n */ | |
737 | short n = op & 0xFFFF; | |
738 | next_addr += n; | |
739 | } | |
740 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
741 | { | |
742 | /* st rn, @(offset,sp) */ | |
743 | short offset = op & 0xFFFF; | |
744 | short n = (op >> 20) & 0xF; | |
cce74817 | 745 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
746 | } |
747 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
748 | { | |
749 | /* st2w rn, @(offset,sp) */ | |
750 | short offset = op & 0xFFFF; | |
751 | short n = (op >> 20) & 0xF; | |
cce74817 | 752 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 753 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
754 | } |
755 | else | |
756 | break; | |
757 | } | |
758 | else | |
759 | { | |
760 | /* short instructions */ | |
761 | if ((op & 0xC0000000) == 0x80000000) | |
762 | { | |
763 | op2 = (op & 0x3FFF8000) >> 15; | |
764 | op1 = op & 0x7FFF; | |
c5aa993b JM |
765 | } |
766 | else | |
c906108c SS |
767 | { |
768 | op1 = (op & 0x3FFF8000) >> 15; | |
769 | op2 = op & 0x7FFF; | |
770 | } | |
c5aa993b | 771 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
772 | break; |
773 | } | |
774 | pc += 4; | |
775 | } | |
c5aa993b | 776 | |
cce74817 | 777 | fi->extra_info->size = -next_addr; |
c906108c SS |
778 | |
779 | if (!(fp & 0xffff)) | |
c5aa993b | 780 | fp = D10V_MAKE_DADDR (read_register (SP_REGNUM)); |
c906108c | 781 | |
c5aa993b | 782 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 783 | if (fi->saved_regs[i]) |
c906108c | 784 | { |
c5aa993b | 785 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
786 | } |
787 | ||
cce74817 | 788 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 789 | { |
cce74817 JM |
790 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
791 | fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc); | |
c906108c SS |
792 | } |
793 | else | |
794 | { | |
c5aa993b | 795 | fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM)); |
c906108c | 796 | } |
c5aa993b | 797 | |
c906108c | 798 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 799 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
800 | { |
801 | /* if the FP was saved, that means the current FP is valid, */ | |
802 | /* otherwise, it isn't being used, so we use the SP instead */ | |
803 | if (uses_frame) | |
c5aa993b | 804 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
805 | else |
806 | { | |
cce74817 JM |
807 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
808 | fi->extra_info->frameless = 1; | |
809 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
810 | } |
811 | } | |
812 | } | |
813 | ||
814 | void | |
fba45db2 | 815 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 816 | { |
cce74817 JM |
817 | fi->extra_info = (struct frame_extra_info *) |
818 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
819 | frame_saved_regs_zalloc (fi); | |
820 | ||
821 | fi->extra_info->frameless = 0; | |
822 | fi->extra_info->size = 0; | |
823 | fi->extra_info->return_pc = 0; | |
c906108c SS |
824 | |
825 | /* The call dummy doesn't save any registers on the stack, so we can | |
826 | return now. */ | |
827 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
828 | { | |
829 | return; | |
830 | } | |
831 | else | |
832 | { | |
cce74817 | 833 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
834 | } |
835 | } | |
836 | ||
837 | static void | |
fba45db2 | 838 | show_regs (char *args, int from_tty) |
c906108c SS |
839 | { |
840 | int a; | |
d4f3574e SS |
841 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
842 | (long) read_register (PC_REGNUM), | |
843 | (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)), | |
844 | (long) read_register (PSW_REGNUM), | |
845 | (long) read_register (24), | |
846 | (long) read_register (25), | |
847 | (long) read_register (23)); | |
848 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
849 | (long) read_register (0), | |
850 | (long) read_register (1), | |
851 | (long) read_register (2), | |
852 | (long) read_register (3), | |
853 | (long) read_register (4), | |
854 | (long) read_register (5), | |
855 | (long) read_register (6), | |
856 | (long) read_register (7)); | |
857 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
858 | (long) read_register (8), | |
859 | (long) read_register (9), | |
860 | (long) read_register (10), | |
861 | (long) read_register (11), | |
862 | (long) read_register (12), | |
863 | (long) read_register (13), | |
864 | (long) read_register (14), | |
865 | (long) read_register (15)); | |
4ce44c66 JM |
866 | for (a = 0; a < NR_IMAP_REGS; a++) |
867 | { | |
868 | if (a > 0) | |
869 | printf_filtered (" "); | |
870 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
871 | } | |
872 | if (NR_DMAP_REGS == 1) | |
873 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
874 | else | |
875 | { | |
876 | for (a = 0; a < NR_DMAP_REGS; a++) | |
877 | { | |
878 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
879 | } | |
880 | printf_filtered ("\n"); | |
881 | } | |
882 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
883 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
884 | { |
885 | char num[MAX_REGISTER_RAW_SIZE]; | |
886 | int i; | |
887 | printf_filtered (" "); | |
c5aa993b | 888 | read_register_gen (a, (char *) &num); |
c906108c SS |
889 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
890 | { | |
891 | printf_filtered ("%02x", (num[i] & 0xff)); | |
892 | } | |
893 | } | |
894 | printf_filtered ("\n"); | |
895 | } | |
896 | ||
897 | CORE_ADDR | |
fba45db2 | 898 | d10v_read_pc (int pid) |
c906108c SS |
899 | { |
900 | int save_pid; | |
901 | CORE_ADDR pc; | |
902 | CORE_ADDR retval; | |
903 | ||
904 | save_pid = inferior_pid; | |
905 | inferior_pid = pid; | |
906 | pc = (int) read_register (PC_REGNUM); | |
907 | inferior_pid = save_pid; | |
908 | retval = D10V_MAKE_IADDR (pc); | |
909 | return retval; | |
910 | } | |
911 | ||
912 | void | |
fba45db2 | 913 | d10v_write_pc (CORE_ADDR val, int pid) |
c906108c SS |
914 | { |
915 | int save_pid; | |
916 | ||
917 | save_pid = inferior_pid; | |
918 | inferior_pid = pid; | |
919 | write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val)); | |
920 | inferior_pid = save_pid; | |
921 | } | |
922 | ||
923 | CORE_ADDR | |
fba45db2 | 924 | d10v_read_sp (void) |
c906108c SS |
925 | { |
926 | return (D10V_MAKE_DADDR (read_register (SP_REGNUM))); | |
927 | } | |
928 | ||
929 | void | |
fba45db2 | 930 | d10v_write_sp (CORE_ADDR val) |
c906108c SS |
931 | { |
932 | write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
933 | } | |
934 | ||
935 | void | |
fba45db2 | 936 | d10v_write_fp (CORE_ADDR val) |
c906108c SS |
937 | { |
938 | write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
939 | } | |
940 | ||
941 | CORE_ADDR | |
fba45db2 | 942 | d10v_read_fp (void) |
c906108c | 943 | { |
c5aa993b | 944 | return (D10V_MAKE_DADDR (read_register (FP_REGNUM))); |
c906108c SS |
945 | } |
946 | ||
947 | /* Function: push_return_address (pc) | |
948 | Set up the return address for the inferior function call. | |
949 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 950 | |
c906108c | 951 | CORE_ADDR |
fba45db2 | 952 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c SS |
953 | { |
954 | write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); | |
955 | return sp; | |
956 | } | |
c5aa993b | 957 | |
c906108c | 958 | |
7a292a7a SS |
959 | /* When arguments must be pushed onto the stack, they go on in reverse |
960 | order. The below implements a FILO (stack) to do this. */ | |
961 | ||
962 | struct stack_item | |
963 | { | |
964 | int len; | |
965 | struct stack_item *prev; | |
966 | void *data; | |
967 | }; | |
968 | ||
a14ed312 KB |
969 | static struct stack_item *push_stack_item (struct stack_item *prev, |
970 | void *contents, int len); | |
7a292a7a | 971 | static struct stack_item * |
fba45db2 | 972 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
973 | { |
974 | struct stack_item *si; | |
975 | si = xmalloc (sizeof (struct stack_item)); | |
976 | si->data = xmalloc (len); | |
977 | si->len = len; | |
978 | si->prev = prev; | |
979 | memcpy (si->data, contents, len); | |
980 | return si; | |
981 | } | |
982 | ||
a14ed312 | 983 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 984 | static struct stack_item * |
fba45db2 | 985 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
986 | { |
987 | struct stack_item *dead = si; | |
988 | si = si->prev; | |
989 | free (dead->data); | |
990 | free (dead); | |
991 | return si; | |
992 | } | |
993 | ||
994 | ||
c906108c | 995 | CORE_ADDR |
fba45db2 KB |
996 | d10v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp, |
997 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
998 | { |
999 | int i; | |
1000 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1001 | struct stack_item *si = NULL; |
c5aa993b | 1002 | |
c906108c SS |
1003 | /* Fill in registers and arg lists */ |
1004 | for (i = 0; i < nargs; i++) | |
1005 | { | |
1006 | value_ptr arg = args[i]; | |
1007 | struct type *type = check_typedef (VALUE_TYPE (arg)); | |
1008 | char *contents = VALUE_CONTENTS (arg); | |
1009 | int len = TYPE_LENGTH (type); | |
1010 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
1011 | if (TYPE_CODE (type) == TYPE_CODE_PTR) | |
1012 | { | |
1013 | /* pointers require special handling - first convert and | |
1014 | then store */ | |
1015 | long val = extract_signed_integer (contents, len); | |
1016 | len = 2; | |
1017 | if (TYPE_TARGET_TYPE (type) | |
1018 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1019 | { | |
1020 | /* function pointer */ | |
1021 | val = D10V_CONVERT_IADDR_TO_RAW (val); | |
1022 | } | |
1023 | else if (D10V_IADDR_P (val)) | |
1024 | { | |
1025 | /* also function pointer! */ | |
1026 | val = D10V_CONVERT_DADDR_TO_RAW (val); | |
1027 | } | |
1028 | else | |
1029 | { | |
1030 | /* data pointer */ | |
1031 | val &= 0xFFFF; | |
1032 | } | |
1033 | if (regnum <= ARGN_REGNUM) | |
1034 | write_register (regnum++, val & 0xffff); | |
1035 | else | |
1036 | { | |
1037 | char ptr[2]; | |
7a292a7a | 1038 | /* arg will go onto stack */ |
0f71a2f6 | 1039 | store_address (ptr, 2, val & 0xffff); |
7a292a7a | 1040 | si = push_stack_item (si, ptr, 2); |
c906108c SS |
1041 | } |
1042 | } | |
1043 | else | |
1044 | { | |
1045 | int aligned_regnum = (regnum + 1) & ~1; | |
1046 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1047 | /* fits in a single register, do not align */ | |
1048 | { | |
1049 | long val = extract_unsigned_integer (contents, len); | |
1050 | write_register (regnum++, val); | |
1051 | } | |
1052 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1053 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1054 | aligned */ |
c906108c SS |
1055 | { |
1056 | int b; | |
1057 | regnum = aligned_regnum; | |
1058 | for (b = 0; b < (len & ~1); b += 2) | |
1059 | { | |
1060 | long val = extract_unsigned_integer (&contents[b], 2); | |
1061 | write_register (regnum++, val); | |
1062 | } | |
1063 | if (b < len) | |
1064 | { | |
1065 | long val = extract_unsigned_integer (&contents[b], 1); | |
1066 | write_register (regnum++, (val << 8)); | |
1067 | } | |
1068 | } | |
1069 | else | |
1070 | { | |
7a292a7a | 1071 | /* arg will go onto stack */ |
c5aa993b | 1072 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1073 | si = push_stack_item (si, contents, len); |
c906108c SS |
1074 | } |
1075 | } | |
1076 | } | |
7a292a7a SS |
1077 | |
1078 | while (si) | |
1079 | { | |
1080 | sp = (sp - si->len) & ~1; | |
1081 | write_memory (sp, si->data, si->len); | |
1082 | si = pop_stack_item (si); | |
1083 | } | |
c5aa993b | 1084 | |
c906108c SS |
1085 | return sp; |
1086 | } | |
1087 | ||
1088 | ||
1089 | /* Given a return value in `regbuf' with a type `valtype', | |
1090 | extract and copy its value into `valbuf'. */ | |
1091 | ||
1092 | void | |
72623009 KB |
1093 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1094 | char *valbuf) | |
c906108c SS |
1095 | { |
1096 | int len; | |
1097 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
1098 | if (TYPE_CODE (type) == TYPE_CODE_PTR | |
1099 | && TYPE_TARGET_TYPE (type) | |
1100 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1101 | { | |
1102 | /* pointer to function */ | |
1103 | int num; | |
1104 | short snum; | |
1105 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1106 | store_address (valbuf, 4, D10V_MAKE_IADDR (snum)); |
c906108c | 1107 | } |
c5aa993b | 1108 | else if (TYPE_CODE (type) == TYPE_CODE_PTR) |
c906108c SS |
1109 | { |
1110 | /* pointer to data */ | |
1111 | int num; | |
1112 | short snum; | |
1113 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1114 | store_address (valbuf, 4, D10V_MAKE_DADDR (snum)); |
c906108c SS |
1115 | } |
1116 | else | |
1117 | { | |
1118 | len = TYPE_LENGTH (type); | |
1119 | if (len == 1) | |
1120 | { | |
1121 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1122 | store_unsigned_integer (valbuf, 1, c); | |
1123 | } | |
1124 | else if ((len & 1) == 0) | |
1125 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1126 | else | |
1127 | { | |
1128 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1129 | least significant part of the first register. The |
1130 | remaining bytes in remaining registers. Interestingly, | |
1131 | when such values are passed in, the last byte is in the | |
1132 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1133 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1134 | } | |
1135 | } | |
1136 | } | |
1137 | ||
c2c6d25f JM |
1138 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1139 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1140 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1141 | (segmentation fault). Since the simulator knows all about how the | |
1142 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1143 | |
4ce44c66 | 1144 | static void |
c2c6d25f JM |
1145 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1146 | CORE_ADDR *targ_addr, int *targ_len) | |
1147 | { | |
4ce44c66 JM |
1148 | long out_addr; |
1149 | long out_len; | |
1150 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1151 | &out_addr, | |
1152 | d10v_dmap_register, | |
1153 | d10v_imap_register); | |
1154 | *targ_addr = out_addr; | |
1155 | *targ_len = out_len; | |
c2c6d25f JM |
1156 | } |
1157 | ||
4ce44c66 | 1158 | |
c906108c SS |
1159 | /* The following code implements access to, and display of, the D10V's |
1160 | instruction trace buffer. The buffer consists of 64K or more | |
1161 | 4-byte words of data, of which each words includes an 8-bit count, | |
1162 | an 8-bit segment number, and a 16-bit instruction address. | |
1163 | ||
1164 | In theory, the trace buffer is continuously capturing instruction | |
1165 | data that the CPU presents on its "debug bus", but in practice, the | |
1166 | ROMified GDB stub only enables tracing when it continues or steps | |
1167 | the program, and stops tracing when the program stops; so it | |
1168 | actually works for GDB to read the buffer counter out of memory and | |
1169 | then read each trace word. The counter records where the tracing | |
1170 | stops, but there is no record of where it started, so we remember | |
1171 | the PC when we resumed and then search backwards in the trace | |
1172 | buffer for a word that includes that address. This is not perfect, | |
1173 | because you will miss trace data if the resumption PC is the target | |
1174 | of a branch. (The value of the buffer counter is semi-random, any | |
1175 | trace data from a previous program stop is gone.) */ | |
1176 | ||
1177 | /* The address of the last word recorded in the trace buffer. */ | |
1178 | ||
1179 | #define DBBC_ADDR (0xd80000) | |
1180 | ||
1181 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1182 | ||
1183 | #define TRACE_BUFFER_BASE (0xf40000) | |
1184 | ||
a14ed312 | 1185 | static void trace_command (char *, int); |
c906108c | 1186 | |
a14ed312 | 1187 | static void untrace_command (char *, int); |
c906108c | 1188 | |
a14ed312 | 1189 | static void trace_info (char *, int); |
c906108c | 1190 | |
a14ed312 | 1191 | static void tdisassemble_command (char *, int); |
c906108c | 1192 | |
a14ed312 | 1193 | static void display_trace (int, int); |
c906108c SS |
1194 | |
1195 | /* True when instruction traces are being collected. */ | |
1196 | ||
1197 | static int tracing; | |
1198 | ||
1199 | /* Remembered PC. */ | |
1200 | ||
1201 | static CORE_ADDR last_pc; | |
1202 | ||
1203 | /* True when trace output should be displayed whenever program stops. */ | |
1204 | ||
1205 | static int trace_display; | |
1206 | ||
1207 | /* True when trace listing should include source lines. */ | |
1208 | ||
1209 | static int default_trace_show_source = 1; | |
1210 | ||
c5aa993b JM |
1211 | struct trace_buffer |
1212 | { | |
1213 | int size; | |
1214 | short *counts; | |
1215 | CORE_ADDR *addrs; | |
1216 | } | |
1217 | trace_data; | |
c906108c SS |
1218 | |
1219 | static void | |
fba45db2 | 1220 | trace_command (char *args, int from_tty) |
c906108c SS |
1221 | { |
1222 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1223 | trace_data.size = 0; | |
1224 | if (trace_data.counts == NULL) | |
c5aa993b | 1225 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1226 | if (trace_data.addrs == NULL) |
c5aa993b | 1227 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1228 | |
1229 | tracing = 1; | |
1230 | ||
1231 | printf_filtered ("Tracing is now on.\n"); | |
1232 | } | |
1233 | ||
1234 | static void | |
fba45db2 | 1235 | untrace_command (char *args, int from_tty) |
c906108c SS |
1236 | { |
1237 | tracing = 0; | |
1238 | ||
1239 | printf_filtered ("Tracing is now off.\n"); | |
1240 | } | |
1241 | ||
1242 | static void | |
fba45db2 | 1243 | trace_info (char *args, int from_tty) |
c906108c SS |
1244 | { |
1245 | int i; | |
1246 | ||
1247 | if (trace_data.size) | |
1248 | { | |
1249 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1250 | ||
1251 | for (i = 0; i < trace_data.size; ++i) | |
1252 | { | |
d4f3574e SS |
1253 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1254 | i, | |
1255 | trace_data.counts[i], | |
c906108c | 1256 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1257 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1258 | } |
1259 | } | |
1260 | else | |
1261 | printf_filtered ("No entries in trace buffer.\n"); | |
1262 | ||
1263 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1264 | } | |
1265 | ||
1266 | /* Print the instruction at address MEMADDR in debugged memory, | |
1267 | on STREAM. Returns length of the instruction, in bytes. */ | |
1268 | ||
1269 | static int | |
fba45db2 | 1270 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1271 | { |
1272 | /* If there's no disassembler, something is very wrong. */ | |
1273 | if (tm_print_insn == NULL) | |
11cf8741 | 1274 | internal_error ("print_insn: no disassembler"); |
c906108c SS |
1275 | |
1276 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1277 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; | |
1278 | else | |
1279 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
1280 | return (*tm_print_insn) (memaddr, &tm_print_insn_info); | |
1281 | } | |
1282 | ||
392a587b | 1283 | static void |
fba45db2 | 1284 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1285 | { |
1286 | if (!tracing) | |
1287 | return; | |
1288 | ||
1289 | last_pc = read_register (PC_REGNUM); | |
1290 | } | |
1291 | ||
1292 | /* Collect trace data from the target board and format it into a form | |
1293 | more useful for display. */ | |
1294 | ||
392a587b | 1295 | static void |
fba45db2 | 1296 | d10v_eva_get_trace_data (void) |
c906108c SS |
1297 | { |
1298 | int count, i, j, oldsize; | |
1299 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1300 | unsigned int last_trace, trace_word, next_word; | |
1301 | unsigned int *tmpspace; | |
1302 | ||
1303 | if (!tracing) | |
1304 | return; | |
1305 | ||
c5aa993b | 1306 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1307 | |
1308 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1309 | ||
1310 | /* Collect buffer contents from the target, stopping when we reach | |
1311 | the word recorded when execution resumed. */ | |
1312 | ||
1313 | count = 0; | |
1314 | while (last_trace > 0) | |
1315 | { | |
1316 | QUIT; | |
1317 | trace_word = | |
1318 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1319 | trace_addr = trace_word & 0xffff; | |
1320 | last_trace -= 4; | |
1321 | /* Ignore an apparently nonsensical entry. */ | |
1322 | if (trace_addr == 0xffd5) | |
1323 | continue; | |
1324 | tmpspace[count++] = trace_word; | |
1325 | if (trace_addr == last_pc) | |
1326 | break; | |
1327 | if (count > 65535) | |
1328 | break; | |
1329 | } | |
1330 | ||
1331 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1332 | include the last instruction executed and transforming the address | |
1333 | into something that GDB likes. */ | |
1334 | ||
1335 | for (i = 0; i < count; ++i) | |
1336 | { | |
1337 | trace_word = tmpspace[i]; | |
1338 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1339 | trace_addr = trace_word & 0xffff; | |
1340 | next_cnt = (next_word >> 24) & 0xff; | |
1341 | j = trace_data.size + count - i - 1; | |
1342 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1343 | trace_data.counts[j] = next_cnt + 1; | |
1344 | } | |
1345 | ||
1346 | oldsize = trace_data.size; | |
1347 | trace_data.size += count; | |
1348 | ||
1349 | free (tmpspace); | |
1350 | ||
1351 | if (trace_display) | |
1352 | display_trace (oldsize, trace_data.size); | |
1353 | } | |
1354 | ||
1355 | static void | |
fba45db2 | 1356 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1357 | { |
1358 | int i, count; | |
1359 | CORE_ADDR low, high; | |
1360 | char *space_index; | |
1361 | ||
1362 | if (!arg) | |
1363 | { | |
1364 | low = 0; | |
1365 | high = trace_data.size; | |
1366 | } | |
1367 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1368 | { | |
1369 | low = parse_and_eval_address (arg); | |
1370 | high = low + 5; | |
1371 | } | |
1372 | else | |
1373 | { | |
1374 | /* Two arguments. */ | |
1375 | *space_index = '\0'; | |
1376 | low = parse_and_eval_address (arg); | |
1377 | high = parse_and_eval_address (space_index + 1); | |
1378 | if (high < low) | |
1379 | high = low; | |
1380 | } | |
1381 | ||
d4f3574e | 1382 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1383 | |
1384 | display_trace (low, high); | |
1385 | ||
1386 | printf_filtered ("End of trace dump.\n"); | |
1387 | gdb_flush (gdb_stdout); | |
1388 | } | |
1389 | ||
1390 | static void | |
fba45db2 | 1391 | display_trace (int low, int high) |
c906108c SS |
1392 | { |
1393 | int i, count, trace_show_source, first, suppress; | |
1394 | CORE_ADDR next_address; | |
1395 | ||
1396 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1397 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1398 | { |
1399 | trace_show_source = 0; | |
1400 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1401 | printf_filtered ("Trace will not display any source.\n"); | |
1402 | } | |
1403 | ||
1404 | first = 1; | |
1405 | suppress = 0; | |
1406 | for (i = low; i < high; ++i) | |
1407 | { | |
1408 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1409 | count = trace_data.counts[i]; |
c906108c SS |
1410 | while (count-- > 0) |
1411 | { | |
1412 | QUIT; | |
1413 | if (trace_show_source) | |
1414 | { | |
1415 | struct symtab_and_line sal, sal_prev; | |
1416 | ||
1417 | sal_prev = find_pc_line (next_address - 4, 0); | |
1418 | sal = find_pc_line (next_address, 0); | |
1419 | ||
1420 | if (sal.symtab) | |
1421 | { | |
1422 | if (first || sal.line != sal_prev.line) | |
1423 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1424 | suppress = 0; | |
1425 | } | |
1426 | else | |
1427 | { | |
1428 | if (!suppress) | |
1429 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1430 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1431 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1432 | suppress = 1; |
1433 | } | |
1434 | } | |
1435 | first = 0; | |
1436 | print_address (next_address, gdb_stdout); | |
1437 | printf_filtered (":"); | |
1438 | printf_filtered ("\t"); | |
1439 | wrap_here (" "); | |
1440 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1441 | printf_filtered ("\n"); | |
1442 | gdb_flush (gdb_stdout); | |
1443 | } | |
1444 | } | |
1445 | } | |
1446 | ||
ac9a91a7 | 1447 | |
0f71a2f6 | 1448 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1449 | |
0f71a2f6 | 1450 | static struct gdbarch * |
fba45db2 | 1451 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1452 | { |
c5aa993b JM |
1453 | static LONGEST d10v_call_dummy_words[] = |
1454 | {0}; | |
0f71a2f6 | 1455 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1456 | int d10v_num_regs; |
1457 | struct gdbarch_tdep *tdep; | |
1458 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1459 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1460 | |
4ce44c66 JM |
1461 | /* Find a candidate among the list of pre-declared architectures. */ |
1462 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1463 | if (arches != NULL) |
1464 | return arches->gdbarch; | |
4ce44c66 JM |
1465 | |
1466 | /* None found, create a new architecture from the information | |
1467 | provided. */ | |
1468 | tdep = XMALLOC (struct gdbarch_tdep); | |
1469 | gdbarch = gdbarch_alloc (&info, tdep); | |
1470 | ||
1471 | switch (info.bfd_arch_info->mach) | |
1472 | { | |
1473 | case bfd_mach_d10v_ts2: | |
1474 | d10v_num_regs = 37; | |
1475 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1476 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1477 | tdep->a0_regnum = TS2_A0_REGNUM; |
1478 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1479 | tdep->dmap_register = d10v_ts2_dmap_register; |
1480 | tdep->imap_register = d10v_ts2_imap_register; | |
1481 | break; | |
1482 | default: | |
1483 | case bfd_mach_d10v_ts3: | |
1484 | d10v_num_regs = 42; | |
1485 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1486 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1487 | tdep->a0_regnum = TS3_A0_REGNUM; |
1488 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1489 | tdep->dmap_register = d10v_ts3_dmap_register; |
1490 | tdep->imap_register = d10v_ts3_imap_register; | |
1491 | break; | |
1492 | } | |
0f71a2f6 JM |
1493 | |
1494 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1495 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1496 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1497 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1498 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1499 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1500 | ||
1501 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1502 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1503 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1504 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1505 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1506 | set_gdbarch_register_size (gdbarch, 2); | |
1507 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1508 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1509 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1510 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
1511 | set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size); | |
1512 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
1513 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1514 | ||
1515 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1516 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1517 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1518 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1519 | set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1520 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1521 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1522 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1523 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1524 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1525 | switch (info.byte_order) |
1526 | { | |
1527 | case BIG_ENDIAN: | |
1528 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1529 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1530 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1531 | break; | |
1532 | case LITTLE_ENDIAN: | |
1533 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
1534 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1535 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1536 | break; | |
1537 | default: | |
1538 | internal_error ("d10v_gdbarch_init: bad byte order for float format"); | |
1539 | } | |
0f71a2f6 JM |
1540 | |
1541 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1542 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1543 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1544 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1545 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1546 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1547 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1548 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1549 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1550 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1551 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1552 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1553 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1554 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1555 | ||
1556 | set_gdbarch_register_convertible (gdbarch, d10v_register_convertible); | |
1557 | set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual); | |
1558 | set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw); | |
1559 | ||
1560 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); | |
1561 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1562 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1563 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1564 | ||
1565 | set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr); | |
1566 | set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr); | |
1567 | set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p); | |
1568 | set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p); | |
1569 | set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw); | |
1570 | set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw); | |
1571 | ||
1572 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); | |
1573 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1574 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1575 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1576 | ||
1577 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1578 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1579 | ||
1580 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1581 | ||
1582 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1583 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1584 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1585 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1586 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1587 | ||
1588 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1589 | ||
1590 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1591 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1592 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1593 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1594 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
1595 | set_gdbarch_frame_args_address (gdbarch, d10v_frame_args_address); | |
1596 | set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address); | |
1597 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); | |
1598 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1599 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1600 | |
7c7651b2 | 1601 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1602 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1603 | |
0f71a2f6 JM |
1604 | return gdbarch; |
1605 | } | |
1606 | ||
1607 | ||
507f3c78 KB |
1608 | extern void (*target_resume_hook) (void); |
1609 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1610 | |
1611 | void | |
fba45db2 | 1612 | _initialize_d10v_tdep (void) |
c906108c | 1613 | { |
0f71a2f6 JM |
1614 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1615 | ||
c906108c SS |
1616 | tm_print_insn = print_insn_d10v; |
1617 | ||
1618 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1619 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1620 | ||
1621 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1622 | ||
cff3e48b | 1623 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1624 | "Enable tracing of instruction execution."); |
1625 | ||
cff3e48b | 1626 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1627 | "Disable tracing of instruction execution."); |
1628 | ||
cff3e48b | 1629 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1630 | "Disassemble the trace buffer.\n\ |
1631 | Two optional arguments specify a range of trace buffer entries\n\ | |
1632 | as reported by info trace (NOT addresses!)."); | |
1633 | ||
cff3e48b | 1634 | add_info ("itrace", trace_info, |
c906108c SS |
1635 | "Display info about the trace data buffer."); |
1636 | ||
cff3e48b | 1637 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1638 | var_integer, (char *) &trace_display, |
1639 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1640 | &showlist); |
cff3e48b | 1641 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1642 | var_integer, (char *) &default_trace_show_source, |
1643 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1644 | &showlist); |
1645 | ||
c5aa993b | 1646 | } |