Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
b6ba6518 KB |
2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "obstack.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
c5aa993b | 34 | #include "dis-asm.h" |
c906108c SS |
35 | #include "symfile.h" |
36 | #include "objfiles.h" | |
104c1213 | 37 | #include "language.h" |
28d069e6 | 38 | #include "arch-utils.h" |
4e052eda | 39 | #include "regcache.h" |
c906108c | 40 | |
f0d4cc9e | 41 | #include "floatformat.h" |
4ce44c66 JM |
42 | #include "sim-d10v.h" |
43 | ||
44 | #undef XMALLOC | |
45 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
46 | ||
cce74817 | 47 | struct frame_extra_info |
c5aa993b JM |
48 | { |
49 | CORE_ADDR return_pc; | |
50 | int frameless; | |
51 | int size; | |
52 | }; | |
cce74817 | 53 | |
4ce44c66 JM |
54 | struct gdbarch_tdep |
55 | { | |
56 | int a0_regnum; | |
57 | int nr_dmap_regs; | |
58 | unsigned long (*dmap_register) (int nr); | |
59 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
60 | }; |
61 | ||
62 | /* These are the addresses the D10V-EVA board maps data and | |
63 | instruction memory to. */ | |
cce74817 | 64 | |
cff3e48b | 65 | #define DMEM_START 0x2000000 |
cce74817 JM |
66 | #define IMEM_START 0x1000000 |
67 | #define STACK_START 0x0007ffe | |
68 | ||
4ce44c66 JM |
69 | /* d10v register names. */ |
70 | ||
71 | enum | |
72 | { | |
73 | R0_REGNUM = 0, | |
74 | LR_REGNUM = 13, | |
75 | PSW_REGNUM = 16, | |
76 | NR_IMAP_REGS = 2, | |
77 | NR_A_REGS = 2 | |
78 | }; | |
79 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
80 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
81 | ||
82 | /* d10v calling convention. */ | |
cce74817 JM |
83 | |
84 | #define ARG1_REGNUM R0_REGNUM | |
85 | #define ARGN_REGNUM 3 | |
86 | #define RET1_REGNUM R0_REGNUM | |
87 | ||
392a587b JM |
88 | /* Local functions */ |
89 | ||
a14ed312 | 90 | extern void _initialize_d10v_tdep (void); |
392a587b | 91 | |
a14ed312 | 92 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 93 | |
a14ed312 | 94 | static void d10v_eva_get_trace_data (void); |
c906108c | 95 | |
a14ed312 KB |
96 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
97 | CORE_ADDR addr); | |
cce74817 | 98 | |
a14ed312 | 99 | extern void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 100 | |
a14ed312 | 101 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 102 | |
c906108c | 103 | int |
72623009 | 104 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c SS |
105 | { |
106 | return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START); | |
107 | } | |
108 | ||
23964bcd | 109 | static CORE_ADDR |
489137c0 AC |
110 | d10v_stack_align (CORE_ADDR len) |
111 | { | |
112 | return (len + 1) & ~1; | |
113 | } | |
c906108c SS |
114 | |
115 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
116 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
117 | and TYPE is the type (which is known to be struct, union or array). | |
118 | ||
119 | The d10v returns anything less than 8 bytes in size in | |
120 | registers. */ | |
121 | ||
122 | int | |
fba45db2 | 123 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
124 | { |
125 | return (TYPE_LENGTH (type) > 8); | |
126 | } | |
127 | ||
128 | ||
392a587b | 129 | unsigned char * |
fba45db2 | 130 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 131 | { |
c5aa993b JM |
132 | static unsigned char breakpoint[] = |
133 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
134 | *lenptr = sizeof (breakpoint); |
135 | return breakpoint; | |
136 | } | |
137 | ||
4ce44c66 JM |
138 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
139 | when the reg_nr isn't valid. */ | |
140 | ||
141 | enum ts2_regnums | |
142 | { | |
143 | TS2_IMAP0_REGNUM = 32, | |
144 | TS2_DMAP_REGNUM = 34, | |
145 | TS2_NR_DMAP_REGS = 1, | |
146 | TS2_A0_REGNUM = 35 | |
147 | }; | |
148 | ||
149 | static char * | |
150 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 151 | { |
c5aa993b JM |
152 | static char *register_names[] = |
153 | { | |
154 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
155 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
156 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
157 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
158 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
159 | }; |
160 | if (reg_nr < 0) | |
161 | return NULL; | |
162 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
163 | return NULL; | |
c5aa993b | 164 | return register_names[reg_nr]; |
392a587b JM |
165 | } |
166 | ||
4ce44c66 JM |
167 | enum ts3_regnums |
168 | { | |
169 | TS3_IMAP0_REGNUM = 36, | |
170 | TS3_DMAP0_REGNUM = 38, | |
171 | TS3_NR_DMAP_REGS = 4, | |
172 | TS3_A0_REGNUM = 32 | |
173 | }; | |
174 | ||
175 | static char * | |
176 | d10v_ts3_register_name (int reg_nr) | |
177 | { | |
178 | static char *register_names[] = | |
179 | { | |
180 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
181 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
182 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
183 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
184 | "a0", "a1", | |
185 | "spi", "spu", | |
186 | "imap0", "imap1", | |
187 | "dmap0", "dmap1", "dmap2", "dmap3" | |
188 | }; | |
189 | if (reg_nr < 0) | |
190 | return NULL; | |
191 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
192 | return NULL; | |
193 | return register_names[reg_nr]; | |
194 | } | |
195 | ||
114d1f2c | 196 | /* Access the DMAP/IMAP registers in a target independent way. */ |
4ce44c66 JM |
197 | |
198 | static unsigned long | |
199 | d10v_ts2_dmap_register (int reg_nr) | |
200 | { | |
201 | switch (reg_nr) | |
202 | { | |
203 | case 0: | |
204 | case 1: | |
205 | return 0x2000; | |
206 | case 2: | |
207 | return read_register (TS2_DMAP_REGNUM); | |
208 | default: | |
209 | return 0; | |
210 | } | |
211 | } | |
212 | ||
213 | static unsigned long | |
214 | d10v_ts3_dmap_register (int reg_nr) | |
215 | { | |
216 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
217 | } | |
218 | ||
219 | static unsigned long | |
220 | d10v_dmap_register (int reg_nr) | |
221 | { | |
222 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
223 | } | |
224 | ||
225 | static unsigned long | |
226 | d10v_ts2_imap_register (int reg_nr) | |
227 | { | |
228 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
229 | } | |
230 | ||
231 | static unsigned long | |
232 | d10v_ts3_imap_register (int reg_nr) | |
233 | { | |
234 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
235 | } | |
236 | ||
237 | static unsigned long | |
238 | d10v_imap_register (int reg_nr) | |
239 | { | |
240 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
241 | } | |
242 | ||
243 | /* MAP GDB's internal register numbering (determined by the layout fo | |
244 | the REGISTER_BYTE array) onto the simulator's register | |
245 | numbering. */ | |
246 | ||
247 | static int | |
248 | d10v_ts2_register_sim_regno (int nr) | |
249 | { | |
250 | if (nr >= TS2_IMAP0_REGNUM | |
251 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
252 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
253 | if (nr == TS2_DMAP_REGNUM) | |
254 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
255 | if (nr >= TS2_A0_REGNUM | |
256 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
257 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
258 | return nr; | |
259 | } | |
260 | ||
261 | static int | |
262 | d10v_ts3_register_sim_regno (int nr) | |
263 | { | |
264 | if (nr >= TS3_IMAP0_REGNUM | |
265 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
266 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
267 | if (nr >= TS3_DMAP0_REGNUM | |
268 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
269 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
270 | if (nr >= TS3_A0_REGNUM | |
271 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
272 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
273 | return nr; | |
274 | } | |
275 | ||
392a587b JM |
276 | /* Index within `registers' of the first byte of the space for |
277 | register REG_NR. */ | |
278 | ||
279 | int | |
fba45db2 | 280 | d10v_register_byte (int reg_nr) |
392a587b | 281 | { |
4ce44c66 | 282 | if (reg_nr < A0_REGNUM) |
392a587b | 283 | return (reg_nr * 2); |
4ce44c66 JM |
284 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
285 | return (A0_REGNUM * 2 | |
286 | + (reg_nr - A0_REGNUM) * 8); | |
287 | else | |
288 | return (A0_REGNUM * 2 | |
289 | + NR_A_REGS * 8 | |
290 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
291 | } |
292 | ||
293 | /* Number of bytes of storage in the actual machine representation for | |
294 | register REG_NR. */ | |
295 | ||
296 | int | |
fba45db2 | 297 | d10v_register_raw_size (int reg_nr) |
392a587b | 298 | { |
4ce44c66 JM |
299 | if (reg_nr < A0_REGNUM) |
300 | return 2; | |
301 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
302 | return 8; |
303 | else | |
304 | return 2; | |
305 | } | |
306 | ||
307 | /* Number of bytes of storage in the program's representation | |
308 | for register N. */ | |
309 | ||
310 | int | |
fba45db2 | 311 | d10v_register_virtual_size (int reg_nr) |
392a587b | 312 | { |
4ce44c66 | 313 | return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr)); |
392a587b JM |
314 | } |
315 | ||
316 | /* Return the GDB type object for the "standard" data type | |
317 | of data in register N. */ | |
318 | ||
319 | struct type * | |
fba45db2 | 320 | d10v_register_virtual_type (int reg_nr) |
392a587b | 321 | { |
4ce44c66 JM |
322 | if (reg_nr >= A0_REGNUM |
323 | && reg_nr < (A0_REGNUM + NR_A_REGS)) | |
324 | return builtin_type_int64; | |
325 | else if (reg_nr == PC_REGNUM | |
326 | || reg_nr == SP_REGNUM) | |
327 | return builtin_type_int32; | |
392a587b | 328 | else |
4ce44c66 | 329 | return builtin_type_int16; |
392a587b JM |
330 | } |
331 | ||
392a587b | 332 | /* convert $pc and $sp to/from virtual addresses */ |
ac9a91a7 | 333 | int |
fba45db2 | 334 | d10v_register_convertible (int nr) |
ac9a91a7 JM |
335 | { |
336 | return ((nr) == PC_REGNUM || (nr) == SP_REGNUM); | |
337 | } | |
338 | ||
339 | void | |
fba45db2 KB |
340 | d10v_register_convert_to_virtual (int regnum, struct type *type, char *from, |
341 | char *to) | |
ac9a91a7 JM |
342 | { |
343 | ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum)); | |
344 | if (regnum == PC_REGNUM) | |
345 | x = (x << 2) | IMEM_START; | |
346 | else | |
347 | x |= DMEM_START; | |
348 | store_unsigned_integer (to, TYPE_LENGTH (type), x); | |
392a587b | 349 | } |
ac9a91a7 JM |
350 | |
351 | void | |
fba45db2 KB |
352 | d10v_register_convert_to_raw (struct type *type, int regnum, char *from, |
353 | char *to) | |
ac9a91a7 JM |
354 | { |
355 | ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type)); | |
356 | x &= 0x3ffff; | |
357 | if (regnum == PC_REGNUM) | |
358 | x >>= 2; | |
359 | store_unsigned_integer (to, 2, x); | |
392a587b | 360 | } |
ac9a91a7 | 361 | |
392a587b JM |
362 | |
363 | CORE_ADDR | |
fba45db2 | 364 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
365 | { |
366 | return ((x) | DMEM_START); | |
367 | } | |
368 | ||
369 | CORE_ADDR | |
fba45db2 | 370 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
371 | { |
372 | return (((x) << 2) | IMEM_START); | |
373 | } | |
374 | ||
375 | int | |
fba45db2 | 376 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
377 | { |
378 | return (((x) & 0x3000000) == DMEM_START); | |
379 | } | |
380 | ||
381 | int | |
fba45db2 | 382 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
383 | { |
384 | return (((x) & 0x3000000) == IMEM_START); | |
385 | } | |
386 | ||
387 | ||
388 | CORE_ADDR | |
fba45db2 | 389 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
390 | { |
391 | return (((x) >> 2) & 0xffff); | |
392 | } | |
393 | ||
394 | CORE_ADDR | |
fba45db2 | 395 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
396 | { |
397 | return ((x) & 0xffff); | |
398 | } | |
399 | ||
400 | /* Store the address of the place in which to copy the structure the | |
401 | subroutine will return. This is called from call_function. | |
402 | ||
403 | We store structs through a pointer passed in the first Argument | |
404 | register. */ | |
405 | ||
406 | void | |
fba45db2 | 407 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
408 | { |
409 | write_register (ARG1_REGNUM, (addr)); | |
410 | } | |
411 | ||
412 | /* Write into appropriate registers a function return value | |
413 | of type TYPE, given in virtual format. | |
414 | ||
415 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
416 | ||
417 | void | |
fba45db2 | 418 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
419 | { |
420 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
421 | valbuf, | |
422 | TYPE_LENGTH (type)); | |
423 | } | |
424 | ||
425 | /* Extract from an array REGBUF containing the (raw) register state | |
426 | the address in which a function should return its structure value, | |
427 | as a CORE_ADDR (or an expression that can be used as one). */ | |
428 | ||
429 | CORE_ADDR | |
fba45db2 | 430 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
431 | { |
432 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
433 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
434 | | DMEM_START); | |
435 | } | |
436 | ||
437 | CORE_ADDR | |
fba45db2 | 438 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 439 | { |
cce74817 | 440 | return ((frame)->extra_info->return_pc); |
392a587b JM |
441 | } |
442 | ||
392a587b JM |
443 | /* Immediately after a function call, return the saved pc. We can't |
444 | use frame->return_pc beause that is determined by reading R13 off | |
445 | the stack and that may not be written yet. */ | |
446 | ||
447 | CORE_ADDR | |
fba45db2 | 448 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 449 | { |
c5aa993b | 450 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
451 | | IMEM_START); |
452 | } | |
453 | ||
c906108c SS |
454 | /* Discard from the stack the innermost frame, restoring all saved |
455 | registers. */ | |
456 | ||
457 | void | |
fba45db2 | 458 | d10v_pop_frame (void) |
cce74817 JM |
459 | { |
460 | generic_pop_current_frame (do_d10v_pop_frame); | |
461 | } | |
462 | ||
463 | static void | |
fba45db2 | 464 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
465 | { |
466 | CORE_ADDR fp; | |
467 | int regnum; | |
c906108c SS |
468 | char raw_buffer[8]; |
469 | ||
cce74817 | 470 | fp = FRAME_FP (fi); |
c906108c SS |
471 | /* fill out fsr with the address of where each */ |
472 | /* register was stored in the frame */ | |
cce74817 | 473 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 474 | |
c906108c | 475 | /* now update the current registers with the old values */ |
4ce44c66 | 476 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 477 | { |
cce74817 | 478 | if (fi->saved_regs[regnum]) |
c906108c | 479 | { |
c5aa993b JM |
480 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
481 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
482 | } |
483 | } | |
484 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
485 | { | |
cce74817 | 486 | if (fi->saved_regs[regnum]) |
c906108c | 487 | { |
c5aa993b | 488 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
489 | } |
490 | } | |
cce74817 | 491 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 492 | { |
c5aa993b | 493 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
494 | } |
495 | ||
496 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 497 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
498 | target_store_registers (-1); |
499 | flush_cached_frames (); | |
500 | } | |
501 | ||
c5aa993b | 502 | static int |
fba45db2 | 503 | check_prologue (unsigned short op) |
c906108c SS |
504 | { |
505 | /* st rn, @-sp */ | |
506 | if ((op & 0x7E1F) == 0x6C1F) | |
507 | return 1; | |
508 | ||
509 | /* st2w rn, @-sp */ | |
510 | if ((op & 0x7E3F) == 0x6E1F) | |
511 | return 1; | |
512 | ||
513 | /* subi sp, n */ | |
514 | if ((op & 0x7FE1) == 0x01E1) | |
515 | return 1; | |
516 | ||
517 | /* mv r11, sp */ | |
518 | if (op == 0x417E) | |
519 | return 1; | |
520 | ||
521 | /* nop */ | |
522 | if (op == 0x5E00) | |
523 | return 1; | |
524 | ||
525 | /* st rn, @sp */ | |
526 | if ((op & 0x7E1F) == 0x681E) | |
527 | return 1; | |
528 | ||
529 | /* st2w rn, @sp */ | |
c5aa993b JM |
530 | if ((op & 0x7E3F) == 0x3A1E) |
531 | return 1; | |
c906108c SS |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
536 | CORE_ADDR | |
fba45db2 | 537 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
538 | { |
539 | unsigned long op; | |
540 | unsigned short op1, op2; | |
541 | CORE_ADDR func_addr, func_end; | |
542 | struct symtab_and_line sal; | |
543 | ||
544 | /* If we have line debugging information, then the end of the */ | |
545 | /* prologue should the first assembly instruction of the first source line */ | |
546 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
547 | { | |
548 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 549 | if (sal.end && sal.end < func_end) |
c906108c SS |
550 | return sal.end; |
551 | } | |
c5aa993b JM |
552 | |
553 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
554 | return pc; /* Can't access it -- assume no prologue. */ |
555 | ||
556 | while (1) | |
557 | { | |
c5aa993b | 558 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
559 | if ((op & 0xC0000000) == 0xC0000000) |
560 | { | |
561 | /* long instruction */ | |
c5aa993b JM |
562 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
563 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
564 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
565 | break; |
566 | } | |
567 | else | |
568 | { | |
569 | /* short instructions */ | |
570 | if ((op & 0xC0000000) == 0x80000000) | |
571 | { | |
572 | op2 = (op & 0x3FFF8000) >> 15; | |
573 | op1 = op & 0x7FFF; | |
c5aa993b JM |
574 | } |
575 | else | |
c906108c SS |
576 | { |
577 | op1 = (op & 0x3FFF8000) >> 15; | |
578 | op2 = op & 0x7FFF; | |
579 | } | |
c5aa993b | 580 | if (check_prologue (op1)) |
c906108c | 581 | { |
c5aa993b | 582 | if (!check_prologue (op2)) |
c906108c SS |
583 | { |
584 | /* if the previous opcode was really part of the prologue */ | |
585 | /* and not just a NOP, then we want to break after both instructions */ | |
586 | if (op1 != 0x5E00) | |
587 | pc += 4; | |
588 | break; | |
589 | } | |
590 | } | |
591 | else | |
592 | break; | |
593 | } | |
594 | pc += 4; | |
595 | } | |
596 | return pc; | |
597 | } | |
598 | ||
599 | /* Given a GDB frame, determine the address of the calling function's frame. | |
600 | This will be used to create a new GDB frame struct, and then | |
601 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 602 | */ |
c906108c SS |
603 | |
604 | CORE_ADDR | |
fba45db2 | 605 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 606 | { |
cce74817 | 607 | d10v_frame_init_saved_regs (fi); |
c906108c | 608 | |
cce74817 JM |
609 | if (fi->extra_info->return_pc == IMEM_START |
610 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 611 | return (CORE_ADDR) 0; |
c906108c | 612 | |
cce74817 | 613 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 614 | { |
cce74817 JM |
615 | if (!fi->saved_regs[SP_REGNUM] |
616 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
617 | return (CORE_ADDR) 0; |
618 | ||
cce74817 | 619 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
620 | } |
621 | ||
c5aa993b JM |
622 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
623 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
624 | return (CORE_ADDR) 0; | |
c906108c | 625 | |
cce74817 | 626 | return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
627 | REGISTER_RAW_SIZE (FP_REGNUM))); |
628 | } | |
c906108c SS |
629 | |
630 | static int next_addr, uses_frame; | |
631 | ||
c5aa993b | 632 | static int |
fba45db2 | 633 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
634 | { |
635 | int n; | |
636 | ||
637 | /* st rn, @-sp */ | |
638 | if ((op & 0x7E1F) == 0x6C1F) | |
639 | { | |
640 | n = (op & 0x1E0) >> 5; | |
641 | next_addr -= 2; | |
cce74817 | 642 | fi->saved_regs[n] = next_addr; |
c906108c SS |
643 | return 1; |
644 | } | |
645 | ||
646 | /* st2w rn, @-sp */ | |
647 | else if ((op & 0x7E3F) == 0x6E1F) | |
648 | { | |
649 | n = (op & 0x1E0) >> 5; | |
650 | next_addr -= 4; | |
cce74817 | 651 | fi->saved_regs[n] = next_addr; |
c5aa993b | 652 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
653 | return 1; |
654 | } | |
655 | ||
656 | /* subi sp, n */ | |
657 | if ((op & 0x7FE1) == 0x01E1) | |
658 | { | |
659 | n = (op & 0x1E) >> 1; | |
660 | if (n == 0) | |
661 | n = 16; | |
662 | next_addr -= n; | |
663 | return 1; | |
664 | } | |
665 | ||
666 | /* mv r11, sp */ | |
667 | if (op == 0x417E) | |
668 | { | |
669 | uses_frame = 1; | |
670 | return 1; | |
671 | } | |
672 | ||
673 | /* nop */ | |
674 | if (op == 0x5E00) | |
675 | return 1; | |
676 | ||
677 | /* st rn, @sp */ | |
678 | if ((op & 0x7E1F) == 0x681E) | |
679 | { | |
680 | n = (op & 0x1E0) >> 5; | |
cce74817 | 681 | fi->saved_regs[n] = next_addr; |
c906108c SS |
682 | return 1; |
683 | } | |
684 | ||
685 | /* st2w rn, @sp */ | |
686 | if ((op & 0x7E3F) == 0x3A1E) | |
687 | { | |
688 | n = (op & 0x1E0) >> 5; | |
cce74817 | 689 | fi->saved_regs[n] = next_addr; |
c5aa993b | 690 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
691 | return 1; |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
cce74817 JM |
697 | /* Put here the code to store, into fi->saved_regs, the addresses of |
698 | the saved registers of frame described by FRAME_INFO. This | |
699 | includes special registers such as pc and fp saved in special ways | |
700 | in the stack frame. sp is even more special: the address we return | |
701 | for it IS the sp for the next frame. */ | |
702 | ||
c906108c | 703 | void |
fba45db2 | 704 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
705 | { |
706 | CORE_ADDR fp, pc; | |
707 | unsigned long op; | |
708 | unsigned short op1, op2; | |
709 | int i; | |
710 | ||
711 | fp = fi->frame; | |
cce74817 | 712 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
713 | next_addr = 0; |
714 | ||
715 | pc = get_pc_function_start (fi->pc); | |
716 | ||
717 | uses_frame = 0; | |
718 | while (1) | |
719 | { | |
c5aa993b | 720 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
721 | if ((op & 0xC0000000) == 0xC0000000) |
722 | { | |
723 | /* long instruction */ | |
724 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
725 | { | |
726 | /* add3 sp,sp,n */ | |
727 | short n = op & 0xFFFF; | |
728 | next_addr += n; | |
729 | } | |
730 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
731 | { | |
732 | /* st rn, @(offset,sp) */ | |
733 | short offset = op & 0xFFFF; | |
734 | short n = (op >> 20) & 0xF; | |
cce74817 | 735 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
736 | } |
737 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
738 | { | |
739 | /* st2w rn, @(offset,sp) */ | |
740 | short offset = op & 0xFFFF; | |
741 | short n = (op >> 20) & 0xF; | |
cce74817 | 742 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 743 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
744 | } |
745 | else | |
746 | break; | |
747 | } | |
748 | else | |
749 | { | |
750 | /* short instructions */ | |
751 | if ((op & 0xC0000000) == 0x80000000) | |
752 | { | |
753 | op2 = (op & 0x3FFF8000) >> 15; | |
754 | op1 = op & 0x7FFF; | |
c5aa993b JM |
755 | } |
756 | else | |
c906108c SS |
757 | { |
758 | op1 = (op & 0x3FFF8000) >> 15; | |
759 | op2 = op & 0x7FFF; | |
760 | } | |
c5aa993b | 761 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
762 | break; |
763 | } | |
764 | pc += 4; | |
765 | } | |
c5aa993b | 766 | |
cce74817 | 767 | fi->extra_info->size = -next_addr; |
c906108c SS |
768 | |
769 | if (!(fp & 0xffff)) | |
c5aa993b | 770 | fp = D10V_MAKE_DADDR (read_register (SP_REGNUM)); |
c906108c | 771 | |
c5aa993b | 772 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 773 | if (fi->saved_regs[i]) |
c906108c | 774 | { |
c5aa993b | 775 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
776 | } |
777 | ||
cce74817 | 778 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 779 | { |
cce74817 JM |
780 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
781 | fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc); | |
c906108c SS |
782 | } |
783 | else | |
784 | { | |
c5aa993b | 785 | fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM)); |
c906108c | 786 | } |
c5aa993b | 787 | |
c906108c | 788 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 789 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
790 | { |
791 | /* if the FP was saved, that means the current FP is valid, */ | |
792 | /* otherwise, it isn't being used, so we use the SP instead */ | |
793 | if (uses_frame) | |
c5aa993b | 794 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
795 | else |
796 | { | |
cce74817 JM |
797 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
798 | fi->extra_info->frameless = 1; | |
799 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
800 | } |
801 | } | |
802 | } | |
803 | ||
804 | void | |
fba45db2 | 805 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 806 | { |
cce74817 JM |
807 | fi->extra_info = (struct frame_extra_info *) |
808 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
809 | frame_saved_regs_zalloc (fi); | |
810 | ||
811 | fi->extra_info->frameless = 0; | |
812 | fi->extra_info->size = 0; | |
813 | fi->extra_info->return_pc = 0; | |
c906108c SS |
814 | |
815 | /* The call dummy doesn't save any registers on the stack, so we can | |
816 | return now. */ | |
817 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
818 | { | |
819 | return; | |
820 | } | |
821 | else | |
822 | { | |
cce74817 | 823 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
824 | } |
825 | } | |
826 | ||
827 | static void | |
fba45db2 | 828 | show_regs (char *args, int from_tty) |
c906108c SS |
829 | { |
830 | int a; | |
d4f3574e SS |
831 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
832 | (long) read_register (PC_REGNUM), | |
833 | (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)), | |
834 | (long) read_register (PSW_REGNUM), | |
835 | (long) read_register (24), | |
836 | (long) read_register (25), | |
837 | (long) read_register (23)); | |
838 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
839 | (long) read_register (0), | |
840 | (long) read_register (1), | |
841 | (long) read_register (2), | |
842 | (long) read_register (3), | |
843 | (long) read_register (4), | |
844 | (long) read_register (5), | |
845 | (long) read_register (6), | |
846 | (long) read_register (7)); | |
847 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
848 | (long) read_register (8), | |
849 | (long) read_register (9), | |
850 | (long) read_register (10), | |
851 | (long) read_register (11), | |
852 | (long) read_register (12), | |
853 | (long) read_register (13), | |
854 | (long) read_register (14), | |
855 | (long) read_register (15)); | |
4ce44c66 JM |
856 | for (a = 0; a < NR_IMAP_REGS; a++) |
857 | { | |
858 | if (a > 0) | |
859 | printf_filtered (" "); | |
860 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
861 | } | |
862 | if (NR_DMAP_REGS == 1) | |
863 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
864 | else | |
865 | { | |
866 | for (a = 0; a < NR_DMAP_REGS; a++) | |
867 | { | |
868 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
869 | } | |
870 | printf_filtered ("\n"); | |
871 | } | |
872 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
873 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
874 | { |
875 | char num[MAX_REGISTER_RAW_SIZE]; | |
876 | int i; | |
877 | printf_filtered (" "); | |
c5aa993b | 878 | read_register_gen (a, (char *) &num); |
c906108c SS |
879 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
880 | { | |
881 | printf_filtered ("%02x", (num[i] & 0xff)); | |
882 | } | |
883 | } | |
884 | printf_filtered ("\n"); | |
885 | } | |
886 | ||
887 | CORE_ADDR | |
fba45db2 | 888 | d10v_read_pc (int pid) |
c906108c SS |
889 | { |
890 | int save_pid; | |
891 | CORE_ADDR pc; | |
892 | CORE_ADDR retval; | |
893 | ||
894 | save_pid = inferior_pid; | |
895 | inferior_pid = pid; | |
896 | pc = (int) read_register (PC_REGNUM); | |
897 | inferior_pid = save_pid; | |
898 | retval = D10V_MAKE_IADDR (pc); | |
899 | return retval; | |
900 | } | |
901 | ||
902 | void | |
fba45db2 | 903 | d10v_write_pc (CORE_ADDR val, int pid) |
c906108c SS |
904 | { |
905 | int save_pid; | |
906 | ||
907 | save_pid = inferior_pid; | |
908 | inferior_pid = pid; | |
909 | write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val)); | |
910 | inferior_pid = save_pid; | |
911 | } | |
912 | ||
913 | CORE_ADDR | |
fba45db2 | 914 | d10v_read_sp (void) |
c906108c SS |
915 | { |
916 | return (D10V_MAKE_DADDR (read_register (SP_REGNUM))); | |
917 | } | |
918 | ||
919 | void | |
fba45db2 | 920 | d10v_write_sp (CORE_ADDR val) |
c906108c SS |
921 | { |
922 | write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
923 | } | |
924 | ||
925 | void | |
fba45db2 | 926 | d10v_write_fp (CORE_ADDR val) |
c906108c SS |
927 | { |
928 | write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
929 | } | |
930 | ||
931 | CORE_ADDR | |
fba45db2 | 932 | d10v_read_fp (void) |
c906108c | 933 | { |
c5aa993b | 934 | return (D10V_MAKE_DADDR (read_register (FP_REGNUM))); |
c906108c SS |
935 | } |
936 | ||
937 | /* Function: push_return_address (pc) | |
938 | Set up the return address for the inferior function call. | |
939 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 940 | |
c906108c | 941 | CORE_ADDR |
fba45db2 | 942 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c SS |
943 | { |
944 | write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); | |
945 | return sp; | |
946 | } | |
c5aa993b | 947 | |
c906108c | 948 | |
7a292a7a SS |
949 | /* When arguments must be pushed onto the stack, they go on in reverse |
950 | order. The below implements a FILO (stack) to do this. */ | |
951 | ||
952 | struct stack_item | |
953 | { | |
954 | int len; | |
955 | struct stack_item *prev; | |
956 | void *data; | |
957 | }; | |
958 | ||
a14ed312 KB |
959 | static struct stack_item *push_stack_item (struct stack_item *prev, |
960 | void *contents, int len); | |
7a292a7a | 961 | static struct stack_item * |
fba45db2 | 962 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
963 | { |
964 | struct stack_item *si; | |
965 | si = xmalloc (sizeof (struct stack_item)); | |
966 | si->data = xmalloc (len); | |
967 | si->len = len; | |
968 | si->prev = prev; | |
969 | memcpy (si->data, contents, len); | |
970 | return si; | |
971 | } | |
972 | ||
a14ed312 | 973 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 974 | static struct stack_item * |
fba45db2 | 975 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
976 | { |
977 | struct stack_item *dead = si; | |
978 | si = si->prev; | |
b8c9b27d KB |
979 | xfree (dead->data); |
980 | xfree (dead); | |
7a292a7a SS |
981 | return si; |
982 | } | |
983 | ||
984 | ||
c906108c | 985 | CORE_ADDR |
fba45db2 KB |
986 | d10v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp, |
987 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
988 | { |
989 | int i; | |
990 | int regnum = ARG1_REGNUM; | |
7a292a7a | 991 | struct stack_item *si = NULL; |
c5aa993b | 992 | |
c906108c SS |
993 | /* Fill in registers and arg lists */ |
994 | for (i = 0; i < nargs; i++) | |
995 | { | |
996 | value_ptr arg = args[i]; | |
997 | struct type *type = check_typedef (VALUE_TYPE (arg)); | |
998 | char *contents = VALUE_CONTENTS (arg); | |
999 | int len = TYPE_LENGTH (type); | |
1000 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
1001 | if (TYPE_CODE (type) == TYPE_CODE_PTR) | |
1002 | { | |
1003 | /* pointers require special handling - first convert and | |
1004 | then store */ | |
1005 | long val = extract_signed_integer (contents, len); | |
1006 | len = 2; | |
1007 | if (TYPE_TARGET_TYPE (type) | |
1008 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1009 | { | |
1010 | /* function pointer */ | |
1011 | val = D10V_CONVERT_IADDR_TO_RAW (val); | |
1012 | } | |
1013 | else if (D10V_IADDR_P (val)) | |
1014 | { | |
1015 | /* also function pointer! */ | |
1016 | val = D10V_CONVERT_DADDR_TO_RAW (val); | |
1017 | } | |
1018 | else | |
1019 | { | |
1020 | /* data pointer */ | |
1021 | val &= 0xFFFF; | |
1022 | } | |
1023 | if (regnum <= ARGN_REGNUM) | |
1024 | write_register (regnum++, val & 0xffff); | |
1025 | else | |
1026 | { | |
1027 | char ptr[2]; | |
7a292a7a | 1028 | /* arg will go onto stack */ |
0f71a2f6 | 1029 | store_address (ptr, 2, val & 0xffff); |
7a292a7a | 1030 | si = push_stack_item (si, ptr, 2); |
c906108c SS |
1031 | } |
1032 | } | |
1033 | else | |
1034 | { | |
1035 | int aligned_regnum = (regnum + 1) & ~1; | |
1036 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1037 | /* fits in a single register, do not align */ | |
1038 | { | |
1039 | long val = extract_unsigned_integer (contents, len); | |
1040 | write_register (regnum++, val); | |
1041 | } | |
1042 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1043 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1044 | aligned */ |
c906108c SS |
1045 | { |
1046 | int b; | |
1047 | regnum = aligned_regnum; | |
1048 | for (b = 0; b < (len & ~1); b += 2) | |
1049 | { | |
1050 | long val = extract_unsigned_integer (&contents[b], 2); | |
1051 | write_register (regnum++, val); | |
1052 | } | |
1053 | if (b < len) | |
1054 | { | |
1055 | long val = extract_unsigned_integer (&contents[b], 1); | |
1056 | write_register (regnum++, (val << 8)); | |
1057 | } | |
1058 | } | |
1059 | else | |
1060 | { | |
7a292a7a | 1061 | /* arg will go onto stack */ |
c5aa993b | 1062 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1063 | si = push_stack_item (si, contents, len); |
c906108c SS |
1064 | } |
1065 | } | |
1066 | } | |
7a292a7a SS |
1067 | |
1068 | while (si) | |
1069 | { | |
1070 | sp = (sp - si->len) & ~1; | |
1071 | write_memory (sp, si->data, si->len); | |
1072 | si = pop_stack_item (si); | |
1073 | } | |
c5aa993b | 1074 | |
c906108c SS |
1075 | return sp; |
1076 | } | |
1077 | ||
1078 | ||
1079 | /* Given a return value in `regbuf' with a type `valtype', | |
1080 | extract and copy its value into `valbuf'. */ | |
1081 | ||
1082 | void | |
72623009 KB |
1083 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1084 | char *valbuf) | |
c906108c SS |
1085 | { |
1086 | int len; | |
1087 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
1088 | if (TYPE_CODE (type) == TYPE_CODE_PTR | |
1089 | && TYPE_TARGET_TYPE (type) | |
1090 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1091 | { | |
1092 | /* pointer to function */ | |
1093 | int num; | |
1094 | short snum; | |
1095 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1096 | store_address (valbuf, 4, D10V_MAKE_IADDR (snum)); |
c906108c | 1097 | } |
c5aa993b | 1098 | else if (TYPE_CODE (type) == TYPE_CODE_PTR) |
c906108c SS |
1099 | { |
1100 | /* pointer to data */ | |
1101 | int num; | |
1102 | short snum; | |
1103 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1104 | store_address (valbuf, 4, D10V_MAKE_DADDR (snum)); |
c906108c SS |
1105 | } |
1106 | else | |
1107 | { | |
1108 | len = TYPE_LENGTH (type); | |
1109 | if (len == 1) | |
1110 | { | |
1111 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1112 | store_unsigned_integer (valbuf, 1, c); | |
1113 | } | |
1114 | else if ((len & 1) == 0) | |
1115 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1116 | else | |
1117 | { | |
1118 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1119 | least significant part of the first register. The |
1120 | remaining bytes in remaining registers. Interestingly, | |
1121 | when such values are passed in, the last byte is in the | |
1122 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1123 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1124 | } | |
1125 | } | |
1126 | } | |
1127 | ||
c2c6d25f JM |
1128 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1129 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1130 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1131 | (segmentation fault). Since the simulator knows all about how the | |
1132 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1133 | |
4ce44c66 | 1134 | static void |
c2c6d25f JM |
1135 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1136 | CORE_ADDR *targ_addr, int *targ_len) | |
1137 | { | |
4ce44c66 JM |
1138 | long out_addr; |
1139 | long out_len; | |
1140 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1141 | &out_addr, | |
1142 | d10v_dmap_register, | |
1143 | d10v_imap_register); | |
1144 | *targ_addr = out_addr; | |
1145 | *targ_len = out_len; | |
c2c6d25f JM |
1146 | } |
1147 | ||
4ce44c66 | 1148 | |
c906108c SS |
1149 | /* The following code implements access to, and display of, the D10V's |
1150 | instruction trace buffer. The buffer consists of 64K or more | |
1151 | 4-byte words of data, of which each words includes an 8-bit count, | |
1152 | an 8-bit segment number, and a 16-bit instruction address. | |
1153 | ||
1154 | In theory, the trace buffer is continuously capturing instruction | |
1155 | data that the CPU presents on its "debug bus", but in practice, the | |
1156 | ROMified GDB stub only enables tracing when it continues or steps | |
1157 | the program, and stops tracing when the program stops; so it | |
1158 | actually works for GDB to read the buffer counter out of memory and | |
1159 | then read each trace word. The counter records where the tracing | |
1160 | stops, but there is no record of where it started, so we remember | |
1161 | the PC when we resumed and then search backwards in the trace | |
1162 | buffer for a word that includes that address. This is not perfect, | |
1163 | because you will miss trace data if the resumption PC is the target | |
1164 | of a branch. (The value of the buffer counter is semi-random, any | |
1165 | trace data from a previous program stop is gone.) */ | |
1166 | ||
1167 | /* The address of the last word recorded in the trace buffer. */ | |
1168 | ||
1169 | #define DBBC_ADDR (0xd80000) | |
1170 | ||
1171 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1172 | ||
1173 | #define TRACE_BUFFER_BASE (0xf40000) | |
1174 | ||
a14ed312 | 1175 | static void trace_command (char *, int); |
c906108c | 1176 | |
a14ed312 | 1177 | static void untrace_command (char *, int); |
c906108c | 1178 | |
a14ed312 | 1179 | static void trace_info (char *, int); |
c906108c | 1180 | |
a14ed312 | 1181 | static void tdisassemble_command (char *, int); |
c906108c | 1182 | |
a14ed312 | 1183 | static void display_trace (int, int); |
c906108c SS |
1184 | |
1185 | /* True when instruction traces are being collected. */ | |
1186 | ||
1187 | static int tracing; | |
1188 | ||
1189 | /* Remembered PC. */ | |
1190 | ||
1191 | static CORE_ADDR last_pc; | |
1192 | ||
1193 | /* True when trace output should be displayed whenever program stops. */ | |
1194 | ||
1195 | static int trace_display; | |
1196 | ||
1197 | /* True when trace listing should include source lines. */ | |
1198 | ||
1199 | static int default_trace_show_source = 1; | |
1200 | ||
c5aa993b JM |
1201 | struct trace_buffer |
1202 | { | |
1203 | int size; | |
1204 | short *counts; | |
1205 | CORE_ADDR *addrs; | |
1206 | } | |
1207 | trace_data; | |
c906108c SS |
1208 | |
1209 | static void | |
fba45db2 | 1210 | trace_command (char *args, int from_tty) |
c906108c SS |
1211 | { |
1212 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1213 | trace_data.size = 0; | |
1214 | if (trace_data.counts == NULL) | |
c5aa993b | 1215 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1216 | if (trace_data.addrs == NULL) |
c5aa993b | 1217 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1218 | |
1219 | tracing = 1; | |
1220 | ||
1221 | printf_filtered ("Tracing is now on.\n"); | |
1222 | } | |
1223 | ||
1224 | static void | |
fba45db2 | 1225 | untrace_command (char *args, int from_tty) |
c906108c SS |
1226 | { |
1227 | tracing = 0; | |
1228 | ||
1229 | printf_filtered ("Tracing is now off.\n"); | |
1230 | } | |
1231 | ||
1232 | static void | |
fba45db2 | 1233 | trace_info (char *args, int from_tty) |
c906108c SS |
1234 | { |
1235 | int i; | |
1236 | ||
1237 | if (trace_data.size) | |
1238 | { | |
1239 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1240 | ||
1241 | for (i = 0; i < trace_data.size; ++i) | |
1242 | { | |
d4f3574e SS |
1243 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1244 | i, | |
1245 | trace_data.counts[i], | |
c906108c | 1246 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1247 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1248 | } |
1249 | } | |
1250 | else | |
1251 | printf_filtered ("No entries in trace buffer.\n"); | |
1252 | ||
1253 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1254 | } | |
1255 | ||
1256 | /* Print the instruction at address MEMADDR in debugged memory, | |
1257 | on STREAM. Returns length of the instruction, in bytes. */ | |
1258 | ||
1259 | static int | |
fba45db2 | 1260 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1261 | { |
1262 | /* If there's no disassembler, something is very wrong. */ | |
1263 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1264 | internal_error (__FILE__, __LINE__, |
1265 | "print_insn: no disassembler"); | |
c906108c SS |
1266 | |
1267 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1268 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; | |
1269 | else | |
1270 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
1271 | return (*tm_print_insn) (memaddr, &tm_print_insn_info); | |
1272 | } | |
1273 | ||
392a587b | 1274 | static void |
fba45db2 | 1275 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1276 | { |
1277 | if (!tracing) | |
1278 | return; | |
1279 | ||
1280 | last_pc = read_register (PC_REGNUM); | |
1281 | } | |
1282 | ||
1283 | /* Collect trace data from the target board and format it into a form | |
1284 | more useful for display. */ | |
1285 | ||
392a587b | 1286 | static void |
fba45db2 | 1287 | d10v_eva_get_trace_data (void) |
c906108c SS |
1288 | { |
1289 | int count, i, j, oldsize; | |
1290 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1291 | unsigned int last_trace, trace_word, next_word; | |
1292 | unsigned int *tmpspace; | |
1293 | ||
1294 | if (!tracing) | |
1295 | return; | |
1296 | ||
c5aa993b | 1297 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1298 | |
1299 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1300 | ||
1301 | /* Collect buffer contents from the target, stopping when we reach | |
1302 | the word recorded when execution resumed. */ | |
1303 | ||
1304 | count = 0; | |
1305 | while (last_trace > 0) | |
1306 | { | |
1307 | QUIT; | |
1308 | trace_word = | |
1309 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1310 | trace_addr = trace_word & 0xffff; | |
1311 | last_trace -= 4; | |
1312 | /* Ignore an apparently nonsensical entry. */ | |
1313 | if (trace_addr == 0xffd5) | |
1314 | continue; | |
1315 | tmpspace[count++] = trace_word; | |
1316 | if (trace_addr == last_pc) | |
1317 | break; | |
1318 | if (count > 65535) | |
1319 | break; | |
1320 | } | |
1321 | ||
1322 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1323 | include the last instruction executed and transforming the address | |
1324 | into something that GDB likes. */ | |
1325 | ||
1326 | for (i = 0; i < count; ++i) | |
1327 | { | |
1328 | trace_word = tmpspace[i]; | |
1329 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1330 | trace_addr = trace_word & 0xffff; | |
1331 | next_cnt = (next_word >> 24) & 0xff; | |
1332 | j = trace_data.size + count - i - 1; | |
1333 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1334 | trace_data.counts[j] = next_cnt + 1; | |
1335 | } | |
1336 | ||
1337 | oldsize = trace_data.size; | |
1338 | trace_data.size += count; | |
1339 | ||
b8c9b27d | 1340 | xfree (tmpspace); |
c906108c SS |
1341 | |
1342 | if (trace_display) | |
1343 | display_trace (oldsize, trace_data.size); | |
1344 | } | |
1345 | ||
1346 | static void | |
fba45db2 | 1347 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1348 | { |
1349 | int i, count; | |
1350 | CORE_ADDR low, high; | |
1351 | char *space_index; | |
1352 | ||
1353 | if (!arg) | |
1354 | { | |
1355 | low = 0; | |
1356 | high = trace_data.size; | |
1357 | } | |
1358 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1359 | { | |
1360 | low = parse_and_eval_address (arg); | |
1361 | high = low + 5; | |
1362 | } | |
1363 | else | |
1364 | { | |
1365 | /* Two arguments. */ | |
1366 | *space_index = '\0'; | |
1367 | low = parse_and_eval_address (arg); | |
1368 | high = parse_and_eval_address (space_index + 1); | |
1369 | if (high < low) | |
1370 | high = low; | |
1371 | } | |
1372 | ||
d4f3574e | 1373 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1374 | |
1375 | display_trace (low, high); | |
1376 | ||
1377 | printf_filtered ("End of trace dump.\n"); | |
1378 | gdb_flush (gdb_stdout); | |
1379 | } | |
1380 | ||
1381 | static void | |
fba45db2 | 1382 | display_trace (int low, int high) |
c906108c SS |
1383 | { |
1384 | int i, count, trace_show_source, first, suppress; | |
1385 | CORE_ADDR next_address; | |
1386 | ||
1387 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1388 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1389 | { |
1390 | trace_show_source = 0; | |
1391 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1392 | printf_filtered ("Trace will not display any source.\n"); | |
1393 | } | |
1394 | ||
1395 | first = 1; | |
1396 | suppress = 0; | |
1397 | for (i = low; i < high; ++i) | |
1398 | { | |
1399 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1400 | count = trace_data.counts[i]; |
c906108c SS |
1401 | while (count-- > 0) |
1402 | { | |
1403 | QUIT; | |
1404 | if (trace_show_source) | |
1405 | { | |
1406 | struct symtab_and_line sal, sal_prev; | |
1407 | ||
1408 | sal_prev = find_pc_line (next_address - 4, 0); | |
1409 | sal = find_pc_line (next_address, 0); | |
1410 | ||
1411 | if (sal.symtab) | |
1412 | { | |
1413 | if (first || sal.line != sal_prev.line) | |
1414 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1415 | suppress = 0; | |
1416 | } | |
1417 | else | |
1418 | { | |
1419 | if (!suppress) | |
1420 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1421 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1422 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1423 | suppress = 1; |
1424 | } | |
1425 | } | |
1426 | first = 0; | |
1427 | print_address (next_address, gdb_stdout); | |
1428 | printf_filtered (":"); | |
1429 | printf_filtered ("\t"); | |
1430 | wrap_here (" "); | |
1431 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1432 | printf_filtered ("\n"); | |
1433 | gdb_flush (gdb_stdout); | |
1434 | } | |
1435 | } | |
1436 | } | |
1437 | ||
ac9a91a7 | 1438 | |
0f71a2f6 | 1439 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1440 | |
0f71a2f6 | 1441 | static struct gdbarch * |
fba45db2 | 1442 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1443 | { |
c5aa993b JM |
1444 | static LONGEST d10v_call_dummy_words[] = |
1445 | {0}; | |
0f71a2f6 | 1446 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1447 | int d10v_num_regs; |
1448 | struct gdbarch_tdep *tdep; | |
1449 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1450 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1451 | |
4ce44c66 JM |
1452 | /* Find a candidate among the list of pre-declared architectures. */ |
1453 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1454 | if (arches != NULL) |
1455 | return arches->gdbarch; | |
4ce44c66 JM |
1456 | |
1457 | /* None found, create a new architecture from the information | |
1458 | provided. */ | |
1459 | tdep = XMALLOC (struct gdbarch_tdep); | |
1460 | gdbarch = gdbarch_alloc (&info, tdep); | |
1461 | ||
1462 | switch (info.bfd_arch_info->mach) | |
1463 | { | |
1464 | case bfd_mach_d10v_ts2: | |
1465 | d10v_num_regs = 37; | |
1466 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1467 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1468 | tdep->a0_regnum = TS2_A0_REGNUM; |
1469 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1470 | tdep->dmap_register = d10v_ts2_dmap_register; |
1471 | tdep->imap_register = d10v_ts2_imap_register; | |
1472 | break; | |
1473 | default: | |
1474 | case bfd_mach_d10v_ts3: | |
1475 | d10v_num_regs = 42; | |
1476 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1477 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1478 | tdep->a0_regnum = TS3_A0_REGNUM; |
1479 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1480 | tdep->dmap_register = d10v_ts3_dmap_register; |
1481 | tdep->imap_register = d10v_ts3_imap_register; | |
1482 | break; | |
1483 | } | |
0f71a2f6 JM |
1484 | |
1485 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1486 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1487 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1488 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1489 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1490 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1491 | ||
1492 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1493 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1494 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1495 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1496 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1497 | set_gdbarch_register_size (gdbarch, 2); | |
1498 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1499 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1500 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1501 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
1502 | set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size); | |
1503 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
1504 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1505 | ||
1506 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1507 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1508 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1509 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1510 | set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1511 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1512 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1513 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1514 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1515 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1516 | switch (info.byte_order) |
1517 | { | |
1518 | case BIG_ENDIAN: | |
1519 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1520 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1521 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1522 | break; | |
1523 | case LITTLE_ENDIAN: | |
1524 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
1525 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1526 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1527 | break; | |
1528 | default: | |
8e65ff28 AC |
1529 | internal_error (__FILE__, __LINE__, |
1530 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1531 | } |
0f71a2f6 JM |
1532 | |
1533 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1534 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1535 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1536 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1537 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1538 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1539 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1540 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1541 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1542 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1543 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1544 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1545 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1546 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1547 | ||
1548 | set_gdbarch_register_convertible (gdbarch, d10v_register_convertible); | |
1549 | set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual); | |
1550 | set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw); | |
1551 | ||
1552 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); | |
1553 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1554 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1555 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1556 | ||
1557 | set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr); | |
1558 | set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr); | |
1559 | set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p); | |
1560 | set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p); | |
1561 | set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw); | |
1562 | set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw); | |
1563 | ||
1564 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); | |
1565 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1566 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1567 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1568 | ||
1569 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1570 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1571 | ||
1572 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1573 | ||
1574 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1575 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1576 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1577 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1578 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1579 | ||
1580 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1581 | ||
1582 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1583 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1584 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1585 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1586 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
c347ee3e MS |
1587 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
1588 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
0f71a2f6 JM |
1589 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1590 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1591 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1592 | |
7c7651b2 | 1593 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1594 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1595 | |
0f71a2f6 JM |
1596 | return gdbarch; |
1597 | } | |
1598 | ||
1599 | ||
507f3c78 KB |
1600 | extern void (*target_resume_hook) (void); |
1601 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1602 | |
1603 | void | |
fba45db2 | 1604 | _initialize_d10v_tdep (void) |
c906108c | 1605 | { |
0f71a2f6 JM |
1606 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1607 | ||
c906108c SS |
1608 | tm_print_insn = print_insn_d10v; |
1609 | ||
1610 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1611 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1612 | ||
1613 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1614 | ||
cff3e48b | 1615 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1616 | "Enable tracing of instruction execution."); |
1617 | ||
cff3e48b | 1618 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1619 | "Disable tracing of instruction execution."); |
1620 | ||
cff3e48b | 1621 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1622 | "Disassemble the trace buffer.\n\ |
1623 | Two optional arguments specify a range of trace buffer entries\n\ | |
1624 | as reported by info trace (NOT addresses!)."); | |
1625 | ||
cff3e48b | 1626 | add_info ("itrace", trace_info, |
c906108c SS |
1627 | "Display info about the trace data buffer."); |
1628 | ||
cff3e48b | 1629 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1630 | var_integer, (char *) &trace_display, |
1631 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1632 | &showlist); |
cff3e48b | 1633 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1634 | var_integer, (char *) &default_trace_show_source, |
1635 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1636 | &showlist); |
1637 | ||
c5aa993b | 1638 | } |