Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
7f6104a9 | 27 | #include "frame-unwind.h" |
270cb5d6 | 28 | #include "frame-base.h" |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdb_string.h" | |
34 | #include "value.h" | |
35 | #include "inferior.h" | |
c5aa993b | 36 | #include "dis-asm.h" |
c906108c SS |
37 | #include "symfile.h" |
38 | #include "objfiles.h" | |
104c1213 | 39 | #include "language.h" |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
e8933a55 | 42 | #include "remote.h" |
f0d4cc9e | 43 | #include "floatformat.h" |
b91b96f4 | 44 | #include "gdb/sim-d10v.h" |
8238d0bf | 45 | #include "sim-regno.h" |
92bf2b80 | 46 | #include "disasm.h" |
a0f267c7 | 47 | #include "trad-frame.h" |
4ce44c66 | 48 | |
fa1fd571 AC |
49 | #include "gdb_assert.h" |
50 | ||
4ce44c66 JM |
51 | struct gdbarch_tdep |
52 | { | |
53 | int a0_regnum; | |
54 | int nr_dmap_regs; | |
f6684c31 AC |
55 | unsigned long (*dmap_register) (void *regcache, int nr); |
56 | unsigned long (*imap_register) (void *regcache, int nr); | |
4ce44c66 JM |
57 | }; |
58 | ||
59 | /* These are the addresses the D10V-EVA board maps data and | |
db72fa6b | 60 | instruction memory to. */ |
cce74817 | 61 | |
78eac43e MS |
62 | enum memspace { |
63 | DMEM_START = 0x2000000, | |
64 | IMEM_START = 0x1000000, | |
65 | STACK_START = 0x200bffe | |
66 | }; | |
cce74817 | 67 | |
db72fa6b | 68 | /* d10v register names. */ |
4ce44c66 JM |
69 | |
70 | enum | |
71 | { | |
72 | R0_REGNUM = 0, | |
78eac43e | 73 | R3_REGNUM = 3, |
6c2b5168 | 74 | D10V_FP_REGNUM = 11, |
4ce44c66 | 75 | LR_REGNUM = 13, |
f75493ed | 76 | D10V_SP_REGNUM = 15, |
4ce44c66 | 77 | PSW_REGNUM = 16, |
27d94c49 | 78 | D10V_PC_REGNUM = 18, |
4ce44c66 | 79 | NR_IMAP_REGS = 2, |
78eac43e MS |
80 | NR_A_REGS = 2, |
81 | TS2_NUM_REGS = 37, | |
82 | TS3_NUM_REGS = 42, | |
db72fa6b | 83 | /* d10v calling convention. */ |
78eac43e | 84 | ARG1_REGNUM = R0_REGNUM, |
181555e9 | 85 | ARGN_REGNUM = R3_REGNUM |
4ce44c66 | 86 | }; |
78eac43e | 87 | |
b9362cc7 | 88 | static int |
f75493ed AC |
89 | nr_dmap_regs (struct gdbarch *gdbarch) |
90 | { | |
91 | return gdbarch_tdep (gdbarch)->nr_dmap_regs; | |
92 | } | |
93 | ||
b9362cc7 | 94 | static int |
f75493ed AC |
95 | a0_regnum (struct gdbarch *gdbarch) |
96 | { | |
97 | return gdbarch_tdep (gdbarch)->a0_regnum; | |
98 | } | |
4ce44c66 | 99 | |
392a587b JM |
100 | /* Local functions */ |
101 | ||
a14ed312 | 102 | extern void _initialize_d10v_tdep (void); |
392a587b | 103 | |
a14ed312 | 104 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 105 | |
a14ed312 | 106 | static void d10v_eva_get_trace_data (void); |
c906108c | 107 | |
23964bcd | 108 | static CORE_ADDR |
6ae2f580 | 109 | d10v_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
489137c0 | 110 | { |
6ae2f580 AC |
111 | /* Align to the size of an instruction (so that they can safely be |
112 | pushed onto the stack. */ | |
113 | return sp & ~3; | |
489137c0 | 114 | } |
c906108c | 115 | |
f4f9705a | 116 | static const unsigned char * |
fba45db2 | 117 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 118 | { |
c5aa993b JM |
119 | static unsigned char breakpoint[] = |
120 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
121 | *lenptr = sizeof (breakpoint); |
122 | return breakpoint; | |
123 | } | |
124 | ||
4ce44c66 | 125 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
db72fa6b | 126 | when the reg_nr isn't valid. */ |
4ce44c66 JM |
127 | |
128 | enum ts2_regnums | |
129 | { | |
130 | TS2_IMAP0_REGNUM = 32, | |
131 | TS2_DMAP_REGNUM = 34, | |
132 | TS2_NR_DMAP_REGS = 1, | |
133 | TS2_A0_REGNUM = 35 | |
134 | }; | |
135 | ||
fa88f677 | 136 | static const char * |
4ce44c66 | 137 | d10v_ts2_register_name (int reg_nr) |
392a587b | 138 | { |
c5aa993b JM |
139 | static char *register_names[] = |
140 | { | |
141 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
142 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
143 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
144 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
145 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
146 | }; |
147 | if (reg_nr < 0) | |
148 | return NULL; | |
149 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
150 | return NULL; | |
c5aa993b | 151 | return register_names[reg_nr]; |
392a587b JM |
152 | } |
153 | ||
4ce44c66 JM |
154 | enum ts3_regnums |
155 | { | |
156 | TS3_IMAP0_REGNUM = 36, | |
157 | TS3_DMAP0_REGNUM = 38, | |
158 | TS3_NR_DMAP_REGS = 4, | |
159 | TS3_A0_REGNUM = 32 | |
160 | }; | |
161 | ||
fa88f677 | 162 | static const char * |
4ce44c66 JM |
163 | d10v_ts3_register_name (int reg_nr) |
164 | { | |
165 | static char *register_names[] = | |
166 | { | |
167 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
168 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
169 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
170 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
171 | "a0", "a1", | |
172 | "spi", "spu", | |
173 | "imap0", "imap1", | |
174 | "dmap0", "dmap1", "dmap2", "dmap3" | |
175 | }; | |
176 | if (reg_nr < 0) | |
177 | return NULL; | |
178 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
179 | return NULL; | |
180 | return register_names[reg_nr]; | |
181 | } | |
182 | ||
bf93dfed JB |
183 | /* Access the DMAP/IMAP registers in a target independent way. |
184 | ||
185 | Divide the D10V's 64k data space into four 16k segments: | |
186 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
187 | 0xc000 -- 0xffff. | |
188 | ||
189 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
190 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
191 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
192 | unified memory or instruction memory, under the control of the | |
193 | single DMAP register. | |
194 | ||
195 | On the TS3, there are four DMAP registers, each of which controls | |
196 | one of the segments. */ | |
4ce44c66 JM |
197 | |
198 | static unsigned long | |
f6684c31 | 199 | d10v_ts2_dmap_register (void *regcache, int reg_nr) |
4ce44c66 JM |
200 | { |
201 | switch (reg_nr) | |
202 | { | |
203 | case 0: | |
204 | case 1: | |
205 | return 0x2000; | |
206 | case 2: | |
f6684c31 AC |
207 | { |
208 | ULONGEST reg; | |
209 | regcache_cooked_read_unsigned (regcache, TS2_DMAP_REGNUM, ®); | |
210 | return reg; | |
211 | } | |
4ce44c66 JM |
212 | default: |
213 | return 0; | |
214 | } | |
215 | } | |
216 | ||
217 | static unsigned long | |
f6684c31 | 218 | d10v_ts3_dmap_register (void *regcache, int reg_nr) |
4ce44c66 | 219 | { |
f6684c31 AC |
220 | ULONGEST reg; |
221 | regcache_cooked_read_unsigned (regcache, TS3_DMAP0_REGNUM + reg_nr, ®); | |
222 | return reg; | |
4ce44c66 JM |
223 | } |
224 | ||
225 | static unsigned long | |
f6684c31 | 226 | d10v_ts2_imap_register (void *regcache, int reg_nr) |
4ce44c66 | 227 | { |
f6684c31 AC |
228 | ULONGEST reg; |
229 | regcache_cooked_read_unsigned (regcache, TS2_IMAP0_REGNUM + reg_nr, ®); | |
230 | return reg; | |
4ce44c66 JM |
231 | } |
232 | ||
233 | static unsigned long | |
f6684c31 | 234 | d10v_ts3_imap_register (void *regcache, int reg_nr) |
4ce44c66 | 235 | { |
f6684c31 AC |
236 | ULONGEST reg; |
237 | regcache_cooked_read_unsigned (regcache, TS3_IMAP0_REGNUM + reg_nr, ®); | |
238 | return reg; | |
4ce44c66 JM |
239 | } |
240 | ||
62700349 AC |
241 | /* MAP GDB's internal register numbering (determined by the layout |
242 | from the DEPRECATED_REGISTER_BYTE array) onto the simulator's | |
db72fa6b | 243 | register numbering. */ |
4ce44c66 JM |
244 | |
245 | static int | |
246 | d10v_ts2_register_sim_regno (int nr) | |
247 | { | |
e8933a55 AC |
248 | /* Only makes sense to supply raw registers. */ |
249 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
250 | if (nr >= TS2_IMAP0_REGNUM |
251 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
252 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
253 | if (nr == TS2_DMAP_REGNUM) | |
254 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
255 | if (nr >= TS2_A0_REGNUM | |
256 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
257 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
258 | return nr; | |
259 | } | |
260 | ||
261 | static int | |
262 | d10v_ts3_register_sim_regno (int nr) | |
263 | { | |
e8933a55 AC |
264 | /* Only makes sense to supply raw registers. */ |
265 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
266 | if (nr >= TS3_IMAP0_REGNUM |
267 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
268 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
269 | if (nr >= TS3_DMAP0_REGNUM | |
270 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
271 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
272 | if (nr >= TS3_A0_REGNUM | |
273 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
274 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
275 | return nr; | |
276 | } | |
277 | ||
392a587b JM |
278 | /* Return the GDB type object for the "standard" data type |
279 | of data in register N. */ | |
280 | ||
f5e1cf12 | 281 | static struct type * |
35cac7cf | 282 | d10v_register_type (struct gdbarch *gdbarch, int reg_nr) |
392a587b | 283 | { |
27d94c49 | 284 | if (reg_nr == D10V_PC_REGNUM) |
75af7f68 | 285 | return builtin_type_void_func_ptr; |
f75493ed | 286 | if (reg_nr == D10V_SP_REGNUM || reg_nr == D10V_FP_REGNUM) |
095a4c96 | 287 | return builtin_type_void_data_ptr; |
f75493ed AC |
288 | else if (reg_nr >= a0_regnum (gdbarch) |
289 | && reg_nr < (a0_regnum (gdbarch) + NR_A_REGS)) | |
4ce44c66 | 290 | return builtin_type_int64; |
392a587b | 291 | else |
4ce44c66 | 292 | return builtin_type_int16; |
392a587b JM |
293 | } |
294 | ||
f5e1cf12 | 295 | static int |
fba45db2 | 296 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
297 | { |
298 | return (((x) & 0x3000000) == DMEM_START); | |
299 | } | |
300 | ||
f5e1cf12 | 301 | static int |
fba45db2 | 302 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
303 | { |
304 | return (((x) & 0x3000000) == IMEM_START); | |
305 | } | |
306 | ||
169a7369 MS |
307 | static CORE_ADDR |
308 | d10v_make_daddr (CORE_ADDR x) | |
309 | { | |
310 | return ((x) | DMEM_START); | |
311 | } | |
312 | ||
313 | static CORE_ADDR | |
314 | d10v_make_iaddr (CORE_ADDR x) | |
315 | { | |
316 | if (d10v_iaddr_p (x)) | |
db72fa6b | 317 | return x; /* Idempotency -- x is already in the IMEM space. */ |
169a7369 MS |
318 | else |
319 | return (((x) << 2) | IMEM_START); | |
320 | } | |
392a587b | 321 | |
f5e1cf12 | 322 | static CORE_ADDR |
fba45db2 | 323 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
324 | { |
325 | return (((x) >> 2) & 0xffff); | |
326 | } | |
327 | ||
f5e1cf12 | 328 | static CORE_ADDR |
fba45db2 | 329 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
330 | { |
331 | return ((x) & 0xffff); | |
332 | } | |
333 | ||
75af7f68 JB |
334 | static void |
335 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
336 | { | |
337 | /* Is it a code address? */ | |
338 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
339 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
340 | { | |
75af7f68 JB |
341 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
342 | d10v_convert_iaddr_to_raw (addr)); | |
343 | } | |
344 | else | |
345 | { | |
346 | /* Strip off any upper segment bits. */ | |
347 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
348 | d10v_convert_daddr_to_raw (addr)); | |
349 | } | |
350 | } | |
351 | ||
352 | static CORE_ADDR | |
66140c26 | 353 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 | 354 | { |
f75493ed | 355 | CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH (type)); |
75af7f68 JB |
356 | /* Is it a code address? */ |
357 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
358 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
359 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
360 | return d10v_make_iaddr (addr); |
361 | else | |
362 | return d10v_make_daddr (addr); | |
363 | } | |
364 | ||
095a4c96 EZ |
365 | /* Don't do anything if we have an integer, this way users can type 'x |
366 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
367 | to the correct space are taken care of in the pointer_to_address | |
368 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
369 | static CORE_ADDR |
370 | d10v_integer_to_address (struct type *type, void *buf) | |
371 | { | |
372 | LONGEST val; | |
373 | val = unpack_long (type, buf); | |
095a4c96 | 374 | return val; |
fc0c74b1 | 375 | } |
75af7f68 | 376 | |
181555e9 | 377 | /* Handle the d10v's return_value convention. */ |
392a587b | 378 | |
181555e9 AC |
379 | static enum return_value_convention |
380 | d10v_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
963e2bb7 AC |
381 | struct regcache *regcache, void *readbuf, |
382 | const void *writebuf) | |
392a587b | 383 | { |
181555e9 AC |
384 | if (TYPE_LENGTH (valtype) > 8) |
385 | /* Anything larger than 8 bytes (4 registers) goes on the stack. */ | |
386 | return RETURN_VALUE_STRUCT_CONVENTION; | |
387 | if (TYPE_LENGTH (valtype) == 5 | |
388 | || TYPE_LENGTH (valtype) == 6) | |
389 | /* Anything 5 or 6 bytes in size goes in memory. Contents don't | |
390 | appear to matter. Note that 7 and 8 byte objects do end up in | |
391 | registers! */ | |
392 | return RETURN_VALUE_STRUCT_CONVENTION; | |
393 | if (TYPE_LENGTH (valtype) == 1) | |
3d79a47c | 394 | { |
181555e9 AC |
395 | /* All single byte values go in a register stored right-aligned. |
396 | Note: 2 byte integer values are handled further down. */ | |
397 | if (readbuf) | |
398 | { | |
399 | /* Since TYPE is smaller than the register, there isn't a | |
400 | sign extension problem. Let the extraction truncate the | |
401 | register value. */ | |
402 | ULONGEST regval; | |
403 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, | |
404 | ®val); | |
405 | store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); | |
406 | ||
407 | } | |
408 | if (writebuf) | |
409 | { | |
410 | ULONGEST regval; | |
411 | if (TYPE_CODE (valtype) == TYPE_CODE_INT) | |
412 | /* Some sort of integer value stored in R0. Use | |
413 | unpack_long since that should handle any required sign | |
414 | extension. */ | |
415 | regval = unpack_long (valtype, writebuf); | |
416 | else | |
417 | /* Some other type. Don't sign-extend the value when | |
418 | storing it in the register. */ | |
419 | regval = extract_unsigned_integer (writebuf, 1); | |
420 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, regval); | |
421 | } | |
422 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3d79a47c | 423 | } |
181555e9 AC |
424 | if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
425 | || TYPE_CODE (valtype) == TYPE_CODE_UNION) | |
426 | && TYPE_NFIELDS (valtype) > 1 | |
427 | && TYPE_FIELD_BITPOS (valtype, 1) == 8) | |
428 | /* If a composite is 8 bit aligned (determined by looking at the | |
429 | start address of the second field), put it in memory. */ | |
430 | return RETURN_VALUE_STRUCT_CONVENTION; | |
431 | /* Assume it is in registers. */ | |
432 | if (writebuf || readbuf) | |
fa1fd571 AC |
433 | { |
434 | int reg; | |
181555e9 AC |
435 | /* Per above, the value is never more than 8 bytes long. */ |
436 | gdb_assert (TYPE_LENGTH (valtype) <= 8); | |
437 | /* Xfer 2 bytes at a time. */ | |
438 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (valtype); reg++) | |
439 | { | |
440 | if (readbuf) | |
441 | regcache_cooked_read (regcache, R0_REGNUM + reg, | |
442 | (bfd_byte *) readbuf + reg * 2); | |
443 | if (writebuf) | |
444 | regcache_cooked_write (regcache, R0_REGNUM + reg, | |
445 | (bfd_byte *) writebuf + reg * 2); | |
446 | } | |
447 | /* Any trailing byte ends up _left_ aligned. */ | |
448 | if ((reg * 2) < TYPE_LENGTH (valtype)) | |
fa1fd571 | 449 | { |
181555e9 AC |
450 | if (readbuf) |
451 | regcache_cooked_read_part (regcache, R0_REGNUM + reg, | |
452 | 0, 1, (bfd_byte *) readbuf + reg * 2); | |
453 | if (writebuf) | |
454 | regcache_cooked_write_part (regcache, R0_REGNUM + reg, | |
455 | 0, 1, (bfd_byte *) writebuf + reg * 2); | |
fa1fd571 | 456 | } |
fa1fd571 | 457 | } |
181555e9 | 458 | return RETURN_VALUE_REGISTER_CONVENTION; |
392a587b JM |
459 | } |
460 | ||
c5aa993b | 461 | static int |
fba45db2 | 462 | check_prologue (unsigned short op) |
c906108c SS |
463 | { |
464 | /* st rn, @-sp */ | |
465 | if ((op & 0x7E1F) == 0x6C1F) | |
466 | return 1; | |
467 | ||
468 | /* st2w rn, @-sp */ | |
469 | if ((op & 0x7E3F) == 0x6E1F) | |
470 | return 1; | |
471 | ||
472 | /* subi sp, n */ | |
473 | if ((op & 0x7FE1) == 0x01E1) | |
474 | return 1; | |
475 | ||
476 | /* mv r11, sp */ | |
477 | if (op == 0x417E) | |
478 | return 1; | |
479 | ||
480 | /* nop */ | |
481 | if (op == 0x5E00) | |
482 | return 1; | |
483 | ||
484 | /* st rn, @sp */ | |
485 | if ((op & 0x7E1F) == 0x681E) | |
486 | return 1; | |
487 | ||
488 | /* st2w rn, @sp */ | |
c5aa993b JM |
489 | if ((op & 0x7E3F) == 0x3A1E) |
490 | return 1; | |
c906108c SS |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
f5e1cf12 | 495 | static CORE_ADDR |
fba45db2 | 496 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
497 | { |
498 | unsigned long op; | |
499 | unsigned short op1, op2; | |
500 | CORE_ADDR func_addr, func_end; | |
501 | struct symtab_and_line sal; | |
502 | ||
db72fa6b | 503 | /* If we have line debugging information, then the end of the prologue |
74276724 | 504 | should be the first assembly instruction of the first source line. */ |
c906108c SS |
505 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
506 | { | |
507 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 508 | if (sal.end && sal.end < func_end) |
c906108c SS |
509 | return sal.end; |
510 | } | |
c5aa993b JM |
511 | |
512 | if (target_read_memory (pc, (char *) &op, 4)) | |
db72fa6b | 513 | return pc; /* Can't access it -- assume no prologue. */ |
c906108c SS |
514 | |
515 | while (1) | |
516 | { | |
c5aa993b | 517 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
518 | if ((op & 0xC0000000) == 0xC0000000) |
519 | { | |
520 | /* long instruction */ | |
c5aa993b JM |
521 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
522 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
523 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
524 | break; |
525 | } | |
526 | else | |
527 | { | |
528 | /* short instructions */ | |
529 | if ((op & 0xC0000000) == 0x80000000) | |
530 | { | |
531 | op2 = (op & 0x3FFF8000) >> 15; | |
532 | op1 = op & 0x7FFF; | |
c5aa993b JM |
533 | } |
534 | else | |
c906108c SS |
535 | { |
536 | op1 = (op & 0x3FFF8000) >> 15; | |
537 | op2 = op & 0x7FFF; | |
538 | } | |
c5aa993b | 539 | if (check_prologue (op1)) |
c906108c | 540 | { |
c5aa993b | 541 | if (!check_prologue (op2)) |
c906108c | 542 | { |
db72fa6b MS |
543 | /* If the previous opcode was really part of the |
544 | prologue and not just a NOP, then we want to | |
545 | break after both instructions. */ | |
c906108c SS |
546 | if (op1 != 0x5E00) |
547 | pc += 4; | |
548 | break; | |
549 | } | |
550 | } | |
551 | else | |
552 | break; | |
553 | } | |
554 | pc += 4; | |
555 | } | |
556 | return pc; | |
557 | } | |
558 | ||
7f6104a9 | 559 | struct d10v_unwind_cache |
c906108c | 560 | { |
270cb5d6 AC |
561 | /* The previous frame's inner most stack address. Used as this |
562 | frame ID's stack_addr. */ | |
563 | CORE_ADDR prev_sp; | |
564 | /* The frame's base, optionally used by the high-level debug info. */ | |
ceea5145 | 565 | CORE_ADDR base; |
7f6104a9 | 566 | int size; |
0d843116 AC |
567 | /* How far the SP and r11 (FP) have been offset from the start of |
568 | the stack frame (as defined by the previous frame's stack | |
569 | pointer). */ | |
570 | LONGEST sp_offset; | |
571 | LONGEST r11_offset; | |
7f6104a9 | 572 | int uses_frame; |
a0f267c7 | 573 | /* Table indicating the location of each and every register. */ |
8983bd83 | 574 | struct trad_frame_saved_reg *saved_regs; |
7f6104a9 | 575 | }; |
c906108c | 576 | |
c5aa993b | 577 | static int |
7f6104a9 AC |
578 | prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, |
579 | CORE_ADDR addr) | |
c906108c SS |
580 | { |
581 | int n; | |
582 | ||
583 | /* st rn, @-sp */ | |
584 | if ((op & 0x7E1F) == 0x6C1F) | |
585 | { | |
586 | n = (op & 0x1E0) >> 5; | |
0d843116 | 587 | info->sp_offset -= 2; |
a0f267c7 | 588 | info->saved_regs[n].addr = info->sp_offset; |
c906108c SS |
589 | return 1; |
590 | } | |
591 | ||
592 | /* st2w rn, @-sp */ | |
593 | else if ((op & 0x7E3F) == 0x6E1F) | |
594 | { | |
595 | n = (op & 0x1E0) >> 5; | |
0d843116 | 596 | info->sp_offset -= 4; |
a0f267c7 AC |
597 | info->saved_regs[n + 0].addr = info->sp_offset + 0; |
598 | info->saved_regs[n + 1].addr = info->sp_offset + 2; | |
c906108c SS |
599 | return 1; |
600 | } | |
601 | ||
602 | /* subi sp, n */ | |
603 | if ((op & 0x7FE1) == 0x01E1) | |
604 | { | |
605 | n = (op & 0x1E) >> 1; | |
606 | if (n == 0) | |
607 | n = 16; | |
0d843116 | 608 | info->sp_offset -= n; |
c906108c SS |
609 | return 1; |
610 | } | |
611 | ||
612 | /* mv r11, sp */ | |
613 | if (op == 0x417E) | |
614 | { | |
7f6104a9 | 615 | info->uses_frame = 1; |
0d843116 AC |
616 | info->r11_offset = info->sp_offset; |
617 | return 1; | |
618 | } | |
619 | ||
620 | /* st rn, @r11 */ | |
621 | if ((op & 0x7E1F) == 0x6816) | |
622 | { | |
623 | n = (op & 0x1E0) >> 5; | |
a0f267c7 | 624 | info->saved_regs[n].addr = info->r11_offset; |
c906108c SS |
625 | return 1; |
626 | } | |
627 | ||
628 | /* nop */ | |
629 | if (op == 0x5E00) | |
630 | return 1; | |
631 | ||
632 | /* st rn, @sp */ | |
633 | if ((op & 0x7E1F) == 0x681E) | |
634 | { | |
635 | n = (op & 0x1E0) >> 5; | |
a0f267c7 | 636 | info->saved_regs[n].addr = info->sp_offset; |
c906108c SS |
637 | return 1; |
638 | } | |
639 | ||
640 | /* st2w rn, @sp */ | |
641 | if ((op & 0x7E3F) == 0x3A1E) | |
642 | { | |
643 | n = (op & 0x1E0) >> 5; | |
a0f267c7 AC |
644 | info->saved_regs[n + 0].addr = info->sp_offset + 0; |
645 | info->saved_regs[n + 1].addr = info->sp_offset + 2; | |
c906108c SS |
646 | return 1; |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
cce74817 JM |
652 | /* Put here the code to store, into fi->saved_regs, the addresses of |
653 | the saved registers of frame described by FRAME_INFO. This | |
654 | includes special registers such as pc and fp saved in special ways | |
655 | in the stack frame. sp is even more special: the address we return | |
db72fa6b | 656 | for it IS the sp for the next frame. */ |
cce74817 | 657 | |
b9362cc7 | 658 | static struct d10v_unwind_cache * |
6dc42492 AC |
659 | d10v_frame_unwind_cache (struct frame_info *next_frame, |
660 | void **this_prologue_cache) | |
c906108c | 661 | { |
ae1e7417 | 662 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
ceea5145 AC |
663 | CORE_ADDR pc; |
664 | ULONGEST prev_sp; | |
665 | ULONGEST this_base; | |
c906108c SS |
666 | unsigned long op; |
667 | unsigned short op1, op2; | |
668 | int i; | |
7f6104a9 AC |
669 | struct d10v_unwind_cache *info; |
670 | ||
6dc42492 AC |
671 | if ((*this_prologue_cache)) |
672 | return (*this_prologue_cache); | |
7f6104a9 AC |
673 | |
674 | info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); | |
6dc42492 | 675 | (*this_prologue_cache) = info; |
a0f267c7 | 676 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
7f6104a9 | 677 | |
7f6104a9 | 678 | info->size = 0; |
0d843116 | 679 | info->sp_offset = 0; |
c906108c | 680 | |
7f6104a9 | 681 | info->uses_frame = 0; |
be41e9f4 | 682 | for (pc = frame_func_unwind (next_frame); |
81f8a206 | 683 | pc > 0 && pc < frame_pc_unwind (next_frame); |
270cb5d6 | 684 | pc += 4) |
c906108c | 685 | { |
ae1e7417 | 686 | op = get_frame_memory_unsigned (next_frame, pc, 4); |
c906108c SS |
687 | if ((op & 0xC0000000) == 0xC0000000) |
688 | { | |
689 | /* long instruction */ | |
690 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
691 | { | |
692 | /* add3 sp,sp,n */ | |
693 | short n = op & 0xFFFF; | |
0d843116 | 694 | info->sp_offset += n; |
c906108c SS |
695 | } |
696 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
697 | { | |
698 | /* st rn, @(offset,sp) */ | |
699 | short offset = op & 0xFFFF; | |
700 | short n = (op >> 20) & 0xF; | |
a0f267c7 | 701 | info->saved_regs[n].addr = info->sp_offset + offset; |
c906108c SS |
702 | } |
703 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
704 | { | |
705 | /* st2w rn, @(offset,sp) */ | |
706 | short offset = op & 0xFFFF; | |
707 | short n = (op >> 20) & 0xF; | |
a0f267c7 AC |
708 | info->saved_regs[n + 0].addr = info->sp_offset + offset + 0; |
709 | info->saved_regs[n + 1].addr = info->sp_offset + offset + 2; | |
c906108c SS |
710 | } |
711 | else | |
712 | break; | |
713 | } | |
714 | else | |
715 | { | |
716 | /* short instructions */ | |
717 | if ((op & 0xC0000000) == 0x80000000) | |
718 | { | |
719 | op2 = (op & 0x3FFF8000) >> 15; | |
720 | op1 = op & 0x7FFF; | |
c5aa993b JM |
721 | } |
722 | else | |
c906108c SS |
723 | { |
724 | op1 = (op & 0x3FFF8000) >> 15; | |
725 | op2 = op & 0x7FFF; | |
726 | } | |
7f6104a9 AC |
727 | if (!prologue_find_regs (info, op1, pc) |
728 | || !prologue_find_regs (info, op2, pc)) | |
c906108c SS |
729 | break; |
730 | } | |
c906108c | 731 | } |
c5aa993b | 732 | |
0d843116 | 733 | info->size = -info->sp_offset; |
c906108c | 734 | |
a0f267c7 AC |
735 | /* Compute the previous frame's stack pointer (which is also the |
736 | frame's ID's stack address), and this frame's base pointer. */ | |
ceea5145 AC |
737 | if (info->uses_frame) |
738 | { | |
739 | /* The SP was moved to the FP. This indicates that a new frame | |
740 | was created. Get THIS frame's FP value by unwinding it from | |
741 | the next frame. */ | |
6c2b5168 | 742 | frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); |
ceea5145 AC |
743 | /* The FP points at the last saved register. Adjust the FP back |
744 | to before the first saved register giving the SP. */ | |
745 | prev_sp = this_base + info->size; | |
746 | } | |
ceea5145 AC |
747 | else |
748 | { | |
749 | /* Assume that the FP is this frame's SP but with that pushed | |
750 | stack space added back. */ | |
f75493ed | 751 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &this_base); |
ceea5145 AC |
752 | prev_sp = this_base + info->size; |
753 | } | |
754 | ||
a0f267c7 AC |
755 | /* Convert that SP/BASE into real addresses. */ |
756 | info->prev_sp = d10v_make_daddr (prev_sp); | |
ceea5145 | 757 | info->base = d10v_make_daddr (this_base); |
c906108c | 758 | |
ceea5145 AC |
759 | /* Adjust all the saved registers so that they contain addresses and |
760 | not offsets. */ | |
c5aa993b | 761 | for (i = 0; i < NUM_REGS - 1; i++) |
3b3850e8 | 762 | if (trad_frame_addr_p (info->saved_regs, i)) |
c906108c | 763 | { |
a0f267c7 | 764 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); |
c906108c SS |
765 | } |
766 | ||
a0f267c7 AC |
767 | /* The call instruction moves the caller's PC in the callee's LR. |
768 | Since this is an unwind, do the reverse. Copy the location of LR | |
769 | into PC (the address / regnum) so that a request for PC will be | |
770 | converted into a request for the LR. */ | |
771 | info->saved_regs[D10V_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
772 | ||
773 | /* The previous frame's SP needed to be computed. Save the computed | |
774 | value. */ | |
3b3850e8 AC |
775 | trad_frame_set_value (info->saved_regs, D10V_SP_REGNUM, |
776 | d10v_make_daddr (prev_sp)); | |
c906108c | 777 | |
7f6104a9 | 778 | return info; |
c906108c SS |
779 | } |
780 | ||
781 | static void | |
5f601589 AC |
782 | d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
783 | struct frame_info *frame, int regnum, int all) | |
c906108c | 784 | { |
f6684c31 | 785 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5f601589 | 786 | if (regnum >= 0) |
4ce44c66 | 787 | { |
5f601589 AC |
788 | default_print_registers_info (gdbarch, file, frame, regnum, all); |
789 | return; | |
4ce44c66 | 790 | } |
5f601589 AC |
791 | |
792 | { | |
793 | ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; | |
7f5f525d AC |
794 | pc = get_frame_register_unsigned (frame, D10V_PC_REGNUM); |
795 | psw = get_frame_register_unsigned (frame, PSW_REGNUM); | |
796 | rpt_s = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_s", -1)); | |
797 | rpt_e = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_e", -1)); | |
798 | rpt_c = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_c", -1)); | |
5f601589 AC |
799 | fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
800 | (long) pc, (long) d10v_make_iaddr (pc), (long) psw, | |
801 | (long) rpt_s, (long) rpt_e, (long) rpt_c); | |
802 | } | |
803 | ||
804 | { | |
805 | int group; | |
806 | for (group = 0; group < 16; group += 8) | |
807 | { | |
808 | int r; | |
809 | fprintf_filtered (file, "R%d-R%-2d", group, group + 7); | |
810 | for (r = group; r < group + 8; r++) | |
811 | { | |
812 | ULONGEST tmp; | |
7f5f525d | 813 | tmp = get_frame_register_unsigned (frame, r); |
5f601589 AC |
814 | fprintf_filtered (file, " %04lx", (long) tmp); |
815 | } | |
816 | fprintf_filtered (file, "\n"); | |
817 | } | |
818 | } | |
819 | ||
820 | /* Note: The IMAP/DMAP registers don't participate in function | |
821 | calls. Don't bother trying to unwind them. */ | |
822 | ||
6789195b | 823 | { |
5f601589 AC |
824 | int a; |
825 | for (a = 0; a < NR_IMAP_REGS; a++) | |
826 | { | |
827 | if (a > 0) | |
828 | fprintf_filtered (file, " "); | |
f6684c31 AC |
829 | fprintf_filtered (file, "IMAP%d %04lx", a, |
830 | tdep->imap_register (current_regcache, a)); | |
5f601589 | 831 | } |
f75493ed | 832 | if (nr_dmap_regs (gdbarch) == 1) |
5f601589 | 833 | /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ |
f6684c31 AC |
834 | fprintf_filtered (file, " DMAP %04lx\n", |
835 | tdep->dmap_register (current_regcache, 2)); | |
5f601589 AC |
836 | else |
837 | { | |
f75493ed | 838 | for (a = 0; a < nr_dmap_regs (gdbarch); a++) |
5f601589 | 839 | { |
f6684c31 AC |
840 | fprintf_filtered (file, " DMAP%d %04lx", a, |
841 | tdep->dmap_register (current_regcache, a)); | |
5f601589 AC |
842 | } |
843 | fprintf_filtered (file, "\n"); | |
844 | } | |
845 | } | |
846 | ||
847 | { | |
0c92afe8 | 848 | char num[MAX_REGISTER_SIZE]; |
5f601589 AC |
849 | int a; |
850 | fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); | |
f75493ed | 851 | for (a = a0_regnum (gdbarch); a < a0_regnum (gdbarch) + NR_A_REGS; a++) |
6789195b AC |
852 | { |
853 | int i; | |
5f601589 | 854 | fprintf_filtered (file, " "); |
7f5f525d | 855 | get_frame_register (frame, a, num); |
ae1e7417 | 856 | for (i = 0; i < register_size (gdbarch, a); i++) |
6789195b | 857 | { |
5f601589 | 858 | fprintf_filtered (file, "%02x", (num[i] & 0xff)); |
6789195b AC |
859 | } |
860 | } | |
861 | } | |
5f601589 AC |
862 | fprintf_filtered (file, "\n"); |
863 | } | |
864 | ||
865 | static void | |
866 | show_regs (char *args, int from_tty) | |
867 | { | |
868 | d10v_print_registers_info (current_gdbarch, gdb_stdout, | |
869 | get_current_frame (), -1, 1); | |
c906108c SS |
870 | } |
871 | ||
f5e1cf12 | 872 | static CORE_ADDR |
39f77062 | 873 | d10v_read_pc (ptid_t ptid) |
c906108c | 874 | { |
39f77062 | 875 | ptid_t save_ptid; |
c906108c SS |
876 | CORE_ADDR pc; |
877 | CORE_ADDR retval; | |
878 | ||
39f77062 KB |
879 | save_ptid = inferior_ptid; |
880 | inferior_ptid = ptid; | |
27d94c49 | 881 | pc = (int) read_register (D10V_PC_REGNUM); |
39f77062 | 882 | inferior_ptid = save_ptid; |
7b570125 | 883 | retval = d10v_make_iaddr (pc); |
c906108c SS |
884 | return retval; |
885 | } | |
886 | ||
f5e1cf12 | 887 | static void |
39f77062 | 888 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 889 | { |
39f77062 | 890 | ptid_t save_ptid; |
c906108c | 891 | |
39f77062 KB |
892 | save_ptid = inferior_ptid; |
893 | inferior_ptid = ptid; | |
27d94c49 | 894 | write_register (D10V_PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 895 | inferior_ptid = save_ptid; |
c906108c SS |
896 | } |
897 | ||
f5e1cf12 | 898 | static CORE_ADDR |
a9e5fdc2 | 899 | d10v_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
c906108c | 900 | { |
a9e5fdc2 AC |
901 | ULONGEST sp; |
902 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &sp); | |
903 | return d10v_make_daddr (sp); | |
c906108c SS |
904 | } |
905 | ||
7a292a7a | 906 | /* When arguments must be pushed onto the stack, they go on in reverse |
db72fa6b | 907 | order. The below implements a FILO (stack) to do this. */ |
7a292a7a SS |
908 | |
909 | struct stack_item | |
910 | { | |
911 | int len; | |
912 | struct stack_item *prev; | |
913 | void *data; | |
914 | }; | |
915 | ||
a14ed312 KB |
916 | static struct stack_item *push_stack_item (struct stack_item *prev, |
917 | void *contents, int len); | |
7a292a7a | 918 | static struct stack_item * |
fba45db2 | 919 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
920 | { |
921 | struct stack_item *si; | |
922 | si = xmalloc (sizeof (struct stack_item)); | |
923 | si->data = xmalloc (len); | |
924 | si->len = len; | |
925 | si->prev = prev; | |
926 | memcpy (si->data, contents, len); | |
927 | return si; | |
928 | } | |
929 | ||
a14ed312 | 930 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 931 | static struct stack_item * |
fba45db2 | 932 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
933 | { |
934 | struct stack_item *dead = si; | |
935 | si = si->prev; | |
b8c9b27d KB |
936 | xfree (dead->data); |
937 | xfree (dead); | |
7a292a7a SS |
938 | return si; |
939 | } | |
940 | ||
941 | ||
7043d8dc AC |
942 | static CORE_ADDR |
943 | d10v_push_dummy_code (struct gdbarch *gdbarch, | |
944 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
945 | struct value **args, int nargs, | |
946 | struct type *value_type, | |
947 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
948 | { | |
949 | /* Allocate space sufficient for a breakpoint. */ | |
950 | sp = (sp - 4) & ~3; | |
951 | /* Store the address of that breakpoint taking care to first convert | |
952 | it into a code (IADDR) address from a stack (DADDR) address. | |
953 | This of course assumes that the two virtual addresses map onto | |
954 | the same real address. */ | |
955 | (*bp_addr) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp)); | |
956 | /* d10v always starts the call at the callee's entry point. */ | |
957 | (*real_pc) = funaddr; | |
958 | return sp; | |
959 | } | |
960 | ||
f5e1cf12 | 961 | static CORE_ADDR |
6a65450a AC |
962 | d10v_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
963 | struct regcache *regcache, CORE_ADDR bp_addr, | |
db72fa6b MS |
964 | int nargs, struct value **args, CORE_ADDR sp, |
965 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
966 | { |
967 | int i; | |
968 | int regnum = ARG1_REGNUM; | |
7a292a7a | 969 | struct stack_item *si = NULL; |
7bd91a28 MS |
970 | long val; |
971 | ||
5873a88d | 972 | /* Set the return address. For the d10v, the return breakpoint is |
6a65450a | 973 | always at BP_ADDR. */ |
5873a88d | 974 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, |
6a65450a | 975 | d10v_convert_iaddr_to_raw (bp_addr)); |
5873a88d | 976 | |
4183d812 AC |
977 | /* If STRUCT_RETURN is true, then the struct return address (in |
978 | STRUCT_ADDR) will consume the first argument-passing register. | |
979 | Both adjust the register count and store that value. */ | |
7bd91a28 | 980 | if (struct_return) |
4183d812 | 981 | { |
5873a88d | 982 | regcache_cooked_write_unsigned (regcache, regnum, struct_addr); |
4183d812 AC |
983 | regnum++; |
984 | } | |
c5aa993b | 985 | |
c906108c SS |
986 | /* Fill in registers and arg lists */ |
987 | for (i = 0; i < nargs; i++) | |
988 | { | |
ea7c478f | 989 | struct value *arg = args[i]; |
c906108c SS |
990 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
991 | char *contents = VALUE_CONTENTS (arg); | |
992 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
993 | int aligned_regnum = (regnum + 1) & ~1; |
994 | ||
8b279e7a | 995 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
996 | if (len <= 2 && regnum <= ARGN_REGNUM) |
997 | /* fits in a single register, do not align */ | |
998 | { | |
999 | val = extract_unsigned_integer (contents, len); | |
5873a88d | 1000 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
7bd91a28 MS |
1001 | } |
1002 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1003 | /* value fits in remaining registers, store keeping left | |
1004 | aligned */ | |
c906108c | 1005 | { |
7bd91a28 MS |
1006 | int b; |
1007 | regnum = aligned_regnum; | |
1008 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1009 | { |
7bd91a28 | 1010 | val = extract_unsigned_integer (&contents[b], 2); |
5873a88d | 1011 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
c906108c | 1012 | } |
7bd91a28 | 1013 | if (b < len) |
c906108c | 1014 | { |
7bd91a28 | 1015 | val = extract_unsigned_integer (&contents[b], 1); |
5873a88d | 1016 | regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); |
c906108c SS |
1017 | } |
1018 | } | |
7bd91a28 MS |
1019 | else |
1020 | { | |
1021 | /* arg will go onto stack */ | |
1022 | regnum = ARGN_REGNUM + 1; | |
1023 | si = push_stack_item (si, contents, len); | |
1024 | } | |
c906108c | 1025 | } |
7a292a7a SS |
1026 | |
1027 | while (si) | |
1028 | { | |
1029 | sp = (sp - si->len) & ~1; | |
1030 | write_memory (sp, si->data, si->len); | |
1031 | si = pop_stack_item (si); | |
1032 | } | |
c5aa993b | 1033 | |
5873a88d | 1034 | /* Finally, update the SP register. */ |
f75493ed | 1035 | regcache_cooked_write_unsigned (regcache, D10V_SP_REGNUM, |
5873a88d AC |
1036 | d10v_convert_daddr_to_raw (sp)); |
1037 | ||
c906108c SS |
1038 | return sp; |
1039 | } | |
1040 | ||
c2c6d25f JM |
1041 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1042 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1043 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1044 | (segmentation fault). Since the simulator knows all about how the | |
db72fa6b | 1045 | VM system works, we just call that to do the translation. */ |
c2c6d25f | 1046 | |
4ce44c66 | 1047 | static void |
f6684c31 AC |
1048 | remote_d10v_translate_xfer_address (struct gdbarch *gdbarch, |
1049 | struct regcache *regcache, | |
1050 | CORE_ADDR memaddr, int nr_bytes, | |
c2c6d25f JM |
1051 | CORE_ADDR *targ_addr, int *targ_len) |
1052 | { | |
f6684c31 | 1053 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4ce44c66 JM |
1054 | long out_addr; |
1055 | long out_len; | |
f6684c31 AC |
1056 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, &out_addr, regcache, |
1057 | tdep->dmap_register, tdep->imap_register); | |
4ce44c66 JM |
1058 | *targ_addr = out_addr; |
1059 | *targ_len = out_len; | |
c2c6d25f JM |
1060 | } |
1061 | ||
4ce44c66 | 1062 | |
c906108c SS |
1063 | /* The following code implements access to, and display of, the D10V's |
1064 | instruction trace buffer. The buffer consists of 64K or more | |
1065 | 4-byte words of data, of which each words includes an 8-bit count, | |
1066 | an 8-bit segment number, and a 16-bit instruction address. | |
1067 | ||
1068 | In theory, the trace buffer is continuously capturing instruction | |
1069 | data that the CPU presents on its "debug bus", but in practice, the | |
1070 | ROMified GDB stub only enables tracing when it continues or steps | |
1071 | the program, and stops tracing when the program stops; so it | |
1072 | actually works for GDB to read the buffer counter out of memory and | |
1073 | then read each trace word. The counter records where the tracing | |
1074 | stops, but there is no record of where it started, so we remember | |
1075 | the PC when we resumed and then search backwards in the trace | |
1076 | buffer for a word that includes that address. This is not perfect, | |
1077 | because you will miss trace data if the resumption PC is the target | |
1078 | of a branch. (The value of the buffer counter is semi-random, any | |
1079 | trace data from a previous program stop is gone.) */ | |
1080 | ||
1081 | /* The address of the last word recorded in the trace buffer. */ | |
1082 | ||
1083 | #define DBBC_ADDR (0xd80000) | |
1084 | ||
1085 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1086 | ||
1087 | #define TRACE_BUFFER_BASE (0xf40000) | |
1088 | ||
a14ed312 | 1089 | static void trace_command (char *, int); |
c906108c | 1090 | |
a14ed312 | 1091 | static void untrace_command (char *, int); |
c906108c | 1092 | |
a14ed312 | 1093 | static void trace_info (char *, int); |
c906108c | 1094 | |
a14ed312 | 1095 | static void tdisassemble_command (char *, int); |
c906108c | 1096 | |
a14ed312 | 1097 | static void display_trace (int, int); |
c906108c SS |
1098 | |
1099 | /* True when instruction traces are being collected. */ | |
1100 | ||
1101 | static int tracing; | |
1102 | ||
1103 | /* Remembered PC. */ | |
1104 | ||
1105 | static CORE_ADDR last_pc; | |
1106 | ||
1107 | /* True when trace output should be displayed whenever program stops. */ | |
1108 | ||
1109 | static int trace_display; | |
1110 | ||
1111 | /* True when trace listing should include source lines. */ | |
1112 | ||
1113 | static int default_trace_show_source = 1; | |
1114 | ||
c5aa993b JM |
1115 | struct trace_buffer |
1116 | { | |
1117 | int size; | |
1118 | short *counts; | |
1119 | CORE_ADDR *addrs; | |
1120 | } | |
1121 | trace_data; | |
c906108c SS |
1122 | |
1123 | static void | |
fba45db2 | 1124 | trace_command (char *args, int from_tty) |
c906108c SS |
1125 | { |
1126 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1127 | trace_data.size = 0; | |
1128 | if (trace_data.counts == NULL) | |
f75493ed | 1129 | trace_data.counts = XCALLOC (65536, short); |
c906108c | 1130 | if (trace_data.addrs == NULL) |
f75493ed | 1131 | trace_data.addrs = XCALLOC (65536, CORE_ADDR); |
c906108c SS |
1132 | |
1133 | tracing = 1; | |
1134 | ||
1135 | printf_filtered ("Tracing is now on.\n"); | |
1136 | } | |
1137 | ||
1138 | static void | |
fba45db2 | 1139 | untrace_command (char *args, int from_tty) |
c906108c SS |
1140 | { |
1141 | tracing = 0; | |
1142 | ||
1143 | printf_filtered ("Tracing is now off.\n"); | |
1144 | } | |
1145 | ||
1146 | static void | |
fba45db2 | 1147 | trace_info (char *args, int from_tty) |
c906108c SS |
1148 | { |
1149 | int i; | |
1150 | ||
1151 | if (trace_data.size) | |
1152 | { | |
1153 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1154 | ||
1155 | for (i = 0; i < trace_data.size; ++i) | |
1156 | { | |
d4f3574e SS |
1157 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1158 | i, | |
1159 | trace_data.counts[i], | |
c906108c | 1160 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1161 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1162 | } |
1163 | } | |
1164 | else | |
1165 | printf_filtered ("No entries in trace buffer.\n"); | |
1166 | ||
1167 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1168 | } | |
1169 | ||
392a587b | 1170 | static void |
fba45db2 | 1171 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1172 | { |
1173 | if (!tracing) | |
1174 | return; | |
1175 | ||
27d94c49 | 1176 | last_pc = read_register (D10V_PC_REGNUM); |
c906108c SS |
1177 | } |
1178 | ||
1179 | /* Collect trace data from the target board and format it into a form | |
1180 | more useful for display. */ | |
1181 | ||
392a587b | 1182 | static void |
fba45db2 | 1183 | d10v_eva_get_trace_data (void) |
c906108c SS |
1184 | { |
1185 | int count, i, j, oldsize; | |
1186 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1187 | unsigned int last_trace, trace_word, next_word; | |
1188 | unsigned int *tmpspace; | |
1189 | ||
1190 | if (!tracing) | |
1191 | return; | |
1192 | ||
c5aa993b | 1193 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1194 | |
1195 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1196 | ||
1197 | /* Collect buffer contents from the target, stopping when we reach | |
1198 | the word recorded when execution resumed. */ | |
1199 | ||
1200 | count = 0; | |
1201 | while (last_trace > 0) | |
1202 | { | |
1203 | QUIT; | |
1204 | trace_word = | |
1205 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1206 | trace_addr = trace_word & 0xffff; | |
1207 | last_trace -= 4; | |
1208 | /* Ignore an apparently nonsensical entry. */ | |
1209 | if (trace_addr == 0xffd5) | |
1210 | continue; | |
1211 | tmpspace[count++] = trace_word; | |
1212 | if (trace_addr == last_pc) | |
1213 | break; | |
1214 | if (count > 65535) | |
1215 | break; | |
1216 | } | |
1217 | ||
1218 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1219 | include the last instruction executed and transforming the address | |
1220 | into something that GDB likes. */ | |
1221 | ||
1222 | for (i = 0; i < count; ++i) | |
1223 | { | |
1224 | trace_word = tmpspace[i]; | |
1225 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1226 | trace_addr = trace_word & 0xffff; | |
1227 | next_cnt = (next_word >> 24) & 0xff; | |
1228 | j = trace_data.size + count - i - 1; | |
1229 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1230 | trace_data.counts[j] = next_cnt + 1; | |
1231 | } | |
1232 | ||
1233 | oldsize = trace_data.size; | |
1234 | trace_data.size += count; | |
1235 | ||
b8c9b27d | 1236 | xfree (tmpspace); |
c906108c SS |
1237 | |
1238 | if (trace_display) | |
1239 | display_trace (oldsize, trace_data.size); | |
1240 | } | |
1241 | ||
1242 | static void | |
fba45db2 | 1243 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1244 | { |
1245 | int i, count; | |
1246 | CORE_ADDR low, high; | |
c906108c SS |
1247 | |
1248 | if (!arg) | |
1249 | { | |
1250 | low = 0; | |
1251 | high = trace_data.size; | |
1252 | } | |
c906108c | 1253 | else |
e8933a55 AC |
1254 | { |
1255 | char *space_index = strchr (arg, ' '); | |
1256 | if (space_index == NULL) | |
1257 | { | |
1258 | low = parse_and_eval_address (arg); | |
1259 | high = low + 5; | |
1260 | } | |
1261 | else | |
1262 | { | |
1263 | /* Two arguments. */ | |
1264 | *space_index = '\0'; | |
1265 | low = parse_and_eval_address (arg); | |
1266 | high = parse_and_eval_address (space_index + 1); | |
1267 | if (high < low) | |
1268 | high = low; | |
1269 | } | |
c906108c SS |
1270 | } |
1271 | ||
db72fa6b MS |
1272 | printf_filtered ("Dump of trace from %s to %s:\n", |
1273 | paddr_u (low), paddr_u (high)); | |
c906108c SS |
1274 | |
1275 | display_trace (low, high); | |
1276 | ||
1277 | printf_filtered ("End of trace dump.\n"); | |
1278 | gdb_flush (gdb_stdout); | |
1279 | } | |
1280 | ||
1281 | static void | |
fba45db2 | 1282 | display_trace (int low, int high) |
c906108c SS |
1283 | { |
1284 | int i, count, trace_show_source, first, suppress; | |
1285 | CORE_ADDR next_address; | |
1286 | ||
1287 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1288 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1289 | { |
1290 | trace_show_source = 0; | |
1291 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1292 | printf_filtered ("Trace will not display any source.\n"); | |
1293 | } | |
1294 | ||
1295 | first = 1; | |
1296 | suppress = 0; | |
1297 | for (i = low; i < high; ++i) | |
1298 | { | |
1299 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1300 | count = trace_data.counts[i]; |
c906108c SS |
1301 | while (count-- > 0) |
1302 | { | |
1303 | QUIT; | |
1304 | if (trace_show_source) | |
1305 | { | |
1306 | struct symtab_and_line sal, sal_prev; | |
1307 | ||
1308 | sal_prev = find_pc_line (next_address - 4, 0); | |
1309 | sal = find_pc_line (next_address, 0); | |
1310 | ||
1311 | if (sal.symtab) | |
1312 | { | |
1313 | if (first || sal.line != sal_prev.line) | |
1314 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1315 | suppress = 0; | |
1316 | } | |
1317 | else | |
1318 | { | |
1319 | if (!suppress) | |
1320 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1321 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1322 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1323 | suppress = 1; |
1324 | } | |
1325 | } | |
1326 | first = 0; | |
1327 | print_address (next_address, gdb_stdout); | |
1328 | printf_filtered (":"); | |
1329 | printf_filtered ("\t"); | |
1330 | wrap_here (" "); | |
92bf2b80 | 1331 | next_address += gdb_print_insn (next_address, gdb_stdout); |
c906108c SS |
1332 | printf_filtered ("\n"); |
1333 | gdb_flush (gdb_stdout); | |
1334 | } | |
1335 | } | |
1336 | } | |
1337 | ||
7f6104a9 | 1338 | static CORE_ADDR |
12cc2063 | 1339 | d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
7f6104a9 | 1340 | { |
12cc2063 | 1341 | ULONGEST pc; |
27d94c49 | 1342 | frame_unwind_unsigned_register (next_frame, D10V_PC_REGNUM, &pc); |
12cc2063 | 1343 | return d10v_make_iaddr (pc); |
7f6104a9 AC |
1344 | } |
1345 | ||
1346 | /* Given a GDB frame, determine the address of the calling function's | |
1347 | frame. This will be used to create a new GDB frame struct. */ | |
1348 | ||
1349 | static void | |
6dc42492 AC |
1350 | d10v_frame_this_id (struct frame_info *next_frame, |
1351 | void **this_prologue_cache, | |
1352 | struct frame_id *this_id) | |
7f6104a9 | 1353 | { |
6dc42492 AC |
1354 | struct d10v_unwind_cache *info |
1355 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
1356 | CORE_ADDR base; | |
81f8a206 AC |
1357 | CORE_ADDR func; |
1358 | struct frame_id id; | |
7f6104a9 | 1359 | |
81f8a206 AC |
1360 | /* The FUNC is easy. */ |
1361 | func = frame_func_unwind (next_frame); | |
7f6104a9 | 1362 | |
6dc42492 AC |
1363 | /* Hopefully the prologue analysis either correctly determined the |
1364 | frame's base (which is the SP from the previous frame), or set | |
1365 | that base to "NULL". */ | |
270cb5d6 | 1366 | base = info->prev_sp; |
6dc42492 AC |
1367 | if (base == STACK_START || base == 0) |
1368 | return; | |
7f6104a9 | 1369 | |
81f8a206 AC |
1370 | id = frame_id_build (base, func); |
1371 | ||
81f8a206 | 1372 | (*this_id) = id; |
7f6104a9 AC |
1373 | } |
1374 | ||
7f6104a9 | 1375 | static void |
6dc42492 AC |
1376 | d10v_frame_prev_register (struct frame_info *next_frame, |
1377 | void **this_prologue_cache, | |
1378 | int regnum, int *optimizedp, | |
1379 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1380 | int *realnump, void *bufferp) | |
7f6104a9 | 1381 | { |
6dc42492 AC |
1382 | struct d10v_unwind_cache *info |
1383 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
a0f267c7 AC |
1384 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, |
1385 | optimizedp, lvalp, addrp, realnump, bufferp); | |
7f6104a9 AC |
1386 | } |
1387 | ||
270cb5d6 | 1388 | static const struct frame_unwind d10v_frame_unwind = { |
7df05f2b | 1389 | NORMAL_FRAME, |
6dc42492 AC |
1390 | d10v_frame_this_id, |
1391 | d10v_frame_prev_register | |
7f6104a9 AC |
1392 | }; |
1393 | ||
b9362cc7 | 1394 | static const struct frame_unwind * |
336d1bba | 1395 | d10v_frame_sniffer (struct frame_info *next_frame) |
7f6104a9 AC |
1396 | { |
1397 | return &d10v_frame_unwind; | |
1398 | } | |
1399 | ||
270cb5d6 AC |
1400 | static CORE_ADDR |
1401 | d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1402 | { | |
1403 | struct d10v_unwind_cache *info | |
1404 | = d10v_frame_unwind_cache (next_frame, this_cache); | |
1405 | return info->base; | |
1406 | } | |
1407 | ||
1408 | static const struct frame_base d10v_frame_base = { | |
1409 | &d10v_frame_unwind, | |
1410 | d10v_frame_base_address, | |
1411 | d10v_frame_base_address, | |
1412 | d10v_frame_base_address | |
1413 | }; | |
1414 | ||
6314f104 AC |
1415 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1416 | dummy frame. The frame ID's base needs to match the TOS value | |
1417 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1418 | breakpoint. */ | |
1419 | ||
1420 | static struct frame_id | |
1421 | d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1422 | { | |
3e210248 AC |
1423 | return frame_id_build (d10v_unwind_sp (gdbarch, next_frame), |
1424 | frame_pc_unwind (next_frame)); | |
6314f104 AC |
1425 | } |
1426 | ||
0f71a2f6 | 1427 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1428 | |
0f71a2f6 | 1429 | static struct gdbarch * |
fba45db2 | 1430 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1431 | { |
0f71a2f6 | 1432 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1433 | int d10v_num_regs; |
1434 | struct gdbarch_tdep *tdep; | |
1435 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1436 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1437 | |
db72fa6b | 1438 | /* Find a candidate among the list of pre-declared architectures. */ |
4ce44c66 | 1439 | arches = gdbarch_list_lookup_by_info (arches, &info); |
0f71a2f6 JM |
1440 | if (arches != NULL) |
1441 | return arches->gdbarch; | |
4ce44c66 JM |
1442 | |
1443 | /* None found, create a new architecture from the information | |
db72fa6b | 1444 | provided. */ |
4ce44c66 JM |
1445 | tdep = XMALLOC (struct gdbarch_tdep); |
1446 | gdbarch = gdbarch_alloc (&info, tdep); | |
1447 | ||
1448 | switch (info.bfd_arch_info->mach) | |
1449 | { | |
1450 | case bfd_mach_d10v_ts2: | |
1451 | d10v_num_regs = 37; | |
1452 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1453 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1454 | tdep->a0_regnum = TS2_A0_REGNUM; |
1455 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1456 | tdep->dmap_register = d10v_ts2_dmap_register; |
1457 | tdep->imap_register = d10v_ts2_imap_register; | |
1458 | break; | |
1459 | default: | |
1460 | case bfd_mach_d10v_ts3: | |
1461 | d10v_num_regs = 42; | |
1462 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1463 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1464 | tdep->a0_regnum = TS3_A0_REGNUM; |
1465 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1466 | tdep->dmap_register = d10v_ts3_dmap_register; |
1467 | tdep->imap_register = d10v_ts3_imap_register; | |
1468 | break; | |
1469 | } | |
0f71a2f6 JM |
1470 | |
1471 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1472 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
a9e5fdc2 | 1473 | set_gdbarch_unwind_sp (gdbarch, d10v_unwind_sp); |
0f71a2f6 JM |
1474 | |
1475 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
f75493ed | 1476 | set_gdbarch_sp_regnum (gdbarch, D10V_SP_REGNUM); |
0f71a2f6 | 1477 | set_gdbarch_register_name (gdbarch, d10v_register_name); |
35cac7cf | 1478 | set_gdbarch_register_type (gdbarch, d10v_register_type); |
0f71a2f6 | 1479 | |
75af7f68 JB |
1480 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1481 | set_gdbarch_addr_bit (gdbarch, 32); | |
1482 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1483 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1484 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1485 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1486 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1487 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1488 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e | 1489 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
db72fa6b | 1490 | double'' is 64 bits. */ |
0f71a2f6 JM |
1491 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1492 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1493 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1494 | switch (info.byte_order) |
1495 | { | |
d7449b42 | 1496 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1497 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1498 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1499 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1500 | break; | |
778eb05e | 1501 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1502 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1503 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
db72fa6b MS |
1504 | set_gdbarch_long_double_format (gdbarch, |
1505 | &floatformat_ieee_double_little); | |
f0d4cc9e AC |
1506 | break; |
1507 | default: | |
8e65ff28 AC |
1508 | internal_error (__FILE__, __LINE__, |
1509 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1510 | } |
0f71a2f6 | 1511 | |
181555e9 | 1512 | set_gdbarch_return_value (gdbarch, d10v_return_value); |
7043d8dc | 1513 | set_gdbarch_push_dummy_code (gdbarch, d10v_push_dummy_code); |
5873a88d | 1514 | set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); |
0f71a2f6 | 1515 | |
0f71a2f6 JM |
1516 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); |
1517 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1518 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1519 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1520 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1521 | ||
db72fa6b MS |
1522 | set_gdbarch_remote_translate_xfer_address (gdbarch, |
1523 | remote_d10v_translate_xfer_address); | |
0f71a2f6 JM |
1524 | |
1525 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
db72fa6b MS |
1526 | set_gdbarch_frameless_function_invocation (gdbarch, |
1527 | frameless_look_for_prologue); | |
f4ded5b1 | 1528 | |
6ae2f580 | 1529 | set_gdbarch_frame_align (gdbarch, d10v_frame_align); |
0f71a2f6 | 1530 | |
7c7651b2 AC |
1531 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
1532 | ||
5f601589 AC |
1533 | set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); |
1534 | ||
336d1bba | 1535 | frame_unwind_append_sniffer (gdbarch, d10v_frame_sniffer); |
270cb5d6 | 1536 | frame_base_set_default (gdbarch, &d10v_frame_base); |
7f6104a9 | 1537 | |
3e210248 AC |
1538 | /* Methods for saving / extracting a dummy frame's ID. The ID's |
1539 | stack address must match the SP value returned by | |
1540 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
6314f104 | 1541 | set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); |
6314f104 | 1542 | |
12cc2063 AC |
1543 | /* Return the unwound PC value. */ |
1544 | set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); | |
1545 | ||
0ef21242 AC |
1546 | set_gdbarch_print_insn (gdbarch, print_insn_d10v); |
1547 | ||
0f71a2f6 JM |
1548 | return gdbarch; |
1549 | } | |
1550 | ||
c906108c | 1551 | void |
fba45db2 | 1552 | _initialize_d10v_tdep (void) |
c906108c | 1553 | { |
0f71a2f6 JM |
1554 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1555 | ||
c906108c SS |
1556 | target_resume_hook = d10v_eva_prepare_to_trace; |
1557 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1558 | ||
db72fa6b MS |
1559 | deprecate_cmd (add_com ("regs", class_vars, show_regs, |
1560 | "Print all registers"), | |
5f601589 | 1561 | "info registers"); |
c906108c | 1562 | |
cff3e48b | 1563 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1564 | "Enable tracing of instruction execution."); |
1565 | ||
cff3e48b | 1566 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1567 | "Disable tracing of instruction execution."); |
1568 | ||
cff3e48b | 1569 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1570 | "Disassemble the trace buffer.\n\ |
1571 | Two optional arguments specify a range of trace buffer entries\n\ | |
1572 | as reported by info trace (NOT addresses!)."); | |
1573 | ||
cff3e48b | 1574 | add_info ("itrace", trace_info, |
c906108c SS |
1575 | "Display info about the trace data buffer."); |
1576 | ||
f75493ed AC |
1577 | add_setshow_boolean_cmd ("itracedisplay", no_class, &trace_display, |
1578 | "Set automatic display of trace.\n", | |
1579 | "Show automatic display of trace.\n", | |
1580 | NULL, NULL, &setlist, &showlist); | |
1581 | add_setshow_boolean_cmd ("itracesource", no_class, | |
1582 | &default_trace_show_source, | |
1583 | "Set display of source code with trace.\n", | |
1584 | "Show display of source code with trace.\n", | |
1585 | NULL, NULL, &setlist, &showlist); | |
c5aa993b | 1586 | } |