Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f AC |
2 | |
3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software | |
4 | Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "obstack.h" | |
28 | #include "symtab.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdb_string.h" | |
33 | #include "value.h" | |
34 | #include "inferior.h" | |
c5aa993b | 35 | #include "dis-asm.h" |
c906108c SS |
36 | #include "symfile.h" |
37 | #include "objfiles.h" | |
104c1213 | 38 | #include "language.h" |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
c906108c | 41 | |
f0d4cc9e | 42 | #include "floatformat.h" |
b91b96f4 | 43 | #include "gdb/sim-d10v.h" |
8238d0bf | 44 | #include "sim-regno.h" |
4ce44c66 | 45 | |
cce74817 | 46 | struct frame_extra_info |
c5aa993b JM |
47 | { |
48 | CORE_ADDR return_pc; | |
49 | int frameless; | |
50 | int size; | |
51 | }; | |
cce74817 | 52 | |
4ce44c66 JM |
53 | struct gdbarch_tdep |
54 | { | |
55 | int a0_regnum; | |
56 | int nr_dmap_regs; | |
57 | unsigned long (*dmap_register) (int nr); | |
58 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
59 | }; |
60 | ||
61 | /* These are the addresses the D10V-EVA board maps data and | |
62 | instruction memory to. */ | |
cce74817 | 63 | |
78eac43e MS |
64 | enum memspace { |
65 | DMEM_START = 0x2000000, | |
66 | IMEM_START = 0x1000000, | |
67 | STACK_START = 0x200bffe | |
68 | }; | |
cce74817 | 69 | |
4ce44c66 JM |
70 | /* d10v register names. */ |
71 | ||
72 | enum | |
73 | { | |
74 | R0_REGNUM = 0, | |
78eac43e MS |
75 | R3_REGNUM = 3, |
76 | _FP_REGNUM = 11, | |
4ce44c66 | 77 | LR_REGNUM = 13, |
78eac43e | 78 | _SP_REGNUM = 15, |
4ce44c66 | 79 | PSW_REGNUM = 16, |
78eac43e | 80 | _PC_REGNUM = 18, |
4ce44c66 | 81 | NR_IMAP_REGS = 2, |
78eac43e MS |
82 | NR_A_REGS = 2, |
83 | TS2_NUM_REGS = 37, | |
84 | TS3_NUM_REGS = 42, | |
85 | /* d10v calling convention. */ | |
86 | ARG1_REGNUM = R0_REGNUM, | |
87 | ARGN_REGNUM = R3_REGNUM, | |
88 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 89 | }; |
78eac43e | 90 | |
4ce44c66 JM |
91 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) |
92 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
93 | ||
392a587b JM |
94 | /* Local functions */ |
95 | ||
a14ed312 | 96 | extern void _initialize_d10v_tdep (void); |
392a587b | 97 | |
095a4c96 EZ |
98 | static CORE_ADDR d10v_read_sp (void); |
99 | ||
100 | static CORE_ADDR d10v_read_fp (void); | |
101 | ||
a14ed312 | 102 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 103 | |
a14ed312 | 104 | static void d10v_eva_get_trace_data (void); |
c906108c | 105 | |
a14ed312 KB |
106 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
107 | CORE_ADDR addr); | |
cce74817 | 108 | |
f5e1cf12 | 109 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 110 | |
a14ed312 | 111 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 112 | |
f5e1cf12 | 113 | static int |
72623009 | 114 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 115 | { |
78eac43e MS |
116 | if (chain != 0 && frame != NULL) |
117 | { | |
118 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
119 | return 1; /* Path back from a call dummy must be valid. */ | |
120 | return ((frame)->pc > IMEM_START | |
121 | && !inside_main_func (frame->pc)); | |
122 | } | |
123 | else return 0; | |
c906108c SS |
124 | } |
125 | ||
23964bcd | 126 | static CORE_ADDR |
489137c0 AC |
127 | d10v_stack_align (CORE_ADDR len) |
128 | { | |
129 | return (len + 1) & ~1; | |
130 | } | |
c906108c SS |
131 | |
132 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
133 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
134 | and TYPE is the type (which is known to be struct, union or array). | |
135 | ||
136 | The d10v returns anything less than 8 bytes in size in | |
137 | registers. */ | |
138 | ||
f5e1cf12 | 139 | static int |
fba45db2 | 140 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 141 | { |
02da6206 JSC |
142 | long alignment; |
143 | int i; | |
144 | /* The d10v only passes a struct in a register when that structure | |
145 | has an alignment that matches the size of a register. */ | |
146 | /* If the structure doesn't fit in 4 registers, put it on the | |
147 | stack. */ | |
148 | if (TYPE_LENGTH (type) > 8) | |
149 | return 1; | |
150 | /* If the struct contains only one field, don't put it on the stack | |
151 | - gcc can fit it in one or more registers. */ | |
152 | if (TYPE_NFIELDS (type) == 1) | |
153 | return 0; | |
154 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
155 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
156 | { | |
157 | /* If the alignment changes, just assume it goes on the | |
158 | stack. */ | |
159 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
160 | return 1; | |
161 | } | |
162 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
163 | don't put it on the stack. */ | |
164 | if (alignment == 2 || alignment == 4) | |
165 | return 0; | |
166 | return 1; | |
c906108c SS |
167 | } |
168 | ||
169 | ||
f4f9705a | 170 | static const unsigned char * |
fba45db2 | 171 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 172 | { |
c5aa993b JM |
173 | static unsigned char breakpoint[] = |
174 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
175 | *lenptr = sizeof (breakpoint); |
176 | return breakpoint; | |
177 | } | |
178 | ||
4ce44c66 JM |
179 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
180 | when the reg_nr isn't valid. */ | |
181 | ||
182 | enum ts2_regnums | |
183 | { | |
184 | TS2_IMAP0_REGNUM = 32, | |
185 | TS2_DMAP_REGNUM = 34, | |
186 | TS2_NR_DMAP_REGS = 1, | |
187 | TS2_A0_REGNUM = 35 | |
188 | }; | |
189 | ||
fa88f677 | 190 | static const char * |
4ce44c66 | 191 | d10v_ts2_register_name (int reg_nr) |
392a587b | 192 | { |
c5aa993b JM |
193 | static char *register_names[] = |
194 | { | |
195 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
196 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
197 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
198 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
199 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
200 | }; |
201 | if (reg_nr < 0) | |
202 | return NULL; | |
203 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
204 | return NULL; | |
c5aa993b | 205 | return register_names[reg_nr]; |
392a587b JM |
206 | } |
207 | ||
4ce44c66 JM |
208 | enum ts3_regnums |
209 | { | |
210 | TS3_IMAP0_REGNUM = 36, | |
211 | TS3_DMAP0_REGNUM = 38, | |
212 | TS3_NR_DMAP_REGS = 4, | |
213 | TS3_A0_REGNUM = 32 | |
214 | }; | |
215 | ||
fa88f677 | 216 | static const char * |
4ce44c66 JM |
217 | d10v_ts3_register_name (int reg_nr) |
218 | { | |
219 | static char *register_names[] = | |
220 | { | |
221 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
222 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
223 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
224 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
225 | "a0", "a1", | |
226 | "spi", "spu", | |
227 | "imap0", "imap1", | |
228 | "dmap0", "dmap1", "dmap2", "dmap3" | |
229 | }; | |
230 | if (reg_nr < 0) | |
231 | return NULL; | |
232 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
233 | return NULL; | |
234 | return register_names[reg_nr]; | |
235 | } | |
236 | ||
bf93dfed JB |
237 | /* Access the DMAP/IMAP registers in a target independent way. |
238 | ||
239 | Divide the D10V's 64k data space into four 16k segments: | |
240 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
241 | 0xc000 -- 0xffff. | |
242 | ||
243 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
244 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
245 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
246 | unified memory or instruction memory, under the control of the | |
247 | single DMAP register. | |
248 | ||
249 | On the TS3, there are four DMAP registers, each of which controls | |
250 | one of the segments. */ | |
4ce44c66 JM |
251 | |
252 | static unsigned long | |
253 | d10v_ts2_dmap_register (int reg_nr) | |
254 | { | |
255 | switch (reg_nr) | |
256 | { | |
257 | case 0: | |
258 | case 1: | |
259 | return 0x2000; | |
260 | case 2: | |
261 | return read_register (TS2_DMAP_REGNUM); | |
262 | default: | |
263 | return 0; | |
264 | } | |
265 | } | |
266 | ||
267 | static unsigned long | |
268 | d10v_ts3_dmap_register (int reg_nr) | |
269 | { | |
270 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
271 | } | |
272 | ||
273 | static unsigned long | |
274 | d10v_dmap_register (int reg_nr) | |
275 | { | |
276 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
277 | } | |
278 | ||
279 | static unsigned long | |
280 | d10v_ts2_imap_register (int reg_nr) | |
281 | { | |
282 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
283 | } | |
284 | ||
285 | static unsigned long | |
286 | d10v_ts3_imap_register (int reg_nr) | |
287 | { | |
288 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
289 | } | |
290 | ||
291 | static unsigned long | |
292 | d10v_imap_register (int reg_nr) | |
293 | { | |
294 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
295 | } | |
296 | ||
297 | /* MAP GDB's internal register numbering (determined by the layout fo | |
298 | the REGISTER_BYTE array) onto the simulator's register | |
299 | numbering. */ | |
300 | ||
301 | static int | |
302 | d10v_ts2_register_sim_regno (int nr) | |
303 | { | |
8238d0bf AC |
304 | if (legacy_register_sim_regno (nr) < 0) |
305 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
306 | if (nr >= TS2_IMAP0_REGNUM |
307 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
308 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
309 | if (nr == TS2_DMAP_REGNUM) | |
310 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
311 | if (nr >= TS2_A0_REGNUM | |
312 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
313 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
314 | return nr; | |
315 | } | |
316 | ||
317 | static int | |
318 | d10v_ts3_register_sim_regno (int nr) | |
319 | { | |
8238d0bf AC |
320 | if (legacy_register_sim_regno (nr) < 0) |
321 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
322 | if (nr >= TS3_IMAP0_REGNUM |
323 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
324 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
325 | if (nr >= TS3_DMAP0_REGNUM | |
326 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
327 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
328 | if (nr >= TS3_A0_REGNUM | |
329 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
330 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
331 | return nr; | |
332 | } | |
333 | ||
392a587b JM |
334 | /* Index within `registers' of the first byte of the space for |
335 | register REG_NR. */ | |
336 | ||
f5e1cf12 | 337 | static int |
fba45db2 | 338 | d10v_register_byte (int reg_nr) |
392a587b | 339 | { |
4ce44c66 | 340 | if (reg_nr < A0_REGNUM) |
392a587b | 341 | return (reg_nr * 2); |
4ce44c66 JM |
342 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
343 | return (A0_REGNUM * 2 | |
344 | + (reg_nr - A0_REGNUM) * 8); | |
345 | else | |
346 | return (A0_REGNUM * 2 | |
347 | + NR_A_REGS * 8 | |
348 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
349 | } |
350 | ||
351 | /* Number of bytes of storage in the actual machine representation for | |
352 | register REG_NR. */ | |
353 | ||
f5e1cf12 | 354 | static int |
fba45db2 | 355 | d10v_register_raw_size (int reg_nr) |
392a587b | 356 | { |
4ce44c66 JM |
357 | if (reg_nr < A0_REGNUM) |
358 | return 2; | |
359 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
360 | return 8; |
361 | else | |
362 | return 2; | |
363 | } | |
364 | ||
392a587b JM |
365 | /* Return the GDB type object for the "standard" data type |
366 | of data in register N. */ | |
367 | ||
f5e1cf12 | 368 | static struct type * |
fba45db2 | 369 | d10v_register_virtual_type (int reg_nr) |
392a587b | 370 | { |
75af7f68 JB |
371 | if (reg_nr == PC_REGNUM) |
372 | return builtin_type_void_func_ptr; | |
095a4c96 EZ |
373 | if (reg_nr == _SP_REGNUM || reg_nr == _FP_REGNUM) |
374 | return builtin_type_void_data_ptr; | |
75af7f68 | 375 | else if (reg_nr >= A0_REGNUM |
4ce44c66 JM |
376 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
377 | return builtin_type_int64; | |
392a587b | 378 | else |
4ce44c66 | 379 | return builtin_type_int16; |
392a587b JM |
380 | } |
381 | ||
f5e1cf12 | 382 | static int |
fba45db2 | 383 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
384 | { |
385 | return (((x) & 0x3000000) == DMEM_START); | |
386 | } | |
387 | ||
f5e1cf12 | 388 | static int |
fba45db2 | 389 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
390 | { |
391 | return (((x) & 0x3000000) == IMEM_START); | |
392 | } | |
393 | ||
169a7369 MS |
394 | static CORE_ADDR |
395 | d10v_make_daddr (CORE_ADDR x) | |
396 | { | |
397 | return ((x) | DMEM_START); | |
398 | } | |
399 | ||
400 | static CORE_ADDR | |
401 | d10v_make_iaddr (CORE_ADDR x) | |
402 | { | |
403 | if (d10v_iaddr_p (x)) | |
404 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
405 | else | |
406 | return (((x) << 2) | IMEM_START); | |
407 | } | |
392a587b | 408 | |
f5e1cf12 | 409 | static CORE_ADDR |
fba45db2 | 410 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
411 | { |
412 | return (((x) >> 2) & 0xffff); | |
413 | } | |
414 | ||
f5e1cf12 | 415 | static CORE_ADDR |
fba45db2 | 416 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
417 | { |
418 | return ((x) & 0xffff); | |
419 | } | |
420 | ||
75af7f68 JB |
421 | static void |
422 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
423 | { | |
424 | /* Is it a code address? */ | |
425 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
426 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
427 | { | |
75af7f68 JB |
428 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
429 | d10v_convert_iaddr_to_raw (addr)); | |
430 | } | |
431 | else | |
432 | { | |
433 | /* Strip off any upper segment bits. */ | |
434 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
435 | d10v_convert_daddr_to_raw (addr)); | |
436 | } | |
437 | } | |
438 | ||
439 | static CORE_ADDR | |
440 | d10v_pointer_to_address (struct type *type, void *buf) | |
441 | { | |
442 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
443 | ||
444 | /* Is it a code address? */ | |
445 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
446 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
447 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
448 | return d10v_make_iaddr (addr); |
449 | else | |
450 | return d10v_make_daddr (addr); | |
451 | } | |
452 | ||
095a4c96 EZ |
453 | /* Don't do anything if we have an integer, this way users can type 'x |
454 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
455 | to the correct space are taken care of in the pointer_to_address | |
456 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
457 | static CORE_ADDR |
458 | d10v_integer_to_address (struct type *type, void *buf) | |
459 | { | |
460 | LONGEST val; | |
461 | val = unpack_long (type, buf); | |
095a4c96 | 462 | return val; |
fc0c74b1 | 463 | } |
75af7f68 | 464 | |
392a587b JM |
465 | /* Store the address of the place in which to copy the structure the |
466 | subroutine will return. This is called from call_function. | |
467 | ||
468 | We store structs through a pointer passed in the first Argument | |
469 | register. */ | |
470 | ||
f5e1cf12 | 471 | static void |
fba45db2 | 472 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
473 | { |
474 | write_register (ARG1_REGNUM, (addr)); | |
475 | } | |
476 | ||
477 | /* Write into appropriate registers a function return value | |
478 | of type TYPE, given in virtual format. | |
479 | ||
480 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
481 | ||
f5e1cf12 | 482 | static void |
fba45db2 | 483 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b | 484 | { |
3d79a47c MS |
485 | char tmp = 0; |
486 | /* Only char return values need to be shifted right within R0. */ | |
487 | if (TYPE_LENGTH (type) == 1 | |
488 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
489 | { | |
490 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
491 | &tmp, 1); /* zero the high byte */ | |
492 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM) + 1, | |
493 | valbuf, 1); /* copy the low byte */ | |
494 | } | |
495 | else | |
496 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
497 | valbuf, | |
498 | TYPE_LENGTH (type)); | |
392a587b JM |
499 | } |
500 | ||
501 | /* Extract from an array REGBUF containing the (raw) register state | |
502 | the address in which a function should return its structure value, | |
503 | as a CORE_ADDR (or an expression that can be used as one). */ | |
504 | ||
f5e1cf12 | 505 | static CORE_ADDR |
fba45db2 | 506 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
507 | { |
508 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
509 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
510 | | DMEM_START); | |
511 | } | |
512 | ||
f5e1cf12 | 513 | static CORE_ADDR |
fba45db2 | 514 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 515 | { |
78eac43e MS |
516 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
517 | return d10v_make_iaddr (generic_read_register_dummy (frame->pc, | |
518 | frame->frame, | |
519 | PC_REGNUM)); | |
520 | else | |
521 | return ((frame)->extra_info->return_pc); | |
392a587b JM |
522 | } |
523 | ||
392a587b JM |
524 | /* Immediately after a function call, return the saved pc. We can't |
525 | use frame->return_pc beause that is determined by reading R13 off | |
526 | the stack and that may not be written yet. */ | |
527 | ||
f5e1cf12 | 528 | static CORE_ADDR |
fba45db2 | 529 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 530 | { |
c5aa993b | 531 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
532 | | IMEM_START); |
533 | } | |
534 | ||
c906108c SS |
535 | /* Discard from the stack the innermost frame, restoring all saved |
536 | registers. */ | |
537 | ||
f5e1cf12 | 538 | static void |
fba45db2 | 539 | d10v_pop_frame (void) |
cce74817 JM |
540 | { |
541 | generic_pop_current_frame (do_d10v_pop_frame); | |
542 | } | |
543 | ||
544 | static void | |
fba45db2 | 545 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
546 | { |
547 | CORE_ADDR fp; | |
548 | int regnum; | |
c906108c SS |
549 | char raw_buffer[8]; |
550 | ||
cce74817 | 551 | fp = FRAME_FP (fi); |
c906108c SS |
552 | /* fill out fsr with the address of where each */ |
553 | /* register was stored in the frame */ | |
cce74817 | 554 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 555 | |
c906108c | 556 | /* now update the current registers with the old values */ |
4ce44c66 | 557 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 558 | { |
cce74817 | 559 | if (fi->saved_regs[regnum]) |
c906108c | 560 | { |
c5aa993b JM |
561 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
562 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
563 | } |
564 | } | |
565 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
566 | { | |
cce74817 | 567 | if (fi->saved_regs[regnum]) |
c906108c | 568 | { |
c5aa993b | 569 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
570 | } |
571 | } | |
cce74817 | 572 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 573 | { |
c5aa993b | 574 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
575 | } |
576 | ||
577 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 578 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
579 | target_store_registers (-1); |
580 | flush_cached_frames (); | |
581 | } | |
582 | ||
c5aa993b | 583 | static int |
fba45db2 | 584 | check_prologue (unsigned short op) |
c906108c SS |
585 | { |
586 | /* st rn, @-sp */ | |
587 | if ((op & 0x7E1F) == 0x6C1F) | |
588 | return 1; | |
589 | ||
590 | /* st2w rn, @-sp */ | |
591 | if ((op & 0x7E3F) == 0x6E1F) | |
592 | return 1; | |
593 | ||
594 | /* subi sp, n */ | |
595 | if ((op & 0x7FE1) == 0x01E1) | |
596 | return 1; | |
597 | ||
598 | /* mv r11, sp */ | |
599 | if (op == 0x417E) | |
600 | return 1; | |
601 | ||
602 | /* nop */ | |
603 | if (op == 0x5E00) | |
604 | return 1; | |
605 | ||
606 | /* st rn, @sp */ | |
607 | if ((op & 0x7E1F) == 0x681E) | |
608 | return 1; | |
609 | ||
610 | /* st2w rn, @sp */ | |
c5aa993b JM |
611 | if ((op & 0x7E3F) == 0x3A1E) |
612 | return 1; | |
c906108c SS |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
f5e1cf12 | 617 | static CORE_ADDR |
fba45db2 | 618 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
619 | { |
620 | unsigned long op; | |
621 | unsigned short op1, op2; | |
622 | CORE_ADDR func_addr, func_end; | |
623 | struct symtab_and_line sal; | |
624 | ||
625 | /* If we have line debugging information, then the end of the */ | |
626 | /* prologue should the first assembly instruction of the first source line */ | |
627 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
628 | { | |
629 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 630 | if (sal.end && sal.end < func_end) |
c906108c SS |
631 | return sal.end; |
632 | } | |
c5aa993b JM |
633 | |
634 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
635 | return pc; /* Can't access it -- assume no prologue. */ |
636 | ||
637 | while (1) | |
638 | { | |
c5aa993b | 639 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
640 | if ((op & 0xC0000000) == 0xC0000000) |
641 | { | |
642 | /* long instruction */ | |
c5aa993b JM |
643 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
644 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
645 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
646 | break; |
647 | } | |
648 | else | |
649 | { | |
650 | /* short instructions */ | |
651 | if ((op & 0xC0000000) == 0x80000000) | |
652 | { | |
653 | op2 = (op & 0x3FFF8000) >> 15; | |
654 | op1 = op & 0x7FFF; | |
c5aa993b JM |
655 | } |
656 | else | |
c906108c SS |
657 | { |
658 | op1 = (op & 0x3FFF8000) >> 15; | |
659 | op2 = op & 0x7FFF; | |
660 | } | |
c5aa993b | 661 | if (check_prologue (op1)) |
c906108c | 662 | { |
c5aa993b | 663 | if (!check_prologue (op2)) |
c906108c SS |
664 | { |
665 | /* if the previous opcode was really part of the prologue */ | |
666 | /* and not just a NOP, then we want to break after both instructions */ | |
667 | if (op1 != 0x5E00) | |
668 | pc += 4; | |
669 | break; | |
670 | } | |
671 | } | |
672 | else | |
673 | break; | |
674 | } | |
675 | pc += 4; | |
676 | } | |
677 | return pc; | |
678 | } | |
679 | ||
680 | /* Given a GDB frame, determine the address of the calling function's frame. | |
681 | This will be used to create a new GDB frame struct, and then | |
682 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 683 | */ |
c906108c | 684 | |
f5e1cf12 | 685 | static CORE_ADDR |
fba45db2 | 686 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 687 | { |
78eac43e MS |
688 | CORE_ADDR addr; |
689 | ||
690 | /* A generic call dummy's frame is the same as caller's. */ | |
691 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
692 | return fi->frame; | |
693 | ||
cce74817 | 694 | d10v_frame_init_saved_regs (fi); |
c906108c | 695 | |
78eac43e | 696 | |
cce74817 JM |
697 | if (fi->extra_info->return_pc == IMEM_START |
698 | || inside_entry_file (fi->extra_info->return_pc)) | |
78eac43e MS |
699 | { |
700 | /* This is meant to halt the backtrace at "_start". | |
701 | Make sure we don't halt it at a generic dummy frame. */ | |
702 | if (!PC_IN_CALL_DUMMY (fi->extra_info->return_pc, 0, 0)) | |
703 | return (CORE_ADDR) 0; | |
704 | } | |
c906108c | 705 | |
cce74817 | 706 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 707 | { |
cce74817 JM |
708 | if (!fi->saved_regs[SP_REGNUM] |
709 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
710 | return (CORE_ADDR) 0; |
711 | ||
cce74817 | 712 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
713 | } |
714 | ||
78eac43e MS |
715 | addr = read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
716 | REGISTER_RAW_SIZE (FP_REGNUM)); | |
717 | if (addr == 0) | |
c5aa993b | 718 | return (CORE_ADDR) 0; |
c906108c | 719 | |
78eac43e | 720 | return d10v_make_daddr (addr); |
c5aa993b | 721 | } |
c906108c SS |
722 | |
723 | static int next_addr, uses_frame; | |
724 | ||
c5aa993b | 725 | static int |
fba45db2 | 726 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
727 | { |
728 | int n; | |
729 | ||
730 | /* st rn, @-sp */ | |
731 | if ((op & 0x7E1F) == 0x6C1F) | |
732 | { | |
733 | n = (op & 0x1E0) >> 5; | |
734 | next_addr -= 2; | |
cce74817 | 735 | fi->saved_regs[n] = next_addr; |
c906108c SS |
736 | return 1; |
737 | } | |
738 | ||
739 | /* st2w rn, @-sp */ | |
740 | else if ((op & 0x7E3F) == 0x6E1F) | |
741 | { | |
742 | n = (op & 0x1E0) >> 5; | |
743 | next_addr -= 4; | |
cce74817 | 744 | fi->saved_regs[n] = next_addr; |
c5aa993b | 745 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
746 | return 1; |
747 | } | |
748 | ||
749 | /* subi sp, n */ | |
750 | if ((op & 0x7FE1) == 0x01E1) | |
751 | { | |
752 | n = (op & 0x1E) >> 1; | |
753 | if (n == 0) | |
754 | n = 16; | |
755 | next_addr -= n; | |
756 | return 1; | |
757 | } | |
758 | ||
759 | /* mv r11, sp */ | |
760 | if (op == 0x417E) | |
761 | { | |
762 | uses_frame = 1; | |
763 | return 1; | |
764 | } | |
765 | ||
766 | /* nop */ | |
767 | if (op == 0x5E00) | |
768 | return 1; | |
769 | ||
770 | /* st rn, @sp */ | |
771 | if ((op & 0x7E1F) == 0x681E) | |
772 | { | |
773 | n = (op & 0x1E0) >> 5; | |
cce74817 | 774 | fi->saved_regs[n] = next_addr; |
c906108c SS |
775 | return 1; |
776 | } | |
777 | ||
778 | /* st2w rn, @sp */ | |
779 | if ((op & 0x7E3F) == 0x3A1E) | |
780 | { | |
781 | n = (op & 0x1E0) >> 5; | |
cce74817 | 782 | fi->saved_regs[n] = next_addr; |
c5aa993b | 783 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
784 | return 1; |
785 | } | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
cce74817 JM |
790 | /* Put here the code to store, into fi->saved_regs, the addresses of |
791 | the saved registers of frame described by FRAME_INFO. This | |
792 | includes special registers such as pc and fp saved in special ways | |
793 | in the stack frame. sp is even more special: the address we return | |
794 | for it IS the sp for the next frame. */ | |
795 | ||
f5e1cf12 | 796 | static void |
fba45db2 | 797 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
798 | { |
799 | CORE_ADDR fp, pc; | |
800 | unsigned long op; | |
801 | unsigned short op1, op2; | |
802 | int i; | |
803 | ||
804 | fp = fi->frame; | |
cce74817 | 805 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
806 | next_addr = 0; |
807 | ||
808 | pc = get_pc_function_start (fi->pc); | |
809 | ||
810 | uses_frame = 0; | |
811 | while (1) | |
812 | { | |
c5aa993b | 813 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
814 | if ((op & 0xC0000000) == 0xC0000000) |
815 | { | |
816 | /* long instruction */ | |
817 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
818 | { | |
819 | /* add3 sp,sp,n */ | |
820 | short n = op & 0xFFFF; | |
821 | next_addr += n; | |
822 | } | |
823 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
824 | { | |
825 | /* st rn, @(offset,sp) */ | |
826 | short offset = op & 0xFFFF; | |
827 | short n = (op >> 20) & 0xF; | |
cce74817 | 828 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
829 | } |
830 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
831 | { | |
832 | /* st2w rn, @(offset,sp) */ | |
833 | short offset = op & 0xFFFF; | |
834 | short n = (op >> 20) & 0xF; | |
cce74817 | 835 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 836 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
837 | } |
838 | else | |
839 | break; | |
840 | } | |
841 | else | |
842 | { | |
843 | /* short instructions */ | |
844 | if ((op & 0xC0000000) == 0x80000000) | |
845 | { | |
846 | op2 = (op & 0x3FFF8000) >> 15; | |
847 | op1 = op & 0x7FFF; | |
c5aa993b JM |
848 | } |
849 | else | |
c906108c SS |
850 | { |
851 | op1 = (op & 0x3FFF8000) >> 15; | |
852 | op2 = op & 0x7FFF; | |
853 | } | |
78eac43e MS |
854 | if (!prologue_find_regs (op1, fi, pc) |
855 | || !prologue_find_regs (op2, fi, pc)) | |
c906108c SS |
856 | break; |
857 | } | |
858 | pc += 4; | |
859 | } | |
c5aa993b | 860 | |
cce74817 | 861 | fi->extra_info->size = -next_addr; |
c906108c SS |
862 | |
863 | if (!(fp & 0xffff)) | |
095a4c96 | 864 | fp = d10v_read_sp (); |
c906108c | 865 | |
c5aa993b | 866 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 867 | if (fi->saved_regs[i]) |
c906108c | 868 | { |
c5aa993b | 869 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
870 | } |
871 | ||
cce74817 | 872 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 873 | { |
78eac43e MS |
874 | CORE_ADDR return_pc |
875 | = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], | |
876 | REGISTER_RAW_SIZE (LR_REGNUM)); | |
7b570125 | 877 | fi->extra_info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
878 | } |
879 | else | |
880 | { | |
7b570125 | 881 | fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 882 | } |
c5aa993b | 883 | |
78eac43e | 884 | /* The SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 885 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
886 | { |
887 | /* if the FP was saved, that means the current FP is valid, */ | |
888 | /* otherwise, it isn't being used, so we use the SP instead */ | |
889 | if (uses_frame) | |
78eac43e | 890 | fi->saved_regs[SP_REGNUM] |
095a4c96 | 891 | = d10v_read_fp () + fi->extra_info->size; |
c906108c SS |
892 | else |
893 | { | |
cce74817 JM |
894 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
895 | fi->extra_info->frameless = 1; | |
896 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
897 | } |
898 | } | |
899 | } | |
900 | ||
f5e1cf12 | 901 | static void |
fba45db2 | 902 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 903 | { |
cce74817 JM |
904 | fi->extra_info = (struct frame_extra_info *) |
905 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
906 | frame_saved_regs_zalloc (fi); | |
907 | ||
908 | fi->extra_info->frameless = 0; | |
909 | fi->extra_info->size = 0; | |
910 | fi->extra_info->return_pc = 0; | |
c906108c | 911 | |
78eac43e MS |
912 | /* If fi->pc is zero, but this is not the outermost frame, |
913 | then let's snatch the return_pc from the callee, so that | |
914 | PC_IN_CALL_DUMMY will work. */ | |
915 | if (fi->pc == 0 && fi->level != 0 && fi->next != NULL) | |
916 | fi->pc = d10v_frame_saved_pc (fi->next); | |
917 | ||
c906108c SS |
918 | /* The call dummy doesn't save any registers on the stack, so we can |
919 | return now. */ | |
920 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
921 | { | |
922 | return; | |
923 | } | |
924 | else | |
925 | { | |
cce74817 | 926 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
927 | } |
928 | } | |
929 | ||
930 | static void | |
fba45db2 | 931 | show_regs (char *args, int from_tty) |
c906108c SS |
932 | { |
933 | int a; | |
d4f3574e SS |
934 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
935 | (long) read_register (PC_REGNUM), | |
7b570125 | 936 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
937 | (long) read_register (PSW_REGNUM), |
938 | (long) read_register (24), | |
939 | (long) read_register (25), | |
940 | (long) read_register (23)); | |
941 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
942 | (long) read_register (0), | |
943 | (long) read_register (1), | |
944 | (long) read_register (2), | |
945 | (long) read_register (3), | |
946 | (long) read_register (4), | |
947 | (long) read_register (5), | |
948 | (long) read_register (6), | |
949 | (long) read_register (7)); | |
950 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
951 | (long) read_register (8), | |
952 | (long) read_register (9), | |
953 | (long) read_register (10), | |
954 | (long) read_register (11), | |
955 | (long) read_register (12), | |
956 | (long) read_register (13), | |
957 | (long) read_register (14), | |
958 | (long) read_register (15)); | |
4ce44c66 JM |
959 | for (a = 0; a < NR_IMAP_REGS; a++) |
960 | { | |
961 | if (a > 0) | |
962 | printf_filtered (" "); | |
963 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
964 | } | |
965 | if (NR_DMAP_REGS == 1) | |
966 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
967 | else | |
968 | { | |
969 | for (a = 0; a < NR_DMAP_REGS; a++) | |
970 | { | |
971 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
972 | } | |
973 | printf_filtered ("\n"); | |
974 | } | |
975 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
976 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
977 | { |
978 | char num[MAX_REGISTER_RAW_SIZE]; | |
979 | int i; | |
980 | printf_filtered (" "); | |
c5aa993b | 981 | read_register_gen (a, (char *) &num); |
c906108c SS |
982 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
983 | { | |
984 | printf_filtered ("%02x", (num[i] & 0xff)); | |
985 | } | |
986 | } | |
987 | printf_filtered ("\n"); | |
988 | } | |
989 | ||
f5e1cf12 | 990 | static CORE_ADDR |
39f77062 | 991 | d10v_read_pc (ptid_t ptid) |
c906108c | 992 | { |
39f77062 | 993 | ptid_t save_ptid; |
c906108c SS |
994 | CORE_ADDR pc; |
995 | CORE_ADDR retval; | |
996 | ||
39f77062 KB |
997 | save_ptid = inferior_ptid; |
998 | inferior_ptid = ptid; | |
c906108c | 999 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 1000 | inferior_ptid = save_ptid; |
7b570125 | 1001 | retval = d10v_make_iaddr (pc); |
c906108c SS |
1002 | return retval; |
1003 | } | |
1004 | ||
f5e1cf12 | 1005 | static void |
39f77062 | 1006 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 1007 | { |
39f77062 | 1008 | ptid_t save_ptid; |
c906108c | 1009 | |
39f77062 KB |
1010 | save_ptid = inferior_ptid; |
1011 | inferior_ptid = ptid; | |
7b570125 | 1012 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 1013 | inferior_ptid = save_ptid; |
c906108c SS |
1014 | } |
1015 | ||
f5e1cf12 | 1016 | static CORE_ADDR |
fba45db2 | 1017 | d10v_read_sp (void) |
c906108c | 1018 | { |
7b570125 | 1019 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
1020 | } |
1021 | ||
f5e1cf12 | 1022 | static void |
fba45db2 | 1023 | d10v_write_sp (CORE_ADDR val) |
c906108c | 1024 | { |
7b570125 | 1025 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
1026 | } |
1027 | ||
f5e1cf12 | 1028 | static CORE_ADDR |
fba45db2 | 1029 | d10v_read_fp (void) |
c906108c | 1030 | { |
7b570125 | 1031 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
1032 | } |
1033 | ||
1034 | /* Function: push_return_address (pc) | |
1035 | Set up the return address for the inferior function call. | |
1036 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 1037 | |
f5e1cf12 | 1038 | static CORE_ADDR |
fba45db2 | 1039 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 1040 | { |
7b570125 | 1041 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
1042 | return sp; |
1043 | } | |
c5aa993b | 1044 | |
c906108c | 1045 | |
7a292a7a SS |
1046 | /* When arguments must be pushed onto the stack, they go on in reverse |
1047 | order. The below implements a FILO (stack) to do this. */ | |
1048 | ||
1049 | struct stack_item | |
1050 | { | |
1051 | int len; | |
1052 | struct stack_item *prev; | |
1053 | void *data; | |
1054 | }; | |
1055 | ||
a14ed312 KB |
1056 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1057 | void *contents, int len); | |
7a292a7a | 1058 | static struct stack_item * |
fba45db2 | 1059 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1060 | { |
1061 | struct stack_item *si; | |
1062 | si = xmalloc (sizeof (struct stack_item)); | |
1063 | si->data = xmalloc (len); | |
1064 | si->len = len; | |
1065 | si->prev = prev; | |
1066 | memcpy (si->data, contents, len); | |
1067 | return si; | |
1068 | } | |
1069 | ||
a14ed312 | 1070 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1071 | static struct stack_item * |
fba45db2 | 1072 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1073 | { |
1074 | struct stack_item *dead = si; | |
1075 | si = si->prev; | |
b8c9b27d KB |
1076 | xfree (dead->data); |
1077 | xfree (dead); | |
7a292a7a SS |
1078 | return si; |
1079 | } | |
1080 | ||
1081 | ||
f5e1cf12 | 1082 | static CORE_ADDR |
ea7c478f | 1083 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1084 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1085 | { |
1086 | int i; | |
1087 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1088 | struct stack_item *si = NULL; |
7bd91a28 MS |
1089 | long val; |
1090 | ||
1091 | /* If struct_return is true, then the struct return address will | |
1092 | consume one argument-passing register. No need to actually | |
1093 | write the value to the register -- that's done by | |
1094 | d10v_store_struct_return(). */ | |
1095 | ||
1096 | if (struct_return) | |
1097 | regnum++; | |
c5aa993b | 1098 | |
c906108c SS |
1099 | /* Fill in registers and arg lists */ |
1100 | for (i = 0; i < nargs; i++) | |
1101 | { | |
ea7c478f | 1102 | struct value *arg = args[i]; |
c906108c SS |
1103 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1104 | char *contents = VALUE_CONTENTS (arg); | |
1105 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
1106 | int aligned_regnum = (regnum + 1) & ~1; |
1107 | ||
8b279e7a | 1108 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1109 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1110 | /* fits in a single register, do not align */ | |
1111 | { | |
1112 | val = extract_unsigned_integer (contents, len); | |
1113 | write_register (regnum++, val); | |
1114 | } | |
1115 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1116 | /* value fits in remaining registers, store keeping left | |
1117 | aligned */ | |
c906108c | 1118 | { |
7bd91a28 MS |
1119 | int b; |
1120 | regnum = aligned_regnum; | |
1121 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1122 | { |
7bd91a28 | 1123 | val = extract_unsigned_integer (&contents[b], 2); |
c906108c SS |
1124 | write_register (regnum++, val); |
1125 | } | |
7bd91a28 | 1126 | if (b < len) |
c906108c | 1127 | { |
7bd91a28 MS |
1128 | val = extract_unsigned_integer (&contents[b], 1); |
1129 | write_register (regnum++, (val << 8)); | |
c906108c SS |
1130 | } |
1131 | } | |
7bd91a28 MS |
1132 | else |
1133 | { | |
1134 | /* arg will go onto stack */ | |
1135 | regnum = ARGN_REGNUM + 1; | |
1136 | si = push_stack_item (si, contents, len); | |
1137 | } | |
c906108c | 1138 | } |
7a292a7a SS |
1139 | |
1140 | while (si) | |
1141 | { | |
1142 | sp = (sp - si->len) & ~1; | |
1143 | write_memory (sp, si->data, si->len); | |
1144 | si = pop_stack_item (si); | |
1145 | } | |
c5aa993b | 1146 | |
c906108c SS |
1147 | return sp; |
1148 | } | |
1149 | ||
1150 | ||
1151 | /* Given a return value in `regbuf' with a type `valtype', | |
1152 | extract and copy its value into `valbuf'. */ | |
1153 | ||
f5e1cf12 | 1154 | static void |
72623009 KB |
1155 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1156 | char *valbuf) | |
c906108c SS |
1157 | { |
1158 | int len; | |
3d79a47c MS |
1159 | #if 0 |
1160 | printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), | |
1161 | TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, | |
1162 | (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), | |
1163 | REGISTER_RAW_SIZE (RET1_REGNUM))); | |
1164 | #endif | |
1165 | len = TYPE_LENGTH (type); | |
1166 | if (len == 1) | |
c906108c | 1167 | { |
3d79a47c MS |
1168 | unsigned short c; |
1169 | ||
1170 | c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), | |
1171 | REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1172 | store_unsigned_integer (valbuf, 1, c); | |
1173 | } | |
1174 | else if ((len & 1) == 0) | |
1175 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1176 | else | |
1177 | { | |
1178 | /* For return values of odd size, the first byte is in the | |
1179 | least significant part of the first register. The | |
1180 | remaining bytes in remaining registers. Interestingly, | |
1181 | when such values are passed in, the last byte is in the | |
1182 | most significant byte of that same register - wierd. */ | |
1183 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); | |
c906108c SS |
1184 | } |
1185 | } | |
1186 | ||
c2c6d25f JM |
1187 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1188 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1189 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1190 | (segmentation fault). Since the simulator knows all about how the | |
1191 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1192 | |
4ce44c66 | 1193 | static void |
c2c6d25f JM |
1194 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1195 | CORE_ADDR *targ_addr, int *targ_len) | |
1196 | { | |
4ce44c66 JM |
1197 | long out_addr; |
1198 | long out_len; | |
1199 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1200 | &out_addr, | |
1201 | d10v_dmap_register, | |
1202 | d10v_imap_register); | |
1203 | *targ_addr = out_addr; | |
1204 | *targ_len = out_len; | |
c2c6d25f JM |
1205 | } |
1206 | ||
4ce44c66 | 1207 | |
c906108c SS |
1208 | /* The following code implements access to, and display of, the D10V's |
1209 | instruction trace buffer. The buffer consists of 64K or more | |
1210 | 4-byte words of data, of which each words includes an 8-bit count, | |
1211 | an 8-bit segment number, and a 16-bit instruction address. | |
1212 | ||
1213 | In theory, the trace buffer is continuously capturing instruction | |
1214 | data that the CPU presents on its "debug bus", but in practice, the | |
1215 | ROMified GDB stub only enables tracing when it continues or steps | |
1216 | the program, and stops tracing when the program stops; so it | |
1217 | actually works for GDB to read the buffer counter out of memory and | |
1218 | then read each trace word. The counter records where the tracing | |
1219 | stops, but there is no record of where it started, so we remember | |
1220 | the PC when we resumed and then search backwards in the trace | |
1221 | buffer for a word that includes that address. This is not perfect, | |
1222 | because you will miss trace data if the resumption PC is the target | |
1223 | of a branch. (The value of the buffer counter is semi-random, any | |
1224 | trace data from a previous program stop is gone.) */ | |
1225 | ||
1226 | /* The address of the last word recorded in the trace buffer. */ | |
1227 | ||
1228 | #define DBBC_ADDR (0xd80000) | |
1229 | ||
1230 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1231 | ||
1232 | #define TRACE_BUFFER_BASE (0xf40000) | |
1233 | ||
a14ed312 | 1234 | static void trace_command (char *, int); |
c906108c | 1235 | |
a14ed312 | 1236 | static void untrace_command (char *, int); |
c906108c | 1237 | |
a14ed312 | 1238 | static void trace_info (char *, int); |
c906108c | 1239 | |
a14ed312 | 1240 | static void tdisassemble_command (char *, int); |
c906108c | 1241 | |
a14ed312 | 1242 | static void display_trace (int, int); |
c906108c SS |
1243 | |
1244 | /* True when instruction traces are being collected. */ | |
1245 | ||
1246 | static int tracing; | |
1247 | ||
1248 | /* Remembered PC. */ | |
1249 | ||
1250 | static CORE_ADDR last_pc; | |
1251 | ||
1252 | /* True when trace output should be displayed whenever program stops. */ | |
1253 | ||
1254 | static int trace_display; | |
1255 | ||
1256 | /* True when trace listing should include source lines. */ | |
1257 | ||
1258 | static int default_trace_show_source = 1; | |
1259 | ||
c5aa993b JM |
1260 | struct trace_buffer |
1261 | { | |
1262 | int size; | |
1263 | short *counts; | |
1264 | CORE_ADDR *addrs; | |
1265 | } | |
1266 | trace_data; | |
c906108c SS |
1267 | |
1268 | static void | |
fba45db2 | 1269 | trace_command (char *args, int from_tty) |
c906108c SS |
1270 | { |
1271 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1272 | trace_data.size = 0; | |
1273 | if (trace_data.counts == NULL) | |
c5aa993b | 1274 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1275 | if (trace_data.addrs == NULL) |
c5aa993b | 1276 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1277 | |
1278 | tracing = 1; | |
1279 | ||
1280 | printf_filtered ("Tracing is now on.\n"); | |
1281 | } | |
1282 | ||
1283 | static void | |
fba45db2 | 1284 | untrace_command (char *args, int from_tty) |
c906108c SS |
1285 | { |
1286 | tracing = 0; | |
1287 | ||
1288 | printf_filtered ("Tracing is now off.\n"); | |
1289 | } | |
1290 | ||
1291 | static void | |
fba45db2 | 1292 | trace_info (char *args, int from_tty) |
c906108c SS |
1293 | { |
1294 | int i; | |
1295 | ||
1296 | if (trace_data.size) | |
1297 | { | |
1298 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1299 | ||
1300 | for (i = 0; i < trace_data.size; ++i) | |
1301 | { | |
d4f3574e SS |
1302 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1303 | i, | |
1304 | trace_data.counts[i], | |
c906108c | 1305 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1306 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1307 | } |
1308 | } | |
1309 | else | |
1310 | printf_filtered ("No entries in trace buffer.\n"); | |
1311 | ||
1312 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1313 | } | |
1314 | ||
1315 | /* Print the instruction at address MEMADDR in debugged memory, | |
1316 | on STREAM. Returns length of the instruction, in bytes. */ | |
1317 | ||
1318 | static int | |
fba45db2 | 1319 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1320 | { |
1321 | /* If there's no disassembler, something is very wrong. */ | |
1322 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1323 | internal_error (__FILE__, __LINE__, |
1324 | "print_insn: no disassembler"); | |
c906108c | 1325 | |
d7449b42 | 1326 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1327 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1328 | else | |
1329 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1330 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1331 | } |
1332 | ||
392a587b | 1333 | static void |
fba45db2 | 1334 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1335 | { |
1336 | if (!tracing) | |
1337 | return; | |
1338 | ||
1339 | last_pc = read_register (PC_REGNUM); | |
1340 | } | |
1341 | ||
1342 | /* Collect trace data from the target board and format it into a form | |
1343 | more useful for display. */ | |
1344 | ||
392a587b | 1345 | static void |
fba45db2 | 1346 | d10v_eva_get_trace_data (void) |
c906108c SS |
1347 | { |
1348 | int count, i, j, oldsize; | |
1349 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1350 | unsigned int last_trace, trace_word, next_word; | |
1351 | unsigned int *tmpspace; | |
1352 | ||
1353 | if (!tracing) | |
1354 | return; | |
1355 | ||
c5aa993b | 1356 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1357 | |
1358 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1359 | ||
1360 | /* Collect buffer contents from the target, stopping when we reach | |
1361 | the word recorded when execution resumed. */ | |
1362 | ||
1363 | count = 0; | |
1364 | while (last_trace > 0) | |
1365 | { | |
1366 | QUIT; | |
1367 | trace_word = | |
1368 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1369 | trace_addr = trace_word & 0xffff; | |
1370 | last_trace -= 4; | |
1371 | /* Ignore an apparently nonsensical entry. */ | |
1372 | if (trace_addr == 0xffd5) | |
1373 | continue; | |
1374 | tmpspace[count++] = trace_word; | |
1375 | if (trace_addr == last_pc) | |
1376 | break; | |
1377 | if (count > 65535) | |
1378 | break; | |
1379 | } | |
1380 | ||
1381 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1382 | include the last instruction executed and transforming the address | |
1383 | into something that GDB likes. */ | |
1384 | ||
1385 | for (i = 0; i < count; ++i) | |
1386 | { | |
1387 | trace_word = tmpspace[i]; | |
1388 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1389 | trace_addr = trace_word & 0xffff; | |
1390 | next_cnt = (next_word >> 24) & 0xff; | |
1391 | j = trace_data.size + count - i - 1; | |
1392 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1393 | trace_data.counts[j] = next_cnt + 1; | |
1394 | } | |
1395 | ||
1396 | oldsize = trace_data.size; | |
1397 | trace_data.size += count; | |
1398 | ||
b8c9b27d | 1399 | xfree (tmpspace); |
c906108c SS |
1400 | |
1401 | if (trace_display) | |
1402 | display_trace (oldsize, trace_data.size); | |
1403 | } | |
1404 | ||
1405 | static void | |
fba45db2 | 1406 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1407 | { |
1408 | int i, count; | |
1409 | CORE_ADDR low, high; | |
1410 | char *space_index; | |
1411 | ||
1412 | if (!arg) | |
1413 | { | |
1414 | low = 0; | |
1415 | high = trace_data.size; | |
1416 | } | |
1417 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1418 | { | |
1419 | low = parse_and_eval_address (arg); | |
1420 | high = low + 5; | |
1421 | } | |
1422 | else | |
1423 | { | |
1424 | /* Two arguments. */ | |
1425 | *space_index = '\0'; | |
1426 | low = parse_and_eval_address (arg); | |
1427 | high = parse_and_eval_address (space_index + 1); | |
1428 | if (high < low) | |
1429 | high = low; | |
1430 | } | |
1431 | ||
d4f3574e | 1432 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1433 | |
1434 | display_trace (low, high); | |
1435 | ||
1436 | printf_filtered ("End of trace dump.\n"); | |
1437 | gdb_flush (gdb_stdout); | |
1438 | } | |
1439 | ||
1440 | static void | |
fba45db2 | 1441 | display_trace (int low, int high) |
c906108c SS |
1442 | { |
1443 | int i, count, trace_show_source, first, suppress; | |
1444 | CORE_ADDR next_address; | |
1445 | ||
1446 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1447 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1448 | { |
1449 | trace_show_source = 0; | |
1450 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1451 | printf_filtered ("Trace will not display any source.\n"); | |
1452 | } | |
1453 | ||
1454 | first = 1; | |
1455 | suppress = 0; | |
1456 | for (i = low; i < high; ++i) | |
1457 | { | |
1458 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1459 | count = trace_data.counts[i]; |
c906108c SS |
1460 | while (count-- > 0) |
1461 | { | |
1462 | QUIT; | |
1463 | if (trace_show_source) | |
1464 | { | |
1465 | struct symtab_and_line sal, sal_prev; | |
1466 | ||
1467 | sal_prev = find_pc_line (next_address - 4, 0); | |
1468 | sal = find_pc_line (next_address, 0); | |
1469 | ||
1470 | if (sal.symtab) | |
1471 | { | |
1472 | if (first || sal.line != sal_prev.line) | |
1473 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1474 | suppress = 0; | |
1475 | } | |
1476 | else | |
1477 | { | |
1478 | if (!suppress) | |
1479 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1480 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1481 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1482 | suppress = 1; |
1483 | } | |
1484 | } | |
1485 | first = 0; | |
1486 | print_address (next_address, gdb_stdout); | |
1487 | printf_filtered (":"); | |
1488 | printf_filtered ("\t"); | |
1489 | wrap_here (" "); | |
1490 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1491 | printf_filtered ("\n"); | |
1492 | gdb_flush (gdb_stdout); | |
1493 | } | |
1494 | } | |
1495 | } | |
1496 | ||
ac9a91a7 | 1497 | |
0f71a2f6 | 1498 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1499 | |
0f71a2f6 | 1500 | static struct gdbarch * |
fba45db2 | 1501 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1502 | { |
c5aa993b JM |
1503 | static LONGEST d10v_call_dummy_words[] = |
1504 | {0}; | |
0f71a2f6 | 1505 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1506 | int d10v_num_regs; |
1507 | struct gdbarch_tdep *tdep; | |
1508 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1509 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1510 | |
4ce44c66 JM |
1511 | /* Find a candidate among the list of pre-declared architectures. */ |
1512 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1513 | if (arches != NULL) |
1514 | return arches->gdbarch; | |
4ce44c66 JM |
1515 | |
1516 | /* None found, create a new architecture from the information | |
1517 | provided. */ | |
1518 | tdep = XMALLOC (struct gdbarch_tdep); | |
1519 | gdbarch = gdbarch_alloc (&info, tdep); | |
1520 | ||
1521 | switch (info.bfd_arch_info->mach) | |
1522 | { | |
1523 | case bfd_mach_d10v_ts2: | |
1524 | d10v_num_regs = 37; | |
1525 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1526 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1527 | tdep->a0_regnum = TS2_A0_REGNUM; |
1528 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1529 | tdep->dmap_register = d10v_ts2_dmap_register; |
1530 | tdep->imap_register = d10v_ts2_imap_register; | |
1531 | break; | |
1532 | default: | |
1533 | case bfd_mach_d10v_ts3: | |
1534 | d10v_num_regs = 42; | |
1535 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1536 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1537 | tdep->a0_regnum = TS3_A0_REGNUM; |
1538 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1539 | tdep->dmap_register = d10v_ts3_dmap_register; |
1540 | tdep->imap_register = d10v_ts3_imap_register; | |
1541 | break; | |
1542 | } | |
0f71a2f6 JM |
1543 | |
1544 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1545 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1546 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 JM |
1547 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
1548 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1549 | ||
1550 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1551 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1552 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1553 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1554 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1555 | set_gdbarch_register_size (gdbarch, 2); | |
1556 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1557 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1558 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1559 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
8b279e7a | 1560 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
0f71a2f6 JM |
1561 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1562 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1563 | ||
75af7f68 JB |
1564 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1565 | set_gdbarch_addr_bit (gdbarch, 32); | |
1566 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1567 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1568 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1569 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1570 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1571 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1572 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1573 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1574 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1575 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1576 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1577 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1578 | switch (info.byte_order) |
1579 | { | |
d7449b42 | 1580 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1581 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1582 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1583 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1584 | break; | |
778eb05e | 1585 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1586 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1587 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1588 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1589 | break; | |
1590 | default: | |
8e65ff28 AC |
1591 | internal_error (__FILE__, __LINE__, |
1592 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1593 | } |
0f71a2f6 JM |
1594 | |
1595 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1596 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1597 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1598 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1599 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1600 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1601 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1602 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1603 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1604 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1605 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1606 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1607 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1608 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1609 | ||
26e9b323 | 1610 | set_gdbarch_deprecated_extract_return_value (gdbarch, d10v_extract_return_value); |
0f71a2f6 JM |
1611 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); |
1612 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1613 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1614 | ||
0f71a2f6 JM |
1615 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
1616 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
26e9b323 | 1617 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); |
0f71a2f6 JM |
1618 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1619 | ||
1620 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1621 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1622 | ||
1623 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1624 | ||
1625 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1626 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1627 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1628 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1629 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1630 | ||
1631 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1632 | ||
1633 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1634 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1635 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1636 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1637 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
c347ee3e MS |
1638 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
1639 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
0f71a2f6 JM |
1640 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1641 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1642 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1643 | |
7c7651b2 | 1644 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1645 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1646 | |
0f71a2f6 JM |
1647 | return gdbarch; |
1648 | } | |
1649 | ||
1650 | ||
507f3c78 KB |
1651 | extern void (*target_resume_hook) (void); |
1652 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1653 | |
1654 | void | |
fba45db2 | 1655 | _initialize_d10v_tdep (void) |
c906108c | 1656 | { |
0f71a2f6 JM |
1657 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1658 | ||
c906108c SS |
1659 | tm_print_insn = print_insn_d10v; |
1660 | ||
1661 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1662 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1663 | ||
1664 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1665 | ||
cff3e48b | 1666 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1667 | "Enable tracing of instruction execution."); |
1668 | ||
cff3e48b | 1669 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1670 | "Disable tracing of instruction execution."); |
1671 | ||
cff3e48b | 1672 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1673 | "Disassemble the trace buffer.\n\ |
1674 | Two optional arguments specify a range of trace buffer entries\n\ | |
1675 | as reported by info trace (NOT addresses!)."); | |
1676 | ||
cff3e48b | 1677 | add_info ("itrace", trace_info, |
c906108c SS |
1678 | "Display info about the trace data buffer."); |
1679 | ||
cff3e48b | 1680 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1681 | var_integer, (char *) &trace_display, |
1682 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1683 | &showlist); |
cff3e48b | 1684 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1685 | var_integer, (char *) &default_trace_show_source, |
1686 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1687 | &showlist); |
1688 | ||
c5aa993b | 1689 | } |