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Fix compile time warnings & asupport more than 999 symbols
[deliverable/binutils-gdb.git] / gdb / d10v-tdep.c
CommitLineData
c906108c
SS		 1/* Target-dependent code for Mitsubishi D10V, for GDB.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
c5aa993b 4 This file is part of GDB.
c906108c 5
c5aa993b
JM		 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
c906108c 10
c5aa993b
JM		 11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
c906108c 15
c5aa993b
JM		 16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
c906108c
SS		 20
21/* Contributed by Martin Hunt, hunt@cygnus.com */
22
23#include "defs.h"
24#include "frame.h"
25#include "obstack.h"
26#include "symtab.h"
27#include "gdbtypes.h"
28#include "gdbcmd.h"
29#include "gdbcore.h"
30#include "gdb_string.h"
31#include "value.h"
32#include "inferior.h"
c5aa993b 33#include "dis-asm.h"
c906108c
SS		 34#include "symfile.h"
35#include "objfiles.h"
104c1213 36#include "language.h"
c906108c 37
4ce44c66
JM		 38#include "sim-d10v.h"
39
40#undef XMALLOC
41#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
42
cce74817 43struct frame_extra_info
c5aa993b
JM		 44 {
45 CORE_ADDR return_pc;
46 int frameless;
47 int size;
48 };
cce74817 49
4ce44c66
JM		 50struct gdbarch_tdep
51 {
52 int a0_regnum;
53 int nr_dmap_regs;
54 unsigned long (*dmap_register) (int nr);
55 unsigned long (*imap_register) (int nr);
56 int (*register_sim_regno) (int nr);
57 };
58
59/* These are the addresses the D10V-EVA board maps data and
60 instruction memory to. */
cce74817 61
cff3e48b 62#define DMEM_START 0x2000000
cce74817
JM		 63#define IMEM_START 0x1000000
64#define STACK_START 0x0007ffe
65
4ce44c66
JM		 66/* d10v register names. */
67
68enum
69 {
70 R0_REGNUM = 0,
71 LR_REGNUM = 13,
72 PSW_REGNUM = 16,
73 NR_IMAP_REGS = 2,
74 NR_A_REGS = 2
75 };
76#define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
77#define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
78
79/* d10v calling convention. */
cce74817
JM		 80
81#define ARG1_REGNUM R0_REGNUM
82#define ARGN_REGNUM 3
83#define RET1_REGNUM R0_REGNUM
84
392a587b
JM		 85/* Local functions */
86
87extern void _initialize_d10v_tdep PARAMS ((void));
88
89static void d10v_eva_prepare_to_trace PARAMS ((void));
90
91static void d10v_eva_get_trace_data PARAMS ((void));
c906108c 92
c5aa993b 93static int prologue_find_regs PARAMS ((unsigned short op, struct frame_info * fi, CORE_ADDR addr));
cce74817
JM		 94
95extern void d10v_frame_init_saved_regs PARAMS ((struct frame_info *));
96
c5aa993b 97static void do_d10v_pop_frame PARAMS ((struct frame_info * fi));
cce74817 98
c906108c
SS		 99int
100d10v_frame_chain_valid (chain, frame)
101 CORE_ADDR chain;
c5aa993b 102 struct frame_info *frame; /* not used here */
c906108c
SS		 103{
104 return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START);
105}
106
107
108/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
109 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
110 and TYPE is the type (which is known to be struct, union or array).
111
112 The d10v returns anything less than 8 bytes in size in
113 registers. */
114
115int
116d10v_use_struct_convention (gcc_p, type)
117 int gcc_p;
118 struct type *type;
119{
120 return (TYPE_LENGTH (type) > 8);
121}
122
123
392a587b
JM		 124unsigned char *
125d10v_breakpoint_from_pc (pcptr, lenptr)
126 CORE_ADDR *pcptr;
127 int *lenptr;
128{
c5aa993b
JM		 129 static unsigned char breakpoint[] =
130 {0x2f, 0x90, 0x5e, 0x00};
392a587b
JM		 131 *lenptr = sizeof (breakpoint);
132 return breakpoint;
133}
134
4ce44c66
JM		 135/* Map the REG_NR onto an ascii name. Return NULL or an empty string
136 when the reg_nr isn't valid. */
137
138enum ts2_regnums
139 {
140 TS2_IMAP0_REGNUM = 32,
141 TS2_DMAP_REGNUM = 34,
142 TS2_NR_DMAP_REGS = 1,
143 TS2_A0_REGNUM = 35
144 };
145
146static char *
147d10v_ts2_register_name (int reg_nr)
392a587b 148{
c5aa993b
JM		 149 static char *register_names[] =
150 {
151 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
152 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
153 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
154 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
155 "imap0", "imap1", "dmap", "a0", "a1"
392a587b
JM		 156 };
157 if (reg_nr < 0)
158 return NULL;
159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
160 return NULL;
c5aa993b 161 return register_names[reg_nr];
392a587b
JM		 162}
163
4ce44c66
JM		 164enum ts3_regnums
165 {
166 TS3_IMAP0_REGNUM = 36,
167 TS3_DMAP0_REGNUM = 38,
168 TS3_NR_DMAP_REGS = 4,
169 TS3_A0_REGNUM = 32
170 };
171
172static char *
173d10v_ts3_register_name (int reg_nr)
174{
175 static char *register_names[] =
176 {
177 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
178 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
179 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
180 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
181 "a0", "a1",
182 "spi", "spu",
183 "imap0", "imap1",
184 "dmap0", "dmap1", "dmap2", "dmap3"
185 };
186 if (reg_nr < 0)
187 return NULL;
188 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
189 return NULL;
190 return register_names[reg_nr];
191}
192
193/* Access the DMAP/IMAP registers in a target independant way. */
194
195static unsigned long
196d10v_ts2_dmap_register (int reg_nr)
197{
198 switch (reg_nr)
199 {
200 case 0:
201 case 1:
202 return 0x2000;
203 case 2:
204 return read_register (TS2_DMAP_REGNUM);
205 default:
206 return 0;
207 }
208}
209
210static unsigned long
211d10v_ts3_dmap_register (int reg_nr)
212{
213 return read_register (TS3_DMAP0_REGNUM + reg_nr);
214}
215
216static unsigned long
217d10v_dmap_register (int reg_nr)
218{
219 return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
220}
221
222static unsigned long
223d10v_ts2_imap_register (int reg_nr)
224{
225 return read_register (TS2_IMAP0_REGNUM + reg_nr);
226}
227
228static unsigned long
229d10v_ts3_imap_register (int reg_nr)
230{
231 return read_register (TS3_IMAP0_REGNUM + reg_nr);
232}
233
234static unsigned long
235d10v_imap_register (int reg_nr)
236{
237 return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
238}
239
240/* MAP GDB's internal register numbering (determined by the layout fo
241 the REGISTER_BYTE array) onto the simulator's register
242 numbering. */
243
244static int
245d10v_ts2_register_sim_regno (int nr)
246{
247 if (nr >= TS2_IMAP0_REGNUM
248 && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
249 return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
250 if (nr == TS2_DMAP_REGNUM)
251 return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
252 if (nr >= TS2_A0_REGNUM
253 && nr < TS2_A0_REGNUM + NR_A_REGS)
254 return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
255 return nr;
256}
257
258static int
259d10v_ts3_register_sim_regno (int nr)
260{
261 if (nr >= TS3_IMAP0_REGNUM
262 && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
263 return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
264 if (nr >= TS3_DMAP0_REGNUM
265 && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
266 return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
267 if (nr >= TS3_A0_REGNUM
268 && nr < TS3_A0_REGNUM + NR_A_REGS)
269 return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
270 return nr;
271}
272
273int
274d10v_register_sim_regno (int nr)
275{
276 return gdbarch_tdep (current_gdbarch)->register_sim_regno (nr);
277}
392a587b
JM		 278
279/* Index within `registers' of the first byte of the space for
280 register REG_NR. */
281
282int
283d10v_register_byte (reg_nr)
284 int reg_nr;
285{
4ce44c66 286 if (reg_nr < A0_REGNUM)
392a587b 287 return (reg_nr * 2);
4ce44c66
JM		 288 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
289 return (A0_REGNUM * 2
290 + (reg_nr - A0_REGNUM) * 8);
291 else
292 return (A0_REGNUM * 2
293 + NR_A_REGS * 8
294 + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
392a587b
JM		 295}
296
297/* Number of bytes of storage in the actual machine representation for
298 register REG_NR. */
299
300int
301d10v_register_raw_size (reg_nr)
302 int reg_nr;
303{
4ce44c66
JM		 304 if (reg_nr < A0_REGNUM)
305 return 2;
306 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
392a587b
JM		 307 return 8;
308 else
309 return 2;
310}
311
312/* Number of bytes of storage in the program's representation
313 for register N. */
314
315int
316d10v_register_virtual_size (reg_nr)
317 int reg_nr;
318{
4ce44c66 319 return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr));
392a587b
JM		 320}
321
322/* Return the GDB type object for the "standard" data type
323 of data in register N. */
324
325struct type *
326d10v_register_virtual_type (reg_nr)
327 int reg_nr;
328{
4ce44c66
JM		 329 if (reg_nr >= A0_REGNUM
330 && reg_nr < (A0_REGNUM + NR_A_REGS))
331 return builtin_type_int64;
332 else if (reg_nr == PC_REGNUM
333 || reg_nr == SP_REGNUM)
334 return builtin_type_int32;
392a587b 335 else
4ce44c66 336 return builtin_type_int16;
392a587b
JM		 337}
338
392a587b 339/* convert $pc and $sp to/from virtual addresses */
ac9a91a7
JM		 340int
341d10v_register_convertible (nr)
342 int nr;
343{
344 return ((nr) == PC_REGNUM || (nr) == SP_REGNUM);
345}
346
347void
348d10v_register_convert_to_virtual (regnum, type, from, to)
349 int regnum;
350 struct type *type;
351 char *from;
352 char *to;
353{
354 ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum));
355 if (regnum == PC_REGNUM)
356 x = (x << 2) | IMEM_START;
357 else
358 x |= DMEM_START;
359 store_unsigned_integer (to, TYPE_LENGTH (type), x);
392a587b 360}
ac9a91a7
JM		 361
362void
363d10v_register_convert_to_raw (type, regnum, from, to)
364 struct type *type;
365 int regnum;
366 char *from;
367 char *to;
368{
369 ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type));
370 x &= 0x3ffff;
371 if (regnum == PC_REGNUM)
372 x >>= 2;
373 store_unsigned_integer (to, 2, x);
392a587b 374}
ac9a91a7 375
392a587b
JM		 376
377CORE_ADDR
378d10v_make_daddr (x)
379 CORE_ADDR x;
380{
381 return ((x) | DMEM_START);
382}
383
384CORE_ADDR
385d10v_make_iaddr (x)
386 CORE_ADDR x;
387{
388 return (((x) << 2) | IMEM_START);
389}
390
391int
392d10v_daddr_p (x)
393 CORE_ADDR x;
394{
395 return (((x) & 0x3000000) == DMEM_START);
396}
397
398int
399d10v_iaddr_p (x)
400 CORE_ADDR x;
401{
402 return (((x) & 0x3000000) == IMEM_START);
403}
404
405
406CORE_ADDR
407d10v_convert_iaddr_to_raw (x)
408 CORE_ADDR x;
409{
410 return (((x) >> 2) & 0xffff);
411}
412
413CORE_ADDR
c5aa993b 414d10v_convert_daddr_to_raw (x)
392a587b
JM		 415 CORE_ADDR x;
416{
417 return ((x) & 0xffff);
418}
419
420/* Store the address of the place in which to copy the structure the
421 subroutine will return. This is called from call_function.
422
423 We store structs through a pointer passed in the first Argument
424 register. */
425
426void
427d10v_store_struct_return (addr, sp)
428 CORE_ADDR addr;
429 CORE_ADDR sp;
430{
431 write_register (ARG1_REGNUM, (addr));
432}
433
434/* Write into appropriate registers a function return value
435 of type TYPE, given in virtual format.
436
437 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
438
439void
c5aa993b 440d10v_store_return_value (type, valbuf)
392a587b
JM		 441 struct type *type;
442 char *valbuf;
443{
444 write_register_bytes (REGISTER_BYTE (RET1_REGNUM),
445 valbuf,
446 TYPE_LENGTH (type));
447}
448
449/* Extract from an array REGBUF containing the (raw) register state
450 the address in which a function should return its structure value,
451 as a CORE_ADDR (or an expression that can be used as one). */
452
453CORE_ADDR
454d10v_extract_struct_value_address (regbuf)
455 char *regbuf;
456{
457 return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM),
458 REGISTER_RAW_SIZE (ARG1_REGNUM))
459 | DMEM_START);
460}
461
462CORE_ADDR
463d10v_frame_saved_pc (frame)
464 struct frame_info *frame;
465{
cce74817 466 return ((frame)->extra_info->return_pc);
392a587b
JM		 467}
468
469CORE_ADDR
470d10v_frame_args_address (fi)
471 struct frame_info *fi;
472{
473 return (fi)->frame;
474}
475
476CORE_ADDR
477d10v_frame_locals_address (fi)
478 struct frame_info *fi;
479{
480 return (fi)->frame;
481}
482
483/* Immediately after a function call, return the saved pc. We can't
484 use frame->return_pc beause that is determined by reading R13 off
485 the stack and that may not be written yet. */
486
487CORE_ADDR
488d10v_saved_pc_after_call (frame)
489 struct frame_info *frame;
490{
c5aa993b 491 return ((read_register (LR_REGNUM) << 2)
392a587b
JM		 492 | IMEM_START);
493}
494
c906108c
SS		 495/* Discard from the stack the innermost frame, restoring all saved
496 registers. */
497
498void
cce74817
JM		 499d10v_pop_frame ()
500{
501 generic_pop_current_frame (do_d10v_pop_frame);
502}
503
504static void
505do_d10v_pop_frame (fi)
506 struct frame_info *fi;
c906108c
SS		 507{
508 CORE_ADDR fp;
509 int regnum;
c906108c
SS		 510 char raw_buffer[8];
511
cce74817 512 fp = FRAME_FP (fi);
c906108c
SS		 513 /* fill out fsr with the address of where each */
514 /* register was stored in the frame */
cce74817 515 d10v_frame_init_saved_regs (fi);
c5aa993b 516
c906108c 517 /* now update the current registers with the old values */
4ce44c66 518 for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
c906108c 519 {
cce74817 520 if (fi->saved_regs[regnum])
c906108c 521 {
c5aa993b
JM		 522 read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
523 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
c906108c
SS		 524 }
525 }
526 for (regnum = 0; regnum < SP_REGNUM; regnum++)
527 {
cce74817 528 if (fi->saved_regs[regnum])
c906108c 529 {
c5aa993b 530 write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
c906108c
SS		 531 }
532 }
cce74817 533 if (fi->saved_regs[PSW_REGNUM])
c906108c 534 {
c5aa993b 535 write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
c906108c
SS		 536 }
537
538 write_register (PC_REGNUM, read_register (LR_REGNUM));
cce74817 539 write_register (SP_REGNUM, fp + fi->extra_info->size);
c906108c
SS		 540 target_store_registers (-1);
541 flush_cached_frames ();
542}
543
c5aa993b 544static int
c906108c
SS		 545check_prologue (op)
546 unsigned short op;
547{
548 /* st rn, @-sp */
549 if ((op & 0x7E1F) == 0x6C1F)
550 return 1;
551
552 /* st2w rn, @-sp */
553 if ((op & 0x7E3F) == 0x6E1F)
554 return 1;
555
556 /* subi sp, n */
557 if ((op & 0x7FE1) == 0x01E1)
558 return 1;
559
560 /* mv r11, sp */
561 if (op == 0x417E)
562 return 1;
563
564 /* nop */
565 if (op == 0x5E00)
566 return 1;
567
568 /* st rn, @sp */
569 if ((op & 0x7E1F) == 0x681E)
570 return 1;
571
572 /* st2w rn, @sp */
c5aa993b
JM		 573 if ((op & 0x7E3F) == 0x3A1E)
574 return 1;
c906108c
SS		 575
576 return 0;
577}
578
579CORE_ADDR
580d10v_skip_prologue (pc)
581 CORE_ADDR pc;
582{
583 unsigned long op;
584 unsigned short op1, op2;
585 CORE_ADDR func_addr, func_end;
586 struct symtab_and_line sal;
587
588 /* If we have line debugging information, then the end of the */
589 /* prologue should the first assembly instruction of the first source line */
590 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
591 {
592 sal = find_pc_line (func_addr, 0);
c5aa993b 593 if (sal.end && sal.end < func_end)
c906108c
SS		 594 return sal.end;
595 }
c5aa993b
JM		 596
597 if (target_read_memory (pc, (char *) &op, 4))
c906108c
SS		 598 return pc; /* Can't access it -- assume no prologue. */
599
600 while (1)
601 {
c5aa993b 602 op = (unsigned long) read_memory_integer (pc, 4);
c906108c
SS		 603 if ((op & 0xC0000000) == 0xC0000000)
604 {
605 /* long instruction */
c5aa993b
JM		 606 if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
607 ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
608 ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
c906108c
SS		 609 break;
610 }
611 else
612 {
613 /* short instructions */
614 if ((op & 0xC0000000) == 0x80000000)
615 {
616 op2 = (op & 0x3FFF8000) >> 15;
617 op1 = op & 0x7FFF;
c5aa993b
JM		 618 }
619 else
c906108c
SS		 620 {
621 op1 = (op & 0x3FFF8000) >> 15;
622 op2 = op & 0x7FFF;
623 }
c5aa993b 624 if (check_prologue (op1))
c906108c 625 {
c5aa993b 626 if (!check_prologue (op2))
c906108c
SS		 627 {
628 /* if the previous opcode was really part of the prologue */
629 /* and not just a NOP, then we want to break after both instructions */
630 if (op1 != 0x5E00)
631 pc += 4;
632 break;
633 }
634 }
635 else
636 break;
637 }
638 pc += 4;
639 }
640 return pc;
641}
642
643/* Given a GDB frame, determine the address of the calling function's frame.
644 This will be used to create a new GDB frame struct, and then
645 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
c5aa993b 646 */
c906108c
SS		 647
648CORE_ADDR
cce74817
JM		 649d10v_frame_chain (fi)
650 struct frame_info *fi;
c906108c 651{
cce74817 652 d10v_frame_init_saved_regs (fi);
c906108c 653
cce74817
JM		 654 if (fi->extra_info->return_pc == IMEM_START
655 || inside_entry_file (fi->extra_info->return_pc))
c5aa993b 656 return (CORE_ADDR) 0;
c906108c 657
cce74817 658 if (!fi->saved_regs[FP_REGNUM])
c906108c 659 {
cce74817
JM		 660 if (!fi->saved_regs[SP_REGNUM]
661 || fi->saved_regs[SP_REGNUM] == STACK_START)
c5aa993b
JM		 662 return (CORE_ADDR) 0;
663
cce74817 664 return fi->saved_regs[SP_REGNUM];
c906108c
SS		 665 }
666
c5aa993b
JM		 667 if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
668 REGISTER_RAW_SIZE (FP_REGNUM)))
669 return (CORE_ADDR) 0;
c906108c 670
cce74817 671 return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
c5aa993b
JM		 672 REGISTER_RAW_SIZE (FP_REGNUM)));
673}
c906108c
SS		 674
675static int next_addr, uses_frame;
676
c5aa993b 677static int
cce74817 678prologue_find_regs (op, fi, addr)
c906108c 679 unsigned short op;
cce74817 680 struct frame_info *fi;
c906108c
SS		 681 CORE_ADDR addr;
682{
683 int n;
684
685 /* st rn, @-sp */
686 if ((op & 0x7E1F) == 0x6C1F)
687 {
688 n = (op & 0x1E0) >> 5;
689 next_addr -= 2;
cce74817 690 fi->saved_regs[n] = next_addr;
c906108c
SS		 691 return 1;
692 }
693
694 /* st2w rn, @-sp */
695 else if ((op & 0x7E3F) == 0x6E1F)
696 {
697 n = (op & 0x1E0) >> 5;
698 next_addr -= 4;
cce74817 699 fi->saved_regs[n] = next_addr;
c5aa993b 700 fi->saved_regs[n + 1] = next_addr + 2;
c906108c
SS		 701 return 1;
702 }
703
704 /* subi sp, n */
705 if ((op & 0x7FE1) == 0x01E1)
706 {
707 n = (op & 0x1E) >> 1;
708 if (n == 0)
709 n = 16;
710 next_addr -= n;
711 return 1;
712 }
713
714 /* mv r11, sp */
715 if (op == 0x417E)
716 {
717 uses_frame = 1;
718 return 1;
719 }
720
721 /* nop */
722 if (op == 0x5E00)
723 return 1;
724
725 /* st rn, @sp */
726 if ((op & 0x7E1F) == 0x681E)
727 {
728 n = (op & 0x1E0) >> 5;
cce74817 729 fi->saved_regs[n] = next_addr;
c906108c
SS		 730 return 1;
731 }
732
733 /* st2w rn, @sp */
734 if ((op & 0x7E3F) == 0x3A1E)
735 {
736 n = (op & 0x1E0) >> 5;
cce74817 737 fi->saved_regs[n] = next_addr;
c5aa993b 738 fi->saved_regs[n + 1] = next_addr + 2;
c906108c
SS		 739 return 1;
740 }
741
742 return 0;
743}
744
cce74817
JM		 745/* Put here the code to store, into fi->saved_regs, the addresses of
746 the saved registers of frame described by FRAME_INFO. This
747 includes special registers such as pc and fp saved in special ways
748 in the stack frame. sp is even more special: the address we return
749 for it IS the sp for the next frame. */
750
c906108c 751void
cce74817 752d10v_frame_init_saved_regs (fi)
c906108c 753 struct frame_info *fi;
c906108c
SS		 754{
755 CORE_ADDR fp, pc;
756 unsigned long op;
757 unsigned short op1, op2;
758 int i;
759
760 fp = fi->frame;
cce74817 761 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
c906108c
SS		 762 next_addr = 0;
763
764 pc = get_pc_function_start (fi->pc);
765
766 uses_frame = 0;
767 while (1)
768 {
c5aa993b 769 op = (unsigned long) read_memory_integer (pc, 4);
c906108c
SS		 770 if ((op & 0xC0000000) == 0xC0000000)
771 {
772 /* long instruction */
773 if ((op & 0x3FFF0000) == 0x01FF0000)
774 {
775 /* add3 sp,sp,n */
776 short n = op & 0xFFFF;
777 next_addr += n;
778 }
779 else if ((op & 0x3F0F0000) == 0x340F0000)
780 {
781 /* st rn, @(offset,sp) */
782 short offset = op & 0xFFFF;
783 short n = (op >> 20) & 0xF;
cce74817 784 fi->saved_regs[n] = next_addr + offset;
c906108c
SS		 785 }
786 else if ((op & 0x3F1F0000) == 0x350F0000)
787 {
788 /* st2w rn, @(offset,sp) */
789 short offset = op & 0xFFFF;
790 short n = (op >> 20) & 0xF;
cce74817 791 fi->saved_regs[n] = next_addr + offset;
c5aa993b 792 fi->saved_regs[n + 1] = next_addr + offset + 2;
c906108c
SS		 793 }
794 else
795 break;
796 }
797 else
798 {
799 /* short instructions */
800 if ((op & 0xC0000000) == 0x80000000)
801 {
802 op2 = (op & 0x3FFF8000) >> 15;
803 op1 = op & 0x7FFF;
c5aa993b
JM		 804 }
805 else
c906108c
SS		 806 {
807 op1 = (op & 0x3FFF8000) >> 15;
808 op2 = op & 0x7FFF;
809 }
c5aa993b 810 if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc))
c906108c
SS		 811 break;
812 }
813 pc += 4;
814 }
c5aa993b 815
cce74817 816 fi->extra_info->size = -next_addr;
c906108c
SS		 817
818 if (!(fp & 0xffff))
c5aa993b 819 fp = D10V_MAKE_DADDR (read_register (SP_REGNUM));
c906108c 820
c5aa993b 821 for (i = 0; i < NUM_REGS - 1; i++)
cce74817 822 if (fi->saved_regs[i])
c906108c 823 {
c5aa993b 824 fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
c906108c
SS		 825 }
826
cce74817 827 if (fi->saved_regs[LR_REGNUM])
c906108c 828 {
cce74817
JM		 829 CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM));
830 fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc);
c906108c
SS		 831 }
832 else
833 {
c5aa993b 834 fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM));
c906108c 835 }
c5aa993b 836
c906108c 837 /* th SP is not normally (ever?) saved, but check anyway */
cce74817 838 if (!fi->saved_regs[SP_REGNUM])
c906108c
SS		 839 {
840 /* if the FP was saved, that means the current FP is valid, */
841 /* otherwise, it isn't being used, so we use the SP instead */
842 if (uses_frame)
c5aa993b 843 fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size;
c906108c
SS		 844 else
845 {
cce74817
JM		 846 fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
847 fi->extra_info->frameless = 1;
848 fi->saved_regs[FP_REGNUM] = 0;
c906108c
SS		 849 }
850 }
851}
852
853void
854d10v_init_extra_frame_info (fromleaf, fi)
855 int fromleaf;
856 struct frame_info *fi;
857{
cce74817
JM		 858 fi->extra_info = (struct frame_extra_info *)
859 frame_obstack_alloc (sizeof (struct frame_extra_info));
860 frame_saved_regs_zalloc (fi);
861
862 fi->extra_info->frameless = 0;
863 fi->extra_info->size = 0;
864 fi->extra_info->return_pc = 0;
c906108c
SS		 865
866 /* The call dummy doesn't save any registers on the stack, so we can
867 return now. */
868 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
869 {
870 return;
871 }
872 else
873 {
cce74817 874 d10v_frame_init_saved_regs (fi);
c906108c
SS		 875 }
876}
877
878static void
879show_regs (args, from_tty)
880 char *args;
881 int from_tty;
882{
883 int a;
d4f3574e
SS		 884 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
885 (long) read_register (PC_REGNUM),
886 (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)),
887 (long) read_register (PSW_REGNUM),
888 (long) read_register (24),
889 (long) read_register (25),
890 (long) read_register (23));
891 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
892 (long) read_register (0),
893 (long) read_register (1),
894 (long) read_register (2),
895 (long) read_register (3),
896 (long) read_register (4),
897 (long) read_register (5),
898 (long) read_register (6),
899 (long) read_register (7));
900 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
901 (long) read_register (8),
902 (long) read_register (9),
903 (long) read_register (10),
904 (long) read_register (11),
905 (long) read_register (12),
906 (long) read_register (13),
907 (long) read_register (14),
908 (long) read_register (15));
4ce44c66
JM		 909 for (a = 0; a < NR_IMAP_REGS; a++)
910 {
911 if (a > 0)
912 printf_filtered (" ");
913 printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
914 }
915 if (NR_DMAP_REGS == 1)
916 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
917 else
918 {
919 for (a = 0; a < NR_DMAP_REGS; a++)
920 {
921 printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a));
922 }
923 printf_filtered ("\n");
924 }
925 printf_filtered ("A0-A%d", NR_A_REGS - 1);
926 for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
c906108c
SS		 927 {
928 char num[MAX_REGISTER_RAW_SIZE];
929 int i;
930 printf_filtered (" ");
c5aa993b 931 read_register_gen (a, (char *) &num);
c906108c
SS		 932 for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
933 {
934 printf_filtered ("%02x", (num[i] & 0xff));
935 }
936 }
937 printf_filtered ("\n");
938}
939
940CORE_ADDR
941d10v_read_pc (pid)
942 int pid;
943{
944 int save_pid;
945 CORE_ADDR pc;
946 CORE_ADDR retval;
947
948 save_pid = inferior_pid;
949 inferior_pid = pid;
950 pc = (int) read_register (PC_REGNUM);
951 inferior_pid = save_pid;
952 retval = D10V_MAKE_IADDR (pc);
953 return retval;
954}
955
956void
957d10v_write_pc (val, pid)
958 CORE_ADDR val;
959 int pid;
960{
961 int save_pid;
962
963 save_pid = inferior_pid;
964 inferior_pid = pid;
965 write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val));
966 inferior_pid = save_pid;
967}
968
969CORE_ADDR
970d10v_read_sp ()
971{
972 return (D10V_MAKE_DADDR (read_register (SP_REGNUM)));
973}
974
975void
976d10v_write_sp (val)
977 CORE_ADDR val;
978{
979 write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val));
980}
981
982void
983d10v_write_fp (val)
984 CORE_ADDR val;
985{
986 write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val));
987}
988
989CORE_ADDR
990d10v_read_fp ()
991{
c5aa993b 992 return (D10V_MAKE_DADDR (read_register (FP_REGNUM)));
c906108c
SS		 993}
994
995/* Function: push_return_address (pc)
996 Set up the return address for the inferior function call.
997 Needed for targets where we don't actually execute a JSR/BSR instruction */
c5aa993b 998
c906108c
SS		 999CORE_ADDR
1000d10v_push_return_address (pc, sp)
1001 CORE_ADDR pc;
1002 CORE_ADDR sp;
1003{
1004 write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ()));
1005 return sp;
1006}
c5aa993b 1007
c906108c 1008
7a292a7a
SS		 1009/* When arguments must be pushed onto the stack, they go on in reverse
1010 order. The below implements a FILO (stack) to do this. */
1011
1012struct stack_item
1013{
1014 int len;
1015 struct stack_item *prev;
1016 void *data;
1017};
1018
c5aa993b 1019static struct stack_item *push_stack_item PARAMS ((struct stack_item * prev, void *contents, int len));
7a292a7a
SS		 1020static struct stack_item *
1021push_stack_item (prev, contents, len)
1022 struct stack_item *prev;
1023 void *contents;
1024 int len;
1025{
1026 struct stack_item *si;
1027 si = xmalloc (sizeof (struct stack_item));
1028 si->data = xmalloc (len);
1029 si->len = len;
1030 si->prev = prev;
1031 memcpy (si->data, contents, len);
1032 return si;
1033}
1034
c5aa993b 1035static struct stack_item *pop_stack_item PARAMS ((struct stack_item * si));
7a292a7a
SS		 1036static struct stack_item *
1037pop_stack_item (si)
1038 struct stack_item *si;
1039{
1040 struct stack_item *dead = si;
1041 si = si->prev;
1042 free (dead->data);
1043 free (dead);
1044 return si;
1045}
1046
1047
c906108c
SS		 1048CORE_ADDR
1049d10v_push_arguments (nargs, args, sp, struct_return, struct_addr)
1050 int nargs;
1051 value_ptr *args;
1052 CORE_ADDR sp;
1053 int struct_return;
1054 CORE_ADDR struct_addr;
1055{
1056 int i;
1057 int regnum = ARG1_REGNUM;
7a292a7a 1058 struct stack_item *si = NULL;
c5aa993b 1059
c906108c
SS		 1060 /* Fill in registers and arg lists */
1061 for (i = 0; i < nargs; i++)
1062 {
1063 value_ptr arg = args[i];
1064 struct type *type = check_typedef (VALUE_TYPE (arg));
1065 char *contents = VALUE_CONTENTS (arg);
1066 int len = TYPE_LENGTH (type);
1067 /* printf ("push: type=%d len=%d\n", type->code, len); */
1068 if (TYPE_CODE (type) == TYPE_CODE_PTR)
1069 {
1070 /* pointers require special handling - first convert and
1071 then store */
1072 long val = extract_signed_integer (contents, len);
1073 len = 2;
1074 if (TYPE_TARGET_TYPE (type)
1075 && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
1076 {
1077 /* function pointer */
1078 val = D10V_CONVERT_IADDR_TO_RAW (val);
1079 }
1080 else if (D10V_IADDR_P (val))
1081 {
1082 /* also function pointer! */
1083 val = D10V_CONVERT_DADDR_TO_RAW (val);
1084 }
1085 else
1086 {
1087 /* data pointer */
1088 val &= 0xFFFF;
1089 }
1090 if (regnum <= ARGN_REGNUM)
1091 write_register (regnum++, val & 0xffff);
1092 else
1093 {
1094 char ptr[2];
7a292a7a 1095 /* arg will go onto stack */
0f71a2f6 1096 store_address (ptr, 2, val & 0xffff);
7a292a7a 1097 si = push_stack_item (si, ptr, 2);
c906108c
SS		 1098 }
1099 }
1100 else
1101 {
1102 int aligned_regnum = (regnum + 1) & ~1;
1103 if (len <= 2 && regnum <= ARGN_REGNUM)
1104 /* fits in a single register, do not align */
1105 {
1106 long val = extract_unsigned_integer (contents, len);
1107 write_register (regnum++, val);
1108 }
1109 else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
1110 /* value fits in remaining registers, store keeping left
c5aa993b 1111 aligned */
c906108c
SS		 1112 {
1113 int b;
1114 regnum = aligned_regnum;
1115 for (b = 0; b < (len & ~1); b += 2)
1116 {
1117 long val = extract_unsigned_integer (&contents[b], 2);
1118 write_register (regnum++, val);
1119 }
1120 if (b < len)
1121 {
1122 long val = extract_unsigned_integer (&contents[b], 1);
1123 write_register (regnum++, (val << 8));
1124 }
1125 }
1126 else
1127 {
7a292a7a 1128 /* arg will go onto stack */
c5aa993b 1129 regnum = ARGN_REGNUM + 1;
7a292a7a 1130 si = push_stack_item (si, contents, len);
c906108c
SS		 1131 }
1132 }
1133 }
7a292a7a
SS		 1134
1135 while (si)
1136 {
1137 sp = (sp - si->len) & ~1;
1138 write_memory (sp, si->data, si->len);
1139 si = pop_stack_item (si);
1140 }
c5aa993b 1141
c906108c
SS		 1142 return sp;
1143}
1144
1145
1146/* Given a return value in `regbuf' with a type `valtype',
1147 extract and copy its value into `valbuf'. */
1148
1149void
1150d10v_extract_return_value (type, regbuf, valbuf)
1151 struct type *type;
1152 char regbuf[REGISTER_BYTES];
1153 char *valbuf;
1154{
1155 int len;
1156 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1157 if (TYPE_CODE (type) == TYPE_CODE_PTR
1158 && TYPE_TARGET_TYPE (type)
1159 && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC))
1160 {
1161 /* pointer to function */
1162 int num;
1163 short snum;
1164 snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
c5aa993b 1165 store_address (valbuf, 4, D10V_MAKE_IADDR (snum));
c906108c 1166 }
c5aa993b 1167 else if (TYPE_CODE (type) == TYPE_CODE_PTR)
c906108c
SS		 1168 {
1169 /* pointer to data */
1170 int num;
1171 short snum;
1172 snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
c5aa993b 1173 store_address (valbuf, 4, D10V_MAKE_DADDR (snum));
c906108c
SS		 1174 }
1175 else
1176 {
1177 len = TYPE_LENGTH (type);
1178 if (len == 1)
1179 {
1180 unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1181 store_unsigned_integer (valbuf, 1, c);
1182 }
1183 else if ((len & 1) == 0)
1184 memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
1185 else
1186 {
1187 /* For return values of odd size, the first byte is in the
c5aa993b
JM		 1188 least significant part of the first register. The
1189 remaining bytes in remaining registers. Interestingly,
1190 when such values are passed in, the last byte is in the
1191 most significant byte of that same register - wierd. */
c906108c
SS		 1192 memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
1193 }
1194 }
1195}
1196
c2c6d25f
JM		 1197/* Translate a GDB virtual ADDR/LEN into a format the remote target
1198 understands. Returns number of bytes that can be transfered
4ce44c66
JM		 1199 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1200 (segmentation fault). Since the simulator knows all about how the
1201 VM system works, we just call that to do the translation. */
c2c6d25f 1202
4ce44c66 1203static void
c2c6d25f
JM		 1204remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1205 CORE_ADDR *targ_addr, int *targ_len)
1206{
4ce44c66
JM		 1207 long out_addr;
1208 long out_len;
1209 out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
1210 &out_addr,
1211 d10v_dmap_register,
1212 d10v_imap_register);
1213 *targ_addr = out_addr;
1214 *targ_len = out_len;
c2c6d25f
JM		 1215}
1216
4ce44c66 1217
c906108c
SS		 1218/* The following code implements access to, and display of, the D10V's
1219 instruction trace buffer. The buffer consists of 64K or more
1220 4-byte words of data, of which each words includes an 8-bit count,
1221 an 8-bit segment number, and a 16-bit instruction address.
1222
1223 In theory, the trace buffer is continuously capturing instruction
1224 data that the CPU presents on its "debug bus", but in practice, the
1225 ROMified GDB stub only enables tracing when it continues or steps
1226 the program, and stops tracing when the program stops; so it
1227 actually works for GDB to read the buffer counter out of memory and
1228 then read each trace word. The counter records where the tracing
1229 stops, but there is no record of where it started, so we remember
1230 the PC when we resumed and then search backwards in the trace
1231 buffer for a word that includes that address. This is not perfect,
1232 because you will miss trace data if the resumption PC is the target
1233 of a branch. (The value of the buffer counter is semi-random, any
1234 trace data from a previous program stop is gone.) */
1235
1236/* The address of the last word recorded in the trace buffer. */
1237
1238#define DBBC_ADDR (0xd80000)
1239
1240/* The base of the trace buffer, at least for the "Board_0". */
1241
1242#define TRACE_BUFFER_BASE (0xf40000)
1243
1244static void trace_command PARAMS ((char *, int));
1245
1246static void untrace_command PARAMS ((char *, int));
1247
1248static void trace_info PARAMS ((char *, int));
1249
1250static void tdisassemble_command PARAMS ((char *, int));
1251
1252static void display_trace PARAMS ((int, int));
1253
1254/* True when instruction traces are being collected. */
1255
1256static int tracing;
1257
1258/* Remembered PC. */
1259
1260static CORE_ADDR last_pc;
1261
1262/* True when trace output should be displayed whenever program stops. */
1263
1264static int trace_display;
1265
1266/* True when trace listing should include source lines. */
1267
1268static int default_trace_show_source = 1;
1269
c5aa993b
JM		 1270struct trace_buffer
1271 {
1272 int size;
1273 short *counts;
1274 CORE_ADDR *addrs;
1275 }
1276trace_data;
c906108c
SS		 1277
1278static void
1279trace_command (args, from_tty)
1280 char *args;
1281 int from_tty;
1282{
1283 /* Clear the host-side trace buffer, allocating space if needed. */
1284 trace_data.size = 0;
1285 if (trace_data.counts == NULL)
c5aa993b 1286 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
c906108c 1287 if (trace_data.addrs == NULL)
c5aa993b 1288 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
c906108c
SS		 1289
1290 tracing = 1;
1291
1292 printf_filtered ("Tracing is now on.\n");
1293}
1294
1295static void
1296untrace_command (args, from_tty)
1297 char *args;
1298 int from_tty;
1299{
1300 tracing = 0;
1301
1302 printf_filtered ("Tracing is now off.\n");
1303}
1304
1305static void
1306trace_info (args, from_tty)
1307 char *args;
1308 int from_tty;
1309{
1310 int i;
1311
1312 if (trace_data.size)
1313 {
1314 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1315
1316 for (i = 0; i < trace_data.size; ++i)
1317 {
d4f3574e
SS		 1318 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1319 i,
1320 trace_data.counts[i],
c906108c 1321 (trace_data.counts[i] == 1 ? "" : "s"),
d4f3574e 1322 paddr_nz (trace_data.addrs[i]));
c906108c
SS		 1323 }
1324 }
1325 else
1326 printf_filtered ("No entries in trace buffer.\n");
1327
1328 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1329}
1330
1331/* Print the instruction at address MEMADDR in debugged memory,
1332 on STREAM. Returns length of the instruction, in bytes. */
1333
1334static int
1335print_insn (memaddr, stream)
1336 CORE_ADDR memaddr;
1337 GDB_FILE *stream;
1338{
1339 /* If there's no disassembler, something is very wrong. */
1340 if (tm_print_insn == NULL)
11cf8741 1341 internal_error ("print_insn: no disassembler");
c906108c
SS		 1342
1343 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1344 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1345 else
1346 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1347 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1348}
1349
392a587b 1350static void
c906108c
SS		 1351d10v_eva_prepare_to_trace ()
1352{
1353 if (!tracing)
1354 return;
1355
1356 last_pc = read_register (PC_REGNUM);
1357}
1358
1359/* Collect trace data from the target board and format it into a form
1360 more useful for display. */
1361
392a587b 1362static void
c906108c
SS		 1363d10v_eva_get_trace_data ()
1364{
1365 int count, i, j, oldsize;
1366 int trace_addr, trace_seg, trace_cnt, next_cnt;
1367 unsigned int last_trace, trace_word, next_word;
1368 unsigned int *tmpspace;
1369
1370 if (!tracing)
1371 return;
1372
c5aa993b 1373 tmpspace = xmalloc (65536 * sizeof (unsigned int));
c906108c
SS		 1374
1375 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1376
1377 /* Collect buffer contents from the target, stopping when we reach
1378 the word recorded when execution resumed. */
1379
1380 count = 0;
1381 while (last_trace > 0)
1382 {
1383 QUIT;
1384 trace_word =
1385 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1386 trace_addr = trace_word & 0xffff;
1387 last_trace -= 4;
1388 /* Ignore an apparently nonsensical entry. */
1389 if (trace_addr == 0xffd5)
1390 continue;
1391 tmpspace[count++] = trace_word;
1392 if (trace_addr == last_pc)
1393 break;
1394 if (count > 65535)
1395 break;
1396 }
1397
1398 /* Move the data to the host-side trace buffer, adjusting counts to
1399 include the last instruction executed and transforming the address
1400 into something that GDB likes. */
1401
1402 for (i = 0; i < count; ++i)
1403 {
1404 trace_word = tmpspace[i];
1405 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1406 trace_addr = trace_word & 0xffff;
1407 next_cnt = (next_word >> 24) & 0xff;
1408 j = trace_data.size + count - i - 1;
1409 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1410 trace_data.counts[j] = next_cnt + 1;
1411 }
1412
1413 oldsize = trace_data.size;
1414 trace_data.size += count;
1415
1416 free (tmpspace);
1417
1418 if (trace_display)
1419 display_trace (oldsize, trace_data.size);
1420}
1421
1422static void
1423tdisassemble_command (arg, from_tty)
1424 char *arg;
1425 int from_tty;
1426{
1427 int i, count;
1428 CORE_ADDR low, high;
1429 char *space_index;
1430
1431 if (!arg)
1432 {
1433 low = 0;
1434 high = trace_data.size;
1435 }
1436 else if (!(space_index = (char *) strchr (arg, ' ')))
1437 {
1438 low = parse_and_eval_address (arg);
1439 high = low + 5;
1440 }
1441 else
1442 {
1443 /* Two arguments. */
1444 *space_index = '\0';
1445 low = parse_and_eval_address (arg);
1446 high = parse_and_eval_address (space_index + 1);
1447 if (high < low)
1448 high = low;
1449 }
1450
d4f3574e 1451 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
c906108c
SS		 1452
1453 display_trace (low, high);
1454
1455 printf_filtered ("End of trace dump.\n");
1456 gdb_flush (gdb_stdout);
1457}
1458
1459static void
1460display_trace (low, high)
1461 int low, high;
1462{
1463 int i, count, trace_show_source, first, suppress;
1464 CORE_ADDR next_address;
1465
1466 trace_show_source = default_trace_show_source;
c5aa993b 1467 if (!have_full_symbols () && !have_partial_symbols ())
c906108c
SS		 1468 {
1469 trace_show_source = 0;
1470 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1471 printf_filtered ("Trace will not display any source.\n");
1472 }
1473
1474 first = 1;
1475 suppress = 0;
1476 for (i = low; i < high; ++i)
1477 {
1478 next_address = trace_data.addrs[i];
c5aa993b 1479 count = trace_data.counts[i];
c906108c
SS		 1480 while (count-- > 0)
1481 {
1482 QUIT;
1483 if (trace_show_source)
1484 {
1485 struct symtab_and_line sal, sal_prev;
1486
1487 sal_prev = find_pc_line (next_address - 4, 0);
1488 sal = find_pc_line (next_address, 0);
1489
1490 if (sal.symtab)
1491 {
1492 if (first || sal.line != sal_prev.line)
1493 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1494 suppress = 0;
1495 }
1496 else
1497 {
1498 if (!suppress)
1499 /* FIXME-32x64--assumes sal.pc fits in long. */
1500 printf_filtered ("No source file for address %s.\n",
c5aa993b 1501 local_hex_string ((unsigned long) sal.pc));
c906108c
SS		 1502 suppress = 1;
1503 }
1504 }
1505 first = 0;
1506 print_address (next_address, gdb_stdout);
1507 printf_filtered (":");
1508 printf_filtered ("\t");
1509 wrap_here (" ");
1510 next_address = next_address + print_insn (next_address, gdb_stdout);
1511 printf_filtered ("\n");
1512 gdb_flush (gdb_stdout);
1513 }
1514 }
1515}
1516
ac9a91a7 1517
0f71a2f6 1518static gdbarch_init_ftype d10v_gdbarch_init;
4ce44c66 1519
0f71a2f6
JM		 1520static struct gdbarch *
1521d10v_gdbarch_init (info, arches)
1522 struct gdbarch_info info;
1523 struct gdbarch_list *arches;
1524{
c5aa993b
JM		 1525 static LONGEST d10v_call_dummy_words[] =
1526 {0};
0f71a2f6 1527 struct gdbarch *gdbarch;
4ce44c66
JM		 1528 int d10v_num_regs;
1529 struct gdbarch_tdep *tdep;
1530 gdbarch_register_name_ftype *d10v_register_name;
0f71a2f6 1531
4ce44c66
JM		 1532 /* Find a candidate among the list of pre-declared architectures. */
1533 arches = gdbarch_list_lookup_by_info (arches, &info);
0f71a2f6
JM		 1534 if (arches != NULL)
1535 return arches->gdbarch;
4ce44c66
JM		 1536
1537 /* None found, create a new architecture from the information
1538 provided. */
1539 tdep = XMALLOC (struct gdbarch_tdep);
1540 gdbarch = gdbarch_alloc (&info, tdep);
1541
1542 switch (info.bfd_arch_info->mach)
1543 {
1544 case bfd_mach_d10v_ts2:
1545 d10v_num_regs = 37;
1546 d10v_register_name = d10v_ts2_register_name;
1547 tdep->a0_regnum = TS2_A0_REGNUM;
1548 tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
1549 tdep->register_sim_regno = d10v_ts2_register_sim_regno;
1550 tdep->dmap_register = d10v_ts2_dmap_register;
1551 tdep->imap_register = d10v_ts2_imap_register;
1552 break;
1553 default:
1554 case bfd_mach_d10v_ts3:
1555 d10v_num_regs = 42;
1556 d10v_register_name = d10v_ts3_register_name;
1557 tdep->a0_regnum = TS3_A0_REGNUM;
1558 tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
1559 tdep->register_sim_regno = d10v_ts3_register_sim_regno;
1560 tdep->dmap_register = d10v_ts3_dmap_register;
1561 tdep->imap_register = d10v_ts3_imap_register;
1562 break;
1563 }
0f71a2f6
JM		 1564
1565 set_gdbarch_read_pc (gdbarch, d10v_read_pc);
1566 set_gdbarch_write_pc (gdbarch, d10v_write_pc);
1567 set_gdbarch_read_fp (gdbarch, d10v_read_fp);
1568 set_gdbarch_write_fp (gdbarch, d10v_write_fp);
1569 set_gdbarch_read_sp (gdbarch, d10v_read_sp);
1570 set_gdbarch_write_sp (gdbarch, d10v_write_sp);
1571
1572 set_gdbarch_num_regs (gdbarch, d10v_num_regs);
1573 set_gdbarch_sp_regnum (gdbarch, 15);
1574 set_gdbarch_fp_regnum (gdbarch, 11);
1575 set_gdbarch_pc_regnum (gdbarch, 18);
1576 set_gdbarch_register_name (gdbarch, d10v_register_name);
1577 set_gdbarch_register_size (gdbarch, 2);
1578 set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
1579 set_gdbarch_register_byte (gdbarch, d10v_register_byte);
1580 set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
1581 set_gdbarch_max_register_raw_size (gdbarch, 8);
1582 set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size);
1583 set_gdbarch_max_register_virtual_size (gdbarch, 8);
1584 set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
1585
1586 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1587 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1588 set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1589 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1590 set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1591 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1592 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1593 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1594
1595 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1596 set_gdbarch_call_dummy_length (gdbarch, 0);
1597 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1598 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1599 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
1600 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1601 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1602 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1603 set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
1604 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
1605 set_gdbarch_call_dummy_p (gdbarch, 1);
1606 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1607 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1608 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1609
1610 set_gdbarch_register_convertible (gdbarch, d10v_register_convertible);
1611 set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual);
1612 set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw);
1613
1614 set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
1615 set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
1616 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1617 set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
1618
1619 set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr);
1620 set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr);
1621 set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p);
1622 set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p);
1623 set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw);
1624 set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw);
1625
1626 set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
1627 set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
1628 set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
1629 set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
1630
1631 set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
1632 set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
1633
1634 set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
1635
1636 set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
1637 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1638 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1639 set_gdbarch_function_start_offset (gdbarch, 0);
1640 set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
1641
1642 set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
1643
1644 set_gdbarch_frame_args_skip (gdbarch, 0);
1645 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1646 set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
1647 set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
1648 set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
1649 set_gdbarch_frame_args_address (gdbarch, d10v_frame_args_address);
1650 set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address);
1651 set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
1652 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1653
1654 return gdbarch;
1655}
1656
1657
c906108c
SS		 1658extern void (*target_resume_hook) PARAMS ((void));
1659extern void (*target_wait_loop_hook) PARAMS ((void));
1660
1661void
1662_initialize_d10v_tdep ()
1663{
0f71a2f6
JM		 1664 register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
1665
c906108c
SS		 1666 tm_print_insn = print_insn_d10v;
1667
1668 target_resume_hook = d10v_eva_prepare_to_trace;
1669 target_wait_loop_hook = d10v_eva_get_trace_data;
1670
1671 add_com ("regs", class_vars, show_regs, "Print all registers");
1672
cff3e48b 1673 add_com ("itrace", class_support, trace_command,
c906108c
SS		 1674 "Enable tracing of instruction execution.");
1675
cff3e48b 1676 add_com ("iuntrace", class_support, untrace_command,
c906108c
SS		 1677 "Disable tracing of instruction execution.");
1678
cff3e48b 1679 add_com ("itdisassemble", class_vars, tdisassemble_command,
c906108c
SS		 1680 "Disassemble the trace buffer.\n\
1681Two optional arguments specify a range of trace buffer entries\n\
1682as reported by info trace (NOT addresses!).");
1683
cff3e48b 1684 add_info ("itrace", trace_info,
c906108c
SS		 1685 "Display info about the trace data buffer.");
1686
cff3e48b 1687 add_show_from_set (add_set_cmd ("itracedisplay", no_class,
c5aa993b
JM		 1688 var_integer, (char *) &trace_display,
1689 "Set automatic display of trace.\n", &setlist),
c906108c 1690 &showlist);
cff3e48b 1691 add_show_from_set (add_set_cmd ("itracesource", no_class,
c5aa993b
JM		 1692 var_integer, (char *) &default_trace_show_source,
1693 "Set display of source code with trace.\n", &setlist),
c906108c
SS		 1694 &showlist);
1695
c5aa993b 1696}
GDB Binutils - Deliverables
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