Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f AC |
2 | |
3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software | |
4 | Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "obstack.h" | |
28 | #include "symtab.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdb_string.h" | |
33 | #include "value.h" | |
34 | #include "inferior.h" | |
c5aa993b | 35 | #include "dis-asm.h" |
c906108c SS |
36 | #include "symfile.h" |
37 | #include "objfiles.h" | |
104c1213 | 38 | #include "language.h" |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
c906108c | 41 | |
f0d4cc9e | 42 | #include "floatformat.h" |
4ce44c66 JM |
43 | #include "sim-d10v.h" |
44 | ||
cce74817 | 45 | struct frame_extra_info |
c5aa993b JM |
46 | { |
47 | CORE_ADDR return_pc; | |
48 | int frameless; | |
49 | int size; | |
50 | }; | |
cce74817 | 51 | |
4ce44c66 JM |
52 | struct gdbarch_tdep |
53 | { | |
54 | int a0_regnum; | |
55 | int nr_dmap_regs; | |
56 | unsigned long (*dmap_register) (int nr); | |
57 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
58 | }; |
59 | ||
60 | /* These are the addresses the D10V-EVA board maps data and | |
61 | instruction memory to. */ | |
cce74817 | 62 | |
cff3e48b | 63 | #define DMEM_START 0x2000000 |
cce74817 | 64 | #define IMEM_START 0x1000000 |
494e8a93 | 65 | #define STACK_START 0x200bffe |
cce74817 | 66 | |
4ce44c66 JM |
67 | /* d10v register names. */ |
68 | ||
69 | enum | |
70 | { | |
71 | R0_REGNUM = 0, | |
72 | LR_REGNUM = 13, | |
73 | PSW_REGNUM = 16, | |
74 | NR_IMAP_REGS = 2, | |
75 | NR_A_REGS = 2 | |
76 | }; | |
77 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
78 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
79 | ||
80 | /* d10v calling convention. */ | |
cce74817 JM |
81 | |
82 | #define ARG1_REGNUM R0_REGNUM | |
83 | #define ARGN_REGNUM 3 | |
84 | #define RET1_REGNUM R0_REGNUM | |
85 | ||
392a587b JM |
86 | /* Local functions */ |
87 | ||
a14ed312 | 88 | extern void _initialize_d10v_tdep (void); |
392a587b | 89 | |
a14ed312 | 90 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 91 | |
a14ed312 | 92 | static void d10v_eva_get_trace_data (void); |
c906108c | 93 | |
a14ed312 KB |
94 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
95 | CORE_ADDR addr); | |
cce74817 | 96 | |
f5e1cf12 | 97 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 98 | |
a14ed312 | 99 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 100 | |
f5e1cf12 | 101 | static int |
72623009 | 102 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 103 | { |
02da6206 JSC |
104 | return ((chain) != 0 && (frame) != 0 |
105 | && (frame)->pc > IMEM_START | |
106 | && !inside_entry_file (FRAME_SAVED_PC (frame))); | |
c906108c SS |
107 | } |
108 | ||
23964bcd | 109 | static CORE_ADDR |
489137c0 AC |
110 | d10v_stack_align (CORE_ADDR len) |
111 | { | |
112 | return (len + 1) & ~1; | |
113 | } | |
c906108c SS |
114 | |
115 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
116 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
117 | and TYPE is the type (which is known to be struct, union or array). | |
118 | ||
119 | The d10v returns anything less than 8 bytes in size in | |
120 | registers. */ | |
121 | ||
f5e1cf12 | 122 | static int |
fba45db2 | 123 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 124 | { |
02da6206 JSC |
125 | long alignment; |
126 | int i; | |
127 | /* The d10v only passes a struct in a register when that structure | |
128 | has an alignment that matches the size of a register. */ | |
129 | /* If the structure doesn't fit in 4 registers, put it on the | |
130 | stack. */ | |
131 | if (TYPE_LENGTH (type) > 8) | |
132 | return 1; | |
133 | /* If the struct contains only one field, don't put it on the stack | |
134 | - gcc can fit it in one or more registers. */ | |
135 | if (TYPE_NFIELDS (type) == 1) | |
136 | return 0; | |
137 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
138 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
139 | { | |
140 | /* If the alignment changes, just assume it goes on the | |
141 | stack. */ | |
142 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
143 | return 1; | |
144 | } | |
145 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
146 | don't put it on the stack. */ | |
147 | if (alignment == 2 || alignment == 4) | |
148 | return 0; | |
149 | return 1; | |
c906108c SS |
150 | } |
151 | ||
152 | ||
f5e1cf12 | 153 | static unsigned char * |
fba45db2 | 154 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 155 | { |
c5aa993b JM |
156 | static unsigned char breakpoint[] = |
157 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
158 | *lenptr = sizeof (breakpoint); |
159 | return breakpoint; | |
160 | } | |
161 | ||
4ce44c66 JM |
162 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
163 | when the reg_nr isn't valid. */ | |
164 | ||
165 | enum ts2_regnums | |
166 | { | |
167 | TS2_IMAP0_REGNUM = 32, | |
168 | TS2_DMAP_REGNUM = 34, | |
169 | TS2_NR_DMAP_REGS = 1, | |
170 | TS2_A0_REGNUM = 35 | |
171 | }; | |
172 | ||
173 | static char * | |
174 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 175 | { |
c5aa993b JM |
176 | static char *register_names[] = |
177 | { | |
178 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
179 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
180 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
181 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
182 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
183 | }; |
184 | if (reg_nr < 0) | |
185 | return NULL; | |
186 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
187 | return NULL; | |
c5aa993b | 188 | return register_names[reg_nr]; |
392a587b JM |
189 | } |
190 | ||
4ce44c66 JM |
191 | enum ts3_regnums |
192 | { | |
193 | TS3_IMAP0_REGNUM = 36, | |
194 | TS3_DMAP0_REGNUM = 38, | |
195 | TS3_NR_DMAP_REGS = 4, | |
196 | TS3_A0_REGNUM = 32 | |
197 | }; | |
198 | ||
199 | static char * | |
200 | d10v_ts3_register_name (int reg_nr) | |
201 | { | |
202 | static char *register_names[] = | |
203 | { | |
204 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
205 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
206 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
207 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
208 | "a0", "a1", | |
209 | "spi", "spu", | |
210 | "imap0", "imap1", | |
211 | "dmap0", "dmap1", "dmap2", "dmap3" | |
212 | }; | |
213 | if (reg_nr < 0) | |
214 | return NULL; | |
215 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
216 | return NULL; | |
217 | return register_names[reg_nr]; | |
218 | } | |
219 | ||
bf93dfed JB |
220 | /* Access the DMAP/IMAP registers in a target independent way. |
221 | ||
222 | Divide the D10V's 64k data space into four 16k segments: | |
223 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
224 | 0xc000 -- 0xffff. | |
225 | ||
226 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
227 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
228 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
229 | unified memory or instruction memory, under the control of the | |
230 | single DMAP register. | |
231 | ||
232 | On the TS3, there are four DMAP registers, each of which controls | |
233 | one of the segments. */ | |
4ce44c66 JM |
234 | |
235 | static unsigned long | |
236 | d10v_ts2_dmap_register (int reg_nr) | |
237 | { | |
238 | switch (reg_nr) | |
239 | { | |
240 | case 0: | |
241 | case 1: | |
242 | return 0x2000; | |
243 | case 2: | |
244 | return read_register (TS2_DMAP_REGNUM); | |
245 | default: | |
246 | return 0; | |
247 | } | |
248 | } | |
249 | ||
250 | static unsigned long | |
251 | d10v_ts3_dmap_register (int reg_nr) | |
252 | { | |
253 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
254 | } | |
255 | ||
256 | static unsigned long | |
257 | d10v_dmap_register (int reg_nr) | |
258 | { | |
259 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
260 | } | |
261 | ||
262 | static unsigned long | |
263 | d10v_ts2_imap_register (int reg_nr) | |
264 | { | |
265 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
266 | } | |
267 | ||
268 | static unsigned long | |
269 | d10v_ts3_imap_register (int reg_nr) | |
270 | { | |
271 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
272 | } | |
273 | ||
274 | static unsigned long | |
275 | d10v_imap_register (int reg_nr) | |
276 | { | |
277 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
278 | } | |
279 | ||
280 | /* MAP GDB's internal register numbering (determined by the layout fo | |
281 | the REGISTER_BYTE array) onto the simulator's register | |
282 | numbering. */ | |
283 | ||
284 | static int | |
285 | d10v_ts2_register_sim_regno (int nr) | |
286 | { | |
287 | if (nr >= TS2_IMAP0_REGNUM | |
288 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
289 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
290 | if (nr == TS2_DMAP_REGNUM) | |
291 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
292 | if (nr >= TS2_A0_REGNUM | |
293 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
294 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
295 | return nr; | |
296 | } | |
297 | ||
298 | static int | |
299 | d10v_ts3_register_sim_regno (int nr) | |
300 | { | |
301 | if (nr >= TS3_IMAP0_REGNUM | |
302 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
303 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
304 | if (nr >= TS3_DMAP0_REGNUM | |
305 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
306 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
307 | if (nr >= TS3_A0_REGNUM | |
308 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
309 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
310 | return nr; | |
311 | } | |
312 | ||
392a587b JM |
313 | /* Index within `registers' of the first byte of the space for |
314 | register REG_NR. */ | |
315 | ||
f5e1cf12 | 316 | static int |
fba45db2 | 317 | d10v_register_byte (int reg_nr) |
392a587b | 318 | { |
4ce44c66 | 319 | if (reg_nr < A0_REGNUM) |
392a587b | 320 | return (reg_nr * 2); |
4ce44c66 JM |
321 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
322 | return (A0_REGNUM * 2 | |
323 | + (reg_nr - A0_REGNUM) * 8); | |
324 | else | |
325 | return (A0_REGNUM * 2 | |
326 | + NR_A_REGS * 8 | |
327 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
328 | } |
329 | ||
330 | /* Number of bytes of storage in the actual machine representation for | |
331 | register REG_NR. */ | |
332 | ||
f5e1cf12 | 333 | static int |
fba45db2 | 334 | d10v_register_raw_size (int reg_nr) |
392a587b | 335 | { |
4ce44c66 JM |
336 | if (reg_nr < A0_REGNUM) |
337 | return 2; | |
338 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
339 | return 8; |
340 | else | |
341 | return 2; | |
342 | } | |
343 | ||
392a587b JM |
344 | /* Return the GDB type object for the "standard" data type |
345 | of data in register N. */ | |
346 | ||
f5e1cf12 | 347 | static struct type * |
fba45db2 | 348 | d10v_register_virtual_type (int reg_nr) |
392a587b | 349 | { |
75af7f68 JB |
350 | if (reg_nr == PC_REGNUM) |
351 | return builtin_type_void_func_ptr; | |
352 | else if (reg_nr >= A0_REGNUM | |
4ce44c66 JM |
353 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
354 | return builtin_type_int64; | |
392a587b | 355 | else |
4ce44c66 | 356 | return builtin_type_int16; |
392a587b JM |
357 | } |
358 | ||
f5e1cf12 | 359 | static CORE_ADDR |
fba45db2 | 360 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
361 | { |
362 | return ((x) | DMEM_START); | |
363 | } | |
364 | ||
f5e1cf12 | 365 | static CORE_ADDR |
fba45db2 | 366 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
367 | { |
368 | return (((x) << 2) | IMEM_START); | |
369 | } | |
370 | ||
f5e1cf12 | 371 | static int |
fba45db2 | 372 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
373 | { |
374 | return (((x) & 0x3000000) == DMEM_START); | |
375 | } | |
376 | ||
f5e1cf12 | 377 | static int |
fba45db2 | 378 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
379 | { |
380 | return (((x) & 0x3000000) == IMEM_START); | |
381 | } | |
382 | ||
383 | ||
f5e1cf12 | 384 | static CORE_ADDR |
fba45db2 | 385 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
386 | { |
387 | return (((x) >> 2) & 0xffff); | |
388 | } | |
389 | ||
f5e1cf12 | 390 | static CORE_ADDR |
fba45db2 | 391 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
392 | { |
393 | return ((x) & 0xffff); | |
394 | } | |
395 | ||
75af7f68 JB |
396 | static void |
397 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
398 | { | |
399 | /* Is it a code address? */ | |
400 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
401 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
402 | { | |
75af7f68 JB |
403 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
404 | d10v_convert_iaddr_to_raw (addr)); | |
405 | } | |
406 | else | |
407 | { | |
408 | /* Strip off any upper segment bits. */ | |
409 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
410 | d10v_convert_daddr_to_raw (addr)); | |
411 | } | |
412 | } | |
413 | ||
414 | static CORE_ADDR | |
415 | d10v_pointer_to_address (struct type *type, void *buf) | |
416 | { | |
417 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
418 | ||
419 | /* Is it a code address? */ | |
420 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
421 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
422 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
423 | return d10v_make_iaddr (addr); |
424 | else | |
425 | return d10v_make_daddr (addr); | |
426 | } | |
427 | ||
fc0c74b1 AC |
428 | static CORE_ADDR |
429 | d10v_integer_to_address (struct type *type, void *buf) | |
430 | { | |
431 | LONGEST val; | |
432 | val = unpack_long (type, buf); | |
433 | if (TYPE_CODE (type) == TYPE_CODE_INT | |
434 | && TYPE_LENGTH (type) <= TYPE_LENGTH (builtin_type_void_data_ptr)) | |
435 | /* Convert small integers that would would be directly copied into | |
436 | a pointer variable into an address pointing into data space. */ | |
437 | return d10v_make_daddr (val & 0xffff); | |
438 | else | |
439 | /* The value is too large to fit in a pointer. Assume this was | |
440 | intentional and that the user in fact specified a raw address. */ | |
441 | return val; | |
442 | } | |
75af7f68 | 443 | |
392a587b JM |
444 | /* Store the address of the place in which to copy the structure the |
445 | subroutine will return. This is called from call_function. | |
446 | ||
447 | We store structs through a pointer passed in the first Argument | |
448 | register. */ | |
449 | ||
f5e1cf12 | 450 | static void |
fba45db2 | 451 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
452 | { |
453 | write_register (ARG1_REGNUM, (addr)); | |
454 | } | |
455 | ||
456 | /* Write into appropriate registers a function return value | |
457 | of type TYPE, given in virtual format. | |
458 | ||
459 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
460 | ||
f5e1cf12 | 461 | static void |
fba45db2 | 462 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
463 | { |
464 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
465 | valbuf, | |
466 | TYPE_LENGTH (type)); | |
467 | } | |
468 | ||
469 | /* Extract from an array REGBUF containing the (raw) register state | |
470 | the address in which a function should return its structure value, | |
471 | as a CORE_ADDR (or an expression that can be used as one). */ | |
472 | ||
f5e1cf12 | 473 | static CORE_ADDR |
fba45db2 | 474 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
475 | { |
476 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
477 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
478 | | DMEM_START); | |
479 | } | |
480 | ||
f5e1cf12 | 481 | static CORE_ADDR |
fba45db2 | 482 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 483 | { |
cce74817 | 484 | return ((frame)->extra_info->return_pc); |
392a587b JM |
485 | } |
486 | ||
392a587b JM |
487 | /* Immediately after a function call, return the saved pc. We can't |
488 | use frame->return_pc beause that is determined by reading R13 off | |
489 | the stack and that may not be written yet. */ | |
490 | ||
f5e1cf12 | 491 | static CORE_ADDR |
fba45db2 | 492 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 493 | { |
c5aa993b | 494 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
495 | | IMEM_START); |
496 | } | |
497 | ||
c906108c SS |
498 | /* Discard from the stack the innermost frame, restoring all saved |
499 | registers. */ | |
500 | ||
f5e1cf12 | 501 | static void |
fba45db2 | 502 | d10v_pop_frame (void) |
cce74817 JM |
503 | { |
504 | generic_pop_current_frame (do_d10v_pop_frame); | |
505 | } | |
506 | ||
507 | static void | |
fba45db2 | 508 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
509 | { |
510 | CORE_ADDR fp; | |
511 | int regnum; | |
c906108c SS |
512 | char raw_buffer[8]; |
513 | ||
cce74817 | 514 | fp = FRAME_FP (fi); |
c906108c SS |
515 | /* fill out fsr with the address of where each */ |
516 | /* register was stored in the frame */ | |
cce74817 | 517 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 518 | |
c906108c | 519 | /* now update the current registers with the old values */ |
4ce44c66 | 520 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 521 | { |
cce74817 | 522 | if (fi->saved_regs[regnum]) |
c906108c | 523 | { |
c5aa993b JM |
524 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
525 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
526 | } |
527 | } | |
528 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
529 | { | |
cce74817 | 530 | if (fi->saved_regs[regnum]) |
c906108c | 531 | { |
c5aa993b | 532 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
533 | } |
534 | } | |
cce74817 | 535 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 536 | { |
c5aa993b | 537 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
538 | } |
539 | ||
540 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 541 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
542 | target_store_registers (-1); |
543 | flush_cached_frames (); | |
544 | } | |
545 | ||
c5aa993b | 546 | static int |
fba45db2 | 547 | check_prologue (unsigned short op) |
c906108c SS |
548 | { |
549 | /* st rn, @-sp */ | |
550 | if ((op & 0x7E1F) == 0x6C1F) | |
551 | return 1; | |
552 | ||
553 | /* st2w rn, @-sp */ | |
554 | if ((op & 0x7E3F) == 0x6E1F) | |
555 | return 1; | |
556 | ||
557 | /* subi sp, n */ | |
558 | if ((op & 0x7FE1) == 0x01E1) | |
559 | return 1; | |
560 | ||
561 | /* mv r11, sp */ | |
562 | if (op == 0x417E) | |
563 | return 1; | |
564 | ||
565 | /* nop */ | |
566 | if (op == 0x5E00) | |
567 | return 1; | |
568 | ||
569 | /* st rn, @sp */ | |
570 | if ((op & 0x7E1F) == 0x681E) | |
571 | return 1; | |
572 | ||
573 | /* st2w rn, @sp */ | |
c5aa993b JM |
574 | if ((op & 0x7E3F) == 0x3A1E) |
575 | return 1; | |
c906108c SS |
576 | |
577 | return 0; | |
578 | } | |
579 | ||
f5e1cf12 | 580 | static CORE_ADDR |
fba45db2 | 581 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
582 | { |
583 | unsigned long op; | |
584 | unsigned short op1, op2; | |
585 | CORE_ADDR func_addr, func_end; | |
586 | struct symtab_and_line sal; | |
587 | ||
588 | /* If we have line debugging information, then the end of the */ | |
589 | /* prologue should the first assembly instruction of the first source line */ | |
590 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
591 | { | |
592 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 593 | if (sal.end && sal.end < func_end) |
c906108c SS |
594 | return sal.end; |
595 | } | |
c5aa993b JM |
596 | |
597 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
598 | return pc; /* Can't access it -- assume no prologue. */ |
599 | ||
600 | while (1) | |
601 | { | |
c5aa993b | 602 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
603 | if ((op & 0xC0000000) == 0xC0000000) |
604 | { | |
605 | /* long instruction */ | |
c5aa993b JM |
606 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
607 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
608 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
609 | break; |
610 | } | |
611 | else | |
612 | { | |
613 | /* short instructions */ | |
614 | if ((op & 0xC0000000) == 0x80000000) | |
615 | { | |
616 | op2 = (op & 0x3FFF8000) >> 15; | |
617 | op1 = op & 0x7FFF; | |
c5aa993b JM |
618 | } |
619 | else | |
c906108c SS |
620 | { |
621 | op1 = (op & 0x3FFF8000) >> 15; | |
622 | op2 = op & 0x7FFF; | |
623 | } | |
c5aa993b | 624 | if (check_prologue (op1)) |
c906108c | 625 | { |
c5aa993b | 626 | if (!check_prologue (op2)) |
c906108c SS |
627 | { |
628 | /* if the previous opcode was really part of the prologue */ | |
629 | /* and not just a NOP, then we want to break after both instructions */ | |
630 | if (op1 != 0x5E00) | |
631 | pc += 4; | |
632 | break; | |
633 | } | |
634 | } | |
635 | else | |
636 | break; | |
637 | } | |
638 | pc += 4; | |
639 | } | |
640 | return pc; | |
641 | } | |
642 | ||
643 | /* Given a GDB frame, determine the address of the calling function's frame. | |
644 | This will be used to create a new GDB frame struct, and then | |
645 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 646 | */ |
c906108c | 647 | |
f5e1cf12 | 648 | static CORE_ADDR |
fba45db2 | 649 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 650 | { |
cce74817 | 651 | d10v_frame_init_saved_regs (fi); |
c906108c | 652 | |
cce74817 JM |
653 | if (fi->extra_info->return_pc == IMEM_START |
654 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 655 | return (CORE_ADDR) 0; |
c906108c | 656 | |
cce74817 | 657 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 658 | { |
cce74817 JM |
659 | if (!fi->saved_regs[SP_REGNUM] |
660 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
661 | return (CORE_ADDR) 0; |
662 | ||
cce74817 | 663 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
664 | } |
665 | ||
c5aa993b JM |
666 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
667 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
668 | return (CORE_ADDR) 0; | |
c906108c | 669 | |
7b570125 | 670 | return d10v_make_daddr (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
671 | REGISTER_RAW_SIZE (FP_REGNUM))); |
672 | } | |
c906108c SS |
673 | |
674 | static int next_addr, uses_frame; | |
675 | ||
c5aa993b | 676 | static int |
fba45db2 | 677 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
678 | { |
679 | int n; | |
680 | ||
681 | /* st rn, @-sp */ | |
682 | if ((op & 0x7E1F) == 0x6C1F) | |
683 | { | |
684 | n = (op & 0x1E0) >> 5; | |
685 | next_addr -= 2; | |
cce74817 | 686 | fi->saved_regs[n] = next_addr; |
c906108c SS |
687 | return 1; |
688 | } | |
689 | ||
690 | /* st2w rn, @-sp */ | |
691 | else if ((op & 0x7E3F) == 0x6E1F) | |
692 | { | |
693 | n = (op & 0x1E0) >> 5; | |
694 | next_addr -= 4; | |
cce74817 | 695 | fi->saved_regs[n] = next_addr; |
c5aa993b | 696 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
697 | return 1; |
698 | } | |
699 | ||
700 | /* subi sp, n */ | |
701 | if ((op & 0x7FE1) == 0x01E1) | |
702 | { | |
703 | n = (op & 0x1E) >> 1; | |
704 | if (n == 0) | |
705 | n = 16; | |
706 | next_addr -= n; | |
707 | return 1; | |
708 | } | |
709 | ||
710 | /* mv r11, sp */ | |
711 | if (op == 0x417E) | |
712 | { | |
713 | uses_frame = 1; | |
714 | return 1; | |
715 | } | |
716 | ||
717 | /* nop */ | |
718 | if (op == 0x5E00) | |
719 | return 1; | |
720 | ||
721 | /* st rn, @sp */ | |
722 | if ((op & 0x7E1F) == 0x681E) | |
723 | { | |
724 | n = (op & 0x1E0) >> 5; | |
cce74817 | 725 | fi->saved_regs[n] = next_addr; |
c906108c SS |
726 | return 1; |
727 | } | |
728 | ||
729 | /* st2w rn, @sp */ | |
730 | if ((op & 0x7E3F) == 0x3A1E) | |
731 | { | |
732 | n = (op & 0x1E0) >> 5; | |
cce74817 | 733 | fi->saved_regs[n] = next_addr; |
c5aa993b | 734 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
735 | return 1; |
736 | } | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
cce74817 JM |
741 | /* Put here the code to store, into fi->saved_regs, the addresses of |
742 | the saved registers of frame described by FRAME_INFO. This | |
743 | includes special registers such as pc and fp saved in special ways | |
744 | in the stack frame. sp is even more special: the address we return | |
745 | for it IS the sp for the next frame. */ | |
746 | ||
f5e1cf12 | 747 | static void |
fba45db2 | 748 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
749 | { |
750 | CORE_ADDR fp, pc; | |
751 | unsigned long op; | |
752 | unsigned short op1, op2; | |
753 | int i; | |
754 | ||
755 | fp = fi->frame; | |
cce74817 | 756 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
757 | next_addr = 0; |
758 | ||
759 | pc = get_pc_function_start (fi->pc); | |
760 | ||
761 | uses_frame = 0; | |
762 | while (1) | |
763 | { | |
c5aa993b | 764 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
765 | if ((op & 0xC0000000) == 0xC0000000) |
766 | { | |
767 | /* long instruction */ | |
768 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
769 | { | |
770 | /* add3 sp,sp,n */ | |
771 | short n = op & 0xFFFF; | |
772 | next_addr += n; | |
773 | } | |
774 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
775 | { | |
776 | /* st rn, @(offset,sp) */ | |
777 | short offset = op & 0xFFFF; | |
778 | short n = (op >> 20) & 0xF; | |
cce74817 | 779 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
780 | } |
781 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
782 | { | |
783 | /* st2w rn, @(offset,sp) */ | |
784 | short offset = op & 0xFFFF; | |
785 | short n = (op >> 20) & 0xF; | |
cce74817 | 786 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 787 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
788 | } |
789 | else | |
790 | break; | |
791 | } | |
792 | else | |
793 | { | |
794 | /* short instructions */ | |
795 | if ((op & 0xC0000000) == 0x80000000) | |
796 | { | |
797 | op2 = (op & 0x3FFF8000) >> 15; | |
798 | op1 = op & 0x7FFF; | |
c5aa993b JM |
799 | } |
800 | else | |
c906108c SS |
801 | { |
802 | op1 = (op & 0x3FFF8000) >> 15; | |
803 | op2 = op & 0x7FFF; | |
804 | } | |
c5aa993b | 805 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
806 | break; |
807 | } | |
808 | pc += 4; | |
809 | } | |
c5aa993b | 810 | |
cce74817 | 811 | fi->extra_info->size = -next_addr; |
c906108c SS |
812 | |
813 | if (!(fp & 0xffff)) | |
7b570125 | 814 | fp = d10v_make_daddr (read_register (SP_REGNUM)); |
c906108c | 815 | |
c5aa993b | 816 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 817 | if (fi->saved_regs[i]) |
c906108c | 818 | { |
c5aa993b | 819 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
820 | } |
821 | ||
cce74817 | 822 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 823 | { |
cce74817 | 824 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
7b570125 | 825 | fi->extra_info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
826 | } |
827 | else | |
828 | { | |
7b570125 | 829 | fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 830 | } |
c5aa993b | 831 | |
c906108c | 832 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 833 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
834 | { |
835 | /* if the FP was saved, that means the current FP is valid, */ | |
836 | /* otherwise, it isn't being used, so we use the SP instead */ | |
837 | if (uses_frame) | |
c5aa993b | 838 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
839 | else |
840 | { | |
cce74817 JM |
841 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
842 | fi->extra_info->frameless = 1; | |
843 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
844 | } |
845 | } | |
846 | } | |
847 | ||
f5e1cf12 | 848 | static void |
fba45db2 | 849 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 850 | { |
cce74817 JM |
851 | fi->extra_info = (struct frame_extra_info *) |
852 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
853 | frame_saved_regs_zalloc (fi); | |
854 | ||
855 | fi->extra_info->frameless = 0; | |
856 | fi->extra_info->size = 0; | |
857 | fi->extra_info->return_pc = 0; | |
c906108c SS |
858 | |
859 | /* The call dummy doesn't save any registers on the stack, so we can | |
860 | return now. */ | |
861 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
862 | { | |
863 | return; | |
864 | } | |
865 | else | |
866 | { | |
cce74817 | 867 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
868 | } |
869 | } | |
870 | ||
871 | static void | |
fba45db2 | 872 | show_regs (char *args, int from_tty) |
c906108c SS |
873 | { |
874 | int a; | |
d4f3574e SS |
875 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
876 | (long) read_register (PC_REGNUM), | |
7b570125 | 877 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
878 | (long) read_register (PSW_REGNUM), |
879 | (long) read_register (24), | |
880 | (long) read_register (25), | |
881 | (long) read_register (23)); | |
882 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
883 | (long) read_register (0), | |
884 | (long) read_register (1), | |
885 | (long) read_register (2), | |
886 | (long) read_register (3), | |
887 | (long) read_register (4), | |
888 | (long) read_register (5), | |
889 | (long) read_register (6), | |
890 | (long) read_register (7)); | |
891 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
892 | (long) read_register (8), | |
893 | (long) read_register (9), | |
894 | (long) read_register (10), | |
895 | (long) read_register (11), | |
896 | (long) read_register (12), | |
897 | (long) read_register (13), | |
898 | (long) read_register (14), | |
899 | (long) read_register (15)); | |
4ce44c66 JM |
900 | for (a = 0; a < NR_IMAP_REGS; a++) |
901 | { | |
902 | if (a > 0) | |
903 | printf_filtered (" "); | |
904 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
905 | } | |
906 | if (NR_DMAP_REGS == 1) | |
907 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
908 | else | |
909 | { | |
910 | for (a = 0; a < NR_DMAP_REGS; a++) | |
911 | { | |
912 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
913 | } | |
914 | printf_filtered ("\n"); | |
915 | } | |
916 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
917 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
918 | { |
919 | char num[MAX_REGISTER_RAW_SIZE]; | |
920 | int i; | |
921 | printf_filtered (" "); | |
c5aa993b | 922 | read_register_gen (a, (char *) &num); |
c906108c SS |
923 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
924 | { | |
925 | printf_filtered ("%02x", (num[i] & 0xff)); | |
926 | } | |
927 | } | |
928 | printf_filtered ("\n"); | |
929 | } | |
930 | ||
f5e1cf12 | 931 | static CORE_ADDR |
39f77062 | 932 | d10v_read_pc (ptid_t ptid) |
c906108c | 933 | { |
39f77062 | 934 | ptid_t save_ptid; |
c906108c SS |
935 | CORE_ADDR pc; |
936 | CORE_ADDR retval; | |
937 | ||
39f77062 KB |
938 | save_ptid = inferior_ptid; |
939 | inferior_ptid = ptid; | |
c906108c | 940 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 941 | inferior_ptid = save_ptid; |
7b570125 | 942 | retval = d10v_make_iaddr (pc); |
c906108c SS |
943 | return retval; |
944 | } | |
945 | ||
f5e1cf12 | 946 | static void |
39f77062 | 947 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 948 | { |
39f77062 | 949 | ptid_t save_ptid; |
c906108c | 950 | |
39f77062 KB |
951 | save_ptid = inferior_ptid; |
952 | inferior_ptid = ptid; | |
7b570125 | 953 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 954 | inferior_ptid = save_ptid; |
c906108c SS |
955 | } |
956 | ||
f5e1cf12 | 957 | static CORE_ADDR |
fba45db2 | 958 | d10v_read_sp (void) |
c906108c | 959 | { |
7b570125 | 960 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
961 | } |
962 | ||
f5e1cf12 | 963 | static void |
fba45db2 | 964 | d10v_write_sp (CORE_ADDR val) |
c906108c | 965 | { |
7b570125 | 966 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
967 | } |
968 | ||
f5e1cf12 | 969 | static void |
fba45db2 | 970 | d10v_write_fp (CORE_ADDR val) |
c906108c | 971 | { |
7b570125 | 972 | write_register (FP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
973 | } |
974 | ||
f5e1cf12 | 975 | static CORE_ADDR |
fba45db2 | 976 | d10v_read_fp (void) |
c906108c | 977 | { |
7b570125 | 978 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
979 | } |
980 | ||
981 | /* Function: push_return_address (pc) | |
982 | Set up the return address for the inferior function call. | |
983 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 984 | |
f5e1cf12 | 985 | static CORE_ADDR |
fba45db2 | 986 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 987 | { |
7b570125 | 988 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
989 | return sp; |
990 | } | |
c5aa993b | 991 | |
c906108c | 992 | |
7a292a7a SS |
993 | /* When arguments must be pushed onto the stack, they go on in reverse |
994 | order. The below implements a FILO (stack) to do this. */ | |
995 | ||
996 | struct stack_item | |
997 | { | |
998 | int len; | |
999 | struct stack_item *prev; | |
1000 | void *data; | |
1001 | }; | |
1002 | ||
a14ed312 KB |
1003 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1004 | void *contents, int len); | |
7a292a7a | 1005 | static struct stack_item * |
fba45db2 | 1006 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1007 | { |
1008 | struct stack_item *si; | |
1009 | si = xmalloc (sizeof (struct stack_item)); | |
1010 | si->data = xmalloc (len); | |
1011 | si->len = len; | |
1012 | si->prev = prev; | |
1013 | memcpy (si->data, contents, len); | |
1014 | return si; | |
1015 | } | |
1016 | ||
a14ed312 | 1017 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1018 | static struct stack_item * |
fba45db2 | 1019 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1020 | { |
1021 | struct stack_item *dead = si; | |
1022 | si = si->prev; | |
b8c9b27d KB |
1023 | xfree (dead->data); |
1024 | xfree (dead); | |
7a292a7a SS |
1025 | return si; |
1026 | } | |
1027 | ||
1028 | ||
f5e1cf12 | 1029 | static CORE_ADDR |
ea7c478f | 1030 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1031 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1032 | { |
1033 | int i; | |
1034 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1035 | struct stack_item *si = NULL; |
c5aa993b | 1036 | |
c906108c SS |
1037 | /* Fill in registers and arg lists */ |
1038 | for (i = 0; i < nargs; i++) | |
1039 | { | |
ea7c478f | 1040 | struct value *arg = args[i]; |
c906108c SS |
1041 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1042 | char *contents = VALUE_CONTENTS (arg); | |
1043 | int len = TYPE_LENGTH (type); | |
1044 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
c906108c SS |
1045 | { |
1046 | int aligned_regnum = (regnum + 1) & ~1; | |
1047 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1048 | /* fits in a single register, do not align */ | |
1049 | { | |
1050 | long val = extract_unsigned_integer (contents, len); | |
1051 | write_register (regnum++, val); | |
1052 | } | |
1053 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1054 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1055 | aligned */ |
c906108c SS |
1056 | { |
1057 | int b; | |
1058 | regnum = aligned_regnum; | |
1059 | for (b = 0; b < (len & ~1); b += 2) | |
1060 | { | |
1061 | long val = extract_unsigned_integer (&contents[b], 2); | |
1062 | write_register (regnum++, val); | |
1063 | } | |
1064 | if (b < len) | |
1065 | { | |
1066 | long val = extract_unsigned_integer (&contents[b], 1); | |
1067 | write_register (regnum++, (val << 8)); | |
1068 | } | |
1069 | } | |
1070 | else | |
1071 | { | |
7a292a7a | 1072 | /* arg will go onto stack */ |
c5aa993b | 1073 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1074 | si = push_stack_item (si, contents, len); |
c906108c SS |
1075 | } |
1076 | } | |
1077 | } | |
7a292a7a SS |
1078 | |
1079 | while (si) | |
1080 | { | |
1081 | sp = (sp - si->len) & ~1; | |
1082 | write_memory (sp, si->data, si->len); | |
1083 | si = pop_stack_item (si); | |
1084 | } | |
c5aa993b | 1085 | |
c906108c SS |
1086 | return sp; |
1087 | } | |
1088 | ||
1089 | ||
1090 | /* Given a return value in `regbuf' with a type `valtype', | |
1091 | extract and copy its value into `valbuf'. */ | |
1092 | ||
f5e1cf12 | 1093 | static void |
72623009 KB |
1094 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1095 | char *valbuf) | |
c906108c SS |
1096 | { |
1097 | int len; | |
1098 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
c906108c SS |
1099 | { |
1100 | len = TYPE_LENGTH (type); | |
1101 | if (len == 1) | |
1102 | { | |
1103 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1104 | store_unsigned_integer (valbuf, 1, c); | |
1105 | } | |
1106 | else if ((len & 1) == 0) | |
1107 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1108 | else | |
1109 | { | |
1110 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1111 | least significant part of the first register. The |
1112 | remaining bytes in remaining registers. Interestingly, | |
1113 | when such values are passed in, the last byte is in the | |
1114 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1115 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1116 | } | |
1117 | } | |
1118 | } | |
1119 | ||
c2c6d25f JM |
1120 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1121 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1122 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1123 | (segmentation fault). Since the simulator knows all about how the | |
1124 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1125 | |
4ce44c66 | 1126 | static void |
c2c6d25f JM |
1127 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1128 | CORE_ADDR *targ_addr, int *targ_len) | |
1129 | { | |
4ce44c66 JM |
1130 | long out_addr; |
1131 | long out_len; | |
1132 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1133 | &out_addr, | |
1134 | d10v_dmap_register, | |
1135 | d10v_imap_register); | |
1136 | *targ_addr = out_addr; | |
1137 | *targ_len = out_len; | |
c2c6d25f JM |
1138 | } |
1139 | ||
4ce44c66 | 1140 | |
c906108c SS |
1141 | /* The following code implements access to, and display of, the D10V's |
1142 | instruction trace buffer. The buffer consists of 64K or more | |
1143 | 4-byte words of data, of which each words includes an 8-bit count, | |
1144 | an 8-bit segment number, and a 16-bit instruction address. | |
1145 | ||
1146 | In theory, the trace buffer is continuously capturing instruction | |
1147 | data that the CPU presents on its "debug bus", but in practice, the | |
1148 | ROMified GDB stub only enables tracing when it continues or steps | |
1149 | the program, and stops tracing when the program stops; so it | |
1150 | actually works for GDB to read the buffer counter out of memory and | |
1151 | then read each trace word. The counter records where the tracing | |
1152 | stops, but there is no record of where it started, so we remember | |
1153 | the PC when we resumed and then search backwards in the trace | |
1154 | buffer for a word that includes that address. This is not perfect, | |
1155 | because you will miss trace data if the resumption PC is the target | |
1156 | of a branch. (The value of the buffer counter is semi-random, any | |
1157 | trace data from a previous program stop is gone.) */ | |
1158 | ||
1159 | /* The address of the last word recorded in the trace buffer. */ | |
1160 | ||
1161 | #define DBBC_ADDR (0xd80000) | |
1162 | ||
1163 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1164 | ||
1165 | #define TRACE_BUFFER_BASE (0xf40000) | |
1166 | ||
a14ed312 | 1167 | static void trace_command (char *, int); |
c906108c | 1168 | |
a14ed312 | 1169 | static void untrace_command (char *, int); |
c906108c | 1170 | |
a14ed312 | 1171 | static void trace_info (char *, int); |
c906108c | 1172 | |
a14ed312 | 1173 | static void tdisassemble_command (char *, int); |
c906108c | 1174 | |
a14ed312 | 1175 | static void display_trace (int, int); |
c906108c SS |
1176 | |
1177 | /* True when instruction traces are being collected. */ | |
1178 | ||
1179 | static int tracing; | |
1180 | ||
1181 | /* Remembered PC. */ | |
1182 | ||
1183 | static CORE_ADDR last_pc; | |
1184 | ||
1185 | /* True when trace output should be displayed whenever program stops. */ | |
1186 | ||
1187 | static int trace_display; | |
1188 | ||
1189 | /* True when trace listing should include source lines. */ | |
1190 | ||
1191 | static int default_trace_show_source = 1; | |
1192 | ||
c5aa993b JM |
1193 | struct trace_buffer |
1194 | { | |
1195 | int size; | |
1196 | short *counts; | |
1197 | CORE_ADDR *addrs; | |
1198 | } | |
1199 | trace_data; | |
c906108c SS |
1200 | |
1201 | static void | |
fba45db2 | 1202 | trace_command (char *args, int from_tty) |
c906108c SS |
1203 | { |
1204 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1205 | trace_data.size = 0; | |
1206 | if (trace_data.counts == NULL) | |
c5aa993b | 1207 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1208 | if (trace_data.addrs == NULL) |
c5aa993b | 1209 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1210 | |
1211 | tracing = 1; | |
1212 | ||
1213 | printf_filtered ("Tracing is now on.\n"); | |
1214 | } | |
1215 | ||
1216 | static void | |
fba45db2 | 1217 | untrace_command (char *args, int from_tty) |
c906108c SS |
1218 | { |
1219 | tracing = 0; | |
1220 | ||
1221 | printf_filtered ("Tracing is now off.\n"); | |
1222 | } | |
1223 | ||
1224 | static void | |
fba45db2 | 1225 | trace_info (char *args, int from_tty) |
c906108c SS |
1226 | { |
1227 | int i; | |
1228 | ||
1229 | if (trace_data.size) | |
1230 | { | |
1231 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1232 | ||
1233 | for (i = 0; i < trace_data.size; ++i) | |
1234 | { | |
d4f3574e SS |
1235 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1236 | i, | |
1237 | trace_data.counts[i], | |
c906108c | 1238 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1239 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1240 | } |
1241 | } | |
1242 | else | |
1243 | printf_filtered ("No entries in trace buffer.\n"); | |
1244 | ||
1245 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1246 | } | |
1247 | ||
1248 | /* Print the instruction at address MEMADDR in debugged memory, | |
1249 | on STREAM. Returns length of the instruction, in bytes. */ | |
1250 | ||
1251 | static int | |
fba45db2 | 1252 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1253 | { |
1254 | /* If there's no disassembler, something is very wrong. */ | |
1255 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1256 | internal_error (__FILE__, __LINE__, |
1257 | "print_insn: no disassembler"); | |
c906108c | 1258 | |
d7449b42 | 1259 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1260 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1261 | else | |
1262 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1263 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1264 | } |
1265 | ||
392a587b | 1266 | static void |
fba45db2 | 1267 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1268 | { |
1269 | if (!tracing) | |
1270 | return; | |
1271 | ||
1272 | last_pc = read_register (PC_REGNUM); | |
1273 | } | |
1274 | ||
1275 | /* Collect trace data from the target board and format it into a form | |
1276 | more useful for display. */ | |
1277 | ||
392a587b | 1278 | static void |
fba45db2 | 1279 | d10v_eva_get_trace_data (void) |
c906108c SS |
1280 | { |
1281 | int count, i, j, oldsize; | |
1282 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1283 | unsigned int last_trace, trace_word, next_word; | |
1284 | unsigned int *tmpspace; | |
1285 | ||
1286 | if (!tracing) | |
1287 | return; | |
1288 | ||
c5aa993b | 1289 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1290 | |
1291 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1292 | ||
1293 | /* Collect buffer contents from the target, stopping when we reach | |
1294 | the word recorded when execution resumed. */ | |
1295 | ||
1296 | count = 0; | |
1297 | while (last_trace > 0) | |
1298 | { | |
1299 | QUIT; | |
1300 | trace_word = | |
1301 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1302 | trace_addr = trace_word & 0xffff; | |
1303 | last_trace -= 4; | |
1304 | /* Ignore an apparently nonsensical entry. */ | |
1305 | if (trace_addr == 0xffd5) | |
1306 | continue; | |
1307 | tmpspace[count++] = trace_word; | |
1308 | if (trace_addr == last_pc) | |
1309 | break; | |
1310 | if (count > 65535) | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1315 | include the last instruction executed and transforming the address | |
1316 | into something that GDB likes. */ | |
1317 | ||
1318 | for (i = 0; i < count; ++i) | |
1319 | { | |
1320 | trace_word = tmpspace[i]; | |
1321 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1322 | trace_addr = trace_word & 0xffff; | |
1323 | next_cnt = (next_word >> 24) & 0xff; | |
1324 | j = trace_data.size + count - i - 1; | |
1325 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1326 | trace_data.counts[j] = next_cnt + 1; | |
1327 | } | |
1328 | ||
1329 | oldsize = trace_data.size; | |
1330 | trace_data.size += count; | |
1331 | ||
b8c9b27d | 1332 | xfree (tmpspace); |
c906108c SS |
1333 | |
1334 | if (trace_display) | |
1335 | display_trace (oldsize, trace_data.size); | |
1336 | } | |
1337 | ||
1338 | static void | |
fba45db2 | 1339 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1340 | { |
1341 | int i, count; | |
1342 | CORE_ADDR low, high; | |
1343 | char *space_index; | |
1344 | ||
1345 | if (!arg) | |
1346 | { | |
1347 | low = 0; | |
1348 | high = trace_data.size; | |
1349 | } | |
1350 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1351 | { | |
1352 | low = parse_and_eval_address (arg); | |
1353 | high = low + 5; | |
1354 | } | |
1355 | else | |
1356 | { | |
1357 | /* Two arguments. */ | |
1358 | *space_index = '\0'; | |
1359 | low = parse_and_eval_address (arg); | |
1360 | high = parse_and_eval_address (space_index + 1); | |
1361 | if (high < low) | |
1362 | high = low; | |
1363 | } | |
1364 | ||
d4f3574e | 1365 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1366 | |
1367 | display_trace (low, high); | |
1368 | ||
1369 | printf_filtered ("End of trace dump.\n"); | |
1370 | gdb_flush (gdb_stdout); | |
1371 | } | |
1372 | ||
1373 | static void | |
fba45db2 | 1374 | display_trace (int low, int high) |
c906108c SS |
1375 | { |
1376 | int i, count, trace_show_source, first, suppress; | |
1377 | CORE_ADDR next_address; | |
1378 | ||
1379 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1380 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1381 | { |
1382 | trace_show_source = 0; | |
1383 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1384 | printf_filtered ("Trace will not display any source.\n"); | |
1385 | } | |
1386 | ||
1387 | first = 1; | |
1388 | suppress = 0; | |
1389 | for (i = low; i < high; ++i) | |
1390 | { | |
1391 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1392 | count = trace_data.counts[i]; |
c906108c SS |
1393 | while (count-- > 0) |
1394 | { | |
1395 | QUIT; | |
1396 | if (trace_show_source) | |
1397 | { | |
1398 | struct symtab_and_line sal, sal_prev; | |
1399 | ||
1400 | sal_prev = find_pc_line (next_address - 4, 0); | |
1401 | sal = find_pc_line (next_address, 0); | |
1402 | ||
1403 | if (sal.symtab) | |
1404 | { | |
1405 | if (first || sal.line != sal_prev.line) | |
1406 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1407 | suppress = 0; | |
1408 | } | |
1409 | else | |
1410 | { | |
1411 | if (!suppress) | |
1412 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1413 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1414 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1415 | suppress = 1; |
1416 | } | |
1417 | } | |
1418 | first = 0; | |
1419 | print_address (next_address, gdb_stdout); | |
1420 | printf_filtered (":"); | |
1421 | printf_filtered ("\t"); | |
1422 | wrap_here (" "); | |
1423 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1424 | printf_filtered ("\n"); | |
1425 | gdb_flush (gdb_stdout); | |
1426 | } | |
1427 | } | |
1428 | } | |
1429 | ||
ac9a91a7 | 1430 | |
0f71a2f6 | 1431 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1432 | |
0f71a2f6 | 1433 | static struct gdbarch * |
fba45db2 | 1434 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1435 | { |
c5aa993b JM |
1436 | static LONGEST d10v_call_dummy_words[] = |
1437 | {0}; | |
0f71a2f6 | 1438 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1439 | int d10v_num_regs; |
1440 | struct gdbarch_tdep *tdep; | |
1441 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1442 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1443 | |
4ce44c66 JM |
1444 | /* Find a candidate among the list of pre-declared architectures. */ |
1445 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1446 | if (arches != NULL) |
1447 | return arches->gdbarch; | |
4ce44c66 JM |
1448 | |
1449 | /* None found, create a new architecture from the information | |
1450 | provided. */ | |
1451 | tdep = XMALLOC (struct gdbarch_tdep); | |
1452 | gdbarch = gdbarch_alloc (&info, tdep); | |
1453 | ||
1454 | switch (info.bfd_arch_info->mach) | |
1455 | { | |
1456 | case bfd_mach_d10v_ts2: | |
1457 | d10v_num_regs = 37; | |
1458 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1459 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1460 | tdep->a0_regnum = TS2_A0_REGNUM; |
1461 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1462 | tdep->dmap_register = d10v_ts2_dmap_register; |
1463 | tdep->imap_register = d10v_ts2_imap_register; | |
1464 | break; | |
1465 | default: | |
1466 | case bfd_mach_d10v_ts3: | |
1467 | d10v_num_regs = 42; | |
1468 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1469 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1470 | tdep->a0_regnum = TS3_A0_REGNUM; |
1471 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1472 | tdep->dmap_register = d10v_ts3_dmap_register; |
1473 | tdep->imap_register = d10v_ts3_imap_register; | |
1474 | break; | |
1475 | } | |
0f71a2f6 JM |
1476 | |
1477 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1478 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1479 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1480 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1481 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1482 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1483 | ||
1484 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1485 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1486 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1487 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1488 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1489 | set_gdbarch_register_size (gdbarch, 2); | |
1490 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1491 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1492 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1493 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
0e7c5946 | 1494 | set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size); |
0f71a2f6 JM |
1495 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1496 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1497 | ||
75af7f68 JB |
1498 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1499 | set_gdbarch_addr_bit (gdbarch, 32); | |
1500 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1501 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1502 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1503 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1504 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1505 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1506 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1507 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1508 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1509 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1510 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1511 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1512 | switch (info.byte_order) |
1513 | { | |
d7449b42 | 1514 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1515 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1516 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1517 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1518 | break; | |
778eb05e | 1519 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1520 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1521 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1522 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1523 | break; | |
1524 | default: | |
8e65ff28 AC |
1525 | internal_error (__FILE__, __LINE__, |
1526 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1527 | } |
0f71a2f6 JM |
1528 | |
1529 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1530 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1531 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1532 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1533 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1534 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1535 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1536 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1537 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1538 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1539 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1540 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1541 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1542 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1543 | ||
0f71a2f6 JM |
1544 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
1545 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1546 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1547 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1548 | ||
0f71a2f6 JM |
1549 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
1550 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1551 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1552 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1553 | ||
1554 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1555 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1556 | ||
1557 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1558 | ||
1559 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1560 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1561 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1562 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1563 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1564 | ||
1565 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1566 | ||
1567 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1568 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1569 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1570 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1571 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
c347ee3e MS |
1572 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
1573 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
0f71a2f6 JM |
1574 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1575 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1576 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1577 | |
7c7651b2 | 1578 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1579 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1580 | |
0f71a2f6 JM |
1581 | return gdbarch; |
1582 | } | |
1583 | ||
1584 | ||
507f3c78 KB |
1585 | extern void (*target_resume_hook) (void); |
1586 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1587 | |
1588 | void | |
fba45db2 | 1589 | _initialize_d10v_tdep (void) |
c906108c | 1590 | { |
0f71a2f6 JM |
1591 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1592 | ||
c906108c SS |
1593 | tm_print_insn = print_insn_d10v; |
1594 | ||
1595 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1596 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1597 | ||
1598 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1599 | ||
cff3e48b | 1600 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1601 | "Enable tracing of instruction execution."); |
1602 | ||
cff3e48b | 1603 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1604 | "Disable tracing of instruction execution."); |
1605 | ||
cff3e48b | 1606 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1607 | "Disassemble the trace buffer.\n\ |
1608 | Two optional arguments specify a range of trace buffer entries\n\ | |
1609 | as reported by info trace (NOT addresses!)."); | |
1610 | ||
cff3e48b | 1611 | add_info ("itrace", trace_info, |
c906108c SS |
1612 | "Display info about the trace data buffer."); |
1613 | ||
cff3e48b | 1614 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1615 | var_integer, (char *) &trace_display, |
1616 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1617 | &showlist); |
cff3e48b | 1618 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1619 | var_integer, (char *) &default_trace_show_source, |
1620 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1621 | &showlist); |
1622 | ||
c5aa993b | 1623 | } |