Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
7f6104a9 | 27 | #include "frame-unwind.h" |
270cb5d6 | 28 | #include "frame-base.h" |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdb_string.h" | |
34 | #include "value.h" | |
35 | #include "inferior.h" | |
c5aa993b | 36 | #include "dis-asm.h" |
c906108c SS |
37 | #include "symfile.h" |
38 | #include "objfiles.h" | |
104c1213 | 39 | #include "language.h" |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
e8933a55 | 42 | #include "remote.h" |
f0d4cc9e | 43 | #include "floatformat.h" |
b91b96f4 | 44 | #include "gdb/sim-d10v.h" |
8238d0bf | 45 | #include "sim-regno.h" |
92bf2b80 | 46 | #include "disasm.h" |
4ce44c66 | 47 | |
fa1fd571 AC |
48 | #include "gdb_assert.h" |
49 | ||
4ce44c66 JM |
50 | struct gdbarch_tdep |
51 | { | |
52 | int a0_regnum; | |
53 | int nr_dmap_regs; | |
f6684c31 AC |
54 | unsigned long (*dmap_register) (void *regcache, int nr); |
55 | unsigned long (*imap_register) (void *regcache, int nr); | |
4ce44c66 JM |
56 | }; |
57 | ||
58 | /* These are the addresses the D10V-EVA board maps data and | |
59 | instruction memory to. */ | |
cce74817 | 60 | |
78eac43e MS |
61 | enum memspace { |
62 | DMEM_START = 0x2000000, | |
63 | IMEM_START = 0x1000000, | |
64 | STACK_START = 0x200bffe | |
65 | }; | |
cce74817 | 66 | |
4ce44c66 JM |
67 | /* d10v register names. */ |
68 | ||
69 | enum | |
70 | { | |
71 | R0_REGNUM = 0, | |
78eac43e | 72 | R3_REGNUM = 3, |
6c2b5168 | 73 | D10V_FP_REGNUM = 11, |
4ce44c66 | 74 | LR_REGNUM = 13, |
f75493ed | 75 | D10V_SP_REGNUM = 15, |
4ce44c66 | 76 | PSW_REGNUM = 16, |
27d94c49 | 77 | D10V_PC_REGNUM = 18, |
4ce44c66 | 78 | NR_IMAP_REGS = 2, |
78eac43e MS |
79 | NR_A_REGS = 2, |
80 | TS2_NUM_REGS = 37, | |
81 | TS3_NUM_REGS = 42, | |
82 | /* d10v calling convention. */ | |
83 | ARG1_REGNUM = R0_REGNUM, | |
84 | ARGN_REGNUM = R3_REGNUM, | |
85 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 86 | }; |
78eac43e | 87 | |
f75493ed AC |
88 | int |
89 | nr_dmap_regs (struct gdbarch *gdbarch) | |
90 | { | |
91 | return gdbarch_tdep (gdbarch)->nr_dmap_regs; | |
92 | } | |
93 | ||
94 | int | |
95 | a0_regnum (struct gdbarch *gdbarch) | |
96 | { | |
97 | return gdbarch_tdep (gdbarch)->a0_regnum; | |
98 | } | |
4ce44c66 | 99 | |
392a587b JM |
100 | /* Local functions */ |
101 | ||
a14ed312 | 102 | extern void _initialize_d10v_tdep (void); |
392a587b | 103 | |
095a4c96 EZ |
104 | static CORE_ADDR d10v_read_sp (void); |
105 | ||
a14ed312 | 106 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 107 | |
a14ed312 | 108 | static void d10v_eva_get_trace_data (void); |
c906108c | 109 | |
23964bcd | 110 | static CORE_ADDR |
6ae2f580 | 111 | d10v_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
489137c0 | 112 | { |
6ae2f580 AC |
113 | /* Align to the size of an instruction (so that they can safely be |
114 | pushed onto the stack. */ | |
115 | return sp & ~3; | |
489137c0 | 116 | } |
c906108c SS |
117 | |
118 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
119 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
120 | and TYPE is the type (which is known to be struct, union or array). | |
121 | ||
122 | The d10v returns anything less than 8 bytes in size in | |
123 | registers. */ | |
124 | ||
f5e1cf12 | 125 | static int |
fba45db2 | 126 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 127 | { |
02da6206 JSC |
128 | long alignment; |
129 | int i; | |
130 | /* The d10v only passes a struct in a register when that structure | |
131 | has an alignment that matches the size of a register. */ | |
132 | /* If the structure doesn't fit in 4 registers, put it on the | |
133 | stack. */ | |
134 | if (TYPE_LENGTH (type) > 8) | |
135 | return 1; | |
136 | /* If the struct contains only one field, don't put it on the stack | |
137 | - gcc can fit it in one or more registers. */ | |
138 | if (TYPE_NFIELDS (type) == 1) | |
139 | return 0; | |
140 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
141 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
142 | { | |
143 | /* If the alignment changes, just assume it goes on the | |
144 | stack. */ | |
145 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
146 | return 1; | |
147 | } | |
148 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
149 | don't put it on the stack. */ | |
150 | if (alignment == 2 || alignment == 4) | |
151 | return 0; | |
152 | return 1; | |
c906108c SS |
153 | } |
154 | ||
155 | ||
f4f9705a | 156 | static const unsigned char * |
fba45db2 | 157 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 158 | { |
c5aa993b JM |
159 | static unsigned char breakpoint[] = |
160 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
161 | *lenptr = sizeof (breakpoint); |
162 | return breakpoint; | |
163 | } | |
164 | ||
4ce44c66 JM |
165 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
166 | when the reg_nr isn't valid. */ | |
167 | ||
168 | enum ts2_regnums | |
169 | { | |
170 | TS2_IMAP0_REGNUM = 32, | |
171 | TS2_DMAP_REGNUM = 34, | |
172 | TS2_NR_DMAP_REGS = 1, | |
173 | TS2_A0_REGNUM = 35 | |
174 | }; | |
175 | ||
fa88f677 | 176 | static const char * |
4ce44c66 | 177 | d10v_ts2_register_name (int reg_nr) |
392a587b | 178 | { |
c5aa993b JM |
179 | static char *register_names[] = |
180 | { | |
181 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
182 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
183 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
184 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
185 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
186 | }; |
187 | if (reg_nr < 0) | |
188 | return NULL; | |
189 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
190 | return NULL; | |
c5aa993b | 191 | return register_names[reg_nr]; |
392a587b JM |
192 | } |
193 | ||
4ce44c66 JM |
194 | enum ts3_regnums |
195 | { | |
196 | TS3_IMAP0_REGNUM = 36, | |
197 | TS3_DMAP0_REGNUM = 38, | |
198 | TS3_NR_DMAP_REGS = 4, | |
199 | TS3_A0_REGNUM = 32 | |
200 | }; | |
201 | ||
fa88f677 | 202 | static const char * |
4ce44c66 JM |
203 | d10v_ts3_register_name (int reg_nr) |
204 | { | |
205 | static char *register_names[] = | |
206 | { | |
207 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
208 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
209 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
210 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
211 | "a0", "a1", | |
212 | "spi", "spu", | |
213 | "imap0", "imap1", | |
214 | "dmap0", "dmap1", "dmap2", "dmap3" | |
215 | }; | |
216 | if (reg_nr < 0) | |
217 | return NULL; | |
218 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
219 | return NULL; | |
220 | return register_names[reg_nr]; | |
221 | } | |
222 | ||
bf93dfed JB |
223 | /* Access the DMAP/IMAP registers in a target independent way. |
224 | ||
225 | Divide the D10V's 64k data space into four 16k segments: | |
226 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
227 | 0xc000 -- 0xffff. | |
228 | ||
229 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
230 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
231 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
232 | unified memory or instruction memory, under the control of the | |
233 | single DMAP register. | |
234 | ||
235 | On the TS3, there are four DMAP registers, each of which controls | |
236 | one of the segments. */ | |
4ce44c66 JM |
237 | |
238 | static unsigned long | |
f6684c31 | 239 | d10v_ts2_dmap_register (void *regcache, int reg_nr) |
4ce44c66 JM |
240 | { |
241 | switch (reg_nr) | |
242 | { | |
243 | case 0: | |
244 | case 1: | |
245 | return 0x2000; | |
246 | case 2: | |
f6684c31 AC |
247 | { |
248 | ULONGEST reg; | |
249 | regcache_cooked_read_unsigned (regcache, TS2_DMAP_REGNUM, ®); | |
250 | return reg; | |
251 | } | |
4ce44c66 JM |
252 | default: |
253 | return 0; | |
254 | } | |
255 | } | |
256 | ||
257 | static unsigned long | |
f6684c31 | 258 | d10v_ts3_dmap_register (void *regcache, int reg_nr) |
4ce44c66 | 259 | { |
f6684c31 AC |
260 | ULONGEST reg; |
261 | regcache_cooked_read_unsigned (regcache, TS3_DMAP0_REGNUM + reg_nr, ®); | |
262 | return reg; | |
4ce44c66 JM |
263 | } |
264 | ||
265 | static unsigned long | |
f6684c31 | 266 | d10v_ts2_imap_register (void *regcache, int reg_nr) |
4ce44c66 | 267 | { |
f6684c31 AC |
268 | ULONGEST reg; |
269 | regcache_cooked_read_unsigned (regcache, TS2_IMAP0_REGNUM + reg_nr, ®); | |
270 | return reg; | |
4ce44c66 JM |
271 | } |
272 | ||
273 | static unsigned long | |
f6684c31 | 274 | d10v_ts3_imap_register (void *regcache, int reg_nr) |
4ce44c66 | 275 | { |
f6684c31 AC |
276 | ULONGEST reg; |
277 | regcache_cooked_read_unsigned (regcache, TS3_IMAP0_REGNUM + reg_nr, ®); | |
278 | return reg; | |
4ce44c66 JM |
279 | } |
280 | ||
281 | /* MAP GDB's internal register numbering (determined by the layout fo | |
282 | the REGISTER_BYTE array) onto the simulator's register | |
283 | numbering. */ | |
284 | ||
285 | static int | |
286 | d10v_ts2_register_sim_regno (int nr) | |
287 | { | |
e8933a55 AC |
288 | /* Only makes sense to supply raw registers. */ |
289 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
290 | if (nr >= TS2_IMAP0_REGNUM |
291 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
292 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
293 | if (nr == TS2_DMAP_REGNUM) | |
294 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
295 | if (nr >= TS2_A0_REGNUM | |
296 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
297 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
298 | return nr; | |
299 | } | |
300 | ||
301 | static int | |
302 | d10v_ts3_register_sim_regno (int nr) | |
303 | { | |
e8933a55 AC |
304 | /* Only makes sense to supply raw registers. */ |
305 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
306 | if (nr >= TS3_IMAP0_REGNUM |
307 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
308 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
309 | if (nr >= TS3_DMAP0_REGNUM | |
310 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
311 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
312 | if (nr >= TS3_A0_REGNUM | |
313 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
314 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
315 | return nr; | |
316 | } | |
317 | ||
392a587b JM |
318 | /* Return the GDB type object for the "standard" data type |
319 | of data in register N. */ | |
320 | ||
f5e1cf12 | 321 | static struct type * |
35cac7cf | 322 | d10v_register_type (struct gdbarch *gdbarch, int reg_nr) |
392a587b | 323 | { |
27d94c49 | 324 | if (reg_nr == D10V_PC_REGNUM) |
75af7f68 | 325 | return builtin_type_void_func_ptr; |
f75493ed | 326 | if (reg_nr == D10V_SP_REGNUM || reg_nr == D10V_FP_REGNUM) |
095a4c96 | 327 | return builtin_type_void_data_ptr; |
f75493ed AC |
328 | else if (reg_nr >= a0_regnum (gdbarch) |
329 | && reg_nr < (a0_regnum (gdbarch) + NR_A_REGS)) | |
4ce44c66 | 330 | return builtin_type_int64; |
392a587b | 331 | else |
4ce44c66 | 332 | return builtin_type_int16; |
392a587b JM |
333 | } |
334 | ||
f5e1cf12 | 335 | static int |
fba45db2 | 336 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
337 | { |
338 | return (((x) & 0x3000000) == DMEM_START); | |
339 | } | |
340 | ||
f5e1cf12 | 341 | static int |
fba45db2 | 342 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
343 | { |
344 | return (((x) & 0x3000000) == IMEM_START); | |
345 | } | |
346 | ||
169a7369 MS |
347 | static CORE_ADDR |
348 | d10v_make_daddr (CORE_ADDR x) | |
349 | { | |
350 | return ((x) | DMEM_START); | |
351 | } | |
352 | ||
353 | static CORE_ADDR | |
354 | d10v_make_iaddr (CORE_ADDR x) | |
355 | { | |
356 | if (d10v_iaddr_p (x)) | |
357 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
358 | else | |
359 | return (((x) << 2) | IMEM_START); | |
360 | } | |
392a587b | 361 | |
f5e1cf12 | 362 | static CORE_ADDR |
fba45db2 | 363 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
364 | { |
365 | return (((x) >> 2) & 0xffff); | |
366 | } | |
367 | ||
f5e1cf12 | 368 | static CORE_ADDR |
fba45db2 | 369 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
370 | { |
371 | return ((x) & 0xffff); | |
372 | } | |
373 | ||
75af7f68 JB |
374 | static void |
375 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
376 | { | |
377 | /* Is it a code address? */ | |
378 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
379 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
380 | { | |
75af7f68 JB |
381 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
382 | d10v_convert_iaddr_to_raw (addr)); | |
383 | } | |
384 | else | |
385 | { | |
386 | /* Strip off any upper segment bits. */ | |
387 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
388 | d10v_convert_daddr_to_raw (addr)); | |
389 | } | |
390 | } | |
391 | ||
392 | static CORE_ADDR | |
66140c26 | 393 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 | 394 | { |
f75493ed | 395 | CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH (type)); |
75af7f68 JB |
396 | /* Is it a code address? */ |
397 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
398 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
399 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
400 | return d10v_make_iaddr (addr); |
401 | else | |
402 | return d10v_make_daddr (addr); | |
403 | } | |
404 | ||
095a4c96 EZ |
405 | /* Don't do anything if we have an integer, this way users can type 'x |
406 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
407 | to the correct space are taken care of in the pointer_to_address | |
408 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
409 | static CORE_ADDR |
410 | d10v_integer_to_address (struct type *type, void *buf) | |
411 | { | |
412 | LONGEST val; | |
413 | val = unpack_long (type, buf); | |
095a4c96 | 414 | return val; |
fc0c74b1 | 415 | } |
75af7f68 | 416 | |
392a587b JM |
417 | /* Write into appropriate registers a function return value |
418 | of type TYPE, given in virtual format. | |
419 | ||
420 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
421 | ||
f5e1cf12 | 422 | static void |
fa1fd571 AC |
423 | d10v_store_return_value (struct type *type, struct regcache *regcache, |
424 | const void *valbuf) | |
392a587b | 425 | { |
fa1fd571 AC |
426 | /* Only char return values need to be shifted right within the first |
427 | regnum. */ | |
3d79a47c MS |
428 | if (TYPE_LENGTH (type) == 1 |
429 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
430 | { | |
fa1fd571 AC |
431 | bfd_byte tmp[2]; |
432 | tmp[1] = *(bfd_byte *)valbuf; | |
433 | regcache_cooked_write (regcache, RET1_REGNUM, tmp); | |
3d79a47c MS |
434 | } |
435 | else | |
fa1fd571 AC |
436 | { |
437 | int reg; | |
438 | /* A structure is never more than 8 bytes long. See | |
439 | use_struct_convention(). */ | |
440 | gdb_assert (TYPE_LENGTH (type) <= 8); | |
441 | /* Write out most registers, stop loop before trying to write | |
442 | out any dangling byte at the end of the buffer. */ | |
443 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) | |
444 | { | |
445 | regcache_cooked_write (regcache, RET1_REGNUM + reg, | |
446 | (bfd_byte *) valbuf + reg * 2); | |
447 | } | |
448 | /* Write out any dangling byte at the end of the buffer. */ | |
449 | if ((reg * 2) + 1 == TYPE_LENGTH (type)) | |
450 | regcache_cooked_write_part (regcache, reg, 0, 1, | |
451 | (bfd_byte *) valbuf + reg * 2); | |
452 | } | |
392a587b JM |
453 | } |
454 | ||
455 | /* Extract from an array REGBUF containing the (raw) register state | |
456 | the address in which a function should return its structure value, | |
457 | as a CORE_ADDR (or an expression that can be used as one). */ | |
458 | ||
f5e1cf12 | 459 | static CORE_ADDR |
fa1fd571 | 460 | d10v_extract_struct_value_address (struct regcache *regcache) |
392a587b | 461 | { |
fa1fd571 AC |
462 | ULONGEST addr; |
463 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
464 | return (addr | DMEM_START); | |
392a587b JM |
465 | } |
466 | ||
c5aa993b | 467 | static int |
fba45db2 | 468 | check_prologue (unsigned short op) |
c906108c SS |
469 | { |
470 | /* st rn, @-sp */ | |
471 | if ((op & 0x7E1F) == 0x6C1F) | |
472 | return 1; | |
473 | ||
474 | /* st2w rn, @-sp */ | |
475 | if ((op & 0x7E3F) == 0x6E1F) | |
476 | return 1; | |
477 | ||
478 | /* subi sp, n */ | |
479 | if ((op & 0x7FE1) == 0x01E1) | |
480 | return 1; | |
481 | ||
482 | /* mv r11, sp */ | |
483 | if (op == 0x417E) | |
484 | return 1; | |
485 | ||
486 | /* nop */ | |
487 | if (op == 0x5E00) | |
488 | return 1; | |
489 | ||
490 | /* st rn, @sp */ | |
491 | if ((op & 0x7E1F) == 0x681E) | |
492 | return 1; | |
493 | ||
494 | /* st2w rn, @sp */ | |
c5aa993b JM |
495 | if ((op & 0x7E3F) == 0x3A1E) |
496 | return 1; | |
c906108c SS |
497 | |
498 | return 0; | |
499 | } | |
500 | ||
f5e1cf12 | 501 | static CORE_ADDR |
fba45db2 | 502 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
503 | { |
504 | unsigned long op; | |
505 | unsigned short op1, op2; | |
506 | CORE_ADDR func_addr, func_end; | |
507 | struct symtab_and_line sal; | |
508 | ||
509 | /* If we have line debugging information, then the end of the */ | |
510 | /* prologue should the first assembly instruction of the first source line */ | |
511 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
512 | { | |
513 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 514 | if (sal.end && sal.end < func_end) |
c906108c SS |
515 | return sal.end; |
516 | } | |
c5aa993b JM |
517 | |
518 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
519 | return pc; /* Can't access it -- assume no prologue. */ |
520 | ||
521 | while (1) | |
522 | { | |
c5aa993b | 523 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
524 | if ((op & 0xC0000000) == 0xC0000000) |
525 | { | |
526 | /* long instruction */ | |
c5aa993b JM |
527 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
528 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
529 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
530 | break; |
531 | } | |
532 | else | |
533 | { | |
534 | /* short instructions */ | |
535 | if ((op & 0xC0000000) == 0x80000000) | |
536 | { | |
537 | op2 = (op & 0x3FFF8000) >> 15; | |
538 | op1 = op & 0x7FFF; | |
c5aa993b JM |
539 | } |
540 | else | |
c906108c SS |
541 | { |
542 | op1 = (op & 0x3FFF8000) >> 15; | |
543 | op2 = op & 0x7FFF; | |
544 | } | |
c5aa993b | 545 | if (check_prologue (op1)) |
c906108c | 546 | { |
c5aa993b | 547 | if (!check_prologue (op2)) |
c906108c SS |
548 | { |
549 | /* if the previous opcode was really part of the prologue */ | |
550 | /* and not just a NOP, then we want to break after both instructions */ | |
551 | if (op1 != 0x5E00) | |
552 | pc += 4; | |
553 | break; | |
554 | } | |
555 | } | |
556 | else | |
557 | break; | |
558 | } | |
559 | pc += 4; | |
560 | } | |
561 | return pc; | |
562 | } | |
563 | ||
7f6104a9 | 564 | struct d10v_unwind_cache |
c906108c | 565 | { |
7f6104a9 | 566 | CORE_ADDR return_pc; |
270cb5d6 AC |
567 | /* The previous frame's inner most stack address. Used as this |
568 | frame ID's stack_addr. */ | |
569 | CORE_ADDR prev_sp; | |
570 | /* The frame's base, optionally used by the high-level debug info. */ | |
ceea5145 | 571 | CORE_ADDR base; |
7f6104a9 AC |
572 | int size; |
573 | CORE_ADDR *saved_regs; | |
0d843116 AC |
574 | /* How far the SP and r11 (FP) have been offset from the start of |
575 | the stack frame (as defined by the previous frame's stack | |
576 | pointer). */ | |
577 | LONGEST sp_offset; | |
578 | LONGEST r11_offset; | |
7f6104a9 AC |
579 | int uses_frame; |
580 | void **regs; | |
581 | }; | |
c906108c | 582 | |
c5aa993b | 583 | static int |
7f6104a9 AC |
584 | prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, |
585 | CORE_ADDR addr) | |
c906108c SS |
586 | { |
587 | int n; | |
588 | ||
589 | /* st rn, @-sp */ | |
590 | if ((op & 0x7E1F) == 0x6C1F) | |
591 | { | |
592 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
593 | info->sp_offset -= 2; |
594 | info->saved_regs[n] = info->sp_offset; | |
c906108c SS |
595 | return 1; |
596 | } | |
597 | ||
598 | /* st2w rn, @-sp */ | |
599 | else if ((op & 0x7E3F) == 0x6E1F) | |
600 | { | |
601 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
602 | info->sp_offset -= 4; |
603 | info->saved_regs[n] = info->sp_offset; | |
604 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
605 | return 1; |
606 | } | |
607 | ||
608 | /* subi sp, n */ | |
609 | if ((op & 0x7FE1) == 0x01E1) | |
610 | { | |
611 | n = (op & 0x1E) >> 1; | |
612 | if (n == 0) | |
613 | n = 16; | |
0d843116 | 614 | info->sp_offset -= n; |
c906108c SS |
615 | return 1; |
616 | } | |
617 | ||
618 | /* mv r11, sp */ | |
619 | if (op == 0x417E) | |
620 | { | |
7f6104a9 | 621 | info->uses_frame = 1; |
0d843116 AC |
622 | info->r11_offset = info->sp_offset; |
623 | return 1; | |
624 | } | |
625 | ||
626 | /* st rn, @r11 */ | |
627 | if ((op & 0x7E1F) == 0x6816) | |
628 | { | |
629 | n = (op & 0x1E0) >> 5; | |
630 | info->saved_regs[n] = info->r11_offset; | |
c906108c SS |
631 | return 1; |
632 | } | |
633 | ||
634 | /* nop */ | |
635 | if (op == 0x5E00) | |
636 | return 1; | |
637 | ||
638 | /* st rn, @sp */ | |
639 | if ((op & 0x7E1F) == 0x681E) | |
640 | { | |
641 | n = (op & 0x1E0) >> 5; | |
0d843116 | 642 | info->saved_regs[n] = info->sp_offset; |
c906108c SS |
643 | return 1; |
644 | } | |
645 | ||
646 | /* st2w rn, @sp */ | |
647 | if ((op & 0x7E3F) == 0x3A1E) | |
648 | { | |
649 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
650 | info->saved_regs[n] = info->sp_offset; |
651 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
652 | return 1; |
653 | } | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
cce74817 JM |
658 | /* Put here the code to store, into fi->saved_regs, the addresses of |
659 | the saved registers of frame described by FRAME_INFO. This | |
660 | includes special registers such as pc and fp saved in special ways | |
661 | in the stack frame. sp is even more special: the address we return | |
662 | for it IS the sp for the next frame. */ | |
663 | ||
7f6104a9 | 664 | struct d10v_unwind_cache * |
6dc42492 AC |
665 | d10v_frame_unwind_cache (struct frame_info *next_frame, |
666 | void **this_prologue_cache) | |
c906108c | 667 | { |
ceea5145 AC |
668 | CORE_ADDR pc; |
669 | ULONGEST prev_sp; | |
670 | ULONGEST this_base; | |
c906108c SS |
671 | unsigned long op; |
672 | unsigned short op1, op2; | |
673 | int i; | |
7f6104a9 AC |
674 | struct d10v_unwind_cache *info; |
675 | ||
6dc42492 AC |
676 | if ((*this_prologue_cache)) |
677 | return (*this_prologue_cache); | |
7f6104a9 AC |
678 | |
679 | info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); | |
6dc42492 | 680 | (*this_prologue_cache) = info; |
f75493ed | 681 | info->saved_regs = FRAME_OBSTACK_CALLOC (NUM_REGS, CORE_ADDR); |
7f6104a9 | 682 | |
7f6104a9 AC |
683 | info->size = 0; |
684 | info->return_pc = 0; | |
0d843116 | 685 | info->sp_offset = 0; |
c906108c | 686 | |
7f6104a9 | 687 | info->uses_frame = 0; |
be41e9f4 | 688 | for (pc = frame_func_unwind (next_frame); |
81f8a206 | 689 | pc > 0 && pc < frame_pc_unwind (next_frame); |
270cb5d6 | 690 | pc += 4) |
c906108c | 691 | { |
c5aa993b | 692 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
693 | if ((op & 0xC0000000) == 0xC0000000) |
694 | { | |
695 | /* long instruction */ | |
696 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
697 | { | |
698 | /* add3 sp,sp,n */ | |
699 | short n = op & 0xFFFF; | |
0d843116 | 700 | info->sp_offset += n; |
c906108c SS |
701 | } |
702 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
703 | { | |
704 | /* st rn, @(offset,sp) */ | |
705 | short offset = op & 0xFFFF; | |
706 | short n = (op >> 20) & 0xF; | |
0d843116 | 707 | info->saved_regs[n] = info->sp_offset + offset; |
c906108c SS |
708 | } |
709 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
710 | { | |
711 | /* st2w rn, @(offset,sp) */ | |
712 | short offset = op & 0xFFFF; | |
713 | short n = (op >> 20) & 0xF; | |
0d843116 AC |
714 | info->saved_regs[n] = info->sp_offset + offset; |
715 | info->saved_regs[n + 1] = info->sp_offset + offset + 2; | |
c906108c SS |
716 | } |
717 | else | |
718 | break; | |
719 | } | |
720 | else | |
721 | { | |
722 | /* short instructions */ | |
723 | if ((op & 0xC0000000) == 0x80000000) | |
724 | { | |
725 | op2 = (op & 0x3FFF8000) >> 15; | |
726 | op1 = op & 0x7FFF; | |
c5aa993b JM |
727 | } |
728 | else | |
c906108c SS |
729 | { |
730 | op1 = (op & 0x3FFF8000) >> 15; | |
731 | op2 = op & 0x7FFF; | |
732 | } | |
7f6104a9 AC |
733 | if (!prologue_find_regs (info, op1, pc) |
734 | || !prologue_find_regs (info, op2, pc)) | |
c906108c SS |
735 | break; |
736 | } | |
c906108c | 737 | } |
c5aa993b | 738 | |
0d843116 | 739 | info->size = -info->sp_offset; |
c906108c | 740 | |
ceea5145 AC |
741 | /* Compute the frame's base, and the previous frame's SP. */ |
742 | if (info->uses_frame) | |
743 | { | |
744 | /* The SP was moved to the FP. This indicates that a new frame | |
745 | was created. Get THIS frame's FP value by unwinding it from | |
746 | the next frame. */ | |
6c2b5168 | 747 | frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); |
ceea5145 AC |
748 | /* The FP points at the last saved register. Adjust the FP back |
749 | to before the first saved register giving the SP. */ | |
750 | prev_sp = this_base + info->size; | |
751 | } | |
f75493ed | 752 | else if (info->saved_regs[D10V_SP_REGNUM]) |
ceea5145 AC |
753 | { |
754 | /* The SP was saved (which is very unusual), the frame base is | |
755 | just the PREV's frame's TOP-OF-STACK. */ | |
f75493ed | 756 | this_base = read_memory_unsigned_integer (info->saved_regs[D10V_SP_REGNUM], |
ceea5145 | 757 | register_size (current_gdbarch, |
f75493ed | 758 | D10V_SP_REGNUM)); |
ceea5145 AC |
759 | prev_sp = this_base; |
760 | } | |
761 | else | |
762 | { | |
763 | /* Assume that the FP is this frame's SP but with that pushed | |
764 | stack space added back. */ | |
f75493ed | 765 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &this_base); |
ceea5145 AC |
766 | prev_sp = this_base + info->size; |
767 | } | |
768 | ||
769 | info->base = d10v_make_daddr (this_base); | |
270cb5d6 | 770 | info->prev_sp = d10v_make_daddr (prev_sp); |
c906108c | 771 | |
ceea5145 AC |
772 | /* Adjust all the saved registers so that they contain addresses and |
773 | not offsets. */ | |
c5aa993b | 774 | for (i = 0; i < NUM_REGS - 1; i++) |
7f6104a9 | 775 | if (info->saved_regs[i]) |
c906108c | 776 | { |
270cb5d6 | 777 | info->saved_regs[i] = (info->prev_sp + info->saved_regs[i]); |
c906108c SS |
778 | } |
779 | ||
7f6104a9 | 780 | if (info->saved_regs[LR_REGNUM]) |
c906108c | 781 | { |
78eac43e | 782 | CORE_ADDR return_pc |
7f6104a9 | 783 | = read_memory_unsigned_integer (info->saved_regs[LR_REGNUM], |
08a617da | 784 | register_size (current_gdbarch, LR_REGNUM)); |
7f6104a9 | 785 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
786 | } |
787 | else | |
788 | { | |
7f6104a9 | 789 | ULONGEST return_pc; |
6dc42492 | 790 | frame_unwind_unsigned_register (next_frame, LR_REGNUM, &return_pc); |
7f6104a9 | 791 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c | 792 | } |
c5aa993b | 793 | |
f75493ed | 794 | /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the |
ceea5145 | 795 | previous frame's SP value is saved. */ |
f75493ed | 796 | info->saved_regs[D10V_SP_REGNUM] = info->prev_sp; |
c906108c | 797 | |
7f6104a9 | 798 | return info; |
c906108c SS |
799 | } |
800 | ||
801 | static void | |
5f601589 AC |
802 | d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
803 | struct frame_info *frame, int regnum, int all) | |
c906108c | 804 | { |
f6684c31 | 805 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5f601589 | 806 | if (regnum >= 0) |
4ce44c66 | 807 | { |
5f601589 AC |
808 | default_print_registers_info (gdbarch, file, frame, regnum, all); |
809 | return; | |
4ce44c66 | 810 | } |
5f601589 AC |
811 | |
812 | { | |
813 | ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; | |
27d94c49 | 814 | frame_read_unsigned_register (frame, D10V_PC_REGNUM, &pc); |
5f601589 AC |
815 | frame_read_unsigned_register (frame, PSW_REGNUM, &psw); |
816 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s); | |
817 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e); | |
818 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c); | |
819 | fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", | |
820 | (long) pc, (long) d10v_make_iaddr (pc), (long) psw, | |
821 | (long) rpt_s, (long) rpt_e, (long) rpt_c); | |
822 | } | |
823 | ||
824 | { | |
825 | int group; | |
826 | for (group = 0; group < 16; group += 8) | |
827 | { | |
828 | int r; | |
829 | fprintf_filtered (file, "R%d-R%-2d", group, group + 7); | |
830 | for (r = group; r < group + 8; r++) | |
831 | { | |
832 | ULONGEST tmp; | |
833 | frame_read_unsigned_register (frame, r, &tmp); | |
834 | fprintf_filtered (file, " %04lx", (long) tmp); | |
835 | } | |
836 | fprintf_filtered (file, "\n"); | |
837 | } | |
838 | } | |
839 | ||
840 | /* Note: The IMAP/DMAP registers don't participate in function | |
841 | calls. Don't bother trying to unwind them. */ | |
842 | ||
6789195b | 843 | { |
5f601589 AC |
844 | int a; |
845 | for (a = 0; a < NR_IMAP_REGS; a++) | |
846 | { | |
847 | if (a > 0) | |
848 | fprintf_filtered (file, " "); | |
f6684c31 AC |
849 | fprintf_filtered (file, "IMAP%d %04lx", a, |
850 | tdep->imap_register (current_regcache, a)); | |
5f601589 | 851 | } |
f75493ed | 852 | if (nr_dmap_regs (gdbarch) == 1) |
5f601589 | 853 | /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ |
f6684c31 AC |
854 | fprintf_filtered (file, " DMAP %04lx\n", |
855 | tdep->dmap_register (current_regcache, 2)); | |
5f601589 AC |
856 | else |
857 | { | |
f75493ed | 858 | for (a = 0; a < nr_dmap_regs (gdbarch); a++) |
5f601589 | 859 | { |
f6684c31 AC |
860 | fprintf_filtered (file, " DMAP%d %04lx", a, |
861 | tdep->dmap_register (current_regcache, a)); | |
5f601589 AC |
862 | } |
863 | fprintf_filtered (file, "\n"); | |
864 | } | |
865 | } | |
866 | ||
867 | { | |
0c92afe8 | 868 | char num[MAX_REGISTER_SIZE]; |
5f601589 AC |
869 | int a; |
870 | fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); | |
f75493ed | 871 | for (a = a0_regnum (gdbarch); a < a0_regnum (gdbarch) + NR_A_REGS; a++) |
6789195b AC |
872 | { |
873 | int i; | |
5f601589 | 874 | fprintf_filtered (file, " "); |
f75493ed AC |
875 | frame_read_register (frame, a, num); |
876 | for (i = 0; i < register_size (current_gdbarch, a); i++) | |
6789195b | 877 | { |
5f601589 | 878 | fprintf_filtered (file, "%02x", (num[i] & 0xff)); |
6789195b AC |
879 | } |
880 | } | |
881 | } | |
5f601589 AC |
882 | fprintf_filtered (file, "\n"); |
883 | } | |
884 | ||
885 | static void | |
886 | show_regs (char *args, int from_tty) | |
887 | { | |
888 | d10v_print_registers_info (current_gdbarch, gdb_stdout, | |
889 | get_current_frame (), -1, 1); | |
c906108c SS |
890 | } |
891 | ||
f5e1cf12 | 892 | static CORE_ADDR |
39f77062 | 893 | d10v_read_pc (ptid_t ptid) |
c906108c | 894 | { |
39f77062 | 895 | ptid_t save_ptid; |
c906108c SS |
896 | CORE_ADDR pc; |
897 | CORE_ADDR retval; | |
898 | ||
39f77062 KB |
899 | save_ptid = inferior_ptid; |
900 | inferior_ptid = ptid; | |
27d94c49 | 901 | pc = (int) read_register (D10V_PC_REGNUM); |
39f77062 | 902 | inferior_ptid = save_ptid; |
7b570125 | 903 | retval = d10v_make_iaddr (pc); |
c906108c SS |
904 | return retval; |
905 | } | |
906 | ||
f5e1cf12 | 907 | static void |
39f77062 | 908 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 909 | { |
39f77062 | 910 | ptid_t save_ptid; |
c906108c | 911 | |
39f77062 KB |
912 | save_ptid = inferior_ptid; |
913 | inferior_ptid = ptid; | |
27d94c49 | 914 | write_register (D10V_PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 915 | inferior_ptid = save_ptid; |
c906108c SS |
916 | } |
917 | ||
f5e1cf12 | 918 | static CORE_ADDR |
fba45db2 | 919 | d10v_read_sp (void) |
c906108c | 920 | { |
f75493ed | 921 | return (d10v_make_daddr (read_register (D10V_SP_REGNUM))); |
c906108c SS |
922 | } |
923 | ||
7a292a7a SS |
924 | /* When arguments must be pushed onto the stack, they go on in reverse |
925 | order. The below implements a FILO (stack) to do this. */ | |
926 | ||
927 | struct stack_item | |
928 | { | |
929 | int len; | |
930 | struct stack_item *prev; | |
931 | void *data; | |
932 | }; | |
933 | ||
a14ed312 KB |
934 | static struct stack_item *push_stack_item (struct stack_item *prev, |
935 | void *contents, int len); | |
7a292a7a | 936 | static struct stack_item * |
fba45db2 | 937 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
938 | { |
939 | struct stack_item *si; | |
940 | si = xmalloc (sizeof (struct stack_item)); | |
941 | si->data = xmalloc (len); | |
942 | si->len = len; | |
943 | si->prev = prev; | |
944 | memcpy (si->data, contents, len); | |
945 | return si; | |
946 | } | |
947 | ||
a14ed312 | 948 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 949 | static struct stack_item * |
fba45db2 | 950 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
951 | { |
952 | struct stack_item *dead = si; | |
953 | si = si->prev; | |
b8c9b27d KB |
954 | xfree (dead->data); |
955 | xfree (dead); | |
7a292a7a SS |
956 | return si; |
957 | } | |
958 | ||
959 | ||
7043d8dc AC |
960 | static CORE_ADDR |
961 | d10v_push_dummy_code (struct gdbarch *gdbarch, | |
962 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
963 | struct value **args, int nargs, | |
964 | struct type *value_type, | |
965 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
966 | { | |
967 | /* Allocate space sufficient for a breakpoint. */ | |
968 | sp = (sp - 4) & ~3; | |
969 | /* Store the address of that breakpoint taking care to first convert | |
970 | it into a code (IADDR) address from a stack (DADDR) address. | |
971 | This of course assumes that the two virtual addresses map onto | |
972 | the same real address. */ | |
973 | (*bp_addr) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp)); | |
974 | /* d10v always starts the call at the callee's entry point. */ | |
975 | (*real_pc) = funaddr; | |
976 | return sp; | |
977 | } | |
978 | ||
f5e1cf12 | 979 | static CORE_ADDR |
5873a88d AC |
980 | d10v_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache, |
981 | CORE_ADDR dummy_addr, int nargs, struct value **args, | |
982 | CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
983 | { |
984 | int i; | |
985 | int regnum = ARG1_REGNUM; | |
7a292a7a | 986 | struct stack_item *si = NULL; |
7bd91a28 MS |
987 | long val; |
988 | ||
5873a88d AC |
989 | /* Set the return address. For the d10v, the return breakpoint is |
990 | always at DUMMY_ADDR. */ | |
991 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, | |
992 | d10v_convert_iaddr_to_raw (dummy_addr)); | |
993 | ||
4183d812 AC |
994 | /* If STRUCT_RETURN is true, then the struct return address (in |
995 | STRUCT_ADDR) will consume the first argument-passing register. | |
996 | Both adjust the register count and store that value. */ | |
7bd91a28 | 997 | if (struct_return) |
4183d812 | 998 | { |
5873a88d | 999 | regcache_cooked_write_unsigned (regcache, regnum, struct_addr); |
4183d812 AC |
1000 | regnum++; |
1001 | } | |
c5aa993b | 1002 | |
c906108c SS |
1003 | /* Fill in registers and arg lists */ |
1004 | for (i = 0; i < nargs; i++) | |
1005 | { | |
ea7c478f | 1006 | struct value *arg = args[i]; |
c906108c SS |
1007 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1008 | char *contents = VALUE_CONTENTS (arg); | |
1009 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
1010 | int aligned_regnum = (regnum + 1) & ~1; |
1011 | ||
8b279e7a | 1012 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1013 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1014 | /* fits in a single register, do not align */ | |
1015 | { | |
1016 | val = extract_unsigned_integer (contents, len); | |
5873a88d | 1017 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
7bd91a28 MS |
1018 | } |
1019 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1020 | /* value fits in remaining registers, store keeping left | |
1021 | aligned */ | |
c906108c | 1022 | { |
7bd91a28 MS |
1023 | int b; |
1024 | regnum = aligned_regnum; | |
1025 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1026 | { |
7bd91a28 | 1027 | val = extract_unsigned_integer (&contents[b], 2); |
5873a88d | 1028 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
c906108c | 1029 | } |
7bd91a28 | 1030 | if (b < len) |
c906108c | 1031 | { |
7bd91a28 | 1032 | val = extract_unsigned_integer (&contents[b], 1); |
5873a88d | 1033 | regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); |
c906108c SS |
1034 | } |
1035 | } | |
7bd91a28 MS |
1036 | else |
1037 | { | |
1038 | /* arg will go onto stack */ | |
1039 | regnum = ARGN_REGNUM + 1; | |
1040 | si = push_stack_item (si, contents, len); | |
1041 | } | |
c906108c | 1042 | } |
7a292a7a SS |
1043 | |
1044 | while (si) | |
1045 | { | |
1046 | sp = (sp - si->len) & ~1; | |
1047 | write_memory (sp, si->data, si->len); | |
1048 | si = pop_stack_item (si); | |
1049 | } | |
c5aa993b | 1050 | |
5873a88d | 1051 | /* Finally, update the SP register. */ |
f75493ed | 1052 | regcache_cooked_write_unsigned (regcache, D10V_SP_REGNUM, |
5873a88d AC |
1053 | d10v_convert_daddr_to_raw (sp)); |
1054 | ||
c906108c SS |
1055 | return sp; |
1056 | } | |
1057 | ||
1058 | ||
1059 | /* Given a return value in `regbuf' with a type `valtype', | |
1060 | extract and copy its value into `valbuf'. */ | |
1061 | ||
f5e1cf12 | 1062 | static void |
fa1fd571 AC |
1063 | d10v_extract_return_value (struct type *type, struct regcache *regcache, |
1064 | void *valbuf) | |
c906108c SS |
1065 | { |
1066 | int len; | |
fa1fd571 | 1067 | if (TYPE_LENGTH (type) == 1) |
c906108c | 1068 | { |
fa1fd571 AC |
1069 | ULONGEST c; |
1070 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); | |
3d79a47c MS |
1071 | store_unsigned_integer (valbuf, 1, c); |
1072 | } | |
3d79a47c MS |
1073 | else |
1074 | { | |
1075 | /* For return values of odd size, the first byte is in the | |
1076 | least significant part of the first register. The | |
fa1fd571 AC |
1077 | remaining bytes in remaining registers. Interestingly, when |
1078 | such values are passed in, the last byte is in the most | |
1079 | significant byte of that same register - wierd. */ | |
1080 | int reg = RET1_REGNUM; | |
1081 | int off = 0; | |
1082 | if (TYPE_LENGTH (type) & 1) | |
1083 | { | |
1084 | regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, | |
1085 | (bfd_byte *)valbuf + off); | |
1086 | off++; | |
1087 | reg++; | |
1088 | } | |
1089 | /* Transfer the remaining registers. */ | |
1090 | for (; off < TYPE_LENGTH (type); reg++, off += 2) | |
1091 | { | |
1092 | regcache_cooked_read (regcache, RET1_REGNUM + reg, | |
1093 | (bfd_byte *) valbuf + off); | |
1094 | } | |
c906108c SS |
1095 | } |
1096 | } | |
1097 | ||
c2c6d25f JM |
1098 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1099 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1100 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1101 | (segmentation fault). Since the simulator knows all about how the | |
1102 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1103 | |
4ce44c66 | 1104 | static void |
f6684c31 AC |
1105 | remote_d10v_translate_xfer_address (struct gdbarch *gdbarch, |
1106 | struct regcache *regcache, | |
1107 | CORE_ADDR memaddr, int nr_bytes, | |
c2c6d25f JM |
1108 | CORE_ADDR *targ_addr, int *targ_len) |
1109 | { | |
f6684c31 | 1110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4ce44c66 JM |
1111 | long out_addr; |
1112 | long out_len; | |
f6684c31 AC |
1113 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, &out_addr, regcache, |
1114 | tdep->dmap_register, tdep->imap_register); | |
4ce44c66 JM |
1115 | *targ_addr = out_addr; |
1116 | *targ_len = out_len; | |
c2c6d25f JM |
1117 | } |
1118 | ||
4ce44c66 | 1119 | |
c906108c SS |
1120 | /* The following code implements access to, and display of, the D10V's |
1121 | instruction trace buffer. The buffer consists of 64K or more | |
1122 | 4-byte words of data, of which each words includes an 8-bit count, | |
1123 | an 8-bit segment number, and a 16-bit instruction address. | |
1124 | ||
1125 | In theory, the trace buffer is continuously capturing instruction | |
1126 | data that the CPU presents on its "debug bus", but in practice, the | |
1127 | ROMified GDB stub only enables tracing when it continues or steps | |
1128 | the program, and stops tracing when the program stops; so it | |
1129 | actually works for GDB to read the buffer counter out of memory and | |
1130 | then read each trace word. The counter records where the tracing | |
1131 | stops, but there is no record of where it started, so we remember | |
1132 | the PC when we resumed and then search backwards in the trace | |
1133 | buffer for a word that includes that address. This is not perfect, | |
1134 | because you will miss trace data if the resumption PC is the target | |
1135 | of a branch. (The value of the buffer counter is semi-random, any | |
1136 | trace data from a previous program stop is gone.) */ | |
1137 | ||
1138 | /* The address of the last word recorded in the trace buffer. */ | |
1139 | ||
1140 | #define DBBC_ADDR (0xd80000) | |
1141 | ||
1142 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1143 | ||
1144 | #define TRACE_BUFFER_BASE (0xf40000) | |
1145 | ||
a14ed312 | 1146 | static void trace_command (char *, int); |
c906108c | 1147 | |
a14ed312 | 1148 | static void untrace_command (char *, int); |
c906108c | 1149 | |
a14ed312 | 1150 | static void trace_info (char *, int); |
c906108c | 1151 | |
a14ed312 | 1152 | static void tdisassemble_command (char *, int); |
c906108c | 1153 | |
a14ed312 | 1154 | static void display_trace (int, int); |
c906108c SS |
1155 | |
1156 | /* True when instruction traces are being collected. */ | |
1157 | ||
1158 | static int tracing; | |
1159 | ||
1160 | /* Remembered PC. */ | |
1161 | ||
1162 | static CORE_ADDR last_pc; | |
1163 | ||
1164 | /* True when trace output should be displayed whenever program stops. */ | |
1165 | ||
1166 | static int trace_display; | |
1167 | ||
1168 | /* True when trace listing should include source lines. */ | |
1169 | ||
1170 | static int default_trace_show_source = 1; | |
1171 | ||
c5aa993b JM |
1172 | struct trace_buffer |
1173 | { | |
1174 | int size; | |
1175 | short *counts; | |
1176 | CORE_ADDR *addrs; | |
1177 | } | |
1178 | trace_data; | |
c906108c SS |
1179 | |
1180 | static void | |
fba45db2 | 1181 | trace_command (char *args, int from_tty) |
c906108c SS |
1182 | { |
1183 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1184 | trace_data.size = 0; | |
1185 | if (trace_data.counts == NULL) | |
f75493ed | 1186 | trace_data.counts = XCALLOC (65536, short); |
c906108c | 1187 | if (trace_data.addrs == NULL) |
f75493ed | 1188 | trace_data.addrs = XCALLOC (65536, CORE_ADDR); |
c906108c SS |
1189 | |
1190 | tracing = 1; | |
1191 | ||
1192 | printf_filtered ("Tracing is now on.\n"); | |
1193 | } | |
1194 | ||
1195 | static void | |
fba45db2 | 1196 | untrace_command (char *args, int from_tty) |
c906108c SS |
1197 | { |
1198 | tracing = 0; | |
1199 | ||
1200 | printf_filtered ("Tracing is now off.\n"); | |
1201 | } | |
1202 | ||
1203 | static void | |
fba45db2 | 1204 | trace_info (char *args, int from_tty) |
c906108c SS |
1205 | { |
1206 | int i; | |
1207 | ||
1208 | if (trace_data.size) | |
1209 | { | |
1210 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1211 | ||
1212 | for (i = 0; i < trace_data.size; ++i) | |
1213 | { | |
d4f3574e SS |
1214 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1215 | i, | |
1216 | trace_data.counts[i], | |
c906108c | 1217 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1218 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1219 | } |
1220 | } | |
1221 | else | |
1222 | printf_filtered ("No entries in trace buffer.\n"); | |
1223 | ||
1224 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1225 | } | |
1226 | ||
392a587b | 1227 | static void |
fba45db2 | 1228 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1229 | { |
1230 | if (!tracing) | |
1231 | return; | |
1232 | ||
27d94c49 | 1233 | last_pc = read_register (D10V_PC_REGNUM); |
c906108c SS |
1234 | } |
1235 | ||
1236 | /* Collect trace data from the target board and format it into a form | |
1237 | more useful for display. */ | |
1238 | ||
392a587b | 1239 | static void |
fba45db2 | 1240 | d10v_eva_get_trace_data (void) |
c906108c SS |
1241 | { |
1242 | int count, i, j, oldsize; | |
1243 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1244 | unsigned int last_trace, trace_word, next_word; | |
1245 | unsigned int *tmpspace; | |
1246 | ||
1247 | if (!tracing) | |
1248 | return; | |
1249 | ||
c5aa993b | 1250 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1251 | |
1252 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1253 | ||
1254 | /* Collect buffer contents from the target, stopping when we reach | |
1255 | the word recorded when execution resumed. */ | |
1256 | ||
1257 | count = 0; | |
1258 | while (last_trace > 0) | |
1259 | { | |
1260 | QUIT; | |
1261 | trace_word = | |
1262 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1263 | trace_addr = trace_word & 0xffff; | |
1264 | last_trace -= 4; | |
1265 | /* Ignore an apparently nonsensical entry. */ | |
1266 | if (trace_addr == 0xffd5) | |
1267 | continue; | |
1268 | tmpspace[count++] = trace_word; | |
1269 | if (trace_addr == last_pc) | |
1270 | break; | |
1271 | if (count > 65535) | |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1276 | include the last instruction executed and transforming the address | |
1277 | into something that GDB likes. */ | |
1278 | ||
1279 | for (i = 0; i < count; ++i) | |
1280 | { | |
1281 | trace_word = tmpspace[i]; | |
1282 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1283 | trace_addr = trace_word & 0xffff; | |
1284 | next_cnt = (next_word >> 24) & 0xff; | |
1285 | j = trace_data.size + count - i - 1; | |
1286 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1287 | trace_data.counts[j] = next_cnt + 1; | |
1288 | } | |
1289 | ||
1290 | oldsize = trace_data.size; | |
1291 | trace_data.size += count; | |
1292 | ||
b8c9b27d | 1293 | xfree (tmpspace); |
c906108c SS |
1294 | |
1295 | if (trace_display) | |
1296 | display_trace (oldsize, trace_data.size); | |
1297 | } | |
1298 | ||
1299 | static void | |
fba45db2 | 1300 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1301 | { |
1302 | int i, count; | |
1303 | CORE_ADDR low, high; | |
c906108c SS |
1304 | |
1305 | if (!arg) | |
1306 | { | |
1307 | low = 0; | |
1308 | high = trace_data.size; | |
1309 | } | |
c906108c | 1310 | else |
e8933a55 AC |
1311 | { |
1312 | char *space_index = strchr (arg, ' '); | |
1313 | if (space_index == NULL) | |
1314 | { | |
1315 | low = parse_and_eval_address (arg); | |
1316 | high = low + 5; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | /* Two arguments. */ | |
1321 | *space_index = '\0'; | |
1322 | low = parse_and_eval_address (arg); | |
1323 | high = parse_and_eval_address (space_index + 1); | |
1324 | if (high < low) | |
1325 | high = low; | |
1326 | } | |
c906108c SS |
1327 | } |
1328 | ||
d4f3574e | 1329 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1330 | |
1331 | display_trace (low, high); | |
1332 | ||
1333 | printf_filtered ("End of trace dump.\n"); | |
1334 | gdb_flush (gdb_stdout); | |
1335 | } | |
1336 | ||
1337 | static void | |
fba45db2 | 1338 | display_trace (int low, int high) |
c906108c SS |
1339 | { |
1340 | int i, count, trace_show_source, first, suppress; | |
1341 | CORE_ADDR next_address; | |
1342 | ||
1343 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1344 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1345 | { |
1346 | trace_show_source = 0; | |
1347 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1348 | printf_filtered ("Trace will not display any source.\n"); | |
1349 | } | |
1350 | ||
1351 | first = 1; | |
1352 | suppress = 0; | |
1353 | for (i = low; i < high; ++i) | |
1354 | { | |
1355 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1356 | count = trace_data.counts[i]; |
c906108c SS |
1357 | while (count-- > 0) |
1358 | { | |
1359 | QUIT; | |
1360 | if (trace_show_source) | |
1361 | { | |
1362 | struct symtab_and_line sal, sal_prev; | |
1363 | ||
1364 | sal_prev = find_pc_line (next_address - 4, 0); | |
1365 | sal = find_pc_line (next_address, 0); | |
1366 | ||
1367 | if (sal.symtab) | |
1368 | { | |
1369 | if (first || sal.line != sal_prev.line) | |
1370 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1371 | suppress = 0; | |
1372 | } | |
1373 | else | |
1374 | { | |
1375 | if (!suppress) | |
1376 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1377 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1378 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1379 | suppress = 1; |
1380 | } | |
1381 | } | |
1382 | first = 0; | |
1383 | print_address (next_address, gdb_stdout); | |
1384 | printf_filtered (":"); | |
1385 | printf_filtered ("\t"); | |
1386 | wrap_here (" "); | |
92bf2b80 | 1387 | next_address += gdb_print_insn (next_address, gdb_stdout); |
c906108c SS |
1388 | printf_filtered ("\n"); |
1389 | gdb_flush (gdb_stdout); | |
1390 | } | |
1391 | } | |
1392 | } | |
1393 | ||
7f6104a9 | 1394 | static CORE_ADDR |
12cc2063 | 1395 | d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
7f6104a9 | 1396 | { |
12cc2063 | 1397 | ULONGEST pc; |
27d94c49 | 1398 | frame_unwind_unsigned_register (next_frame, D10V_PC_REGNUM, &pc); |
12cc2063 | 1399 | return d10v_make_iaddr (pc); |
7f6104a9 AC |
1400 | } |
1401 | ||
1402 | /* Given a GDB frame, determine the address of the calling function's | |
1403 | frame. This will be used to create a new GDB frame struct. */ | |
1404 | ||
1405 | static void | |
6dc42492 AC |
1406 | d10v_frame_this_id (struct frame_info *next_frame, |
1407 | void **this_prologue_cache, | |
1408 | struct frame_id *this_id) | |
7f6104a9 | 1409 | { |
6dc42492 AC |
1410 | struct d10v_unwind_cache *info |
1411 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
1412 | CORE_ADDR base; | |
81f8a206 AC |
1413 | CORE_ADDR func; |
1414 | struct frame_id id; | |
7f6104a9 | 1415 | |
81f8a206 AC |
1416 | /* The FUNC is easy. */ |
1417 | func = frame_func_unwind (next_frame); | |
7f6104a9 | 1418 | |
6dc42492 AC |
1419 | /* This is meant to halt the backtrace at "_start". Make sure we |
1420 | don't halt it at a generic dummy frame. */ | |
81f8a206 | 1421 | if (func <= IMEM_START || inside_entry_file (func)) |
6dc42492 | 1422 | return; |
7f6104a9 | 1423 | |
6dc42492 AC |
1424 | /* Hopefully the prologue analysis either correctly determined the |
1425 | frame's base (which is the SP from the previous frame), or set | |
1426 | that base to "NULL". */ | |
270cb5d6 | 1427 | base = info->prev_sp; |
6dc42492 AC |
1428 | if (base == STACK_START || base == 0) |
1429 | return; | |
7f6104a9 | 1430 | |
81f8a206 AC |
1431 | id = frame_id_build (base, func); |
1432 | ||
6dc42492 AC |
1433 | /* Check that we're not going round in circles with the same frame |
1434 | ID (but avoid applying the test to sentinel frames which do go | |
1435 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1436 | compare the frame's PC value. */ | |
1437 | if (frame_relative_level (next_frame) >= 0 | |
1438 | && get_frame_type (next_frame) != DUMMY_FRAME | |
81f8a206 | 1439 | && frame_id_eq (get_frame_id (next_frame), id)) |
7f6104a9 AC |
1440 | return; |
1441 | ||
81f8a206 | 1442 | (*this_id) = id; |
7f6104a9 AC |
1443 | } |
1444 | ||
1445 | static void | |
6dc42492 AC |
1446 | saved_regs_unwinder (struct frame_info *next_frame, |
1447 | CORE_ADDR *this_saved_regs, | |
7f6104a9 AC |
1448 | int regnum, int *optimizedp, |
1449 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1450 | int *realnump, void *bufferp) | |
1451 | { | |
6dc42492 | 1452 | if (this_saved_regs[regnum] != 0) |
7f6104a9 | 1453 | { |
f75493ed | 1454 | if (regnum == D10V_SP_REGNUM) |
7f6104a9 AC |
1455 | { |
1456 | /* SP register treated specially. */ | |
1457 | *optimizedp = 0; | |
1458 | *lvalp = not_lval; | |
1459 | *addrp = 0; | |
1460 | *realnump = -1; | |
1461 | if (bufferp != NULL) | |
f75493ed AC |
1462 | store_unsigned_integer (bufferp, |
1463 | register_size (current_gdbarch, regnum), | |
1464 | this_saved_regs[regnum]); | |
7f6104a9 AC |
1465 | } |
1466 | else | |
1467 | { | |
1468 | /* Any other register is saved in memory, fetch it but cache | |
1469 | a local copy of its value. */ | |
1470 | *optimizedp = 0; | |
1471 | *lvalp = lval_memory; | |
6dc42492 | 1472 | *addrp = this_saved_regs[regnum]; |
7f6104a9 AC |
1473 | *realnump = -1; |
1474 | if (bufferp != NULL) | |
1475 | { | |
1476 | /* Read the value in from memory. */ | |
6dc42492 | 1477 | read_memory (this_saved_regs[regnum], bufferp, |
08a617da | 1478 | register_size (current_gdbarch, regnum)); |
7f6104a9 AC |
1479 | } |
1480 | } | |
1481 | return; | |
1482 | } | |
1483 | ||
1484 | /* No luck, assume this and the next frame have the same register | |
1485 | value. If a value is needed, pass the request on down the chain; | |
1486 | otherwise just return an indication that the value is in the same | |
1487 | register as the next frame. */ | |
6dc42492 AC |
1488 | frame_register_unwind (next_frame, regnum, optimizedp, lvalp, addrp, |
1489 | realnump, bufferp); | |
7f6104a9 AC |
1490 | } |
1491 | ||
1492 | ||
1493 | static void | |
6dc42492 AC |
1494 | d10v_frame_prev_register (struct frame_info *next_frame, |
1495 | void **this_prologue_cache, | |
1496 | int regnum, int *optimizedp, | |
1497 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1498 | int *realnump, void *bufferp) | |
7f6104a9 | 1499 | { |
6dc42492 AC |
1500 | struct d10v_unwind_cache *info |
1501 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
27d94c49 | 1502 | if (regnum == D10V_PC_REGNUM) |
ef840a37 AC |
1503 | { |
1504 | /* The call instruction saves the caller's PC in LR. The | |
1505 | function prologue of the callee may then save the LR on the | |
1506 | stack. Find that possibly saved LR value and return it. */ | |
6dc42492 | 1507 | saved_regs_unwinder (next_frame, info->saved_regs, LR_REGNUM, optimizedp, |
ef840a37 AC |
1508 | lvalp, addrp, realnump, bufferp); |
1509 | } | |
1510 | else | |
1511 | { | |
6dc42492 | 1512 | saved_regs_unwinder (next_frame, info->saved_regs, regnum, optimizedp, |
ef840a37 AC |
1513 | lvalp, addrp, realnump, bufferp); |
1514 | } | |
7f6104a9 AC |
1515 | } |
1516 | ||
270cb5d6 | 1517 | static const struct frame_unwind d10v_frame_unwind = { |
7df05f2b | 1518 | NORMAL_FRAME, |
6dc42492 AC |
1519 | d10v_frame_this_id, |
1520 | d10v_frame_prev_register | |
7f6104a9 AC |
1521 | }; |
1522 | ||
1523 | const struct frame_unwind * | |
1524 | d10v_frame_p (CORE_ADDR pc) | |
1525 | { | |
1526 | return &d10v_frame_unwind; | |
1527 | } | |
1528 | ||
270cb5d6 AC |
1529 | static CORE_ADDR |
1530 | d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1531 | { | |
1532 | struct d10v_unwind_cache *info | |
1533 | = d10v_frame_unwind_cache (next_frame, this_cache); | |
1534 | return info->base; | |
1535 | } | |
1536 | ||
1537 | static const struct frame_base d10v_frame_base = { | |
1538 | &d10v_frame_unwind, | |
1539 | d10v_frame_base_address, | |
1540 | d10v_frame_base_address, | |
1541 | d10v_frame_base_address | |
1542 | }; | |
1543 | ||
6314f104 AC |
1544 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1545 | dummy frame. The frame ID's base needs to match the TOS value | |
1546 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1547 | breakpoint. */ | |
1548 | ||
1549 | static struct frame_id | |
1550 | d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1551 | { | |
1552 | ULONGEST base; | |
f75493ed | 1553 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &base); |
11889732 | 1554 | return frame_id_build (d10v_make_daddr (base), frame_pc_unwind (next_frame)); |
6314f104 AC |
1555 | } |
1556 | ||
0f71a2f6 | 1557 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1558 | |
0f71a2f6 | 1559 | static struct gdbarch * |
fba45db2 | 1560 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1561 | { |
0f71a2f6 | 1562 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1563 | int d10v_num_regs; |
1564 | struct gdbarch_tdep *tdep; | |
1565 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1566 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1567 | |
4ce44c66 JM |
1568 | /* Find a candidate among the list of pre-declared architectures. */ |
1569 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1570 | if (arches != NULL) |
1571 | return arches->gdbarch; | |
4ce44c66 JM |
1572 | |
1573 | /* None found, create a new architecture from the information | |
1574 | provided. */ | |
1575 | tdep = XMALLOC (struct gdbarch_tdep); | |
1576 | gdbarch = gdbarch_alloc (&info, tdep); | |
1577 | ||
1578 | switch (info.bfd_arch_info->mach) | |
1579 | { | |
1580 | case bfd_mach_d10v_ts2: | |
1581 | d10v_num_regs = 37; | |
1582 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1583 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1584 | tdep->a0_regnum = TS2_A0_REGNUM; |
1585 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1586 | tdep->dmap_register = d10v_ts2_dmap_register; |
1587 | tdep->imap_register = d10v_ts2_imap_register; | |
1588 | break; | |
1589 | default: | |
1590 | case bfd_mach_d10v_ts3: | |
1591 | d10v_num_regs = 42; | |
1592 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1593 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1594 | tdep->a0_regnum = TS3_A0_REGNUM; |
1595 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1596 | tdep->dmap_register = d10v_ts3_dmap_register; |
1597 | tdep->imap_register = d10v_ts3_imap_register; | |
1598 | break; | |
1599 | } | |
0f71a2f6 JM |
1600 | |
1601 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1602 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
0f71a2f6 | 1603 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
0f71a2f6 JM |
1604 | |
1605 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
f75493ed | 1606 | set_gdbarch_sp_regnum (gdbarch, D10V_SP_REGNUM); |
0f71a2f6 | 1607 | set_gdbarch_register_name (gdbarch, d10v_register_name); |
35cac7cf | 1608 | set_gdbarch_register_type (gdbarch, d10v_register_type); |
0f71a2f6 | 1609 | |
75af7f68 JB |
1610 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1611 | set_gdbarch_addr_bit (gdbarch, 32); | |
1612 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1613 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1614 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1615 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1616 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1617 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1618 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1619 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1620 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1621 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1622 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1623 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1624 | switch (info.byte_order) |
1625 | { | |
d7449b42 | 1626 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1627 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1628 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1629 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1630 | break; | |
778eb05e | 1631 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1632 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1633 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1634 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1635 | break; | |
1636 | default: | |
8e65ff28 AC |
1637 | internal_error (__FILE__, __LINE__, |
1638 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1639 | } |
0f71a2f6 | 1640 | |
fa1fd571 | 1641 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
7043d8dc | 1642 | set_gdbarch_push_dummy_code (gdbarch, d10v_push_dummy_code); |
5873a88d | 1643 | set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); |
fa1fd571 AC |
1644 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); |
1645 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
0f71a2f6 JM |
1646 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1647 | ||
0f71a2f6 JM |
1648 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); |
1649 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1650 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1651 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1652 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1653 | ||
1654 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1655 | ||
1656 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1657 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
f4ded5b1 | 1658 | |
0f71a2f6 | 1659 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
6ae2f580 | 1660 | set_gdbarch_frame_align (gdbarch, d10v_frame_align); |
0f71a2f6 | 1661 | |
7c7651b2 AC |
1662 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
1663 | ||
5f601589 AC |
1664 | set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); |
1665 | ||
7f6104a9 | 1666 | frame_unwind_append_predicate (gdbarch, d10v_frame_p); |
270cb5d6 | 1667 | frame_base_set_default (gdbarch, &d10v_frame_base); |
7f6104a9 | 1668 | |
6314f104 AC |
1669 | /* Methods for saving / extracting a dummy frame's ID. */ |
1670 | set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); | |
1671 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
1672 | ||
12cc2063 AC |
1673 | /* Return the unwound PC value. */ |
1674 | set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); | |
1675 | ||
0ef21242 AC |
1676 | set_gdbarch_print_insn (gdbarch, print_insn_d10v); |
1677 | ||
0f71a2f6 JM |
1678 | return gdbarch; |
1679 | } | |
1680 | ||
c906108c | 1681 | void |
fba45db2 | 1682 | _initialize_d10v_tdep (void) |
c906108c | 1683 | { |
0f71a2f6 JM |
1684 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1685 | ||
c906108c SS |
1686 | target_resume_hook = d10v_eva_prepare_to_trace; |
1687 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1688 | ||
5f601589 AC |
1689 | deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"), |
1690 | "info registers"); | |
c906108c | 1691 | |
cff3e48b | 1692 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1693 | "Enable tracing of instruction execution."); |
1694 | ||
cff3e48b | 1695 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1696 | "Disable tracing of instruction execution."); |
1697 | ||
cff3e48b | 1698 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1699 | "Disassemble the trace buffer.\n\ |
1700 | Two optional arguments specify a range of trace buffer entries\n\ | |
1701 | as reported by info trace (NOT addresses!)."); | |
1702 | ||
cff3e48b | 1703 | add_info ("itrace", trace_info, |
c906108c SS |
1704 | "Display info about the trace data buffer."); |
1705 | ||
f75493ed AC |
1706 | add_setshow_boolean_cmd ("itracedisplay", no_class, &trace_display, |
1707 | "Set automatic display of trace.\n", | |
1708 | "Show automatic display of trace.\n", | |
1709 | NULL, NULL, &setlist, &showlist); | |
1710 | add_setshow_boolean_cmd ("itracesource", no_class, | |
1711 | &default_trace_show_source, | |
1712 | "Set display of source code with trace.\n", | |
1713 | "Show display of source code with trace.\n", | |
1714 | NULL, NULL, &setlist, &showlist); | |
c5aa993b | 1715 | } |