Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
b6ba6518 KB |
2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "obstack.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
c5aa993b | 34 | #include "dis-asm.h" |
c906108c SS |
35 | #include "symfile.h" |
36 | #include "objfiles.h" | |
104c1213 | 37 | #include "language.h" |
28d069e6 | 38 | #include "arch-utils.h" |
4e052eda | 39 | #include "regcache.h" |
c906108c | 40 | |
f0d4cc9e | 41 | #include "floatformat.h" |
4ce44c66 JM |
42 | #include "sim-d10v.h" |
43 | ||
44 | #undef XMALLOC | |
45 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
46 | ||
cce74817 | 47 | struct frame_extra_info |
c5aa993b JM |
48 | { |
49 | CORE_ADDR return_pc; | |
50 | int frameless; | |
51 | int size; | |
52 | }; | |
cce74817 | 53 | |
4ce44c66 JM |
54 | struct gdbarch_tdep |
55 | { | |
56 | int a0_regnum; | |
57 | int nr_dmap_regs; | |
58 | unsigned long (*dmap_register) (int nr); | |
59 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
60 | }; |
61 | ||
62 | /* These are the addresses the D10V-EVA board maps data and | |
63 | instruction memory to. */ | |
cce74817 | 64 | |
cff3e48b | 65 | #define DMEM_START 0x2000000 |
cce74817 | 66 | #define IMEM_START 0x1000000 |
494e8a93 | 67 | #define STACK_START 0x200bffe |
cce74817 | 68 | |
4ce44c66 JM |
69 | /* d10v register names. */ |
70 | ||
71 | enum | |
72 | { | |
73 | R0_REGNUM = 0, | |
74 | LR_REGNUM = 13, | |
75 | PSW_REGNUM = 16, | |
76 | NR_IMAP_REGS = 2, | |
77 | NR_A_REGS = 2 | |
78 | }; | |
79 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
80 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
81 | ||
82 | /* d10v calling convention. */ | |
cce74817 JM |
83 | |
84 | #define ARG1_REGNUM R0_REGNUM | |
85 | #define ARGN_REGNUM 3 | |
86 | #define RET1_REGNUM R0_REGNUM | |
87 | ||
392a587b JM |
88 | /* Local functions */ |
89 | ||
a14ed312 | 90 | extern void _initialize_d10v_tdep (void); |
392a587b | 91 | |
a14ed312 | 92 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 93 | |
a14ed312 | 94 | static void d10v_eva_get_trace_data (void); |
c906108c | 95 | |
a14ed312 KB |
96 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
97 | CORE_ADDR addr); | |
cce74817 | 98 | |
f5e1cf12 | 99 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 100 | |
a14ed312 | 101 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 102 | |
f5e1cf12 | 103 | static int |
72623009 | 104 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 105 | { |
02da6206 JSC |
106 | return ((chain) != 0 && (frame) != 0 |
107 | && (frame)->pc > IMEM_START | |
108 | && !inside_entry_file (FRAME_SAVED_PC (frame))); | |
c906108c SS |
109 | } |
110 | ||
23964bcd | 111 | static CORE_ADDR |
489137c0 AC |
112 | d10v_stack_align (CORE_ADDR len) |
113 | { | |
114 | return (len + 1) & ~1; | |
115 | } | |
c906108c SS |
116 | |
117 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
118 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
119 | and TYPE is the type (which is known to be struct, union or array). | |
120 | ||
121 | The d10v returns anything less than 8 bytes in size in | |
122 | registers. */ | |
123 | ||
f5e1cf12 | 124 | static int |
fba45db2 | 125 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 126 | { |
02da6206 JSC |
127 | long alignment; |
128 | int i; | |
129 | /* The d10v only passes a struct in a register when that structure | |
130 | has an alignment that matches the size of a register. */ | |
131 | /* If the structure doesn't fit in 4 registers, put it on the | |
132 | stack. */ | |
133 | if (TYPE_LENGTH (type) > 8) | |
134 | return 1; | |
135 | /* If the struct contains only one field, don't put it on the stack | |
136 | - gcc can fit it in one or more registers. */ | |
137 | if (TYPE_NFIELDS (type) == 1) | |
138 | return 0; | |
139 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
140 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
141 | { | |
142 | /* If the alignment changes, just assume it goes on the | |
143 | stack. */ | |
144 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
145 | return 1; | |
146 | } | |
147 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
148 | don't put it on the stack. */ | |
149 | if (alignment == 2 || alignment == 4) | |
150 | return 0; | |
151 | return 1; | |
c906108c SS |
152 | } |
153 | ||
154 | ||
f5e1cf12 | 155 | static unsigned char * |
fba45db2 | 156 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 157 | { |
c5aa993b JM |
158 | static unsigned char breakpoint[] = |
159 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
160 | *lenptr = sizeof (breakpoint); |
161 | return breakpoint; | |
162 | } | |
163 | ||
4ce44c66 JM |
164 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
165 | when the reg_nr isn't valid. */ | |
166 | ||
167 | enum ts2_regnums | |
168 | { | |
169 | TS2_IMAP0_REGNUM = 32, | |
170 | TS2_DMAP_REGNUM = 34, | |
171 | TS2_NR_DMAP_REGS = 1, | |
172 | TS2_A0_REGNUM = 35 | |
173 | }; | |
174 | ||
175 | static char * | |
176 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 177 | { |
c5aa993b JM |
178 | static char *register_names[] = |
179 | { | |
180 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
181 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
182 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
183 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
184 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
185 | }; |
186 | if (reg_nr < 0) | |
187 | return NULL; | |
188 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
189 | return NULL; | |
c5aa993b | 190 | return register_names[reg_nr]; |
392a587b JM |
191 | } |
192 | ||
4ce44c66 JM |
193 | enum ts3_regnums |
194 | { | |
195 | TS3_IMAP0_REGNUM = 36, | |
196 | TS3_DMAP0_REGNUM = 38, | |
197 | TS3_NR_DMAP_REGS = 4, | |
198 | TS3_A0_REGNUM = 32 | |
199 | }; | |
200 | ||
201 | static char * | |
202 | d10v_ts3_register_name (int reg_nr) | |
203 | { | |
204 | static char *register_names[] = | |
205 | { | |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
207 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
208 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
209 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
210 | "a0", "a1", | |
211 | "spi", "spu", | |
212 | "imap0", "imap1", | |
213 | "dmap0", "dmap1", "dmap2", "dmap3" | |
214 | }; | |
215 | if (reg_nr < 0) | |
216 | return NULL; | |
217 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
218 | return NULL; | |
219 | return register_names[reg_nr]; | |
220 | } | |
221 | ||
bf93dfed JB |
222 | /* Access the DMAP/IMAP registers in a target independent way. |
223 | ||
224 | Divide the D10V's 64k data space into four 16k segments: | |
225 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
226 | 0xc000 -- 0xffff. | |
227 | ||
228 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
229 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
230 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
231 | unified memory or instruction memory, under the control of the | |
232 | single DMAP register. | |
233 | ||
234 | On the TS3, there are four DMAP registers, each of which controls | |
235 | one of the segments. */ | |
4ce44c66 JM |
236 | |
237 | static unsigned long | |
238 | d10v_ts2_dmap_register (int reg_nr) | |
239 | { | |
240 | switch (reg_nr) | |
241 | { | |
242 | case 0: | |
243 | case 1: | |
244 | return 0x2000; | |
245 | case 2: | |
246 | return read_register (TS2_DMAP_REGNUM); | |
247 | default: | |
248 | return 0; | |
249 | } | |
250 | } | |
251 | ||
252 | static unsigned long | |
253 | d10v_ts3_dmap_register (int reg_nr) | |
254 | { | |
255 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
256 | } | |
257 | ||
258 | static unsigned long | |
259 | d10v_dmap_register (int reg_nr) | |
260 | { | |
261 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
262 | } | |
263 | ||
264 | static unsigned long | |
265 | d10v_ts2_imap_register (int reg_nr) | |
266 | { | |
267 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
268 | } | |
269 | ||
270 | static unsigned long | |
271 | d10v_ts3_imap_register (int reg_nr) | |
272 | { | |
273 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
274 | } | |
275 | ||
276 | static unsigned long | |
277 | d10v_imap_register (int reg_nr) | |
278 | { | |
279 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
280 | } | |
281 | ||
282 | /* MAP GDB's internal register numbering (determined by the layout fo | |
283 | the REGISTER_BYTE array) onto the simulator's register | |
284 | numbering. */ | |
285 | ||
286 | static int | |
287 | d10v_ts2_register_sim_regno (int nr) | |
288 | { | |
289 | if (nr >= TS2_IMAP0_REGNUM | |
290 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
291 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
292 | if (nr == TS2_DMAP_REGNUM) | |
293 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
294 | if (nr >= TS2_A0_REGNUM | |
295 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
296 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
297 | return nr; | |
298 | } | |
299 | ||
300 | static int | |
301 | d10v_ts3_register_sim_regno (int nr) | |
302 | { | |
303 | if (nr >= TS3_IMAP0_REGNUM | |
304 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
305 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
306 | if (nr >= TS3_DMAP0_REGNUM | |
307 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
308 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
309 | if (nr >= TS3_A0_REGNUM | |
310 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
311 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
312 | return nr; | |
313 | } | |
314 | ||
392a587b JM |
315 | /* Index within `registers' of the first byte of the space for |
316 | register REG_NR. */ | |
317 | ||
f5e1cf12 | 318 | static int |
fba45db2 | 319 | d10v_register_byte (int reg_nr) |
392a587b | 320 | { |
4ce44c66 | 321 | if (reg_nr < A0_REGNUM) |
392a587b | 322 | return (reg_nr * 2); |
4ce44c66 JM |
323 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
324 | return (A0_REGNUM * 2 | |
325 | + (reg_nr - A0_REGNUM) * 8); | |
326 | else | |
327 | return (A0_REGNUM * 2 | |
328 | + NR_A_REGS * 8 | |
329 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
330 | } |
331 | ||
332 | /* Number of bytes of storage in the actual machine representation for | |
333 | register REG_NR. */ | |
334 | ||
f5e1cf12 | 335 | static int |
fba45db2 | 336 | d10v_register_raw_size (int reg_nr) |
392a587b | 337 | { |
4ce44c66 JM |
338 | if (reg_nr < A0_REGNUM) |
339 | return 2; | |
340 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
341 | return 8; |
342 | else | |
343 | return 2; | |
344 | } | |
345 | ||
392a587b JM |
346 | /* Return the GDB type object for the "standard" data type |
347 | of data in register N. */ | |
348 | ||
f5e1cf12 | 349 | static struct type * |
fba45db2 | 350 | d10v_register_virtual_type (int reg_nr) |
392a587b | 351 | { |
75af7f68 JB |
352 | if (reg_nr == PC_REGNUM) |
353 | return builtin_type_void_func_ptr; | |
354 | else if (reg_nr >= A0_REGNUM | |
4ce44c66 JM |
355 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
356 | return builtin_type_int64; | |
392a587b | 357 | else |
4ce44c66 | 358 | return builtin_type_int16; |
392a587b JM |
359 | } |
360 | ||
f5e1cf12 | 361 | static CORE_ADDR |
fba45db2 | 362 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
363 | { |
364 | return ((x) | DMEM_START); | |
365 | } | |
366 | ||
f5e1cf12 | 367 | static CORE_ADDR |
fba45db2 | 368 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
369 | { |
370 | return (((x) << 2) | IMEM_START); | |
371 | } | |
372 | ||
f5e1cf12 | 373 | static int |
fba45db2 | 374 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
375 | { |
376 | return (((x) & 0x3000000) == DMEM_START); | |
377 | } | |
378 | ||
f5e1cf12 | 379 | static int |
fba45db2 | 380 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
381 | { |
382 | return (((x) & 0x3000000) == IMEM_START); | |
383 | } | |
384 | ||
385 | ||
f5e1cf12 | 386 | static CORE_ADDR |
fba45db2 | 387 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
388 | { |
389 | return (((x) >> 2) & 0xffff); | |
390 | } | |
391 | ||
f5e1cf12 | 392 | static CORE_ADDR |
fba45db2 | 393 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
394 | { |
395 | return ((x) & 0xffff); | |
396 | } | |
397 | ||
75af7f68 JB |
398 | static void |
399 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
400 | { | |
401 | /* Is it a code address? */ | |
402 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
403 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
404 | { | |
75af7f68 JB |
405 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
406 | d10v_convert_iaddr_to_raw (addr)); | |
407 | } | |
408 | else | |
409 | { | |
410 | /* Strip off any upper segment bits. */ | |
411 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
412 | d10v_convert_daddr_to_raw (addr)); | |
413 | } | |
414 | } | |
415 | ||
416 | static CORE_ADDR | |
417 | d10v_pointer_to_address (struct type *type, void *buf) | |
418 | { | |
419 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
420 | ||
421 | /* Is it a code address? */ | |
422 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
423 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
424 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
425 | return d10v_make_iaddr (addr); |
426 | else | |
427 | return d10v_make_daddr (addr); | |
428 | } | |
429 | ||
fc0c74b1 AC |
430 | static CORE_ADDR |
431 | d10v_integer_to_address (struct type *type, void *buf) | |
432 | { | |
433 | LONGEST val; | |
434 | val = unpack_long (type, buf); | |
435 | if (TYPE_CODE (type) == TYPE_CODE_INT | |
436 | && TYPE_LENGTH (type) <= TYPE_LENGTH (builtin_type_void_data_ptr)) | |
437 | /* Convert small integers that would would be directly copied into | |
438 | a pointer variable into an address pointing into data space. */ | |
439 | return d10v_make_daddr (val & 0xffff); | |
440 | else | |
441 | /* The value is too large to fit in a pointer. Assume this was | |
442 | intentional and that the user in fact specified a raw address. */ | |
443 | return val; | |
444 | } | |
75af7f68 | 445 | |
392a587b JM |
446 | /* Store the address of the place in which to copy the structure the |
447 | subroutine will return. This is called from call_function. | |
448 | ||
449 | We store structs through a pointer passed in the first Argument | |
450 | register. */ | |
451 | ||
f5e1cf12 | 452 | static void |
fba45db2 | 453 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
454 | { |
455 | write_register (ARG1_REGNUM, (addr)); | |
456 | } | |
457 | ||
458 | /* Write into appropriate registers a function return value | |
459 | of type TYPE, given in virtual format. | |
460 | ||
461 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
462 | ||
f5e1cf12 | 463 | static void |
fba45db2 | 464 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
465 | { |
466 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
467 | valbuf, | |
468 | TYPE_LENGTH (type)); | |
469 | } | |
470 | ||
471 | /* Extract from an array REGBUF containing the (raw) register state | |
472 | the address in which a function should return its structure value, | |
473 | as a CORE_ADDR (or an expression that can be used as one). */ | |
474 | ||
f5e1cf12 | 475 | static CORE_ADDR |
fba45db2 | 476 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
477 | { |
478 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
479 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
480 | | DMEM_START); | |
481 | } | |
482 | ||
f5e1cf12 | 483 | static CORE_ADDR |
fba45db2 | 484 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 485 | { |
cce74817 | 486 | return ((frame)->extra_info->return_pc); |
392a587b JM |
487 | } |
488 | ||
392a587b JM |
489 | /* Immediately after a function call, return the saved pc. We can't |
490 | use frame->return_pc beause that is determined by reading R13 off | |
491 | the stack and that may not be written yet. */ | |
492 | ||
f5e1cf12 | 493 | static CORE_ADDR |
fba45db2 | 494 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 495 | { |
c5aa993b | 496 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
497 | | IMEM_START); |
498 | } | |
499 | ||
c906108c SS |
500 | /* Discard from the stack the innermost frame, restoring all saved |
501 | registers. */ | |
502 | ||
f5e1cf12 | 503 | static void |
fba45db2 | 504 | d10v_pop_frame (void) |
cce74817 JM |
505 | { |
506 | generic_pop_current_frame (do_d10v_pop_frame); | |
507 | } | |
508 | ||
509 | static void | |
fba45db2 | 510 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
511 | { |
512 | CORE_ADDR fp; | |
513 | int regnum; | |
c906108c SS |
514 | char raw_buffer[8]; |
515 | ||
cce74817 | 516 | fp = FRAME_FP (fi); |
c906108c SS |
517 | /* fill out fsr with the address of where each */ |
518 | /* register was stored in the frame */ | |
cce74817 | 519 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 520 | |
c906108c | 521 | /* now update the current registers with the old values */ |
4ce44c66 | 522 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 523 | { |
cce74817 | 524 | if (fi->saved_regs[regnum]) |
c906108c | 525 | { |
c5aa993b JM |
526 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
527 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
528 | } |
529 | } | |
530 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
531 | { | |
cce74817 | 532 | if (fi->saved_regs[regnum]) |
c906108c | 533 | { |
c5aa993b | 534 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
535 | } |
536 | } | |
cce74817 | 537 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 538 | { |
c5aa993b | 539 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
540 | } |
541 | ||
542 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 543 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
544 | target_store_registers (-1); |
545 | flush_cached_frames (); | |
546 | } | |
547 | ||
c5aa993b | 548 | static int |
fba45db2 | 549 | check_prologue (unsigned short op) |
c906108c SS |
550 | { |
551 | /* st rn, @-sp */ | |
552 | if ((op & 0x7E1F) == 0x6C1F) | |
553 | return 1; | |
554 | ||
555 | /* st2w rn, @-sp */ | |
556 | if ((op & 0x7E3F) == 0x6E1F) | |
557 | return 1; | |
558 | ||
559 | /* subi sp, n */ | |
560 | if ((op & 0x7FE1) == 0x01E1) | |
561 | return 1; | |
562 | ||
563 | /* mv r11, sp */ | |
564 | if (op == 0x417E) | |
565 | return 1; | |
566 | ||
567 | /* nop */ | |
568 | if (op == 0x5E00) | |
569 | return 1; | |
570 | ||
571 | /* st rn, @sp */ | |
572 | if ((op & 0x7E1F) == 0x681E) | |
573 | return 1; | |
574 | ||
575 | /* st2w rn, @sp */ | |
c5aa993b JM |
576 | if ((op & 0x7E3F) == 0x3A1E) |
577 | return 1; | |
c906108c SS |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
f5e1cf12 | 582 | static CORE_ADDR |
fba45db2 | 583 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
584 | { |
585 | unsigned long op; | |
586 | unsigned short op1, op2; | |
587 | CORE_ADDR func_addr, func_end; | |
588 | struct symtab_and_line sal; | |
589 | ||
590 | /* If we have line debugging information, then the end of the */ | |
591 | /* prologue should the first assembly instruction of the first source line */ | |
592 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
593 | { | |
594 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 595 | if (sal.end && sal.end < func_end) |
c906108c SS |
596 | return sal.end; |
597 | } | |
c5aa993b JM |
598 | |
599 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
600 | return pc; /* Can't access it -- assume no prologue. */ |
601 | ||
602 | while (1) | |
603 | { | |
c5aa993b | 604 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
605 | if ((op & 0xC0000000) == 0xC0000000) |
606 | { | |
607 | /* long instruction */ | |
c5aa993b JM |
608 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
609 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
610 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
611 | break; |
612 | } | |
613 | else | |
614 | { | |
615 | /* short instructions */ | |
616 | if ((op & 0xC0000000) == 0x80000000) | |
617 | { | |
618 | op2 = (op & 0x3FFF8000) >> 15; | |
619 | op1 = op & 0x7FFF; | |
c5aa993b JM |
620 | } |
621 | else | |
c906108c SS |
622 | { |
623 | op1 = (op & 0x3FFF8000) >> 15; | |
624 | op2 = op & 0x7FFF; | |
625 | } | |
c5aa993b | 626 | if (check_prologue (op1)) |
c906108c | 627 | { |
c5aa993b | 628 | if (!check_prologue (op2)) |
c906108c SS |
629 | { |
630 | /* if the previous opcode was really part of the prologue */ | |
631 | /* and not just a NOP, then we want to break after both instructions */ | |
632 | if (op1 != 0x5E00) | |
633 | pc += 4; | |
634 | break; | |
635 | } | |
636 | } | |
637 | else | |
638 | break; | |
639 | } | |
640 | pc += 4; | |
641 | } | |
642 | return pc; | |
643 | } | |
644 | ||
645 | /* Given a GDB frame, determine the address of the calling function's frame. | |
646 | This will be used to create a new GDB frame struct, and then | |
647 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 648 | */ |
c906108c | 649 | |
f5e1cf12 | 650 | static CORE_ADDR |
fba45db2 | 651 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 652 | { |
cce74817 | 653 | d10v_frame_init_saved_regs (fi); |
c906108c | 654 | |
cce74817 JM |
655 | if (fi->extra_info->return_pc == IMEM_START |
656 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 657 | return (CORE_ADDR) 0; |
c906108c | 658 | |
cce74817 | 659 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 660 | { |
cce74817 JM |
661 | if (!fi->saved_regs[SP_REGNUM] |
662 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
663 | return (CORE_ADDR) 0; |
664 | ||
cce74817 | 665 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
666 | } |
667 | ||
c5aa993b JM |
668 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
669 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
670 | return (CORE_ADDR) 0; | |
c906108c | 671 | |
7b570125 | 672 | return d10v_make_daddr (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
673 | REGISTER_RAW_SIZE (FP_REGNUM))); |
674 | } | |
c906108c SS |
675 | |
676 | static int next_addr, uses_frame; | |
677 | ||
c5aa993b | 678 | static int |
fba45db2 | 679 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
680 | { |
681 | int n; | |
682 | ||
683 | /* st rn, @-sp */ | |
684 | if ((op & 0x7E1F) == 0x6C1F) | |
685 | { | |
686 | n = (op & 0x1E0) >> 5; | |
687 | next_addr -= 2; | |
cce74817 | 688 | fi->saved_regs[n] = next_addr; |
c906108c SS |
689 | return 1; |
690 | } | |
691 | ||
692 | /* st2w rn, @-sp */ | |
693 | else if ((op & 0x7E3F) == 0x6E1F) | |
694 | { | |
695 | n = (op & 0x1E0) >> 5; | |
696 | next_addr -= 4; | |
cce74817 | 697 | fi->saved_regs[n] = next_addr; |
c5aa993b | 698 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
699 | return 1; |
700 | } | |
701 | ||
702 | /* subi sp, n */ | |
703 | if ((op & 0x7FE1) == 0x01E1) | |
704 | { | |
705 | n = (op & 0x1E) >> 1; | |
706 | if (n == 0) | |
707 | n = 16; | |
708 | next_addr -= n; | |
709 | return 1; | |
710 | } | |
711 | ||
712 | /* mv r11, sp */ | |
713 | if (op == 0x417E) | |
714 | { | |
715 | uses_frame = 1; | |
716 | return 1; | |
717 | } | |
718 | ||
719 | /* nop */ | |
720 | if (op == 0x5E00) | |
721 | return 1; | |
722 | ||
723 | /* st rn, @sp */ | |
724 | if ((op & 0x7E1F) == 0x681E) | |
725 | { | |
726 | n = (op & 0x1E0) >> 5; | |
cce74817 | 727 | fi->saved_regs[n] = next_addr; |
c906108c SS |
728 | return 1; |
729 | } | |
730 | ||
731 | /* st2w rn, @sp */ | |
732 | if ((op & 0x7E3F) == 0x3A1E) | |
733 | { | |
734 | n = (op & 0x1E0) >> 5; | |
cce74817 | 735 | fi->saved_regs[n] = next_addr; |
c5aa993b | 736 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
737 | return 1; |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
cce74817 JM |
743 | /* Put here the code to store, into fi->saved_regs, the addresses of |
744 | the saved registers of frame described by FRAME_INFO. This | |
745 | includes special registers such as pc and fp saved in special ways | |
746 | in the stack frame. sp is even more special: the address we return | |
747 | for it IS the sp for the next frame. */ | |
748 | ||
f5e1cf12 | 749 | static void |
fba45db2 | 750 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
751 | { |
752 | CORE_ADDR fp, pc; | |
753 | unsigned long op; | |
754 | unsigned short op1, op2; | |
755 | int i; | |
756 | ||
757 | fp = fi->frame; | |
cce74817 | 758 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
759 | next_addr = 0; |
760 | ||
761 | pc = get_pc_function_start (fi->pc); | |
762 | ||
763 | uses_frame = 0; | |
764 | while (1) | |
765 | { | |
c5aa993b | 766 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
767 | if ((op & 0xC0000000) == 0xC0000000) |
768 | { | |
769 | /* long instruction */ | |
770 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
771 | { | |
772 | /* add3 sp,sp,n */ | |
773 | short n = op & 0xFFFF; | |
774 | next_addr += n; | |
775 | } | |
776 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
777 | { | |
778 | /* st rn, @(offset,sp) */ | |
779 | short offset = op & 0xFFFF; | |
780 | short n = (op >> 20) & 0xF; | |
cce74817 | 781 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
782 | } |
783 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
784 | { | |
785 | /* st2w rn, @(offset,sp) */ | |
786 | short offset = op & 0xFFFF; | |
787 | short n = (op >> 20) & 0xF; | |
cce74817 | 788 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 789 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
790 | } |
791 | else | |
792 | break; | |
793 | } | |
794 | else | |
795 | { | |
796 | /* short instructions */ | |
797 | if ((op & 0xC0000000) == 0x80000000) | |
798 | { | |
799 | op2 = (op & 0x3FFF8000) >> 15; | |
800 | op1 = op & 0x7FFF; | |
c5aa993b JM |
801 | } |
802 | else | |
c906108c SS |
803 | { |
804 | op1 = (op & 0x3FFF8000) >> 15; | |
805 | op2 = op & 0x7FFF; | |
806 | } | |
c5aa993b | 807 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
808 | break; |
809 | } | |
810 | pc += 4; | |
811 | } | |
c5aa993b | 812 | |
cce74817 | 813 | fi->extra_info->size = -next_addr; |
c906108c SS |
814 | |
815 | if (!(fp & 0xffff)) | |
7b570125 | 816 | fp = d10v_make_daddr (read_register (SP_REGNUM)); |
c906108c | 817 | |
c5aa993b | 818 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 819 | if (fi->saved_regs[i]) |
c906108c | 820 | { |
c5aa993b | 821 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
822 | } |
823 | ||
cce74817 | 824 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 825 | { |
cce74817 | 826 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
7b570125 | 827 | fi->extra_info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
828 | } |
829 | else | |
830 | { | |
7b570125 | 831 | fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 832 | } |
c5aa993b | 833 | |
c906108c | 834 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 835 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
836 | { |
837 | /* if the FP was saved, that means the current FP is valid, */ | |
838 | /* otherwise, it isn't being used, so we use the SP instead */ | |
839 | if (uses_frame) | |
c5aa993b | 840 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
841 | else |
842 | { | |
cce74817 JM |
843 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
844 | fi->extra_info->frameless = 1; | |
845 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
846 | } |
847 | } | |
848 | } | |
849 | ||
f5e1cf12 | 850 | static void |
fba45db2 | 851 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 852 | { |
cce74817 JM |
853 | fi->extra_info = (struct frame_extra_info *) |
854 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
855 | frame_saved_regs_zalloc (fi); | |
856 | ||
857 | fi->extra_info->frameless = 0; | |
858 | fi->extra_info->size = 0; | |
859 | fi->extra_info->return_pc = 0; | |
c906108c SS |
860 | |
861 | /* The call dummy doesn't save any registers on the stack, so we can | |
862 | return now. */ | |
863 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
864 | { | |
865 | return; | |
866 | } | |
867 | else | |
868 | { | |
cce74817 | 869 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
870 | } |
871 | } | |
872 | ||
873 | static void | |
fba45db2 | 874 | show_regs (char *args, int from_tty) |
c906108c SS |
875 | { |
876 | int a; | |
d4f3574e SS |
877 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
878 | (long) read_register (PC_REGNUM), | |
7b570125 | 879 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
880 | (long) read_register (PSW_REGNUM), |
881 | (long) read_register (24), | |
882 | (long) read_register (25), | |
883 | (long) read_register (23)); | |
884 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
885 | (long) read_register (0), | |
886 | (long) read_register (1), | |
887 | (long) read_register (2), | |
888 | (long) read_register (3), | |
889 | (long) read_register (4), | |
890 | (long) read_register (5), | |
891 | (long) read_register (6), | |
892 | (long) read_register (7)); | |
893 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
894 | (long) read_register (8), | |
895 | (long) read_register (9), | |
896 | (long) read_register (10), | |
897 | (long) read_register (11), | |
898 | (long) read_register (12), | |
899 | (long) read_register (13), | |
900 | (long) read_register (14), | |
901 | (long) read_register (15)); | |
4ce44c66 JM |
902 | for (a = 0; a < NR_IMAP_REGS; a++) |
903 | { | |
904 | if (a > 0) | |
905 | printf_filtered (" "); | |
906 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
907 | } | |
908 | if (NR_DMAP_REGS == 1) | |
909 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
910 | else | |
911 | { | |
912 | for (a = 0; a < NR_DMAP_REGS; a++) | |
913 | { | |
914 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
915 | } | |
916 | printf_filtered ("\n"); | |
917 | } | |
918 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
919 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
920 | { |
921 | char num[MAX_REGISTER_RAW_SIZE]; | |
922 | int i; | |
923 | printf_filtered (" "); | |
c5aa993b | 924 | read_register_gen (a, (char *) &num); |
c906108c SS |
925 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
926 | { | |
927 | printf_filtered ("%02x", (num[i] & 0xff)); | |
928 | } | |
929 | } | |
930 | printf_filtered ("\n"); | |
931 | } | |
932 | ||
f5e1cf12 | 933 | static CORE_ADDR |
39f77062 | 934 | d10v_read_pc (ptid_t ptid) |
c906108c | 935 | { |
39f77062 | 936 | ptid_t save_ptid; |
c906108c SS |
937 | CORE_ADDR pc; |
938 | CORE_ADDR retval; | |
939 | ||
39f77062 KB |
940 | save_ptid = inferior_ptid; |
941 | inferior_ptid = ptid; | |
c906108c | 942 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 943 | inferior_ptid = save_ptid; |
7b570125 | 944 | retval = d10v_make_iaddr (pc); |
c906108c SS |
945 | return retval; |
946 | } | |
947 | ||
f5e1cf12 | 948 | static void |
39f77062 | 949 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 950 | { |
39f77062 | 951 | ptid_t save_ptid; |
c906108c | 952 | |
39f77062 KB |
953 | save_ptid = inferior_ptid; |
954 | inferior_ptid = ptid; | |
7b570125 | 955 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 956 | inferior_ptid = save_ptid; |
c906108c SS |
957 | } |
958 | ||
f5e1cf12 | 959 | static CORE_ADDR |
fba45db2 | 960 | d10v_read_sp (void) |
c906108c | 961 | { |
7b570125 | 962 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
963 | } |
964 | ||
f5e1cf12 | 965 | static void |
fba45db2 | 966 | d10v_write_sp (CORE_ADDR val) |
c906108c | 967 | { |
7b570125 | 968 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
969 | } |
970 | ||
f5e1cf12 | 971 | static void |
fba45db2 | 972 | d10v_write_fp (CORE_ADDR val) |
c906108c | 973 | { |
7b570125 | 974 | write_register (FP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
975 | } |
976 | ||
f5e1cf12 | 977 | static CORE_ADDR |
fba45db2 | 978 | d10v_read_fp (void) |
c906108c | 979 | { |
7b570125 | 980 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
981 | } |
982 | ||
983 | /* Function: push_return_address (pc) | |
984 | Set up the return address for the inferior function call. | |
985 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 986 | |
f5e1cf12 | 987 | static CORE_ADDR |
fba45db2 | 988 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 989 | { |
7b570125 | 990 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
991 | return sp; |
992 | } | |
c5aa993b | 993 | |
c906108c | 994 | |
7a292a7a SS |
995 | /* When arguments must be pushed onto the stack, they go on in reverse |
996 | order. The below implements a FILO (stack) to do this. */ | |
997 | ||
998 | struct stack_item | |
999 | { | |
1000 | int len; | |
1001 | struct stack_item *prev; | |
1002 | void *data; | |
1003 | }; | |
1004 | ||
a14ed312 KB |
1005 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1006 | void *contents, int len); | |
7a292a7a | 1007 | static struct stack_item * |
fba45db2 | 1008 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1009 | { |
1010 | struct stack_item *si; | |
1011 | si = xmalloc (sizeof (struct stack_item)); | |
1012 | si->data = xmalloc (len); | |
1013 | si->len = len; | |
1014 | si->prev = prev; | |
1015 | memcpy (si->data, contents, len); | |
1016 | return si; | |
1017 | } | |
1018 | ||
a14ed312 | 1019 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1020 | static struct stack_item * |
fba45db2 | 1021 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1022 | { |
1023 | struct stack_item *dead = si; | |
1024 | si = si->prev; | |
b8c9b27d KB |
1025 | xfree (dead->data); |
1026 | xfree (dead); | |
7a292a7a SS |
1027 | return si; |
1028 | } | |
1029 | ||
1030 | ||
f5e1cf12 | 1031 | static CORE_ADDR |
ea7c478f | 1032 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1033 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1034 | { |
1035 | int i; | |
1036 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1037 | struct stack_item *si = NULL; |
c5aa993b | 1038 | |
c906108c SS |
1039 | /* Fill in registers and arg lists */ |
1040 | for (i = 0; i < nargs; i++) | |
1041 | { | |
ea7c478f | 1042 | struct value *arg = args[i]; |
c906108c SS |
1043 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1044 | char *contents = VALUE_CONTENTS (arg); | |
1045 | int len = TYPE_LENGTH (type); | |
1046 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
c906108c SS |
1047 | { |
1048 | int aligned_regnum = (regnum + 1) & ~1; | |
1049 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1050 | /* fits in a single register, do not align */ | |
1051 | { | |
1052 | long val = extract_unsigned_integer (contents, len); | |
1053 | write_register (regnum++, val); | |
1054 | } | |
1055 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1056 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1057 | aligned */ |
c906108c SS |
1058 | { |
1059 | int b; | |
1060 | regnum = aligned_regnum; | |
1061 | for (b = 0; b < (len & ~1); b += 2) | |
1062 | { | |
1063 | long val = extract_unsigned_integer (&contents[b], 2); | |
1064 | write_register (regnum++, val); | |
1065 | } | |
1066 | if (b < len) | |
1067 | { | |
1068 | long val = extract_unsigned_integer (&contents[b], 1); | |
1069 | write_register (regnum++, (val << 8)); | |
1070 | } | |
1071 | } | |
1072 | else | |
1073 | { | |
7a292a7a | 1074 | /* arg will go onto stack */ |
c5aa993b | 1075 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1076 | si = push_stack_item (si, contents, len); |
c906108c SS |
1077 | } |
1078 | } | |
1079 | } | |
7a292a7a SS |
1080 | |
1081 | while (si) | |
1082 | { | |
1083 | sp = (sp - si->len) & ~1; | |
1084 | write_memory (sp, si->data, si->len); | |
1085 | si = pop_stack_item (si); | |
1086 | } | |
c5aa993b | 1087 | |
c906108c SS |
1088 | return sp; |
1089 | } | |
1090 | ||
1091 | ||
1092 | /* Given a return value in `regbuf' with a type `valtype', | |
1093 | extract and copy its value into `valbuf'. */ | |
1094 | ||
f5e1cf12 | 1095 | static void |
72623009 KB |
1096 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1097 | char *valbuf) | |
c906108c SS |
1098 | { |
1099 | int len; | |
1100 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
c906108c SS |
1101 | { |
1102 | len = TYPE_LENGTH (type); | |
1103 | if (len == 1) | |
1104 | { | |
1105 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1106 | store_unsigned_integer (valbuf, 1, c); | |
1107 | } | |
1108 | else if ((len & 1) == 0) | |
1109 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1110 | else | |
1111 | { | |
1112 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1113 | least significant part of the first register. The |
1114 | remaining bytes in remaining registers. Interestingly, | |
1115 | when such values are passed in, the last byte is in the | |
1116 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1117 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | ||
c2c6d25f JM |
1122 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1123 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1124 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1125 | (segmentation fault). Since the simulator knows all about how the | |
1126 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1127 | |
4ce44c66 | 1128 | static void |
c2c6d25f JM |
1129 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1130 | CORE_ADDR *targ_addr, int *targ_len) | |
1131 | { | |
4ce44c66 JM |
1132 | long out_addr; |
1133 | long out_len; | |
1134 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1135 | &out_addr, | |
1136 | d10v_dmap_register, | |
1137 | d10v_imap_register); | |
1138 | *targ_addr = out_addr; | |
1139 | *targ_len = out_len; | |
c2c6d25f JM |
1140 | } |
1141 | ||
4ce44c66 | 1142 | |
c906108c SS |
1143 | /* The following code implements access to, and display of, the D10V's |
1144 | instruction trace buffer. The buffer consists of 64K or more | |
1145 | 4-byte words of data, of which each words includes an 8-bit count, | |
1146 | an 8-bit segment number, and a 16-bit instruction address. | |
1147 | ||
1148 | In theory, the trace buffer is continuously capturing instruction | |
1149 | data that the CPU presents on its "debug bus", but in practice, the | |
1150 | ROMified GDB stub only enables tracing when it continues or steps | |
1151 | the program, and stops tracing when the program stops; so it | |
1152 | actually works for GDB to read the buffer counter out of memory and | |
1153 | then read each trace word. The counter records where the tracing | |
1154 | stops, but there is no record of where it started, so we remember | |
1155 | the PC when we resumed and then search backwards in the trace | |
1156 | buffer for a word that includes that address. This is not perfect, | |
1157 | because you will miss trace data if the resumption PC is the target | |
1158 | of a branch. (The value of the buffer counter is semi-random, any | |
1159 | trace data from a previous program stop is gone.) */ | |
1160 | ||
1161 | /* The address of the last word recorded in the trace buffer. */ | |
1162 | ||
1163 | #define DBBC_ADDR (0xd80000) | |
1164 | ||
1165 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1166 | ||
1167 | #define TRACE_BUFFER_BASE (0xf40000) | |
1168 | ||
a14ed312 | 1169 | static void trace_command (char *, int); |
c906108c | 1170 | |
a14ed312 | 1171 | static void untrace_command (char *, int); |
c906108c | 1172 | |
a14ed312 | 1173 | static void trace_info (char *, int); |
c906108c | 1174 | |
a14ed312 | 1175 | static void tdisassemble_command (char *, int); |
c906108c | 1176 | |
a14ed312 | 1177 | static void display_trace (int, int); |
c906108c SS |
1178 | |
1179 | /* True when instruction traces are being collected. */ | |
1180 | ||
1181 | static int tracing; | |
1182 | ||
1183 | /* Remembered PC. */ | |
1184 | ||
1185 | static CORE_ADDR last_pc; | |
1186 | ||
1187 | /* True when trace output should be displayed whenever program stops. */ | |
1188 | ||
1189 | static int trace_display; | |
1190 | ||
1191 | /* True when trace listing should include source lines. */ | |
1192 | ||
1193 | static int default_trace_show_source = 1; | |
1194 | ||
c5aa993b JM |
1195 | struct trace_buffer |
1196 | { | |
1197 | int size; | |
1198 | short *counts; | |
1199 | CORE_ADDR *addrs; | |
1200 | } | |
1201 | trace_data; | |
c906108c SS |
1202 | |
1203 | static void | |
fba45db2 | 1204 | trace_command (char *args, int from_tty) |
c906108c SS |
1205 | { |
1206 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1207 | trace_data.size = 0; | |
1208 | if (trace_data.counts == NULL) | |
c5aa993b | 1209 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1210 | if (trace_data.addrs == NULL) |
c5aa993b | 1211 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1212 | |
1213 | tracing = 1; | |
1214 | ||
1215 | printf_filtered ("Tracing is now on.\n"); | |
1216 | } | |
1217 | ||
1218 | static void | |
fba45db2 | 1219 | untrace_command (char *args, int from_tty) |
c906108c SS |
1220 | { |
1221 | tracing = 0; | |
1222 | ||
1223 | printf_filtered ("Tracing is now off.\n"); | |
1224 | } | |
1225 | ||
1226 | static void | |
fba45db2 | 1227 | trace_info (char *args, int from_tty) |
c906108c SS |
1228 | { |
1229 | int i; | |
1230 | ||
1231 | if (trace_data.size) | |
1232 | { | |
1233 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1234 | ||
1235 | for (i = 0; i < trace_data.size; ++i) | |
1236 | { | |
d4f3574e SS |
1237 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1238 | i, | |
1239 | trace_data.counts[i], | |
c906108c | 1240 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1241 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1242 | } |
1243 | } | |
1244 | else | |
1245 | printf_filtered ("No entries in trace buffer.\n"); | |
1246 | ||
1247 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1248 | } | |
1249 | ||
1250 | /* Print the instruction at address MEMADDR in debugged memory, | |
1251 | on STREAM. Returns length of the instruction, in bytes. */ | |
1252 | ||
1253 | static int | |
fba45db2 | 1254 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1255 | { |
1256 | /* If there's no disassembler, something is very wrong. */ | |
1257 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1258 | internal_error (__FILE__, __LINE__, |
1259 | "print_insn: no disassembler"); | |
c906108c | 1260 | |
d7449b42 | 1261 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1262 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1263 | else | |
1264 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1265 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1266 | } |
1267 | ||
392a587b | 1268 | static void |
fba45db2 | 1269 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1270 | { |
1271 | if (!tracing) | |
1272 | return; | |
1273 | ||
1274 | last_pc = read_register (PC_REGNUM); | |
1275 | } | |
1276 | ||
1277 | /* Collect trace data from the target board and format it into a form | |
1278 | more useful for display. */ | |
1279 | ||
392a587b | 1280 | static void |
fba45db2 | 1281 | d10v_eva_get_trace_data (void) |
c906108c SS |
1282 | { |
1283 | int count, i, j, oldsize; | |
1284 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1285 | unsigned int last_trace, trace_word, next_word; | |
1286 | unsigned int *tmpspace; | |
1287 | ||
1288 | if (!tracing) | |
1289 | return; | |
1290 | ||
c5aa993b | 1291 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1292 | |
1293 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1294 | ||
1295 | /* Collect buffer contents from the target, stopping when we reach | |
1296 | the word recorded when execution resumed. */ | |
1297 | ||
1298 | count = 0; | |
1299 | while (last_trace > 0) | |
1300 | { | |
1301 | QUIT; | |
1302 | trace_word = | |
1303 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1304 | trace_addr = trace_word & 0xffff; | |
1305 | last_trace -= 4; | |
1306 | /* Ignore an apparently nonsensical entry. */ | |
1307 | if (trace_addr == 0xffd5) | |
1308 | continue; | |
1309 | tmpspace[count++] = trace_word; | |
1310 | if (trace_addr == last_pc) | |
1311 | break; | |
1312 | if (count > 65535) | |
1313 | break; | |
1314 | } | |
1315 | ||
1316 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1317 | include the last instruction executed and transforming the address | |
1318 | into something that GDB likes. */ | |
1319 | ||
1320 | for (i = 0; i < count; ++i) | |
1321 | { | |
1322 | trace_word = tmpspace[i]; | |
1323 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1324 | trace_addr = trace_word & 0xffff; | |
1325 | next_cnt = (next_word >> 24) & 0xff; | |
1326 | j = trace_data.size + count - i - 1; | |
1327 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1328 | trace_data.counts[j] = next_cnt + 1; | |
1329 | } | |
1330 | ||
1331 | oldsize = trace_data.size; | |
1332 | trace_data.size += count; | |
1333 | ||
b8c9b27d | 1334 | xfree (tmpspace); |
c906108c SS |
1335 | |
1336 | if (trace_display) | |
1337 | display_trace (oldsize, trace_data.size); | |
1338 | } | |
1339 | ||
1340 | static void | |
fba45db2 | 1341 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1342 | { |
1343 | int i, count; | |
1344 | CORE_ADDR low, high; | |
1345 | char *space_index; | |
1346 | ||
1347 | if (!arg) | |
1348 | { | |
1349 | low = 0; | |
1350 | high = trace_data.size; | |
1351 | } | |
1352 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1353 | { | |
1354 | low = parse_and_eval_address (arg); | |
1355 | high = low + 5; | |
1356 | } | |
1357 | else | |
1358 | { | |
1359 | /* Two arguments. */ | |
1360 | *space_index = '\0'; | |
1361 | low = parse_and_eval_address (arg); | |
1362 | high = parse_and_eval_address (space_index + 1); | |
1363 | if (high < low) | |
1364 | high = low; | |
1365 | } | |
1366 | ||
d4f3574e | 1367 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1368 | |
1369 | display_trace (low, high); | |
1370 | ||
1371 | printf_filtered ("End of trace dump.\n"); | |
1372 | gdb_flush (gdb_stdout); | |
1373 | } | |
1374 | ||
1375 | static void | |
fba45db2 | 1376 | display_trace (int low, int high) |
c906108c SS |
1377 | { |
1378 | int i, count, trace_show_source, first, suppress; | |
1379 | CORE_ADDR next_address; | |
1380 | ||
1381 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1382 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1383 | { |
1384 | trace_show_source = 0; | |
1385 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1386 | printf_filtered ("Trace will not display any source.\n"); | |
1387 | } | |
1388 | ||
1389 | first = 1; | |
1390 | suppress = 0; | |
1391 | for (i = low; i < high; ++i) | |
1392 | { | |
1393 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1394 | count = trace_data.counts[i]; |
c906108c SS |
1395 | while (count-- > 0) |
1396 | { | |
1397 | QUIT; | |
1398 | if (trace_show_source) | |
1399 | { | |
1400 | struct symtab_and_line sal, sal_prev; | |
1401 | ||
1402 | sal_prev = find_pc_line (next_address - 4, 0); | |
1403 | sal = find_pc_line (next_address, 0); | |
1404 | ||
1405 | if (sal.symtab) | |
1406 | { | |
1407 | if (first || sal.line != sal_prev.line) | |
1408 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1409 | suppress = 0; | |
1410 | } | |
1411 | else | |
1412 | { | |
1413 | if (!suppress) | |
1414 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1415 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1416 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1417 | suppress = 1; |
1418 | } | |
1419 | } | |
1420 | first = 0; | |
1421 | print_address (next_address, gdb_stdout); | |
1422 | printf_filtered (":"); | |
1423 | printf_filtered ("\t"); | |
1424 | wrap_here (" "); | |
1425 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1426 | printf_filtered ("\n"); | |
1427 | gdb_flush (gdb_stdout); | |
1428 | } | |
1429 | } | |
1430 | } | |
1431 | ||
ac9a91a7 | 1432 | |
0f71a2f6 | 1433 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1434 | |
0f71a2f6 | 1435 | static struct gdbarch * |
fba45db2 | 1436 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1437 | { |
c5aa993b JM |
1438 | static LONGEST d10v_call_dummy_words[] = |
1439 | {0}; | |
0f71a2f6 | 1440 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1441 | int d10v_num_regs; |
1442 | struct gdbarch_tdep *tdep; | |
1443 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1444 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1445 | |
4ce44c66 JM |
1446 | /* Find a candidate among the list of pre-declared architectures. */ |
1447 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1448 | if (arches != NULL) |
1449 | return arches->gdbarch; | |
4ce44c66 JM |
1450 | |
1451 | /* None found, create a new architecture from the information | |
1452 | provided. */ | |
1453 | tdep = XMALLOC (struct gdbarch_tdep); | |
1454 | gdbarch = gdbarch_alloc (&info, tdep); | |
1455 | ||
1456 | switch (info.bfd_arch_info->mach) | |
1457 | { | |
1458 | case bfd_mach_d10v_ts2: | |
1459 | d10v_num_regs = 37; | |
1460 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1461 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1462 | tdep->a0_regnum = TS2_A0_REGNUM; |
1463 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1464 | tdep->dmap_register = d10v_ts2_dmap_register; |
1465 | tdep->imap_register = d10v_ts2_imap_register; | |
1466 | break; | |
1467 | default: | |
1468 | case bfd_mach_d10v_ts3: | |
1469 | d10v_num_regs = 42; | |
1470 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1471 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1472 | tdep->a0_regnum = TS3_A0_REGNUM; |
1473 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1474 | tdep->dmap_register = d10v_ts3_dmap_register; |
1475 | tdep->imap_register = d10v_ts3_imap_register; | |
1476 | break; | |
1477 | } | |
0f71a2f6 JM |
1478 | |
1479 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1480 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1481 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1482 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1483 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1484 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1485 | ||
1486 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1487 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1488 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1489 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1490 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1491 | set_gdbarch_register_size (gdbarch, 2); | |
1492 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1493 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1494 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1495 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
0e7c5946 | 1496 | set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size); |
0f71a2f6 JM |
1497 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1498 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1499 | ||
75af7f68 JB |
1500 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1501 | set_gdbarch_addr_bit (gdbarch, 32); | |
1502 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1503 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1504 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1505 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1506 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1507 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1508 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1509 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1510 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1511 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1512 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1513 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1514 | switch (info.byte_order) |
1515 | { | |
d7449b42 | 1516 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1517 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1518 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1519 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1520 | break; | |
778eb05e | 1521 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1522 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1523 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1524 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1525 | break; | |
1526 | default: | |
8e65ff28 AC |
1527 | internal_error (__FILE__, __LINE__, |
1528 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1529 | } |
0f71a2f6 JM |
1530 | |
1531 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1532 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1533 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1534 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1535 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1536 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1537 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1538 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1539 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1540 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1541 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1542 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1543 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1544 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1545 | ||
0f71a2f6 JM |
1546 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
1547 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1548 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1549 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1550 | ||
0f71a2f6 JM |
1551 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
1552 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1553 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1554 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1555 | ||
1556 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1557 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1558 | ||
1559 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1560 | ||
1561 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1562 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1563 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1564 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1565 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1566 | ||
1567 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1568 | ||
1569 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1570 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1571 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1572 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1573 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
c347ee3e MS |
1574 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
1575 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
0f71a2f6 JM |
1576 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1577 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1578 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1579 | |
7c7651b2 | 1580 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1581 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1582 | |
0f71a2f6 JM |
1583 | return gdbarch; |
1584 | } | |
1585 | ||
1586 | ||
507f3c78 KB |
1587 | extern void (*target_resume_hook) (void); |
1588 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1589 | |
1590 | void | |
fba45db2 | 1591 | _initialize_d10v_tdep (void) |
c906108c | 1592 | { |
0f71a2f6 JM |
1593 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1594 | ||
c906108c SS |
1595 | tm_print_insn = print_insn_d10v; |
1596 | ||
1597 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1598 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1599 | ||
1600 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1601 | ||
cff3e48b | 1602 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1603 | "Enable tracing of instruction execution."); |
1604 | ||
cff3e48b | 1605 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1606 | "Disable tracing of instruction execution."); |
1607 | ||
cff3e48b | 1608 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1609 | "Disassemble the trace buffer.\n\ |
1610 | Two optional arguments specify a range of trace buffer entries\n\ | |
1611 | as reported by info trace (NOT addresses!)."); | |
1612 | ||
cff3e48b | 1613 | add_info ("itrace", trace_info, |
c906108c SS |
1614 | "Display info about the trace data buffer."); |
1615 | ||
cff3e48b | 1616 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1617 | var_integer, (char *) &trace_display, |
1618 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1619 | &showlist); |
cff3e48b | 1620 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1621 | var_integer, (char *) &default_trace_show_source, |
1622 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1623 | &showlist); |
1624 | ||
c5aa993b | 1625 | } |