Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
7f6104a9 | 27 | #include "frame-unwind.h" |
270cb5d6 | 28 | #include "frame-base.h" |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdb_string.h" | |
34 | #include "value.h" | |
35 | #include "inferior.h" | |
c5aa993b | 36 | #include "dis-asm.h" |
c906108c SS |
37 | #include "symfile.h" |
38 | #include "objfiles.h" | |
104c1213 | 39 | #include "language.h" |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
e8933a55 | 42 | #include "remote.h" |
f0d4cc9e | 43 | #include "floatformat.h" |
b91b96f4 | 44 | #include "gdb/sim-d10v.h" |
8238d0bf | 45 | #include "sim-regno.h" |
4ce44c66 | 46 | |
fa1fd571 AC |
47 | #include "gdb_assert.h" |
48 | ||
4ce44c66 JM |
49 | struct gdbarch_tdep |
50 | { | |
51 | int a0_regnum; | |
52 | int nr_dmap_regs; | |
53 | unsigned long (*dmap_register) (int nr); | |
54 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
55 | }; |
56 | ||
57 | /* These are the addresses the D10V-EVA board maps data and | |
58 | instruction memory to. */ | |
cce74817 | 59 | |
78eac43e MS |
60 | enum memspace { |
61 | DMEM_START = 0x2000000, | |
62 | IMEM_START = 0x1000000, | |
63 | STACK_START = 0x200bffe | |
64 | }; | |
cce74817 | 65 | |
4ce44c66 JM |
66 | /* d10v register names. */ |
67 | ||
68 | enum | |
69 | { | |
70 | R0_REGNUM = 0, | |
78eac43e | 71 | R3_REGNUM = 3, |
6c2b5168 | 72 | D10V_FP_REGNUM = 11, |
4ce44c66 | 73 | LR_REGNUM = 13, |
78eac43e | 74 | _SP_REGNUM = 15, |
4ce44c66 | 75 | PSW_REGNUM = 16, |
78eac43e | 76 | _PC_REGNUM = 18, |
4ce44c66 | 77 | NR_IMAP_REGS = 2, |
78eac43e MS |
78 | NR_A_REGS = 2, |
79 | TS2_NUM_REGS = 37, | |
80 | TS3_NUM_REGS = 42, | |
81 | /* d10v calling convention. */ | |
82 | ARG1_REGNUM = R0_REGNUM, | |
83 | ARGN_REGNUM = R3_REGNUM, | |
84 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 85 | }; |
78eac43e | 86 | |
4ce44c66 JM |
87 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) |
88 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
89 | ||
392a587b JM |
90 | /* Local functions */ |
91 | ||
a14ed312 | 92 | extern void _initialize_d10v_tdep (void); |
392a587b | 93 | |
095a4c96 EZ |
94 | static CORE_ADDR d10v_read_sp (void); |
95 | ||
96 | static CORE_ADDR d10v_read_fp (void); | |
97 | ||
a14ed312 | 98 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 99 | |
a14ed312 | 100 | static void d10v_eva_get_trace_data (void); |
c906108c | 101 | |
23964bcd | 102 | static CORE_ADDR |
489137c0 AC |
103 | d10v_stack_align (CORE_ADDR len) |
104 | { | |
105 | return (len + 1) & ~1; | |
106 | } | |
c906108c SS |
107 | |
108 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
109 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
110 | and TYPE is the type (which is known to be struct, union or array). | |
111 | ||
112 | The d10v returns anything less than 8 bytes in size in | |
113 | registers. */ | |
114 | ||
f5e1cf12 | 115 | static int |
fba45db2 | 116 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 117 | { |
02da6206 JSC |
118 | long alignment; |
119 | int i; | |
120 | /* The d10v only passes a struct in a register when that structure | |
121 | has an alignment that matches the size of a register. */ | |
122 | /* If the structure doesn't fit in 4 registers, put it on the | |
123 | stack. */ | |
124 | if (TYPE_LENGTH (type) > 8) | |
125 | return 1; | |
126 | /* If the struct contains only one field, don't put it on the stack | |
127 | - gcc can fit it in one or more registers. */ | |
128 | if (TYPE_NFIELDS (type) == 1) | |
129 | return 0; | |
130 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
131 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
132 | { | |
133 | /* If the alignment changes, just assume it goes on the | |
134 | stack. */ | |
135 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
136 | return 1; | |
137 | } | |
138 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
139 | don't put it on the stack. */ | |
140 | if (alignment == 2 || alignment == 4) | |
141 | return 0; | |
142 | return 1; | |
c906108c SS |
143 | } |
144 | ||
145 | ||
f4f9705a | 146 | static const unsigned char * |
fba45db2 | 147 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 148 | { |
c5aa993b JM |
149 | static unsigned char breakpoint[] = |
150 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
151 | *lenptr = sizeof (breakpoint); |
152 | return breakpoint; | |
153 | } | |
154 | ||
4ce44c66 JM |
155 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
156 | when the reg_nr isn't valid. */ | |
157 | ||
158 | enum ts2_regnums | |
159 | { | |
160 | TS2_IMAP0_REGNUM = 32, | |
161 | TS2_DMAP_REGNUM = 34, | |
162 | TS2_NR_DMAP_REGS = 1, | |
163 | TS2_A0_REGNUM = 35 | |
164 | }; | |
165 | ||
fa88f677 | 166 | static const char * |
4ce44c66 | 167 | d10v_ts2_register_name (int reg_nr) |
392a587b | 168 | { |
c5aa993b JM |
169 | static char *register_names[] = |
170 | { | |
171 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
172 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
173 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
174 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
175 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
176 | }; |
177 | if (reg_nr < 0) | |
178 | return NULL; | |
179 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
180 | return NULL; | |
c5aa993b | 181 | return register_names[reg_nr]; |
392a587b JM |
182 | } |
183 | ||
4ce44c66 JM |
184 | enum ts3_regnums |
185 | { | |
186 | TS3_IMAP0_REGNUM = 36, | |
187 | TS3_DMAP0_REGNUM = 38, | |
188 | TS3_NR_DMAP_REGS = 4, | |
189 | TS3_A0_REGNUM = 32 | |
190 | }; | |
191 | ||
fa88f677 | 192 | static const char * |
4ce44c66 JM |
193 | d10v_ts3_register_name (int reg_nr) |
194 | { | |
195 | static char *register_names[] = | |
196 | { | |
197 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
198 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
199 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
200 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
201 | "a0", "a1", | |
202 | "spi", "spu", | |
203 | "imap0", "imap1", | |
204 | "dmap0", "dmap1", "dmap2", "dmap3" | |
205 | }; | |
206 | if (reg_nr < 0) | |
207 | return NULL; | |
208 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
209 | return NULL; | |
210 | return register_names[reg_nr]; | |
211 | } | |
212 | ||
bf93dfed JB |
213 | /* Access the DMAP/IMAP registers in a target independent way. |
214 | ||
215 | Divide the D10V's 64k data space into four 16k segments: | |
216 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
217 | 0xc000 -- 0xffff. | |
218 | ||
219 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
220 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
221 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
222 | unified memory or instruction memory, under the control of the | |
223 | single DMAP register. | |
224 | ||
225 | On the TS3, there are four DMAP registers, each of which controls | |
226 | one of the segments. */ | |
4ce44c66 JM |
227 | |
228 | static unsigned long | |
229 | d10v_ts2_dmap_register (int reg_nr) | |
230 | { | |
231 | switch (reg_nr) | |
232 | { | |
233 | case 0: | |
234 | case 1: | |
235 | return 0x2000; | |
236 | case 2: | |
237 | return read_register (TS2_DMAP_REGNUM); | |
238 | default: | |
239 | return 0; | |
240 | } | |
241 | } | |
242 | ||
243 | static unsigned long | |
244 | d10v_ts3_dmap_register (int reg_nr) | |
245 | { | |
246 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
247 | } | |
248 | ||
249 | static unsigned long | |
250 | d10v_dmap_register (int reg_nr) | |
251 | { | |
252 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
253 | } | |
254 | ||
255 | static unsigned long | |
256 | d10v_ts2_imap_register (int reg_nr) | |
257 | { | |
258 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
259 | } | |
260 | ||
261 | static unsigned long | |
262 | d10v_ts3_imap_register (int reg_nr) | |
263 | { | |
264 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
265 | } | |
266 | ||
267 | static unsigned long | |
268 | d10v_imap_register (int reg_nr) | |
269 | { | |
270 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
271 | } | |
272 | ||
273 | /* MAP GDB's internal register numbering (determined by the layout fo | |
274 | the REGISTER_BYTE array) onto the simulator's register | |
275 | numbering. */ | |
276 | ||
277 | static int | |
278 | d10v_ts2_register_sim_regno (int nr) | |
279 | { | |
e8933a55 AC |
280 | /* Only makes sense to supply raw registers. */ |
281 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
282 | if (nr >= TS2_IMAP0_REGNUM |
283 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
284 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
285 | if (nr == TS2_DMAP_REGNUM) | |
286 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
287 | if (nr >= TS2_A0_REGNUM | |
288 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
289 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
290 | return nr; | |
291 | } | |
292 | ||
293 | static int | |
294 | d10v_ts3_register_sim_regno (int nr) | |
295 | { | |
e8933a55 AC |
296 | /* Only makes sense to supply raw registers. */ |
297 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
298 | if (nr >= TS3_IMAP0_REGNUM |
299 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
300 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
301 | if (nr >= TS3_DMAP0_REGNUM | |
302 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
303 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
304 | if (nr >= TS3_A0_REGNUM | |
305 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
306 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
307 | return nr; | |
308 | } | |
309 | ||
392a587b JM |
310 | /* Index within `registers' of the first byte of the space for |
311 | register REG_NR. */ | |
312 | ||
f5e1cf12 | 313 | static int |
fba45db2 | 314 | d10v_register_byte (int reg_nr) |
392a587b | 315 | { |
4ce44c66 | 316 | if (reg_nr < A0_REGNUM) |
392a587b | 317 | return (reg_nr * 2); |
4ce44c66 JM |
318 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
319 | return (A0_REGNUM * 2 | |
320 | + (reg_nr - A0_REGNUM) * 8); | |
321 | else | |
322 | return (A0_REGNUM * 2 | |
323 | + NR_A_REGS * 8 | |
324 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
325 | } |
326 | ||
327 | /* Number of bytes of storage in the actual machine representation for | |
328 | register REG_NR. */ | |
329 | ||
f5e1cf12 | 330 | static int |
fba45db2 | 331 | d10v_register_raw_size (int reg_nr) |
392a587b | 332 | { |
4ce44c66 JM |
333 | if (reg_nr < A0_REGNUM) |
334 | return 2; | |
335 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
336 | return 8; |
337 | else | |
338 | return 2; | |
339 | } | |
340 | ||
392a587b JM |
341 | /* Return the GDB type object for the "standard" data type |
342 | of data in register N. */ | |
343 | ||
f5e1cf12 | 344 | static struct type * |
35cac7cf | 345 | d10v_register_type (struct gdbarch *gdbarch, int reg_nr) |
392a587b | 346 | { |
75af7f68 JB |
347 | if (reg_nr == PC_REGNUM) |
348 | return builtin_type_void_func_ptr; | |
6c2b5168 | 349 | if (reg_nr == _SP_REGNUM || reg_nr == D10V_FP_REGNUM) |
095a4c96 | 350 | return builtin_type_void_data_ptr; |
75af7f68 | 351 | else if (reg_nr >= A0_REGNUM |
4ce44c66 JM |
352 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
353 | return builtin_type_int64; | |
392a587b | 354 | else |
4ce44c66 | 355 | return builtin_type_int16; |
392a587b JM |
356 | } |
357 | ||
f5e1cf12 | 358 | static int |
fba45db2 | 359 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
360 | { |
361 | return (((x) & 0x3000000) == DMEM_START); | |
362 | } | |
363 | ||
f5e1cf12 | 364 | static int |
fba45db2 | 365 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
366 | { |
367 | return (((x) & 0x3000000) == IMEM_START); | |
368 | } | |
369 | ||
169a7369 MS |
370 | static CORE_ADDR |
371 | d10v_make_daddr (CORE_ADDR x) | |
372 | { | |
373 | return ((x) | DMEM_START); | |
374 | } | |
375 | ||
376 | static CORE_ADDR | |
377 | d10v_make_iaddr (CORE_ADDR x) | |
378 | { | |
379 | if (d10v_iaddr_p (x)) | |
380 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
381 | else | |
382 | return (((x) << 2) | IMEM_START); | |
383 | } | |
392a587b | 384 | |
f5e1cf12 | 385 | static CORE_ADDR |
fba45db2 | 386 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
387 | { |
388 | return (((x) >> 2) & 0xffff); | |
389 | } | |
390 | ||
f5e1cf12 | 391 | static CORE_ADDR |
fba45db2 | 392 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
393 | { |
394 | return ((x) & 0xffff); | |
395 | } | |
396 | ||
75af7f68 JB |
397 | static void |
398 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
399 | { | |
400 | /* Is it a code address? */ | |
401 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
402 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
403 | { | |
75af7f68 JB |
404 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
405 | d10v_convert_iaddr_to_raw (addr)); | |
406 | } | |
407 | else | |
408 | { | |
409 | /* Strip off any upper segment bits. */ | |
410 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
411 | d10v_convert_daddr_to_raw (addr)); | |
412 | } | |
413 | } | |
414 | ||
415 | static CORE_ADDR | |
66140c26 | 416 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 JB |
417 | { |
418 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
419 | ||
420 | /* Is it a code address? */ | |
421 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
422 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
423 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
424 | return d10v_make_iaddr (addr); |
425 | else | |
426 | return d10v_make_daddr (addr); | |
427 | } | |
428 | ||
095a4c96 EZ |
429 | /* Don't do anything if we have an integer, this way users can type 'x |
430 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
431 | to the correct space are taken care of in the pointer_to_address | |
432 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
433 | static CORE_ADDR |
434 | d10v_integer_to_address (struct type *type, void *buf) | |
435 | { | |
436 | LONGEST val; | |
437 | val = unpack_long (type, buf); | |
095a4c96 | 438 | return val; |
fc0c74b1 | 439 | } |
75af7f68 | 440 | |
392a587b JM |
441 | /* Write into appropriate registers a function return value |
442 | of type TYPE, given in virtual format. | |
443 | ||
444 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
445 | ||
f5e1cf12 | 446 | static void |
fa1fd571 AC |
447 | d10v_store_return_value (struct type *type, struct regcache *regcache, |
448 | const void *valbuf) | |
392a587b | 449 | { |
fa1fd571 AC |
450 | /* Only char return values need to be shifted right within the first |
451 | regnum. */ | |
3d79a47c MS |
452 | if (TYPE_LENGTH (type) == 1 |
453 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
454 | { | |
fa1fd571 AC |
455 | bfd_byte tmp[2]; |
456 | tmp[1] = *(bfd_byte *)valbuf; | |
457 | regcache_cooked_write (regcache, RET1_REGNUM, tmp); | |
3d79a47c MS |
458 | } |
459 | else | |
fa1fd571 AC |
460 | { |
461 | int reg; | |
462 | /* A structure is never more than 8 bytes long. See | |
463 | use_struct_convention(). */ | |
464 | gdb_assert (TYPE_LENGTH (type) <= 8); | |
465 | /* Write out most registers, stop loop before trying to write | |
466 | out any dangling byte at the end of the buffer. */ | |
467 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) | |
468 | { | |
469 | regcache_cooked_write (regcache, RET1_REGNUM + reg, | |
470 | (bfd_byte *) valbuf + reg * 2); | |
471 | } | |
472 | /* Write out any dangling byte at the end of the buffer. */ | |
473 | if ((reg * 2) + 1 == TYPE_LENGTH (type)) | |
474 | regcache_cooked_write_part (regcache, reg, 0, 1, | |
475 | (bfd_byte *) valbuf + reg * 2); | |
476 | } | |
392a587b JM |
477 | } |
478 | ||
479 | /* Extract from an array REGBUF containing the (raw) register state | |
480 | the address in which a function should return its structure value, | |
481 | as a CORE_ADDR (or an expression that can be used as one). */ | |
482 | ||
f5e1cf12 | 483 | static CORE_ADDR |
fa1fd571 | 484 | d10v_extract_struct_value_address (struct regcache *regcache) |
392a587b | 485 | { |
fa1fd571 AC |
486 | ULONGEST addr; |
487 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
488 | return (addr | DMEM_START); | |
392a587b JM |
489 | } |
490 | ||
c5aa993b | 491 | static int |
fba45db2 | 492 | check_prologue (unsigned short op) |
c906108c SS |
493 | { |
494 | /* st rn, @-sp */ | |
495 | if ((op & 0x7E1F) == 0x6C1F) | |
496 | return 1; | |
497 | ||
498 | /* st2w rn, @-sp */ | |
499 | if ((op & 0x7E3F) == 0x6E1F) | |
500 | return 1; | |
501 | ||
502 | /* subi sp, n */ | |
503 | if ((op & 0x7FE1) == 0x01E1) | |
504 | return 1; | |
505 | ||
506 | /* mv r11, sp */ | |
507 | if (op == 0x417E) | |
508 | return 1; | |
509 | ||
510 | /* nop */ | |
511 | if (op == 0x5E00) | |
512 | return 1; | |
513 | ||
514 | /* st rn, @sp */ | |
515 | if ((op & 0x7E1F) == 0x681E) | |
516 | return 1; | |
517 | ||
518 | /* st2w rn, @sp */ | |
c5aa993b JM |
519 | if ((op & 0x7E3F) == 0x3A1E) |
520 | return 1; | |
c906108c SS |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
f5e1cf12 | 525 | static CORE_ADDR |
fba45db2 | 526 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
527 | { |
528 | unsigned long op; | |
529 | unsigned short op1, op2; | |
530 | CORE_ADDR func_addr, func_end; | |
531 | struct symtab_and_line sal; | |
532 | ||
533 | /* If we have line debugging information, then the end of the */ | |
534 | /* prologue should the first assembly instruction of the first source line */ | |
535 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
536 | { | |
537 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 538 | if (sal.end && sal.end < func_end) |
c906108c SS |
539 | return sal.end; |
540 | } | |
c5aa993b JM |
541 | |
542 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
543 | return pc; /* Can't access it -- assume no prologue. */ |
544 | ||
545 | while (1) | |
546 | { | |
c5aa993b | 547 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
548 | if ((op & 0xC0000000) == 0xC0000000) |
549 | { | |
550 | /* long instruction */ | |
c5aa993b JM |
551 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
552 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
553 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
554 | break; |
555 | } | |
556 | else | |
557 | { | |
558 | /* short instructions */ | |
559 | if ((op & 0xC0000000) == 0x80000000) | |
560 | { | |
561 | op2 = (op & 0x3FFF8000) >> 15; | |
562 | op1 = op & 0x7FFF; | |
c5aa993b JM |
563 | } |
564 | else | |
c906108c SS |
565 | { |
566 | op1 = (op & 0x3FFF8000) >> 15; | |
567 | op2 = op & 0x7FFF; | |
568 | } | |
c5aa993b | 569 | if (check_prologue (op1)) |
c906108c | 570 | { |
c5aa993b | 571 | if (!check_prologue (op2)) |
c906108c SS |
572 | { |
573 | /* if the previous opcode was really part of the prologue */ | |
574 | /* and not just a NOP, then we want to break after both instructions */ | |
575 | if (op1 != 0x5E00) | |
576 | pc += 4; | |
577 | break; | |
578 | } | |
579 | } | |
580 | else | |
581 | break; | |
582 | } | |
583 | pc += 4; | |
584 | } | |
585 | return pc; | |
586 | } | |
587 | ||
7f6104a9 | 588 | struct d10v_unwind_cache |
c906108c | 589 | { |
7f6104a9 | 590 | CORE_ADDR return_pc; |
270cb5d6 AC |
591 | /* The previous frame's inner most stack address. Used as this |
592 | frame ID's stack_addr. */ | |
593 | CORE_ADDR prev_sp; | |
594 | /* The frame's base, optionally used by the high-level debug info. */ | |
ceea5145 | 595 | CORE_ADDR base; |
7f6104a9 AC |
596 | int size; |
597 | CORE_ADDR *saved_regs; | |
0d843116 AC |
598 | /* How far the SP and r11 (FP) have been offset from the start of |
599 | the stack frame (as defined by the previous frame's stack | |
600 | pointer). */ | |
601 | LONGEST sp_offset; | |
602 | LONGEST r11_offset; | |
7f6104a9 AC |
603 | int uses_frame; |
604 | void **regs; | |
605 | }; | |
c906108c | 606 | |
c5aa993b | 607 | static int |
7f6104a9 AC |
608 | prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, |
609 | CORE_ADDR addr) | |
c906108c SS |
610 | { |
611 | int n; | |
612 | ||
613 | /* st rn, @-sp */ | |
614 | if ((op & 0x7E1F) == 0x6C1F) | |
615 | { | |
616 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
617 | info->sp_offset -= 2; |
618 | info->saved_regs[n] = info->sp_offset; | |
c906108c SS |
619 | return 1; |
620 | } | |
621 | ||
622 | /* st2w rn, @-sp */ | |
623 | else if ((op & 0x7E3F) == 0x6E1F) | |
624 | { | |
625 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
626 | info->sp_offset -= 4; |
627 | info->saved_regs[n] = info->sp_offset; | |
628 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
629 | return 1; |
630 | } | |
631 | ||
632 | /* subi sp, n */ | |
633 | if ((op & 0x7FE1) == 0x01E1) | |
634 | { | |
635 | n = (op & 0x1E) >> 1; | |
636 | if (n == 0) | |
637 | n = 16; | |
0d843116 | 638 | info->sp_offset -= n; |
c906108c SS |
639 | return 1; |
640 | } | |
641 | ||
642 | /* mv r11, sp */ | |
643 | if (op == 0x417E) | |
644 | { | |
7f6104a9 | 645 | info->uses_frame = 1; |
0d843116 AC |
646 | info->r11_offset = info->sp_offset; |
647 | return 1; | |
648 | } | |
649 | ||
650 | /* st rn, @r11 */ | |
651 | if ((op & 0x7E1F) == 0x6816) | |
652 | { | |
653 | n = (op & 0x1E0) >> 5; | |
654 | info->saved_regs[n] = info->r11_offset; | |
c906108c SS |
655 | return 1; |
656 | } | |
657 | ||
658 | /* nop */ | |
659 | if (op == 0x5E00) | |
660 | return 1; | |
661 | ||
662 | /* st rn, @sp */ | |
663 | if ((op & 0x7E1F) == 0x681E) | |
664 | { | |
665 | n = (op & 0x1E0) >> 5; | |
0d843116 | 666 | info->saved_regs[n] = info->sp_offset; |
c906108c SS |
667 | return 1; |
668 | } | |
669 | ||
670 | /* st2w rn, @sp */ | |
671 | if ((op & 0x7E3F) == 0x3A1E) | |
672 | { | |
673 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
674 | info->saved_regs[n] = info->sp_offset; |
675 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
676 | return 1; |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
cce74817 JM |
682 | /* Put here the code to store, into fi->saved_regs, the addresses of |
683 | the saved registers of frame described by FRAME_INFO. This | |
684 | includes special registers such as pc and fp saved in special ways | |
685 | in the stack frame. sp is even more special: the address we return | |
686 | for it IS the sp for the next frame. */ | |
687 | ||
7f6104a9 | 688 | struct d10v_unwind_cache * |
6dc42492 AC |
689 | d10v_frame_unwind_cache (struct frame_info *next_frame, |
690 | void **this_prologue_cache) | |
c906108c | 691 | { |
ceea5145 AC |
692 | CORE_ADDR pc; |
693 | ULONGEST prev_sp; | |
694 | ULONGEST this_base; | |
c906108c SS |
695 | unsigned long op; |
696 | unsigned short op1, op2; | |
697 | int i; | |
7f6104a9 AC |
698 | struct d10v_unwind_cache *info; |
699 | ||
6dc42492 AC |
700 | if ((*this_prologue_cache)) |
701 | return (*this_prologue_cache); | |
7f6104a9 AC |
702 | |
703 | info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); | |
6dc42492 | 704 | (*this_prologue_cache) = info; |
7f6104a9 AC |
705 | info->saved_regs = frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS); |
706 | ||
7f6104a9 AC |
707 | info->size = 0; |
708 | info->return_pc = 0; | |
0d843116 | 709 | info->sp_offset = 0; |
c906108c | 710 | |
7f6104a9 | 711 | info->uses_frame = 0; |
be41e9f4 | 712 | for (pc = frame_func_unwind (next_frame); |
81f8a206 | 713 | pc > 0 && pc < frame_pc_unwind (next_frame); |
270cb5d6 | 714 | pc += 4) |
c906108c | 715 | { |
c5aa993b | 716 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
717 | if ((op & 0xC0000000) == 0xC0000000) |
718 | { | |
719 | /* long instruction */ | |
720 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
721 | { | |
722 | /* add3 sp,sp,n */ | |
723 | short n = op & 0xFFFF; | |
0d843116 | 724 | info->sp_offset += n; |
c906108c SS |
725 | } |
726 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
727 | { | |
728 | /* st rn, @(offset,sp) */ | |
729 | short offset = op & 0xFFFF; | |
730 | short n = (op >> 20) & 0xF; | |
0d843116 | 731 | info->saved_regs[n] = info->sp_offset + offset; |
c906108c SS |
732 | } |
733 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
734 | { | |
735 | /* st2w rn, @(offset,sp) */ | |
736 | short offset = op & 0xFFFF; | |
737 | short n = (op >> 20) & 0xF; | |
0d843116 AC |
738 | info->saved_regs[n] = info->sp_offset + offset; |
739 | info->saved_regs[n + 1] = info->sp_offset + offset + 2; | |
c906108c SS |
740 | } |
741 | else | |
742 | break; | |
743 | } | |
744 | else | |
745 | { | |
746 | /* short instructions */ | |
747 | if ((op & 0xC0000000) == 0x80000000) | |
748 | { | |
749 | op2 = (op & 0x3FFF8000) >> 15; | |
750 | op1 = op & 0x7FFF; | |
c5aa993b JM |
751 | } |
752 | else | |
c906108c SS |
753 | { |
754 | op1 = (op & 0x3FFF8000) >> 15; | |
755 | op2 = op & 0x7FFF; | |
756 | } | |
7f6104a9 AC |
757 | if (!prologue_find_regs (info, op1, pc) |
758 | || !prologue_find_regs (info, op2, pc)) | |
c906108c SS |
759 | break; |
760 | } | |
c906108c | 761 | } |
c5aa993b | 762 | |
0d843116 | 763 | info->size = -info->sp_offset; |
c906108c | 764 | |
ceea5145 AC |
765 | /* Compute the frame's base, and the previous frame's SP. */ |
766 | if (info->uses_frame) | |
767 | { | |
768 | /* The SP was moved to the FP. This indicates that a new frame | |
769 | was created. Get THIS frame's FP value by unwinding it from | |
770 | the next frame. */ | |
6c2b5168 | 771 | frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); |
ceea5145 AC |
772 | /* The FP points at the last saved register. Adjust the FP back |
773 | to before the first saved register giving the SP. */ | |
774 | prev_sp = this_base + info->size; | |
775 | } | |
776 | else if (info->saved_regs[SP_REGNUM]) | |
777 | { | |
778 | /* The SP was saved (which is very unusual), the frame base is | |
779 | just the PREV's frame's TOP-OF-STACK. */ | |
780 | this_base = read_memory_unsigned_integer (info->saved_regs[SP_REGNUM], | |
781 | register_size (current_gdbarch, | |
782 | SP_REGNUM)); | |
783 | prev_sp = this_base; | |
784 | } | |
785 | else | |
786 | { | |
787 | /* Assume that the FP is this frame's SP but with that pushed | |
788 | stack space added back. */ | |
6dc42492 | 789 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); |
ceea5145 AC |
790 | prev_sp = this_base + info->size; |
791 | } | |
792 | ||
793 | info->base = d10v_make_daddr (this_base); | |
270cb5d6 | 794 | info->prev_sp = d10v_make_daddr (prev_sp); |
c906108c | 795 | |
ceea5145 AC |
796 | /* Adjust all the saved registers so that they contain addresses and |
797 | not offsets. */ | |
c5aa993b | 798 | for (i = 0; i < NUM_REGS - 1; i++) |
7f6104a9 | 799 | if (info->saved_regs[i]) |
c906108c | 800 | { |
270cb5d6 | 801 | info->saved_regs[i] = (info->prev_sp + info->saved_regs[i]); |
c906108c SS |
802 | } |
803 | ||
7f6104a9 | 804 | if (info->saved_regs[LR_REGNUM]) |
c906108c | 805 | { |
78eac43e | 806 | CORE_ADDR return_pc |
7f6104a9 | 807 | = read_memory_unsigned_integer (info->saved_regs[LR_REGNUM], |
08a617da | 808 | register_size (current_gdbarch, LR_REGNUM)); |
7f6104a9 | 809 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
810 | } |
811 | else | |
812 | { | |
7f6104a9 | 813 | ULONGEST return_pc; |
6dc42492 | 814 | frame_unwind_unsigned_register (next_frame, LR_REGNUM, &return_pc); |
7f6104a9 | 815 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c | 816 | } |
c5aa993b | 817 | |
ceea5145 AC |
818 | /* The SP_REGNUM is special. Instead of the address of the SP, the |
819 | previous frame's SP value is saved. */ | |
270cb5d6 | 820 | info->saved_regs[SP_REGNUM] = info->prev_sp; |
c906108c | 821 | |
7f6104a9 | 822 | return info; |
c906108c SS |
823 | } |
824 | ||
825 | static void | |
5f601589 AC |
826 | d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
827 | struct frame_info *frame, int regnum, int all) | |
c906108c | 828 | { |
5f601589 | 829 | if (regnum >= 0) |
4ce44c66 | 830 | { |
5f601589 AC |
831 | default_print_registers_info (gdbarch, file, frame, regnum, all); |
832 | return; | |
4ce44c66 | 833 | } |
5f601589 AC |
834 | |
835 | { | |
836 | ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; | |
837 | frame_read_unsigned_register (frame, PC_REGNUM, &pc); | |
838 | frame_read_unsigned_register (frame, PSW_REGNUM, &psw); | |
839 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s); | |
840 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e); | |
841 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c); | |
842 | fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", | |
843 | (long) pc, (long) d10v_make_iaddr (pc), (long) psw, | |
844 | (long) rpt_s, (long) rpt_e, (long) rpt_c); | |
845 | } | |
846 | ||
847 | { | |
848 | int group; | |
849 | for (group = 0; group < 16; group += 8) | |
850 | { | |
851 | int r; | |
852 | fprintf_filtered (file, "R%d-R%-2d", group, group + 7); | |
853 | for (r = group; r < group + 8; r++) | |
854 | { | |
855 | ULONGEST tmp; | |
856 | frame_read_unsigned_register (frame, r, &tmp); | |
857 | fprintf_filtered (file, " %04lx", (long) tmp); | |
858 | } | |
859 | fprintf_filtered (file, "\n"); | |
860 | } | |
861 | } | |
862 | ||
863 | /* Note: The IMAP/DMAP registers don't participate in function | |
864 | calls. Don't bother trying to unwind them. */ | |
865 | ||
6789195b | 866 | { |
5f601589 AC |
867 | int a; |
868 | for (a = 0; a < NR_IMAP_REGS; a++) | |
869 | { | |
870 | if (a > 0) | |
871 | fprintf_filtered (file, " "); | |
872 | fprintf_filtered (file, "IMAP%d %04lx", a, d10v_imap_register (a)); | |
873 | } | |
874 | if (NR_DMAP_REGS == 1) | |
875 | /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ | |
876 | fprintf_filtered (file, " DMAP %04lx\n", d10v_dmap_register (2)); | |
877 | else | |
878 | { | |
879 | for (a = 0; a < NR_DMAP_REGS; a++) | |
880 | { | |
881 | fprintf_filtered (file, " DMAP%d %04lx", a, d10v_dmap_register (a)); | |
882 | } | |
883 | fprintf_filtered (file, "\n"); | |
884 | } | |
885 | } | |
886 | ||
887 | { | |
888 | char *num = alloca (max_register_size (gdbarch)); | |
889 | int a; | |
890 | fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); | |
6789195b AC |
891 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) |
892 | { | |
893 | int i; | |
5f601589 AC |
894 | fprintf_filtered (file, " "); |
895 | frame_register_read (frame, a, num); | |
08a617da | 896 | for (i = 0; i < max_register_size (current_gdbarch); i++) |
6789195b | 897 | { |
5f601589 | 898 | fprintf_filtered (file, "%02x", (num[i] & 0xff)); |
6789195b AC |
899 | } |
900 | } | |
901 | } | |
5f601589 AC |
902 | fprintf_filtered (file, "\n"); |
903 | } | |
904 | ||
905 | static void | |
906 | show_regs (char *args, int from_tty) | |
907 | { | |
908 | d10v_print_registers_info (current_gdbarch, gdb_stdout, | |
909 | get_current_frame (), -1, 1); | |
c906108c SS |
910 | } |
911 | ||
f5e1cf12 | 912 | static CORE_ADDR |
39f77062 | 913 | d10v_read_pc (ptid_t ptid) |
c906108c | 914 | { |
39f77062 | 915 | ptid_t save_ptid; |
c906108c SS |
916 | CORE_ADDR pc; |
917 | CORE_ADDR retval; | |
918 | ||
39f77062 KB |
919 | save_ptid = inferior_ptid; |
920 | inferior_ptid = ptid; | |
c906108c | 921 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 922 | inferior_ptid = save_ptid; |
7b570125 | 923 | retval = d10v_make_iaddr (pc); |
c906108c SS |
924 | return retval; |
925 | } | |
926 | ||
f5e1cf12 | 927 | static void |
39f77062 | 928 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 929 | { |
39f77062 | 930 | ptid_t save_ptid; |
c906108c | 931 | |
39f77062 KB |
932 | save_ptid = inferior_ptid; |
933 | inferior_ptid = ptid; | |
7b570125 | 934 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 935 | inferior_ptid = save_ptid; |
c906108c SS |
936 | } |
937 | ||
f5e1cf12 | 938 | static CORE_ADDR |
fba45db2 | 939 | d10v_read_sp (void) |
c906108c | 940 | { |
7b570125 | 941 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
942 | } |
943 | ||
f5e1cf12 | 944 | static CORE_ADDR |
fba45db2 | 945 | d10v_read_fp (void) |
c906108c | 946 | { |
6c2b5168 | 947 | return (d10v_make_daddr (read_register (D10V_FP_REGNUM))); |
c906108c SS |
948 | } |
949 | ||
7a292a7a SS |
950 | /* When arguments must be pushed onto the stack, they go on in reverse |
951 | order. The below implements a FILO (stack) to do this. */ | |
952 | ||
953 | struct stack_item | |
954 | { | |
955 | int len; | |
956 | struct stack_item *prev; | |
957 | void *data; | |
958 | }; | |
959 | ||
a14ed312 KB |
960 | static struct stack_item *push_stack_item (struct stack_item *prev, |
961 | void *contents, int len); | |
7a292a7a | 962 | static struct stack_item * |
fba45db2 | 963 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
964 | { |
965 | struct stack_item *si; | |
966 | si = xmalloc (sizeof (struct stack_item)); | |
967 | si->data = xmalloc (len); | |
968 | si->len = len; | |
969 | si->prev = prev; | |
970 | memcpy (si->data, contents, len); | |
971 | return si; | |
972 | } | |
973 | ||
a14ed312 | 974 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 975 | static struct stack_item * |
fba45db2 | 976 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
977 | { |
978 | struct stack_item *dead = si; | |
979 | si = si->prev; | |
b8c9b27d KB |
980 | xfree (dead->data); |
981 | xfree (dead); | |
7a292a7a SS |
982 | return si; |
983 | } | |
984 | ||
985 | ||
f5e1cf12 | 986 | static CORE_ADDR |
5873a88d AC |
987 | d10v_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache, |
988 | CORE_ADDR dummy_addr, int nargs, struct value **args, | |
989 | CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
990 | { |
991 | int i; | |
992 | int regnum = ARG1_REGNUM; | |
7a292a7a | 993 | struct stack_item *si = NULL; |
7bd91a28 MS |
994 | long val; |
995 | ||
5873a88d AC |
996 | /* Set the return address. For the d10v, the return breakpoint is |
997 | always at DUMMY_ADDR. */ | |
998 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, | |
999 | d10v_convert_iaddr_to_raw (dummy_addr)); | |
1000 | ||
4183d812 AC |
1001 | /* If STRUCT_RETURN is true, then the struct return address (in |
1002 | STRUCT_ADDR) will consume the first argument-passing register. | |
1003 | Both adjust the register count and store that value. */ | |
7bd91a28 | 1004 | if (struct_return) |
4183d812 | 1005 | { |
5873a88d | 1006 | regcache_cooked_write_unsigned (regcache, regnum, struct_addr); |
4183d812 AC |
1007 | regnum++; |
1008 | } | |
c5aa993b | 1009 | |
c906108c SS |
1010 | /* Fill in registers and arg lists */ |
1011 | for (i = 0; i < nargs; i++) | |
1012 | { | |
ea7c478f | 1013 | struct value *arg = args[i]; |
c906108c SS |
1014 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1015 | char *contents = VALUE_CONTENTS (arg); | |
1016 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
1017 | int aligned_regnum = (regnum + 1) & ~1; |
1018 | ||
8b279e7a | 1019 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1020 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1021 | /* fits in a single register, do not align */ | |
1022 | { | |
1023 | val = extract_unsigned_integer (contents, len); | |
5873a88d | 1024 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
7bd91a28 MS |
1025 | } |
1026 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1027 | /* value fits in remaining registers, store keeping left | |
1028 | aligned */ | |
c906108c | 1029 | { |
7bd91a28 MS |
1030 | int b; |
1031 | regnum = aligned_regnum; | |
1032 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1033 | { |
7bd91a28 | 1034 | val = extract_unsigned_integer (&contents[b], 2); |
5873a88d | 1035 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
c906108c | 1036 | } |
7bd91a28 | 1037 | if (b < len) |
c906108c | 1038 | { |
7bd91a28 | 1039 | val = extract_unsigned_integer (&contents[b], 1); |
5873a88d | 1040 | regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); |
c906108c SS |
1041 | } |
1042 | } | |
7bd91a28 MS |
1043 | else |
1044 | { | |
1045 | /* arg will go onto stack */ | |
1046 | regnum = ARGN_REGNUM + 1; | |
1047 | si = push_stack_item (si, contents, len); | |
1048 | } | |
c906108c | 1049 | } |
7a292a7a SS |
1050 | |
1051 | while (si) | |
1052 | { | |
1053 | sp = (sp - si->len) & ~1; | |
1054 | write_memory (sp, si->data, si->len); | |
1055 | si = pop_stack_item (si); | |
1056 | } | |
c5aa993b | 1057 | |
5873a88d AC |
1058 | /* Finally, update the SP register. */ |
1059 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, | |
1060 | d10v_convert_daddr_to_raw (sp)); | |
1061 | ||
c906108c SS |
1062 | return sp; |
1063 | } | |
1064 | ||
1065 | ||
1066 | /* Given a return value in `regbuf' with a type `valtype', | |
1067 | extract and copy its value into `valbuf'. */ | |
1068 | ||
f5e1cf12 | 1069 | static void |
fa1fd571 AC |
1070 | d10v_extract_return_value (struct type *type, struct regcache *regcache, |
1071 | void *valbuf) | |
c906108c SS |
1072 | { |
1073 | int len; | |
3d79a47c MS |
1074 | #if 0 |
1075 | printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), | |
1076 | TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, | |
1077 | (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), | |
08a617da | 1078 | register_size (current_gdbarch, RET1_REGNUM))); |
3d79a47c | 1079 | #endif |
fa1fd571 | 1080 | if (TYPE_LENGTH (type) == 1) |
c906108c | 1081 | { |
fa1fd571 AC |
1082 | ULONGEST c; |
1083 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); | |
3d79a47c MS |
1084 | store_unsigned_integer (valbuf, 1, c); |
1085 | } | |
3d79a47c MS |
1086 | else |
1087 | { | |
1088 | /* For return values of odd size, the first byte is in the | |
1089 | least significant part of the first register. The | |
fa1fd571 AC |
1090 | remaining bytes in remaining registers. Interestingly, when |
1091 | such values are passed in, the last byte is in the most | |
1092 | significant byte of that same register - wierd. */ | |
1093 | int reg = RET1_REGNUM; | |
1094 | int off = 0; | |
1095 | if (TYPE_LENGTH (type) & 1) | |
1096 | { | |
1097 | regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, | |
1098 | (bfd_byte *)valbuf + off); | |
1099 | off++; | |
1100 | reg++; | |
1101 | } | |
1102 | /* Transfer the remaining registers. */ | |
1103 | for (; off < TYPE_LENGTH (type); reg++, off += 2) | |
1104 | { | |
1105 | regcache_cooked_read (regcache, RET1_REGNUM + reg, | |
1106 | (bfd_byte *) valbuf + off); | |
1107 | } | |
c906108c SS |
1108 | } |
1109 | } | |
1110 | ||
c2c6d25f JM |
1111 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1112 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1113 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1114 | (segmentation fault). Since the simulator knows all about how the | |
1115 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1116 | |
4ce44c66 | 1117 | static void |
c2c6d25f JM |
1118 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1119 | CORE_ADDR *targ_addr, int *targ_len) | |
1120 | { | |
4ce44c66 JM |
1121 | long out_addr; |
1122 | long out_len; | |
1123 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1124 | &out_addr, | |
1125 | d10v_dmap_register, | |
1126 | d10v_imap_register); | |
1127 | *targ_addr = out_addr; | |
1128 | *targ_len = out_len; | |
c2c6d25f JM |
1129 | } |
1130 | ||
4ce44c66 | 1131 | |
c906108c SS |
1132 | /* The following code implements access to, and display of, the D10V's |
1133 | instruction trace buffer. The buffer consists of 64K or more | |
1134 | 4-byte words of data, of which each words includes an 8-bit count, | |
1135 | an 8-bit segment number, and a 16-bit instruction address. | |
1136 | ||
1137 | In theory, the trace buffer is continuously capturing instruction | |
1138 | data that the CPU presents on its "debug bus", but in practice, the | |
1139 | ROMified GDB stub only enables tracing when it continues or steps | |
1140 | the program, and stops tracing when the program stops; so it | |
1141 | actually works for GDB to read the buffer counter out of memory and | |
1142 | then read each trace word. The counter records where the tracing | |
1143 | stops, but there is no record of where it started, so we remember | |
1144 | the PC when we resumed and then search backwards in the trace | |
1145 | buffer for a word that includes that address. This is not perfect, | |
1146 | because you will miss trace data if the resumption PC is the target | |
1147 | of a branch. (The value of the buffer counter is semi-random, any | |
1148 | trace data from a previous program stop is gone.) */ | |
1149 | ||
1150 | /* The address of the last word recorded in the trace buffer. */ | |
1151 | ||
1152 | #define DBBC_ADDR (0xd80000) | |
1153 | ||
1154 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1155 | ||
1156 | #define TRACE_BUFFER_BASE (0xf40000) | |
1157 | ||
a14ed312 | 1158 | static void trace_command (char *, int); |
c906108c | 1159 | |
a14ed312 | 1160 | static void untrace_command (char *, int); |
c906108c | 1161 | |
a14ed312 | 1162 | static void trace_info (char *, int); |
c906108c | 1163 | |
a14ed312 | 1164 | static void tdisassemble_command (char *, int); |
c906108c | 1165 | |
a14ed312 | 1166 | static void display_trace (int, int); |
c906108c SS |
1167 | |
1168 | /* True when instruction traces are being collected. */ | |
1169 | ||
1170 | static int tracing; | |
1171 | ||
1172 | /* Remembered PC. */ | |
1173 | ||
1174 | static CORE_ADDR last_pc; | |
1175 | ||
1176 | /* True when trace output should be displayed whenever program stops. */ | |
1177 | ||
1178 | static int trace_display; | |
1179 | ||
1180 | /* True when trace listing should include source lines. */ | |
1181 | ||
1182 | static int default_trace_show_source = 1; | |
1183 | ||
c5aa993b JM |
1184 | struct trace_buffer |
1185 | { | |
1186 | int size; | |
1187 | short *counts; | |
1188 | CORE_ADDR *addrs; | |
1189 | } | |
1190 | trace_data; | |
c906108c SS |
1191 | |
1192 | static void | |
fba45db2 | 1193 | trace_command (char *args, int from_tty) |
c906108c SS |
1194 | { |
1195 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1196 | trace_data.size = 0; | |
1197 | if (trace_data.counts == NULL) | |
c5aa993b | 1198 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1199 | if (trace_data.addrs == NULL) |
c5aa993b | 1200 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1201 | |
1202 | tracing = 1; | |
1203 | ||
1204 | printf_filtered ("Tracing is now on.\n"); | |
1205 | } | |
1206 | ||
1207 | static void | |
fba45db2 | 1208 | untrace_command (char *args, int from_tty) |
c906108c SS |
1209 | { |
1210 | tracing = 0; | |
1211 | ||
1212 | printf_filtered ("Tracing is now off.\n"); | |
1213 | } | |
1214 | ||
1215 | static void | |
fba45db2 | 1216 | trace_info (char *args, int from_tty) |
c906108c SS |
1217 | { |
1218 | int i; | |
1219 | ||
1220 | if (trace_data.size) | |
1221 | { | |
1222 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1223 | ||
1224 | for (i = 0; i < trace_data.size; ++i) | |
1225 | { | |
d4f3574e SS |
1226 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1227 | i, | |
1228 | trace_data.counts[i], | |
c906108c | 1229 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1230 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1231 | } |
1232 | } | |
1233 | else | |
1234 | printf_filtered ("No entries in trace buffer.\n"); | |
1235 | ||
1236 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1237 | } | |
1238 | ||
1239 | /* Print the instruction at address MEMADDR in debugged memory, | |
1240 | on STREAM. Returns length of the instruction, in bytes. */ | |
1241 | ||
1242 | static int | |
fba45db2 | 1243 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1244 | { |
1245 | /* If there's no disassembler, something is very wrong. */ | |
1246 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1247 | internal_error (__FILE__, __LINE__, |
1248 | "print_insn: no disassembler"); | |
c906108c | 1249 | |
d7449b42 | 1250 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1251 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1252 | else | |
1253 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1254 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1255 | } |
1256 | ||
392a587b | 1257 | static void |
fba45db2 | 1258 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1259 | { |
1260 | if (!tracing) | |
1261 | return; | |
1262 | ||
1263 | last_pc = read_register (PC_REGNUM); | |
1264 | } | |
1265 | ||
1266 | /* Collect trace data from the target board and format it into a form | |
1267 | more useful for display. */ | |
1268 | ||
392a587b | 1269 | static void |
fba45db2 | 1270 | d10v_eva_get_trace_data (void) |
c906108c SS |
1271 | { |
1272 | int count, i, j, oldsize; | |
1273 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1274 | unsigned int last_trace, trace_word, next_word; | |
1275 | unsigned int *tmpspace; | |
1276 | ||
1277 | if (!tracing) | |
1278 | return; | |
1279 | ||
c5aa993b | 1280 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1281 | |
1282 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1283 | ||
1284 | /* Collect buffer contents from the target, stopping when we reach | |
1285 | the word recorded when execution resumed. */ | |
1286 | ||
1287 | count = 0; | |
1288 | while (last_trace > 0) | |
1289 | { | |
1290 | QUIT; | |
1291 | trace_word = | |
1292 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1293 | trace_addr = trace_word & 0xffff; | |
1294 | last_trace -= 4; | |
1295 | /* Ignore an apparently nonsensical entry. */ | |
1296 | if (trace_addr == 0xffd5) | |
1297 | continue; | |
1298 | tmpspace[count++] = trace_word; | |
1299 | if (trace_addr == last_pc) | |
1300 | break; | |
1301 | if (count > 65535) | |
1302 | break; | |
1303 | } | |
1304 | ||
1305 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1306 | include the last instruction executed and transforming the address | |
1307 | into something that GDB likes. */ | |
1308 | ||
1309 | for (i = 0; i < count; ++i) | |
1310 | { | |
1311 | trace_word = tmpspace[i]; | |
1312 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1313 | trace_addr = trace_word & 0xffff; | |
1314 | next_cnt = (next_word >> 24) & 0xff; | |
1315 | j = trace_data.size + count - i - 1; | |
1316 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1317 | trace_data.counts[j] = next_cnt + 1; | |
1318 | } | |
1319 | ||
1320 | oldsize = trace_data.size; | |
1321 | trace_data.size += count; | |
1322 | ||
b8c9b27d | 1323 | xfree (tmpspace); |
c906108c SS |
1324 | |
1325 | if (trace_display) | |
1326 | display_trace (oldsize, trace_data.size); | |
1327 | } | |
1328 | ||
1329 | static void | |
fba45db2 | 1330 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1331 | { |
1332 | int i, count; | |
1333 | CORE_ADDR low, high; | |
c906108c SS |
1334 | |
1335 | if (!arg) | |
1336 | { | |
1337 | low = 0; | |
1338 | high = trace_data.size; | |
1339 | } | |
c906108c | 1340 | else |
e8933a55 AC |
1341 | { |
1342 | char *space_index = strchr (arg, ' '); | |
1343 | if (space_index == NULL) | |
1344 | { | |
1345 | low = parse_and_eval_address (arg); | |
1346 | high = low + 5; | |
1347 | } | |
1348 | else | |
1349 | { | |
1350 | /* Two arguments. */ | |
1351 | *space_index = '\0'; | |
1352 | low = parse_and_eval_address (arg); | |
1353 | high = parse_and_eval_address (space_index + 1); | |
1354 | if (high < low) | |
1355 | high = low; | |
1356 | } | |
c906108c SS |
1357 | } |
1358 | ||
d4f3574e | 1359 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1360 | |
1361 | display_trace (low, high); | |
1362 | ||
1363 | printf_filtered ("End of trace dump.\n"); | |
1364 | gdb_flush (gdb_stdout); | |
1365 | } | |
1366 | ||
1367 | static void | |
fba45db2 | 1368 | display_trace (int low, int high) |
c906108c SS |
1369 | { |
1370 | int i, count, trace_show_source, first, suppress; | |
1371 | CORE_ADDR next_address; | |
1372 | ||
1373 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1374 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1375 | { |
1376 | trace_show_source = 0; | |
1377 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1378 | printf_filtered ("Trace will not display any source.\n"); | |
1379 | } | |
1380 | ||
1381 | first = 1; | |
1382 | suppress = 0; | |
1383 | for (i = low; i < high; ++i) | |
1384 | { | |
1385 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1386 | count = trace_data.counts[i]; |
c906108c SS |
1387 | while (count-- > 0) |
1388 | { | |
1389 | QUIT; | |
1390 | if (trace_show_source) | |
1391 | { | |
1392 | struct symtab_and_line sal, sal_prev; | |
1393 | ||
1394 | sal_prev = find_pc_line (next_address - 4, 0); | |
1395 | sal = find_pc_line (next_address, 0); | |
1396 | ||
1397 | if (sal.symtab) | |
1398 | { | |
1399 | if (first || sal.line != sal_prev.line) | |
1400 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1401 | suppress = 0; | |
1402 | } | |
1403 | else | |
1404 | { | |
1405 | if (!suppress) | |
1406 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1407 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1408 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1409 | suppress = 1; |
1410 | } | |
1411 | } | |
1412 | first = 0; | |
1413 | print_address (next_address, gdb_stdout); | |
1414 | printf_filtered (":"); | |
1415 | printf_filtered ("\t"); | |
1416 | wrap_here (" "); | |
1417 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1418 | printf_filtered ("\n"); | |
1419 | gdb_flush (gdb_stdout); | |
1420 | } | |
1421 | } | |
1422 | } | |
1423 | ||
7f6104a9 | 1424 | static CORE_ADDR |
12cc2063 | 1425 | d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
7f6104a9 | 1426 | { |
12cc2063 AC |
1427 | ULONGEST pc; |
1428 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1429 | return d10v_make_iaddr (pc); | |
7f6104a9 AC |
1430 | } |
1431 | ||
1432 | /* Given a GDB frame, determine the address of the calling function's | |
1433 | frame. This will be used to create a new GDB frame struct. */ | |
1434 | ||
1435 | static void | |
6dc42492 AC |
1436 | d10v_frame_this_id (struct frame_info *next_frame, |
1437 | void **this_prologue_cache, | |
1438 | struct frame_id *this_id) | |
7f6104a9 | 1439 | { |
6dc42492 AC |
1440 | struct d10v_unwind_cache *info |
1441 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
1442 | CORE_ADDR base; | |
81f8a206 AC |
1443 | CORE_ADDR func; |
1444 | struct frame_id id; | |
7f6104a9 | 1445 | |
81f8a206 AC |
1446 | /* The FUNC is easy. */ |
1447 | func = frame_func_unwind (next_frame); | |
7f6104a9 | 1448 | |
6dc42492 AC |
1449 | /* This is meant to halt the backtrace at "_start". Make sure we |
1450 | don't halt it at a generic dummy frame. */ | |
81f8a206 | 1451 | if (func <= IMEM_START || inside_entry_file (func)) |
6dc42492 | 1452 | return; |
7f6104a9 | 1453 | |
6dc42492 AC |
1454 | /* Hopefully the prologue analysis either correctly determined the |
1455 | frame's base (which is the SP from the previous frame), or set | |
1456 | that base to "NULL". */ | |
270cb5d6 | 1457 | base = info->prev_sp; |
6dc42492 AC |
1458 | if (base == STACK_START || base == 0) |
1459 | return; | |
7f6104a9 | 1460 | |
81f8a206 AC |
1461 | id = frame_id_build (base, func); |
1462 | ||
6dc42492 AC |
1463 | /* Check that we're not going round in circles with the same frame |
1464 | ID (but avoid applying the test to sentinel frames which do go | |
1465 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1466 | compare the frame's PC value. */ | |
1467 | if (frame_relative_level (next_frame) >= 0 | |
1468 | && get_frame_type (next_frame) != DUMMY_FRAME | |
81f8a206 | 1469 | && frame_id_eq (get_frame_id (next_frame), id)) |
7f6104a9 AC |
1470 | return; |
1471 | ||
81f8a206 | 1472 | (*this_id) = id; |
7f6104a9 AC |
1473 | } |
1474 | ||
1475 | static void | |
6dc42492 AC |
1476 | saved_regs_unwinder (struct frame_info *next_frame, |
1477 | CORE_ADDR *this_saved_regs, | |
7f6104a9 AC |
1478 | int regnum, int *optimizedp, |
1479 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1480 | int *realnump, void *bufferp) | |
1481 | { | |
6dc42492 | 1482 | if (this_saved_regs[regnum] != 0) |
7f6104a9 AC |
1483 | { |
1484 | if (regnum == SP_REGNUM) | |
1485 | { | |
1486 | /* SP register treated specially. */ | |
1487 | *optimizedp = 0; | |
1488 | *lvalp = not_lval; | |
1489 | *addrp = 0; | |
1490 | *realnump = -1; | |
1491 | if (bufferp != NULL) | |
08a617da | 1492 | store_address (bufferp, register_size (current_gdbarch, regnum), |
6dc42492 | 1493 | this_saved_regs[regnum]); |
7f6104a9 AC |
1494 | } |
1495 | else | |
1496 | { | |
1497 | /* Any other register is saved in memory, fetch it but cache | |
1498 | a local copy of its value. */ | |
1499 | *optimizedp = 0; | |
1500 | *lvalp = lval_memory; | |
6dc42492 | 1501 | *addrp = this_saved_regs[regnum]; |
7f6104a9 AC |
1502 | *realnump = -1; |
1503 | if (bufferp != NULL) | |
1504 | { | |
1505 | /* Read the value in from memory. */ | |
6dc42492 | 1506 | read_memory (this_saved_regs[regnum], bufferp, |
08a617da | 1507 | register_size (current_gdbarch, regnum)); |
7f6104a9 AC |
1508 | } |
1509 | } | |
1510 | return; | |
1511 | } | |
1512 | ||
1513 | /* No luck, assume this and the next frame have the same register | |
1514 | value. If a value is needed, pass the request on down the chain; | |
1515 | otherwise just return an indication that the value is in the same | |
1516 | register as the next frame. */ | |
6dc42492 AC |
1517 | frame_register_unwind (next_frame, regnum, optimizedp, lvalp, addrp, |
1518 | realnump, bufferp); | |
7f6104a9 AC |
1519 | } |
1520 | ||
1521 | ||
1522 | static void | |
6dc42492 AC |
1523 | d10v_frame_prev_register (struct frame_info *next_frame, |
1524 | void **this_prologue_cache, | |
1525 | int regnum, int *optimizedp, | |
1526 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1527 | int *realnump, void *bufferp) | |
7f6104a9 | 1528 | { |
6dc42492 AC |
1529 | struct d10v_unwind_cache *info |
1530 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
ef840a37 AC |
1531 | if (regnum == PC_REGNUM) |
1532 | { | |
1533 | /* The call instruction saves the caller's PC in LR. The | |
1534 | function prologue of the callee may then save the LR on the | |
1535 | stack. Find that possibly saved LR value and return it. */ | |
6dc42492 | 1536 | saved_regs_unwinder (next_frame, info->saved_regs, LR_REGNUM, optimizedp, |
ef840a37 AC |
1537 | lvalp, addrp, realnump, bufferp); |
1538 | } | |
1539 | else | |
1540 | { | |
6dc42492 | 1541 | saved_regs_unwinder (next_frame, info->saved_regs, regnum, optimizedp, |
ef840a37 AC |
1542 | lvalp, addrp, realnump, bufferp); |
1543 | } | |
7f6104a9 AC |
1544 | } |
1545 | ||
270cb5d6 | 1546 | static const struct frame_unwind d10v_frame_unwind = { |
7df05f2b | 1547 | NORMAL_FRAME, |
6dc42492 AC |
1548 | d10v_frame_this_id, |
1549 | d10v_frame_prev_register | |
7f6104a9 AC |
1550 | }; |
1551 | ||
1552 | const struct frame_unwind * | |
1553 | d10v_frame_p (CORE_ADDR pc) | |
1554 | { | |
1555 | return &d10v_frame_unwind; | |
1556 | } | |
1557 | ||
270cb5d6 AC |
1558 | static CORE_ADDR |
1559 | d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1560 | { | |
1561 | struct d10v_unwind_cache *info | |
1562 | = d10v_frame_unwind_cache (next_frame, this_cache); | |
1563 | return info->base; | |
1564 | } | |
1565 | ||
1566 | static const struct frame_base d10v_frame_base = { | |
1567 | &d10v_frame_unwind, | |
1568 | d10v_frame_base_address, | |
1569 | d10v_frame_base_address, | |
1570 | d10v_frame_base_address | |
1571 | }; | |
1572 | ||
6314f104 AC |
1573 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1574 | dummy frame. The frame ID's base needs to match the TOS value | |
1575 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1576 | breakpoint. */ | |
1577 | ||
1578 | static struct frame_id | |
1579 | d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1580 | { | |
1581 | ULONGEST base; | |
6314f104 | 1582 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &base); |
11889732 | 1583 | return frame_id_build (d10v_make_daddr (base), frame_pc_unwind (next_frame)); |
6314f104 AC |
1584 | } |
1585 | ||
0f71a2f6 | 1586 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1587 | |
0f71a2f6 | 1588 | static struct gdbarch * |
fba45db2 | 1589 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1590 | { |
0f71a2f6 | 1591 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1592 | int d10v_num_regs; |
1593 | struct gdbarch_tdep *tdep; | |
1594 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1595 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1596 | |
4ce44c66 JM |
1597 | /* Find a candidate among the list of pre-declared architectures. */ |
1598 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1599 | if (arches != NULL) |
1600 | return arches->gdbarch; | |
4ce44c66 JM |
1601 | |
1602 | /* None found, create a new architecture from the information | |
1603 | provided. */ | |
1604 | tdep = XMALLOC (struct gdbarch_tdep); | |
1605 | gdbarch = gdbarch_alloc (&info, tdep); | |
1606 | ||
1607 | switch (info.bfd_arch_info->mach) | |
1608 | { | |
1609 | case bfd_mach_d10v_ts2: | |
1610 | d10v_num_regs = 37; | |
1611 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1612 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1613 | tdep->a0_regnum = TS2_A0_REGNUM; |
1614 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1615 | tdep->dmap_register = d10v_ts2_dmap_register; |
1616 | tdep->imap_register = d10v_ts2_imap_register; | |
1617 | break; | |
1618 | default: | |
1619 | case bfd_mach_d10v_ts3: | |
1620 | d10v_num_regs = 42; | |
1621 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1622 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1623 | tdep->a0_regnum = TS3_A0_REGNUM; |
1624 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1625 | tdep->dmap_register = d10v_ts3_dmap_register; |
1626 | tdep->imap_register = d10v_ts3_imap_register; | |
1627 | break; | |
1628 | } | |
0f71a2f6 JM |
1629 | |
1630 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1631 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1632 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 | 1633 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
0f71a2f6 JM |
1634 | |
1635 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1636 | set_gdbarch_sp_regnum (gdbarch, 15); | |
0f71a2f6 JM |
1637 | set_gdbarch_pc_regnum (gdbarch, 18); |
1638 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1639 | set_gdbarch_register_size (gdbarch, 2); | |
1640 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1641 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1642 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
8b279e7a | 1643 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
35cac7cf | 1644 | set_gdbarch_register_type (gdbarch, d10v_register_type); |
0f71a2f6 | 1645 | |
75af7f68 JB |
1646 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1647 | set_gdbarch_addr_bit (gdbarch, 32); | |
1648 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1649 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1650 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1651 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1652 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1653 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1654 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1655 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1656 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1657 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1658 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1659 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1660 | switch (info.byte_order) |
1661 | { | |
d7449b42 | 1662 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1663 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1664 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1665 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1666 | break; | |
778eb05e | 1667 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1668 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1669 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1670 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1671 | break; | |
1672 | default: | |
8e65ff28 AC |
1673 | internal_error (__FILE__, __LINE__, |
1674 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1675 | } |
0f71a2f6 | 1676 | |
fa1fd571 | 1677 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
5873a88d | 1678 | set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); |
fa1fd571 AC |
1679 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); |
1680 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
0f71a2f6 JM |
1681 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1682 | ||
0f71a2f6 JM |
1683 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); |
1684 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1685 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1686 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1687 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1688 | ||
1689 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1690 | ||
1691 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1692 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
f4ded5b1 | 1693 | |
0f71a2f6 | 1694 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
23964bcd | 1695 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1696 | |
7c7651b2 AC |
1697 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
1698 | ||
5f601589 AC |
1699 | set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); |
1700 | ||
7f6104a9 | 1701 | frame_unwind_append_predicate (gdbarch, d10v_frame_p); |
270cb5d6 | 1702 | frame_base_set_default (gdbarch, &d10v_frame_base); |
7f6104a9 | 1703 | |
6314f104 AC |
1704 | /* Methods for saving / extracting a dummy frame's ID. */ |
1705 | set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); | |
1706 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
1707 | ||
12cc2063 AC |
1708 | /* Return the unwound PC value. */ |
1709 | set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); | |
1710 | ||
0f71a2f6 JM |
1711 | return gdbarch; |
1712 | } | |
1713 | ||
c906108c | 1714 | void |
fba45db2 | 1715 | _initialize_d10v_tdep (void) |
c906108c | 1716 | { |
0f71a2f6 JM |
1717 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1718 | ||
c906108c SS |
1719 | tm_print_insn = print_insn_d10v; |
1720 | ||
1721 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1722 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1723 | ||
5f601589 AC |
1724 | deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"), |
1725 | "info registers"); | |
c906108c | 1726 | |
cff3e48b | 1727 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1728 | "Enable tracing of instruction execution."); |
1729 | ||
cff3e48b | 1730 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1731 | "Disable tracing of instruction execution."); |
1732 | ||
cff3e48b | 1733 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1734 | "Disassemble the trace buffer.\n\ |
1735 | Two optional arguments specify a range of trace buffer entries\n\ | |
1736 | as reported by info trace (NOT addresses!)."); | |
1737 | ||
cff3e48b | 1738 | add_info ("itrace", trace_info, |
c906108c SS |
1739 | "Display info about the trace data buffer."); |
1740 | ||
cff3e48b | 1741 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1742 | var_integer, (char *) &trace_display, |
1743 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1744 | &showlist); |
cff3e48b | 1745 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1746 | var_integer, (char *) &default_trace_show_source, |
1747 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1748 | &showlist); |
1749 | ||
c5aa993b | 1750 | } |