Commit | Line | Data |
---|---|---|
7b3fa778 MH |
1 | /* Target-dependent code for MItsubishi D10V, for GDB. |
2 | Copyright (C) 1996 Free Software Foundation, Inc. | |
3 | This file is part of GDB. | |
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2 of the License, or | |
7 | (at your option) any later version. | |
8 | This program is distributed in the hope that it will be useful, | |
9 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | GNU General Public License for more details. | |
12 | You should have received a copy of the GNU General Public License | |
13 | along with this program; if not, write to the Free Software | |
14 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
15 | ||
16 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
17 | ||
18 | #include "defs.h" | |
19 | #include "frame.h" | |
20 | #include "obstack.h" | |
21 | #include "symtab.h" | |
22 | #include "gdbtypes.h" | |
23 | #include "gdbcmd.h" | |
24 | #include "gdbcore.h" | |
81dc176f | 25 | #include "gdb_string.h" |
7b3fa778 MH |
26 | #include "value.h" |
27 | #include "inferior.h" | |
28 | #include "dis-asm.h" | |
3b1af95c MH |
29 | #include "symfile.h" |
30 | #include "objfiles.h" | |
7b3fa778 | 31 | |
e05bda9f | 32 | void d10v_frame_find_saved_regs PARAMS ((struct frame_info *fi, struct frame_saved_regs *fsr)); |
19414cdf | 33 | static void d10v_pop_dummy_frame PARAMS ((struct frame_info *fi)); |
e05bda9f MH |
34 | |
35 | /* Discard from the stack the innermost frame, | |
36 | restoring all saved registers. */ | |
37 | ||
7b3fa778 MH |
38 | void |
39 | d10v_pop_frame () | |
40 | { | |
e05bda9f | 41 | struct frame_info *frame = get_current_frame (); |
b70b03b0 | 42 | CORE_ADDR fp; |
e05bda9f MH |
43 | int regnum; |
44 | struct frame_saved_regs fsr; | |
45 | char raw_buffer[8]; | |
46 | ||
b70b03b0 | 47 | fp = FRAME_FP (frame); |
19414cdf MH |
48 | if (frame->dummy) |
49 | { | |
50 | d10v_pop_dummy_frame(frame); | |
51 | return; | |
52 | } | |
53 | ||
e05bda9f MH |
54 | /* fill out fsr with the address of where each */ |
55 | /* register was stored in the frame */ | |
56 | get_frame_saved_regs (frame, &fsr); | |
57 | ||
e05bda9f MH |
58 | /* now update the current registers with the old values */ |
59 | for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++) | |
60 | { | |
61 | if (fsr.regs[regnum]) | |
62 | { | |
81dc176f | 63 | read_memory (fsr.regs[regnum], raw_buffer, 8); |
e05bda9f MH |
64 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8); |
65 | } | |
66 | } | |
67 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
68 | { | |
69 | if (fsr.regs[regnum]) | |
70 | { | |
81dc176f | 71 | write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 2)); |
e05bda9f MH |
72 | } |
73 | } | |
74 | if (fsr.regs[PSW_REGNUM]) | |
75 | { | |
81dc176f | 76 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 2)); |
e05bda9f MH |
77 | } |
78 | ||
b70b03b0 MH |
79 | write_register (PC_REGNUM, read_register(13)); |
80 | write_register (SP_REGNUM, fp + frame->size); | |
81 | target_store_registers (-1); | |
e05bda9f MH |
82 | flush_cached_frames (); |
83 | } | |
84 | ||
85 | static int | |
86 | check_prologue (op) | |
87 | unsigned short op; | |
88 | { | |
89 | /* st rn, @-sp */ | |
90 | if ((op & 0x7E1F) == 0x6C1F) | |
91 | return 1; | |
92 | ||
93 | /* st2w rn, @-sp */ | |
94 | if ((op & 0x7E3F) == 0x6E1F) | |
95 | return 1; | |
96 | ||
97 | /* subi sp, n */ | |
98 | if ((op & 0x7FE1) == 0x01E1) | |
99 | return 1; | |
100 | ||
101 | /* mv r11, sp */ | |
102 | if (op == 0x417E) | |
103 | return 1; | |
104 | ||
105 | /* nop */ | |
106 | if (op == 0x5E00) | |
107 | return 1; | |
108 | ||
109 | /* st rn, @sp */ | |
110 | if ((op & 0x7E1F) == 0x681E) | |
111 | return 1; | |
112 | ||
113 | /* st2w rn, @sp */ | |
114 | if ((op & 0x7E3F) == 0x3A1E) | |
115 | return 1; | |
116 | ||
e05bda9f | 117 | return 0; |
7b3fa778 MH |
118 | } |
119 | ||
120 | CORE_ADDR | |
e05bda9f MH |
121 | d10v_skip_prologue (pc) |
122 | CORE_ADDR pc; | |
7b3fa778 | 123 | { |
e05bda9f MH |
124 | unsigned long op; |
125 | unsigned short op1, op2; | |
d716b33d MH |
126 | CORE_ADDR func_addr, func_end; |
127 | struct symtab_and_line sal; | |
e05bda9f | 128 | |
d716b33d MH |
129 | /* If we have line debugging information, then the end of the */ |
130 | /* prologue should the first assembly instruction of the first source line */ | |
131 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
132 | { | |
133 | sal = find_pc_line (func_addr, 0); | |
134 | if (sal.end < func_end) | |
135 | return sal.end; | |
136 | } | |
137 | ||
e05bda9f MH |
138 | if (target_read_memory (pc, (char *)&op, 4)) |
139 | return pc; /* Can't access it -- assume no prologue. */ | |
140 | ||
141 | while (1) | |
142 | { | |
81dc176f | 143 | op = (unsigned long)read_memory_integer (pc, 4); |
e05bda9f MH |
144 | if ((op & 0xC0000000) == 0xC0000000) |
145 | { | |
146 | /* long instruction */ | |
147 | if ( ((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ | |
148 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
149 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
150 | break; | |
151 | } | |
152 | else | |
153 | { | |
154 | /* short instructions */ | |
21260fe1 MH |
155 | if ((op & 0xC0000000) == 0x80000000) |
156 | { | |
157 | op2 = (op & 0x3FFF8000) >> 15; | |
158 | op1 = op & 0x7FFF; | |
159 | } | |
160 | else | |
161 | { | |
162 | op1 = (op & 0x3FFF8000) >> 15; | |
163 | op2 = op & 0x7FFF; | |
164 | } | |
165 | if (check_prologue(op1)) | |
166 | { | |
167 | if (!check_prologue(op2)) | |
168 | { | |
169 | /* if the previous opcode was really part of the prologue */ | |
170 | /* and not just a NOP, then we want to break after both instructions */ | |
171 | if (op1 != 0x5E00) | |
172 | pc += 4; | |
173 | break; | |
174 | } | |
175 | } | |
176 | else | |
e05bda9f MH |
177 | break; |
178 | } | |
179 | pc += 4; | |
180 | } | |
181 | return pc; | |
7b3fa778 | 182 | } |
19414cdf | 183 | |
e05bda9f MH |
184 | /* Given a GDB frame, determine the address of the calling function's frame. |
185 | This will be used to create a new GDB frame struct, and then | |
186 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
81dc176f | 187 | */ |
e05bda9f | 188 | |
7b3fa778 MH |
189 | CORE_ADDR |
190 | d10v_frame_chain (frame) | |
191 | struct frame_info *frame; | |
192 | { | |
e05bda9f | 193 | struct frame_saved_regs fsr; |
3b1af95c | 194 | |
e05bda9f | 195 | d10v_frame_find_saved_regs (frame, &fsr); |
3b1af95c | 196 | |
21260fe1 MH |
197 | if (frame->return_pc == IMEM_START) |
198 | return (CORE_ADDR)0; | |
199 | ||
3b1af95c MH |
200 | if (!fsr.regs[FP_REGNUM]) |
201 | { | |
21260fe1 MH |
202 | if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START) |
203 | return (CORE_ADDR)0; | |
204 | ||
205 | return fsr.regs[SP_REGNUM]; | |
3b1af95c | 206 | } |
21260fe1 MH |
207 | |
208 | if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM],2)) | |
209 | return (CORE_ADDR)0; | |
210 | ||
211 | return read_memory_unsigned_integer(fsr.regs[FP_REGNUM],2)| DMEM_START; | |
7b3fa778 MH |
212 | } |
213 | ||
21260fe1 | 214 | static int next_addr, uses_frame; |
e05bda9f MH |
215 | |
216 | static int | |
217 | prologue_find_regs (op, fsr, addr) | |
218 | unsigned short op; | |
219 | struct frame_saved_regs *fsr; | |
220 | CORE_ADDR addr; | |
221 | { | |
222 | int n; | |
223 | ||
224 | /* st rn, @-sp */ | |
225 | if ((op & 0x7E1F) == 0x6C1F) | |
226 | { | |
227 | n = (op & 0x1E0) >> 5; | |
228 | next_addr -= 2; | |
229 | fsr->regs[n] = next_addr; | |
230 | return 1; | |
231 | } | |
232 | ||
233 | /* st2w rn, @-sp */ | |
234 | else if ((op & 0x7E3F) == 0x6E1F) | |
235 | { | |
236 | n = (op & 0x1E0) >> 5; | |
237 | next_addr -= 4; | |
238 | fsr->regs[n] = next_addr; | |
239 | fsr->regs[n+1] = next_addr+2; | |
240 | return 1; | |
241 | } | |
242 | ||
243 | /* subi sp, n */ | |
244 | if ((op & 0x7FE1) == 0x01E1) | |
245 | { | |
246 | n = (op & 0x1E) >> 1; | |
247 | if (n == 0) | |
248 | n = 16; | |
249 | next_addr -= n; | |
250 | return 1; | |
251 | } | |
252 | ||
253 | /* mv r11, sp */ | |
254 | if (op == 0x417E) | |
21260fe1 MH |
255 | { |
256 | uses_frame = 1; | |
3b1af95c | 257 | return 1; |
21260fe1 | 258 | } |
e05bda9f MH |
259 | |
260 | /* nop */ | |
261 | if (op == 0x5E00) | |
262 | return 1; | |
263 | ||
264 | /* st rn, @sp */ | |
265 | if ((op & 0x7E1F) == 0x681E) | |
266 | { | |
267 | n = (op & 0x1E0) >> 5; | |
268 | fsr->regs[n] = next_addr; | |
269 | return 1; | |
270 | } | |
271 | ||
272 | /* st2w rn, @sp */ | |
273 | if ((op & 0x7E3F) == 0x3A1E) | |
274 | { | |
275 | n = (op & 0x1E0) >> 5; | |
276 | fsr->regs[n] = next_addr; | |
277 | fsr->regs[n+1] = next_addr+2; | |
278 | return 1; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
7b3fa778 MH |
284 | /* Put here the code to store, into a struct frame_saved_regs, the |
285 | addresses of the saved registers of frame described by FRAME_INFO. | |
286 | This includes special registers such as pc and fp saved in special | |
287 | ways in the stack frame. sp is even more special: the address we | |
288 | return for it IS the sp for the next frame. */ | |
289 | void | |
290 | d10v_frame_find_saved_regs (fi, fsr) | |
291 | struct frame_info *fi; | |
292 | struct frame_saved_regs *fsr; | |
e05bda9f MH |
293 | { |
294 | CORE_ADDR fp, pc; | |
295 | unsigned long op; | |
296 | unsigned short op1, op2; | |
297 | int i; | |
298 | ||
299 | fp = fi->frame; | |
300 | memset (fsr, 0, sizeof (*fsr)); | |
301 | next_addr = 0; | |
302 | ||
303 | pc = get_pc_function_start (fi->pc); | |
304 | ||
21260fe1 | 305 | uses_frame = 0; |
e05bda9f MH |
306 | while (1) |
307 | { | |
81dc176f | 308 | op = (unsigned long)read_memory_integer (pc, 4); |
e05bda9f MH |
309 | if ((op & 0xC0000000) == 0xC0000000) |
310 | { | |
311 | /* long instruction */ | |
312 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
313 | { | |
314 | /* add3 sp,sp,n */ | |
315 | short n = op & 0xFFFF; | |
316 | next_addr += n; | |
317 | } | |
318 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
319 | { | |
320 | /* st rn, @(offset,sp) */ | |
321 | short offset = op & 0xFFFF; | |
322 | short n = (op >> 20) & 0xF; | |
323 | fsr->regs[n] = next_addr + offset; | |
324 | } | |
325 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
326 | { | |
327 | /* st2w rn, @(offset,sp) */ | |
328 | short offset = op & 0xFFFF; | |
329 | short n = (op >> 20) & 0xF; | |
330 | fsr->regs[n] = next_addr + offset; | |
331 | fsr->regs[n+1] = next_addr + offset + 2; | |
332 | } | |
333 | else | |
334 | break; | |
335 | } | |
336 | else | |
337 | { | |
338 | /* short instructions */ | |
21260fe1 MH |
339 | if ((op & 0xC0000000) == 0x80000000) |
340 | { | |
341 | op2 = (op & 0x3FFF8000) >> 15; | |
342 | op1 = op & 0x7FFF; | |
343 | } | |
344 | else | |
345 | { | |
346 | op1 = (op & 0x3FFF8000) >> 15; | |
347 | op2 = op & 0x7FFF; | |
348 | } | |
e05bda9f MH |
349 | if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc)) |
350 | break; | |
351 | } | |
352 | pc += 4; | |
353 | } | |
354 | ||
355 | fi->size = -next_addr; | |
e05bda9f | 356 | |
21260fe1 MH |
357 | if (!(fp & 0xffff)) |
358 | fp = read_register(SP_REGNUM) | DMEM_START; | |
359 | ||
3b1af95c | 360 | for (i=0; i<NUM_REGS-1; i++) |
e05bda9f MH |
361 | if (fsr->regs[i]) |
362 | { | |
363 | fsr->regs[i] = fp - (next_addr - fsr->regs[i]); | |
e05bda9f | 364 | } |
81dc176f | 365 | |
21260fe1 MH |
366 | if (fsr->regs[LR_REGNUM]) |
367 | fi->return_pc = ((read_memory_unsigned_integer(fsr->regs[LR_REGNUM],2) - 1) << 2) | IMEM_START; | |
81dc176f | 368 | else |
21260fe1 MH |
369 | fi->return_pc = ((read_register(LR_REGNUM) - 1) << 2) | IMEM_START; |
370 | ||
3b1af95c | 371 | /* th SP is not normally (ever?) saved, but check anyway */ |
b70b03b0 | 372 | if (!fsr->regs[SP_REGNUM]) |
3b1af95c MH |
373 | { |
374 | /* if the FP was saved, that means the current FP is valid, */ | |
375 | /* otherwise, it isn't being used, so we use the SP instead */ | |
21260fe1 | 376 | if (uses_frame) |
3b1af95c MH |
377 | fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size; |
378 | else | |
21260fe1 MH |
379 | { |
380 | fsr->regs[SP_REGNUM] = fp + fi->size; | |
381 | fi->frameless = 1; | |
382 | fsr->regs[FP_REGNUM] = 0; | |
383 | } | |
3b1af95c | 384 | } |
7b3fa778 MH |
385 | } |
386 | ||
387 | void | |
388 | d10v_init_extra_frame_info (fromleaf, fi) | |
389 | int fromleaf; | |
390 | struct frame_info *fi; | |
391 | { | |
392 | struct frame_saved_regs dummy; | |
e05bda9f | 393 | |
21260fe1 | 394 | if (fi->next && ((fi->pc & 0xffff) == 0)) |
81dc176f MH |
395 | fi->pc = fi->next->return_pc; |
396 | ||
21260fe1 | 397 | d10v_frame_find_saved_regs (fi, &dummy); |
7b3fa778 MH |
398 | } |
399 | ||
400 | static void | |
401 | show_regs (args, from_tty) | |
402 | char *args; | |
403 | int from_tty; | |
404 | { | |
405 | long long num1, num2; | |
406 | printf_filtered ("PC=%04x (0x%x) PSW=%04x RPT_S=%04x RPT_E=%04x RPT_C=%04x\n", | |
21260fe1 | 407 | read_register (PC_REGNUM), (read_register (PC_REGNUM) << 2) + IMEM_START, |
7b3fa778 MH |
408 | read_register (PSW_REGNUM), |
409 | read_register (24), | |
410 | read_register (25), | |
411 | read_register (23)); | |
412 | printf_filtered ("R0-R7 %04x %04x %04x %04x %04x %04x %04x %04x\n", | |
413 | read_register (0), | |
414 | read_register (1), | |
415 | read_register (2), | |
416 | read_register (3), | |
417 | read_register (4), | |
418 | read_register (5), | |
419 | read_register (6), | |
420 | read_register (7)); | |
421 | printf_filtered ("R8-R15 %04x %04x %04x %04x %04x %04x %04x %04x\n", | |
422 | read_register (8), | |
423 | read_register (9), | |
424 | read_register (10), | |
425 | read_register (11), | |
426 | read_register (12), | |
427 | read_register (13), | |
428 | read_register (14), | |
429 | read_register (15)); | |
19414cdf MH |
430 | printf_filtered ("IMAP0 %04x IMAP1 %04x DMAP %04x\n", |
431 | read_register (IMAP0_REGNUM), | |
432 | read_register (IMAP1_REGNUM), | |
433 | read_register (DMAP_REGNUM)); | |
7b3fa778 MH |
434 | read_register_gen (A0_REGNUM, (char *)&num1); |
435 | read_register_gen (A0_REGNUM+1, (char *)&num2); | |
436 | printf_filtered ("A0-A1 %010llx %010llx\n",num1, num2); | |
81dc176f | 437 | } |
7b3fa778 MH |
438 | |
439 | void | |
440 | _initialize_d10v_tdep () | |
441 | { | |
7b3fa778 MH |
442 | tm_print_insn = print_insn_d10v; |
443 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
444 | } | |
445 | ||
19414cdf MH |
446 | static CORE_ADDR |
447 | d10v_xlate_addr (addr) | |
448 | int addr; | |
7b3fa778 | 449 | { |
19414cdf MH |
450 | int imap; |
451 | ||
452 | if (addr < 0x20000) | |
453 | imap = (int)read_register(IMAP0_REGNUM); | |
454 | else | |
455 | imap = (int)read_register(IMAP1_REGNUM); | |
7b3fa778 | 456 | |
19414cdf MH |
457 | if (imap & 0x1000) |
458 | return (CORE_ADDR)(addr + 0x1000000); | |
459 | return (CORE_ADDR)(addr + (imap & 0xff)*0x20000); | |
460 | } | |
461 | ||
462 | ||
463 | CORE_ADDR | |
464 | d10v_read_pc (pid) | |
465 | int pid; | |
466 | { | |
467 | int save_pid, retval; | |
7b3fa778 MH |
468 | |
469 | save_pid = inferior_pid; | |
470 | inferior_pid = pid; | |
19414cdf | 471 | retval = (int)read_register (PC_REGNUM); |
7b3fa778 | 472 | inferior_pid = save_pid; |
19414cdf | 473 | return d10v_xlate_addr(retval << 2); |
7b3fa778 MH |
474 | } |
475 | ||
476 | void | |
19414cdf | 477 | d10v_write_pc (val, pid) |
21260fe1 | 478 | CORE_ADDR val; |
7b3fa778 MH |
479 | int pid; |
480 | { | |
481 | int save_pid; | |
482 | ||
7b3fa778 MH |
483 | save_pid = inferior_pid; |
484 | inferior_pid = pid; | |
19414cdf | 485 | write_register (PC_REGNUM, (val & 0x3ffff) >> 2); |
7b3fa778 MH |
486 | inferior_pid = save_pid; |
487 | } | |
3b1af95c | 488 | |
19414cdf | 489 | CORE_ADDR |
21260fe1 | 490 | d10v_read_sp () |
19414cdf | 491 | { |
21260fe1 | 492 | return (read_register(SP_REGNUM) | DMEM_START); |
19414cdf MH |
493 | } |
494 | ||
495 | void | |
21260fe1 MH |
496 | d10v_write_sp (val) |
497 | CORE_ADDR val; | |
19414cdf | 498 | { |
21260fe1 | 499 | write_register (SP_REGNUM, (LONGEST)(val & 0xffff)); |
19414cdf | 500 | } |
3b1af95c | 501 | |
21260fe1 | 502 | CORE_ADDR |
3b1af95c MH |
503 | d10v_fix_call_dummy (dummyname, start_sp, fun, nargs, args, type, gcc_p) |
504 | char *dummyname; | |
505 | CORE_ADDR start_sp; | |
506 | CORE_ADDR fun; | |
507 | int nargs; | |
508 | value_ptr *args; | |
509 | struct type *type; | |
510 | int gcc_p; | |
511 | { | |
21260fe1 | 512 | int regnum; |
3b1af95c MH |
513 | CORE_ADDR sp; |
514 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
19414cdf | 515 | struct frame_info *frame = get_current_frame (); |
81a6f5b2 | 516 | frame->dummy = start_sp; |
21260fe1 MH |
517 | start_sp |= DMEM_START; |
518 | ||
3b1af95c | 519 | sp = start_sp; |
21260fe1 | 520 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
3b1af95c | 521 | { |
21260fe1 | 522 | sp -= REGISTER_RAW_SIZE(regnum); |
3b1af95c MH |
523 | store_address (buffer, REGISTER_RAW_SIZE(regnum), read_register(regnum)); |
524 | write_memory (sp, buffer, REGISTER_RAW_SIZE(regnum)); | |
3b1af95c | 525 | } |
21260fe1 | 526 | write_register (SP_REGNUM, (LONGEST)(sp & 0xffff)); |
19414cdf | 527 | /* now we need to load LR with the return address */ |
21260fe1 MH |
528 | write_register (LR_REGNUM, (LONGEST)(d10v_call_dummy_address() & 0xffff) >> 2); |
529 | return sp; | |
3b1af95c MH |
530 | } |
531 | ||
19414cdf MH |
532 | static void |
533 | d10v_pop_dummy_frame (fi) | |
534 | struct frame_info *fi; | |
535 | { | |
81a6f5b2 | 536 | CORE_ADDR sp = fi->dummy; |
21260fe1 MH |
537 | int regnum; |
538 | ||
81a6f5b2 | 539 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
19414cdf | 540 | { |
81a6f5b2 | 541 | sp -= REGISTER_RAW_SIZE(regnum); |
21260fe1 | 542 | write_register(regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE(regnum))); |
19414cdf | 543 | } |
81a6f5b2 | 544 | flush_cached_frames (); /* needed? */ |
19414cdf MH |
545 | } |
546 | ||
547 | ||
3b1af95c MH |
548 | CORE_ADDR |
549 | d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
550 | int nargs; | |
551 | value_ptr *args; | |
552 | CORE_ADDR sp; | |
553 | int struct_return; | |
554 | CORE_ADDR struct_addr; | |
555 | { | |
81a6f5b2 MH |
556 | int i, len, index=0, regnum=2; |
557 | char buffer[4], *contents; | |
19414cdf | 558 | LONGEST val; |
81a6f5b2 MH |
559 | CORE_ADDR ptrs[10]; |
560 | ||
561 | /* Pass 1. Put all large args on stack */ | |
3b1af95c MH |
562 | for (i = 0; i < nargs; i++) |
563 | { | |
564 | value_ptr arg = args[i]; | |
565 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
81a6f5b2 MH |
566 | len = TYPE_LENGTH (arg_type); |
567 | contents = VALUE_CONTENTS(arg); | |
568 | val = extract_signed_integer (contents, len); | |
569 | if (len > 4) | |
570 | { | |
571 | /* put on stack and pass pointers */ | |
572 | sp -= len; | |
573 | write_memory (sp, contents, len); | |
574 | ptrs[index++] = sp; | |
3b1af95c | 575 | } |
81a6f5b2 MH |
576 | } |
577 | ||
578 | index = 0; | |
579 | ||
580 | for (i = 0; i < nargs; i++) | |
581 | { | |
582 | value_ptr arg = args[i]; | |
583 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3b1af95c MH |
584 | len = TYPE_LENGTH (arg_type); |
585 | contents = VALUE_CONTENTS(arg); | |
19414cdf | 586 | val = extract_signed_integer (contents, len); |
81a6f5b2 MH |
587 | if (len > 4) |
588 | { | |
589 | /* use a pointer to previously saved data */ | |
590 | if (regnum < 6) | |
591 | write_register (regnum++, ptrs[index++]); | |
592 | else | |
593 | { | |
594 | /* no more registers available. put it on the stack */ | |
595 | sp -= 2; | |
596 | store_address (buffer, 2, ptrs[index++]); | |
597 | write_memory (sp, buffer, 2); | |
598 | } | |
599 | } | |
600 | else | |
601 | { | |
602 | if (regnum < 6 ) | |
603 | { | |
604 | if (len == 4) | |
605 | write_register (regnum++, val>>16); | |
606 | write_register (regnum++, val & 0xffff); | |
607 | } | |
608 | else | |
609 | { | |
610 | sp -= len; | |
611 | store_address (buffer, len, val); | |
612 | write_memory (sp, buffer, len); | |
613 | } | |
614 | } | |
3b1af95c | 615 | } |
21260fe1 | 616 | return sp; |
3b1af95c MH |
617 | } |
618 | ||
19414cdf | 619 | |
81a6f5b2 MH |
620 | /* pick an out-of-the-way place to set the return value */ |
621 | /* for an inferior function call. The link register is set to this */ | |
622 | /* value and a momentary breakpoint is set there. When the breakpoint */ | |
623 | /* is hit, the dummy frame is popped and the previous environment is */ | |
624 | /* restored. */ | |
625 | ||
3b1af95c MH |
626 | CORE_ADDR |
627 | d10v_call_dummy_address () | |
628 | { | |
19414cdf | 629 | CORE_ADDR entry; |
3b1af95c MH |
630 | struct minimal_symbol *sym; |
631 | ||
632 | entry = entry_point_address (); | |
633 | ||
634 | if (entry != 0) | |
19414cdf | 635 | return entry; |
3b1af95c MH |
636 | |
637 | sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile); | |
638 | ||
639 | if (!sym || MSYMBOL_TYPE (sym) != mst_text) | |
19414cdf | 640 | return 0; |
3b1af95c | 641 | else |
19414cdf | 642 | return SYMBOL_VALUE_ADDRESS (sym); |
3b1af95c MH |
643 | } |
644 | ||
645 | /* Given a return value in `regbuf' with a type `valtype', | |
646 | extract and copy its value into `valbuf'. */ | |
647 | ||
648 | void | |
649 | d10v_extract_return_value (valtype, regbuf, valbuf) | |
650 | struct type *valtype; | |
651 | char regbuf[REGISTER_BYTES]; | |
652 | char *valbuf; | |
653 | { | |
81a6f5b2 | 654 | memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype)); |
3b1af95c | 655 | } |