Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
7f6104a9 | 27 | #include "frame-unwind.h" |
270cb5d6 | 28 | #include "frame-base.h" |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdb_string.h" | |
34 | #include "value.h" | |
35 | #include "inferior.h" | |
c5aa993b | 36 | #include "dis-asm.h" |
c906108c SS |
37 | #include "symfile.h" |
38 | #include "objfiles.h" | |
104c1213 | 39 | #include "language.h" |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
e8933a55 | 42 | #include "remote.h" |
f0d4cc9e | 43 | #include "floatformat.h" |
b91b96f4 | 44 | #include "gdb/sim-d10v.h" |
8238d0bf | 45 | #include "sim-regno.h" |
4ce44c66 | 46 | |
fa1fd571 AC |
47 | #include "gdb_assert.h" |
48 | ||
4ce44c66 JM |
49 | struct gdbarch_tdep |
50 | { | |
51 | int a0_regnum; | |
52 | int nr_dmap_regs; | |
53 | unsigned long (*dmap_register) (int nr); | |
54 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
55 | }; |
56 | ||
57 | /* These are the addresses the D10V-EVA board maps data and | |
58 | instruction memory to. */ | |
cce74817 | 59 | |
78eac43e MS |
60 | enum memspace { |
61 | DMEM_START = 0x2000000, | |
62 | IMEM_START = 0x1000000, | |
63 | STACK_START = 0x200bffe | |
64 | }; | |
cce74817 | 65 | |
4ce44c66 JM |
66 | /* d10v register names. */ |
67 | ||
68 | enum | |
69 | { | |
70 | R0_REGNUM = 0, | |
78eac43e | 71 | R3_REGNUM = 3, |
6c2b5168 | 72 | D10V_FP_REGNUM = 11, |
4ce44c66 | 73 | LR_REGNUM = 13, |
f75493ed | 74 | D10V_SP_REGNUM = 15, |
4ce44c66 | 75 | PSW_REGNUM = 16, |
78eac43e | 76 | _PC_REGNUM = 18, |
4ce44c66 | 77 | NR_IMAP_REGS = 2, |
78eac43e MS |
78 | NR_A_REGS = 2, |
79 | TS2_NUM_REGS = 37, | |
80 | TS3_NUM_REGS = 42, | |
81 | /* d10v calling convention. */ | |
82 | ARG1_REGNUM = R0_REGNUM, | |
83 | ARGN_REGNUM = R3_REGNUM, | |
84 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 85 | }; |
78eac43e | 86 | |
f75493ed AC |
87 | int |
88 | nr_dmap_regs (struct gdbarch *gdbarch) | |
89 | { | |
90 | return gdbarch_tdep (gdbarch)->nr_dmap_regs; | |
91 | } | |
92 | ||
93 | int | |
94 | a0_regnum (struct gdbarch *gdbarch) | |
95 | { | |
96 | return gdbarch_tdep (gdbarch)->a0_regnum; | |
97 | } | |
4ce44c66 | 98 | |
392a587b JM |
99 | /* Local functions */ |
100 | ||
a14ed312 | 101 | extern void _initialize_d10v_tdep (void); |
392a587b | 102 | |
095a4c96 EZ |
103 | static CORE_ADDR d10v_read_sp (void); |
104 | ||
105 | static CORE_ADDR d10v_read_fp (void); | |
106 | ||
a14ed312 | 107 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 108 | |
a14ed312 | 109 | static void d10v_eva_get_trace_data (void); |
c906108c | 110 | |
23964bcd | 111 | static CORE_ADDR |
489137c0 AC |
112 | d10v_stack_align (CORE_ADDR len) |
113 | { | |
114 | return (len + 1) & ~1; | |
115 | } | |
c906108c SS |
116 | |
117 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
118 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
119 | and TYPE is the type (which is known to be struct, union or array). | |
120 | ||
121 | The d10v returns anything less than 8 bytes in size in | |
122 | registers. */ | |
123 | ||
f5e1cf12 | 124 | static int |
fba45db2 | 125 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 126 | { |
02da6206 JSC |
127 | long alignment; |
128 | int i; | |
129 | /* The d10v only passes a struct in a register when that structure | |
130 | has an alignment that matches the size of a register. */ | |
131 | /* If the structure doesn't fit in 4 registers, put it on the | |
132 | stack. */ | |
133 | if (TYPE_LENGTH (type) > 8) | |
134 | return 1; | |
135 | /* If the struct contains only one field, don't put it on the stack | |
136 | - gcc can fit it in one or more registers. */ | |
137 | if (TYPE_NFIELDS (type) == 1) | |
138 | return 0; | |
139 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
140 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
141 | { | |
142 | /* If the alignment changes, just assume it goes on the | |
143 | stack. */ | |
144 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
145 | return 1; | |
146 | } | |
147 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
148 | don't put it on the stack. */ | |
149 | if (alignment == 2 || alignment == 4) | |
150 | return 0; | |
151 | return 1; | |
c906108c SS |
152 | } |
153 | ||
154 | ||
f4f9705a | 155 | static const unsigned char * |
fba45db2 | 156 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 157 | { |
c5aa993b JM |
158 | static unsigned char breakpoint[] = |
159 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
160 | *lenptr = sizeof (breakpoint); |
161 | return breakpoint; | |
162 | } | |
163 | ||
4ce44c66 JM |
164 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
165 | when the reg_nr isn't valid. */ | |
166 | ||
167 | enum ts2_regnums | |
168 | { | |
169 | TS2_IMAP0_REGNUM = 32, | |
170 | TS2_DMAP_REGNUM = 34, | |
171 | TS2_NR_DMAP_REGS = 1, | |
172 | TS2_A0_REGNUM = 35 | |
173 | }; | |
174 | ||
fa88f677 | 175 | static const char * |
4ce44c66 | 176 | d10v_ts2_register_name (int reg_nr) |
392a587b | 177 | { |
c5aa993b JM |
178 | static char *register_names[] = |
179 | { | |
180 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
181 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
182 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
183 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
184 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
185 | }; |
186 | if (reg_nr < 0) | |
187 | return NULL; | |
188 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
189 | return NULL; | |
c5aa993b | 190 | return register_names[reg_nr]; |
392a587b JM |
191 | } |
192 | ||
4ce44c66 JM |
193 | enum ts3_regnums |
194 | { | |
195 | TS3_IMAP0_REGNUM = 36, | |
196 | TS3_DMAP0_REGNUM = 38, | |
197 | TS3_NR_DMAP_REGS = 4, | |
198 | TS3_A0_REGNUM = 32 | |
199 | }; | |
200 | ||
fa88f677 | 201 | static const char * |
4ce44c66 JM |
202 | d10v_ts3_register_name (int reg_nr) |
203 | { | |
204 | static char *register_names[] = | |
205 | { | |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
207 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
208 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
209 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
210 | "a0", "a1", | |
211 | "spi", "spu", | |
212 | "imap0", "imap1", | |
213 | "dmap0", "dmap1", "dmap2", "dmap3" | |
214 | }; | |
215 | if (reg_nr < 0) | |
216 | return NULL; | |
217 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
218 | return NULL; | |
219 | return register_names[reg_nr]; | |
220 | } | |
221 | ||
bf93dfed JB |
222 | /* Access the DMAP/IMAP registers in a target independent way. |
223 | ||
224 | Divide the D10V's 64k data space into four 16k segments: | |
225 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
226 | 0xc000 -- 0xffff. | |
227 | ||
228 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
229 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
230 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
231 | unified memory or instruction memory, under the control of the | |
232 | single DMAP register. | |
233 | ||
234 | On the TS3, there are four DMAP registers, each of which controls | |
235 | one of the segments. */ | |
4ce44c66 JM |
236 | |
237 | static unsigned long | |
238 | d10v_ts2_dmap_register (int reg_nr) | |
239 | { | |
240 | switch (reg_nr) | |
241 | { | |
242 | case 0: | |
243 | case 1: | |
244 | return 0x2000; | |
245 | case 2: | |
246 | return read_register (TS2_DMAP_REGNUM); | |
247 | default: | |
248 | return 0; | |
249 | } | |
250 | } | |
251 | ||
252 | static unsigned long | |
253 | d10v_ts3_dmap_register (int reg_nr) | |
254 | { | |
255 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
256 | } | |
257 | ||
258 | static unsigned long | |
259 | d10v_dmap_register (int reg_nr) | |
260 | { | |
261 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
262 | } | |
263 | ||
264 | static unsigned long | |
265 | d10v_ts2_imap_register (int reg_nr) | |
266 | { | |
267 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
268 | } | |
269 | ||
270 | static unsigned long | |
271 | d10v_ts3_imap_register (int reg_nr) | |
272 | { | |
273 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
274 | } | |
275 | ||
276 | static unsigned long | |
277 | d10v_imap_register (int reg_nr) | |
278 | { | |
279 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
280 | } | |
281 | ||
282 | /* MAP GDB's internal register numbering (determined by the layout fo | |
283 | the REGISTER_BYTE array) onto the simulator's register | |
284 | numbering. */ | |
285 | ||
286 | static int | |
287 | d10v_ts2_register_sim_regno (int nr) | |
288 | { | |
e8933a55 AC |
289 | /* Only makes sense to supply raw registers. */ |
290 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
291 | if (nr >= TS2_IMAP0_REGNUM |
292 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
293 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
294 | if (nr == TS2_DMAP_REGNUM) | |
295 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
296 | if (nr >= TS2_A0_REGNUM | |
297 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
298 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
299 | return nr; | |
300 | } | |
301 | ||
302 | static int | |
303 | d10v_ts3_register_sim_regno (int nr) | |
304 | { | |
e8933a55 AC |
305 | /* Only makes sense to supply raw registers. */ |
306 | gdb_assert (nr >= 0 && nr < NUM_REGS); | |
4ce44c66 JM |
307 | if (nr >= TS3_IMAP0_REGNUM |
308 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
309 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
310 | if (nr >= TS3_DMAP0_REGNUM | |
311 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
312 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
313 | if (nr >= TS3_A0_REGNUM | |
314 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
315 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
316 | return nr; | |
317 | } | |
318 | ||
392a587b JM |
319 | /* Return the GDB type object for the "standard" data type |
320 | of data in register N. */ | |
321 | ||
f5e1cf12 | 322 | static struct type * |
35cac7cf | 323 | d10v_register_type (struct gdbarch *gdbarch, int reg_nr) |
392a587b | 324 | { |
75af7f68 JB |
325 | if (reg_nr == PC_REGNUM) |
326 | return builtin_type_void_func_ptr; | |
f75493ed | 327 | if (reg_nr == D10V_SP_REGNUM || reg_nr == D10V_FP_REGNUM) |
095a4c96 | 328 | return builtin_type_void_data_ptr; |
f75493ed AC |
329 | else if (reg_nr >= a0_regnum (gdbarch) |
330 | && reg_nr < (a0_regnum (gdbarch) + NR_A_REGS)) | |
4ce44c66 | 331 | return builtin_type_int64; |
392a587b | 332 | else |
4ce44c66 | 333 | return builtin_type_int16; |
392a587b JM |
334 | } |
335 | ||
f5e1cf12 | 336 | static int |
fba45db2 | 337 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
338 | { |
339 | return (((x) & 0x3000000) == DMEM_START); | |
340 | } | |
341 | ||
f5e1cf12 | 342 | static int |
fba45db2 | 343 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
344 | { |
345 | return (((x) & 0x3000000) == IMEM_START); | |
346 | } | |
347 | ||
169a7369 MS |
348 | static CORE_ADDR |
349 | d10v_make_daddr (CORE_ADDR x) | |
350 | { | |
351 | return ((x) | DMEM_START); | |
352 | } | |
353 | ||
354 | static CORE_ADDR | |
355 | d10v_make_iaddr (CORE_ADDR x) | |
356 | { | |
357 | if (d10v_iaddr_p (x)) | |
358 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
359 | else | |
360 | return (((x) << 2) | IMEM_START); | |
361 | } | |
392a587b | 362 | |
f5e1cf12 | 363 | static CORE_ADDR |
fba45db2 | 364 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
365 | { |
366 | return (((x) >> 2) & 0xffff); | |
367 | } | |
368 | ||
f5e1cf12 | 369 | static CORE_ADDR |
fba45db2 | 370 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
371 | { |
372 | return ((x) & 0xffff); | |
373 | } | |
374 | ||
75af7f68 JB |
375 | static void |
376 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
377 | { | |
378 | /* Is it a code address? */ | |
379 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
380 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
381 | { | |
75af7f68 JB |
382 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
383 | d10v_convert_iaddr_to_raw (addr)); | |
384 | } | |
385 | else | |
386 | { | |
387 | /* Strip off any upper segment bits. */ | |
388 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
389 | d10v_convert_daddr_to_raw (addr)); | |
390 | } | |
391 | } | |
392 | ||
393 | static CORE_ADDR | |
66140c26 | 394 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 | 395 | { |
f75493ed | 396 | CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH (type)); |
75af7f68 JB |
397 | /* Is it a code address? */ |
398 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
399 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
400 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
401 | return d10v_make_iaddr (addr); |
402 | else | |
403 | return d10v_make_daddr (addr); | |
404 | } | |
405 | ||
095a4c96 EZ |
406 | /* Don't do anything if we have an integer, this way users can type 'x |
407 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
408 | to the correct space are taken care of in the pointer_to_address | |
409 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
410 | static CORE_ADDR |
411 | d10v_integer_to_address (struct type *type, void *buf) | |
412 | { | |
413 | LONGEST val; | |
414 | val = unpack_long (type, buf); | |
095a4c96 | 415 | return val; |
fc0c74b1 | 416 | } |
75af7f68 | 417 | |
392a587b JM |
418 | /* Write into appropriate registers a function return value |
419 | of type TYPE, given in virtual format. | |
420 | ||
421 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
422 | ||
f5e1cf12 | 423 | static void |
fa1fd571 AC |
424 | d10v_store_return_value (struct type *type, struct regcache *regcache, |
425 | const void *valbuf) | |
392a587b | 426 | { |
fa1fd571 AC |
427 | /* Only char return values need to be shifted right within the first |
428 | regnum. */ | |
3d79a47c MS |
429 | if (TYPE_LENGTH (type) == 1 |
430 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
431 | { | |
fa1fd571 AC |
432 | bfd_byte tmp[2]; |
433 | tmp[1] = *(bfd_byte *)valbuf; | |
434 | regcache_cooked_write (regcache, RET1_REGNUM, tmp); | |
3d79a47c MS |
435 | } |
436 | else | |
fa1fd571 AC |
437 | { |
438 | int reg; | |
439 | /* A structure is never more than 8 bytes long. See | |
440 | use_struct_convention(). */ | |
441 | gdb_assert (TYPE_LENGTH (type) <= 8); | |
442 | /* Write out most registers, stop loop before trying to write | |
443 | out any dangling byte at the end of the buffer. */ | |
444 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) | |
445 | { | |
446 | regcache_cooked_write (regcache, RET1_REGNUM + reg, | |
447 | (bfd_byte *) valbuf + reg * 2); | |
448 | } | |
449 | /* Write out any dangling byte at the end of the buffer. */ | |
450 | if ((reg * 2) + 1 == TYPE_LENGTH (type)) | |
451 | regcache_cooked_write_part (regcache, reg, 0, 1, | |
452 | (bfd_byte *) valbuf + reg * 2); | |
453 | } | |
392a587b JM |
454 | } |
455 | ||
456 | /* Extract from an array REGBUF containing the (raw) register state | |
457 | the address in which a function should return its structure value, | |
458 | as a CORE_ADDR (or an expression that can be used as one). */ | |
459 | ||
f5e1cf12 | 460 | static CORE_ADDR |
fa1fd571 | 461 | d10v_extract_struct_value_address (struct regcache *regcache) |
392a587b | 462 | { |
fa1fd571 AC |
463 | ULONGEST addr; |
464 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
465 | return (addr | DMEM_START); | |
392a587b JM |
466 | } |
467 | ||
c5aa993b | 468 | static int |
fba45db2 | 469 | check_prologue (unsigned short op) |
c906108c SS |
470 | { |
471 | /* st rn, @-sp */ | |
472 | if ((op & 0x7E1F) == 0x6C1F) | |
473 | return 1; | |
474 | ||
475 | /* st2w rn, @-sp */ | |
476 | if ((op & 0x7E3F) == 0x6E1F) | |
477 | return 1; | |
478 | ||
479 | /* subi sp, n */ | |
480 | if ((op & 0x7FE1) == 0x01E1) | |
481 | return 1; | |
482 | ||
483 | /* mv r11, sp */ | |
484 | if (op == 0x417E) | |
485 | return 1; | |
486 | ||
487 | /* nop */ | |
488 | if (op == 0x5E00) | |
489 | return 1; | |
490 | ||
491 | /* st rn, @sp */ | |
492 | if ((op & 0x7E1F) == 0x681E) | |
493 | return 1; | |
494 | ||
495 | /* st2w rn, @sp */ | |
c5aa993b JM |
496 | if ((op & 0x7E3F) == 0x3A1E) |
497 | return 1; | |
c906108c SS |
498 | |
499 | return 0; | |
500 | } | |
501 | ||
f5e1cf12 | 502 | static CORE_ADDR |
fba45db2 | 503 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
504 | { |
505 | unsigned long op; | |
506 | unsigned short op1, op2; | |
507 | CORE_ADDR func_addr, func_end; | |
508 | struct symtab_and_line sal; | |
509 | ||
510 | /* If we have line debugging information, then the end of the */ | |
511 | /* prologue should the first assembly instruction of the first source line */ | |
512 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
513 | { | |
514 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 515 | if (sal.end && sal.end < func_end) |
c906108c SS |
516 | return sal.end; |
517 | } | |
c5aa993b JM |
518 | |
519 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
520 | return pc; /* Can't access it -- assume no prologue. */ |
521 | ||
522 | while (1) | |
523 | { | |
c5aa993b | 524 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
525 | if ((op & 0xC0000000) == 0xC0000000) |
526 | { | |
527 | /* long instruction */ | |
c5aa993b JM |
528 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
529 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
530 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
531 | break; |
532 | } | |
533 | else | |
534 | { | |
535 | /* short instructions */ | |
536 | if ((op & 0xC0000000) == 0x80000000) | |
537 | { | |
538 | op2 = (op & 0x3FFF8000) >> 15; | |
539 | op1 = op & 0x7FFF; | |
c5aa993b JM |
540 | } |
541 | else | |
c906108c SS |
542 | { |
543 | op1 = (op & 0x3FFF8000) >> 15; | |
544 | op2 = op & 0x7FFF; | |
545 | } | |
c5aa993b | 546 | if (check_prologue (op1)) |
c906108c | 547 | { |
c5aa993b | 548 | if (!check_prologue (op2)) |
c906108c SS |
549 | { |
550 | /* if the previous opcode was really part of the prologue */ | |
551 | /* and not just a NOP, then we want to break after both instructions */ | |
552 | if (op1 != 0x5E00) | |
553 | pc += 4; | |
554 | break; | |
555 | } | |
556 | } | |
557 | else | |
558 | break; | |
559 | } | |
560 | pc += 4; | |
561 | } | |
562 | return pc; | |
563 | } | |
564 | ||
7f6104a9 | 565 | struct d10v_unwind_cache |
c906108c | 566 | { |
7f6104a9 | 567 | CORE_ADDR return_pc; |
270cb5d6 AC |
568 | /* The previous frame's inner most stack address. Used as this |
569 | frame ID's stack_addr. */ | |
570 | CORE_ADDR prev_sp; | |
571 | /* The frame's base, optionally used by the high-level debug info. */ | |
ceea5145 | 572 | CORE_ADDR base; |
7f6104a9 AC |
573 | int size; |
574 | CORE_ADDR *saved_regs; | |
0d843116 AC |
575 | /* How far the SP and r11 (FP) have been offset from the start of |
576 | the stack frame (as defined by the previous frame's stack | |
577 | pointer). */ | |
578 | LONGEST sp_offset; | |
579 | LONGEST r11_offset; | |
7f6104a9 AC |
580 | int uses_frame; |
581 | void **regs; | |
582 | }; | |
c906108c | 583 | |
c5aa993b | 584 | static int |
7f6104a9 AC |
585 | prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, |
586 | CORE_ADDR addr) | |
c906108c SS |
587 | { |
588 | int n; | |
589 | ||
590 | /* st rn, @-sp */ | |
591 | if ((op & 0x7E1F) == 0x6C1F) | |
592 | { | |
593 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
594 | info->sp_offset -= 2; |
595 | info->saved_regs[n] = info->sp_offset; | |
c906108c SS |
596 | return 1; |
597 | } | |
598 | ||
599 | /* st2w rn, @-sp */ | |
600 | else if ((op & 0x7E3F) == 0x6E1F) | |
601 | { | |
602 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
603 | info->sp_offset -= 4; |
604 | info->saved_regs[n] = info->sp_offset; | |
605 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
606 | return 1; |
607 | } | |
608 | ||
609 | /* subi sp, n */ | |
610 | if ((op & 0x7FE1) == 0x01E1) | |
611 | { | |
612 | n = (op & 0x1E) >> 1; | |
613 | if (n == 0) | |
614 | n = 16; | |
0d843116 | 615 | info->sp_offset -= n; |
c906108c SS |
616 | return 1; |
617 | } | |
618 | ||
619 | /* mv r11, sp */ | |
620 | if (op == 0x417E) | |
621 | { | |
7f6104a9 | 622 | info->uses_frame = 1; |
0d843116 AC |
623 | info->r11_offset = info->sp_offset; |
624 | return 1; | |
625 | } | |
626 | ||
627 | /* st rn, @r11 */ | |
628 | if ((op & 0x7E1F) == 0x6816) | |
629 | { | |
630 | n = (op & 0x1E0) >> 5; | |
631 | info->saved_regs[n] = info->r11_offset; | |
c906108c SS |
632 | return 1; |
633 | } | |
634 | ||
635 | /* nop */ | |
636 | if (op == 0x5E00) | |
637 | return 1; | |
638 | ||
639 | /* st rn, @sp */ | |
640 | if ((op & 0x7E1F) == 0x681E) | |
641 | { | |
642 | n = (op & 0x1E0) >> 5; | |
0d843116 | 643 | info->saved_regs[n] = info->sp_offset; |
c906108c SS |
644 | return 1; |
645 | } | |
646 | ||
647 | /* st2w rn, @sp */ | |
648 | if ((op & 0x7E3F) == 0x3A1E) | |
649 | { | |
650 | n = (op & 0x1E0) >> 5; | |
0d843116 AC |
651 | info->saved_regs[n] = info->sp_offset; |
652 | info->saved_regs[n + 1] = info->sp_offset + 2; | |
c906108c SS |
653 | return 1; |
654 | } | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
cce74817 JM |
659 | /* Put here the code to store, into fi->saved_regs, the addresses of |
660 | the saved registers of frame described by FRAME_INFO. This | |
661 | includes special registers such as pc and fp saved in special ways | |
662 | in the stack frame. sp is even more special: the address we return | |
663 | for it IS the sp for the next frame. */ | |
664 | ||
7f6104a9 | 665 | struct d10v_unwind_cache * |
6dc42492 AC |
666 | d10v_frame_unwind_cache (struct frame_info *next_frame, |
667 | void **this_prologue_cache) | |
c906108c | 668 | { |
ceea5145 AC |
669 | CORE_ADDR pc; |
670 | ULONGEST prev_sp; | |
671 | ULONGEST this_base; | |
c906108c SS |
672 | unsigned long op; |
673 | unsigned short op1, op2; | |
674 | int i; | |
7f6104a9 AC |
675 | struct d10v_unwind_cache *info; |
676 | ||
6dc42492 AC |
677 | if ((*this_prologue_cache)) |
678 | return (*this_prologue_cache); | |
7f6104a9 AC |
679 | |
680 | info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); | |
6dc42492 | 681 | (*this_prologue_cache) = info; |
f75493ed | 682 | info->saved_regs = FRAME_OBSTACK_CALLOC (NUM_REGS, CORE_ADDR); |
7f6104a9 | 683 | |
7f6104a9 AC |
684 | info->size = 0; |
685 | info->return_pc = 0; | |
0d843116 | 686 | info->sp_offset = 0; |
c906108c | 687 | |
7f6104a9 | 688 | info->uses_frame = 0; |
be41e9f4 | 689 | for (pc = frame_func_unwind (next_frame); |
81f8a206 | 690 | pc > 0 && pc < frame_pc_unwind (next_frame); |
270cb5d6 | 691 | pc += 4) |
c906108c | 692 | { |
c5aa993b | 693 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
694 | if ((op & 0xC0000000) == 0xC0000000) |
695 | { | |
696 | /* long instruction */ | |
697 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
698 | { | |
699 | /* add3 sp,sp,n */ | |
700 | short n = op & 0xFFFF; | |
0d843116 | 701 | info->sp_offset += n; |
c906108c SS |
702 | } |
703 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
704 | { | |
705 | /* st rn, @(offset,sp) */ | |
706 | short offset = op & 0xFFFF; | |
707 | short n = (op >> 20) & 0xF; | |
0d843116 | 708 | info->saved_regs[n] = info->sp_offset + offset; |
c906108c SS |
709 | } |
710 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
711 | { | |
712 | /* st2w rn, @(offset,sp) */ | |
713 | short offset = op & 0xFFFF; | |
714 | short n = (op >> 20) & 0xF; | |
0d843116 AC |
715 | info->saved_regs[n] = info->sp_offset + offset; |
716 | info->saved_regs[n + 1] = info->sp_offset + offset + 2; | |
c906108c SS |
717 | } |
718 | else | |
719 | break; | |
720 | } | |
721 | else | |
722 | { | |
723 | /* short instructions */ | |
724 | if ((op & 0xC0000000) == 0x80000000) | |
725 | { | |
726 | op2 = (op & 0x3FFF8000) >> 15; | |
727 | op1 = op & 0x7FFF; | |
c5aa993b JM |
728 | } |
729 | else | |
c906108c SS |
730 | { |
731 | op1 = (op & 0x3FFF8000) >> 15; | |
732 | op2 = op & 0x7FFF; | |
733 | } | |
7f6104a9 AC |
734 | if (!prologue_find_regs (info, op1, pc) |
735 | || !prologue_find_regs (info, op2, pc)) | |
c906108c SS |
736 | break; |
737 | } | |
c906108c | 738 | } |
c5aa993b | 739 | |
0d843116 | 740 | info->size = -info->sp_offset; |
c906108c | 741 | |
ceea5145 AC |
742 | /* Compute the frame's base, and the previous frame's SP. */ |
743 | if (info->uses_frame) | |
744 | { | |
745 | /* The SP was moved to the FP. This indicates that a new frame | |
746 | was created. Get THIS frame's FP value by unwinding it from | |
747 | the next frame. */ | |
6c2b5168 | 748 | frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); |
ceea5145 AC |
749 | /* The FP points at the last saved register. Adjust the FP back |
750 | to before the first saved register giving the SP. */ | |
751 | prev_sp = this_base + info->size; | |
752 | } | |
f75493ed | 753 | else if (info->saved_regs[D10V_SP_REGNUM]) |
ceea5145 AC |
754 | { |
755 | /* The SP was saved (which is very unusual), the frame base is | |
756 | just the PREV's frame's TOP-OF-STACK. */ | |
f75493ed | 757 | this_base = read_memory_unsigned_integer (info->saved_regs[D10V_SP_REGNUM], |
ceea5145 | 758 | register_size (current_gdbarch, |
f75493ed | 759 | D10V_SP_REGNUM)); |
ceea5145 AC |
760 | prev_sp = this_base; |
761 | } | |
762 | else | |
763 | { | |
764 | /* Assume that the FP is this frame's SP but with that pushed | |
765 | stack space added back. */ | |
f75493ed | 766 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &this_base); |
ceea5145 AC |
767 | prev_sp = this_base + info->size; |
768 | } | |
769 | ||
770 | info->base = d10v_make_daddr (this_base); | |
270cb5d6 | 771 | info->prev_sp = d10v_make_daddr (prev_sp); |
c906108c | 772 | |
ceea5145 AC |
773 | /* Adjust all the saved registers so that they contain addresses and |
774 | not offsets. */ | |
c5aa993b | 775 | for (i = 0; i < NUM_REGS - 1; i++) |
7f6104a9 | 776 | if (info->saved_regs[i]) |
c906108c | 777 | { |
270cb5d6 | 778 | info->saved_regs[i] = (info->prev_sp + info->saved_regs[i]); |
c906108c SS |
779 | } |
780 | ||
7f6104a9 | 781 | if (info->saved_regs[LR_REGNUM]) |
c906108c | 782 | { |
78eac43e | 783 | CORE_ADDR return_pc |
7f6104a9 | 784 | = read_memory_unsigned_integer (info->saved_regs[LR_REGNUM], |
08a617da | 785 | register_size (current_gdbarch, LR_REGNUM)); |
7f6104a9 | 786 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
787 | } |
788 | else | |
789 | { | |
7f6104a9 | 790 | ULONGEST return_pc; |
6dc42492 | 791 | frame_unwind_unsigned_register (next_frame, LR_REGNUM, &return_pc); |
7f6104a9 | 792 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c | 793 | } |
c5aa993b | 794 | |
f75493ed | 795 | /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the |
ceea5145 | 796 | previous frame's SP value is saved. */ |
f75493ed | 797 | info->saved_regs[D10V_SP_REGNUM] = info->prev_sp; |
c906108c | 798 | |
7f6104a9 | 799 | return info; |
c906108c SS |
800 | } |
801 | ||
802 | static void | |
5f601589 AC |
803 | d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
804 | struct frame_info *frame, int regnum, int all) | |
c906108c | 805 | { |
5f601589 | 806 | if (regnum >= 0) |
4ce44c66 | 807 | { |
5f601589 AC |
808 | default_print_registers_info (gdbarch, file, frame, regnum, all); |
809 | return; | |
4ce44c66 | 810 | } |
5f601589 AC |
811 | |
812 | { | |
813 | ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; | |
814 | frame_read_unsigned_register (frame, PC_REGNUM, &pc); | |
815 | frame_read_unsigned_register (frame, PSW_REGNUM, &psw); | |
816 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s); | |
817 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e); | |
818 | frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c); | |
819 | fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", | |
820 | (long) pc, (long) d10v_make_iaddr (pc), (long) psw, | |
821 | (long) rpt_s, (long) rpt_e, (long) rpt_c); | |
822 | } | |
823 | ||
824 | { | |
825 | int group; | |
826 | for (group = 0; group < 16; group += 8) | |
827 | { | |
828 | int r; | |
829 | fprintf_filtered (file, "R%d-R%-2d", group, group + 7); | |
830 | for (r = group; r < group + 8; r++) | |
831 | { | |
832 | ULONGEST tmp; | |
833 | frame_read_unsigned_register (frame, r, &tmp); | |
834 | fprintf_filtered (file, " %04lx", (long) tmp); | |
835 | } | |
836 | fprintf_filtered (file, "\n"); | |
837 | } | |
838 | } | |
839 | ||
840 | /* Note: The IMAP/DMAP registers don't participate in function | |
841 | calls. Don't bother trying to unwind them. */ | |
842 | ||
6789195b | 843 | { |
5f601589 AC |
844 | int a; |
845 | for (a = 0; a < NR_IMAP_REGS; a++) | |
846 | { | |
847 | if (a > 0) | |
848 | fprintf_filtered (file, " "); | |
849 | fprintf_filtered (file, "IMAP%d %04lx", a, d10v_imap_register (a)); | |
850 | } | |
f75493ed | 851 | if (nr_dmap_regs (gdbarch) == 1) |
5f601589 AC |
852 | /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ |
853 | fprintf_filtered (file, " DMAP %04lx\n", d10v_dmap_register (2)); | |
854 | else | |
855 | { | |
f75493ed | 856 | for (a = 0; a < nr_dmap_regs (gdbarch); a++) |
5f601589 AC |
857 | { |
858 | fprintf_filtered (file, " DMAP%d %04lx", a, d10v_dmap_register (a)); | |
859 | } | |
860 | fprintf_filtered (file, "\n"); | |
861 | } | |
862 | } | |
863 | ||
864 | { | |
865 | char *num = alloca (max_register_size (gdbarch)); | |
866 | int a; | |
867 | fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); | |
f75493ed | 868 | for (a = a0_regnum (gdbarch); a < a0_regnum (gdbarch) + NR_A_REGS; a++) |
6789195b AC |
869 | { |
870 | int i; | |
5f601589 | 871 | fprintf_filtered (file, " "); |
f75493ed AC |
872 | frame_read_register (frame, a, num); |
873 | for (i = 0; i < register_size (current_gdbarch, a); i++) | |
6789195b | 874 | { |
5f601589 | 875 | fprintf_filtered (file, "%02x", (num[i] & 0xff)); |
6789195b AC |
876 | } |
877 | } | |
878 | } | |
5f601589 AC |
879 | fprintf_filtered (file, "\n"); |
880 | } | |
881 | ||
882 | static void | |
883 | show_regs (char *args, int from_tty) | |
884 | { | |
885 | d10v_print_registers_info (current_gdbarch, gdb_stdout, | |
886 | get_current_frame (), -1, 1); | |
c906108c SS |
887 | } |
888 | ||
f5e1cf12 | 889 | static CORE_ADDR |
39f77062 | 890 | d10v_read_pc (ptid_t ptid) |
c906108c | 891 | { |
39f77062 | 892 | ptid_t save_ptid; |
c906108c SS |
893 | CORE_ADDR pc; |
894 | CORE_ADDR retval; | |
895 | ||
39f77062 KB |
896 | save_ptid = inferior_ptid; |
897 | inferior_ptid = ptid; | |
c906108c | 898 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 899 | inferior_ptid = save_ptid; |
7b570125 | 900 | retval = d10v_make_iaddr (pc); |
c906108c SS |
901 | return retval; |
902 | } | |
903 | ||
f5e1cf12 | 904 | static void |
39f77062 | 905 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 906 | { |
39f77062 | 907 | ptid_t save_ptid; |
c906108c | 908 | |
39f77062 KB |
909 | save_ptid = inferior_ptid; |
910 | inferior_ptid = ptid; | |
7b570125 | 911 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 912 | inferior_ptid = save_ptid; |
c906108c SS |
913 | } |
914 | ||
f5e1cf12 | 915 | static CORE_ADDR |
fba45db2 | 916 | d10v_read_sp (void) |
c906108c | 917 | { |
f75493ed | 918 | return (d10v_make_daddr (read_register (D10V_SP_REGNUM))); |
c906108c SS |
919 | } |
920 | ||
f5e1cf12 | 921 | static CORE_ADDR |
fba45db2 | 922 | d10v_read_fp (void) |
c906108c | 923 | { |
6c2b5168 | 924 | return (d10v_make_daddr (read_register (D10V_FP_REGNUM))); |
c906108c SS |
925 | } |
926 | ||
7a292a7a SS |
927 | /* When arguments must be pushed onto the stack, they go on in reverse |
928 | order. The below implements a FILO (stack) to do this. */ | |
929 | ||
930 | struct stack_item | |
931 | { | |
932 | int len; | |
933 | struct stack_item *prev; | |
934 | void *data; | |
935 | }; | |
936 | ||
a14ed312 KB |
937 | static struct stack_item *push_stack_item (struct stack_item *prev, |
938 | void *contents, int len); | |
7a292a7a | 939 | static struct stack_item * |
fba45db2 | 940 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
941 | { |
942 | struct stack_item *si; | |
943 | si = xmalloc (sizeof (struct stack_item)); | |
944 | si->data = xmalloc (len); | |
945 | si->len = len; | |
946 | si->prev = prev; | |
947 | memcpy (si->data, contents, len); | |
948 | return si; | |
949 | } | |
950 | ||
a14ed312 | 951 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 952 | static struct stack_item * |
fba45db2 | 953 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
954 | { |
955 | struct stack_item *dead = si; | |
956 | si = si->prev; | |
b8c9b27d KB |
957 | xfree (dead->data); |
958 | xfree (dead); | |
7a292a7a SS |
959 | return si; |
960 | } | |
961 | ||
962 | ||
f5e1cf12 | 963 | static CORE_ADDR |
5873a88d AC |
964 | d10v_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache, |
965 | CORE_ADDR dummy_addr, int nargs, struct value **args, | |
966 | CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
967 | { |
968 | int i; | |
969 | int regnum = ARG1_REGNUM; | |
7a292a7a | 970 | struct stack_item *si = NULL; |
7bd91a28 MS |
971 | long val; |
972 | ||
5873a88d AC |
973 | /* Set the return address. For the d10v, the return breakpoint is |
974 | always at DUMMY_ADDR. */ | |
975 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, | |
976 | d10v_convert_iaddr_to_raw (dummy_addr)); | |
977 | ||
4183d812 AC |
978 | /* If STRUCT_RETURN is true, then the struct return address (in |
979 | STRUCT_ADDR) will consume the first argument-passing register. | |
980 | Both adjust the register count and store that value. */ | |
7bd91a28 | 981 | if (struct_return) |
4183d812 | 982 | { |
5873a88d | 983 | regcache_cooked_write_unsigned (regcache, regnum, struct_addr); |
4183d812 AC |
984 | regnum++; |
985 | } | |
c5aa993b | 986 | |
c906108c SS |
987 | /* Fill in registers and arg lists */ |
988 | for (i = 0; i < nargs; i++) | |
989 | { | |
ea7c478f | 990 | struct value *arg = args[i]; |
c906108c SS |
991 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
992 | char *contents = VALUE_CONTENTS (arg); | |
993 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
994 | int aligned_regnum = (regnum + 1) & ~1; |
995 | ||
8b279e7a | 996 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
997 | if (len <= 2 && regnum <= ARGN_REGNUM) |
998 | /* fits in a single register, do not align */ | |
999 | { | |
1000 | val = extract_unsigned_integer (contents, len); | |
5873a88d | 1001 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
7bd91a28 MS |
1002 | } |
1003 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1004 | /* value fits in remaining registers, store keeping left | |
1005 | aligned */ | |
c906108c | 1006 | { |
7bd91a28 MS |
1007 | int b; |
1008 | regnum = aligned_regnum; | |
1009 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1010 | { |
7bd91a28 | 1011 | val = extract_unsigned_integer (&contents[b], 2); |
5873a88d | 1012 | regcache_cooked_write_unsigned (regcache, regnum++, val); |
c906108c | 1013 | } |
7bd91a28 | 1014 | if (b < len) |
c906108c | 1015 | { |
7bd91a28 | 1016 | val = extract_unsigned_integer (&contents[b], 1); |
5873a88d | 1017 | regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); |
c906108c SS |
1018 | } |
1019 | } | |
7bd91a28 MS |
1020 | else |
1021 | { | |
1022 | /* arg will go onto stack */ | |
1023 | regnum = ARGN_REGNUM + 1; | |
1024 | si = push_stack_item (si, contents, len); | |
1025 | } | |
c906108c | 1026 | } |
7a292a7a SS |
1027 | |
1028 | while (si) | |
1029 | { | |
1030 | sp = (sp - si->len) & ~1; | |
1031 | write_memory (sp, si->data, si->len); | |
1032 | si = pop_stack_item (si); | |
1033 | } | |
c5aa993b | 1034 | |
5873a88d | 1035 | /* Finally, update the SP register. */ |
f75493ed | 1036 | regcache_cooked_write_unsigned (regcache, D10V_SP_REGNUM, |
5873a88d AC |
1037 | d10v_convert_daddr_to_raw (sp)); |
1038 | ||
c906108c SS |
1039 | return sp; |
1040 | } | |
1041 | ||
1042 | ||
1043 | /* Given a return value in `regbuf' with a type `valtype', | |
1044 | extract and copy its value into `valbuf'. */ | |
1045 | ||
f5e1cf12 | 1046 | static void |
fa1fd571 AC |
1047 | d10v_extract_return_value (struct type *type, struct regcache *regcache, |
1048 | void *valbuf) | |
c906108c SS |
1049 | { |
1050 | int len; | |
fa1fd571 | 1051 | if (TYPE_LENGTH (type) == 1) |
c906108c | 1052 | { |
fa1fd571 AC |
1053 | ULONGEST c; |
1054 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); | |
3d79a47c MS |
1055 | store_unsigned_integer (valbuf, 1, c); |
1056 | } | |
3d79a47c MS |
1057 | else |
1058 | { | |
1059 | /* For return values of odd size, the first byte is in the | |
1060 | least significant part of the first register. The | |
fa1fd571 AC |
1061 | remaining bytes in remaining registers. Interestingly, when |
1062 | such values are passed in, the last byte is in the most | |
1063 | significant byte of that same register - wierd. */ | |
1064 | int reg = RET1_REGNUM; | |
1065 | int off = 0; | |
1066 | if (TYPE_LENGTH (type) & 1) | |
1067 | { | |
1068 | regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, | |
1069 | (bfd_byte *)valbuf + off); | |
1070 | off++; | |
1071 | reg++; | |
1072 | } | |
1073 | /* Transfer the remaining registers. */ | |
1074 | for (; off < TYPE_LENGTH (type); reg++, off += 2) | |
1075 | { | |
1076 | regcache_cooked_read (regcache, RET1_REGNUM + reg, | |
1077 | (bfd_byte *) valbuf + off); | |
1078 | } | |
c906108c SS |
1079 | } |
1080 | } | |
1081 | ||
c2c6d25f JM |
1082 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1083 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1084 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1085 | (segmentation fault). Since the simulator knows all about how the | |
1086 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1087 | |
4ce44c66 | 1088 | static void |
c2c6d25f JM |
1089 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1090 | CORE_ADDR *targ_addr, int *targ_len) | |
1091 | { | |
4ce44c66 JM |
1092 | long out_addr; |
1093 | long out_len; | |
1094 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1095 | &out_addr, | |
1096 | d10v_dmap_register, | |
1097 | d10v_imap_register); | |
1098 | *targ_addr = out_addr; | |
1099 | *targ_len = out_len; | |
c2c6d25f JM |
1100 | } |
1101 | ||
4ce44c66 | 1102 | |
c906108c SS |
1103 | /* The following code implements access to, and display of, the D10V's |
1104 | instruction trace buffer. The buffer consists of 64K or more | |
1105 | 4-byte words of data, of which each words includes an 8-bit count, | |
1106 | an 8-bit segment number, and a 16-bit instruction address. | |
1107 | ||
1108 | In theory, the trace buffer is continuously capturing instruction | |
1109 | data that the CPU presents on its "debug bus", but in practice, the | |
1110 | ROMified GDB stub only enables tracing when it continues or steps | |
1111 | the program, and stops tracing when the program stops; so it | |
1112 | actually works for GDB to read the buffer counter out of memory and | |
1113 | then read each trace word. The counter records where the tracing | |
1114 | stops, but there is no record of where it started, so we remember | |
1115 | the PC when we resumed and then search backwards in the trace | |
1116 | buffer for a word that includes that address. This is not perfect, | |
1117 | because you will miss trace data if the resumption PC is the target | |
1118 | of a branch. (The value of the buffer counter is semi-random, any | |
1119 | trace data from a previous program stop is gone.) */ | |
1120 | ||
1121 | /* The address of the last word recorded in the trace buffer. */ | |
1122 | ||
1123 | #define DBBC_ADDR (0xd80000) | |
1124 | ||
1125 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1126 | ||
1127 | #define TRACE_BUFFER_BASE (0xf40000) | |
1128 | ||
a14ed312 | 1129 | static void trace_command (char *, int); |
c906108c | 1130 | |
a14ed312 | 1131 | static void untrace_command (char *, int); |
c906108c | 1132 | |
a14ed312 | 1133 | static void trace_info (char *, int); |
c906108c | 1134 | |
a14ed312 | 1135 | static void tdisassemble_command (char *, int); |
c906108c | 1136 | |
a14ed312 | 1137 | static void display_trace (int, int); |
c906108c SS |
1138 | |
1139 | /* True when instruction traces are being collected. */ | |
1140 | ||
1141 | static int tracing; | |
1142 | ||
1143 | /* Remembered PC. */ | |
1144 | ||
1145 | static CORE_ADDR last_pc; | |
1146 | ||
1147 | /* True when trace output should be displayed whenever program stops. */ | |
1148 | ||
1149 | static int trace_display; | |
1150 | ||
1151 | /* True when trace listing should include source lines. */ | |
1152 | ||
1153 | static int default_trace_show_source = 1; | |
1154 | ||
c5aa993b JM |
1155 | struct trace_buffer |
1156 | { | |
1157 | int size; | |
1158 | short *counts; | |
1159 | CORE_ADDR *addrs; | |
1160 | } | |
1161 | trace_data; | |
c906108c SS |
1162 | |
1163 | static void | |
fba45db2 | 1164 | trace_command (char *args, int from_tty) |
c906108c SS |
1165 | { |
1166 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1167 | trace_data.size = 0; | |
1168 | if (trace_data.counts == NULL) | |
f75493ed | 1169 | trace_data.counts = XCALLOC (65536, short); |
c906108c | 1170 | if (trace_data.addrs == NULL) |
f75493ed | 1171 | trace_data.addrs = XCALLOC (65536, CORE_ADDR); |
c906108c SS |
1172 | |
1173 | tracing = 1; | |
1174 | ||
1175 | printf_filtered ("Tracing is now on.\n"); | |
1176 | } | |
1177 | ||
1178 | static void | |
fba45db2 | 1179 | untrace_command (char *args, int from_tty) |
c906108c SS |
1180 | { |
1181 | tracing = 0; | |
1182 | ||
1183 | printf_filtered ("Tracing is now off.\n"); | |
1184 | } | |
1185 | ||
1186 | static void | |
fba45db2 | 1187 | trace_info (char *args, int from_tty) |
c906108c SS |
1188 | { |
1189 | int i; | |
1190 | ||
1191 | if (trace_data.size) | |
1192 | { | |
1193 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1194 | ||
1195 | for (i = 0; i < trace_data.size; ++i) | |
1196 | { | |
d4f3574e SS |
1197 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1198 | i, | |
1199 | trace_data.counts[i], | |
c906108c | 1200 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1201 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1202 | } |
1203 | } | |
1204 | else | |
1205 | printf_filtered ("No entries in trace buffer.\n"); | |
1206 | ||
1207 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1208 | } | |
1209 | ||
1210 | /* Print the instruction at address MEMADDR in debugged memory, | |
1211 | on STREAM. Returns length of the instruction, in bytes. */ | |
1212 | ||
1213 | static int | |
fba45db2 | 1214 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c | 1215 | { |
d7449b42 | 1216 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1217 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1218 | else | |
1219 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1220 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1221 | } |
1222 | ||
392a587b | 1223 | static void |
fba45db2 | 1224 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1225 | { |
1226 | if (!tracing) | |
1227 | return; | |
1228 | ||
1229 | last_pc = read_register (PC_REGNUM); | |
1230 | } | |
1231 | ||
1232 | /* Collect trace data from the target board and format it into a form | |
1233 | more useful for display. */ | |
1234 | ||
392a587b | 1235 | static void |
fba45db2 | 1236 | d10v_eva_get_trace_data (void) |
c906108c SS |
1237 | { |
1238 | int count, i, j, oldsize; | |
1239 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1240 | unsigned int last_trace, trace_word, next_word; | |
1241 | unsigned int *tmpspace; | |
1242 | ||
1243 | if (!tracing) | |
1244 | return; | |
1245 | ||
c5aa993b | 1246 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1247 | |
1248 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1249 | ||
1250 | /* Collect buffer contents from the target, stopping when we reach | |
1251 | the word recorded when execution resumed. */ | |
1252 | ||
1253 | count = 0; | |
1254 | while (last_trace > 0) | |
1255 | { | |
1256 | QUIT; | |
1257 | trace_word = | |
1258 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1259 | trace_addr = trace_word & 0xffff; | |
1260 | last_trace -= 4; | |
1261 | /* Ignore an apparently nonsensical entry. */ | |
1262 | if (trace_addr == 0xffd5) | |
1263 | continue; | |
1264 | tmpspace[count++] = trace_word; | |
1265 | if (trace_addr == last_pc) | |
1266 | break; | |
1267 | if (count > 65535) | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1272 | include the last instruction executed and transforming the address | |
1273 | into something that GDB likes. */ | |
1274 | ||
1275 | for (i = 0; i < count; ++i) | |
1276 | { | |
1277 | trace_word = tmpspace[i]; | |
1278 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1279 | trace_addr = trace_word & 0xffff; | |
1280 | next_cnt = (next_word >> 24) & 0xff; | |
1281 | j = trace_data.size + count - i - 1; | |
1282 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1283 | trace_data.counts[j] = next_cnt + 1; | |
1284 | } | |
1285 | ||
1286 | oldsize = trace_data.size; | |
1287 | trace_data.size += count; | |
1288 | ||
b8c9b27d | 1289 | xfree (tmpspace); |
c906108c SS |
1290 | |
1291 | if (trace_display) | |
1292 | display_trace (oldsize, trace_data.size); | |
1293 | } | |
1294 | ||
1295 | static void | |
fba45db2 | 1296 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1297 | { |
1298 | int i, count; | |
1299 | CORE_ADDR low, high; | |
c906108c SS |
1300 | |
1301 | if (!arg) | |
1302 | { | |
1303 | low = 0; | |
1304 | high = trace_data.size; | |
1305 | } | |
c906108c | 1306 | else |
e8933a55 AC |
1307 | { |
1308 | char *space_index = strchr (arg, ' '); | |
1309 | if (space_index == NULL) | |
1310 | { | |
1311 | low = parse_and_eval_address (arg); | |
1312 | high = low + 5; | |
1313 | } | |
1314 | else | |
1315 | { | |
1316 | /* Two arguments. */ | |
1317 | *space_index = '\0'; | |
1318 | low = parse_and_eval_address (arg); | |
1319 | high = parse_and_eval_address (space_index + 1); | |
1320 | if (high < low) | |
1321 | high = low; | |
1322 | } | |
c906108c SS |
1323 | } |
1324 | ||
d4f3574e | 1325 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1326 | |
1327 | display_trace (low, high); | |
1328 | ||
1329 | printf_filtered ("End of trace dump.\n"); | |
1330 | gdb_flush (gdb_stdout); | |
1331 | } | |
1332 | ||
1333 | static void | |
fba45db2 | 1334 | display_trace (int low, int high) |
c906108c SS |
1335 | { |
1336 | int i, count, trace_show_source, first, suppress; | |
1337 | CORE_ADDR next_address; | |
1338 | ||
1339 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1340 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1341 | { |
1342 | trace_show_source = 0; | |
1343 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1344 | printf_filtered ("Trace will not display any source.\n"); | |
1345 | } | |
1346 | ||
1347 | first = 1; | |
1348 | suppress = 0; | |
1349 | for (i = low; i < high; ++i) | |
1350 | { | |
1351 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1352 | count = trace_data.counts[i]; |
c906108c SS |
1353 | while (count-- > 0) |
1354 | { | |
1355 | QUIT; | |
1356 | if (trace_show_source) | |
1357 | { | |
1358 | struct symtab_and_line sal, sal_prev; | |
1359 | ||
1360 | sal_prev = find_pc_line (next_address - 4, 0); | |
1361 | sal = find_pc_line (next_address, 0); | |
1362 | ||
1363 | if (sal.symtab) | |
1364 | { | |
1365 | if (first || sal.line != sal_prev.line) | |
1366 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1367 | suppress = 0; | |
1368 | } | |
1369 | else | |
1370 | { | |
1371 | if (!suppress) | |
1372 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1373 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1374 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1375 | suppress = 1; |
1376 | } | |
1377 | } | |
1378 | first = 0; | |
1379 | print_address (next_address, gdb_stdout); | |
1380 | printf_filtered (":"); | |
1381 | printf_filtered ("\t"); | |
1382 | wrap_here (" "); | |
1383 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1384 | printf_filtered ("\n"); | |
1385 | gdb_flush (gdb_stdout); | |
1386 | } | |
1387 | } | |
1388 | } | |
1389 | ||
7f6104a9 | 1390 | static CORE_ADDR |
12cc2063 | 1391 | d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
7f6104a9 | 1392 | { |
12cc2063 AC |
1393 | ULONGEST pc; |
1394 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1395 | return d10v_make_iaddr (pc); | |
7f6104a9 AC |
1396 | } |
1397 | ||
1398 | /* Given a GDB frame, determine the address of the calling function's | |
1399 | frame. This will be used to create a new GDB frame struct. */ | |
1400 | ||
1401 | static void | |
6dc42492 AC |
1402 | d10v_frame_this_id (struct frame_info *next_frame, |
1403 | void **this_prologue_cache, | |
1404 | struct frame_id *this_id) | |
7f6104a9 | 1405 | { |
6dc42492 AC |
1406 | struct d10v_unwind_cache *info |
1407 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
1408 | CORE_ADDR base; | |
81f8a206 AC |
1409 | CORE_ADDR func; |
1410 | struct frame_id id; | |
7f6104a9 | 1411 | |
81f8a206 AC |
1412 | /* The FUNC is easy. */ |
1413 | func = frame_func_unwind (next_frame); | |
7f6104a9 | 1414 | |
6dc42492 AC |
1415 | /* This is meant to halt the backtrace at "_start". Make sure we |
1416 | don't halt it at a generic dummy frame. */ | |
81f8a206 | 1417 | if (func <= IMEM_START || inside_entry_file (func)) |
6dc42492 | 1418 | return; |
7f6104a9 | 1419 | |
6dc42492 AC |
1420 | /* Hopefully the prologue analysis either correctly determined the |
1421 | frame's base (which is the SP from the previous frame), or set | |
1422 | that base to "NULL". */ | |
270cb5d6 | 1423 | base = info->prev_sp; |
6dc42492 AC |
1424 | if (base == STACK_START || base == 0) |
1425 | return; | |
7f6104a9 | 1426 | |
81f8a206 AC |
1427 | id = frame_id_build (base, func); |
1428 | ||
6dc42492 AC |
1429 | /* Check that we're not going round in circles with the same frame |
1430 | ID (but avoid applying the test to sentinel frames which do go | |
1431 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1432 | compare the frame's PC value. */ | |
1433 | if (frame_relative_level (next_frame) >= 0 | |
1434 | && get_frame_type (next_frame) != DUMMY_FRAME | |
81f8a206 | 1435 | && frame_id_eq (get_frame_id (next_frame), id)) |
7f6104a9 AC |
1436 | return; |
1437 | ||
81f8a206 | 1438 | (*this_id) = id; |
7f6104a9 AC |
1439 | } |
1440 | ||
1441 | static void | |
6dc42492 AC |
1442 | saved_regs_unwinder (struct frame_info *next_frame, |
1443 | CORE_ADDR *this_saved_regs, | |
7f6104a9 AC |
1444 | int regnum, int *optimizedp, |
1445 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1446 | int *realnump, void *bufferp) | |
1447 | { | |
6dc42492 | 1448 | if (this_saved_regs[regnum] != 0) |
7f6104a9 | 1449 | { |
f75493ed | 1450 | if (regnum == D10V_SP_REGNUM) |
7f6104a9 AC |
1451 | { |
1452 | /* SP register treated specially. */ | |
1453 | *optimizedp = 0; | |
1454 | *lvalp = not_lval; | |
1455 | *addrp = 0; | |
1456 | *realnump = -1; | |
1457 | if (bufferp != NULL) | |
f75493ed AC |
1458 | store_unsigned_integer (bufferp, |
1459 | register_size (current_gdbarch, regnum), | |
1460 | this_saved_regs[regnum]); | |
7f6104a9 AC |
1461 | } |
1462 | else | |
1463 | { | |
1464 | /* Any other register is saved in memory, fetch it but cache | |
1465 | a local copy of its value. */ | |
1466 | *optimizedp = 0; | |
1467 | *lvalp = lval_memory; | |
6dc42492 | 1468 | *addrp = this_saved_regs[regnum]; |
7f6104a9 AC |
1469 | *realnump = -1; |
1470 | if (bufferp != NULL) | |
1471 | { | |
1472 | /* Read the value in from memory. */ | |
6dc42492 | 1473 | read_memory (this_saved_regs[regnum], bufferp, |
08a617da | 1474 | register_size (current_gdbarch, regnum)); |
7f6104a9 AC |
1475 | } |
1476 | } | |
1477 | return; | |
1478 | } | |
1479 | ||
1480 | /* No luck, assume this and the next frame have the same register | |
1481 | value. If a value is needed, pass the request on down the chain; | |
1482 | otherwise just return an indication that the value is in the same | |
1483 | register as the next frame. */ | |
6dc42492 AC |
1484 | frame_register_unwind (next_frame, regnum, optimizedp, lvalp, addrp, |
1485 | realnump, bufferp); | |
7f6104a9 AC |
1486 | } |
1487 | ||
1488 | ||
1489 | static void | |
6dc42492 AC |
1490 | d10v_frame_prev_register (struct frame_info *next_frame, |
1491 | void **this_prologue_cache, | |
1492 | int regnum, int *optimizedp, | |
1493 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1494 | int *realnump, void *bufferp) | |
7f6104a9 | 1495 | { |
6dc42492 AC |
1496 | struct d10v_unwind_cache *info |
1497 | = d10v_frame_unwind_cache (next_frame, this_prologue_cache); | |
ef840a37 AC |
1498 | if (regnum == PC_REGNUM) |
1499 | { | |
1500 | /* The call instruction saves the caller's PC in LR. The | |
1501 | function prologue of the callee may then save the LR on the | |
1502 | stack. Find that possibly saved LR value and return it. */ | |
6dc42492 | 1503 | saved_regs_unwinder (next_frame, info->saved_regs, LR_REGNUM, optimizedp, |
ef840a37 AC |
1504 | lvalp, addrp, realnump, bufferp); |
1505 | } | |
1506 | else | |
1507 | { | |
6dc42492 | 1508 | saved_regs_unwinder (next_frame, info->saved_regs, regnum, optimizedp, |
ef840a37 AC |
1509 | lvalp, addrp, realnump, bufferp); |
1510 | } | |
7f6104a9 AC |
1511 | } |
1512 | ||
270cb5d6 | 1513 | static const struct frame_unwind d10v_frame_unwind = { |
7df05f2b | 1514 | NORMAL_FRAME, |
6dc42492 AC |
1515 | d10v_frame_this_id, |
1516 | d10v_frame_prev_register | |
7f6104a9 AC |
1517 | }; |
1518 | ||
1519 | const struct frame_unwind * | |
1520 | d10v_frame_p (CORE_ADDR pc) | |
1521 | { | |
1522 | return &d10v_frame_unwind; | |
1523 | } | |
1524 | ||
270cb5d6 AC |
1525 | static CORE_ADDR |
1526 | d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1527 | { | |
1528 | struct d10v_unwind_cache *info | |
1529 | = d10v_frame_unwind_cache (next_frame, this_cache); | |
1530 | return info->base; | |
1531 | } | |
1532 | ||
1533 | static const struct frame_base d10v_frame_base = { | |
1534 | &d10v_frame_unwind, | |
1535 | d10v_frame_base_address, | |
1536 | d10v_frame_base_address, | |
1537 | d10v_frame_base_address | |
1538 | }; | |
1539 | ||
6314f104 AC |
1540 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1541 | dummy frame. The frame ID's base needs to match the TOS value | |
1542 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1543 | breakpoint. */ | |
1544 | ||
1545 | static struct frame_id | |
1546 | d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1547 | { | |
1548 | ULONGEST base; | |
f75493ed | 1549 | frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &base); |
11889732 | 1550 | return frame_id_build (d10v_make_daddr (base), frame_pc_unwind (next_frame)); |
6314f104 AC |
1551 | } |
1552 | ||
0f71a2f6 | 1553 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1554 | |
0f71a2f6 | 1555 | static struct gdbarch * |
fba45db2 | 1556 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1557 | { |
0f71a2f6 | 1558 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1559 | int d10v_num_regs; |
1560 | struct gdbarch_tdep *tdep; | |
1561 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1562 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1563 | |
4ce44c66 JM |
1564 | /* Find a candidate among the list of pre-declared architectures. */ |
1565 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1566 | if (arches != NULL) |
1567 | return arches->gdbarch; | |
4ce44c66 JM |
1568 | |
1569 | /* None found, create a new architecture from the information | |
1570 | provided. */ | |
1571 | tdep = XMALLOC (struct gdbarch_tdep); | |
1572 | gdbarch = gdbarch_alloc (&info, tdep); | |
1573 | ||
1574 | switch (info.bfd_arch_info->mach) | |
1575 | { | |
1576 | case bfd_mach_d10v_ts2: | |
1577 | d10v_num_regs = 37; | |
1578 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1579 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1580 | tdep->a0_regnum = TS2_A0_REGNUM; |
1581 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1582 | tdep->dmap_register = d10v_ts2_dmap_register; |
1583 | tdep->imap_register = d10v_ts2_imap_register; | |
1584 | break; | |
1585 | default: | |
1586 | case bfd_mach_d10v_ts3: | |
1587 | d10v_num_regs = 42; | |
1588 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1589 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1590 | tdep->a0_regnum = TS3_A0_REGNUM; |
1591 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1592 | tdep->dmap_register = d10v_ts3_dmap_register; |
1593 | tdep->imap_register = d10v_ts3_imap_register; | |
1594 | break; | |
1595 | } | |
0f71a2f6 JM |
1596 | |
1597 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1598 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1599 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 | 1600 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
0f71a2f6 JM |
1601 | |
1602 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
f75493ed | 1603 | set_gdbarch_sp_regnum (gdbarch, D10V_SP_REGNUM); |
0f71a2f6 JM |
1604 | set_gdbarch_pc_regnum (gdbarch, 18); |
1605 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1606 | set_gdbarch_register_size (gdbarch, 2); | |
1607 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
8b279e7a | 1608 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
35cac7cf | 1609 | set_gdbarch_register_type (gdbarch, d10v_register_type); |
0f71a2f6 | 1610 | |
75af7f68 JB |
1611 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1612 | set_gdbarch_addr_bit (gdbarch, 32); | |
1613 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1614 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1615 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1616 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1617 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1618 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1619 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1620 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1621 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1622 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1623 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1624 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1625 | switch (info.byte_order) |
1626 | { | |
d7449b42 | 1627 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1628 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1629 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1630 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1631 | break; | |
778eb05e | 1632 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1633 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1634 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1635 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1636 | break; | |
1637 | default: | |
8e65ff28 AC |
1638 | internal_error (__FILE__, __LINE__, |
1639 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1640 | } |
0f71a2f6 | 1641 | |
fa1fd571 | 1642 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
5873a88d | 1643 | set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); |
fa1fd571 AC |
1644 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); |
1645 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
0f71a2f6 JM |
1646 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1647 | ||
0f71a2f6 JM |
1648 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); |
1649 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1650 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1651 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1652 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1653 | ||
1654 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1655 | ||
1656 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1657 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
f4ded5b1 | 1658 | |
0f71a2f6 | 1659 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
23964bcd | 1660 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1661 | |
7c7651b2 AC |
1662 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
1663 | ||
5f601589 AC |
1664 | set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); |
1665 | ||
7f6104a9 | 1666 | frame_unwind_append_predicate (gdbarch, d10v_frame_p); |
270cb5d6 | 1667 | frame_base_set_default (gdbarch, &d10v_frame_base); |
7f6104a9 | 1668 | |
6314f104 AC |
1669 | /* Methods for saving / extracting a dummy frame's ID. */ |
1670 | set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); | |
1671 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
1672 | ||
12cc2063 AC |
1673 | /* Return the unwound PC value. */ |
1674 | set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); | |
1675 | ||
0f71a2f6 JM |
1676 | return gdbarch; |
1677 | } | |
1678 | ||
c906108c | 1679 | void |
fba45db2 | 1680 | _initialize_d10v_tdep (void) |
c906108c | 1681 | { |
0f71a2f6 JM |
1682 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1683 | ||
c906108c SS |
1684 | tm_print_insn = print_insn_d10v; |
1685 | ||
1686 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1687 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1688 | ||
5f601589 AC |
1689 | deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"), |
1690 | "info registers"); | |
c906108c | 1691 | |
cff3e48b | 1692 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1693 | "Enable tracing of instruction execution."); |
1694 | ||
cff3e48b | 1695 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1696 | "Disable tracing of instruction execution."); |
1697 | ||
cff3e48b | 1698 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1699 | "Disassemble the trace buffer.\n\ |
1700 | Two optional arguments specify a range of trace buffer entries\n\ | |
1701 | as reported by info trace (NOT addresses!)."); | |
1702 | ||
cff3e48b | 1703 | add_info ("itrace", trace_info, |
c906108c SS |
1704 | "Display info about the trace data buffer."); |
1705 | ||
f75493ed AC |
1706 | add_setshow_boolean_cmd ("itracedisplay", no_class, &trace_display, |
1707 | "Set automatic display of trace.\n", | |
1708 | "Show automatic display of trace.\n", | |
1709 | NULL, NULL, &setlist, &showlist); | |
1710 | add_setshow_boolean_cmd ("itracesource", no_class, | |
1711 | &default_trace_show_source, | |
1712 | "Set display of source code with trace.\n", | |
1713 | "Show display of source code with trace.\n", | |
1714 | NULL, NULL, &setlist, &showlist); | |
c5aa993b | 1715 | } |